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--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
--Date : Thu Dec 5 20:46:46 2019
--Host : balintmaci-surface running 64-bit major release (build 9200)
--Command : generate_target pwm_model.bd
--Design : pwm_model
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pwm_model is
port (
pwm : out STD_LOGIC;
sys_clk : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of pwm_model : entity is "pwm_model,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=pwm_model,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=4,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of pwm_model : entity is "pwm_model.hwdef";
end pwm_model;
architecture STRUCTURE of pwm_model is
component pwm_model_comparator_10_0_0 is
port (
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
b : in STD_LOGIC_VECTOR ( 9 downto 0 );
c : out STD_LOGIC
);
end component pwm_model_comparator_10_0_0;
component pwm_model_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component pwm_model_xlconstant_0_0;
component pwm_model_counter_10_0_0 is
port (
sys_clk : in STD_LOGIC;
count : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component pwm_model_counter_10_0_0;
component pwm_model_inverter_0_0 is
port (
a : in STD_LOGIC;
b : out STD_LOGIC
);
end component pwm_model_inverter_0_0;
signal comparator_10_c : STD_LOGIC;
signal counter_10_0_count : STD_LOGIC_VECTOR ( 9 downto 0 );
signal inverter_0_output : STD_LOGIC;
signal sys_clk_0_1 : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.SYS_CLK, CLK_DOMAIN pwm_model_sys_clk, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000";
begin
pwm <= inverter_0_output;
sys_clk_0_1 <= sys_clk;
comparator_10: component pwm_model_comparator_10_0_0
port map (
a(9 downto 0) => counter_10_0_count(9 downto 0),
b(9 downto 0) => xlconstant_0_dout(9 downto 0),
c => comparator_10_c
);
counter_10: component pwm_model_counter_10_0_0
port map (
count(9 downto 0) => counter_10_0_count(9 downto 0),
sys_clk => sys_clk_0_1
);
inverter_0: component pwm_model_inverter_0_0
port map (
a => comparator_10_c,
b => inverter_0_output
);
xlconstant_0: component pwm_model_xlconstant_0_0
port map (
dout(9 downto 0) => xlconstant_0_dout(9 downto 0)
);
end STRUCTURE;
|
-- Reciever
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: <NAME>
-- email: <EMAIL>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reciever is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
rx: in std_logic;
baud16_clk_en: in std_logic;
rx_data: out unsigned(7 downto 0);
rx_done: out std_logic
);
end entity reciever;
architecture reciever_arch of reciever is
type rx_state_type is (idle, start_sync, wait_for_sync, sync, wait_b0, get_b0, wait_b1, get_b1,wait_b2, get_b2,
wait_b3, get_b3,wait_b4, get_b4,wait_b5, get_b5,wait_b6, get_b6,wait_b7, get_b7,
wait_stopbit, store_data_0, store_data_1);
signal state: rx_state_type; -- state for RX FSM
signal sipo_val: unsigned(7 downto 0);
signal rx_rec_com, res_counter, shift_sipo_reg: std_logic; -- control signals for RX FSM
signal baud_clk_en: std_logic; -- this is an baud clock
signal count: unsigned(3 downto 0); -- this is rx counter value
begin
sipo_reg:
process(res, clk, rx, shift_sipo_reg) is
variable sipo_var: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
sipo_var := (others => '0');
elsif shift_sipo_reg = '1' then
sipo_var(6 downto 0) := sipo_var(7 downto 1);
sipo_var(7) := rx;
end if;
end if;
sipo_val <= sipo_var;
end process;
rx_out_reg:
process(res, clk, rx_rec_com) is
variable out_reg: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if(res = '1') then
out_reg := (others => '0');
elsif rx_rec_com = '1' then
out_reg := sipo_val;
end if;
end if;
rx_data <= out_reg;
end process;
rxcounter:
process(clk, res) is
variable counter: unsigned(3 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := (others => '0');
elsif res_counter = '1' then
counter := (others => '0');
elsif baud16_clk_en = '1' then
counter := counter + 1;
end if;
end if;
count <= counter;
end process;
process(count, baud16_clk_en) is
begin
if count = x"F" then
baud_clk_en <= baud16_clk_en;
else
baud_clk_en <= '0';
end if;
end process;
process(clk, res, count, baud_clk_en, rx) is
begin
if rising_edge(clk) then
if res = '1' then
state <= idle;
else
case state is
when idle =>
if ((rx = '0') and (en = '1')) then
state <= start_sync;
else
state <= idle;
end if;
when start_sync => state <= wait_for_sync;
when wait_for_sync =>
if count = "0111" then
state <= sync;
else
state <= wait_for_sync;
end if;
when sync => state <= wait_b0;
when wait_b0 =>
if baud_clk_en = '1' then
state <= get_b0;
else
state <= wait_b0;
end if;
when get_b0 => state <= wait_b1;
when wait_b1 =>
if baud_clk_en = '1' then
state <= get_b1;
else
state <= wait_b1;
end if;
when get_b1 => state <= wait_b2;
when wait_b2 =>
if baud_clk_en = '1' then
state <= get_b2;
else
state <= wait_b2;
end if;
when get_b2 => state <= wait_b3;
when wait_b3 =>
if baud_clk_en = '1' then
state <= get_b3;
else
state <= wait_b3;
end if;
when get_b3 => state <= wait_b4;
when wait_b4 =>
if baud_clk_en = '1' then
state <= get_b4;
else
state <= wait_b4;
end if;
when get_b4 => state <= wait_b5;
when wait_b5 =>
if baud_clk_en = '1' then
state <= get_b5;
else
state <= wait_b5;
end if;
when get_b5 => state <= wait_b6;
when wait_b6 =>
if baud_clk_en = '1' then
state <= get_b6;
else
state <= wait_b6;
end if;
when get_b6 => state <= wait_b7;
when wait_b7 =>
if baud_clk_en = '1' then
state <= get_b7;
else
state <= wait_b7;
end if;
when get_b7 => state <= wait_stopbit;
when wait_stopbit =>
if baud_clk_en = '1' then
state <= store_data_0;
else
state <= wait_stopbit;
end if;
when store_data_0 => state <= store_data_1;
when store_data_1 => state <= idle;
end case;
end if;
end if;
end process;
process(state) is
begin
case state is
when idle => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when start_sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_for_sync => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_stopbit => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_0 => rx_rec_com <= '1'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '1';
end case;
end process;
end architecture reciever_arch;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:30:20 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
apply : in STD_LOGIC;
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
state : out STD_LOGIC_VECTOR ( 1 downto 0 );
transform : in STD_LOGIC;
transform_led : out STD_LOGIC;
trigger : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=27,numReposBlks=27,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end component system_debounce_0_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_vga_buffer_1_1 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_1_1;
component system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_overlay_0_0;
component system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_xlconstant_0_3 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_xlconstant_0_3;
component system_vga_transform_0_1 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_transform_0_1;
component system_rgb888_to_g8_1_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_1_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_c_addsub_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
S : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_c_addsub_0_0;
component system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_0_0;
component system_vga_hessian_1_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_1_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_vga_feature_transform_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
vsync : in STD_LOGIC;
x_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rot_m00 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : out STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : out STD_LOGIC_VECTOR ( 9 downto 0 );
state : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system_vga_feature_transform_0_0;
component system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_0_0;
component system_buffer_register_1_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_1_0;
component system_util_ds_buf_0_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_ds_buf_0_0;
component system_util_ds_buf_1_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_ds_buf_1_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal buffer_register_0_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffer_register_1_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal c_addsub_0_S : STD_LOGIC_VECTOR ( 9 downto 0 );
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_1_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal data_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal debounce_0_o : STD_LOGIC;
signal hsync_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pclk_1 : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_to_g8_0_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb888_to_g8_1_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal transform_1 : STD_LOGIC;
signal trigger_1 : STD_LOGIC;
signal twenty_u_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
signal util_ds_buf_0_BUFG_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_buffer_1_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_feature_transform_0_rot_m00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m01 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m10 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vga_feature_transform_0_t_x : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_feature_transform_0_t_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_hessian_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_hessian_1_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_overlay_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_12_5 : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_pll_0_clk_12_6 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_x_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_y_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vsync_1 : STD_LOGIC;
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
data_1(7 downto 0) <= data(7 downto 0);
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1 <= hsync;
pclk_1 <= pclk;
ready <= ov7670_controller_0_config_finished;
reset_1 <= reset;
sioc <= ov7670_controller_0_sioc;
state(1 downto 0) <= vga_feature_transform_0_state(1 downto 0);
transform_1 <= transform;
transform_led <= transform_1;
trigger_1 <= trigger;
vsync_1 <= vsync;
xclk <= clk_wiz_0_clk_out1;
buffer_register_0: component system_buffer_register_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
val_in(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_0_val_out(31 downto 0)
);
buffer_register_1: component system_buffer_register_1_0
port map (
clk => vga_pll_0_clk_12_5(0),
val_in(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_1_val_out(31 downto 0)
);
c_addsub_0: component system_c_addsub_0_0
port map (
A(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
B(9 downto 0) => twenty_u_dout(9 downto 0),
S(9 downto 0) => c_addsub_0_S(9 downto 0)
);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out1
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_1_clk_out1
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => pclk_1,
clk_out => clock_splitter_0_clk_out,
latch_edge => vsync_1
);
debounce_0: component system_debounce_0_0
port map (
clk => util_ds_buf_0_BUFG_O(0),
signal_in => reset_1,
signal_out => debounce_0_o
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => util_ds_buf_0_BUFG_O(0),
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => pclk_1,
data(7 downto 0) => data_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb888_to_g8_0: component system_rgb888_to_g8_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_0_data_r(23 downto 0)
);
rgb888_to_g8_1: component system_rgb888_to_g8_1_0
port map (
clk => vga_pll_0_clk_12_5(0),
g8(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
twenty_u: component system_xlconstant_0_3
port map (
dout(9 downto 0) => twenty_u_dout(9 downto 0)
);
util_ds_buf_0: component system_util_ds_buf_0_0
port map (
BUFG_I(0) => vga_pll_0_clk_25,
BUFG_O(0) => util_ds_buf_0_BUFG_O(0)
);
util_ds_buf_1: component system_util_ds_buf_1_0
port map (
BUFG_I(0) => vga_pll_0_clk_12_6,
BUFG_O(0) => vga_pll_0_clk_12_5(0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_5(0),
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_buffer_1: component system_vga_buffer_1_1
port map (
clk_r => vga_pll_0_clk_12_5(0),
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_1_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
x_addr_w(9 downto 0) => c_addsub_0_S(9 downto 0),
y_addr_r(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_feature_transform_0: component system_vga_feature_transform_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
clk_x2 => util_ds_buf_0_BUFG_O(0),
hessian_0(31 downto 0) => buffer_register_0_val_out(31 downto 0),
hessian_1(31 downto 0) => buffer_register_1_val_out(31 downto 0),
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
rst => ov7670_controller_0_config_finished,
state(1 downto 0) => vga_feature_transform_0_state(1 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
vsync => vsync_1,
x_addr_0(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_1(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr_0(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_1(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_hessian_0: component system_vga_hessian_0_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_hessian_1: component system_vga_hessian_1_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_overlay_0: component system_vga_overlay_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
rgb(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
rgb_0(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
rgb_1(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_6,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => hsync_1,
rst => ov7670_controller_0_config_finished,
start => vga_sync_ref_0_start,
vsync => vsync_1,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_transform_0: component system_vga_transform_0_1
port map (
clk => vga_pll_0_clk_12_5(0),
enable => transform_1,
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_out(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
clk_100 => clk_100_1,
clk_x2 => util_ds_buf_0_BUFG_O(0),
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
|
<gh_stars>0
-- fixed-point math operations
-- sources: ...
library ieee;
use ieee.std_logic_1164.all;
use IEEE.math_real.all;
package fixpt_math is
-- 1-cycle
component adder
generic (
WIDTH : integer
);
port (
op1 : std_logic_vector(WIDTH-1 downto 0);
op2 : std_logic_vector(WIDTH-1 downto 0);
result : std_logic_vector(WIDTH-1 downto 0)
);
end component;
end package fixpt_math;
|
<gh_stars>10-100
-- simlpe dual-port ram, based on vivado coding example
-- 1 cycle of latency for writes
-- 1 cycle of latency for reads
-- this makes a total of 2 clk cycles of latency (if the same clock is used for both ports)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity simple_dualport_ram_with_init is
Generic (
ADDRESS_WIDTH : positive := 15;
DATA_WIDTH : positive := 16;
DATA_FILE : string := "ram_init_file.txt"
);
Port (
-- Write port:
clk_write : in std_logic;
write_enable : in std_logic;
write_address : in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
write_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Read port:
clk_read : in std_logic;
read_enable : in std_logic;
read_address : in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
read_data : out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end simple_dualport_ram_with_init;
architecture Behavioral of simple_dualport_ram_with_init is
-- The libraries ieee.std_logic_unsigned and std.textio will need to be included
-- with this example
-- The following code will infer a Single port Block RAM and initialize it using a FILE
type RAM_TYPE is array(0 to 2**ADDRESS_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
impure function ram_init (ram_file_name : in string) return RAM_TYPE is
FILE ram_file : text is in ram_file_name;
variable line_name : line;
variable RAM_inst : RAM_TYPE;
variable bitvec : bit_vector(DATA_WIDTH-1 downto 0);
begin
for I in RAM_TYPE'range loop
readline (ram_file, line_name);
read (line_name, bitvec);
RAM_inst(I) := to_stdlogicvector(bitvec);
end loop;
return RAM_inst;
end function;
signal RAM : RAM_TYPE := ram_init(DATA_FILE);
signal read_data_internal : std_logic_vector (DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- write port, 1 cycle latency:
process (clk_write)
begin
if rising_edge(clk_write) then
if write_enable = '1' then
RAM(to_integer(unsigned(write_address))) <= write_data;
end if;
end if;
end process;
-- Read port, 1 cycle latency:
process (clk_read)
begin
if rising_edge(clk_read) then
if read_enable = '1' then
read_data_internal <= RAM(to_integer(unsigned(read_address)));
end if;
end if;
end process;
read_data <= read_data_internal;
end Behavioral;
|
<gh_stars>10-100
---------------------------------------------------------------------------------
--
-- Copyright 2017 - <NAME> Laboratory and University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ipbus.web.cern.ch/ipbus
--
---------------------------------------------------------------------------------
-- Top-level design for ipbus demo
--
-- This version is for KC705 eval board, using SFP ethernet interface
--
-- You must edit this file to set the IP and MAC addresses
--
-- <NAME>, 23/2/11
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.ipbus.all;
entity top is port(
sysclk_p : in std_logic;
sysclk_n : in std_logic;
leds : out std_logic_vector(3 downto 0); -- status LEDs
dip_sw : in std_logic_vector(3 downto 0); -- switches
gmii_gtx_clk : out std_logic;
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_rx_clk : in std_logic;
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
phy_rst : out std_logic
);
end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, clk_aux, rst_aux, nuke, soft_rst, phy_rst_e, userled : std_logic;
signal mac_addr : std_logic_vector(47 downto 0);
signal ip_addr : std_logic_vector(31 downto 0);
signal ipb_out : ipb_wbus;
signal ipb_in : ipb_rbus;
begin
-- Infrastructure
infra : entity work.kc705_gmii_infra
port map(
sysclk_p => sysclk_p,
sysclk_n => sysclk_n,
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
rst_125_o => phy_rst_e,
clk_aux_o => clk_aux,
rst_aux_o => rst_aux,
nuke => nuke,
soft_rst => soft_rst,
leds => leds(1 downto 0),
gmii_gtx_clk => gmii_gtx_clk,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rx_clk => gmii_rx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
mac_addr => mac_addr,
ip_addr => ip_addr,
rarp_select => '0',
ipb_in => ipb_in,
ipb_out => ipb_out
);
leds(3 downto 2) <= '0' & userled;
phy_rst <= not phy_rst_e;
mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
-- ipbus slaves live in the entity below, and can expose top-level ports
-- The ipbus fabric is instantiated within.
payload : entity work.payload
port map(
ipb_clk => clk_ipb,
ipb_rst => rst_ipb,
ipb_in => ipb_out,
ipb_out => ipb_in,
clk => clk_aux,
rst => rst_aux,
nuke => nuke,
soft_rst => soft_rst,
userled => userled
);
end rtl;
|
<reponame>crupest/what-can-a-programmer-do
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder_1 is
port (A, B, CI:in std_logic; S, CO: out std_logic);
end full_adder_1;
architecture behavior of full_adder_1 is
begin
S <= (A XOR B) XOR CI;
CO <= (A AND B) OR (B AND CI) OR (CI AND A);
end architecture;
|
<reponame>VanderSant/PCS3225_Sistemas-Digitais-II<filename>Ep5/ex.2/fulladder.vhdl
entity fulladder is
port (
a,b : in bit; -- adends
cin : in bit; -- carry-in
s : out bit; -- sum
cout : out bit -- carry-out
);
end entity fulladder;
architecture wakerly of fulladder is
begin
s <= (a xor b) xor cin;
cout <= (a and b) or (cin and a) or (cin and b);
end architecture wakerly;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- <NAME>, 260668818
-- <NAME>, 260661832
-- <NAME>,260687154
entity MEM_datapath is
generic(
RAM_SIZE : integer := 8192
);
port(
clk : in std_logic;
stall_in : in std_logic;
inst_id : in integer;
result : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
wb_reg_in : in std_logic_vector(4 downto 0);
mem_read : in std_logic;
mem_addr : in integer;
counter_jal : in integer;
lw_hazard : in std_logic;
EX_forward : in std_logic;
MEM_forward_data : out std_logic_vector(31 downto 0);
lw_forward : out std_logic :='0';
wb_reg_out : out std_logic_vector(4 downto 0);
wb_data_out : out std_logic_vector(31 downto 0);
read_data : out std_logic_vector(31 downto 0);
MEM_forward : out std_logic:= '0';
is_load : out std_logic:= '0';
need_wb : out std_logic:= '0';
stall_out : out std_logic:= '0';
mem_data : out std_logic_vector (31 downto 0)
);
end MEM_datapath;
architecture md of MEM_datapath is
type MEM is array(ram_size-1 downto 0) of std_logic_vector(31 downto 0);
signal ram_block: MEM:= (others=>(others=> '0'));
begin
mem_data <= ram_block(mem_addr) when mem_read = '1';
process (clk)
begin
if(clk'event and clk = '1') then
if(stall_in = '1') then
stall_out <= '1';
else
stall_out <= '0';
MEM_forward_data <= result;
MEM_forward <= EX_forward;
lw_forward <= '0';
if (inst_id=20) then --lw
read_data <= ram_block(to_integer(unsigned(result)));
wb_reg_out <= wb_reg_in;
is_load <= '1';
need_wb <= '1';
if(lw_hazard='1')then
MEM_forward_data <= ram_block(to_integer(unsigned(result)));
lw_forward <= '1';
end if;
elsif (inst_id=21) then --sw
ram_block(to_integer(unsigned(result))) <= b;
is_load <= '0';
need_wb <= '0';
elsif (inst_id=22 or inst_id=23 or inst_id=24 or inst_id=25) then --beq,bne,j,jr
is_load <= '0';
need_wb <= '0';
elsif (inst_id= 26) then--jal
wb_reg_out <= "11111";
wb_data_out <= std_logic_vector(to_unsigned(counter_jal,32));
is_load <= '0';
need_wb <= '1';
else
wb_reg_out <= wb_reg_in;
wb_data_out <= result;
is_load <= '0';
need_wb <= '1';
end if;
end if;
end if;
end process;
end md;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fen_pin IS
PORT( CLK : IN STD_LOGIC;
CLK_1 : OUT STD_LOGIC );
END fen_pin;
ARCHITECTURE BEHAV OF fen_pin IS
SIGNAL A : INTEGER RANGE 0 TO 2499;
SIGNAL Q : STD_LOGIC;
BEGIN
PROCESS(CLK) ----5000分频得到1Hz的频率（假设系统频率为5KHz）
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF A=2499 THEN
Q <= NOT Q;
A <= 0;
ELSE A <= A+1;END IF;
END IF;
END PROCESS;
CLK_1 <= Q;
END;
|
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ov7seg IS
PORT (
OV : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END ov7seg;
ARCHITECTURE behavioral OF ov7seg IS
BEGIN
seg : PROCESS(OV)
BEGIN
CASE OV IS
WHEN "00" => HEX <= "1111111"; -- Positive number
WHEN "01" => HEX <= "1000001"; -- Positive spillover
WHEN "10" => HEX <= "1001000"; -- Negative Overflow
WHEN OTHERS => HEX <= "0111111"; -- Negative
END CASE;
END PROCESS;
END behavioral;
|
<reponame>eugenecartwright/hthreads<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AWIDTH -- User logic address bus width
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_Burst -- Bus to IP burst-mode qualifier
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- Bus2IP_MstError -- Bus to IP master error
-- Bus2IP_MstLastAck -- Bus to IP master last acknowledge
-- Bus2IP_MstRdAck -- Bus to IP master read acknowledge
-- Bus2IP_MstWrAck -- Bus to IP master write acknowledge
-- Bus2IP_MstRetry -- Bus to IP master retry
-- Bus2IP_MstTimeOut -- Bus to IP mster timeout
-- IP2Bus_Addr -- IP to Bus address for the master transaction
-- IP2Bus_MstBE -- IP to Bus byte-enables qualifiers
-- IP2Bus_MstBurst -- IP to Bus burst qualifier
-- IP2Bus_MstBusLock -- IP to Bus bus-lock qualifier
-- IP2Bus_MstNum -- IP to Bus burst size indicator
-- IP2Bus_MstRdReq -- IP to Bus master read request
-- IP2Bus_MstWrReq -- IP to Bus master write request
-- IP2IP_Addr -- IP to IP local device address for the master transaction
------------------------------------------------------------------------------
entity user_logic is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64;
C_NUM_CE : integer := 8
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity user_logic;
architecture IMP of user_logic is
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 5);
signal slv_reg_read_select : std_logic_vector(0 to 5);
signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for write/read data
signal mst_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal mst_reg_read_request : std_logic;
signal mst_reg_write_select : std_logic_vector(0 to 1);
signal mst_reg_read_select : std_logic_vector(0 to 1);
signal mst_write_ack : std_logic;
signal mst_read_ack : std_logic;
-- signals for master control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_reg : BYTE_REG_TYPE;
signal mst_byte_we : std_logic_vector(0 to 15);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_ip2ip_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_ip2bus_be : std_logic_vector(0 to C_DWIDTH/8-1);
signal mst_go : std_logic;
-- signals for master control state machine
type MASTER_CNTL_SM_TYPE is (IDLE, SINGLE, BURST_16, LAST_BURST, CHK_BURST_DONE);
signal mst_cntl_state : MASTER_CNTL_SM_TYPE;
signal mst_sm_set_done : std_logic;
signal mst_sm_busy : std_logic;
signal mst_sm_clr_go : std_logic;
signal mst_sm_rd_req : std_logic;
signal mst_sm_wr_req : std_logic;
signal mst_sm_burst : std_logic;
signal mst_sm_bus_lock : std_logic;
signal mst_sm_ip2bus_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_sm_ip2ip_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_sm_ip2bus_be : std_logic_vector(0 to C_DWIDTH/8-1);
signal mst_sm_ip2bus_mstnum : std_logic_vector(0 to 4);
signal mst_xfer_length : integer;
signal mst_xfer_count : integer;
signal mst_ip_addr_count : integer;
signal mst_bus_addr_count : integer;
signal tid_reg : std_logic_vector(0 to C_DWIDTH-1);
signal tmr_reg : std_logic_vector(0 to C_DWIDTH-1);
signal sta_reg : std_logic_vector(0 to C_DWIDTH-1);
signal cmd_reg : std_logic_vector(0 to C_DWIDTH-1);
signal arg_reg : std_logic_vector(0 to C_DWIDTH-1);
signal res_reg : std_logic_vector(0 to C_DWIDTH-1);
alias tid_read : std_logic is Bus2IP_RdCE(0);
alias tmr_read : std_logic is Bus2IP_RdCE(1);
alias sta_read : std_logic is Bus2IP_RdCE(2);
alias cmd_read : std_logic is Bus2IP_RdCE(3);
alias arg_read : std_logic is Bus2IP_RdCE(4);
alias res_read : std_logic is Bus2IP_RdCE(5);
alias tid_write : std_logic is Bus2IP_WrCE(0);
alias tmr_write : std_logic is Bus2IP_WrCE(1);
alias sta_write : std_logic is Bus2IP_WrCE(2);
alias cmd_write : std_logic is Bus2IP_WrCE(3);
alias arg_write : std_logic is Bus2IP_WrCE(4);
alias res_write : std_logic is Bus2IP_WrCE(5);
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 5);
slv_reg_read_select <= Bus2IP_RdCE(0 to 5);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5);
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
else
case slv_reg_write_select is
when "100000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "010000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "001000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000001" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5 ) is
begin
case slv_reg_read_select is
when "100000" => slv_ip2bus_data <= slv_reg0;
when "010000" => slv_ip2bus_data <= slv_reg1;
when "001000" => slv_ip2bus_data <= slv_reg2;
when "000100" => slv_ip2bus_data <= slv_reg3;
when "000010" => slv_ip2bus_data <= slv_reg4;
when "000001" => slv_ip2bus_data <= slv_reg5;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to demonstrate user logic master model functionality
--
-- Note:
-- The example code presented here is to show you one way of stimulating
-- the IPIF IP master interface under user control. It is provided for
-- demonstration purposes only and allows the user to exercise the IPIF
-- IP master interface during test and evaluation of the template.
-- This user logic master model contains a 16-byte flattened register and
-- the user is required to initialize the value to desire and then write to
-- the model's 'Go' port to initiate the user logic master operation.
--
-- Control Register (C_BASEADDR + OFFSET + 0x0):
-- bit 0 - Rd (Read Request Control)
-- bit 1 - Wr (Write Request Control)
-- bit 2 - BL (Bus Lock Control)
-- bit 3 - Brst (Burst Assertion Control)
-- bit 4-7 - Spare (Spare Control Bits)
-- Status Register (C_BASEADDR + OFFSET + 0x1):
-- bit 0 - Done (Transfer Done Status)
-- bit 1 - Bsy (User Logic Master is Busy)
-- bit 2-7 - Spare (Spare Status Bits)
-- IP2IP Register (C_BASEADDR + OFFSET + 0x4):
-- bit 0-31 - IP2IP Address (This 32-bit value is used to populate the
-- IP2IP_Addr(0:31) address bus during a Read or Write user
-- logic master operation)
-- IP2Bus Register (C_BASEADDR + OFFSET + 0x8):
-- bit 0-31 - IP2Bus Address (This 32-bit value is used to populate the
-- IP2Bus_Addr(0:31) address bus during a Read or Write user
-- logic master operation)
-- Length Register (C_BASEADDR + OFFSET + 0xC):
-- bit 0-15 - Transfer Length (This 16-bit value is used to specify the
-- number of bytes (1 to 65,536) to transfer during user logic
-- master read or write operations)
-- BE Register (C_BASEADDR + OFFSET + 0xE):
-- bit 0-7 - IP2Bus master BE (This 8-bit value is used to populate the
-- IP2Bus_MstBE byte enable bus during user logic master read or
-- write operations, only used in single data beat operation)
-- Go Register (C_BASEADDR + OFFSET + 0xF):
-- bit 0-7 - Go Port (A write to this byte address initiates the user
-- logic master transfer, data key value of 0x0A must be used)
--
-- Note: OFFSET may be different depending on your address space configuration,
-- by default it's either 0x0 or 0x100. Refer to IPIF address range array
-- for actual value.
--
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the source data address (local) to the ip2ip register
-- 3. write the destination address (remote) to the ip2bus register
-- - note: this address will be put on the target bus address line
-- 4. write 0x0004 to the length register
-- 5. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 6. write 0x0a to the go register, this will start the write operation
--
------------------------------------------
mst_reg_read_request <= Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
mst_reg_write_select <= Bus2IP_WrCE(6 to 7);
mst_reg_read_select <= Bus2IP_RdCE(6 to 7);
mst_write_ack <= Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
mst_read_ack <= Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
-- user logic master request output assignments
IP2Bus_Addr <= mst_sm_ip2bus_addr;
IP2Bus_MstBE <= mst_sm_ip2bus_be;
IP2Bus_MstBurst <= mst_sm_burst;
IP2Bus_MstBusLock <= mst_sm_bus_lock;
IP2Bus_MstNum <= mst_sm_ip2bus_mstnum;
IP2Bus_MstRdReq <= mst_sm_rd_req;
IP2Bus_MstWrReq <= mst_sm_wr_req;
IP2IP_Addr <= mst_sm_ip2ip_addr;
-- rip control bits from master model registers
mst_cntl_rd_req <= mst_reg(0)(0);
mst_cntl_wr_req <= mst_reg(0)(1);
mst_cntl_bus_lock <= mst_reg(0)(2);
mst_cntl_burst <= mst_reg(0)(3);
mst_ip2ip_addr <= mst_reg(4) & mst_reg(5) & mst_reg(6) & mst_reg(7);
mst_ip2bus_addr <= mst_reg(8) & mst_reg(9) & mst_reg(10) & mst_reg(11);
mst_xfer_length <= CONV_INTEGER(mst_reg(12) & mst_reg(13));
mst_ip2bus_be <= mst_reg(14);
-- implement byte write enable for each byte slice of the master model registers
MASTER_REG_BYTE_WR_EN : process( Bus2IP_BE, Bus2IP_WrReq, mst_reg_write_select ) is
begin
for byte_index in 0 to 15 loop
mst_byte_we(byte_index) <= Bus2IP_WrReq and
mst_reg_write_select(byte_index/(C_DWIDTH/8)) and
Bus2IP_BE(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8));
end loop;
end process MASTER_REG_BYTE_WR_EN;
-- implement master model registers
MASTER_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_reg(0 to 14) <= (others => "00000000");
else
-- control register (byte 0)
if ( mst_byte_we(0) = '1' ) then
mst_reg(0) <= Bus2IP_Data(0 to 7);
end if;
-- status register (byte 1)
mst_reg(1)(1) <= mst_sm_busy;
if ( mst_byte_we(1) = '1' ) then
-- allows a clear of the 'Done'
mst_reg(1)(0) <= Bus2IP_Data((1-(1/(C_DWIDTH/8))*(C_DWIDTH/8))*8);
else
-- 'Done' from master control state machine
mst_reg(1)(0) <= mst_sm_set_done or mst_reg(1)(0);
end if;
-- ip2ip address register (byte 4 to 7)
-- ip2bus address register (byte 8 to 11)
-- length register (byte 12 to 13)
-- be register (byte 14)
for byte_index in 4 to 14 loop
if ( mst_byte_we(byte_index) = '1' ) then
mst_reg(byte_index) <= Bus2IP_Data(
(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8))*8 to
(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8))*8+7);
end if;
end loop;
end if;
end if;
end process MASTER_REG_WRITE_PROC;
-- implement master model write only 'go' port
MASTER_WRITE_GO_PORT : process( Bus2IP_Clk ) is
constant GO_DATA_KEY : std_logic_vector(0 to 7) := X"0A";
constant GO_BYTE_LANE : integer := 15;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' or mst_sm_clr_go = '1' ) then
mst_go <= '0';
elsif ( mst_byte_we(GO_BYTE_LANE) = '1' and
Bus2IP_Data((GO_BYTE_LANE-(GO_BYTE_LANE/(C_DWIDTH/8))*(C_DWIDTH/8))*8 to
(GO_BYTE_LANE-(GO_BYTE_LANE/(C_DWIDTH/8))*(C_DWIDTH/8))*8+7) = GO_DATA_KEY ) then
mst_go <= '1';
else
null;
end if;
end if;
end process MASTER_WRITE_GO_PORT;
-- implement master model register read mux
MASTER_REG_READ_PROC : process( mst_reg_read_select, mst_reg ) is
begin
case mst_reg_read_select is
when "10" =>
for byte_index in 0 to C_DWIDTH/8-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(byte_index);
end loop;
when "01" =>
for byte_index in 0 to C_DWIDTH/8-1 loop
if ( byte_index = C_DWIDTH/8-1 ) then
-- go port is not readable
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= (others => '0');
else
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg((C_DWIDTH/8)*1+byte_index);
end if;
end loop;
when others =>
mst_ip2bus_data <= (others => '0');
end case;
end process MASTER_REG_READ_PROC;
--implement master model control state machine
MASTER_CNTL_STATE_MACHINE : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_cntl_state <= IDLE;
mst_sm_clr_go <= '0';
mst_sm_rd_req <= '0';
mst_sm_wr_req <= '0';
mst_sm_burst <= '0';
mst_sm_bus_lock <= '0';
mst_sm_ip2bus_addr <= (others => '0');
mst_sm_ip2bus_be <= (others => '0');
mst_sm_ip2ip_addr <= (others => '0');
mst_sm_ip2bus_mstnum <= "00000";
mst_sm_set_done <= '0';
mst_sm_busy <= '0';
mst_xfer_count <= 0;
mst_bus_addr_count <= 0;
mst_ip_addr_count <= 0;
else
-- default condition
mst_sm_clr_go <= '0';
mst_sm_rd_req <= '0';
mst_sm_wr_req <= '0';
mst_sm_burst <= '0';
mst_sm_bus_lock <= '0';
mst_sm_ip2bus_addr <= (others => '0');
mst_sm_ip2bus_be <= (others => '0');
mst_sm_ip2ip_addr <= (others => '0');
mst_sm_ip2bus_mstnum <= "00000";
mst_sm_set_done <= '0';
mst_sm_busy <= '1';
-- state transition
case mst_cntl_state is
when IDLE =>
if ( mst_go = '1' and mst_xfer_length <= 8 ) then
-- single beat transfer
mst_cntl_state <= SINGLE;
mst_sm_clr_go <= '1';
mst_xfer_count <= CONV_INTEGER(mst_xfer_length);
mst_bus_addr_count <= CONV_INTEGER(mst_ip2bus_addr);
mst_ip_addr_count <= CONV_INTEGER(mst_ip2ip_addr);
elsif ( mst_go = '1' and mst_xfer_length < 128 ) then
-- burst transfer less than 128 bytes
mst_cntl_state <= LAST_BURST;
mst_sm_clr_go <= '1';
mst_xfer_count <= CONV_INTEGER(mst_xfer_length);
mst_bus_addr_count <= CONV_INTEGER(mst_ip2bus_addr);
mst_ip_addr_count <= CONV_INTEGER(mst_ip2ip_addr);
elsif ( mst_go = '1' ) then
-- burst transfer greater than 128 bytes
mst_cntl_state <= BURST_16;
mst_sm_clr_go <= '1';
mst_xfer_count <= CONV_INTEGER(mst_xfer_length);
mst_bus_addr_count <= CONV_INTEGER(mst_ip2bus_addr);
mst_ip_addr_count <= CONV_INTEGER(mst_ip2ip_addr);
else
mst_cntl_state <= IDLE;
mst_sm_busy <= '0';
end if;
when SINGLE =>
if ( Bus2IP_MstLastAck = '1' ) then
mst_cntl_state <= IDLE;
mst_sm_set_done <= '1';
mst_sm_busy <= '0';
else
mst_cntl_state <= SINGLE;
mst_sm_rd_req <= mst_cntl_rd_req;
mst_sm_wr_req <= mst_cntl_wr_req;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_sm_ip2bus_addr <= CONV_STD_LOGIC_VECTOR(mst_bus_addr_count, C_AWIDTH);
mst_sm_ip2bus_be <= mst_ip2bus_be;
mst_sm_ip2ip_addr <= CONV_STD_LOGIC_VECTOR(mst_ip_addr_count, C_AWIDTH);
mst_sm_ip2bus_mstnum <= "00001";
end if;
when BURST_16 =>
if ( Bus2IP_MstLastAck = '1' ) then
mst_cntl_state <= CHK_BURST_DONE;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_xfer_count <= mst_xfer_count-128;
mst_bus_addr_count <= mst_bus_addr_count+128;
mst_ip_addr_count <= mst_ip_addr_count+128;
else
mst_cntl_state <= BURST_16;
mst_sm_rd_req <= mst_cntl_rd_req;
mst_sm_wr_req <= mst_cntl_wr_req;
mst_sm_burst <= mst_cntl_burst;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_sm_ip2bus_addr <= CONV_STD_LOGIC_VECTOR(mst_bus_addr_count, C_AWIDTH);
mst_sm_ip2bus_be <= (others => '1');
mst_sm_ip2ip_addr <= CONV_STD_LOGIC_VECTOR(mst_ip_addr_count, C_AWIDTH);
mst_sm_ip2bus_mstnum <= "10000"; -- 16 double words
end if;
when LAST_BURST =>
if ( Bus2IP_MstLastAck = '1' ) then
mst_cntl_state <= CHK_BURST_DONE;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_xfer_count <= mst_xfer_count-((mst_xfer_count/8)*8);
mst_bus_addr_count <= mst_bus_addr_count+(mst_xfer_count/8)*8;
mst_ip_addr_count <= mst_ip_addr_count+(mst_xfer_count/8)*8;
else
mst_cntl_state <= LAST_BURST;
mst_sm_rd_req <= mst_cntl_rd_req;
mst_sm_wr_req <= mst_cntl_wr_req;
mst_sm_burst <= mst_cntl_burst;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_sm_ip2bus_addr <= CONV_STD_LOGIC_VECTOR(mst_bus_addr_count, C_AWIDTH);
mst_sm_ip2bus_be <= (others => '1');
mst_sm_ip2ip_addr <= CONV_STD_LOGIC_VECTOR(mst_ip_addr_count, C_AWIDTH);
mst_sm_ip2bus_mstnum <= CONV_STD_LOGIC_VECTOR((mst_xfer_count/8), 5);
end if;
when CHK_BURST_DONE =>
if ( mst_xfer_count = 0 ) then
-- transfer done
mst_cntl_state <= IDLE;
mst_sm_set_done <= '1';
mst_sm_busy <= '0';
elsif ( mst_xfer_count <= 8 ) then
-- need single beat transfer
mst_cntl_state <= SINGLE;
mst_sm_bus_lock <= mst_cntl_bus_lock;
elsif ( mst_xfer_count < 128 ) then
-- need burst transfer less than 128 bytes
mst_cntl_state <= LAST_BURST;
mst_sm_bus_lock <= mst_cntl_bus_lock;
else
-- need burst transfer greater than 128 bytes
mst_cntl_state <= BURST_16;
mst_sm_bus_lock <= mst_cntl_bus_lock;
end if;
when others =>
mst_cntl_state <= IDLE;
mst_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CNTL_STATE_MACHINE;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= mst_ip2bus_data when mst_reg_read_request = '1' else
slv_ip2bus_data;
IP2Bus_WrAck <= slv_write_ack or mst_write_ack;
IP2Bus_RdAck <= slv_read_ack or mst_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;
|
<reponame>UVVM/uvvm_vvc_framework
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--===========================================================================================
package gpio_bfm_pkg is
--=========================================================================================
-- Types and constants for GPIO BFM
--=========================================================================================
constant C_SCOPE : string := "GPIO BFM";
-- Configuration record to be assigned in the test harness.
type t_gpio_bfm_config is record
clock_period : time;
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the GPIO BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the GPIO BFM.
timeout : time; -- Timeout value for the expect procedures
end record;
-- Define the default value for the BFM config
constant C_GPIO_BFM_CONFIG_DEFAULT : t_gpio_bfm_config := (
clock_period => -1 ns,
match_strictness => MATCH_STD,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
timeout => -1 ns
);
--=========================================================================================
-- BFM procedures
--=========================================================================================
---------------------------------------------------------------------------------
-- set data
---------------------------------------------------------------------------------
procedure gpio_set (
constant data_value : in std_logic_vector; -- '-' means don't change
constant msg : in string;
signal data_port : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
);
---------------------------------------------------------------------------------
-- get data()
---------------------------------------------------------------------------------
procedure gpio_get (
variable data_value : out std_logic_vector;
constant msg : in string;
signal data_port : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
);
---------------------------------------------------------------------------------
-- check data()
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the expected value.
procedure gpio_check (
constant data_exp : in std_logic_vector; -- '-' means don't care
constant msg : in string;
signal data_port : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
);
-- Perform a read operation, then compare the read value to the expected value.
-- Verify that the read value has been stable for a certain time.
procedure gpio_check_stable (
constant data_exp : in std_logic_vector; -- '-' means don't care
constant stable_req : in time;
constant msg : in string;
signal data_port : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
);
---------------------------------------------------------------------------------
-- expect data()
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the expected value.
procedure gpio_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal data_port : in std_logic_vector;
constant timeout : in time := -1 ns; -- -1 = no timeout
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
);
-- Perform a read operation, then compare the read value to the expected value.
-- Verify that the read value remains stable for a certain time after the data
-- is same as expected or after the data last event.
procedure gpio_expect_stable (
constant data_exp : in std_logic_vector;
constant stable_req : in time;
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant msg : in string;
signal data_port : in std_logic_vector;
constant timeout : in time := -1 ns; -- -1 = no timeout
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
);
end package gpio_bfm_pkg;
--=================================================================================
--=================================================================================
package body gpio_bfm_pkg is
---------------------------------------------------------------------------------
-- set data
---------------------------------------------------------------------------------
procedure gpio_set (
constant data_value : in std_logic_vector; -- '-' means don't change
constant msg : in string;
signal data_port : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
) is
constant name : string := "gpio_set(" & to_string(data_value) & ")";
constant c_data_value : std_logic_vector(data_port'range) := data_value;
begin
for i in 0 to data_port'length-1 loop --data_port'range loop
if c_data_value(i) /= '-' then
data_port(i) <= c_data_value(i);
end if;
end loop;
log(config.id_for_bfm, name & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------
-- get data()
---------------------------------------------------------------------------------
-- Perform a read operation and returns the gpio value
procedure gpio_get (
variable data_value : out std_logic_vector;
constant msg : in string;
signal data_port : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
) is
constant name : string := "gpio_get()";
begin
log(config.id_for_bfm, name & " => Read gpio value: " & to_string(data_port, HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
data_value := data_port;
end procedure;
---------------------------------------------------------------------------------
-- check data()
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the expected value.
procedure gpio_check (
constant data_exp : in std_logic_vector; -- '-' means don't care
constant msg : in string;
signal data_port : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
) is
constant name : string := "gpio_check(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
constant c_data_exp : std_logic_vector(data_port'range) := data_exp;
variable v_check_ok : boolean := true;
variable v_alert_radix : t_radix;
begin
for i in c_data_exp'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if c_data_exp(i) = '-' or check_value(data_port(i), c_data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(data_port, c_data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, name & "=> Failed. Was " & to_string(data_port, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(c_data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, name & "=> OK, read data = " & to_string(data_port, HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
procedure gpio_check_stable (
constant data_exp : in std_logic_vector; -- '-' means don't care
constant stable_req : in time;
constant msg : in string;
signal data_port : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
) is
constant name : string := "gpio_check_stable(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ", " & to_string(stable_req) & ")";
constant c_data_exp : std_logic_vector(data_port'range) := data_exp;
variable v_data_ok : boolean := true;
variable v_stable_ok : boolean := true;
variable v_alert_radix : t_radix;
begin
for i in c_data_exp'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if c_data_exp(i) = '-' or check_value(data_port(i), c_data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_data_ok := true;
else
v_data_ok := false;
exit;
end if;
end loop;
check_stable(data_port, stable_req, alert_level, v_stable_ok, msg, scope, ID_NEVER, msg_id_panel, name);
if not v_data_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(data_port, c_data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, name & "=> Failed. Was " & to_string(data_port, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(c_data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_stable_ok then
log(config.id_for_bfm, name & "=> OK, read data = " & to_string(data_port, HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & ", stable for " & to_string(stable_req) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
---------------------------------------------------------------------------------
-- expect()
---------------------------------------------------------------------------------
-- Perform a receive operation, then compare the received value to the expected value.
procedure gpio_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal data_port : in std_logic_vector;
constant timeout : in time := -1 ns; -- -1 = no timeout
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
) is
constant name : string := "gpio_expect(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
constant c_data_exp : std_logic_vector(data_port'range) := data_exp;
variable v_internal_timeout : time;
variable v_timestamp : time := now;
variable v_time_lapse : time;
variable v_data_ok : boolean := true;
begin
if timeout = -1 ns then -- function was called without parameter
v_internal_timeout := config.timeout;
else
v_internal_timeout := timeout;
end if;
check_value(v_internal_timeout >= 0 ns, TB_FAILURE, "Configured negative timeout (not allowed). " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
await_value(data_port, c_data_exp, config.match_strictness, 0 ns, v_internal_timeout, alert_level, v_data_ok, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, name);
v_time_lapse := now - v_timestamp;
if v_data_ok then
log(config.id_for_bfm, name & "=> OK, expected data = " & to_string(data_port, HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & " after " & to_string(v_time_lapse) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
procedure gpio_expect_stable (
constant data_exp : in std_logic_vector;
constant stable_req : in time;
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant msg : in string;
signal data_port : in std_logic_vector;
constant timeout : in time := -1 ns; -- -1 = no timeout
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT
) is
constant name : string := "gpio_expect_stable(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ", " & to_string(stable_req) & ")";
constant c_data_exp : std_logic_vector(data_port'range) := data_exp;
variable v_internal_timeout : time;
variable v_timestamp : time := now;
variable v_time_lapse : time;
variable v_data_ok : boolean := true;
variable v_stable_ok : boolean := true;
begin
if timeout = -1 ns then -- function was called without parameter
v_internal_timeout := config.timeout;
else
v_internal_timeout := timeout;
end if;
check_value(v_internal_timeout >= 0 ns, TB_FAILURE, "Configured negative timeout (not allowed). " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
await_value(data_port, c_data_exp, config.match_strictness, 0 ns, v_internal_timeout, alert_level, v_data_ok, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, name);
v_time_lapse := now - v_timestamp;
-- The data port already had the expected value
if v_timestamp = now then
await_stable(data_port, stable_req, stable_req_from, stable_req, stable_req_from, alert_level, v_stable_ok, msg, scope, ID_NEVER, msg_id_panel, name);
-- The data port received the expected value after some time
else
await_stable(data_port, stable_req, FROM_NOW, stable_req, FROM_NOW, alert_level, v_stable_ok, msg, scope, ID_NEVER, msg_id_panel, name);
end if;
if v_data_ok and v_stable_ok then
log(config.id_for_bfm, name & "=> OK, expected data = " & to_string(data_port, HEX_BIN_IF_INVALID, AS_IS, INCL_RADIX) & " after " & to_string(v_time_lapse) &
", stable for " & to_string(stable_req) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
end package body gpio_bfm_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PIPO10 is
Port ( Rin: in STD_LOGIC_VECTOR (9 downto 0);
CLK,Preset,Clear: in STD_LOGIC;
Rout : out STD_LOGIC_VECTOR (9 downto 0));
end PIPO10;
architecture PIPO10_arch of PIPO10 is
component DFF_PC
port(D,CLK,Preset,Clear: in STD_LOGIC; Q,Qnot: out STD_LOGIC);
end component;
begin
DFF0: DFF_PC port map(Rin(0),CLK,Preset,Clear,Rout(0),open);
DFF1: DFF_PC port map(Rin(1),CLK,Preset,Clear,Rout(1),open);
DFF2: DFF_PC port map(Rin(2),CLK,Preset,Clear,Rout(2),open);
DFF3: DFF_PC port map(Rin(3),CLK,Preset,Clear,Rout(3),open);
DFF4: DFF_PC port map(Rin(4),CLK,Preset,Clear,Rout(4),open);
DFF5: DFF_PC port map(Rin(5),CLK,Preset,Clear,Rout(5),open);
DFF6: DFF_PC port map(Rin(6),CLK,Preset,Clear,Rout(6),open);
DFF7: DFF_PC port map(Rin(7),CLK,Preset,Clear,Rout(7),open);
DFF8: DFF_PC port map(Rin(8),CLK,Preset,Clear,Rout(8),open);
DFF9: DFF_PC port map(Rin(9),CLK,Preset,Clear,Rout(9),open);
end PIPO10_arch;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity adders is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in1 : IN STD_LOGIC_VECTOR (31 downto 0);
in2 : IN STD_LOGIC_VECTOR (31 downto 0);
in3 : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of adders is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"adders,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a75tlftg256-2l,HLS_INPUT_CLOCK=3.250000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.365667,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=236,HLS_SYN_LUT=87}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_boolean_1 : BOOLEAN := true;
signal tmp1_fu_42_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_reg_53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
tmp1_reg_53 <= tmp1_fu_42_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_CS_fsm)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_return <= std_logic_vector(unsigned(tmp1_reg_53) + unsigned(in2));
tmp1_fu_42_p2 <= std_logic_vector(unsigned(in1) + unsigned(in3));
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity test_display is
port(
seg_a: out std_logic;
seg_b: out std_logic;
seg_c: out std_logic;
seg_d: out std_logic;
seg_e: out std_logic;
seg_f: out std_logic;
seg_g: out std_logic;
display_1: out std_logic;
display_2: out std_logic
);
end test_display;
architecture synth of test_display is
component SB_HFOSC is
generic (
CLKHF_DIV : String := "0b00" -- Divide 48MHz clock by 2ˆN (0-3)
);
port(
CLKHFPU : in std_logic := 'X'; -- Set to 1 to power up
CLKHFEN : in std_logic := 'X'; -- Set to 1 to enable output
CLKHF : out std_logic := 'X' -- Clock output
);
end component;
-- Clock signal
signal clk: std_logic;
signal counter: unsigned(25 downto 0);
begin
osc: SB_HFOSC
generic map(CLKHF_DIV => "0b00")
port map(
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => clk
);
process(clk) begin
if rising_edge(clk) then
counter <= counter + 1;
display_1 <= counter(24);
display_2 <= not counter(24);
seg_a <= counter(25);
seg_b <= not counter(25);
seg_c <= counter(25);
seg_d <= not counter(25);
seg_e <= counter(25);
seg_f <= not counter(25);
seg_g <= counter(25);
end if;
end process;
end;
|
<reponame>lars2309/fletcher
-- Copyright 2019 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.UtilInt_pkg.all;
use work.Interconnect_pkg.all;
use work.MM_pkg.all;
-- AXI4 compatible top level for Fletcher generated accelerators.
entity f1_top is
generic (
-- Host bus properties
BUS_ADDR_WIDTH : natural := 64;
BUS_DATA_WIDTH : natural := 512;
BUS_STROBE_WIDTH : natural := 64;
BUS_LEN_WIDTH : natural := 8;
BUS_BURST_MAX_LEN : natural := 64;
BUS_BURST_STEP_LEN : natural := 1;
-- MMIO bus properties
SLV_BUS_ADDR_WIDTH : natural := 32;
SLV_BUS_DATA_WIDTH : natural := 32;
REG_WIDTH : natural := 32;
-- Virtual memory properties
PAGE_SIZE_LOG2 : natural := 22;
VM_BASE : unsigned(ADDR_WIDTH_LIMIT-1 downto 0) := X"4000_0000_0000_0000";
MEM_REGIONS : natural := 1;
MEM_SIZES : nat_array := (0 => 16*1024*1024/(2**22/1024)); -- (2**PAGE_SIZE_LOG2/1024)
MEM_MAP_BASE : unsigned(ADDR_WIDTH_LIMIT-1 downto 0) := (others => '0');
MEM_MAP_SIZE_LOG2 : natural := 37;
PT_ENTRIES_LOG2 : natural := 13;
PTE_BITS : natural := 64; -- BUS_ADDR_WIDTH
-- Accelerator properties
INDEX_WIDTH : natural := 32;
TAG_WIDTH : natural := 1;
NUM_ARROW_BUFFERS : natural := 0;
NUM_USER_REGS : natural := 0;
NUM_REGS : natural := 26 + 12 * 4 + 1 + 1
);
port (
kcd_clk : in std_logic;
kcd_reset : in std_logic;
bcd_clk : in std_logic;
bcd_reset_n : in std_logic;
---------------------------------------------------------------------------
-- AXI4 master as Device Memory Interface for Fletcher
---------------------------------------------------------------------------
-- Read address channel
m_axi_araddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_arsize : out std_logic_vector(2 downto 0);
-- Read data channel
m_axi_rdata : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rlast : in std_logic;
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
-- Write address channel
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
-- Write data channel
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
m_axi_wlast : out std_logic;
m_axi_wstrb : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);
-- Write response channel
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- AXI4 master as Device Memory Interface for Host
---------------------------------------------------------------------------
-- Read address channel
ml_axi_araddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
ml_axi_arid : out std_logic_vector(15 downto 0);
ml_axi_arlen : out std_logic_vector(7 downto 0);
ml_axi_arvalid : out std_logic;
ml_axi_arready : in std_logic;
ml_axi_arsize : out std_logic_vector(2 downto 0);
-- Read data channel
ml_axi_rdata : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
ml_axi_rid : in std_logic_vector(15 downto 0);
ml_axi_rresp : in std_logic_vector(1 downto 0);
ml_axi_rlast : in std_logic;
ml_axi_rvalid : in std_logic;
ml_axi_rready : out std_logic;
-- Write address channel
ml_axi_awvalid : out std_logic;
ml_axi_awready : in std_logic;
ml_axi_awid : out std_logic_vector(15 downto 0);
ml_axi_awaddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
ml_axi_awlen : out std_logic_vector(7 downto 0);
ml_axi_awsize : out std_logic_vector(2 downto 0);
-- Write data channel
ml_axi_wvalid : out std_logic;
ml_axi_wready : in std_logic;
ml_axi_wdata : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
ml_axi_wlast : out std_logic;
ml_axi_wstrb : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);
-- Write response channel
ml_axi_bvalid : in std_logic;
ml_axi_bready : out std_logic;
ml_axi_bid : in std_logic_vector(15 downto 0);
ml_axi_bresp : in std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- AXI4 slave as Host Memory Interface
---------------------------------------------------------------------------
-- Read address channel
s_axi_araddr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
s_axi_arid : in std_logic_vector(15 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_arsize : in std_logic_vector(2 downto 0);
-- Read data channel
s_axi_rdata : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
s_axi_rid : out std_logic_vector(15 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Write address channel
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_awid : in std_logic_vector(15 downto 0);
s_axi_awaddr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
-- Write data channel
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_wdata : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wstrb : in std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);
-- Write response channel
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_bid : out std_logic_vector(15 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- AXI4-lite Slave as MMIO interface
---------------------------------------------------------------------------
-- Write adress channel
mmio_axi_awvalid : in std_logic;
mmio_axi_awready : out std_logic;
mmio_axi_awaddr : in std_logic_vector(SLV_BUS_ADDR_WIDTH-1 downto 0);
-- Write data channel
mmio_axi_wvalid : in std_logic;
mmio_axi_wready : out std_logic;
mmio_axi_wdata : in std_logic_vector(SLV_BUS_DATA_WIDTH-1 downto 0);
mmio_axi_wstrb : in std_logic_vector((SLV_BUS_DATA_WIDTH/8)-1 downto 0);
-- Write response channel
mmio_axi_bvalid : out std_logic;
mmio_axi_bready : in std_logic;
mmio_axi_bresp : out std_logic_vector(1 downto 0);
-- Read address channel
mmio_axi_arvalid : in std_logic;
mmio_axi_arready : out std_logic;
mmio_axi_araddr : in std_logic_vector(SLV_BUS_ADDR_WIDTH-1 downto 0);
-- Read data channel
mmio_axi_rvalid : out std_logic;
mmio_axi_rready : in std_logic;
mmio_axi_rdata : out std_logic_vector(SLV_BUS_DATA_WIDTH-1 downto 0);
mmio_axi_rresp : out std_logic_vector(1 downto 0)
);
end f1_top;
architecture Behavorial of f1_top is
component axi_top is
generic (
-- Host bus properties
BUS_ADDR_WIDTH : natural := 64;
BUS_DATA_WIDTH : natural := 512;
BUS_STROBE_WIDTH : natural := 64;
BUS_LEN_WIDTH : natural := 8;
BUS_BURST_MAX_LEN : natural := 64;
BUS_BURST_STEP_LEN : natural := 1;
-- MMIO bus properties
SLV_BUS_ADDR_WIDTH : natural := 32;
SLV_BUS_DATA_WIDTH : natural := 32;
REG_WIDTH : natural := 32;
-- Arrow properties
INDEX_WIDTH : natural := 32;
-- Virtual memory properties
PAGE_SIZE_LOG2 : natural := 22;
VM_BASE : unsigned(ADDR_WIDTH_LIMIT-1 downto 0) := X"4000_0000_0000_0000";
MEM_REGIONS : natural := 1;
MEM_SIZES : nat_array;
MEM_MAP_BASE : unsigned(ADDR_WIDTH_LIMIT-1 downto 0) := (others => '0');
MEM_MAP_SIZE_LOG2 : natural := 37;
PT_ENTRIES_LOG2 : natural := 13;
PTE_BITS : natural := 64; -- BUS_ADDR_WIDTH
-- Accelerator properties
TAG_WIDTH : natural := 1;
NUM_ARROW_BUFFERS : natural := 0;
NUM_USER_REGS : natural := 0;
NUM_REGS : natural := 10
);
port (
kcd_clk : in std_logic;
kcd_reset : in std_logic;
bcd_clk : in std_logic;
bcd_reset_n : in std_logic;
---------------------------------------------------------------------------
-- AXI4 master as Host Memory Interface
---------------------------------------------------------------------------
-- Read address channel
m_axi_araddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_arsize : out std_logic_vector(2 downto 0);
-- Read data channel
m_axi_rdata : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rlast : in std_logic;
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
-- Write address channel
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
-- Write data channel
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
m_axi_wlast : out std_logic;
m_axi_wstrb : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);
-- Write response channel
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- AXI4-lite Slave as MMIO interface
---------------------------------------------------------------------------
-- Write adress channel
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_awaddr : in std_logic_vector(SLV_BUS_ADDR_WIDTH-1 downto 0);
-- Write data channel
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_wdata : in std_logic_vector(SLV_BUS_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((SLV_BUS_DATA_WIDTH/8)-1 downto 0);
-- Write response channel
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
-- Read address channel
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_araddr : in std_logic_vector(SLV_BUS_ADDR_WIDTH-1 downto 0);
-- Read data channel
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_rdata : out std_logic_vector(SLV_BUS_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
-- Translate request channel
htr_req_valid : in std_logic := '0';
htr_req_ready : out std_logic;
htr_req_addr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Translate response channel
htr_resp_valid : out std_logic;
htr_resp_ready : in std_logic := '1';
htr_resp_virt : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
htr_resp_phys : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
htr_resp_mask : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0)
);
end component;
signal bcd_reset : std_logic;
-- Translate request channel
signal tr_q_valid : std_logic;
signal tr_q_ready : std_logic;
signal tr_q_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
-- Translate response channel
signal tr_a_valid : std_logic;
signal tr_a_ready : std_logic;
signal tr_a_virt : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_a_phys : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_a_mask : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_a_data : std_logic_vector(BUS_ADDR_WIDTH*3-1 downto 0);
-- Translate request channel (read)
signal tr_rq_valid : std_logic;
signal tr_rq_ready : std_logic;
signal tr_rq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
-- Translate response channel (read)
signal tr_ra_valid : std_logic;
signal tr_ra_ready : std_logic;
signal tr_ra_virt : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_ra_phys : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_ra_mask : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_ra_data : std_logic_vector(BUS_ADDR_WIDTH*3-1 downto 0);
-- Translate request channel (write)
signal tr_wq_valid : std_logic;
signal tr_wq_ready : std_logic;
signal tr_wq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
-- Translate response channel (write)
signal tr_wa_valid : std_logic;
signal tr_wa_ready : std_logic;
signal tr_wa_virt : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_wa_phys : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_wa_mask : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
signal tr_wa_data : std_logic_vector(BUS_ADDR_WIDTH*3-1 downto 0);
signal s_axi_aruser : std_logic_vector(s_axi_arid'length + s_axi_arsize'length - 1 downto 0);
signal ml_axi_aruser : std_logic_vector(s_axi_arid'length + s_axi_arsize'length - 1 downto 0);
signal s_axi_awuser : std_logic_vector(s_axi_awid'length + s_axi_awsize'length - 1 downto 0);
signal ml_axi_awuser : std_logic_vector(s_axi_awid'length + s_axi_awsize'length - 1 downto 0);
begin
-- Active high reset
bcd_reset <= '1' when bcd_reset_n = '0' else '0';
axi_top_inst : axi_top
generic map (
-- Host bus properties
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
BUS_DATA_WIDTH => BUS_DATA_WIDTH,
BUS_STROBE_WIDTH => BUS_STROBE_WIDTH,
BUS_LEN_WIDTH => BUS_LEN_WIDTH,
BUS_BURST_MAX_LEN => BUS_BURST_MAX_LEN,
BUS_BURST_STEP_LEN => BUS_BURST_STEP_LEN,
-- MMIO bus properties
SLV_BUS_ADDR_WIDTH => SLV_BUS_ADDR_WIDTH,
SLV_BUS_DATA_WIDTH => SLV_BUS_DATA_WIDTH,
REG_WIDTH => REG_WIDTH,
-- Arrow properties
INDEX_WIDTH => INDEX_WIDTH,
-- Virtual memory properties
PAGE_SIZE_LOG2 => PAGE_SIZE_LOG2,
VM_BASE => VM_BASE,
MEM_REGIONS => MEM_REGIONS,
MEM_SIZES => MEM_SIZES,
MEM_MAP_BASE => MEM_MAP_BASE,
MEM_MAP_SIZE_LOG2 => MEM_MAP_SIZE_LOG2,
PT_ENTRIES_LOG2 => PT_ENTRIES_LOG2,
PTE_BITS => PTE_BITS,
-- Accelerator properties
TAG_WIDTH => TAG_WIDTH,
NUM_ARROW_BUFFERS => NUM_ARROW_BUFFERS,
NUM_USER_REGS => NUM_USER_REGS,
NUM_REGS => NUM_REGS
)
port map (
kcd_clk => kcd_clk,
kcd_reset => kcd_reset,
bcd_clk => bcd_clk,
bcd_reset_n => bcd_reset_n,
---------------------------------------------------------------------------
-- AXI4 master as Host Memory Interface
---------------------------------------------------------------------------
-- Read address channel
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_arsize => m_axi_arsize,
-- Read data channel
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready,
-- Write address channel
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
-- Write data channel
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wlast => m_axi_wlast,
m_axi_wstrb => m_axi_wstrb,
-- Write response channel
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp => m_axi_bresp,
---------------------------------------------------------------------------
-- AXI4-lite Slave as MMIO interface
---------------------------------------------------------------------------
-- Write adress channel
s_axi_awvalid => mmio_axi_awvalid,
s_axi_awready => mmio_axi_awready,
s_axi_awaddr => mmio_axi_awaddr,
-- Write data channel
s_axi_wvalid => mmio_axi_wvalid,
s_axi_wready => mmio_axi_wready,
s_axi_wdata => mmio_axi_wdata,
s_axi_wstrb => mmio_axi_wstrb,
-- Write response channel
s_axi_bvalid => mmio_axi_bvalid,
s_axi_bready => mmio_axi_bready,
s_axi_bresp => mmio_axi_bresp,
-- Read address channel
s_axi_arvalid => mmio_axi_arvalid,
s_axi_arready => mmio_axi_arready,
s_axi_araddr => mmio_axi_araddr,
-- Read data channel
s_axi_rvalid => mmio_axi_rvalid,
s_axi_rready => mmio_axi_rready,
s_axi_rdata => mmio_axi_rdata,
s_axi_rresp => mmio_axi_rresp,
-- Translate request channel
htr_req_valid => tr_q_valid,
htr_req_ready => tr_q_ready,
htr_req_addr => tr_q_addr,
-- Translate response channel
htr_resp_valid => tr_a_valid,
htr_resp_ready => tr_a_ready,
htr_resp_virt => tr_a_virt,
htr_resp_phys => tr_a_phys,
htr_resp_mask => tr_a_mask
);
-----------------------------------------------------------------------------
-- Device memory AXI slave for host
-----------------------------------------------------------------------------
-- Read data channel
s_axi_rid <= ml_axi_rid;
s_axi_rdata <= ml_axi_rdata;
s_axi_rresp <= ml_axi_rresp;
s_axi_rlast <= ml_axi_rlast;
s_axi_rvalid <= ml_axi_rvalid;
ml_axi_rready <= s_axi_rready;
-- Write data channel
ml_axi_wvalid <= s_axi_wvalid;
s_axi_wready <= ml_axi_wready;
ml_axi_wdata <= s_axi_wdata;
ml_axi_wlast <= s_axi_wlast;
ml_axi_wstrb <= s_axi_wstrb;
-- Write response channel
s_axi_bvalid <= ml_axi_bvalid;
ml_axi_bready <= s_axi_bready;
s_axi_bid <= ml_axi_bid;
s_axi_bresp <= ml_axi_bresp;
read_translator : MMTranslator
generic map (
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
BUS_LEN_WIDTH => BUS_LEN_WIDTH,
USER_WIDTH => s_axi_aruser'length,
VM_BASE => VM_BASE,
PT_ENTRIES_LOG2 => PT_ENTRIES_LOG2,
PAGE_SIZE_LOG2 => PAGE_SIZE_LOG2,
SLV_SLICES => 4, -- Extra slices to accomodate SLR crossing
MST_SLICES => 4
)
port map (
clk => bcd_clk,
reset => bcd_reset,
-- Slave request channel
slv_req_valid => s_axi_arvalid,
slv_req_ready => s_axi_arready,
slv_req_addr => s_axi_araddr,
slv_req_len => s_axi_arlen,
slv_req_user => s_axi_aruser,
-- Master request channel
mst_req_valid => ml_axi_arvalid,
mst_req_ready => ml_axi_arready,
mst_req_addr => ml_axi_araddr,
mst_req_len => ml_axi_arlen,
mst_req_user => ml_axi_aruser,
-- Translate request channel
req_valid => tr_rq_valid,
req_ready => tr_rq_ready,
req_addr => tr_rq_addr,
-- Translate response channel
resp_valid => tr_ra_valid,
resp_ready => tr_ra_ready,
resp_virt => tr_ra_virt,
resp_phys => tr_ra_phys,
resp_mask => tr_ra_mask
);
s_axi_aruser <= s_axi_arid & s_axi_arsize;
ml_axi_arsize <= ml_axi_aruser(s_axi_arsize'high downto 0);
ml_axi_arid <= ml_axi_aruser(s_axi_aruser'high downto s_axi_arsize'high + 1);
write_translator : MMTranslator
generic map (
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
BUS_LEN_WIDTH => BUS_LEN_WIDTH,
USER_WIDTH => s_axi_awuser'length,
VM_BASE => VM_BASE,
PT_ENTRIES_LOG2 => PT_ENTRIES_LOG2,
PAGE_SIZE_LOG2 => PAGE_SIZE_LOG2,
SLV_SLICES => 4, -- Extra slices to accomodate SLR crossing
MST_SLICES => 4
)
port map (
clk => bcd_clk,
reset => bcd_reset,
-- Slave request channel
slv_req_valid => s_axi_awvalid,
slv_req_ready => s_axi_awready,
slv_req_addr => s_axi_awaddr,
slv_req_len => s_axi_awlen,
slv_req_user => s_axi_awuser,
-- Master request channel
mst_req_valid => ml_axi_awvalid,
mst_req_ready => ml_axi_awready,
mst_req_addr => ml_axi_awaddr,
mst_req_len => ml_axi_awlen,
mst_req_user => ml_axi_awuser,
-- Translate request channel
req_valid => tr_wq_valid,
req_ready => tr_wq_ready,
req_addr => tr_wq_addr,
-- Translate response channel
resp_valid => tr_wa_valid,
resp_ready => tr_wa_ready,
resp_virt => tr_wa_virt,
resp_phys => tr_wa_phys,
resp_mask => tr_wa_mask
);
s_axi_awuser <= s_axi_awid & s_axi_awsize;
ml_axi_awsize <= ml_axi_awuser(s_axi_awsize'high downto 0);
ml_axi_awid <= ml_axi_awuser(s_axi_awuser'high downto s_axi_awsize'high + 1);
-- Arbiter for the address translation requests of AXI slave R/W channels.
tr_req_arb_inst : BusReadArbiter
generic map (
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
BUS_LEN_WIDTH => 1,
BUS_DATA_WIDTH => BUS_ADDR_WIDTH * 3,
NUM_SLAVE_PORTS => 2,
ARB_METHOD => "ROUND-ROBIN",
MAX_OUTSTANDING => 2,
SLV_REQ_SLICES => true,
MST_REQ_SLICE => true,
MST_DAT_SLICE => true,
SLV_DAT_SLICES => true
)
port map (
bcd_clk => bcd_clk,
bcd_reset => bcd_reset,
mst_rreq_valid => tr_q_valid,
mst_rreq_ready => tr_q_ready,
mst_rreq_addr => tr_q_addr,
mst_rdat_valid => tr_a_valid,
mst_rdat_ready => tr_a_ready,
mst_rdat_data => tr_a_data,
mst_rdat_last => '1',
bs00_rreq_valid => tr_rq_valid,
bs00_rreq_ready => tr_rq_ready,
bs00_rreq_addr => tr_rq_addr,
bs00_rreq_len => "1",
bs00_rdat_valid => tr_ra_valid,
bs00_rdat_ready => tr_ra_ready,
bs00_rdat_data => tr_ra_data,
bs01_rreq_valid => tr_wq_valid,
bs01_rreq_ready => tr_wq_ready,
bs01_rreq_addr => tr_wq_addr,
bs01_rreq_len => "1",
bs01_rdat_valid => tr_wa_valid,
bs01_rdat_ready => tr_wa_ready,
bs01_rdat_data => tr_wa_data
);
tr_a_data <= tr_a_virt & tr_a_phys & tr_a_mask;
tr_ra_virt <= EXTRACT(tr_ra_data, BUS_ADDR_WIDTH*2, BUS_ADDR_WIDTH);
tr_ra_phys <= EXTRACT(tr_ra_data, BUS_ADDR_WIDTH*1, BUS_ADDR_WIDTH);
tr_ra_mask <= EXTRACT(tr_ra_data, BUS_ADDR_WIDTH*0, BUS_ADDR_WIDTH);
tr_wa_virt <= EXTRACT(tr_wa_data, BUS_ADDR_WIDTH*2, BUS_ADDR_WIDTH);
tr_wa_phys <= EXTRACT(tr_wa_data, BUS_ADDR_WIDTH*1, BUS_ADDR_WIDTH);
tr_wa_mask <= EXTRACT(tr_wa_data, BUS_ADDR_WIDTH*0, BUS_ADDR_WIDTH);
end architecture;
|
<filename>LCMX02-DevBoard/top.vhd<gh_stars>0
-- Project top level
-- Implements eight readable and eight writable registers
-- The hex switch is connected to one of the readable registers
-- The LEDs are connected to one of the writable registers
-- The other registers are connected to each other for readback
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library MACHXO2;
use MACHXO2.components.all;
ENTITY top IS
PORT(
hex_switch_nb0 : IN STD_LOGIC; -- Connects to PT33A, pin 1, inverted
hex_switch_nb1 : IN STD_LOGIC; -- Connects to PT33A, pin 5, inverted
hex_switch_nb2 : IN STD_LOGIC; -- Connects to PT33A, pin 112, inverted
hex_switch_nb3 : IN STD_LOGIC; -- Connects to PT33A, pin 114, inverted
led1 : INOUT STD_LOGIC; -- Connects to PR2C, pin 97, D1
led2 : INOUT STD_LOGIC; -- Connects to PR2C, pin 98, D2
led3 : INOUT STD_LOGIC; -- Connects to PR2C, pin 99, D3
led4 : INOUT STD_LOGIC; -- Connects to PR2C, pin 100, D4
led5 : INOUT STD_LOGIC; -- Connects to PR2C, pin 104, D5
led6 : INOUT STD_LOGIC; -- Connects to PR2C, pin 105, D6
led7 : INOUT STD_LOGIC; -- Connects to PR2B, pin 106, D7
led8 : INOUT STD_LOGIC; -- Connects to PR2A, pin 107, D8
ft2232b_d0 : IN STD_LOGIC; -- Connects to Port B D0 on the FT2232 (SCLK - rising edge active)
ft2232b_d1 : IN STD_LOGIC; -- Connects to Port B D1 on the FT2232 (SDI - into the Lattice device)
ft2232b_d2 : OUT STD_LOGIC; -- Connects to Port B D2 on the FT2232 (SDO - out of the Lattice device)
ft2232b_d3 : IN STD_LOGIC; -- Connects to Port B D3 on the FT2232 (CS - active low)
ft2232b_d4 : IN STD_LOGIC; -- Connects to Port B D4 on the FT2232
ft2232b_d5 : IN STD_LOGIC; -- Connects to Port B D5 on the FT2232
ft2232b_d6 : IN STD_LOGIC); -- Connects to Port B D6 on the FT2232
END top;
ARCHITECTURE behavior OF top IS
SIGNAL clk : STD_LOGIC;
SIGNAL myWrReg0 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myWrReg1 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myWrReg2 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myWrReg3 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myWrReg4 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myWrReg5 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myWrReg6 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myWrReg7 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg0 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg1 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg2 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg3 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg4 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg5 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg6 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL myRdReg7 : STD_LOGIC_VECTOR(7 downto 0);
--internal oscillator
COMPONENT OSCH
GENERIC(
NOM_FREQ: string := "53.20");
PORT(
STDBY : IN STD_LOGIC;
OSC : OUT STD_LOGIC;
SEDSTDBY : OUT STD_LOGIC);
END COMPONENT;
COMPONENT spi_port
PORT(
clkin : IN STD_LOGIC; -- The master clock
sclk : IN STD_LOGIC; -- Serial clock
sdi : IN STD_LOGIC; -- Serial data in
sdo : OUT STD_LOGIC; -- Serial data out
cs : IN STD_LOGIC; -- Chip select, active low
wrReg0 : OUT STD_LOGIC_VECTOR(7 downto 0); -- Registers that get written over the SPI bus
wrReg1 : OUT STD_LOGIC_VECTOR(7 downto 0);
wrReg2 : OUT STD_LOGIC_VECTOR(7 downto 0);
wrReg3 : OUT STD_LOGIC_VECTOR(7 downto 0);
wrReg4 : OUT STD_LOGIC_VECTOR(7 downto 0);
wrReg5 : OUT STD_LOGIC_VECTOR(7 downto 0);
wrReg6 : OUT STD_LOGIC_VECTOR(7 downto 0);
wrReg7 : OUT STD_LOGIC_VECTOR(7 downto 0);
rdReg0 : IN STD_LOGIC_VECTOR(7 downto 0); -- Registers that get read over the SPI bus
rdReg1 : IN STD_LOGIC_VECTOR(7 downto 0);
rdReg2 : IN STD_LOGIC_VECTOR(7 downto 0);
rdReg3 : IN STD_LOGIC_VECTOR(7 downto 0);
rdReg4 : IN STD_LOGIC_VECTOR(7 downto 0);
rdReg5 : IN STD_LOGIC_VECTOR(7 downto 0);
rdReg6 : IN STD_LOGIC_VECTOR(7 downto 0);
rdReg7 : IN STD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
BEGIN
--internal oscillator
OSCInst0: OSCH
GENERIC MAP (NOM_FREQ => "53.20")
PORT MAP (STDBY => '0', OSC => clk, SEDSTDBY => OPEN);
PROCESS(clk)
VARIABLE count : INTEGER RANGE 0 TO 25_000_000;
BEGIN
IF(clk'EVENT AND clk = '1') THEN
-- Flash led1 so we know something is working
IF(count < 25_000_000) THEN
count := count + 1;
ELSE
count := 0;
led1 <= not led1;
END IF;
myRdReg0 <= myWrReg0;
myRdReg1 <= myWrReg1;
myRdReg2 <= myWrReg2;
myRdReg3 <= myWrReg3;
myRdReg4 <= myWrReg4;
myRdReg5 <= myWrReg5;
myRdReg6 <= myWrReg6;
myRdReg7(0) <= hex_switch_nb0;
myRdReg7(1) <= hex_switch_nb1;
myRdReg7(2) <= hex_switch_nb2;
myRdReg7(3) <= hex_switch_nb3;
led5 <= not myWrReg0(0);
led6 <= not myWrReg0(1);
led7 <= not myWrReg0(2);
led8 <= not myWrReg0(3);
END IF;
END PROCESS;
spi_port_1 : spi_port PORT MAP( clkin => clk, sclk => ft2232b_d0, sdi => ft2232b_d1, sdo => ft2232b_d2, cs => ft2232b_d3, wrReg0 => myWrReg0, wrReg1 => myWrReg1, wrReg2 => myWrReg2, wrReg3 => myWrReg3, wrReg4 => myWrReg4, wrReg5 => myWrReg5, wrReg6 => myWrReg6, wrReg7 => myWrReg7, rdReg0 => myRdReg0, rdReg1 => myRdReg1, rdReg2 => myRdReg2, rdReg3 => myRdReg3, rdReg4 => myRdReg4, rdReg5 => myRdReg5, rdReg6 => myRdReg6, rdReg7 => myRdReg7);
END behavior;
|
----------------------------------------------------------------------------------
-- Company: None
-- Engineer: <NAME>
--
-- Create Date: 18:17:00 08/05/2020 (dd/mm/yyyy)
-- Design Name: Signed Multiplier #2
-- Module Name: multiplier_1 - Behavioral
-- Project Name: ex_3.2
-- Target Devices: Basys 3
-- Tool versions: Vivado 2019.1
-- Description:
--
-- Dependencies:
--
--
-- Revision History:
-- 08/05/2020 v0.01 File created
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity multiplier_2s is
port (
-- input ports
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector (3 downto 0);
-- output ports
y : out std_logic_vector (7 downto 0)
);
end entity;
architecture arch of multiplier_2s is
begin
y <= a * b;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15.12.2016 19:00:34
-- Design Name:
-- Module Name: adc_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity adc_interface is
Generic (ADC_A_INV : std_logic_vector(7 downto 0) := x"00";
ADC_B_INV : std_logic_vector(7 downto 0) := x"00";
ADC_CLK_INV : std_logic := '0';
IODELAY_GROUP_NAME : string := "ADC_DESER_group"
);
Port ( clock_ref : in STD_LOGIC;
locked_dcmref : in STD_LOGIC;
SMADC_1_RESET : out STD_LOGIC;
sCLK_25 : in std_logic;
ADC_BUS_CLK_A_P : in STD_LOGIC;
ADC_BUS_CLK_A_N : in STD_LOGIC;
ADC_BUS_FRAME_A_P : in STD_LOGIC;
ADC_BUS_FRAME_A_N : in STD_LOGIC;
ADC_BUS_DATA_A_P: in STD_LOGIC_VECTOR(7 downto 0);
ADC_BUS_DATA_A_N: in STD_LOGIC_VECTOR(7 downto 0);
ADC_BUS_DATA_B_P: in STD_LOGIC_VECTOR(7 downto 0);
ADC_BUS_DATA_B_N: in STD_LOGIC_VECTOR(7 downto 0);
eDATA_OUT: out STD_LOGIC_VECTOR((14*8)-1 downto 0);
eEMPTY : out STD_LOGIC;
eCLK : in STD_LOGIC;
eREAD : in STD_LOGIC;
SMADC_CSA : out std_logic;
SMADC_CSB : out std_logic;
SMADC_CLK : out std_logic;
SMADC_MOSI : out std_logic
);
end adc_interface;
architecture Behavioral of adc_interface is
signal counter : std_logic_vector (26 downto 0);
signal clk : std_logic;
component ADC_REC_1
generic
(-- width of the data for the system
SYS_W : integer := 17;
-- width of the data for the device
DEV_W : integer := 238);
port
(
-- From the system into the device
data_in_from_pins_p : in std_logic_vector(SYS_W-1 downto 0);
data_in_from_pins_n : in std_logic_vector(SYS_W-1 downto 0);
data_in_to_device : out std_logic_vector(DEV_W-1 downto 0);
in_delay_reset : in std_logic;
in_delay_data_ce : in std_logic_vector(SYS_W-1 downto 0);
in_delay_data_inc : in std_logic_vector(SYS_W-1 downto 0);
in_delay_tap_in : in std_logic_vector((5*SYS_W)-1 downto 0);
in_delay_tap_out : out std_logic_vector((5*SYS_W)-1 downto 0);
delay_locked : out std_logic;
ref_clock : in std_logic;
bitslip : in std_logic_vector(SYS_W-1 downto 0); -- Bitslip module is enabled in NETWORKING mode
-- User should tie it to '0' if not needed
-- Clock and reset signals
clk_in_int : in std_logic; -- Differential fast clock from IOB
clk_div_out : out std_logic; -- Slow clock output
clk_reset : in std_logic; -- Reset signal for Clock circuit
io_reset : in std_logic); -- Reset signal for IO circuit
end component;
component adc_sync
Port (
clk : in std_logic;
start_delay : in std_logic;
bitsleep : out std_logic_vector(16 downto 0);
probe_data : in std_logic_vector (13 downto 0);
adc_frame : in std_logic_vector (13 downto 0);
serdes_delay : out std_logic_vector(7 downto 0);
serdes_dprog : out std_logic;
obit_locked : out std_logic;
initialized : out std_logic
);
end component;
component fifo_generator_0
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(223 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(111 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal data_in_to_device1 : std_logic_vector (237 downto 0) := (others => '0');
signal clk_div_out1 : std_logic :='0';
attribute keep : string;
signal ADC_F_0 : std_logic_vector (13 downto 0);
signal ADC_F_1 : std_logic_vector (13 downto 0);
signal ADC_A_0 : std_logic_vector (13 downto 0);
signal ADC_B_0 : std_logic_vector (13 downto 0);
signal ADC_A_1 : std_logic_vector (13 downto 0);
signal ADC_B_1 : std_logic_vector (13 downto 0);
signal ADC_A_2 : std_logic_vector (13 downto 0);
signal ADC_B_2 : std_logic_vector (13 downto 0);
signal ADC_A_3 : std_logic_vector (13 downto 0);
signal ADC_B_3 : std_logic_vector (13 downto 0);
signal ADC_A_4 : std_logic_vector (13 downto 0);
signal ADC_B_4 : std_logic_vector (13 downto 0);
signal ADC_A_5 : std_logic_vector (13 downto 0);
signal ADC_B_5 : std_logic_vector (13 downto 0);
signal ADC_A_6 : std_logic_vector (13 downto 0);
signal ADC_B_6 : std_logic_vector (13 downto 0);
signal ADC_A_7 : std_logic_vector (13 downto 0);
signal ADC_B_7 : std_logic_vector (13 downto 0);
signal DATA_A_0 : std_logic_vector (13 downto 0);
signal DATA_B_0 : std_logic_vector (13 downto 0);
signal DATA_A_1 : std_logic_vector (13 downto 0);
signal DATA_B_1 : std_logic_vector (13 downto 0);
signal DATA_A_2 : std_logic_vector (13 downto 0);
signal DATA_B_2 : std_logic_vector (13 downto 0);
signal DATA_A_3 : std_logic_vector (13 downto 0);
signal DATA_B_3 : std_logic_vector (13 downto 0);
signal DATA_A_4 : std_logic_vector (13 downto 0);
signal DATA_B_4 : std_logic_vector (13 downto 0);
signal DATA_A_5 : std_logic_vector (13 downto 0);
signal DATA_B_5 : std_logic_vector (13 downto 0);
signal DATA_A_6 : std_logic_vector (13 downto 0);
signal DATA_B_6 : std_logic_vector (13 downto 0);
signal DATA_A_7 : std_logic_vector (13 downto 0);
signal DATA_B_7 : std_logic_vector (13 downto 0);
attribute keep of ADC_F_0: signal is "true";
attribute keep of ADC_F_1: signal is "true";
attribute keep of ADC_A_0: signal is "true";
attribute keep of ADC_B_0: signal is "true";
attribute keep of ADC_A_1: signal is "true";
attribute keep of ADC_B_1: signal is "true";
attribute keep of ADC_A_2: signal is "true";
attribute keep of ADC_B_2: signal is "true";
attribute keep of ADC_A_3: signal is "true";
attribute keep of ADC_B_3: signal is "true";
attribute keep of ADC_A_4: signal is "true";
attribute keep of ADC_B_4: signal is "true";
attribute keep of ADC_A_5: signal is "true";
attribute keep of ADC_B_5: signal is "true";
attribute keep of ADC_A_6: signal is "true";
attribute keep of ADC_B_6: signal is "true";
attribute keep of ADC_A_7: signal is "true";
attribute keep of ADC_B_7: signal is "true";
attribute keep of DATA_A_0: signal is "true";
attribute keep of DATA_B_0: signal is "true";
attribute keep of DATA_A_1: signal is "true";
attribute keep of DATA_B_1: signal is "true";
attribute keep of DATA_A_2: signal is "true";
attribute keep of DATA_B_2: signal is "true";
attribute keep of DATA_A_3: signal is "true";
attribute keep of DATA_B_3: signal is "true";
attribute keep of DATA_A_4: signal is "true";
attribute keep of DATA_B_4: signal is "true";
attribute keep of DATA_A_5: signal is "true";
attribute keep of DATA_B_5: signal is "true";
attribute keep of DATA_A_6: signal is "true";
attribute keep of DATA_B_6: signal is "true";
attribute keep of DATA_A_7: signal is "true";
attribute keep of DATA_B_7: signal is "true";
signal SMADC_CS : std_logic := '1';
signal bitsleep1 : std_logic_vector(16 downto 0) := "00000000000000000";
signal start_delay : std_logic := '0';
signal reset_counter : integer :=0;
signal reset_sm : std_logic_vector(3 downto 0) := x"0";
signal reset_sm_d : std_logic_vector(3 downto 0) := x"0";
signal delay_rs : std_logic_vector(15 downto 0) := x"0000";
signal reset_clkref_dcm : std_logic := '0';
signal serdes_ioreset : std_logic := '0';
signal serdes_delayreset : std_logic := '0';
signal serdes_reset : std_logic := '0';
signal serdes1_program_delay : std_logic := '0';
signal serdes1_delaylock : std_logic := '0';
signal serdes1_delay : std_logic_vector( (5*17) -1 downto 0) := (others => '0');
signal serdes1_delay_temp : std_logic_vector( 7 downto 0) := (others => '0');
signal adc_programmed : std_logic := '0';
signal bit_locked1 : std_logic := '0';
signal initialized1 :std_logic := '0';
attribute keep of bit_locked1: signal is "true";
attribute keep of initialized1: signal is "true";
signal FIFO1_DIN : std_logic_vector(223 downto 0);
signal FIFO1_DOUT : std_logic_vector(111 downto 0);
signal FIFO1_empty : std_logic;
signal ADC_READY : STD_LOGIC;
attribute keep of ADC_READY: signal is "true";
signal ADC_BIT_CLOCK : std_logic;
signal ADC_BIT_CLOCKii : std_logic;
--attribute IODELAY_GROUP : STRING;
--attribute IODELAY_GROUP of IDELAYCTRL_inst: label is IODELAY_GROUP_NAME;
begin
ADC_OUTFIFO1: fifo_generator_0
PORT MAP(
rst => serdes_reset,
wr_clk => clk_div_out1,
rd_clk => eCLK,
din => FIFO1_DIN,
wr_en => '1',
rd_en => eREAD,
dout => FIFO1_DOUT,
full => open,
empty => FIFO1_empty
);
eDATA_OUT <= FIFO1_DOUT;
eEMPTY <= FIFO1_empty;
FIFO1_DIN <= DATA_B_7 & DATA_B_6 & DATA_B_5 & DATA_B_4 & DATA_B_3 & DATA_B_2 & DATA_B_1 & DATA_B_0 &
DATA_A_7 & DATA_A_6 & DATA_A_5 & DATA_A_4 & DATA_A_3 & DATA_A_2 & DATA_A_1 & DATA_A_0;
reset_process : process(sCLK_25)
begin
if rising_edge(sCLK_25) then
case reset_sm is
when x"0" =>
reset_clkref_dcm <= '1';
delay_rs <= x"000F";
reset_sm_d <= x"1";
reset_sm <= x"F";
when x"1" =>
reset_clkref_dcm <= '0';
if locked_dcmref = '1' and adc_programmed = '1' then
reset_sm <= x"2";
end if;
when x"2" =>
serdes_ioreset <= '1';
delay_rs <= x"000F";
reset_sm_d <= x"3";
reset_sm <= x"F";
when x"3" =>
serdes_ioreset <= '0';
delay_rs <= x"003F";
reset_sm_d <= x"4";
reset_sm <= x"F";
when x"4" =>
serdes_delayreset <= '1';
delay_rs <= x"000F";
reset_sm_d <= x"5";
reset_sm <= x"F";
when x"5" =>
serdes_delayreset <= '0';
delay_rs <= x"003F";
reset_sm_d <= x"6";
reset_sm <= x"F";
when x"6" =>
serdes_reset <= '1';
delay_rs <= x"000F";
reset_sm_d <= x"7";
reset_sm <= x"F";
when x"7" =>
serdes_reset <= '0';
delay_rs <= x"003F";
reset_sm_d <= x"8";
reset_sm <= x"F";
when x"8" =>
if serdes1_delaylock = '1' then
start_delay <= '1';
end if;
when x"F" =>
if delay_rs = x"0000" then
reset_sm <= reset_sm_d;
else
delay_rs <= delay_rs-1;
end if;
when others =>
reset_sm <= x"0";
end case;
end if;
end process;
clk <= sCLK_25;
SMADC_CSA <= SMADC_CS;
SMADC_CSB <= SMADC_CS;
aaprog: block
signal SMADC : std_logic_vector(3 downto 0) := x"0";
signal SMADCnew : std_logic_vector(3 downto 0) := x"0";
signal SMADCwordwrite : std_logic_vector(23 downto 0) := x"000000";
signal SMID : integer :=0;
signal idx : integer := 0;
signal SMdelay : std_logic_vector(15 downto 0);
signal ramp_counter : std_logic_vector(13 downto 0):= (others => '0');
signal ramp_next : std_logic;
signal delay_end : integer range 0 to 10000;
attribute keep of ramp_next: signal is "true";
attribute keep of ramp_counter: signal is "true";
begin
programmachine : process (clk)
begin
if rising_edge(clk) then
ramp_next <= '0';
case SMADC is
when x"0" =>
SMADC_CS <= '1';
SMADC_MOSI <= '1';
idx <= 0;
case SMID is
when 0 =>
ADC_READY <= '0';
SMADC <= x"F";
SMADCnew <= x"0";
SMdelay <= x"03FF";
SMID <= SMID +1;
SMADC_1_RESET <= '1';
when 1 =>
--SMADCwordwrite <= X"000001";
SMADC_1_RESET <= '0';
SMID <= SMID +1;
--SMADC <= x"1";
when 2 =>
SMADC <= x"F";
SMADCnew <= x"0";
SMdelay <= x"FFFF";
SMID <= SMID +1;
when 3 =>
SMADCwordwrite <= X"46A409";
SMID <= SMID +1;
SMADC <= x"1";
when 4 =>
SMADCwordwrite <= X"280000";
SMID <= SMID +1;
SMADC <= x"1";
when 5 =>
SMADCwordwrite <= X"450001";
SMID <= SMID +1;
SMADC <= x"1";
when 6 =>
adc_programmed <= '1';
if initialized1 = '1' then --and initialized2 = '1' then
delay_end <= 9000;
SMID <= 10;
end if;
when 7=>
--ramp_next <= '1';
--SMADCwordwrite <= X"03" & "10" & ramp_counter(13 downto 8);
--SMID <= SMID +1;
SMADCwordwrite <= X"250000"; --250040 per la rampa
SMID <= 9;
SMADC <= x"1";
when 8=>
--SMADCwordwrite <= X"04" & ramp_counter(7 downto 0);
SMID <= 7;
SMADC <= x"1";
ramp_counter <= ramp_counter +1;
when 9=>
when 10=>
if delay_end = 0 then
SMADCwordwrite <= X"450000";
-- SMID <= SMID +1;
SMID <= 7;
SMADC <= x"1";
else
delay_end <= delay_end -1;
end if;
when others =>
end case;
when x"1" =>
SMADC_CLK <= '0';
SMADC_CS <= '0';
SMADC <= x"F";
SMADCnew <= x"2";
SMdelay <= x"00FF";
when x"2" =>
SMADC_CLK <= '0';
SMADC_CS <= '0';
SMADC_MOSI <= SMADCwordwrite(23-idx);
idx <= idx +1;
SMdelay <= x"00FF";
SMADC <= x"F";
SMADCnew <= x"3";
when x"3" =>
SMADC_CLK <= '1';
SMdelay <= x"00FF";
SMADC <= x"F";
SMADCnew <= x"2";
if idx = 24 then
SMdelay <= x"00FF";
SMADC <= x"F";
SMADCnew <= x"A";
end if;
when x"A" =>
SMADC_CS <= '1';
SMdelay <= x"01FF";
SMADC <= x"F";
SMADCnew <= x"0";
when x"F" =>
if SMdelay = x"0000" then
SMADC <= SMADCnew;
else
SMdelay <= SMdelay-1;
end if;
when others =>
end case;
end if;
end process;
end block;
ADDESR: for I in 0 to 13 generate
begin
ADS1: process(clk_div_out1)
begin
if rising_edge(clk_div_out1) then
--frame
ADC_F_0(I) <= data_in_to_device1 ( (I * 17) + 0 );
--A 0
if ADC_B_INV(0) = '0' then
ADC_A_0(I) <= data_in_to_device1 ( (I * 17) + 1 );
else
ADC_A_0(I) <= not data_in_to_device1 ( (I * 17) + 1 );
end if;
--B 0
if ADC_A_INV(0) = '0' then
ADC_B_0(I) <= data_in_to_device1 ( (I * 17) + 2 );
else
ADC_B_0(I) <= not data_in_to_device1 ( (I * 17) + 2 );
end if;
--A 1
if ADC_B_INV(1) = '0' then
ADC_A_1(I) <= data_in_to_device1 ( (I * 17) + 3 );
else
ADC_A_1(I) <= not data_in_to_device1 ( (I * 17) + 3 );
end if;
--B 1
if ADC_A_INV(1) = '0' then
ADC_B_1(I) <= data_in_to_device1 ( (I * 17) + 4 );
else
ADC_B_1(I) <= not data_in_to_device1 ( (I * 17) + 4 );
end if;
--A 2
if ADC_B_INV(2) = '0' then
ADC_A_2(I) <= data_in_to_device1 ( (I * 17) + 5 );
else
ADC_A_2(I) <= not data_in_to_device1 ( (I * 17) + 5 );
end if;
--B 2
if ADC_A_INV(2) = '0' then
ADC_B_2(I) <= data_in_to_device1 ( (I * 17) + 6 );
else
ADC_B_2(I) <= not data_in_to_device1 ( (I * 17) + 6 );
end if;
--A 3
if ADC_B_INV(3) = '0' then
ADC_A_3(I) <= data_in_to_device1 ( (I * 17) + 7 );
else
ADC_A_3(I) <= not data_in_to_device1 ( (I * 17) + 7 );
end if;
--B 3
if ADC_A_INV(3) = '0' then
ADC_B_3(I) <= data_in_to_device1 ( (I * 17) + 8 );
else
ADC_B_3(I) <= not data_in_to_device1 ( (I * 17) + 8 );
end if;
--A 4
if ADC_B_INV(4) = '0' then
ADC_A_4(I) <= data_in_to_device1 ( (I * 17) + 9 );
else
ADC_A_4(I) <= not data_in_to_device1 ( (I * 17) + 9 );
end if;
--B 4
if ADC_A_INV(4) = '0' then
ADC_B_4(I) <= data_in_to_device1 ( (I * 17) + 10 );
else
ADC_B_4(I) <= not data_in_to_device1 ( (I * 17) + 10 );
end if;
--A 5
if ADC_B_INV(5) = '0' then
ADC_A_5(I) <= data_in_to_device1 ( (I * 17) + 11 );
else
ADC_A_5(I) <= not data_in_to_device1 ( (I * 17) + 11 );
end if;
--B 5
if ADC_A_INV(5) = '0' then
ADC_B_5(I) <= data_in_to_device1 ( (I * 17) + 12 );
else
ADC_B_5(I) <= not data_in_to_device1 ( (I * 17) + 12 );
end if;
--A 6
if ADC_B_INV(6) = '0' then
ADC_A_6(I) <= data_in_to_device1 ( (I * 17) + 13 );
else
ADC_A_6(I) <= not data_in_to_device1 ( (I * 17) + 13 );
end if;
--B 6
if ADC_A_INV(6) = '0' then
ADC_B_6(I) <= data_in_to_device1 ( (I * 17) + 14 );
else
ADC_B_6(I) <= not data_in_to_device1 ( (I * 17) + 14 );
end if;
--A 7
if ADC_B_INV(7) = '0' then
ADC_A_7(I) <= data_in_to_device1 ( (I * 17) + 15 );
else
ADC_A_7(I) <= not data_in_to_device1 ( (I * 17) + 15 );
end if;
--B 7
if ADC_A_INV(7) = '0' then
ADC_B_7(I) <= data_in_to_device1 ( (I * 17) + 16 );
else
ADC_B_7(I) <= not data_in_to_device1 ( (I * 17) + 16 );
end if;
end if;
end process;
end generate;
DATA_A_0 <= ADC_A_0(7) & ADC_A_0(8) & ADC_A_0(9) & ADC_A_0(10) & ADC_A_0(11) & ADC_A_0(12) & ADC_A_0(13) & ADC_B_0(7) & ADC_B_0(8) & ADC_B_0(9) & ADC_B_0(10) & ADC_B_0(11) & ADC_B_0(12) & ADC_B_0(13) ;
DATA_B_0 <= ADC_A_0(0) & ADC_A_0(1) & ADC_A_0(2) & ADC_A_0(3) & ADC_A_0(4) & ADC_A_0(5) & ADC_A_0(6) & ADC_B_0(0) & ADC_B_0(1) & ADC_B_0(2) & ADC_B_0(3) & ADC_B_0(4) & ADC_B_0(5) & ADC_B_0(6) ;
DATA_A_1 <= ADC_A_1(7) & ADC_A_1(8) & ADC_A_1(9) & ADC_A_1(10) & ADC_A_1(11) & ADC_A_1(12) & ADC_A_1(13) & ADC_B_1(7) & ADC_B_1(8) & ADC_B_1(9) & ADC_B_1(10) & ADC_B_1(11) & ADC_B_1(12) & ADC_B_1(13) ;
DATA_B_1 <= ADC_A_1(0) & ADC_A_1(1) & ADC_A_1(2) & ADC_A_1(3) & ADC_A_1(4) & ADC_A_1(5) & ADC_A_1(6) & ADC_B_1(0) & ADC_B_1(1) & ADC_B_1(2) & ADC_B_1(3) & ADC_B_1(4) & ADC_B_1(5) & ADC_B_1(6) ;
DATA_A_2 <= ADC_A_2(7) & ADC_A_2(8) & ADC_A_2(9) & ADC_A_2(10) & ADC_A_2(11) & ADC_A_2(12) & ADC_A_2(13) & ADC_B_2(7) & ADC_B_2(8) & ADC_B_2(9) & ADC_B_2(10) & ADC_B_2(11) & ADC_B_2(12) & ADC_B_2(13) ;
DATA_B_2 <= ADC_A_2(0) & ADC_A_2(1) & ADC_A_2(2) & ADC_A_2(3) & ADC_A_2(4) & ADC_A_2(5) & ADC_A_2(6) & ADC_B_2(0) & ADC_B_2(1) & ADC_B_2(2) & ADC_B_2(3) & ADC_B_2(4) & ADC_B_2(5) & ADC_B_2(6) ;
DATA_A_3 <= ADC_A_3(7) & ADC_A_3(8) & ADC_A_3(9) & ADC_A_3(10) & ADC_A_3(11) & ADC_A_3(12) & ADC_A_3(13) & ADC_B_3(7) & ADC_B_3(8) & ADC_B_3(9) & ADC_B_3(10) & ADC_B_3(11) & ADC_B_3(12) & ADC_B_3(13) ;
DATA_B_3 <= ADC_A_3(0) & ADC_A_3(1) & ADC_A_3(2) & ADC_A_3(3) & ADC_A_3(4) & ADC_A_3(5) & ADC_A_3(6) & ADC_B_3(0) & ADC_B_3(1) & ADC_B_3(2) & ADC_B_3(3) & ADC_B_3(4) & ADC_B_3(5) & ADC_B_3(6) ;
DATA_A_4 <= ADC_A_4(7) & ADC_A_4(8) & ADC_A_4(9) & ADC_A_4(10) & ADC_A_4(11) & ADC_A_4(12) & ADC_A_4(13) & ADC_B_4(7) & ADC_B_4(8) & ADC_B_4(9) & ADC_B_4(10) & ADC_B_4(11) & ADC_B_4(12) & ADC_B_4(13) ;
DATA_B_4 <= ADC_A_4(0) & ADC_A_4(1) & ADC_A_4(2) & ADC_A_4(3) & ADC_A_4(4) & ADC_A_4(5) & ADC_A_4(6) & ADC_B_4(0) & ADC_B_4(1) & ADC_B_4(2) & ADC_B_4(3) & ADC_B_4(4) & ADC_B_4(5) & ADC_B_4(6) ;
DATA_A_5 <= ADC_A_5(7) & ADC_A_5(8) & ADC_A_5(9) & ADC_A_5(10) & ADC_A_5(11) & ADC_A_5(12) & ADC_A_5(13) & ADC_B_5(7) & ADC_B_5(8) & ADC_B_5(9) & ADC_B_5(10) & ADC_B_5(11) & ADC_B_5(12) & ADC_B_5(13) ;
DATA_B_5 <= ADC_A_5(0) & ADC_A_5(1) & ADC_A_5(2) & ADC_A_5(3) & ADC_A_5(4) & ADC_A_5(5) & ADC_A_5(6) & ADC_B_5(0) & ADC_B_5(1) & ADC_B_5(2) & ADC_B_5(3) & ADC_B_5(4) & ADC_B_5(5) & ADC_B_5(6) ;
DATA_A_6 <= ADC_A_6(7) & ADC_A_6(8) & ADC_A_6(9) & ADC_A_6(10) & ADC_A_6(11) & ADC_A_6(12) & ADC_A_6(13) & ADC_B_6(7) & ADC_B_6(8) & ADC_B_6(9) & ADC_B_6(10) & ADC_B_6(11) & ADC_B_6(12) & ADC_B_6(13) ;
DATA_B_6 <= ADC_A_6(0) & ADC_A_6(1) & ADC_A_6(2) & ADC_A_6(3) & ADC_A_6(4) & ADC_A_6(5) & ADC_A_6(6) & ADC_B_6(0) & ADC_B_6(1) & ADC_B_6(2) & ADC_B_6(3) & ADC_B_6(4) & ADC_B_6(5) & ADC_B_6(6) ;
DATA_A_7 <= ADC_A_7(7) & ADC_A_7(8) & ADC_A_7(9) & ADC_A_7(10) & ADC_A_7(11) & ADC_A_7(12) & ADC_A_7(13) & ADC_B_7(7) & ADC_B_7(8) & ADC_B_7(9) & ADC_B_7(10) & ADC_B_7(11) & ADC_B_7(12) & ADC_B_7(13) ;
DATA_B_7 <= ADC_A_7(0) & ADC_A_7(1) & ADC_A_7(2) & ADC_A_7(3) & ADC_A_7(4) & ADC_A_7(5) & ADC_A_7(6) & ADC_B_7(0) & ADC_B_7(1) & ADC_B_7(2) & ADC_B_7(3) & ADC_B_7(4) & ADC_B_7(5) & ADC_B_7(6) ;
ADC_DESER1 : ADC_REC_1
port map
(
data_in_from_pins_p(0) => ADC_BUS_FRAME_A_P,
data_in_from_pins_p(1) => ADC_BUS_DATA_B_P(0), --1
data_in_from_pins_p(2) => ADC_BUS_DATA_A_P(0),
data_in_from_pins_p(3) => ADC_BUS_DATA_B_P(1), --4
data_in_from_pins_p(4) => ADC_BUS_DATA_A_P(1),
data_in_from_pins_p(5) => ADC_BUS_DATA_B_P(2), --5
data_in_from_pins_p(6) => ADC_BUS_DATA_A_P(2),
data_in_from_pins_p(7) => ADC_BUS_DATA_B_P(3), --8
data_in_from_pins_p(8) => ADC_BUS_DATA_A_P(3),
data_in_from_pins_p(9) => ADC_BUS_DATA_B_P(4),
data_in_from_pins_p(10) => ADC_BUS_DATA_A_P(4),
data_in_from_pins_p(11) => ADC_BUS_DATA_B_P(5),
data_in_from_pins_p(12) => ADC_BUS_DATA_A_P(5),
data_in_from_pins_p(13) => ADC_BUS_DATA_B_P(6),
data_in_from_pins_p(14) => ADC_BUS_DATA_A_P(6),
data_in_from_pins_p(15) => ADC_BUS_DATA_B_P(7),
data_in_from_pins_p(16) => ADC_BUS_DATA_A_P(7),
data_in_from_pins_n(0) => ADC_BUS_FRAME_A_N,
data_in_from_pins_n(1) => ADC_BUS_DATA_B_N(0),
data_in_from_pins_n(2) => ADC_BUS_DATA_A_N(0),
data_in_from_pins_n(3) => ADC_BUS_DATA_B_N(1),
data_in_from_pins_n(4) => ADC_BUS_DATA_A_N(1),
data_in_from_pins_n(5) => ADC_BUS_DATA_B_N(2),
data_in_from_pins_n(6) => ADC_BUS_DATA_A_N(2),
data_in_from_pins_n(7) => ADC_BUS_DATA_B_N(3),
data_in_from_pins_n(8) => ADC_BUS_DATA_A_N(3),
data_in_from_pins_n(9) => ADC_BUS_DATA_B_N(4),
data_in_from_pins_n(10) => ADC_BUS_DATA_A_N(4),
data_in_from_pins_n(11) => ADC_BUS_DATA_B_N(5),
data_in_from_pins_n(12) => ADC_BUS_DATA_A_N(5),
data_in_from_pins_n(13) => ADC_BUS_DATA_B_N(6),
data_in_from_pins_n(14) => ADC_BUS_DATA_A_N(6),
data_in_from_pins_n(15) => ADC_BUS_DATA_B_N(7),
data_in_from_pins_n(16) => ADC_BUS_DATA_A_N(7),
data_in_to_device => data_in_to_device1,
bitslip => bitsleep1,
clk_in_int => ADC_BIT_CLOCK,
clk_div_out => clk_div_out1,
clk_reset => serdes_ioreset,
io_reset => serdes_reset,
in_delay_reset => serdes1_program_delay,
in_delay_data_ce => "00000000000000000",
in_delay_data_inc => "00000000000000000",
in_delay_tap_in => serdes1_delay,
in_delay_tap_out => open,
delay_locked => serdes1_delaylock,
ref_clock => clock_ref
);
ADC_SYNC1: adc_sync
Port Map(
clk => clk_div_out1,
start_delay => start_delay,
bitsleep => bitsleep1,
probe_data => ADC_A_0,
adc_frame => ADC_F_0,
serdes_delay => serdes1_delay_temp,
serdes_dprog => serdes1_program_delay,
obit_locked => bit_locked1,
initialized => initialized1
);
serdes1_delay <= serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) &
serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) &
serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) &
serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) & serdes1_delay_temp(4 downto 0) &
serdes1_delay_temp(4 downto 0);
gen_clk_inv : if ADC_CLK_INV = '1' generate
begin
ADC_BIT_CLOCK <= not ADC_BIT_CLOCKii;
end generate;
gen_clk_notinv : if ADC_CLK_INV = '0' generate
begin
ADC_BIT_CLOCK <= ADC_BIT_CLOCKii;
end generate;
ADC_CLOCK_BUFFER : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "LVDS")
port map (
O => ADC_BIT_CLOCKii,
I => ADC_BUS_CLK_A_P,
IB => ADC_BUS_CLK_A_N
);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memoria_programa is
generic (
m : integer := 10;
n : integer := 25
);
Port ( pc : in STD_LOGIC_VECTOR (m-1 downto 0);
inst : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end entity;
architecture Behavioral of memoria_programa is
type arreglo is array (0 to (2**m - 1)) of STD_LOGIC_VECTOR (n-1 downto 0);
signal mem : arreglo := (others=>(others=>'0'));
constant code_LI : std_logic_vector (4 downto 0) := "00001";
constant code_ADD : std_logic_vector (4 downto 0) := "00000";
constant code_SWI : std_logic_vector (4 downto 0) := "00011";
constant code_ADDI : std_logic_vector (4 downto 0) := "00101";
constant code_BNEI : std_logic_vector (4 downto 0) := "01110";
constant code_NOP : std_logic_vector (4 downto 0) := "10110";
begin
mem(0) <= code_LI & "0000" & "000000000000" & "0000";
mem(1) <= code_LI & "0001" & "000000000000" & "0001";
mem(2) <= code_LI & "0010" & "000000000000" & "0000";
mem(3) <= code_LI & "0011" & "000000000000" & "1100";
mem(4) <= code_ADD & "0100" & "0000" & "0001" & "00000000";
mem(5) <= code_SWI & "0100" & "00000000" & "0111" & "0010";
mem(6) <= code_ADDI & "0000" & "0001" & "000000000000";
mem(7) <= code_ADDI & "0001" & "0100" & "000000000000";
mem(8) <= code_ADDI & "0010" & "0010" & "000000000001";
mem(9) <= code_BNEI & "0011" & "0010" & "111111111011";
mem(10) <= code_NOP & "00000000000000000000";
inst <= mem(conv_integer(pc));
end Behavioral;
|
architecture test of test2 is
constant foo : bar := baz;
begin end;
|
<gh_stars>1-10
-- Memory module to be synthesized as block RAM
-- can be initalized with a file
-- New "single process" version as recommended by Xilinx XST user guide
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library STD;
use STD.textio.all;
entity BootMem is
generic (RamFileName : string := "meminit.ram";
mode : string := "B";
ADDR_WIDTH: integer;
SIZE : integer;
Swapbytes : boolean; -- SWAP Bytes in RAM word in low byte first order to use data2mem
EnableSecondPort : boolean := true -- enable inference of the second port
);
Port ( A_DOUT : out STD_LOGIC_VECTOR (31 downto 0);
A_DIN : in STD_LOGIC_VECTOR (31 downto 0);
A_ADDR : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
A_EN : in STD_LOGIC;
A_WE : in STD_LOGIC_VECTOR (3 downto 0);
A_CLK : in STD_LOGIC;
-- Second Port ( read only)
B_CLK : in STD_LOGIC;
B_EN : in STD_LOGIC;
B_ADDR : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
B_DOUT : out STD_LOGIC_VECTOR (31 downto 0)
);
end BootMem;
architecture Behavioral of BootMem is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "TRUE";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of A_CLK : SIGNAL is "xilinx.com:signal:clock:1.0 A_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO of B_CLK : SIGNAL is "xilinx.com:signal:clock:1.0 B_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF A_EN : SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_A EN";
ATTRIBUTE X_INTERFACE_INFO OF A_DOUT: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_A DOUT";
ATTRIBUTE X_INTERFACE_INFO OF A_DIN: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_A DIN";
ATTRIBUTE X_INTERFACE_INFO OF A_WE: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_A WE";
ATTRIBUTE X_INTERFACE_INFO OF A_ADDR: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_A ADDR";
ATTRIBUTE X_INTERFACE_INFO OF B_EN : SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_B EN";
ATTRIBUTE X_INTERFACE_INFO OF B_DOUT : SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_B DOUT";
ATTRIBUTE X_INTERFACE_INFO OF B_ADDR : SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_B ADDR";
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER of A_CLK : SIGNAL is "ASSOCIATED_BUSIF BRAM_A";
ATTRIBUTE X_INTERFACE_PARAMETER of B_CLK : SIGNAL is "ASSOCIATED_BUSIF BRAM_B";
type tRam is array (0 to SIZE-1) of STD_LOGIC_VECTOR (31 downto 0);
subtype tWord is std_logic_vector(31 downto 0);
signal DOA,DOB,DIA : tWord;
signal WEA : STD_LOGIC_VECTOR (3 downto 0);
function doSwapBytes(d : tWord) return tWord is
begin
return d(7 downto 0)&d(15 downto 8)&d(23 downto 16)&d(31 downto 24);
end;
-- Design time code...
-- Initalizes block RAM form memory file
-- The file does either contain hex values (mode = 'H') or binary values
impure function InitFromFile return tRam is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable word : tWord;
variable r : tRam;
begin
for I in tRam'range loop
if not endfile(RamFile) then
readline (RamFile, RamFileLine);
if mode="H" then
hread (RamFileLine, word); -- alternative: HEX read
else
read(RamFileLine,word); -- Binary read
end if;
if SwapBytes then
r(I) := DoSwapBytes(word);
else
r(I) := word;
end if;
else
r(I) := (others=>'0');
end if;
end loop;
return r;
end function;
signal ram : tRam := InitFromFile;
attribute ram_style: string; -- for Xilinx
attribute ram_style of ram: signal is "block";
-- helper component
---- for byte swapping
--COMPONENT byte_swapper
-- PORT(
-- din : IN std_logic_vector(31 downto 0);
-- dout : OUT std_logic_vector(31 downto 0)
-- );
-- END COMPONENT;
begin
swap: if SwapBytes generate
-- The Data input bus is swapped with the helper component to avoid
-- confusing the xilinx synthesis tools which sometimes infer distributed
-- instead of block RAM
-- It is important that the byte swapper component has set the keep_hierarchy attribute to TRUE
-- this will make the byte swap of the input bus invisble for the RAM inference
-- bs: byte_swapper PORT MAP(
-- din => A_DIN,
-- dout => DIA
-- );
DIA<=DoSwapBytes(A_DIN);
A_DOUT<=DoSwapBytes(DOA);
B_DOUT<=DoSwapBytes(DOB);
WEA(0)<=A_WE(3);
WEA(1)<=A_WE(2);
WEA(2)<=A_WE(1);
WEA(3)<=A_WE(0);
end generate;
noswap: if not SwapBytes generate
DIA<=A_DIN;
A_DOUT<=DOA;
B_DOUT<=DOB;
WEA<=A_WE;
end generate;
process(A_CLK)
variable adr : integer;
begin
if rising_edge(A_CLK) then
if A_EN = '1' then
adr := to_integer(unsigned(A_ADDR));
for i in 0 to 3 loop
if WEA(i) = '1' then
ram(adr)((i+1)*8-1 downto i*8)<= DIA((i+1)*8-1 downto i*8);
end if;
end loop;
DOA <= ram(adr);
end if;
end if;
end process;
portb: if EnableSecondPort generate
process(B_CLK) begin
if rising_edge(B_CLK) then
if B_EN='1' then
DOB <= ram(to_integer(unsigned(B_ADDR)));
end if;
end if;
end process;
end generate;
end Behavioral;
|
-- ----------------------------------------------------------------------------
-- FILE: DDR3_avmm_2x32_ctrl.vhd
-- DESCRIPTION: describe
-- DATE: June 13, 2016
-- AUTHOR(s): <NAME>
-- REVISIONS:
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity DDR3_avmm_2x32_ctrl is
generic(
dev_family : string := "Cyclone V GX";
cntrl_rate : integer := 1; --1 - full rate, 2 - half rate
cntrl_addr_size : integer := 14;
cntrl_ba_size : integer := 3;
cntrl_bus_size : integer := 32;
--multiport front end parameters
mpfe_0_addr_size : integer := 27;
mpfe_0_bus_size : integer := 32;
mpfe_0_burst_length : integer := 2;
mpfe_1_addr_size : integer := 26;
mpfe_1_bus_size : integer := 64;
mpfe_1_burst_length : integer := 2;
-- addr_size : integer := 27;
-- lcl_bus_size : integer := 32;
-- lcl_burst_length : integer := 2;
cmd_fifo_size : integer := 9;
outfifo_size_0 : integer := 10; -- outfifo buffer size
outfifo_size_1 : integer := 10 -- outfifo buffer size
);
port (
pll_ref_clk : in std_logic;
global_reset_n : in std_logic;
soft_reset_n : in std_logic;
--Port 0
wcmd_clk_0 : in std_logic;
wcmd_reset_n_0 : in std_logic;
wcmd_rdy_0 : out std_logic;
wcmd_addr_0 : in std_logic_vector(mpfe_0_addr_size-1 downto 0);
wcmd_wr_0 : in std_logic;
wcmd_brst_en_0 : in std_logic; --1- writes in burst, 0- single write
wcmd_data_0 : in std_logic_vector(mpfe_0_bus_size-1 downto 0);
rcmd_clk_0 : in std_logic;
rcmd_reset_n_0 : in std_logic;
rcmd_rdy_0 : out std_logic;
rcmd_addr_0 : in std_logic_vector(mpfe_0_addr_size-1 downto 0);
rcmd_wr_0 : in std_logic;
rcmd_brst_en_0 : in std_logic; --1- reads in burst, 0- single read
outbuf_wrusedw_0 : in std_logic_vector(outfifo_size_0-1 downto 0);
local_ready_0 : out std_logic;
local_rdata_0 : out std_logic_vector(mpfe_0_bus_size-1 downto 0);
local_rdata_valid_0 : out std_logic;
--Port 1
wcmd_clk_1 : in std_logic;
wcmd_reset_n_1 : in std_logic;
wcmd_rdy_1 : out std_logic;
wcmd_addr_1 : in std_logic_vector(mpfe_1_addr_size-1 downto 0);
wcmd_wr_1 : in std_logic;
wcmd_brst_en_1 : in std_logic; --1- writes in burst, 0- single write
wcmd_data_1 : in std_logic_vector(mpfe_1_bus_size-1 downto 0);
rcmd_clk_1 : in std_logic;
rcmd_reset_n_1 : in std_logic;
rcmd_rdy_1 : out std_logic;
rcmd_addr_1 : in std_logic_vector(mpfe_1_addr_size-1 downto 0);
rcmd_wr_1 : in std_logic;
rcmd_brst_en_1 : in std_logic; --1- reads in burst, 0- single read
outbuf_wrusedw_1 : in std_logic_vector(outfifo_size_0-1 downto 0);
local_ready_1 : out std_logic;
local_rdata_1 : out std_logic_vector(mpfe_1_bus_size-1 downto 0);
local_rdata_valid_1 : out std_logic;
local_init_done : out std_logic;
--External memory signals
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_reset_n : out std_logic; -- .mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0);
phy_clk : out std_logic;
oct_rzqin : in std_logic := '0'; -- oct.rzqin
--aux_full_rate_clk : out std_logic;
--aux_half_rate_clk : out std_logic;
--reset_request_n : out std_logic;
begin_test : in std_logic;
insert_error : in std_logic;
pnf_per_bit : out std_logic_vector(31 downto 0);
pnf_per_bit_persist : out std_logic_vector(31 downto 0);
pass : out std_logic;
fail : out std_logic;
test_complete : out std_logic
);
end DDR3_avmm_2x32_ctrl;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture arch of DDR3_avmm_2x32_ctrl is
--declare signals, components here
--inst0 signals
signal inst0_local_addr : std_logic_vector(mpfe_0_addr_size-1 downto 0);
signal inst0_local_write_req : std_logic;
signal inst0_local_read_req : std_logic;
signal inst0_local_burstbegin : std_logic;
signal inst0_local_wdata : std_logic_vector(mpfe_0_bus_size-1 downto 0);
signal inst0_local_be : std_logic_vector(mpfe_0_bus_size/8*cntrl_rate-1 downto 0);
signal inst0_local_size : std_logic_vector(1 downto 0);
--inst1 signals
signal inst1_local_addr : std_logic_vector(mpfe_1_addr_size-1 downto 0);
signal inst1_local_write_req : std_logic;
signal inst1_local_read_req : std_logic;
signal inst1_local_burstbegin : std_logic;
signal inst1_local_wdata : std_logic_vector(mpfe_1_bus_size-1 downto 0);
signal inst1_local_be : std_logic_vector(mpfe_1_bus_size/8*cntrl_rate-1 downto 0);
signal inst1_local_size : std_logic_vector(1 downto 0);
--inst2 signals
signal inst2_avl_addr : std_logic_vector(mpfe_0_addr_size-1 downto 0);
signal inst2_avl_write_req : std_logic;
signal inst2_avl_read_req : std_logic;
signal inst2_avl_burstbegin : std_logic;
signal inst2_avl_wdata : std_logic_vector(mpfe_0_bus_size-1 downto 0);
signal inst2_avl_be : std_logic_vector(mpfe_0_bus_size/8*cntrl_rate-1 downto 0);
signal inst2_avl_size : std_logic_vector(1 downto 0);
signal begin_test_port0 : std_logic;
signal inst2_pnf_per_bit : std_logic_vector(mpfe_0_bus_size-1 downto 0);
signal inst2_pnf_per_bit_persist : std_logic_vector(mpfe_0_bus_size-1 downto 0);
signal inst2_pass : std_logic;
signal inst2_fail : std_logic;
signal inst2_test_complete : std_logic;
--inst3 signals
signal inst3_avl_addr : std_logic_vector(mpfe_1_addr_size-1 downto 0);
signal inst3_avl_write_req : std_logic;
signal inst3_avl_read_req : std_logic;
signal inst3_avl_burstbegin : std_logic;
signal inst3_avl_wdata : std_logic_vector(mpfe_1_bus_size-1 downto 0);
signal inst3_avl_be : std_logic_vector(mpfe_1_bus_size/8*cntrl_rate-1 downto 0);
signal inst3_avl_size : std_logic_vector(1 downto 0);
signal begin_test_port1 : std_logic;
signal inst3_pnf_per_bit : std_logic_vector(mpfe_1_bus_size-1 downto 0);
signal inst3_pnf_per_bit_persist : std_logic_vector(mpfe_1_bus_size-1 downto 0);
signal inst3_pass : std_logic;
signal inst3_fail : std_logic;
signal inst3_test_complete : std_logic;
--Avalon signal mux port 0
signal mux_avl_addr_0 : std_logic_vector(mpfe_0_addr_size-1 downto 0);
signal mux_avl_write_req_0 : std_logic;
signal mux_avl_read_req_0 : std_logic;
signal mux_avl_burstbegin_0 : std_logic;
signal mux_avl_wdata_0 : std_logic_vector(mpfe_0_bus_size-1 downto 0);
signal mux_avl_be_0 : std_logic_vector(mpfe_0_bus_size/8*cntrl_rate-1 downto 0);
signal mux_avl_size_0 : std_logic_vector(1 downto 0);
--Avalon signal mux port 1
signal mux_avl_addr_1 : std_logic_vector(mpfe_1_addr_size-1 downto 0);
signal mux_avl_write_req_1 : std_logic;
signal mux_avl_read_req_1 : std_logic;
signal mux_avl_burstbegin_1 : std_logic;
signal mux_avl_wdata_1 : std_logic_vector(mpfe_1_bus_size-1 downto 0);
signal mux_avl_be_1 : std_logic_vector(mpfe_1_bus_size/8*cntrl_rate-1 downto 0);
signal mux_avl_size_1 : std_logic_vector(1 downto 0);
--DDR3 controller instance inst4 signals
signal inst4_afi_half_clk : std_logic;
signal inst4_avl_ready_0 : std_logic;
signal inst4_avl_rdata_valid_0 : std_logic;
signal inst4_avl_rdata_0 : std_logic_vector(mpfe_0_bus_size-1 downto 0);
signal inst4_avl_ready_1 : std_logic;
signal inst4_avl_rdata_valid_1 : std_logic;
signal inst4_avl_rdata_1 : std_logic_vector(mpfe_1_bus_size-1 downto 0);
signal mp_cmd_clk_0_clk : std_logic;
signal mp_cmd_reset_n_0_reset_n : std_logic;
signal mp_cmd_clk_1_clk : std_logic;
signal mp_cmd_reset_n_1_reset_n : std_logic;
signal mp_rfifo_clk_0_clk : std_logic;
signal mp_rfifo_reset_n_0_reset_n : std_logic;
signal mp_wfifo_clk_0_clk : std_logic;
signal mp_wfifo_reset_n_0_reset_n : std_logic;
signal mp_rfifo_clk_1_clk : std_logic;
signal mp_rfifo_reset_n_1_reset_n : std_logic;
signal mp_wfifo_clk_1_clk : std_logic;
signal mp_wfifo_reset_n_1_reset_n : std_logic;
signal inst4_local_init_done : std_logic;
signal inst4_local_cal_success : std_logic;
signal inst4_local_cal_fail : std_logic;
signal inst4_pll_locked : std_logic;
signal inst4_soft_reset_n : std_logic;
component avmm_arb_top is
generic(
dev_family : string := "Cyclone V GX";
cntrl_rate : integer := 1; --1 - full rate, 2 - half rate
cntrl_bus_size : integer := 16;
addr_size : integer := 24;
lcl_bus_size : integer := 63;
lcl_burst_length : integer := 2;
cmd_fifo_size : integer := 9;
outfifo_size : integer :=10 -- outfifo buffer size
);
port (
clk : in std_logic;
reset_n : in std_logic;
--Write command ports
wcmd_clk : in std_logic;
wcmd_reset_n : in std_logic;
wcmd_rdy : out std_logic;
wcmd_addr : in std_logic_vector(addr_size-1 downto 0);
wcmd_wr : in std_logic;
wcmd_brst_en : in std_logic; --1- writes in burst, 0- single write
wcmd_data : in std_logic_vector(lcl_bus_size-1 downto 0);
--rd command ports
rcmd_clk : in std_logic;
rcmd_reset_n : in std_logic;
rcmd_rdy : out std_logic;
rcmd_addr : in std_logic_vector(addr_size-1 downto 0);
rcmd_wr : in std_logic;
rcmd_brst_en : in std_logic; --1- reads in burst, 0- single read
outbuf_wrusedw : in std_logic_vector(outfifo_size-1 downto 0);
local_ready : in std_logic;
local_addr : out std_logic_vector(addr_size-1 downto 0);
local_write_req : out std_logic;
local_read_req : out std_logic;
local_burstbegin : out std_logic;
local_wdata : out std_logic_vector(lcl_bus_size-1 downto 0);
local_be : out std_logic_vector(lcl_bus_size/8*cntrl_rate-1 downto 0);
local_size : out std_logic_vector(1 downto 0)
);
end component;
component ddr3_av_2x32_tester is
port (
avl_ready : in std_logic := '0'; -- avl.waitrequest_n
avl_addr : out std_logic_vector(26 downto 0); -- .address
avl_size : out std_logic_vector(1 downto 0); -- .burstcount
avl_wdata : out std_logic_vector(31 downto 0); -- .writedata
avl_rdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
avl_write_req : out std_logic; -- .write
avl_read_req : out std_logic; -- .read
avl_rdata_valid : in std_logic := '0'; -- .readdatavalid
avl_be : out std_logic_vector(3 downto 0); -- .byteenable
avl_burstbegin : out std_logic; -- .beginbursttransfer
clk : in std_logic := '0'; -- avl_clock.clk
reset_n : in std_logic := '0'; -- avl_reset.reset_n
pnf_per_bit : out std_logic_vector(31 downto 0); -- pnf.pnf_per_bit
pnf_per_bit_persist : out std_logic_vector(31 downto 0); -- .pnf_per_bit_persist
pass : out std_logic; -- status.pass
fail : out std_logic; -- .fail
test_complete : out std_logic -- .test_complete
);
end component;
component ddr3_av_x64_tester is
port (
avl_ready : in std_logic := '0'; -- avl.waitrequest_n
avl_addr : out std_logic_vector(25 downto 0); -- .address
avl_size : out std_logic_vector(1 downto 0); -- .burstcount
avl_wdata : out std_logic_vector(63 downto 0); -- .writedata
avl_rdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .readdata
avl_write_req : out std_logic; -- .write
avl_read_req : out std_logic; -- .read
avl_rdata_valid : in std_logic := '0'; -- .readdatavalid
avl_be : out std_logic_vector(7 downto 0); -- .byteenable
avl_burstbegin : out std_logic; -- .beginbursttransfer
clk : in std_logic := '0'; -- avl_clock.clk
reset_n : in std_logic := '0'; -- avl_reset.reset_n
pnf_per_bit : out std_logic_vector(63 downto 0); -- pnf.pnf_per_bit
pnf_per_bit_persist : out std_logic_vector(63 downto 0); -- .pnf_per_bit_persist
pass : out std_logic; -- status.pass
fail : out std_logic; -- .fail
test_complete : out std_logic -- .test_complete
);
end component;
component ddr3_av_2x32 is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_reset_n : out std_logic; -- .mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready_0 : out std_logic; -- avl_0.waitrequest_n
avl_burstbegin_0 : in std_logic := '0'; -- .beginbursttransfer
avl_addr_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avl_rdata_valid_0 : out std_logic; -- .readdatavalid
avl_rdata_0 : out std_logic_vector(63 downto 0); -- .readdata
avl_wdata_0 : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata
avl_be_0 : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable
avl_read_req_0 : in std_logic := '0'; -- .read
avl_write_req_0 : in std_logic := '0'; -- .write
avl_size_0 : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
avl_ready_1 : out std_logic; -- avl_1.waitrequest_n
avl_burstbegin_1 : in std_logic := '0'; -- .beginbursttransfer
avl_addr_1 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avl_rdata_valid_1 : out std_logic; -- .readdatavalid
avl_rdata_1 : out std_logic_vector(63 downto 0); -- .readdata
avl_wdata_1 : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata
avl_be_1 : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable
avl_read_req_1 : in std_logic := '0'; -- .read
avl_write_req_1 : in std_logic := '0'; -- .write
avl_size_1 : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
mp_cmd_clk_0_clk : in std_logic := '0'; -- mp_cmd_clk_0.clk
mp_cmd_reset_n_0_reset_n : in std_logic := '0'; -- mp_cmd_reset_n_0.reset_n
mp_cmd_clk_1_clk : in std_logic := '0'; -- mp_cmd_clk_1.clk
mp_cmd_reset_n_1_reset_n : in std_logic := '0'; -- mp_cmd_reset_n_1.reset_n
mp_rfifo_clk_0_clk : in std_logic := '0'; -- mp_rfifo_clk_0.clk
mp_rfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_rfifo_reset_n_0.reset_n
mp_wfifo_clk_0_clk : in std_logic := '0'; -- mp_wfifo_clk_0.clk
mp_wfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_wfifo_reset_n_0.reset_n
mp_rfifo_clk_1_clk : in std_logic := '0'; -- mp_rfifo_clk_1.clk
mp_rfifo_reset_n_1_reset_n : in std_logic := '0'; -- mp_rfifo_reset_n_1.reset_n
mp_wfifo_clk_1_clk : in std_logic := '0'; -- mp_wfifo_clk_1.clk
mp_wfifo_reset_n_1_reset_n : in std_logic := '0'; -- mp_wfifo_reset_n_1.reset_n
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rzqin : in std_logic := '0'; -- oct.rzqin
pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
pll_write_clk : out std_logic; -- .pll_write_clk
pll_locked : out std_logic; -- .pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- .pll_avl_clk
pll_config_clk : out std_logic; -- .pll_config_clk
pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk
afi_phy_clk : out std_logic; -- .afi_phy_clk
pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk
);
end component;
begin
-- ----------------------------------------------------------------------------
-- Arbiter for memory port 0
-- ----------------------------------------------------------------------------
avmm_arb_top_inst0 : avmm_arb_top
generic map(
dev_family => dev_family,
cntrl_rate => cntrl_rate,
cntrl_bus_size => cntrl_bus_size,
addr_size => mpfe_0_addr_size,
lcl_bus_size => mpfe_0_bus_size,
lcl_burst_length => mpfe_0_burst_length,
cmd_fifo_size => cmd_fifo_size,
outfifo_size => outfifo_size_0
)
port map (
clk => inst4_afi_half_clk,
reset_n => inst4_local_init_done,
--Write command ports
wcmd_clk => wcmd_clk_0,
wcmd_reset_n => wcmd_reset_n_0,
wcmd_rdy => wcmd_rdy_0,
wcmd_addr => wcmd_addr_0,
wcmd_wr => wcmd_wr_0,
wcmd_brst_en => wcmd_brst_en_0,
wcmd_data => wcmd_data_0,
--rd command ports
rcmd_clk => rcmd_clk_0,
rcmd_reset_n => rcmd_reset_n_0,
rcmd_rdy => rcmd_rdy_0,
rcmd_addr => rcmd_addr_0,
rcmd_wr => rcmd_wr_0,
rcmd_brst_en => rcmd_brst_en_0,
outbuf_wrusedw => outbuf_wrusedw_0,
local_ready => inst4_avl_ready_0,
local_addr => inst0_local_addr,
local_write_req => inst0_local_write_req,
local_read_req => inst0_local_read_req,
local_burstbegin => inst0_local_burstbegin,
local_wdata => inst0_local_wdata,
local_be => inst0_local_be,
local_size => inst0_local_size
);
-- ----------------------------------------------------------------------------
-- Arbiter for memory port 1
-- ----------------------------------------------------------------------------
avmm_arb_top_inst1 : avmm_arb_top
generic map(
dev_family => dev_family,
cntrl_rate => cntrl_rate,
cntrl_bus_size => cntrl_bus_size,
addr_size => mpfe_1_addr_size,
lcl_bus_size => mpfe_1_bus_size,
lcl_burst_length => mpfe_1_burst_length,
cmd_fifo_size => cmd_fifo_size,
outfifo_size => outfifo_size_1
)
port map (
clk => inst4_afi_half_clk,
reset_n => inst4_local_init_done,
--Write command ports
wcmd_clk => wcmd_clk_1,
wcmd_reset_n => wcmd_reset_n_1,
wcmd_rdy => wcmd_rdy_1,
wcmd_addr => wcmd_addr_1,
wcmd_wr => wcmd_wr_1,
wcmd_brst_en => wcmd_brst_en_1,
wcmd_data => wcmd_data_1,
--rd command ports
rcmd_clk => rcmd_clk_1,
rcmd_reset_n => rcmd_reset_n_1,
rcmd_rdy => rcmd_rdy_1,
rcmd_addr => rcmd_addr_1,
rcmd_wr => rcmd_wr_1,
rcmd_brst_en => rcmd_brst_en_1,
outbuf_wrusedw => outbuf_wrusedw_1,
local_ready => inst4_avl_ready_1,
local_addr => inst1_local_addr,
local_write_req => inst1_local_write_req,
local_read_req => inst1_local_read_req,
local_burstbegin => inst1_local_burstbegin,
local_wdata => inst1_local_wdata,
local_be => inst1_local_be,
local_size => inst1_local_size
);
-- ----------------------------------------------------------------------------
-- Port 0 tester
-- ----------------------------------------------------------------------------
ddr3_av_2x32_tester_inst2 : ddr3_av_x64_tester
port map (
avl_ready => inst4_avl_ready_0,
avl_addr => inst2_avl_addr,
avl_size => inst2_avl_size,
avl_wdata => inst2_avl_wdata,
avl_rdata => inst4_avl_rdata_0,
avl_write_req => inst2_avl_write_req,
avl_read_req => inst2_avl_read_req,
avl_rdata_valid => inst4_avl_rdata_valid_0,
avl_be => inst2_avl_be,
avl_burstbegin => inst2_avl_burstbegin,
clk => inst4_afi_half_clk,
reset_n => begin_test_port0,
pnf_per_bit => inst2_pnf_per_bit,
pnf_per_bit_persist => inst2_pnf_per_bit_persist,
pass => inst2_pass,
fail => inst2_fail,
test_complete => inst2_test_complete
);
begin_test_port0<= inst4_local_init_done and begin_test;
-- ----------------------------------------------------------------------------
-- Port 1 tester
-- ----------------------------------------------------------------------------
ddr3_av_x64_tester_inst3 : ddr3_av_x64_tester
port map (
avl_ready => inst4_avl_ready_1,
avl_addr => inst3_avl_addr,
avl_size => inst3_avl_size,
avl_wdata => inst3_avl_wdata,
avl_rdata => inst4_avl_rdata_1,
avl_write_req => inst3_avl_write_req,
avl_read_req => inst3_avl_read_req,
avl_rdata_valid => inst4_avl_rdata_valid_1,
avl_be => inst3_avl_be,
avl_burstbegin => inst3_avl_burstbegin,
clk => inst4_afi_half_clk,
reset_n => begin_test_port1,
pnf_per_bit => inst3_pnf_per_bit,
pnf_per_bit_persist => inst3_pnf_per_bit_persist,
pass => inst3_pass,
fail => inst3_fail,
test_complete => inst3_test_complete
);
begin_test_port1 <= begin_test_port0 and inst2_test_complete;
mux_avl_addr_0 <= inst0_local_addr when begin_test='0' else inst2_avl_addr;
mux_avl_write_req_0 <= inst0_local_write_req when begin_test='0' else inst2_avl_write_req;
mux_avl_read_req_0 <= inst0_local_read_req when begin_test='0' else inst2_avl_read_req;
mux_avl_burstbegin_0 <= inst0_local_burstbegin when begin_test='0' else inst2_avl_burstbegin;
mux_avl_wdata_0 <= inst0_local_wdata when begin_test='0' else inst2_avl_wdata;
mux_avl_be_0 <= inst0_local_be when begin_test='0' else inst2_avl_be;
mux_avl_size_0 <= inst0_local_size when begin_test='0' else inst2_avl_size;
mux_avl_addr_1 <= inst1_local_addr when begin_test='0' else inst3_avl_addr;
mux_avl_write_req_1 <= inst1_local_write_req when begin_test='0' else inst3_avl_write_req;
mux_avl_read_req_1 <= inst1_local_read_req when begin_test='0' else inst3_avl_read_req;
mux_avl_burstbegin_1 <= inst1_local_burstbegin when begin_test='0' else inst3_avl_burstbegin;
mux_avl_wdata_1 <= inst1_local_wdata when begin_test='0' else inst3_avl_wdata;
mux_avl_be_1 <= inst1_local_be when begin_test='0' else inst3_avl_be;
mux_avl_size_1 <= inst1_local_size when begin_test='0' else inst3_avl_size;
inst4_soft_reset_n <= inst4_pll_locked AND soft_reset_n;
ddr3_av_2x32_inst4: component ddr3_av_2x32
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => inst4_soft_reset_n, -- soft_reset.reset_n
afi_clk => open, -- afi_clk, -- afi_clk.clk
afi_half_clk => inst4_afi_half_clk, -- afi_half_clk.clk
afi_reset_n => open, --afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => open, --afi_reset_export_n, -- afi_reset_export.reset_n
mem_a => mem_a, -- memory.mem_a
mem_ba => mem_ba, -- .mem_ba
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_ras_n => mem_ras_n, -- .mem_ras_n
mem_cas_n => mem_cas_n, -- .mem_cas_n
mem_we_n => mem_we_n, -- .mem_we_n
mem_reset_n => mem_reset_n, -- .mem_reset_n
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
mem_odt => mem_odt, -- .mem_odt
avl_ready_0 => inst4_avl_ready_0, -- avl_0.waitrequest_n
avl_burstbegin_0 => mux_avl_burstbegin_0, -- .beginbursttransfer
avl_addr_0 => mux_avl_addr_0, -- .address
avl_rdata_valid_0 => inst4_avl_rdata_valid_0, -- .readdatavalid
avl_rdata_0 => inst4_avl_rdata_0, -- .readdata
avl_wdata_0 => mux_avl_wdata_0, -- .writedata
avl_be_0 => mux_avl_be_0, -- .byteenable
avl_read_req_0 => mux_avl_read_req_0, -- .read
avl_write_req_0 => mux_avl_write_req_0, -- .write
avl_size_0 => mux_avl_size_0, -- .burstcount
avl_ready_1 => inst4_avl_ready_1, -- avl_1.waitrequest_n
avl_burstbegin_1 => mux_avl_burstbegin_1, -- .beginbursttransfer
avl_addr_1 => mux_avl_addr_1, -- .address
avl_rdata_valid_1 => inst4_avl_rdata_valid_1, -- .readdatavalid
avl_rdata_1 => inst4_avl_rdata_1, -- .readdata
avl_wdata_1 => mux_avl_wdata_1, -- .writedata
avl_be_1 => mux_avl_be_1, -- .byteenable
avl_read_req_1 => mux_avl_read_req_1, -- .read
avl_write_req_1 => mux_avl_write_req_1, -- .write
avl_size_1 => mux_avl_size_1, -- .burstcount
mp_cmd_clk_0_clk => mp_cmd_clk_0_clk, -- mp_cmd_clk_0.clk
mp_cmd_reset_n_0_reset_n => mp_cmd_reset_n_0_reset_n, -- mp_cmd_reset_n_0.reset_n
mp_cmd_clk_1_clk => mp_cmd_clk_1_clk, -- mp_cmd_clk_1.clk
mp_cmd_reset_n_1_reset_n => mp_cmd_reset_n_1_reset_n, -- mp_cmd_reset_n_1.reset_n
mp_rfifo_clk_0_clk => mp_rfifo_clk_0_clk, -- mp_rfifo_clk_0.clk
mp_rfifo_reset_n_0_reset_n => mp_rfifo_reset_n_0_reset_n, -- mp_rfifo_reset_n_0.reset_n
mp_wfifo_clk_0_clk => mp_wfifo_clk_0_clk, -- mp_wfifo_clk_0.clk
mp_wfifo_reset_n_0_reset_n => mp_wfifo_reset_n_0_reset_n, -- mp_wfifo_reset_n_0.reset_n
mp_rfifo_clk_1_clk => mp_rfifo_clk_1_clk, -- mp_rfifo_clk_1.clk
mp_rfifo_reset_n_1_reset_n => mp_rfifo_reset_n_1_reset_n, -- mp_rfifo_reset_n_1.reset_n
mp_wfifo_clk_1_clk => mp_wfifo_clk_1_clk, -- mp_wfifo_clk_1.clk
mp_wfifo_reset_n_1_reset_n => mp_wfifo_reset_n_1_reset_n, -- mp_wfifo_reset_n_1.reset_n
local_init_done => inst4_local_init_done, -- status.local_init_done
local_cal_success => inst4_local_cal_success, -- .local_cal_success
local_cal_fail => inst4_local_cal_fail, -- .local_cal_fail
oct_rzqin => oct_rzqin, -- oct.rzqin
pll_mem_clk => open, --pll_mem_clk, -- pll_sharing.pll_mem_clk
pll_write_clk => open, --pll_write_clk, -- .pll_write_clk
pll_locked => inst4_pll_locked, -- .pll_locked
pll_write_clk_pre_phy_clk => open, --pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk => open, --pll_addr_cmd_clk, -- .pll_addr_cmd_clk
pll_avl_clk => open, --pll_avl_clk, -- .pll_avl_clk
pll_config_clk => open, --pll_config_clk, -- .pll_config_clk
pll_mem_phy_clk => open, --pll_mem_phy_clk, -- .pll_mem_phy_clk
afi_phy_clk => open, --afi_phy_clk, -- .afi_phy_clk
pll_avl_phy_clk => open --pll_avl_phy_clk -- .pll_avl_phy_clk
);
mp_cmd_clk_0_clk <= inst4_afi_half_clk;
mp_cmd_reset_n_0_reset_n <= inst4_local_cal_success;
mp_cmd_clk_1_clk <= inst4_afi_half_clk;
mp_cmd_reset_n_1_reset_n <= inst4_local_cal_success;
mp_rfifo_clk_0_clk <= inst4_afi_half_clk;
mp_rfifo_reset_n_0_reset_n <= inst4_local_cal_success;
mp_wfifo_clk_0_clk <= inst4_afi_half_clk;
mp_wfifo_reset_n_0_reset_n <= inst4_local_cal_success;
mp_rfifo_clk_1_clk <= inst4_afi_half_clk;
mp_rfifo_reset_n_1_reset_n <= inst4_local_cal_success;
mp_wfifo_clk_1_clk <= inst4_afi_half_clk;
mp_wfifo_reset_n_1_reset_n <= inst4_local_cal_success;
--top level ports
pass <= inst2_pass and inst3_pass;
fail <= inst2_fail and inst3_fail;
test_complete <= inst2_test_complete and inst3_test_complete;
phy_clk <= inst4_afi_half_clk;
local_init_done <= inst4_local_init_done;
local_rdata_0 <= inst4_avl_rdata_0;
local_rdata_valid_0 <= inst4_avl_rdata_valid_0;
local_rdata_1 <= inst4_avl_rdata_1;
local_rdata_valid_1 <= inst4_avl_rdata_valid_1;
end arch;
|
<gh_stars>0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Receptor is
Port ( clk_Div_Freq : in STD_LOGIC;
Bit_Entrada : in STD_LOGIC;
Habilitador_Recepcion : in STD_LOGIC;
Recepcion_completa : out STD_LOGIC;
Registro : out STD_LOGIC_VECTOR (7 downto 0));
end Receptor;
architecture Behavioral of Receptor is
signal cont: integer range 7 downto 0 := 7;
signal estado: integer range 1 to 2 := 1;
signal registro_acum: std_logic_vector (7 downto 0);
begin
process(clk_Div_Freq)
begin
if Rising_edge(clk_Div_Freq) then
if Habilitador_Recepcion = '1' then
if estado = 1 then
if (cont >= 0 and cont <= 7) then
registro_acum(cont) <= Bit_Entrada;
Recepcion_completa <= '0';
cont <= cont - 1;
end if;
if cont = 0 then
Recepcion_completa <= '1';
estado <= 2;
end if;
end if;
if estado = 2 then
Registro <= registro_acum;
Recepcion_completa <= '0';
cont <= 7;
estado <= 1;
end if;
end if;
end if;
end process;
end Behavioral;
|
<reponame>Nibble-Knowledge/cpu-vhdl
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:40:19 10/22/2015
-- Design Name:
-- Module Name: C:/Users/Colton/Nibble_Knowledge_CPU/tb_register16.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register16 IS
END tb_register16;
ARCHITECTURE behavior OF tb_register16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register16
PORT(
d : IN std_logic_vector(3 downto 0);
q : OUT std_logic_vector(15 downto 0);
clk : IN std_logic;
reset : IN std_logic;
load : IN std_logic
);
END COMPONENT;
--Inputs
signal d : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal load : std_logic := '0';
--Outputs
signal q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register16 PORT MAP (
d => d,
q => q,
clk => clk,
reset => reset,
load => load
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
-- Load nibble3
load <= '1';
d <= "0011";
-- Load nibble2
wait for clk_period;
d <= "0010";
-- Load nibble1
wait for clk_period;
d <= "0001";
-- Load nibble0
wait for clk_period;
d <= "1010";
wait for clk_period;
load <= '0';
-- Simulate Junk
-- execute stage
d <= "1101";
wait for clk_period;
-- op code stage
d <= "1001";
wait for clk_period;
-- new address
-- Load nibble3
load <= '1';
d <= "1100";
-- Load nibble2
wait for clk_period;
d <= "0100";
-- Load nibble1
wait for clk_period;
d <= "1000";
-- Load nibble0
wait for clk_period;
d <= "0101";
wait for clk_period;
load <= '0';
-- Simulate Junk
-- execute stage
d <= "1111";
wait for clk_period;
-- op code stage
d <= "1101";
wait;
end process;
END;
|
<reponame>Rigoaguia/PWM-VHDL
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.ALL;
use work.Package_PWM.all;
entity PWM is
Port ( clk : in STD_LOGIC;
duty : in STD_LOGIC_VECTOR ((pwm_bit - 1) downto 0);
reset : in std_logic;
PWM_out : out STD_LOGIC);
end PWM;
architecture Behavioral of PWM is
signal counter : std_logic_vector ((pwm_bit - 1) downto 0) := (others => '0');
signal clk_out : std_logic;
component Prescaler
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component;
begin
presc : Prescaler port map (clk, reset, clk_out);
process (clk_out)
begin
if reset = '1' then
counter <= (others => '0');
PWM_out <= '0';
elsif rising_edge(clk_out) then
if counter = (resolucao_max - 1) then
counter <= (others => '0');
else
counter <= counter + '1';
end if;
if counter > duty then
PWM_out <= '0';
elsif duty /= 0 then
PWM_out <= '1';
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity decodificador2x4 is
port(
inpt: in std_logic_vector(1 downto 0);
enable: in std_logic;
outp: out std_logic_vector(3 downto 0)
);
end decodificador2x4;
architecture decoder of decodificador2x4 is
begin
process(inpt, enable)
begin
if enable='1' then
case inpt is
when "00" =>
outp <= "0001";
when "01" =>
outp <= "0010";
when "10" =>
outp <= "0100";
when others =>
outp <= "1000";
end case;
else
outp <= "0000";
end if;
end process;
end decoder;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity perm_layer is
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end perm_layer;
architecture structural of perm_layer is
begin
PERM: for i in 63 downto 0 generate
data_out((i mod 4) * 16 + (i / 4)) <= data_in(i);
end generate;
end structural;
|
library ieee;
library std;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.env.finish;
use work.numeric_lib.all;
use work.str_lib.all;
use work.sim_lib.all;
entity test_numeric_lib4 is
end entity;
architecture SIM of test_numeric_lib4 is
begin
process is
begin
print("Test numeric_lib");
check(clog2(1), 0, "clog2(1)", True);
check(clog2(2), 1, "clog2(2)", True);
check(clog2(3), 2, "clog2(3)", True);
check(clog2(4), 2, "clog2(4)", True);
check(clog2(5), 3, "clog2(5)", True);
check(clog2(6), 3, "clog2(6)", True);
check(clog2(7), 3, "clog2(7)", True);
check(clog2(8), 3, "clog2(8)", True);
check(clog2(9), 4, "clog2(9)", True);
check(f_increment("0000"), "0001", "f_increment(0000)", True);
check(f_increment("1010"), "1011", "f_increment(1010)", True);
check(f_increment("1111"), "0000", "f_increment(1111)", True);
check(f_increment("0"), "1", "f_ncrement(0)", True);
check(f_increment("1"), "0", "f_ncrement(1)", True);
finish(0);
end process;
end architecture;
|
<filename>Somador_4b/tb_fulladder4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity tb_fulladder4 is
end;
architecture behavioral of tb_fulladder4 is
signal
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity and2 is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of and2 is
begin
Y <= A and B;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity and3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of and3 is
begin
Y <= A and B and C;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity and4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of and4 is
begin
Y <= A and B and C and D;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ao21 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of ao21 is
begin
Y <= (A0 and A1) or B0;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ao22 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
B1 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of ao22 is
begin
Y <= (A0 and A1) or (B0 and B1);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aoi21 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of aoi21 is
begin
Y <= not ((A0 and A1) or B0);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aoi22 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
B1 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of aoi22 is
begin
Y <= not ((A0 and A1) or (B0 and B1));
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity buffer_module is
port (
A : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of buffer_module is
begin
Y <= A;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity inverter is
port (
A : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of inverter is
begin
Y <= not A;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux2 is
port (
A : in std_logic;
B : in std_logic;
S : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of mux2 is
begin
Y <= B when S = '1' else A;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity muxi2 is
port (
A : in std_logic;
B : in std_logic;
S : in std_logic;
Y : out std_logic
);
end entity;
begin
Y <= not (B when S = '1' else A);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nand2 is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nand2 is
begin
Y <= not (A and B);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nand2b is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nand2b is
begin
Y <= not (not A and B);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nand3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nand3 is
begin
Y <= not (A and B and C);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nand4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nand4 is
begin
Y <= not (A and B and C and D);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nor2 is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nor2 is
begin
Y <= not (A or B);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nor2b is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nor2b is
begin
Y <= not (not A or B);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nor3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nor3 is
begin
Y <= not (A or B or C);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nor4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of nor4 is
begin
Y <= not (A or B or C or D);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oa21 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of oa21 is
begin
Y <= (A0 or A1) and B0;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oa22 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
B1 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of oa22 is
begin
Y <= (A0 or A1) and (B0 or B1);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oai21 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of oai21 is
begin
Y <= not ((A0 or A1) and B0);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity oai22 is
port (
A0 : in std_logic;
A1 : in std_logic;
B0 : in std_logic;
B1 : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of oai22 is
begin
Y <= not (A0 or A1) and (B0 or B1);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity or2 is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of or2 is
begin
Y <= A or B;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity or3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of or3 is
begin
Y <= A or B or C;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity or4 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of or4 is
begin
Y <= A or B or C or D;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xnor2 is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of xnor2 is
begin
Y <= not (A xor B);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xor2 is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of xor2 is
begin
Y <= A xor B;
end architecture;
|
<gh_stars>1-10
-------------------------------------------------------------------------------
-- Title : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : ep_tx_pcs_tbi.vhd
-- Author : <NAME>
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Module implements the transmit path for 802.3z 1000BaseX PCS.
-- This block interfaces the Ethernet framer to TX PMA (Physical Medium Attachment).
-- It performs preamble generation, insertion of idle patterns, all the low-level
-- signalling (including 8b10b coding). Strobing signal for taking TX timestamps
-- is also generated.
--
-- Module uses two separate clocks: 125 MHz tbi_tx_clk (or gtp_tx_clk)
-- (Transmit clock for PHY) which clocks 8b10b signalling layer, and 62.5 MHz
-- (clk_sys_i) which is used for data exchange with the rest of switch. Data
-- exchange between these clock domains is done using an async FIFO.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-06-16 0.1 twlostow Created (no error propagation supported yet)
-- 2010-04-06 0.2 twlostow Cleanup, new timestamping/LCR scheme
-- 2010-07-30 0.2 twlostow Fixed preamble length bug
-- 2010-11-18 0.4 twlostow Added support for Xilinx GTP transceivers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_tx_pcs_8bit is
port (
-- reset (synchronous to refclk2, active LO)
rst_n_i : in std_logic;
-- 62.5 MHz clock (refclk/2)
clk_sys_i : in std_logic;
-- reset (phy_tx_clk_i sync)
rst_txclk_n_i : in std_logic;
-------------------------------------------------------------------------------
-- TX Framer inteface
-------------------------------------------------------------------------------
-- TX Fabric input
pcs_fab_i : in t_ep_internal_fabric;
-- HI pulse indicates an error during transmission of a frame (buffer underrun)
pcs_error_o : out std_logic;
-- HI indicates that the PCS is busy (transmitting a frame or during autonegotiation)
pcs_busy_o : out std_logic;
-- HI indicates that PCS FIFO is almost full.
pcs_dreq_o : out std_logic;
-------------------------------------------------------------------------------
-- WB controller control signals
-------------------------------------------------------------------------------
mdio_mcr_reset_i : in std_logic;
-- Transmit Control Register, EN_PCS field
mdio_mcr_pdown_i : in std_logic;
-- Transmit Control Register, TX_CAL field
mdio_wr_spec_tx_cal_i : in std_logic;
-- autonegotiation control
an_tx_en_i : in std_logic;
an_tx_val_i : in std_logic_vector(15 downto 0);
-- Timestamp strobe
timestamp_trigger_p_a_o : out std_logic;
-- RMON events
rmon_tx_underrun : out std_logic;
-------------------------------------------------------------------------------
-- PHY Interface
-------------------------------------------------------------------------------
phy_tx_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic
);
end ep_tx_pcs_8bit;
architecture behavioral of ep_tx_pcs_8bit is
-- TX state machine definitions
type t_tbif_tx_state is (TX_COMMA, TX_CAL, TX_CR1, TX_CR2, TX_CR3, TX_CR4, TX_SPD, TX_IDLE, TX_DATA, TX_PREAMBLE, TX_SFD, TX_EPD, TX_EXTEND, TX_GOTO_COMMA, TX_GEN_ERROR);
-- TX state machine signals
signal tx_is_k : std_logic;
signal tx_catch_disparity : std_logic;
signal tx_odata_reg : std_logic_vector(7 downto 0);
signal tx_state : t_tbif_tx_state;
signal tx_cntr : unsigned(3 downto 0);
signal tx_cr_alternate : std_logic;
-- TX clock alignment FIFO signals
signal fifo_packed_in, fifo_packed_out : std_logic_vector(17 downto 0);
signal fifo_empty : std_logic;
signal fifo_almost_empty : std_logic;
signal fifo_almost_full : std_logic;
signal fifo_enough_data : std_logic;
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal fifo_ready : std_logic;
signal fifo_clear_n : std_logic;
signal fifo_fab : t_ep_internal_fabric;
signal tx_rdreq_toggle : std_logic;
signal tx_odd_length : std_logic;
signal tx_busy : std_logic;
signal tx_error : std_logic;
signal rst_n_tx : std_logic;
signal mdio_mcr_reset_synced : std_logic;
signal mdio_mcr_pdown_synced : std_logic;
signal an_tx_en_synced : std_logic;
begin
U_sync_pcs_busy_o : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => tx_busy,
synced_o => pcs_busy_o);
U_sync_pcs_error_o : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => tx_error,
ppulse_o => pcs_error_o);
U_sync_an_tx_en : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => '1',
data_i => an_tx_en_i,
synced_o => an_tx_en_synced);
U_sync_mcr_reset : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => '1',
data_i => mdio_mcr_reset_i,
synced_o => mdio_mcr_reset_synced,
npulse_o => open,
ppulse_o => open);
U_sync_power_down : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => '1',
data_i => mdio_mcr_pdown_i,
synced_o => mdio_mcr_pdown_synced);
phy_tx_data_o <= tx_odata_reg;
phy_tx_k_o <= tx_is_k;
rst_n_tx <= rst_txclk_n_i and not mdio_mcr_reset_synced;
-------------------------------------------------------------------------------
-- Clock alignment FIFO
-------------------------------------------------------------------------------
fifo_clear_n <= '0' when (rst_n_i = '0') or (mdio_mcr_pdown_synced = '1') else '1';
f_pack_fifo_contents(pcs_fab_i, fifo_packed_in, fifo_wr, true);
U_TX_FIFO : generic_async_fifo
generic map (
g_data_width => 18,
g_size => 64,
g_with_rd_empty => true,
g_with_rd_almost_empty => true,
g_with_rd_count => true,
g_with_wr_almost_full => true,
g_almost_empty_threshold => 16,
g_almost_full_threshold => 56) -- fixme: make this a generic (or WB register)
port map (
rst_n_i => fifo_clear_n,
clk_wr_i => clk_sys_i,
d_i => fifo_packed_in,
we_i => fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => fifo_almost_full,
wr_count_o => open,
clk_rd_i => phy_tx_clk_i,
q_o => fifo_packed_out,
rd_i => fifo_rd,
rd_empty_o => fifo_empty,
rd_full_o => open,
rd_almost_empty_o => fifo_almost_empty,
rd_almost_full_o => open,
rd_count_o => open);
fifo_enough_data <= not fifo_almost_empty;
f_unpack_fifo_contents(fifo_packed_out, '1', fifo_fab, true);
-----------------------------------------------------------------------------
-- TX PCS state machine
-----------------------------------------------------------------------------
p_tx_fsm : process (phy_tx_clk_i)
begin
if rising_edge(phy_tx_clk_i) then
-- The PCS is reset or disabled
if(rst_n_tx = '0' or mdio_mcr_pdown_synced = '1') then
tx_state <= TX_COMMA;
timestamp_trigger_p_a_o <= '0';
fifo_rd <= '0';
tx_error <= '0';
tx_odata_reg <= (others => '0');
tx_is_k <= '0';
tx_cr_alternate <= '0';
tx_catch_disparity <= '0';
tx_cntr <= (others => '0');
tx_odd_length <= '0';
tx_rdreq_toggle <= '0';
rmon_tx_underrun <= '0';
else
case tx_state is
-------------------------------------------------------------------------------
-- State COMMA: sends K28.5 comma character (first byte of /I/ sequence)
-------------------------------------------------------------------------------
when TX_COMMA =>
tx_is_k <= '1';
tx_odata_reg <= c_K28_5;
tx_state <= TX_IDLE;
fifo_rd <= '0';
fifo_ready <= fifo_rd;
-------------------------------------------------------------------------------
-- State IDLE: sends the second code of the /I/ sequence with proper disparity\
-------------------------------------------------------------------------------
when TX_IDLE =>
-- clear the RMON/error pulse after 2 cycles (DATA->COMMA->IDLE) to
-- make sure is't long enough to trigger the event counter
rmon_tx_underrun <= '0';
tx_error <= '0';
-- endpoint wants to send Config_Reg
if(an_tx_en_synced = '1') then
tx_state <= TX_CR1;
tx_cr_alternate <= '0';
fifo_rd <= '0';
-- we've got a new frame in the FIFO
elsif (fifo_fab.sof = '1' and fifo_ready = '1' and tx_cntr = "0000")then
fifo_rd <= '1';
tx_state <= TX_SPD;
tx_cntr <= "0101";
-- host requested a calibration pattern
elsif(mdio_wr_spec_tx_cal_i = '1') then
tx_state <= TX_CAL;
fifo_rd <= '0';
tx_cr_alternate <= '0';
else
-- continue sending idle sequences and checking if something has arrived in the
-- FIFO
if(tx_cntr /= "0000") then
fifo_rd <= '0';
else
fifo_rd <= (not fifo_empty) and fifo_enough_data;
end if;
tx_state <= TX_COMMA;
end if;
tx_is_k <= '0';
-- check the disparity of the previously emitted code and choose whether to send
-- /I1/ or /I2/
if (phy_tx_disparity_i = '1' and tx_catch_disparity = '1') then
tx_odata_reg <= c_d5_6;
else
tx_odata_reg <= c_d16_2;
end if;
tx_catch_disparity <= '0';
if(tx_cntr /= "0000") then
tx_cntr <= tx_cntr - 1;
end if;
-------------------------------------------------------------------------------
-- State: CAL: transmit the calibration sequence
-------------------------------------------------------------------------------
when TX_CAL =>
tx_odata_reg <= c_k28_7;
tx_is_k <= '1';
if(mdio_wr_spec_tx_cal_i = '0' and tx_cr_alternate = '1') then
tx_state <= TX_COMMA;
end if;
tx_cr_alternate <= not tx_cr_alternate;
-------------------------------------------------------------------------------
-- States: CR1, CR2, CR3, CR4: send the /C/ Configuration code set
-------------------------------------------------------------------------------
when TX_CR1 =>
tx_is_k <= '1';
tx_odata_reg <= c_k28_5;
tx_state <= TX_CR2;
when TX_CR2 =>
tx_is_k <= '0';
if (tx_cr_alternate = '1') then
tx_odata_reg <= c_d21_5;
else
tx_odata_reg <= c_d2_2;
end if;
tx_cr_alternate <= not tx_cr_alternate;
tx_state <= TX_CR3;
when TX_CR3 =>
tx_odata_reg <= an_tx_val_i(7 downto 0);
tx_state <= TX_CR4;
when TX_CR4 =>
tx_odata_reg <= an_tx_val_i(15 downto 8);
-- check if the autonegotiation control still wants the Config_Reg to be sent
if(an_tx_en_synced = '1') then
tx_state <= TX_CR1;
else
tx_state <= TX_COMMA;
end if;
-------------------------------------------------------------------------------
-- State SPD: sends a start-of-packet delimeter
-------------------------------------------------------------------------------
when TX_SPD =>
fifo_rd <= '0';
tx_is_k <= '1';
tx_odata_reg <= c_k27_7;
tx_state <= TX_PREAMBLE;
-------------------------------------------------------------------------------
-- State PREAMBLE: produces an Ethernet preamble
-------------------------------------------------------------------------------
when TX_PREAMBLE =>
tx_is_k <= '0';
tx_odata_reg <= c_preamble_char;
if (tx_cntr = "0000") then
tx_state <= TX_SFD;
tx_rdreq_toggle <= '1';
end if;
tx_cntr <= tx_cntr - 1;
-------------------------------------------------------------------------------
-- State SFD: outputs the start-of-frame delimeter (last byte of the preamble)
-------------------------------------------------------------------------------
when TX_SFD =>
tx_odata_reg <= c_preamble_sfd;
tx_rdreq_toggle <= '1';
tx_state <= TX_DATA;
timestamp_trigger_p_a_o <= '1';
when TX_DATA =>
-- toggle the TX FIFO request line, so we read a 16-bit word
-- every 2 phy_tx_clk_i periods
fifo_rd <= tx_rdreq_toggle and not (fifo_empty or fifo_fab.eof);
if((fifo_empty = '1' or fifo_fab.error = '1') and fifo_fab.eof = '0') then --
-- FIFO underrun?
tx_odata_reg <= c_k30_7; -- emit error propagation code
tx_is_k <= '1';
tx_state <= TX_GEN_ERROR;
tx_error <= not fifo_fab.error;
rmon_tx_underrun <= '1';
else
if tx_rdreq_toggle = '1' then -- send 16-bit word MSB or LSB
tx_odata_reg <= fifo_fab.data(15 downto 8);
else
tx_odata_reg <= fifo_fab.data(7 downto 0);
end if;
tx_rdreq_toggle <= not tx_rdreq_toggle;
-- handle the end of frame both for even- and odd-length frames
tx_odd_length <= fifo_fab.bytesel;
if (fifo_fab.eof = '1' and (tx_rdreq_toggle = '0' or (tx_rdreq_toggle = '1' and fifo_fab.bytesel = '1'))) then
tx_state <= TX_EPD;
fifo_rd <= '0';
end if;
end if;
-------------------------------------------------------------------------------
-- State EPD: send End-of-frame delimeter
-------------------------------------------------------------------------------
when TX_EPD =>
timestamp_trigger_p_a_o <= '0';
tx_is_k <= '1';
tx_odata_reg <= c_k29_7;
tx_state <= TX_EXTEND;
--------------------------------------------------------------------------------
-- State EXTEND: send the carrier extension
-------------------------------------------------------------------------------
when TX_EXTEND =>
tx_odata_reg <= c_k23_7;
if(tx_odd_length = '0')then
tx_state <= TX_COMMA;
tx_catch_disparity <= '1';
else
tx_odd_length <= '0';
end if;
tx_cntr <= "1000";
-------------------------------------------------------------------------------
-- State GEN_ERROR: entered when an error occured. Just terminates the frame.
-------------------------------------------------------------------------------
when TX_GEN_ERROR =>
tx_state <= TX_EPD;
when others => null;
end case;
end if;
end if;
end process;
process(phy_tx_clk_i)
begin
if rising_edge(phy_tx_clk_i) then
if fifo_empty = '0' or (tx_state /= TX_IDLE and tx_state /= TX_COMMA) then
tx_busy <= '1';
else
tx_busy <= '0';
end if;
end if;
end process;
pcs_dreq_o <= not fifo_almost_full;
end behavioral;
|
<filename>rtl/addn.vhd
library ieee;
use ieee.std_logic_1164.all;
library TP_LIB;
use TP_LIB.ADD1;
entity ADDN is
generic (N : natural := 8);
port (
A, B : in std_logic_vector(N - 1 downto 0);
S : out std_logic_vector(N - 1 downto 0);
C_out : out std_logic
);
end ADDN;
architecture str of ADDN is
component ADD1 is
port (
A, B, Cin : in std_logic;
S, Cout : out std_logic
);
end component;
signal carry : std_logic_vector(N downto 0);
begin
carry(0) <= '0';
ADD_insts : for k in 0 to N - 1 generate
ADD_inst : ADD1 port map(A(k), B(k), carry(k), S(k), carry(k + 1));
end generate;
C_out <= carry(N);
end architecture;
|
<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
entity siguelineas is port(
md, mi : out std_logic;
sd, si : in std_logic
);
end siguelineas;
architecture arch_siguelineas of siguelineas is
begin
md <= si;
mi <= sd;
end arch_siguelineas ; -- arch_siguelineas
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity letter2screen is
port(
row, column : in INTEGER;
letter : in std_logic_vector(7 downto 0);
red, green, blue : out std_logic_vector(7 downto 0));
end letter2screen;
architecture a of letter2screen is
begin
process(row,column,letter)
begin
case letter is
when x"41" => --A
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (row>=301 AND row <=401 AND column>=1 AND column <=501)
OR (column>=501 AND column <=601 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"42" => --B
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=401)
OR (row>=1 AND row <=301 AND column>=401 AND column <=501)
OR (row>=301 AND row <=401 AND column>=1 AND column <=501)
OR (column>=501 AND column <=601 AND row>=301 AND row <=801)
OR (row>=701 AND row <=801 AND column>=1 AND column <=501) ) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"43" => --C
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (column>=1 AND column <=501 AND row>=701 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"44" => --D
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=401)
OR (row>=101 AND row <=201 AND column>=401 AND column <=501)
OR (column>=501 AND column <=601 AND row>=201 AND row <=601)
OR (row>=601 AND row <=701 AND column>=401 AND column <=501)
OR (row>=701 AND row <=801 AND column>=1 AND column <=401) ) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"45" => --E
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=401)
OR (row>=301 AND row <=401 AND column>=1 AND column <=401)
OR (row>=701 AND row <=801 AND column>=1 AND column <=401)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"46" => --F
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=401)
OR (row>=301 AND row <=401 AND column>=1 AND column <=301)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"47" => --G
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (column>=1 AND column <=601 AND row>=701 AND row <=801)
OR (column>=501 AND column <=601 AND row>=401 AND row <=801)
OR (column>=301 AND column <=601 AND row>=401 AND row <=501)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"48" => --H
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=301 AND row <=401 AND column>=1 AND column <=501)
OR (column>=501 AND column <=601 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"49" => --I
if( (column>=201 AND column <=301 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (row>=701 AND row <=801 AND column>=1 AND column <=501)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"4A" => --J
if( (column>=1 AND column <=101 AND row>=501 AND row <=801)
OR (row>=701 AND row <=801 AND column>=1 AND column <=501)
OR (column>=401 AND column <=501 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"4B" => --K
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=301 AND row <=401 AND column>=101 AND column <=201)
OR (row>=201 AND row <=301 AND column>=201 AND column <=301)
OR (row>=101 AND row <=201 AND column>=301 AND column <=401)
OR (row>=1 AND row <=101 AND column>=401 AND column <=501)
OR (row>=401 AND row <=501 AND column>=201 AND column <=301)
OR (row>=501 AND row <=601 AND column>=301 AND column <=401)
OR (row>=601 AND row <=701 AND column>=401 AND column <=501)
OR (row>=701 AND row <=801 AND column>=501 AND column <=601) ) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"4C" => --L
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (column>=1 AND column <=501 AND row>=701 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"4D" => --M
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=101 AND row <=201 AND column>=101 AND column <=201)
OR (row>=201 AND row <=301 AND column>=201 AND column <=301)
OR (row>=301 AND row <=401 AND column>=301 AND column <=401)
OR (row>=201 AND row <=301 AND column>=401 AND column <=501)
OR (row>=101 AND row <=201 AND column>=501 AND column <=601)
OR (column>=601 AND column <=701 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"4E" => --N
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=101 AND row <=301 AND column>=101 AND column <=201)
OR (row>=201 AND row <=401 AND column>=201 AND column <=301)
OR (row>=301 AND row <=501 AND column>=301 AND column <=401)
OR (row>=401 AND row <=601 AND column>=401 AND column <=501)
OR (row>=501 AND row <=701 AND column>=501 AND column <=601)
OR (column>=601 AND column <=701 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"4F" => --O
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (column>=1 AND column <=501 AND row>=701 AND row <=801)
OR (column>=501 AND column <=601 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"50" => --P
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=301 AND row <=401 AND column>=1 AND column <=501)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (column>=501 AND column <=601 AND row>=1 AND row <=401)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"51" => --Q
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (column>=1 AND column <=501 AND row>=701 AND row <=801)
OR (column>=301 AND column <=601 AND row>=501 AND row <=601)
OR (column>=401 AND column <=501 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"52" => --R
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=301 AND row <=401 AND column>=1 AND column <=501)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)
OR (row>=401 AND row <=501 AND column>=301 AND column <=401)
OR (row>=501 AND row <=701 AND column>=401 AND column <=501)
OR (row>=701 AND row <=801 AND column>=501 AND column <=601)
OR (column>=501 AND column <=601 AND row>=1 AND row <=401)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"53" => --S
if( (column>=1 AND column <=101 AND row>=1 AND row <=401)
OR (column>=1 AND column <=101 AND row>=601 AND row <=801)
OR (column>=1 AND column <=501 AND row>=1 AND row <=101)
OR (column>=1 AND column <=501 AND row>=301 AND row <=401)
OR (column>=1 AND column <=501 AND row>=701 AND row <=801)
OR (column>=401 AND column <=501 AND row>=1 AND row <=201)
OR (column>=401 AND column <=501 AND row>=301 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"54" => --T
if( (column>=201 AND column <=301 AND row>=1 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=501)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"55" => --U
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (column>=1 AND column <=501 AND row>=701 AND row <=801)
OR (column>=501 AND column <=601 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"56" => --V
if( (column>=1 AND column <=101 AND row>=1 AND row <=501)
OR (row>=501 AND row <=601 AND column>=101 AND column <=201)
OR (row>=601 AND row <=701 AND column>=201 AND column <=301)
OR (row>=701 AND row <=801 AND column>=301 AND column <=401)
OR (row>=601 AND row <=701 AND column>=401 AND column <=501)
OR (row>=501 AND row <=601 AND column>=501 AND column <=601)
OR (column>=601 AND column <=701 AND row>=1 AND row <=501)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"57" => --W
if( (column>=1 AND column <=101 AND row>=1 AND row <=801)
OR (row>=601 AND row <=701 AND column>=101 AND column <=201)
OR (row>=501 AND row <=601 AND column>=201 AND column <=301)
OR (row>=401 AND row <=501 AND column>=301 AND column <=401)
OR (row>=501 AND row <=601 AND column>=401 AND column <=501)
OR (row>=601 AND row <=701 AND column>=501 AND column <=601)
OR (column>=601 AND column <=701 AND row>=1 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"58" => --X
if( (column>=1 AND column <=101 AND row>=1 AND row <=201)
OR (column>=1 AND column <=101 AND row>=501 AND row <=801)
OR (column>=101 AND column <=201 AND row>=201 AND row <=301)
OR (column>=101 AND column <=201 AND row>=401 AND row <=501)
OR (column>=201 AND column <=301 AND row>=301 AND row <=401)
OR (column>=301 AND column <=401 AND row>=201 AND row <=301)
OR (column>=301 AND column <=401 AND row>=401 AND row <=501)
OR (column>=401 AND column <=501 AND row>=1 AND row <=201)
OR (column>=401 AND column <=501 AND row>=501 AND row <=801)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"59" => --Y
if( (column>=1 AND column <=101 AND row>=1 AND row <=201)
OR (column>=101 AND column <=201 AND row>=201 AND row <=301)
OR (row>=301 AND row <=801 AND column>=201 AND column <=301)
OR (column>=301 AND column <=401 AND row>=201 AND row <=301)
OR (column>=401 AND column <=501 AND row>=1 AND row <=201)) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when x"5A" => --Z
if( (column>=1 AND column <=101 AND row>=601 AND row <=801)
OR (row>=1 AND row <=101 AND column>=1 AND column <=601)
OR (row>=701 AND row <=801 AND column>=1 AND column <=601)
OR (column>=1 AND column <=101 AND row>=601 AND row <=801)
OR (column>=501 AND column <=601 AND row>=1 AND row <=201)
OR (column>=101 AND column <=201 AND row>=501 AND row <=601)
OR (column>=201 AND column <=301 AND row>=401 AND row <=501)
OR (column>=301 AND column <=401 AND row>=301 AND row <=401)
OR (column>=401 AND column <=501 AND row>=201 AND row <=301)
) then
red <= x"FF";
green <= x"FF";
blue <= x"FF";
else
red <= x"00";
green <= x"00";
blue <= x"00";
end if;
when OTHERS =>
red <= x"00";
green <= x"00";
blue <= x"00";
end case;
end process;
end a;
|
<reponame>alimpk/aut-ceit-psd-ta
--/*
--**********************************************************
-- Design Automation Course Homework (Spring, 2020 Semester)
-- Amirkabir University of Technology (Tehran Polytechnic)
-- Department of Computer Engineering (CE-AUT)
-- https://ce.aut.ac.ir
-- Designed TA (ali[dot]mohammadpour[at]ac[dot]ir)
-- *******************************************************
-- Student ID : XXXXXXX
-- Student Name: -----------------
-- Student Mail: -----------------
-- *******************************************************
-- Module: ProblemSet 3, Problem 2, Section A
-- *******************************************************
-- Additional Comments:
--*/
library ieee;
use ieee.std_logic_1164.all;
entity piso is
port (
clk : in std_logic ;
para_in : in std_logic_vector ;
reset : in std_logic ;
load : in std_logic ;
shift_en : in std_logic ;
ser_out : out std_logic) ;
end piso;
architecture piso_arc of piso is
begin
-- write your code here
end piso_arc;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity DebounceUnit is
generic(kHzClkFreq : positive := 50000;
mSecMinInWidth : positive := 100;
inPolarity : std_logic := '1';
outPolarity : std_logic := '1');
port(refClk : in std_logic;
dirtyIn : in std_logic;
pulsedOut : out std_logic);
end DebounceUnit;
architecture Behavioral of DebounceUnit is
constant MIN_IN_WIDTH_CYCLES : positive := mSecMinInWidth * kHzClkFreq;
subtype TCounter is natural range 0 to MIN_IN_WIDTH_CYCLES;
signal s_debounceCnt : TCounter := 0;
signal s_dirtyIn, s_previousIn, s_pulsedOut : std_logic;
begin
in_sync_proc : process(refClk)
begin
if (rising_edge(refClk)) then
if (inPolarity = '1') then
s_dirtyIn <= dirtyIn;
else
s_dirtyIn <= not dirtyIn;
end if;
s_previousIn <= s_dirtyIn;
end if;
end process;
count_proc : process(refClk)
begin
if (rising_edge(refClk)) then
if ((s_dirtyIn = '0') or
(s_debounceCnt > MIN_IN_WIDTH_CYCLES)) then
s_debounceCnt <= 0;
s_pulsedOut <= '0';
elsif (s_dirtyIn = '1') then
if (s_previousIn = '0') then
s_debounceCnt <= MIN_IN_WIDTH_CYCLES;
s_pulsedOut <= '0';
else
if (s_debounceCnt >= 1) then
s_debounceCnt <= s_debounceCnt - 1;
end if;
if (s_debounceCnt = 1) then
s_pulsedOut <= '1';
else
s_pulsedOut <= '0';
end if;
end if;
end if;
end if;
end process;
pulsedOut <= s_pulsedOut when (outPolarity = '1') else
not s_pulsedOut;
end Behavioral;
|
<reponame>abs-tudelft/vhdeps<gh_stars>10-100
-- Copyright 2018 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.Stream_pkg.all;
use work.ClockGen_pkg.all;
use work.StreamSource_pkg.all;
use work.StreamSink_pkg.all;
entity StreamSync_tb is
end StreamSync_tb;
architecture TestBench of StreamSync_tb is
signal clk : std_logic;
signal reset : std_logic;
signal a_valid : std_logic;
signal a_ready : std_logic;
signal a_data : std_logic_vector(7 downto 0);
signal a_x, a_y, a_z : std_logic_vector(0 downto 0);
signal a_advance_other : std_logic;
signal a_use_other : std_logic;
signal a_out_enable : std_logic;
signal b_valid : std_logic;
signal b_ready : std_logic;
signal b_data : std_logic_vector(7 downto 0);
signal b_x, b_y, b_z : std_logic_vector(0 downto 0);
signal b_advance_other : std_logic;
signal b_use_other : std_logic;
signal b_out_enable : std_logic;
signal c_valid : std_logic;
signal c_ready : std_logic;
signal c_data : std_logic_vector(7 downto 0);
signal d_valid : std_logic;
signal d_ready : std_logic;
signal d_data : std_logic_vector(7 downto 0);
begin
clkgen: ClockGen_mdl
port map (
clk => clk,
reset => reset
);
a_source: StreamSource_mdl
generic map (
NAME => "a",
ELEMENT_WIDTH => 8,
X_WIDTH => 1,
Y_WIDTH => 1,
Z_WIDTH => 1
)
port map (
clk => clk,
reset => reset,
valid => a_valid,
ready => a_ready,
data => a_data,
x => a_x,
y => a_y,
z => a_z
);
a_advance_other <= a_x(0) or not a_valid;
a_use_other <= a_y(0) or not a_valid;
a_out_enable <= a_z(0) or not a_valid;
b_source: StreamSource_mdl
generic map (
NAME => "b",
ELEMENT_WIDTH => 8,
X_WIDTH => 1,
Y_WIDTH => 1,
Z_WIDTH => 1
)
port map (
clk => clk,
reset => reset,
valid => b_valid,
ready => b_ready,
data => b_data,
x => b_x,
y => b_y,
z => b_z
);
b_advance_other <= b_x(0) or not b_valid;
b_use_other <= b_y(0) or not b_valid;
b_out_enable <= b_z(0) or not b_valid;
uut: StreamSync
generic map (
NUM_INPUTS => 2,
NUM_OUTPUTS => 2
)
port map (
clk => clk,
reset => reset,
in_valid(1) => b_valid,
in_valid(0) => a_valid,
in_ready(1) => b_ready,
in_ready(0) => a_ready,
in_advance(1) => a_advance_other,
in_advance(0) => b_advance_other,
in_use(1) => a_use_other,
in_use(0) => b_use_other,
out_valid(1) => d_valid,
out_valid(0) => c_valid,
out_ready(1) => d_ready,
out_ready(0) => c_ready,
out_enable(1) => b_out_enable,
out_enable(0) => a_out_enable
);
mix_proc: process (a_data, b_data) is
begin
-- C = text from A, capitalization from B.
c_data <= a_data;
if a_data(6) = '1' then
c_data(5) <= b_data(5);
end if;
-- D = text from B, capitalization from A.
d_data <= b_data;
if b_data(6) = '1' then
d_data(5) <= a_data(5);
end if;
end process;
c_sink: StreamSink_mdl
generic map (
NAME => "c",
ELEMENT_WIDTH => 8
)
port map (
clk => clk,
reset => reset,
valid => c_valid,
ready => c_ready,
data => c_data
);
d_sink: StreamSink_mdl
generic map (
NAME => "d",
ELEMENT_WIDTH => 8
)
port map (
clk => clk,
reset => reset,
valid => d_valid,
ready => d_ready,
data => d_data
);
end TestBench;
|
<filename>SobelMatrixMultiplier/solution1/syn/vhdl/combineOperatorResul.vhd
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4.1
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity combineOperatorResul is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
verticalResult : IN STD_LOGIC_VECTOR (31 downto 0);
horizontalResult : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of combineOperatorResul is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
signal result_fu_39_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal result_reg_78 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state2_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state3_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state12_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_state13_pp0_stage0_iter12 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter13 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal result_1_fu_45_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal result_1_reg_83 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fxp_sqrt_fu_34_in_val_V_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fxp_sqrt_fu_34_ap_return : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fxp_sqrt_fu_34_ap_ce : STD_LOGIC;
signal ap_block_pp0_stage0 : BOOLEAN;
signal result_fu_39_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal result_fu_39_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal result_1_fu_45_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal result_1_fu_45_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_3_fu_56_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_2_fu_51_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal verticalResult_int_reg : STD_LOGIC_VECTOR (31 downto 0);
signal horizontalResult_int_reg : STD_LOGIC_VECTOR (31 downto 0);
component fxp_sqrt IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_val_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (19 downto 0);
ap_ce : IN STD_LOGIC );
end component;
begin
grp_fxp_sqrt_fu_34 : component fxp_sqrt
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_val_V_read => grp_fxp_sqrt_fu_34_in_val_V_read,
ap_return => grp_fxp_sqrt_fu_34_ap_return,
ap_ce => grp_fxp_sqrt_fu_34_ap_ce);
horizontalResult_int_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
horizontalResult_int_reg <= horizontalResult;
end if;
end process;
verticalResult_int_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
verticalResult_int_reg <= verticalResult;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
result_1_reg_83 <= result_1_fu_45_p2;
result_reg_78 <= result_fu_39_p2;
end if;
end if;
end process;
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage0_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_return <= grp_fxp_sqrt_fu_34_ap_return(19 downto 8);
grp_fxp_sqrt_fu_34_ap_ce_assign_proc : process(ap_block_pp0_stage0_11001)
begin
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
grp_fxp_sqrt_fu_34_ap_ce <= ap_const_logic_1;
else
grp_fxp_sqrt_fu_34_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_fxp_sqrt_fu_34_in_val_V_read <= std_logic_vector(unsigned(p_Val2_3_fu_56_p2) + unsigned(p_Val2_2_fu_51_p2));
p_Val2_2_fu_51_p2 <= std_logic_vector(shift_left(unsigned(result_reg_78),to_integer(unsigned('0' & ap_const_lv32_8(31-1 downto 0)))));
p_Val2_3_fu_56_p2 <= std_logic_vector(shift_left(unsigned(result_1_reg_83),to_integer(unsigned('0' & ap_const_lv32_8(31-1 downto 0)))));
result_1_fu_45_p0 <= horizontalResult_int_reg;
result_1_fu_45_p1 <= horizontalResult_int_reg;
result_1_fu_45_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(result_1_fu_45_p0) * signed(result_1_fu_45_p1))), 32));
result_fu_39_p0 <= verticalResult_int_reg;
result_fu_39_p1 <= verticalResult_int_reg;
result_fu_39_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(result_fu_39_p0) * signed(result_fu_39_p1))), 32));
end behav;
|
<filename>VHDL/RTL/VGA/dp_ram.vhd
-- from http://help.latticesemi.com/docs/webhelp/eng/wwhelp/wwhimpl/common/html/wwhelp.htm#href=Design%20Entry/inferring_ram_dual_port.htm
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dp_ram is
generic (
addr_width : natural;
data_width : natural);
port (
addra_i : in std_logic_vector (addr_width - 1 downto 0);
wea_i : in std_logic;
clka_i : in std_logic;
dina_i : in std_logic_vector (data_width - 1 downto 0);
douta_o : out std_logic_vector (data_width - 1 downto 0);
addrb_i : in std_logic_vector (addr_width - 1 downto 0);
web_i : in std_logic;
clkb_i : in std_logic;
dinb_i : in std_logic_vector (data_width - 1 downto 0);
doutb_o : out std_logic_vector (data_width - 1 downto 0));
end dp_ram;
architecture rtl of dp_ram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type := (others => X"02");
attribute syn_ramstyle: string;
attribute syn_ramstyle of mem: signal is "no_rw_check";
begin
process (clka_i) -- Using port a.
begin
if (rising_edge(clka_i)) then
if (wea_i = '1') then
mem(conv_integer(addra_i)) <= dina_i;
-- Using address bus a.
end if;
douta_o <= mem(conv_integer(addra_i));
end if;
end process;
process (clkb_i) -- Using port b.
begin
if (rising_edge(clkb_i)) then
if (web_i = '1') then
mem(conv_integer(addrb_i)) <= dinb_i;
-- Using address bus b.
end if;
doutb_o <= mem(conv_integer(addrb_i));
end if;
end process;
end rtl;
|
-- file: player/calculate_speed.vhd
-- authors: <NAME> and <NAME>
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Calculate current speed based on internal register for speed, gravity value
-- and jump signal.
library ieee ;
use ieee.std_logic_1164.all ;
entity calculate_speed is
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
speed : out integer range - V_RES to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end calculate_speed ;
architecture behavior of calculate_speed is
--signal sp : integer range - V_RES to V_RES - 1 := -1;
signal jump_aux : std_logic ;
begin
process (clock, reset)
variable sp : integer range - V_RES to V_RES - 1 := -1;
begin
if enable = '1' and rising_edge(clock) then
if jump = '1' then
sp := -1 ;
else
sp := sp + gravity ;
end if ;
end if ;
speed <= sp;
end process ;
end behavior;
|
<gh_stars>0
-- _/\/\/\/\/\/\_ _/\/\/\/\_ ___/\/\/\/\___
-- _/\/\_________ ___/\/\___ _/\/\____/\/\_
-- _/\/\/\/\/\___ ___/\/\___ _/\/\____/\/\_
-- _/\/\_________ ___/\/\___ _/\/\____/\/\_
-- _/\/\_________ _/\/\/\/\_ ___/\/\/\/\___
-- ______________ __________ ______________
-- LEGv8 CPU Assembler, CPU, and I/O System
-- "I want to take responsibility for my work to the very end" --<NAME>
--
-- pipelinedcpu3_testbench.vhd
-- <NAME> | <NAME> | <NAME>
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PipelinedCPU3Testbench is
end;
architecture tesbench of PipelinedCPU3Testbench is
signal DEBUG_PC : std_logic_vector(63 downto 0);
signal DEBUG_INSTRUCTION : std_logic_vector(31 downto 0);
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal X09 : std_logic_vector(63 downto 0);
signal X10 : std_logic_vector(63 downto 0);
signal X11 : std_logic_vector(63 downto 0);
signal X12 : std_logic_vector(63 downto 0);
signal X19 : std_logic_vector(63 downto 0);
signal X20 : std_logic_vector(63 downto 0);
signal X21 : std_logic_vector(63 downto 0);
signal X22 : std_logic_vector(63 downto 0);
signal DEBUG_TEMPS : std_logic_vector(64*4-1 downto 0);
signal DEBUG_SAVED : std_logic_vector(64*4-1 downto 0);
signal DEBUG_MEM : std_logic_vector(64*4-1 downto 0);
signal DEBUG_FORWARDA : std_logic_vector(1 downto 0);
signal DEBUG_FORWARDB : std_logic_vector(1 downto 0);
signal MEM_00 : std_logic_vector(63 downto 0);
signal MEM_08 : std_logic_vector(63 downto 0);
signal MEM_16 : std_logic_vector(63 downto 0);
signal MEM_24 : std_logic_vector(63 downto 0);
signal DMEM_ADDR : std_logic_vector(63 downto 0);
signal DMEM_READ_DATA : std_logic_vector(63 downto 0);
signal DMEM_WRITE_DATA : std_logic_vector(63 downto 0);
signal DMEM_READ : std_logic;
signal DMEM_WRITE : std_logic;
signal IMEM_ADDR : std_logic_vector(63 downto 0);
signal IMEM_DATA : std_logic_vector(31 downto 0);
component PipelinedCPU3 is
port(
clk : in std_logic;
rst : in std_logic;
--IMEM ports
IMEM_ADDR : out std_logic_vector(63 downto 0);
IMEM_DATA : in std_logic_vector(31 downto 0);
--DMEM ports
DMEM_ADDR : out std_logic_vector(63 downto 0);
DMEM_WRITE_DATA : out std_logic_vector(63 downto 0);
DMEM_READ_DATA : in std_logic_vector(63 downto 0);
DMEM_READ : out std_logic;
DMEM_WRITE : out std_logic;
--Probe ports used for testing
DEBUG_IF_FLUSH : out std_logic;
DEBUG_REG_EQUAL : out std_logic;
-- Forwarding control signals
DEBUG_FORWARDA : out std_logic_vector(1 downto 0);
DEBUG_FORWARDB : out std_logic_vector(1 downto 0);
--The current address (AddressOut from the PC)
DEBUG_PC : out std_logic_vector(63 downto 0);
--Value of PC.write_enable
DEBUG_PC_WRITE_ENABLE : out STD_LOGIC;
--The current instruction (Instruction output of IMEM)
DEBUG_INSTRUCTION : out std_logic_vector(31 downto 0);
--DEBUG ports from other components
DEBUG_TMP_REGS : out std_logic_vector(64*4 - 1 downto 0);
DEBUG_SAVED_REGS : out std_logic_vector(64*4 - 1 downto 0);
DEBUG_MEM_CONTENTS : out std_logic_vector(64*4 - 1 downto 0)
);
end component;
component IMEM is
-- The instruction memory is a byte addressable, big-endian, read-only memory
-- Reads occur continuously
generic(NUM_BYTES : integer := 256);
-- NUM_BYTES is the number of bytes in the memory (small to save computation resources)
port(
Address : in STD_LOGIC_VECTOR(63 downto 0); -- Address to read from
ReadData : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
component DMEM is
-- The data memory is a byte addressble, big-endian, read/write memory with a single address port
-- It may not read and write at the same time
generic(NUM_BYTES : integer := 512);
-- NUM_BYTES is the number of bytes in the memory (small to save computation resources)
port(
WriteData : in STD_LOGIC_VECTOR(63 downto 0); -- Input data
Address : in STD_LOGIC_VECTOR(63 downto 0); -- Read/Write address
MemRead : in STD_LOGIC; -- Indicates a read operation
MemWrite : in STD_LOGIC; -- Indicates a write operation
Clock : in STD_LOGIC; -- Writes are triggered by a rising edge
ReadData : out STD_LOGIC_VECTOR(63 downto 0); -- Output data
--Probe ports used for testing
-- Four 64-bit words: DMEM(0) & DMEM(4) & DMEM(8) & DMEM(12)
DEBUG_MEM_CONTENTS : out STD_LOGIC_VECTOR(64*4 - 1 downto 0)
);
end component;
begin
DUT : PipelinedCPU3 port map(
clk => clk,
rst => rst,
--IMEM ports
IMEM_ADDR => IMEM_ADDR,
IMEM_DATA => IMEM_DATA,
--DMEM ports
DMEM_ADDR => DMEM_ADDR,
DMEM_WRITE_DATA => DMEM_WRITE_DATA,
DMEM_READ_DATA => DMEM_READ_DATA,
DMEM_READ => DMEM_READ,
DMEM_WRITE => DMEM_WRITE,
DEBUG_FORWARDA => DEBUG_FORWARDA,
DEBUG_FORWARDB => DEBUG_FORWARDB,
DEBUG_PC => DEBUG_PC,
DEBUG_INSTRUCTION => DEBUG_INSTRUCTION,
DEBUG_TMP_REGS => DEBUG_TEMPS,
DEBUG_SAVED_REGS => DEBUG_SAVED
);
DMEM_0 : DMEM port map(
WriteData => DMEM_WRITE_DATA,
Address => DMEM_ADDR,
MemRead => DMEM_READ,
MemWrite => DMEM_WRITE,
Clock => clk,
ReadData => DMEM_READ_DATA,
DEBUG_MEM_CONTENTS => DEBUG_MEM
);
IMEM_0 : IMEM port map(
Address => IMEM_ADDR,
ReadData => IMEM_DATA
);
MEM_24 <= DEBUG_MEM(8* 1-1 downto 8* 0) &
DEBUG_MEM(8* 2-1 downto 8* 1) &
DEBUG_MEM(8* 3-1 downto 8* 2) &
DEBUG_MEM(8* 4-1 downto 8* 3) &
DEBUG_MEM(8* 5-1 downto 8* 4) &
DEBUG_MEM(8* 6-1 downto 8* 5) &
DEBUG_MEM(8* 7-1 downto 8* 6) &
DEBUG_MEM(8* 8-1 downto 8* 7);
MEM_16 <= DEBUG_MEM(8* 9-1 downto 8* 8) &
DEBUG_MEM(8*10-1 downto 8* 9) &
DEBUG_MEM(8*11-1 downto 8*10) &
DEBUG_MEM(8*12-1 downto 8*11) &
DEBUG_MEM(8*13-1 downto 8*12) &
DEBUG_MEM(8*14-1 downto 8*13) &
DEBUG_MEM(8*15-1 downto 8*14) &
DEBUG_MEM(8*16-1 downto 8*15);
MEM_08 <= DEBUG_MEM(8*17-1 downto 8*16) &
DEBUG_MEM(8*18-1 downto 8*17) &
DEBUG_MEM(8*19-1 downto 8*18) &
DEBUG_MEM(8*20-1 downto 8*19) &
DEBUG_MEM(8*21-1 downto 8*20) &
DEBUG_MEM(8*22-1 downto 8*21) &
DEBUG_MEM(8*23-1 downto 8*22) &
DEBUG_MEM(8*24-1 downto 8*23);
MEM_00 <= DEBUG_MEM(8*25-1 downto 8*24) &
DEBUG_MEM(8*26-1 downto 8*25) &
DEBUG_MEM(8*27-1 downto 8*26) &
DEBUG_MEM(8*28-1 downto 8*27) &
DEBUG_MEM(8*29-1 downto 8*28) &
DEBUG_MEM(8*30-1 downto 8*29) &
DEBUG_MEM(8*31-1 downto 8*30) &
DEBUG_MEM(8*32-1 downto 8*31);
X12 <= DEBUG_TEMPS(63 downto 0 );
X11 <= DEBUG_TEMPS(127 downto 64 );
X10 <= DEBUG_TEMPS(191 downto 128);
X09 <= DEBUG_TEMPS(255 downto 192);
X22 <= DEBUG_SAVED(63 downto 0 );
X21 <= DEBUG_SAVED(127 downto 64 );
X20 <= DEBUG_SAVED(191 downto 128);
X19 <= DEBUG_SAVED(255 downto 192);
process begin
wait for 5 ns;
clk <= not clk;
wait for 5 ns;
clk <= not clk;
end process;
process begin
wait for 7.5 ns;
rst <= '0';
wait;
end process;
end;
|
<reponame>EmilyClaire/cpe233-experiment08<gh_stars>0
LIBRARY ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.all;
entity ALU is
Port (A : in std_logic_vector (7 downto 0);
B : in std_logic_vector (7 downto 0);
SEL : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Result : out std_logic_vector (7 downto 0);
C : out std_logic;
Z : out std_logic);
end ALU;
architecture Behavioral of ALU is
signal s_out : std_logic_vector (7 downto 0) := x"00";
signal s_c : std_logic := '0';
signal s_z : std_logic := '0';
begin
process (SEL, A, B, Cin)
variable v_outAndC: std_logic_vector (8 downto 0) := "000000000";
variable v_out: std_logic_vector (7 downto 0):= x"00";
begin
case SEL is
--ADD
when "0000" =>
v_outAndC := '1' & (A + B);
s_c <= v_outAndC(8);
v_out := v_outAndC(7 downto 0);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--ADDC
when "0001" =>
v_outAndC := ('0' & A) + B + Cin;
s_c <= v_outAndC(8);
v_out := v_outAndC(7 downto 0);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--SUB
when "0010" =>
v_outAndC := ('0' & A) - B;
s_c <= v_outAndC(8);
v_out := v_outAndC(7 downto 0);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--SUBC
when "0011" =>
v_outAndC := ('0' & A) - B - Cin;
s_c <= v_outAndC(8);
v_out := v_outAndC(7 downto 0);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--CMP
when "0100" =>
v_outAndC := ('0' & A) - B;
v_out := v_outAndC(7 downto 0);
s_c <= v_outAndC(8);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= A;
--AND
when "0101" =>
v_out := A and B;
s_c <= '0';
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--OR
when "0110" =>
v_out := A or B;
s_c <= '0';
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--EXOR
when "0111" =>
v_out := A xor B;
s_c <= '0';
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--TEST
when "1000" =>
v_out := A and B;
s_c <= '0';
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= A;
--LSL
when "1001" =>
v_out := A(6 downto 0) & Cin;
s_c <= A(7);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--LSR
when "1010" =>
v_out := Cin & A(7 downto 1);
s_c <= A(0);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--ROL
when "1011" =>
v_out := A(6 downto 0) & A(7);
s_c <= A(7);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--ROR
when "1100" =>
v_out := A(0) & A(7 downto 1);
s_c <= A(0);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--ASR
when "1101" =>
v_out := A(7) & A(7 downto 1);
s_c <= A(0);
if(v_out = x"00") then
s_z <= '1';
else
s_z <= '0';
end if;
s_out <= v_out;
--MOV
when "1110" =>
s_out <= B;
--Not Used
when others =>
s_out <= x"FF";
end case;
end process;
c <= s_c;
z <= s_z;
Result <= s_out;
end Behavioral;
|
<filename>Labs/03-vivado/multiplexer/multiplexer/multiplexer.srcs/sources_1/new/mux_3bit_4to1.vhd
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------
-- Entity declaration for 2-bit binary comparator
------------------------------------------------------------
entity mux_3bit_4to1 is
port(
a_i : in std_logic_vector(3 - 1 downto 0);
b_i : in std_logic_vector(3 - 1 downto 0);
c_i : in std_logic_vector(3 - 1 downto 0);
d_i : in std_logic_vector(3 - 1 downto 0)
);
end entity mux_3bit_4to1;
------------------------------------------------------------
-- Architecture body for 2-bit binary comparator
------------------------------------------------------------
architecture Behavioral of mux_3bit_4to1 is
begin
y_o <= a_i when (addr_i = "000" and en_i = '1') else
b_i when (addr_i = "001" and en_i = '1') else
c_i when (addr_i = "010" and en_i = '1') else
d_i;
end architecture Behavioral;
|
<reponame>MattisLind/Alfaskop3550InVHDL<filename>STD_TTL_LIB/TTL74198/design.vhd
-- Standard 74198 TTL shift register designed from the behavioral model in the data sheet.
library IEEE;
use IEEE.std_logic_1164.all;
entity TTL74198 is
port(
pin1_s0: in std_logic;
pin2_srsi : in std_logic;
pin3_a : in std_logic;
pin4_qA : out std_logic;
pin5_b : in std_logic;
pin6_qB : out std_logic;
pin7_c : in std_logic;
pin8_qC : out std_logic;
pin9_d : in std_logic;
pin10_qD : out std_logic;
pin11_clk: in std_logic;
pin13_clear : in std_logic;
pin14_qE : out std_logic;
pin15_e : in std_logic;
pin16_qF : out std_logic;
pin17_f : in std_logic;
pin18_qG : out std_logic;
pin19_g : in std_logic;
pin20_qH : out std_logic;
pin21_h : in std_logic;
pin22_slsi : in std_logic;
pin23_s1: in std_logic);
end TTL74198;
architecture Behavioral of TTL74198 is
signal sQA, sQB, sQC, sQD, sQE, sQF, sQG, sQH : std_logic;
begin
process(pin11_clk, pin2_srsi, pin23_s1, pin1_s0, pin3_a, pin5_b, pin7_c, pin9_d, pin15_e, pin17_f, pin19_g, pin21_h, pin22_slsi, pin13_clear, pin4_qA, pin6_qB, pin8_qC, pin10_qD, pin14_qE, pin16_qF,pin18_qG, pin20_qH) is
begin
if (pin13_clear = '0') then
sQA <= '0';
sQB <= '0';
sQC <= '0';
sQD <= '0';
sQE <= '0';
sQF <= '0';
sQG <= '0';
sQH <= '0';
elsif (pin23_s1 = '1' and pin1_s0 = '1' and rising_edge(pin11_clk)) then
sQA <= pin3_a;
sQB <= pin5_b;
sQC <= pin7_c;
sQD <= pin9_d;
sQE <= pin15_e;
sQF <= pin17_f;
sQG <= pin19_g;
sQH <= pin21_h;
elsif (pin23_s1 = '0' and pin1_s0 = '1' and rising_edge(pin11_clk)) then
sQA <= pin2_srsi;
sQB <= sQA;
sQC <= sQB;
sQD <= sQC;
sQE <= sQD;
sQF <= sQE;
sQG <= sQF;
sQH <= sQG;
elsif (pin23_s1 = '1' and pin1_s0 = '0' and rising_edge(pin11_clk)) then
sQH <= pin22_slsi;
sQG <= sQH;
sQF <= sQG;
sQE <= sQF;
sQD <= sQE;
sQC <= sQD;
sQB <= sQC;
sQA <= sQB;
end if;
end process;
pin4_qA <= sQA;
pin6_qB <= sQB;
pin8_qC <= sQC;
pin10_qD <= sQD;
pin14_qE <= sQE;
pin16_qF <= sQF;
pin18_qG <= sQG;
pin20_qH <= sQH;
end Behavioral;
|
<filename>schemtic/lib/worklib/ic/xc7a200tffg1156/entity/vhdl.vhd
-- generated by newgenasym Mon Jun 11 22:47:38 2018
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity xc7a200tffg1156 is
port (
A1: INOUT STD_LOGIC;
A10: INOUT STD_LOGIC;
A11: INOUT STD_LOGIC;
A12: INOUT STD_LOGIC;
A13: INOUT STD_LOGIC;
A14: INOUT STD_LOGIC;
A15: INOUT STD_LOGIC;
A16: INOUT STD_LOGIC;
A17: INOUT STD_LOGIC;
A18: INOUT STD_LOGIC;
A19: INOUT STD_LOGIC;
A2: INOUT STD_LOGIC;
A20: INOUT STD_LOGIC;
A21: INOUT STD_LOGIC;
A22: INOUT STD_LOGIC;
A23: INOUT STD_LOGIC;
A24: INOUT STD_LOGIC;
A25: INOUT STD_LOGIC;
A26: INOUT STD_LOGIC;
A27: INOUT STD_LOGIC;
A28: INOUT STD_LOGIC;
A29: INOUT STD_LOGIC;
A3: INOUT STD_LOGIC;
A30: INOUT STD_LOGIC;
A31: INOUT STD_LOGIC;
A32: INOUT STD_LOGIC;
A33: INOUT STD_LOGIC;
A34: INOUT STD_LOGIC;
A4: INOUT STD_LOGIC;
A5: INOUT STD_LOGIC;
A6: INOUT STD_LOGIC;
A7: INOUT STD_LOGIC;
A8: INOUT STD_LOGIC;
A9: INOUT STD_LOGIC;
AA1: INOUT STD_LOGIC;
AA10: INOUT STD_LOGIC;
AA11: INOUT STD_LOGIC;
AA12: INOUT STD_LOGIC;
AA13: INOUT STD_LOGIC;
AA14: INOUT STD_LOGIC;
AA15: INOUT STD_LOGIC;
AA16: INOUT STD_LOGIC;
AA17: INOUT STD_LOGIC;
AA18: INOUT STD_LOGIC;
AA19: INOUT STD_LOGIC;
AA2: INOUT STD_LOGIC;
AA20: INOUT STD_LOGIC;
AA21: INOUT STD_LOGIC;
AA22: INOUT STD_LOGIC;
AA23: INOUT STD_LOGIC;
AA24: INOUT STD_LOGIC;
AA25: INOUT STD_LOGIC;
AA26: INOUT STD_LOGIC;
AA27: INOUT STD_LOGIC;
AA28: INOUT STD_LOGIC;
AA29: INOUT STD_LOGIC;
AA3: INOUT STD_LOGIC;
AA30: INOUT STD_LOGIC;
AA31: INOUT STD_LOGIC;
AA32: INOUT STD_LOGIC;
AA33: INOUT STD_LOGIC;
AA34: INOUT STD_LOGIC;
AA4: INOUT STD_LOGIC;
AA5: INOUT STD_LOGIC;
AA6: INOUT STD_LOGIC;
AA7: INOUT STD_LOGIC;
AA8: INOUT STD_LOGIC;
AA9: INOUT STD_LOGIC;
AB1: INOUT STD_LOGIC;
AB10: INOUT STD_LOGIC;
AB11: INOUT STD_LOGIC;
AB12: INOUT STD_LOGIC;
AB13: INOUT STD_LOGIC;
AB14: INOUT STD_LOGIC;
AB15: INOUT STD_LOGIC;
AB16: INOUT STD_LOGIC;
AB17: INOUT STD_LOGIC;
AB18: INOUT STD_LOGIC;
AB19: INOUT STD_LOGIC;
AB2: INOUT STD_LOGIC;
AB20: INOUT STD_LOGIC;
AB21: INOUT STD_LOGIC;
AB22: INOUT STD_LOGIC;
AB23: INOUT STD_LOGIC;
AB24: INOUT STD_LOGIC;
AB25: INOUT STD_LOGIC;
AB26: INOUT STD_LOGIC;
AB27: INOUT STD_LOGIC;
AB28: INOUT STD_LOGIC;
AB29: INOUT STD_LOGIC;
AB3: INOUT STD_LOGIC;
AB30: INOUT STD_LOGIC;
AB31: INOUT STD_LOGIC;
AB32: INOUT STD_LOGIC;
AB33: INOUT STD_LOGIC;
AB34: INOUT STD_LOGIC;
AB4: INOUT STD_LOGIC;
AB5: INOUT STD_LOGIC;
AB6: INOUT STD_LOGIC;
AB7: INOUT STD_LOGIC;
AB8: INOUT STD_LOGIC;
AB9: INOUT STD_LOGIC;
AC1: INOUT STD_LOGIC;
AC10: INOUT STD_LOGIC;
AC11: INOUT STD_LOGIC;
AC12: INOUT STD_LOGIC;
AC13: INOUT STD_LOGIC;
AC14: INOUT STD_LOGIC;
AC15: INOUT STD_LOGIC;
AC16: INOUT STD_LOGIC;
AC17: INOUT STD_LOGIC;
AC18: INOUT STD_LOGIC;
AC19: INOUT STD_LOGIC;
AC2: INOUT STD_LOGIC;
AC20: INOUT STD_LOGIC;
AC21: INOUT STD_LOGIC;
AC22: INOUT STD_LOGIC;
AC23: INOUT STD_LOGIC;
AC24: INOUT STD_LOGIC;
AC25: INOUT STD_LOGIC;
AC26: INOUT STD_LOGIC;
AC27: INOUT STD_LOGIC;
AC28: INOUT STD_LOGIC;
AC29: INOUT STD_LOGIC;
AC3: INOUT STD_LOGIC;
AC30: INOUT STD_LOGIC;
AC31: INOUT STD_LOGIC;
AC32: INOUT STD_LOGIC;
AC33: INOUT STD_LOGIC;
AC34: INOUT STD_LOGIC;
AC4: INOUT STD_LOGIC;
AC5: INOUT STD_LOGIC;
AC6: INOUT STD_LOGIC;
AC7: INOUT STD_LOGIC;
AC8: INOUT STD_LOGIC;
AC9: INOUT STD_LOGIC;
AD1: INOUT STD_LOGIC;
AD10: INOUT STD_LOGIC;
AD11: INOUT STD_LOGIC;
AD12: INOUT STD_LOGIC;
AD13: INOUT STD_LOGIC;
AD14: INOUT STD_LOGIC;
AD15: INOUT STD_LOGIC;
AD16: INOUT STD_LOGIC;
AD17: INOUT STD_LOGIC;
AD18: INOUT STD_LOGIC;
AD19: INOUT STD_LOGIC;
AD2: INOUT STD_LOGIC;
AD20: INOUT STD_LOGIC;
AD21: INOUT STD_LOGIC;
AD22: INOUT STD_LOGIC;
AD23: INOUT STD_LOGIC;
AD24: INOUT STD_LOGIC;
AD25: INOUT STD_LOGIC;
AD26: INOUT STD_LOGIC;
AD27: INOUT STD_LOGIC;
AD28: INOUT STD_LOGIC;
AD29: INOUT STD_LOGIC;
AD3: INOUT STD_LOGIC;
AD30: INOUT STD_LOGIC;
AD31: INOUT STD_LOGIC;
AD32: INOUT STD_LOGIC;
AD33: INOUT STD_LOGIC;
AD34: INOUT STD_LOGIC;
AD4: INOUT STD_LOGIC;
AD5: INOUT STD_LOGIC;
AD6: INOUT STD_LOGIC;
AD7: INOUT STD_LOGIC;
AD8: INOUT STD_LOGIC;
AD9: INOUT STD_LOGIC;
AE1: INOUT STD_LOGIC;
AE10: INOUT STD_LOGIC;
AE11: INOUT STD_LOGIC;
AE12: INOUT STD_LOGIC;
AE13: INOUT STD_LOGIC;
AE14: INOUT STD_LOGIC;
AE15: INOUT STD_LOGIC;
AE16: INOUT STD_LOGIC;
AE17: INOUT STD_LOGIC;
AE18: INOUT STD_LOGIC;
AE19: INOUT STD_LOGIC;
AE2: INOUT STD_LOGIC;
AE20: INOUT STD_LOGIC;
AE21: INOUT STD_LOGIC;
AE22: INOUT STD_LOGIC;
AE23: INOUT STD_LOGIC;
AE24: INOUT STD_LOGIC;
AE25: INOUT STD_LOGIC;
AE26: INOUT STD_LOGIC;
AE27: INOUT STD_LOGIC;
AE28: INOUT STD_LOGIC;
AE29: INOUT STD_LOGIC;
AE3: INOUT STD_LOGIC;
AE30: INOUT STD_LOGIC;
AE31: INOUT STD_LOGIC;
AE32: INOUT STD_LOGIC;
AE33: INOUT STD_LOGIC;
AE34: INOUT STD_LOGIC;
AE4: INOUT STD_LOGIC;
AE5: INOUT STD_LOGIC;
AE6: INOUT STD_LOGIC;
AE7: INOUT STD_LOGIC;
AE8: INOUT STD_LOGIC;
AE9: INOUT STD_LOGIC;
AF1: INOUT STD_LOGIC;
AF10: INOUT STD_LOGIC;
AF11: INOUT STD_LOGIC;
AF12: INOUT STD_LOGIC;
AF13: INOUT STD_LOGIC;
AF14: INOUT STD_LOGIC;
AF15: INOUT STD_LOGIC;
AF16: INOUT STD_LOGIC;
AF17: INOUT STD_LOGIC;
AF18: INOUT STD_LOGIC;
AF19: INOUT STD_LOGIC;
AF2: INOUT STD_LOGIC;
AF20: INOUT STD_LOGIC;
AF21: INOUT STD_LOGIC;
AF22: INOUT STD_LOGIC;
AF23: INOUT STD_LOGIC;
AF24: INOUT STD_LOGIC;
AF25: INOUT STD_LOGIC;
AF26: INOUT STD_LOGIC;
AF27: INOUT STD_LOGIC;
AF28: INOUT STD_LOGIC;
AF29: INOUT STD_LOGIC;
AF3: INOUT STD_LOGIC;
AF30: INOUT STD_LOGIC;
AF31: INOUT STD_LOGIC;
AF32: INOUT STD_LOGIC;
AF33: INOUT STD_LOGIC;
AF34: INOUT STD_LOGIC;
AF4: INOUT STD_LOGIC;
AF5: INOUT STD_LOGIC;
AF6: INOUT STD_LOGIC;
AF7: INOUT STD_LOGIC;
AF8: INOUT STD_LOGIC;
AF9: INOUT STD_LOGIC;
AG1: INOUT STD_LOGIC;
AG10: INOUT STD_LOGIC;
AG11: INOUT STD_LOGIC;
AG12: INOUT STD_LOGIC;
AG13: INOUT STD_LOGIC;
AG14: INOUT STD_LOGIC;
AG15: INOUT STD_LOGIC;
AG16: INOUT STD_LOGIC;
AG17: INOUT STD_LOGIC;
AG18: INOUT STD_LOGIC;
AG19: INOUT STD_LOGIC;
AG2: INOUT STD_LOGIC;
AG20: INOUT STD_LOGIC;
AG21: INOUT STD_LOGIC;
AG22: INOUT STD_LOGIC;
AG23: INOUT STD_LOGIC;
AG24: INOUT STD_LOGIC;
AG25: INOUT STD_LOGIC;
AG26: INOUT STD_LOGIC;
AG27: INOUT STD_LOGIC;
AG28: INOUT STD_LOGIC;
AG29: INOUT STD_LOGIC;
AG3: INOUT STD_LOGIC;
AG30: INOUT STD_LOGIC;
AG31: INOUT STD_LOGIC;
AG32: INOUT STD_LOGIC;
AG33: INOUT STD_LOGIC;
AG34: INOUT STD_LOGIC;
AG4: INOUT STD_LOGIC;
AG5: INOUT STD_LOGIC;
AG6: INOUT STD_LOGIC;
AG7: INOUT STD_LOGIC;
AG8: INOUT STD_LOGIC;
AG9: INOUT STD_LOGIC;
AH1: INOUT STD_LOGIC;
AH10: INOUT STD_LOGIC;
AH11: INOUT STD_LOGIC;
AH12: INOUT STD_LOGIC;
AH13: INOUT STD_LOGIC;
AH14: INOUT STD_LOGIC;
AH15: INOUT STD_LOGIC;
AH16: INOUT STD_LOGIC;
AH17: INOUT STD_LOGIC;
AH18: INOUT STD_LOGIC;
AH19: INOUT STD_LOGIC;
AH2: INOUT STD_LOGIC;
AH20: INOUT STD_LOGIC;
AH21: INOUT STD_LOGIC;
AH22: INOUT STD_LOGIC;
AH23: INOUT STD_LOGIC;
AH24: INOUT STD_LOGIC;
AH25: INOUT STD_LOGIC;
AH26: INOUT STD_LOGIC;
AH27: INOUT STD_LOGIC;
AH28: INOUT STD_LOGIC;
AH29: INOUT STD_LOGIC;
AH3: INOUT STD_LOGIC;
AH30: INOUT STD_LOGIC;
AH31: INOUT STD_LOGIC;
AH32: INOUT STD_LOGIC;
AH33: INOUT STD_LOGIC;
AH34: INOUT STD_LOGIC;
AH4: INOUT STD_LOGIC;
AH5: INOUT STD_LOGIC;
AH6: INOUT STD_LOGIC;
AH7: INOUT STD_LOGIC;
AH8: INOUT STD_LOGIC;
AH9: INOUT STD_LOGIC;
AJ1: INOUT STD_LOGIC;
AJ10: INOUT STD_LOGIC;
AJ11: INOUT STD_LOGIC;
AJ12: INOUT STD_LOGIC;
AJ13: INOUT STD_LOGIC;
AJ14: INOUT STD_LOGIC;
AJ15: INOUT STD_LOGIC;
AJ16: INOUT STD_LOGIC;
AJ17: INOUT STD_LOGIC;
AJ18: INOUT STD_LOGIC;
AJ19: INOUT STD_LOGIC;
AJ2: INOUT STD_LOGIC;
AJ20: INOUT STD_LOGIC;
AJ21: INOUT STD_LOGIC;
AJ22: INOUT STD_LOGIC;
AJ23: INOUT STD_LOGIC;
AJ24: INOUT STD_LOGIC;
AJ25: INOUT STD_LOGIC;
AJ26: INOUT STD_LOGIC;
AJ27: INOUT STD_LOGIC;
AJ28: INOUT STD_LOGIC;
AJ29: INOUT STD_LOGIC;
AJ3: INOUT STD_LOGIC;
AJ30: INOUT STD_LOGIC;
AJ31: INOUT STD_LOGIC;
AJ32: INOUT STD_LOGIC;
AJ33: INOUT STD_LOGIC;
AJ34: INOUT STD_LOGIC;
AJ4: INOUT STD_LOGIC;
AJ5: INOUT STD_LOGIC;
AJ6: INOUT STD_LOGIC;
AJ7: INOUT STD_LOGIC;
AJ8: INOUT STD_LOGIC;
AJ9: INOUT STD_LOGIC;
AK1: INOUT STD_LOGIC;
AK10: INOUT STD_LOGIC;
AK11: INOUT STD_LOGIC;
AK12: INOUT STD_LOGIC;
AK13: INOUT STD_LOGIC;
AK14: INOUT STD_LOGIC;
AK15: INOUT STD_LOGIC;
AK16: INOUT STD_LOGIC;
AK17: INOUT STD_LOGIC;
AK18: INOUT STD_LOGIC;
AK19: INOUT STD_LOGIC;
AK2: INOUT STD_LOGIC;
AK20: INOUT STD_LOGIC;
AK21: INOUT STD_LOGIC;
AK22: INOUT STD_LOGIC;
AK23: INOUT STD_LOGIC;
AK24: INOUT STD_LOGIC;
AK25: INOUT STD_LOGIC;
AK26: INOUT STD_LOGIC;
AK27: INOUT STD_LOGIC;
AK28: INOUT STD_LOGIC;
AK29: INOUT STD_LOGIC;
AK3: INOUT STD_LOGIC;
AK30: INOUT STD_LOGIC;
AK31: INOUT STD_LOGIC;
AK32: INOUT STD_LOGIC;
AK33: INOUT STD_LOGIC;
AK34: INOUT STD_LOGIC;
AK4: INOUT STD_LOGIC;
AK5: INOUT STD_LOGIC;
AK6: INOUT STD_LOGIC;
AK7: INOUT STD_LOGIC;
AK8: INOUT STD_LOGIC;
AK9: INOUT STD_LOGIC;
AL1: INOUT STD_LOGIC;
AL10: INOUT STD_LOGIC;
AL11: INOUT STD_LOGIC;
AL12: INOUT STD_LOGIC;
AL13: INOUT STD_LOGIC;
AL14: INOUT STD_LOGIC;
AL15: INOUT STD_LOGIC;
AL16: INOUT STD_LOGIC;
AL17: INOUT STD_LOGIC;
AL18: INOUT STD_LOGIC;
AL19: INOUT STD_LOGIC;
AL2: INOUT STD_LOGIC;
AL20: INOUT STD_LOGIC;
AL21: INOUT STD_LOGIC;
AL22: INOUT STD_LOGIC;
AL23: INOUT STD_LOGIC;
AL24: INOUT STD_LOGIC;
AL25: INOUT STD_LOGIC;
AL26: INOUT STD_LOGIC;
AL27: INOUT STD_LOGIC;
AL28: INOUT STD_LOGIC;
AL29: INOUT STD_LOGIC;
AL3: INOUT STD_LOGIC;
AL30: INOUT STD_LOGIC;
AL31: INOUT STD_LOGIC;
AL32: INOUT STD_LOGIC;
AL33: INOUT STD_LOGIC;
AL34: INOUT STD_LOGIC;
AL4: INOUT STD_LOGIC;
AL5: INOUT STD_LOGIC;
AL6: INOUT STD_LOGIC;
AL7: INOUT STD_LOGIC;
AL8: INOUT STD_LOGIC;
AL9: INOUT STD_LOGIC;
AM1: INOUT STD_LOGIC;
AM10: INOUT STD_LOGIC;
AM11: INOUT STD_LOGIC;
AM12: INOUT STD_LOGIC;
AM13: INOUT STD_LOGIC;
AM14: INOUT STD_LOGIC;
AM15: INOUT STD_LOGIC;
AM16: INOUT STD_LOGIC;
AM17: INOUT STD_LOGIC;
AM18: INOUT STD_LOGIC;
AM19: INOUT STD_LOGIC;
AM2: INOUT STD_LOGIC;
AM20: INOUT STD_LOGIC;
AM21: INOUT STD_LOGIC;
AM22: INOUT STD_LOGIC;
AM23: INOUT STD_LOGIC;
AM24: INOUT STD_LOGIC;
AM25: INOUT STD_LOGIC;
AM26: INOUT STD_LOGIC;
AM27: INOUT STD_LOGIC;
AM28: INOUT STD_LOGIC;
AM29: INOUT STD_LOGIC;
AM3: INOUT STD_LOGIC;
AM30: INOUT STD_LOGIC;
AM31: INOUT STD_LOGIC;
AM32: INOUT STD_LOGIC;
AM33: INOUT STD_LOGIC;
AM34: INOUT STD_LOGIC;
AM4: INOUT STD_LOGIC;
AM5: INOUT STD_LOGIC;
AM6: INOUT STD_LOGIC;
AM7: INOUT STD_LOGIC;
AM8: INOUT STD_LOGIC;
AM9: INOUT STD_LOGIC;
AN1: INOUT STD_LOGIC;
AN10: INOUT STD_LOGIC;
AN11: INOUT STD_LOGIC;
AN12: INOUT STD_LOGIC;
AN13: INOUT STD_LOGIC;
AN14: INOUT STD_LOGIC;
AN15: INOUT STD_LOGIC;
AN16: INOUT STD_LOGIC;
AN17: INOUT STD_LOGIC;
AN18: INOUT STD_LOGIC;
AN19: INOUT STD_LOGIC;
AN2: INOUT STD_LOGIC;
AN20: INOUT STD_LOGIC;
AN21: INOUT STD_LOGIC;
AN22: INOUT STD_LOGIC;
AN23: INOUT STD_LOGIC;
AN24: INOUT STD_LOGIC;
AN25: INOUT STD_LOGIC;
AN26: INOUT STD_LOGIC;
AN27: INOUT STD_LOGIC;
AN28: INOUT STD_LOGIC;
AN29: INOUT STD_LOGIC;
AN3: INOUT STD_LOGIC;
AN30: INOUT STD_LOGIC;
AN31: INOUT STD_LOGIC;
AN32: INOUT STD_LOGIC;
AN33: INOUT STD_LOGIC;
AN34: INOUT STD_LOGIC;
AN4: INOUT STD_LOGIC;
AN5: INOUT STD_LOGIC;
AN6: INOUT STD_LOGIC;
AN7: INOUT STD_LOGIC;
AN8: INOUT STD_LOGIC;
AN9: INOUT STD_LOGIC;
AP1: INOUT STD_LOGIC;
AP10: INOUT STD_LOGIC;
AP11: INOUT STD_LOGIC;
AP12: INOUT STD_LOGIC;
AP13: INOUT STD_LOGIC;
AP14: INOUT STD_LOGIC;
AP15: INOUT STD_LOGIC;
AP16: INOUT STD_LOGIC;
AP17: INOUT STD_LOGIC;
AP18: INOUT STD_LOGIC;
AP19: INOUT STD_LOGIC;
AP2: INOUT STD_LOGIC;
AP20: INOUT STD_LOGIC;
AP21: INOUT STD_LOGIC;
AP22: INOUT STD_LOGIC;
AP23: INOUT STD_LOGIC;
AP24: INOUT STD_LOGIC;
AP25: INOUT STD_LOGIC;
AP26: INOUT STD_LOGIC;
AP27: INOUT STD_LOGIC;
AP28: INOUT STD_LOGIC;
AP29: INOUT STD_LOGIC;
AP3: INOUT STD_LOGIC;
AP30: INOUT STD_LOGIC;
AP31: INOUT STD_LOGIC;
AP32: INOUT STD_LOGIC;
AP33: INOUT STD_LOGIC;
AP34: INOUT STD_LOGIC;
AP4: INOUT STD_LOGIC;
AP5: INOUT STD_LOGIC;
AP6: INOUT STD_LOGIC;
AP7: INOUT STD_LOGIC;
AP8: INOUT STD_LOGIC;
AP9: INOUT STD_LOGIC;
B1: INOUT STD_LOGIC;
B10: INOUT STD_LOGIC;
B11: INOUT STD_LOGIC;
B12: INOUT STD_LOGIC;
B13: INOUT STD_LOGIC;
B14: INOUT STD_LOGIC;
B15: INOUT STD_LOGIC;
B16: INOUT STD_LOGIC;
B17: INOUT STD_LOGIC;
B18: INOUT STD_LOGIC;
B19: INOUT STD_LOGIC;
B2: INOUT STD_LOGIC;
B20: INOUT STD_LOGIC;
B21: INOUT STD_LOGIC;
B22: INOUT STD_LOGIC;
B23: INOUT STD_LOGIC;
B24: INOUT STD_LOGIC;
B25: INOUT STD_LOGIC;
B26: INOUT STD_LOGIC;
B27: INOUT STD_LOGIC;
B28: INOUT STD_LOGIC;
B29: INOUT STD_LOGIC;
B3: INOUT STD_LOGIC;
B30: INOUT STD_LOGIC;
B31: INOUT STD_LOGIC;
B32: INOUT STD_LOGIC;
B33: INOUT STD_LOGIC;
B34: INOUT STD_LOGIC;
B4: INOUT STD_LOGIC;
B5: INOUT STD_LOGIC;
B6: INOUT STD_LOGIC;
B7: INOUT STD_LOGIC;
B8: INOUT STD_LOGIC;
B9: INOUT STD_LOGIC;
C1: INOUT STD_LOGIC;
C10: INOUT STD_LOGIC;
C11: INOUT STD_LOGIC;
C12: INOUT STD_LOGIC;
C13: INOUT STD_LOGIC;
C14: INOUT STD_LOGIC;
C15: INOUT STD_LOGIC;
C16: INOUT STD_LOGIC;
C17: INOUT STD_LOGIC;
C18: INOUT STD_LOGIC;
C19: INOUT STD_LOGIC;
C2: INOUT STD_LOGIC;
C20: INOUT STD_LOGIC;
C21: INOUT STD_LOGIC;
C22: INOUT STD_LOGIC;
C23: INOUT STD_LOGIC;
C24: INOUT STD_LOGIC;
C25: INOUT STD_LOGIC;
C26: INOUT STD_LOGIC;
C27: INOUT STD_LOGIC;
C28: INOUT STD_LOGIC;
C29: INOUT STD_LOGIC;
C3: INOUT STD_LOGIC;
C30: INOUT STD_LOGIC;
C31: INOUT STD_LOGIC;
C32: INOUT STD_LOGIC;
C33: INOUT STD_LOGIC;
C34: INOUT STD_LOGIC;
C4: INOUT STD_LOGIC;
C5: INOUT STD_LOGIC;
C6: INOUT STD_LOGIC;
C7: INOUT STD_LOGIC;
C8: INOUT STD_LOGIC;
C9: INOUT STD_LOGIC;
D1: INOUT STD_LOGIC;
D10: INOUT STD_LOGIC;
D11: INOUT STD_LOGIC;
D12: INOUT STD_LOGIC;
D13: INOUT STD_LOGIC;
D14: INOUT STD_LOGIC;
D15: INOUT STD_LOGIC;
D16: INOUT STD_LOGIC;
D17: INOUT STD_LOGIC;
D18: INOUT STD_LOGIC;
D19: INOUT STD_LOGIC;
D2: INOUT STD_LOGIC;
D20: INOUT STD_LOGIC;
D21: INOUT STD_LOGIC;
D22: INOUT STD_LOGIC;
D23: INOUT STD_LOGIC;
D24: INOUT STD_LOGIC;
D25: INOUT STD_LOGIC;
D26: INOUT STD_LOGIC;
D27: INOUT STD_LOGIC;
D28: INOUT STD_LOGIC;
D29: INOUT STD_LOGIC;
D3: INOUT STD_LOGIC;
D30: INOUT STD_LOGIC;
D31: INOUT STD_LOGIC;
D32: INOUT STD_LOGIC;
D33: INOUT STD_LOGIC;
D34: INOUT STD_LOGIC;
D4: INOUT STD_LOGIC;
D5: INOUT STD_LOGIC;
D6: INOUT STD_LOGIC;
D7: INOUT STD_LOGIC;
D8: INOUT STD_LOGIC;
D9: INOUT STD_LOGIC;
E1: INOUT STD_LOGIC;
E10: INOUT STD_LOGIC;
E11: INOUT STD_LOGIC;
E12: INOUT STD_LOGIC;
E13: INOUT STD_LOGIC;
E14: INOUT STD_LOGIC;
E15: INOUT STD_LOGIC;
E16: INOUT STD_LOGIC;
E17: INOUT STD_LOGIC;
E18: INOUT STD_LOGIC;
E19: INOUT STD_LOGIC;
E2: INOUT STD_LOGIC;
E20: INOUT STD_LOGIC;
E21: INOUT STD_LOGIC;
E22: INOUT STD_LOGIC;
E23: INOUT STD_LOGIC;
E24: INOUT STD_LOGIC;
E25: INOUT STD_LOGIC;
E26: INOUT STD_LOGIC;
E27: INOUT STD_LOGIC;
E28: INOUT STD_LOGIC;
E29: INOUT STD_LOGIC;
E3: INOUT STD_LOGIC;
E30: INOUT STD_LOGIC;
E31: INOUT STD_LOGIC;
E32: INOUT STD_LOGIC;
E33: INOUT STD_LOGIC;
E34: INOUT STD_LOGIC;
E4: INOUT STD_LOGIC;
E5: INOUT STD_LOGIC;
E6: INOUT STD_LOGIC;
E7: INOUT STD_LOGIC;
E8: INOUT STD_LOGIC;
E9: INOUT STD_LOGIC;
F1: INOUT STD_LOGIC;
F10: INOUT STD_LOGIC;
F11: INOUT STD_LOGIC;
F12: INOUT STD_LOGIC;
F13: INOUT STD_LOGIC;
F14: INOUT STD_LOGIC;
F15: INOUT STD_LOGIC;
F16: INOUT STD_LOGIC;
F17: INOUT STD_LOGIC;
F18: INOUT STD_LOGIC;
F19: INOUT STD_LOGIC;
F2: INOUT STD_LOGIC;
F20: INOUT STD_LOGIC;
F21: INOUT STD_LOGIC;
F22: INOUT STD_LOGIC;
F23: INOUT STD_LOGIC;
F24: INOUT STD_LOGIC;
F25: INOUT STD_LOGIC;
F26: INOUT STD_LOGIC;
F27: INOUT STD_LOGIC;
F28: INOUT STD_LOGIC;
F29: INOUT STD_LOGIC;
F3: INOUT STD_LOGIC;
F30: INOUT STD_LOGIC;
F31: INOUT STD_LOGIC;
F32: INOUT STD_LOGIC;
F33: INOUT STD_LOGIC;
F34: INOUT STD_LOGIC;
F4: INOUT STD_LOGIC;
F5: INOUT STD_LOGIC;
F6: INOUT STD_LOGIC;
F7: INOUT STD_LOGIC;
F8: INOUT STD_LOGIC;
F9: INOUT STD_LOGIC;
G1: INOUT STD_LOGIC;
G10: INOUT STD_LOGIC;
G11: INOUT STD_LOGIC;
G12: INOUT STD_LOGIC;
G13: INOUT STD_LOGIC;
G14: INOUT STD_LOGIC;
G15: INOUT STD_LOGIC;
G16: INOUT STD_LOGIC;
G17: INOUT STD_LOGIC;
G18: INOUT STD_LOGIC;
G19: INOUT STD_LOGIC;
G2: INOUT STD_LOGIC;
G20: INOUT STD_LOGIC;
G21: INOUT STD_LOGIC;
G22: INOUT STD_LOGIC;
G23: INOUT STD_LOGIC;
G24: INOUT STD_LOGIC;
G25: INOUT STD_LOGIC;
G26: INOUT STD_LOGIC;
G27: INOUT STD_LOGIC;
G28: INOUT STD_LOGIC;
G29: INOUT STD_LOGIC;
G3: INOUT STD_LOGIC;
G30: INOUT STD_LOGIC;
G31: INOUT STD_LOGIC;
G32: INOUT STD_LOGIC;
G33: INOUT STD_LOGIC;
G34: INOUT STD_LOGIC;
G4: INOUT STD_LOGIC;
G5: INOUT STD_LOGIC;
G6: INOUT STD_LOGIC;
G7: INOUT STD_LOGIC;
G8: INOUT STD_LOGIC;
G9: INOUT STD_LOGIC;
H1: INOUT STD_LOGIC;
H10: INOUT STD_LOGIC;
H11: INOUT STD_LOGIC;
H12: INOUT STD_LOGIC;
H13: INOUT STD_LOGIC;
H14: INOUT STD_LOGIC;
H15: INOUT STD_LOGIC;
H16: INOUT STD_LOGIC;
H17: INOUT STD_LOGIC;
H18: INOUT STD_LOGIC;
H19: INOUT STD_LOGIC;
H2: INOUT STD_LOGIC;
H20: INOUT STD_LOGIC;
H21: INOUT STD_LOGIC;
H22: INOUT STD_LOGIC;
H23: INOUT STD_LOGIC;
H24: INOUT STD_LOGIC;
H25: INOUT STD_LOGIC;
H26: INOUT STD_LOGIC;
H27: INOUT STD_LOGIC;
H28: INOUT STD_LOGIC;
H29: INOUT STD_LOGIC;
H3: INOUT STD_LOGIC;
H30: INOUT STD_LOGIC;
H31: INOUT STD_LOGIC;
H32: INOUT STD_LOGIC;
H33: INOUT STD_LOGIC;
H34: INOUT STD_LOGIC;
H4: INOUT STD_LOGIC;
H5: INOUT STD_LOGIC;
H6: INOUT STD_LOGIC;
H7: INOUT STD_LOGIC;
H8: INOUT STD_LOGIC;
H9: INOUT STD_LOGIC;
J1: INOUT STD_LOGIC;
J10: INOUT STD_LOGIC;
J11: INOUT STD_LOGIC;
J12: INOUT STD_LOGIC;
J13: INOUT STD_LOGIC;
J14: INOUT STD_LOGIC;
J15: INOUT STD_LOGIC;
J16: INOUT STD_LOGIC;
J17: INOUT STD_LOGIC;
J18: INOUT STD_LOGIC;
J19: INOUT STD_LOGIC;
J2: INOUT STD_LOGIC;
J20: INOUT STD_LOGIC;
J21: INOUT STD_LOGIC;
J22: INOUT STD_LOGIC;
J23: INOUT STD_LOGIC;
J24: INOUT STD_LOGIC;
J25: INOUT STD_LOGIC;
J26: INOUT STD_LOGIC;
J27: INOUT STD_LOGIC;
J28: INOUT STD_LOGIC;
J29: INOUT STD_LOGIC;
J3: INOUT STD_LOGIC;
J30: INOUT STD_LOGIC;
J31: INOUT STD_LOGIC;
J32: INOUT STD_LOGIC;
J33: INOUT STD_LOGIC;
J34: INOUT STD_LOGIC;
J4: INOUT STD_LOGIC;
J5: INOUT STD_LOGIC;
J6: INOUT STD_LOGIC;
J7: INOUT STD_LOGIC;
J8: INOUT STD_LOGIC;
J9: INOUT STD_LOGIC;
K1: INOUT STD_LOGIC;
K10: INOUT STD_LOGIC;
K11: INOUT STD_LOGIC;
K12: INOUT STD_LOGIC;
K13: INOUT STD_LOGIC;
K14: INOUT STD_LOGIC;
K15: INOUT STD_LOGIC;
K16: INOUT STD_LOGIC;
K17: INOUT STD_LOGIC;
K18: INOUT STD_LOGIC;
K19: INOUT STD_LOGIC;
K2: INOUT STD_LOGIC;
K20: INOUT STD_LOGIC;
K21: INOUT STD_LOGIC;
K22: INOUT STD_LOGIC;
K23: INOUT STD_LOGIC;
K24: INOUT STD_LOGIC;
K25: INOUT STD_LOGIC;
K26: INOUT STD_LOGIC;
K27: INOUT STD_LOGIC;
K28: INOUT STD_LOGIC;
K29: INOUT STD_LOGIC;
K3: INOUT STD_LOGIC;
K30: INOUT STD_LOGIC;
K31: INOUT STD_LOGIC;
K32: INOUT STD_LOGIC;
K33: INOUT STD_LOGIC;
K34: INOUT STD_LOGIC;
K4: INOUT STD_LOGIC;
K5: INOUT STD_LOGIC;
K6: INOUT STD_LOGIC;
K7: INOUT STD_LOGIC;
K8: INOUT STD_LOGIC;
K9: INOUT STD_LOGIC;
L1: INOUT STD_LOGIC;
L10: INOUT STD_LOGIC;
L11: INOUT STD_LOGIC;
L12: INOUT STD_LOGIC;
L13: INOUT STD_LOGIC;
L14: INOUT STD_LOGIC;
L15: INOUT STD_LOGIC;
L16: INOUT STD_LOGIC;
L17: INOUT STD_LOGIC;
L18: INOUT STD_LOGIC;
L19: INOUT STD_LOGIC;
L2: INOUT STD_LOGIC;
L20: INOUT STD_LOGIC;
L21: INOUT STD_LOGIC;
L22: INOUT STD_LOGIC;
L23: INOUT STD_LOGIC;
L24: INOUT STD_LOGIC;
L25: INOUT STD_LOGIC;
L26: INOUT STD_LOGIC;
L27: INOUT STD_LOGIC;
L28: INOUT STD_LOGIC;
L29: INOUT STD_LOGIC;
L3: INOUT STD_LOGIC;
L30: INOUT STD_LOGIC;
L31: INOUT STD_LOGIC;
L32: INOUT STD_LOGIC;
L33: INOUT STD_LOGIC;
L34: INOUT STD_LOGIC;
L4: INOUT STD_LOGIC;
L5: INOUT STD_LOGIC;
L6: INOUT STD_LOGIC;
L7: INOUT STD_LOGIC;
L8: INOUT STD_LOGIC;
L9: INOUT STD_LOGIC;
M1: INOUT STD_LOGIC;
M10: INOUT STD_LOGIC;
M11: INOUT STD_LOGIC;
M12: INOUT STD_LOGIC;
M13: INOUT STD_LOGIC;
M14: INOUT STD_LOGIC;
M15: INOUT STD_LOGIC;
M16: INOUT STD_LOGIC;
M17: INOUT STD_LOGIC;
M18: INOUT STD_LOGIC;
M19: INOUT STD_LOGIC;
M2: INOUT STD_LOGIC;
M20: INOUT STD_LOGIC;
M21: INOUT STD_LOGIC;
M22: INOUT STD_LOGIC;
M23: INOUT STD_LOGIC;
M24: INOUT STD_LOGIC;
M25: INOUT STD_LOGIC;
M26: INOUT STD_LOGIC;
M27: INOUT STD_LOGIC;
M28: INOUT STD_LOGIC;
M29: INOUT STD_LOGIC;
M3: INOUT STD_LOGIC;
M30: INOUT STD_LOGIC;
M31: INOUT STD_LOGIC;
M32: INOUT STD_LOGIC;
M33: INOUT STD_LOGIC;
M34: INOUT STD_LOGIC;
M4: INOUT STD_LOGIC;
M5: INOUT STD_LOGIC;
M6: INOUT STD_LOGIC;
M7: INOUT STD_LOGIC;
M8: INOUT STD_LOGIC;
M9: INOUT STD_LOGIC;
N1: INOUT STD_LOGIC;
N10: INOUT STD_LOGIC;
N11: INOUT STD_LOGIC;
N12: INOUT STD_LOGIC;
N13: INOUT STD_LOGIC;
N14: INOUT STD_LOGIC;
N15: INOUT STD_LOGIC;
N16: INOUT STD_LOGIC;
N17: INOUT STD_LOGIC;
N18: INOUT STD_LOGIC;
N19: INOUT STD_LOGIC;
N2: INOUT STD_LOGIC;
N20: INOUT STD_LOGIC;
N21: INOUT STD_LOGIC;
N22: INOUT STD_LOGIC;
N23: INOUT STD_LOGIC;
N24: INOUT STD_LOGIC;
N25: INOUT STD_LOGIC;
N26: INOUT STD_LOGIC;
N27: INOUT STD_LOGIC;
N28: INOUT STD_LOGIC;
N29: INOUT STD_LOGIC;
N3: INOUT STD_LOGIC;
N30: INOUT STD_LOGIC;
N31: INOUT STD_LOGIC;
N32: INOUT STD_LOGIC;
N33: INOUT STD_LOGIC;
N34: INOUT STD_LOGIC;
N4: INOUT STD_LOGIC;
N5: INOUT STD_LOGIC;
N6: INOUT STD_LOGIC;
N7: INOUT STD_LOGIC;
N8: INOUT STD_LOGIC;
N9: INOUT STD_LOGIC;
P1: INOUT STD_LOGIC;
P10: INOUT STD_LOGIC;
P11: INOUT STD_LOGIC;
P12: INOUT STD_LOGIC;
P13: INOUT STD_LOGIC;
P14: INOUT STD_LOGIC;
P15: INOUT STD_LOGIC;
P16: INOUT STD_LOGIC;
P17: INOUT STD_LOGIC;
P18: INOUT STD_LOGIC;
P19: INOUT STD_LOGIC;
P2: INOUT STD_LOGIC;
P20: INOUT STD_LOGIC;
P21: INOUT STD_LOGIC;
P22: INOUT STD_LOGIC;
P23: INOUT STD_LOGIC;
P24: INOUT STD_LOGIC;
P25: INOUT STD_LOGIC;
P26: INOUT STD_LOGIC;
P27: INOUT STD_LOGIC;
P28: INOUT STD_LOGIC;
P29: INOUT STD_LOGIC;
P3: INOUT STD_LOGIC;
P30: INOUT STD_LOGIC;
P31: INOUT STD_LOGIC;
P32: INOUT STD_LOGIC;
P33: INOUT STD_LOGIC;
P34: INOUT STD_LOGIC;
P4: INOUT STD_LOGIC;
P5: INOUT STD_LOGIC;
P6: INOUT STD_LOGIC;
P7: INOUT STD_LOGIC;
P8: INOUT STD_LOGIC;
P9: INOUT STD_LOGIC;
R1: INOUT STD_LOGIC;
R10: INOUT STD_LOGIC;
R11: INOUT STD_LOGIC;
R12: INOUT STD_LOGIC;
R13: INOUT STD_LOGIC;
R14: INOUT STD_LOGIC;
R15: INOUT STD_LOGIC;
R16: INOUT STD_LOGIC;
R17: INOUT STD_LOGIC;
R18: INOUT STD_LOGIC;
R19: INOUT STD_LOGIC;
R2: INOUT STD_LOGIC;
R20: INOUT STD_LOGIC;
R21: INOUT STD_LOGIC;
R22: INOUT STD_LOGIC;
R23: INOUT STD_LOGIC;
R24: INOUT STD_LOGIC;
R25: INOUT STD_LOGIC;
R26: INOUT STD_LOGIC;
R27: INOUT STD_LOGIC;
R28: INOUT STD_LOGIC;
R29: INOUT STD_LOGIC;
R3: INOUT STD_LOGIC;
R30: INOUT STD_LOGIC;
R31: INOUT STD_LOGIC;
R32: INOUT STD_LOGIC;
R33: INOUT STD_LOGIC;
R34: INOUT STD_LOGIC;
R4: INOUT STD_LOGIC;
R5: INOUT STD_LOGIC;
R6: INOUT STD_LOGIC;
R7: INOUT STD_LOGIC;
R8: INOUT STD_LOGIC;
R9: INOUT STD_LOGIC;
T1: INOUT STD_LOGIC;
T10: INOUT STD_LOGIC;
T11: INOUT STD_LOGIC;
T12: INOUT STD_LOGIC;
T13: INOUT STD_LOGIC;
T14: INOUT STD_LOGIC;
T15: INOUT STD_LOGIC;
T16: INOUT STD_LOGIC;
T17: INOUT STD_LOGIC;
T18: INOUT STD_LOGIC;
T19: INOUT STD_LOGIC;
T2: INOUT STD_LOGIC;
T20: INOUT STD_LOGIC;
T21: INOUT STD_LOGIC;
T22: INOUT STD_LOGIC;
T23: INOUT STD_LOGIC;
T24: INOUT STD_LOGIC;
T25: INOUT STD_LOGIC;
T26: INOUT STD_LOGIC;
T27: INOUT STD_LOGIC;
T28: INOUT STD_LOGIC;
T29: INOUT STD_LOGIC;
T3: INOUT STD_LOGIC;
T30: INOUT STD_LOGIC;
T31: INOUT STD_LOGIC;
T32: INOUT STD_LOGIC;
T33: INOUT STD_LOGIC;
T34: INOUT STD_LOGIC;
T4: INOUT STD_LOGIC;
T5: INOUT STD_LOGIC;
T6: INOUT STD_LOGIC;
T7: INOUT STD_LOGIC;
T8: INOUT STD_LOGIC;
T9: INOUT STD_LOGIC;
U1: INOUT STD_LOGIC;
U10: INOUT STD_LOGIC;
U11: INOUT STD_LOGIC;
U12: INOUT STD_LOGIC;
U13: INOUT STD_LOGIC;
U14: INOUT STD_LOGIC;
U15: INOUT STD_LOGIC;
U16: INOUT STD_LOGIC;
U17: INOUT STD_LOGIC;
U18: INOUT STD_LOGIC;
U19: INOUT STD_LOGIC;
U2: INOUT STD_LOGIC;
U20: INOUT STD_LOGIC;
U21: INOUT STD_LOGIC;
U22: INOUT STD_LOGIC;
U23: INOUT STD_LOGIC;
U24: INOUT STD_LOGIC;
U25: INOUT STD_LOGIC;
U26: INOUT STD_LOGIC;
U27: INOUT STD_LOGIC;
U28: INOUT STD_LOGIC;
U29: INOUT STD_LOGIC;
U3: INOUT STD_LOGIC;
U30: INOUT STD_LOGIC;
U31: INOUT STD_LOGIC;
U32: INOUT STD_LOGIC;
U33: INOUT STD_LOGIC;
U34: INOUT STD_LOGIC;
U4: INOUT STD_LOGIC;
U5: INOUT STD_LOGIC;
U6: INOUT STD_LOGIC;
U7: INOUT STD_LOGIC;
U8: INOUT STD_LOGIC;
U9: INOUT STD_LOGIC;
V1: INOUT STD_LOGIC;
V10: INOUT STD_LOGIC;
V11: INOUT STD_LOGIC;
V12: INOUT STD_LOGIC;
V13: INOUT STD_LOGIC;
V14: INOUT STD_LOGIC;
V15: INOUT STD_LOGIC;
V16: INOUT STD_LOGIC;
V17: INOUT STD_LOGIC;
V18: INOUT STD_LOGIC;
V19: INOUT STD_LOGIC;
V2: INOUT STD_LOGIC;
V20: INOUT STD_LOGIC;
V21: INOUT STD_LOGIC;
V22: INOUT STD_LOGIC;
V23: INOUT STD_LOGIC;
V24: INOUT STD_LOGIC;
V25: INOUT STD_LOGIC;
V26: INOUT STD_LOGIC;
V27: INOUT STD_LOGIC;
V28: INOUT STD_LOGIC;
V29: INOUT STD_LOGIC;
V3: INOUT STD_LOGIC;
V30: INOUT STD_LOGIC;
V31: INOUT STD_LOGIC;
V32: INOUT STD_LOGIC;
V33: INOUT STD_LOGIC;
V34: INOUT STD_LOGIC;
V4: INOUT STD_LOGIC;
V5: INOUT STD_LOGIC;
V6: INOUT STD_LOGIC;
V7: INOUT STD_LOGIC;
V8: INOUT STD_LOGIC;
V9: INOUT STD_LOGIC;
W1: INOUT STD_LOGIC;
W10: INOUT STD_LOGIC;
W11: INOUT STD_LOGIC;
W12: INOUT STD_LOGIC;
W13: INOUT STD_LOGIC;
W14: INOUT STD_LOGIC;
W15: INOUT STD_LOGIC;
W16: INOUT STD_LOGIC;
W17: INOUT STD_LOGIC;
W18: INOUT STD_LOGIC;
W19: INOUT STD_LOGIC;
W2: INOUT STD_LOGIC;
W20: INOUT STD_LOGIC;
W21: INOUT STD_LOGIC;
W22: INOUT STD_LOGIC;
W23: INOUT STD_LOGIC;
W24: INOUT STD_LOGIC;
W25: INOUT STD_LOGIC;
W26: INOUT STD_LOGIC;
W27: INOUT STD_LOGIC;
W28: INOUT STD_LOGIC;
W29: INOUT STD_LOGIC;
W3: INOUT STD_LOGIC;
W30: INOUT STD_LOGIC;
W31: INOUT STD_LOGIC;
W32: INOUT STD_LOGIC;
W33: INOUT STD_LOGIC;
W34: INOUT STD_LOGIC;
W4: INOUT STD_LOGIC;
W5: INOUT STD_LOGIC;
W6: INOUT STD_LOGIC;
W7: INOUT STD_LOGIC;
W8: INOUT STD_LOGIC;
W9: INOUT STD_LOGIC;
Y1: INOUT STD_LOGIC;
Y10: INOUT STD_LOGIC;
Y11: INOUT STD_LOGIC;
Y12: INOUT STD_LOGIC;
Y13: INOUT STD_LOGIC;
Y14: INOUT STD_LOGIC;
Y15: INOUT STD_LOGIC;
Y16: INOUT STD_LOGIC;
Y17: INOUT STD_LOGIC;
Y18: INOUT STD_LOGIC;
Y19: INOUT STD_LOGIC;
Y2: INOUT STD_LOGIC;
Y20: INOUT STD_LOGIC;
Y21: INOUT STD_LOGIC;
Y22: INOUT STD_LOGIC;
Y23: INOUT STD_LOGIC;
Y24: INOUT STD_LOGIC;
Y25: INOUT STD_LOGIC;
Y26: INOUT STD_LOGIC;
Y27: INOUT STD_LOGIC;
Y28: INOUT STD_LOGIC;
Y29: INOUT STD_LOGIC;
Y3: INOUT STD_LOGIC;
Y30: INOUT STD_LOGIC;
Y31: INOUT STD_LOGIC;
Y32: INOUT STD_LOGIC;
Y33: INOUT STD_LOGIC;
Y34: INOUT STD_LOGIC;
Y4: INOUT STD_LOGIC;
Y5: INOUT STD_LOGIC;
Y6: INOUT STD_LOGIC;
Y7: INOUT STD_LOGIC;
Y8: INOUT STD_LOGIC;
Y9: INOUT STD_LOGIC);
end xc7a200tffg1156;
|
library ieee;
use ieee.std_logic_1164.all;
entity tictactoe is
port (x : in std_logic_vector (8 downto 0);
o : in std_logic_vector (8 downto 0);
newx : out std_logic_vector(8 downto 0);
error : out std_logic;
full : out std_logic;
winX : out std_logic;
winO : out std_logic;
noWin : out std_logic);
end tictactoe;
architecture game of tictactoe is
signal sigf, sige, sigx, sigo : std_logic;
signal xmove, tempx : std_logic_vector(8 downto 0);
component sub_error is
port (x : in std_logic_vector (8 downto 0); o : in std_logic_vector (8 downto 0); error: out std_logic);
end component;
component sub_win is
port (a: in std_logic_vector (8 downto 0); win : out std_logic);
end component;
component sub_full is
port (y : in std_logic_vector (8 downto 0); u : in std_logic_vector (8 downto 0); full : out std_logic);
end component;
component MoveGen is
port (x : in std_logic_vector(8 downto 0); o : in std_logic_vector(8 downto 0); newX : out std_logic_vector(8 downto 0));
end component;
--component PanelDisplay is
-- port (clk : in std_logic; rst : in std_logic; x : in std_logic_vector(8 downto 0); o : in std_logic_vector(8 downto 0); hsync : out std_logic; vsync : out std_logic; red : out std_logic_vector (3 downto 0); green : out std_logic_vector (3 downto 0); blue : out std_logic_vector (3 downto 0));
--end component;
begin
mg : MoveGen port map(x => x, o => o, newx => xmove);
tempx <= x AND xmove;
se: sub_error port map(x => tempx, o => o, error => sige);
sf: sub_full port map(y => tempx, u => o, full => sigf);
swx: sub_win port map(a => tempx, win => sigx);
swo: sub_win port map(a => o, win => sigo);
noWin <= sigf AND (NOT(sigx OR sigo));
full <= sigf;
winX <= sigx;
winO <= sigo;
error <= sige;
newx <= tempx;
--pd : PanelDisplay pro map(clk => clk, x => newx, o => o, hsync => hsync, vsync => vsync, red => red, green => green, blue => blue);
end game;
|
library ieee;
use ieee.std_logic_1164.all;
ENTITY SAMPLER IS
PORT (
EXT_IN : IN STD_LOGIC;
CLK : IN STD_LOGIC ;
SAMPLE : IN STD_LOGIC;
nRESET: IN STD_LOGIC;
ASY_RISING : OUT STD_LOGIC;
ASY_FALLING : OUT STD_LOGIC;
ASY_GLITCH : BUFFER STD_LOGIC;
OUT_CAMPIONE : OUT STD_LOGIC;
GLITCH : OUT STD_LOGIC
);
END SAMPLER;
ARCHITECTURE BEH OF SAMPLER IS
COMPONENT GLITCH_EVALUATOR IS
PORT(
EXT_IN : IN STD_LOGIC;
CLK : IN STD_LOGIC ;
SAMPLE : IN STD_LOGIC;
nRESET: IN STD_LOGIC;
ASY_RISING: BUFFER STD_LOGIC;
ASY_FALLING : BUFFER STD_LOGIC;
ASY_GLITCH : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT D_FF
port
(
CLK : in std_logic;
CLRN : in std_logic;
ENA : in std_logic;
D : in std_logic;
Q : out std_logic
);
end COMPONENT ;
BEGIN
GLITCH_EVALUATOR_0 : GLITCH_EVALUATOR PORT MAP(
EXT_IN => EXT_IN,
CLK => CLK,
SAMPLE => SAMPLE,
nRESET => nRESET,
ASY_RISING => ASY_RISING,
ASY_FALLING => ASY_FALLING,
ASY_GLITCH => ASY_GLITCH
);
CAMPIONAMENTO_IN : D_FF PORT MAP (
CLK => CLK,
CLRN => nRESET,
ENA => SAMPLE,
D => EXT_IN,
Q =>OUT_CAMPIONE
);
CAMPIONAMENTO_GLITCH : D_FF PORT MAP (
CLK => CLK,
CLRN => nRESET,
ENA => SAMPLE,
D => ASY_GLITCH,
Q => GLITCH
);
END BEH ;
|
<filename>tb_light_controller.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_light_controller is
end entity tb_light_controller;
architecture tb_light_controller_behaviour of tb_light_controller is
component light_controller is
port (
clk : in std_logic;
enable : in std_logic;
nominal : in std_logic;
standby : in std_logic;
maintenance : in std_logic;
mod0 : in std_logic;
mod1 : in std_logic;
mod_auto : in std_logic;
red : out std_logic;
yellow : out std_logic;
green : out std_logic
);
end component light_controller;
signal clk_int : std_logic;
signal enable_int : std_logic;
signal nominal_int : std_logic;
signal standby_int : std_logic;
signal maintenance_int : std_logic;
signal mod0_int : std_logic;
signal mod1_int : std_logic;
signal mod_auto_int : std_logic;
signal red_int : std_logic;
signal yellow_int : std_logic;
signal green_int : std_logic;
begin
clk_gen : process
begin
clk_int <= '0'; wait for 5 ns;
clk_int <= '1'; wait for 5 ns;
end process clk_gen;
mod0_gen : process
begin
mod0_int <= '1'; wait for 10 ns;
mod0_int <= '0'; wait for 20 ns;
end process mod0_gen;
mod1_gen : process
begin
mod1_int <= '0'; wait for 10 ns;
mod1_int <= '1'; wait for 10 ns;
mod1_int <= '0'; wait for 10 ns;
end process mod1_gen;
mod_auto_gen : process
begin
mod_auto_int <= '0'; wait for 20 ns;
mod_auto_int <= '1'; wait for 10 ns;
end process mod_auto_gen;
nominal_gen : process
begin
nominal_int <= '1'; wait for 30 ns;
nominal_int <= '0'; wait for 60 ns;
end process nominal_gen;
standby_gen : process
begin
standby_int <= '0'; wait for 30 ns;
standby_int <= '1'; wait for 30 ns;
standby_int <= '0'; wait for 30 ns;
end process standby_gen;
maintenance_gen : process
begin
maintenance_int <= '0'; wait for 60 ns;
maintenance_int <= '1'; wait for 30 ns;
end process maintenance_gen;
enable_gen : process
begin
enable_int <= '1'; wait for 90 ns;
enable_int <= '0'; wait for 90 ns;
end process enable_gen;
light_controller_component : light_controller
port map (
clk => clk_int,
enable => enable_int,
nominal => nominal_int,
standby => standby_int,
maintenance => maintenance_int,
mod0 => mod0_int,
mod1 => mod1_int,
mod_auto => mod_auto_int,
red => red_int,
yellow => yellow_int,
green => green_int
);
end architecture tb_light_controller_behaviour;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: <NAME>
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 17:11:29 03/06/2013
-- Design Name:
-- Module Name: dbncr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents a debouncer and is used to synchronize with the system clock
-- and remove glitches from the incoming button signals
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Dbncr is
generic(
NR_OF_CLKS : integer := 4095 -- Number of System Clock periods while the incoming signal
); -- has to be stable until a one-shot output signal is generated
port(
clk_i : in std_logic;
sig_i : in std_logic;
pls_o : out std_logic
);
end Dbncr;
architecture Behavioral of Dbncr is
signal cnt : integer range 0 to NR_OF_CLKS-1;
signal sigTmp : std_logic;
signal stble, stbleTmp : std_logic;
begin
DEB: process(clk_i)
begin
if rising_edge(clk_i) then
if sig_i = sigTmp then -- Count the number of clock periods if the signal is stable
if cnt = NR_OF_CLKS-1 then
stble <= sig_i;
else
cnt <= cnt + 1;
end if;
else -- Reset counter and sample the new signal value
cnt <= 0;
sigTmp <= sig_i;
end if;
end if;
end process DEB;
PLS: process(clk_i)
begin
if rising_edge(clk_i) then
stbleTmp <= stble;
end if;
end process PLS;
-- generate the one-shot output signal
pls_o <= '1' when stbleTmp = '0' and stble = '1' else '0';
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.util.all;
entity mem_stage is
port (clk : in std_logic;
rstn : in std_logic;
mem_write_mem : in std_logic;
mem_read_mem : in std_logic;
alu_res_mem : in std_logic_vector(Nbit - 1 downto 0);
read_data : in std_logic_vector(Nbit - 1 downto 0);
rf_data2_mem : in std_logic_vector(Nbit - 1 downto 0);
rd_mem_data_mem : out std_logic_vector(Nbit - 1 downto 0);
address : out std_logic_vector(Nbit_address - 1 downto 0);
write_data : out std_logic_vector(Nbit - 1 downto 0);
enable_write, enable_read : out std_logic;
alu_res_mem_wb : out std_logic_vector(Nbit - 1 downto 0);
reg_dest_data_mem_wb : out std_logic_vector(bitNreg - 1 downto 0);
reg_dest_data_mem : in std_logic_vector(bitNreg - 1 downto 0);
pc_jump_branch_mem : in std_logic_vector(Nbit - 1 downto 0);
pc_jump_branch_mem_wb : out std_logic_vector(Nbit - 1 downto 0);
jump_branch_mem : in std_logic;
jump_branch_mem_wb : out std_logic
);
end mem_stage;
architecture behav of mem_stage is
component data_memory
port (clk : in std_logic;
RSn : in std_logic;
enable_write, enable_read : in std_logic;
address : in std_logic_vector (Nbit_address-1 downto 0);
write_data : in std_logic_vector (Nbit-1 downto 0);
read_data : out std_logic_vector (Nbit-1 downto 0));
end component;
begin
enable_write <= mem_write_mem;
enable_read <= mem_read_mem;
address <= alu_res_mem(Nbit_address - 1 downto 0);
rd_mem_data_mem <= read_data;
write_data <= rf_data2_mem;
alu_res_mem_wb <= alu_res_mem;
reg_dest_data_mem_wb <= reg_dest_data_mem;
pc_jump_branch_mem_wb <= pc_jump_branch_mem;
jump_branch_mem_wb <= jump_branch_mem;
end behav;
|
library verilog;
use verilog.vl_types.all;
entity altshift_taps is
generic(
number_of_taps : integer := 4;
tap_distance : integer := 3;
width : integer := 8;
power_up_state : string := "CLEARED";
lpm_type : string := "altshift_taps";
intended_device_family: string := "Stratix";
lpm_hint : string := "UNUSED";
RAM_WIDTH : vl_notype;
TOTAL_TAP_DISTANCE: vl_notype
);
port(
shiftin : in vl_logic_vector;
clock : in vl_logic;
clken : in vl_logic;
aclr : in vl_logic;
sclr : in vl_logic;
shiftout : out vl_logic_vector;
taps : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_taps : constant is 1;
attribute mti_svvh_generic_type of tap_distance : constant is 1;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of power_up_state : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of RAM_WIDTH : constant is 3;
attribute mti_svvh_generic_type of TOTAL_TAP_DISTANCE : constant is 3;
end altshift_taps;
|
<reponame>ameershalabi/amshal_misc_pkg
--------------------------------------------------------------------------------
-- Title : RAM block
-- Project : amshal_misc package
--------------------------------------------------------------------------------
-- File : RAM_dual_read.vhdl
-- Author : <NAME> <<EMAIL>>
-- Company : -
-- Created : Mon Nov 2 13:40:44 2020
-- Last update : Mon Nov 2 14:01:55 2020
-- Platform : -
-- Standard : <VHDL-2008 | VHDL-2002 | VHDL-1993 | VHDL-1987>
--------------------------------------------------------------------------------
-- Copyright (c) 2020 User Company Name
-------------------------------------------------------------------------------
-- Description: A dual-read-port RAM block generator
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RAM_dual_R is
generic (
ram_width : natural := 4;
ram_depth : natural := 8
);
port (
clk : in std_logic;
rst : in std_logic;
-- write port
w_en : in std_logic;
w_addr : in std_logic_vector(ram_depth-1 downto 0);
w_data : in std_logic_vector(ram_width-1 downto 0);
-- read ports
r_addr_1 : in std_logic_vector(ram_depth-1 downto 0);
r_addr_2 : in std_logic_vector(ram_depth-1 downto 0);
r_data_1 : out std_logic_vector(ram_width-1 downto 0);
r_data_2 : out std_logic_vector(ram_width-1 downto 0)
);
end RAM_dual_R;
architecture RAM_dual_R_arch of RAM_dual_R is
constant rst_value : std_logic_vector(ram_width-1 downto 0) := (others => '0');
type ram_type is array (ram_depth-1 downto 0) of std_logic_vector (ram_width-1 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if (rst = '1') then
RAM <= (others => (rst_value));
elsif (clk'event and clk = '1') then
if (w_en = '1') then
RAM(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end process;
r_data_1 <= RAM(conv_integer(r_addr_1));
r_data_2 <= RAM(conv_integer(r_addr_2));
end RAM_dual_R_arch;
|
-- 09.05.19 --- <NAME> --- LatchSR_rstPr.vhdl
-- LATCH SR CON RESET PRIORITARIO
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------
entity LatchSR_rstPr is
port(r_i : in std_logic;
s_i : in std_logic;
q_o : out std_logic);
end entity LatchSR_rstPr;
---------------------------------------------------
-- LA PRIORIDAD LA FIJA EL ORDEN DE LOS "WHEN".
-- SI R=S=0, Q RETIENE SU VALOR (MEMORIZA)
architecture Arq of LatchSR_rstPr is begin
q_o <= '0' when r_i = '1' else
'1' when s_i = '1';
end architecture Arq;
---------------------------------------------------
|
<filename>hw/dns-anomaly-arty-a7/dns-anomaly-arty-a7.srcs/sources_1/imports/dns-anomaly/mac_rcv.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.common.ALL;
ENTITY mac_rcv IS
PORT (
E_RX_CLK : IN STD_LOGIC; -- Receiver Clock.
E_RX_DV : IN STD_LOGIC; -- Received Data Valid.
E_RXD : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Received Nibble.
el_data : OUT rcv_data_t; -- Ethernet Receving Data.
el_dv : OUT STD_LOGIC -- Data valid.
--led : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END mac_rcv;
ARCHITECTURE rtl OF mac_rcv IS
TYPE state_t IS (
Preamble, StartOfFrame, -- 7 Bytes 0x55, 1 Byte 0x5d.
EtherMACDST, -- 6 Byte MAC address DST
EtherMACSRC, -- 6 Byte MAC address SRC
EtherType, -- Next Protocol 0x0800
IPVersion, -- 4 bits IP Version 0x4
IPIHL, -- 4 bits IP IHL 0x5
IPDSCPECN, -- 1 byte DSCP 6 bits + ECN 2 bits 0x?0
IPLength, -- 2 byte IP Length
IPID, -- 2 byte IPID
IPFlagsFragment, -- 2 byte Flags 3 bits + Fragment Offset 13 bits 0x00
IPTTL, -- 1 byte
IPProtocol, -- 1 byte 0x11 UDP, 0x06 TCP
IPChecksum, -- 2 byte
IPAddrSRC, -- 4 byte IP Addr SRC
IPAddrDST, -- 4 byte IP Addr DST
IPOptions, -- dependent on IPIHL size > 5
UDPPortSRC, -- 2 byte UDP Port SRC
UDPPortDST, -- 2 byte UDP Port DST
UDPLength, -- 2 byte UDP Length
UDPChecksum, -- 2 byte
DNSMsgRecord, -- 1472 bytes 1500 MTU - 20 IP - 8 UDP = 1472
DNSMsgDiscard,
Notify -- Inform other hardware components.
);
TYPE rcv_t IS RECORD
s : state_t; -- Receiver Parse State
c : NATURAL RANGE 0 TO 65535; -- Counter MAX 65535
ipc : NATURAL RANGE 0 TO 65535;
udpc : NATURAL RANGE 0 TO 65535;
END RECORD;
SIGNAL d : rcv_data_t
:= rcv_data_t'(
srcMAC => (OTHERS => '0'), dstMAC => (OTHERS => '0'),
srcIP => (OTHERS => '0'), dstIP => (OTHERS => '0'),
ipHeaderLength => 0, ipLength => 0,
srcPort => (OTHERS => '0'), dstPort => (OTHERS => '0'),
dnsLength => 0,
dnsPkt => (OTHERS => '0')
);
SIGNAL r, rin : rcv_t
:= rcv_t'(
s => Preamble,
c => 0,
ipc => 0,
udpc => 0
);
BEGIN
rcv_nsl : PROCESS (E_RX_CLK) --, el_ack)
BEGIN
IF (rising_edge(E_RX_CLK)) THEN
el_dv <= '0';
IF E_RX_DV = '1' THEN
CASE r.s IS
-- Ethernet II - Preamble and Start Of Frame
WHEN Preamble =>
IF E_RXD = x"5" THEN
IF r.c = 14 THEN
rin.c <= 0;
rin.s <= StartOfFrame;
ELSE
rin.c <= r.c + 1;
END IF;
ELSE
rin.c <= 0;
END IF;
WHEN StartOfFrame =>
IF E_RXD = x"d" THEN
rin.s <= EtherMACDST;
ELSE
rin.s <= Preamble;
END IF;
-- Ethernet II - MAC DST and MAC SRC
WHEN EtherMACDST =>
d.dstMAC((r.c + 3) DOWNTO (r.c)) <= E_RXD;
IF r.c = 44 THEN
rin.c <= 0;
rin.s <= EtherMACSRC;
ELSE
rin.c <= r.c + 4;
END IF;
WHEN EtherMACSRC =>
d.srcMAC((r.c + 3) DOWNTO (r.c)) <= E_RXD;
IF r.c = 44 THEN
rin.c <= 0;
rin.s <= EtherType;
ELSE
rin.c <= r.c + 4;
END IF;
-- Ethernet II - Ethertype 0x0800
WHEN EtherType =>
IF E_RXD = x"8" THEN
IF r.c = 0 THEN
rin.c <= r.c + 1;
ELSE
rin.c <= 0;
rin.s <= Preamble;
END IF;
ELSIF E_RXD = x"0" THEN
IF r.c = 3 THEN
rin.c <= 0;
rin.s <= IPIHL;
d.ipHeaderLength <= 0;
ELSIF r.c = 0 THEN
rin.c <= 0;
rin.s <= Preamble;
ELSE
rin.c <= r.c + 1;
END IF;
ELSE
rin.c <= 0;
rin.s <= Preamble;
END IF;
-- IP - IHL 0x5
WHEN IPIHL =>
d.ipHeaderLength <= to_integer(unsigned(E_RXD));
IF (E_RXD >= x"5") THEN
rin.c <= 0;
rin.s <= IPVersion;
ELSE
rin.c <= 0;
d.ipHeaderLength <= 0;
rin.s <= Preamble;
END IF;
-- IP - Version 0x4 --
WHEN IPVersion =>
IF E_RXD = x"4" THEN
rin.c <= 0;
rin.s <= IPDSCPECN;
ELSE
rin.c <= 0;
rin.s <= Preamble;
END IF;
-- IP - DSCP ECN 0x?0
WHEN IPDSCPECN =>
IF r.c = 1 THEN
rin.c <= 0;
rin.s <= IPLength;
rin.ipc <= 0;
ELSE
rin.c <= r.c + 1;
END IF;
-- IP - Length
WHEN IPLength =>
rin.ipc <= r.ipc * 16 + to_integer(unsigned(E_RXD));
IF r.c = 3 THEN
rin.c <= 0;
rin.s <= IPID;
ELSE
rin.c <= r.c + 1;
END IF;
-- IP - ID
WHEN IPID =>
IF r.c = 3 THEN
rin.c <= 0;
rin.s <= IPFlagsFragment;
d.ipLength <= r.ipc;
ELSE
rin.c <= r.c + 1;
END IF;
-- IP Flags Fragment Offset 0x00
WHEN IPFlagsFragment =>
IF E_RXD = x"0" THEN
IF r.c = 3 THEN
rin.c <= 0;
rin.s <= IPTTL;
ELSE
rin.c <= r.c + 1;
END IF;
ELSE
rin.c <= 0;
rin.s <= Preamble;
END IF;
-- IP TTL
WHEN IPTTL =>
IF r.c = 1 THEN
rin.c <= 0;
rin.s <= IPProtocol;
ELSE
rin.c <= r.c + 1;
END IF;
-- IP Protocol UDP 0x11
WHEN IPProtocol =>
IF E_RXD = x"1" THEN
IF r.c = 1 THEN
rin.c <= 0;
rin.s <= IPChecksum;
ELSE
rin.c <= r.c + 1;
END IF;
ELSE
rin.c <= 0;
rin.s <= Preamble;
END IF;
-- IP Checksum
WHEN IPChecksum =>
IF r.c = 3 THEN
rin.c <= 0;
rin.s <= IPAddrSRC;
ELSE
rin.c <= r.c + 1;
END IF;
-- IP addr src
WHEN IPAddrSRC =>
d.srcIP((r.c + 3) DOWNTO (r.c)) <= E_RXD;
IF r.c = 28 THEN
rin.c <= 0;
rin.s <= IPAddrDST;
ELSE
rin.c <= r.c + 4;
END IF;
-- IP addr dst
WHEN IPAddrDST =>
d.dstIP((r.c + 3) DOWNTO (r.c)) <= E_RXD;
IF r.c = 28 THEN
rin.c <= 0;
IF d.ipHeaderLength = 5 THEN
rin.s <= UDPPortSRC;
ELSE
rin.s <= IPOptions;
END IF;
ELSE
rin.c <= r.c + 4;
END IF;
-- IP Options, dependent on IPIHL > 5
WHEN IPOptions =>
IF (r.c = (d.ipHeaderLength - 5) * 8 - 1) THEN
rin.c <= 0;
rin.s <= UDPPortSRC;
ELSE
rin.c <= r.c + 1;
END IF;
-- UDP port src
WHEN UDPPortSRC =>
d.srcPort((r.c + 3) DOWNTO (r.c)) <= E_RXD;
IF r.c = 12 THEN
rin.c <= 0;
rin.s <= UDPPortDST;
ELSE
rin.c <= r.c + 4;
END IF;
-- UDP port dst
WHEN UDPPortDST =>
d.dstPort((r.c + 3) DOWNTO (r.c)) <= E_RXD;
IF r.c = 12 THEN
rin.c <= 0;
rin.s <= UDPLength;
rin.udpc <= 0;
ELSE
rin.c <= r.c + 4;
END IF;
-- UDP payload length
WHEN UDPLength =>
IF r.c = 0 OR r.c = 2 THEN
rin.udpc <= r.udpc + to_integer(unsigned(E_RXD));
ELSIF r.c = 1 THEN
rin.udpc <= (r.udpc + to_integer(unsigned(E_RXD)) * 16) * 256;
ELSE
rin.udpc <= r.udpc + to_integer(unsigned(E_RXD)) * 16 - 8;
END IF;
IF r.c = 3 THEN
rin.c <= 0;
rin.s <= UDPChecksum;
ELSE
rin.c <= r.c + 1;
END IF;
-- UDP Checksum
WHEN UDPChecksum =>
IF r.c = 3 THEN
rin.c <= 0;
d.dnsLength <= r.udpc;
rin.udpc <= r.udpc * 8 - 4;
d.dnsPkt <= (OTHERS => '0');
rin.s <= DNSMsgRecord;
ELSE
rin.c <= r.c + 1;
END IF;
-- DNS Msg
WHEN DNSMsgRecord =>
d.dnsPkt((r.c + 3) DOWNTO (r.c)) <= E_RXD;
IF r.c = r.udpc THEN
rin.c <= 0;
rin.s <= Notify;
ELSIF r.c = 1020 THEN
rin.c <= r.c + 4;
rin.s <= DNSMsgDiscard;
ELSE
rin.c <= r.c + 4;
END IF;
WHEN DNSMsgDiscard =>
IF r.c = r.udpc THEN
rin.c <= 0;
rin.s <= Notify;
ELSE
rin.c <= r.c + 4;
END IF;
-- Notification --
WHEN Notify =>
el_dv <= '1';
rin.s <= Preamble;
rin.c <= 0;
END CASE;
ELSE
rin.s <= Preamble;
rin.c <= 0;
END IF;
END IF;
END PROCESS;
el_data <= d;
snd_reg : PROCESS (E_RX_CLK)
BEGIN
IF falling_edge(E_RX_CLK) THEN
r <= rin;
END IF;
END PROCESS;
END rtl;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pulse_source is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
radius : IN STD_LOGIC_VECTOR (31 downto 0);
step : IN STD_LOGIC_VECTOR (31 downto 0);
amp : IN STD_LOGIC_VECTOR (63 downto 0);
uc_address0 : OUT STD_LOGIC_VECTOR (13 downto 0);
uc_ce0 : OUT STD_LOGIC;
uc_we0 : OUT STD_LOGIC;
uc_d0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ny : IN STD_LOGIC_VECTOR (31 downto 0);
nx : IN STD_LOGIC_VECTOR (31 downto 0);
scenario_source_x : IN STD_LOGIC_VECTOR (31 downto 0);
scenario_source_y : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of pulse_source is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_state43 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_state44 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_state45 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_state46 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state47 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state48 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state49 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state50 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state51 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state52 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state53 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state54 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state55 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state56 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state57 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state58 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state59 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state60 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state61 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state62 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state63 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state64 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state65 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state66 : STD_LOGIC_VECTOR (75 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state67 : STD_LOGIC_VECTOR (75 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state68 : STD_LOGIC_VECTOR (75 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state69 : STD_LOGIC_VECTOR (75 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state70 : STD_LOGIC_VECTOR (75 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state71 : STD_LOGIC_VECTOR (75 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state72 : STD_LOGIC_VECTOR (75 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state73 : STD_LOGIC_VECTOR (75 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state74 : STD_LOGIC_VECTOR (75 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state75 : STD_LOGIC_VECTOR (75 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state76 : STD_LOGIC_VECTOR (75 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_42 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000010";
constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011";
constant ap_const_lv32_44 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000100";
constant ap_const_lv32_45 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000101";
constant ap_const_lv32_4A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001011";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv64_400921FB54442D18 : STD_LOGIC_VECTOR (63 downto 0) := "0100000000001001001000011111101101010100010001000010110100011000";
constant ap_const_lv64_3FD0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111010000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv52_0 : STD_LOGIC_VECTOR (51 downto 0) := "0000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_64 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000001100100";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
signal ap_CS_fsm : STD_LOGIC_VECTOR (75 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal grp_fu_146_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_159 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal ap_CS_fsm_state17 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal grp_fu_132_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_165 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal ap_CS_fsm_state18 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal tmp_193_i_to_int_fu_171_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_193_i_to_int_reg_363 : STD_LOGIC_VECTOR (63 downto 0);
signal notrhs2_fu_179_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notrhs2_reg_368 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_316_fu_185_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_316_reg_373 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_state19 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state19 : signal is "none";
signal next_mul_fu_189_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal next_mul_reg_378 : STD_LOGIC_VECTOR (63 downto 0);
signal i_fu_205_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_386 : STD_LOGIC_VECTOR (31 downto 0);
signal j_fu_221_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_reg_394 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state20 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state20 : signal is "none";
signal tmp_i_fu_231_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_129_fu_215_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_258_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_reg_409 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_186_i_reg_414 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state25 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
signal grp_fu_151_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_189_i_reg_420 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_187_i_reg_426 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state31 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state31 : signal is "none";
signal grp_fu_138_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_190_i_reg_431 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_128_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_191_i_reg_436 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state36 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
signal grp_fu_154_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_192_i_reg_441 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state67 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state67 : signal is "none";
signal tmp_182_fu_309_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_reg_447 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state68 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state68 : signal is "none";
signal tmp_252_fu_319_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_252_reg_451 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_318_fu_328_p1 : STD_LOGIC_VECTOR (62 downto 0);
signal tmp_318_reg_456 : STD_LOGIC_VECTOR (62 downto 0);
signal ap_CS_fsm_state69 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state69 : signal is "none";
signal grp_sin_cos_range_redux_s_fu_119_ap_done : STD_LOGIC;
signal ret_i_i_i_i_i_fu_339_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state70 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state70 : signal is "none";
signal tmp_130_reg_466 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state75 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state75 : signal is "none";
signal grp_sin_cos_range_redux_s_fu_119_ap_start : STD_LOGIC;
signal grp_sin_cos_range_redux_s_fu_119_ap_idle : STD_LOGIC;
signal grp_sin_cos_range_redux_s_fu_119_ap_ready : STD_LOGIC;
signal grp_sin_cos_range_redux_s_fu_119_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal x_assign_reg_84 : STD_LOGIC_VECTOR (31 downto 0);
signal phi_mul_reg_96 : STD_LOGIC_VECTOR (63 downto 0);
signal y_assign_reg_107 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state76 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state76 : signal is "none";
signal tmp_127_fu_199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_grp_sin_cos_range_redux_s_fu_119_ap_start : STD_LOGIC := '0';
signal tmp_253_cast_fu_344_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state32 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state32 : signal is "none";
signal grp_fu_132_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_132_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal ap_CS_fsm_state26 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal grp_fu_146_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_151_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state37 : STD_LOGIC_VECTOR (0 downto 0);
attribute fsm_encoding of ap_CS_fsm_state37 : signal is "none";
signal tmp_315_fu_175_p1 : STD_LOGIC_VECTOR (51 downto 0);
signal tmp_177_fu_249_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_192_i_to_int_fu_264_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_175_fu_267_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_317_fu_277_p1 : STD_LOGIC_VECTOR (51 downto 0);
signal notrhs_fu_287_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_281_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_178_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_179_fu_299_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_180_fu_303_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_fu_142_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_319_fu_315_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal p_Val2_s_fu_324_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Result_s_fu_332_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (75 downto 0);
component sin_cos_range_redux_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
t_in : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component s_compute_acoustijbC IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component s_compute_acoustikbM IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component s_compute_acoustilbW IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component s_compute_acoustimb6 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component s_compute_acoustincg IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
grp_sin_cos_range_redux_s_fu_119 : component sin_cos_range_redux_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sin_cos_range_redux_s_fu_119_ap_start,
ap_done => grp_sin_cos_range_redux_s_fu_119_ap_done,
ap_idle => grp_sin_cos_range_redux_s_fu_119_ap_idle,
ap_ready => grp_sin_cos_range_redux_s_fu_119_ap_ready,
t_in => reg_165,
ap_return => grp_sin_cos_range_redux_s_fu_119_ap_return);
s_compute_acoustijbC_U12 : component s_compute_acoustijbC
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => tmp_187_i_reg_426,
din1 => tmp_190_i_reg_431,
ce => ap_const_logic_1,
dout => grp_fu_128_p2);
s_compute_acoustikbM_U13 : component s_compute_acoustikbM
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_132_p0,
din1 => grp_fu_132_p1,
ce => ap_const_logic_1,
dout => grp_fu_132_p2);
s_compute_acoustikbM_U14 : component s_compute_acoustikbM
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => tmp_189_i_reg_420,
din1 => tmp_189_i_reg_420,
ce => ap_const_logic_1,
dout => grp_fu_138_p2);
s_compute_acoustilbW_U15 : component s_compute_acoustilbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 1)
port map (
din0 => tmp_192_i_reg_441,
din1 => reg_159,
opcode => ap_const_lv5_5,
dout => tmp_181_fu_142_p2);
s_compute_acoustimb6_U16 : component s_compute_acoustimb6
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_146_p0,
ce => ap_const_logic_1,
dout => grp_fu_146_p1);
s_compute_acoustimb6_U17 : component s_compute_acoustimb6
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_151_p0,
ce => ap_const_logic_1,
dout => grp_fu_151_p1);
s_compute_acoustincg_U18 : component s_compute_acoustincg
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => ap_const_lv64_0,
din1 => tmp_191_i_reg_436,
ce => ap_const_logic_1,
dout => grp_fu_154_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_grp_sin_cos_range_redux_s_fu_119_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_sin_cos_range_redux_s_fu_119_ap_start <= ap_const_logic_0;
else
if (((ap_const_lv1_1 = ap_CS_fsm_state68) and not((ap_const_lv1_0 = tmp_182_fu_309_p2)))) then
ap_reg_grp_sin_cos_range_redux_s_fu_119_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sin_cos_range_redux_s_fu_119_ap_ready)) then
ap_reg_grp_sin_cos_range_redux_s_fu_119_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
phi_mul_reg_96_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state20) and (tmp_129_fu_215_p2 = ap_const_lv1_0))) then
phi_mul_reg_96 <= next_mul_reg_378;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state18))) then
phi_mul_reg_96 <= ap_const_lv64_0;
end if;
end if;
end process;
x_assign_reg_84_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state20) and (tmp_129_fu_215_p2 = ap_const_lv1_0))) then
x_assign_reg_84 <= i_reg_386;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state18))) then
x_assign_reg_84 <= ap_const_lv32_0;
end if;
end if;
end process;
y_assign_reg_107_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state19) and not((ap_const_lv1_0 = tmp_127_fu_199_p2)))) then
y_assign_reg_107 <= ap_const_lv32_0;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state76))) then
y_assign_reg_107 <= j_reg_394;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state19))) then
i_reg_386 <= i_fu_205_p2;
next_mul_reg_378 <= next_mul_fu_189_p2;
tmp_316_reg_373 <= tmp_316_fu_185_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state20))) then
j_reg_394 <= j_fu_221_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state20) and not((tmp_129_fu_215_p2 = ap_const_lv1_0)))) then
notlhs1_reg_409 <= notlhs1_fu_258_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state18))) then
notrhs2_reg_368 <= notrhs2_fu_179_p2;
tmp_193_i_to_int_reg_363 <= tmp_193_i_to_int_fu_171_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_lv1_1 = ap_CS_fsm_state6)) or ((ap_const_lv1_1 = ap_CS_fsm_state17)))) then
reg_159 <= grp_fu_146_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_lv1_1 = ap_CS_fsm_state12)) or ((ap_const_lv1_1 = ap_CS_fsm_state18)))) then
reg_165 <= grp_fu_132_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state75))) then
tmp_130_reg_466 <= grp_fu_132_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state68))) then
tmp_182_reg_447 <= tmp_182_fu_309_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state25))) then
tmp_186_i_reg_414 <= grp_fu_146_p1;
tmp_189_i_reg_420 <= grp_fu_151_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state31))) then
tmp_187_i_reg_426 <= grp_fu_132_p2;
tmp_190_i_reg_431 <= grp_fu_138_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state36))) then
tmp_191_i_reg_436 <= grp_fu_128_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state67))) then
tmp_192_i_reg_441 <= grp_fu_154_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state68) and not((ap_const_lv1_0 = tmp_182_fu_309_p2)))) then
tmp_252_reg_451 <= tmp_252_fu_319_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_1 = ap_CS_fsm_state69) and not((ap_const_logic_0 = grp_sin_cos_range_redux_s_fu_119_ap_done)))) then
tmp_318_reg_456 <= tmp_318_fu_328_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_129_fu_215_p2, tmp_182_fu_309_p2, grp_sin_cos_range_redux_s_fu_119_ap_done, tmp_127_fu_199_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
if ((ap_const_lv1_0 = tmp_127_fu_199_p2)) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state20;
end if;
when ap_ST_fsm_state20 =>
if ((tmp_129_fu_215_p2 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_fsm_state19;
else
ap_NS_fsm <= ap_ST_fsm_state21;
end if;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state34;
when ap_ST_fsm_state34 =>
ap_NS_fsm <= ap_ST_fsm_state35;
when ap_ST_fsm_state35 =>
ap_NS_fsm <= ap_ST_fsm_state36;
when ap_ST_fsm_state36 =>
ap_NS_fsm <= ap_ST_fsm_state37;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state38;
when ap_ST_fsm_state38 =>
ap_NS_fsm <= ap_ST_fsm_state39;
when ap_ST_fsm_state39 =>
ap_NS_fsm <= ap_ST_fsm_state40;
when ap_ST_fsm_state40 =>
ap_NS_fsm <= ap_ST_fsm_state41;
when ap_ST_fsm_state41 =>
ap_NS_fsm <= ap_ST_fsm_state42;
when ap_ST_fsm_state42 =>
ap_NS_fsm <= ap_ST_fsm_state43;
when ap_ST_fsm_state43 =>
ap_NS_fsm <= ap_ST_fsm_state44;
when ap_ST_fsm_state44 =>
ap_NS_fsm <= ap_ST_fsm_state45;
when ap_ST_fsm_state45 =>
ap_NS_fsm <= ap_ST_fsm_state46;
when ap_ST_fsm_state46 =>
ap_NS_fsm <= ap_ST_fsm_state47;
when ap_ST_fsm_state47 =>
ap_NS_fsm <= ap_ST_fsm_state48;
when ap_ST_fsm_state48 =>
ap_NS_fsm <= ap_ST_fsm_state49;
when ap_ST_fsm_state49 =>
ap_NS_fsm <= ap_ST_fsm_state50;
when ap_ST_fsm_state50 =>
ap_NS_fsm <= ap_ST_fsm_state51;
when ap_ST_fsm_state51 =>
ap_NS_fsm <= ap_ST_fsm_state52;
when ap_ST_fsm_state52 =>
ap_NS_fsm <= ap_ST_fsm_state53;
when ap_ST_fsm_state53 =>
ap_NS_fsm <= ap_ST_fsm_state54;
when ap_ST_fsm_state54 =>
ap_NS_fsm <= ap_ST_fsm_state55;
when ap_ST_fsm_state55 =>
ap_NS_fsm <= ap_ST_fsm_state56;
when ap_ST_fsm_state56 =>
ap_NS_fsm <= ap_ST_fsm_state57;
when ap_ST_fsm_state57 =>
ap_NS_fsm <= ap_ST_fsm_state58;
when ap_ST_fsm_state58 =>
ap_NS_fsm <= ap_ST_fsm_state59;
when ap_ST_fsm_state59 =>
ap_NS_fsm <= ap_ST_fsm_state60;
when ap_ST_fsm_state60 =>
ap_NS_fsm <= ap_ST_fsm_state61;
when ap_ST_fsm_state61 =>
ap_NS_fsm <= ap_ST_fsm_state62;
when ap_ST_fsm_state62 =>
ap_NS_fsm <= ap_ST_fsm_state63;
when ap_ST_fsm_state63 =>
ap_NS_fsm <= ap_ST_fsm_state64;
when ap_ST_fsm_state64 =>
ap_NS_fsm <= ap_ST_fsm_state65;
when ap_ST_fsm_state65 =>
ap_NS_fsm <= ap_ST_fsm_state66;
when ap_ST_fsm_state66 =>
ap_NS_fsm <= ap_ST_fsm_state67;
when ap_ST_fsm_state67 =>
ap_NS_fsm <= ap_ST_fsm_state68;
when ap_ST_fsm_state68 =>
if ((ap_const_lv1_0 = tmp_182_fu_309_p2)) then
ap_NS_fsm <= ap_ST_fsm_state76;
else
ap_NS_fsm <= ap_ST_fsm_state69;
end if;
when ap_ST_fsm_state69 =>
if (not((ap_const_logic_0 = grp_sin_cos_range_redux_s_fu_119_ap_done))) then
ap_NS_fsm <= ap_ST_fsm_state70;
else
ap_NS_fsm <= ap_ST_fsm_state69;
end if;
when ap_ST_fsm_state70 =>
ap_NS_fsm <= ap_ST_fsm_state71;
when ap_ST_fsm_state71 =>
ap_NS_fsm <= ap_ST_fsm_state72;
when ap_ST_fsm_state72 =>
ap_NS_fsm <= ap_ST_fsm_state73;
when ap_ST_fsm_state73 =>
ap_NS_fsm <= ap_ST_fsm_state74;
when ap_ST_fsm_state74 =>
ap_NS_fsm <= ap_ST_fsm_state75;
when ap_ST_fsm_state75 =>
ap_NS_fsm <= ap_ST_fsm_state76;
when ap_ST_fsm_state76 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0 downto 0);
ap_CS_fsm_state12 <= ap_CS_fsm(11 downto 11);
ap_CS_fsm_state13 <= ap_CS_fsm(12 downto 12);
ap_CS_fsm_state17 <= ap_CS_fsm(16 downto 16);
ap_CS_fsm_state18 <= ap_CS_fsm(17 downto 17);
ap_CS_fsm_state19 <= ap_CS_fsm(18 downto 18);
ap_CS_fsm_state20 <= ap_CS_fsm(19 downto 19);
ap_CS_fsm_state25 <= ap_CS_fsm(24 downto 24);
ap_CS_fsm_state26 <= ap_CS_fsm(25 downto 25);
ap_CS_fsm_state31 <= ap_CS_fsm(30 downto 30);
ap_CS_fsm_state32 <= ap_CS_fsm(31 downto 31);
ap_CS_fsm_state36 <= ap_CS_fsm(35 downto 35);
ap_CS_fsm_state37 <= ap_CS_fsm(36 downto 36);
ap_CS_fsm_state6 <= ap_CS_fsm(5 downto 5);
ap_CS_fsm_state67 <= ap_CS_fsm(66 downto 66);
ap_CS_fsm_state68 <= ap_CS_fsm(67 downto 67);
ap_CS_fsm_state69 <= ap_CS_fsm(68 downto 68);
ap_CS_fsm_state7 <= ap_CS_fsm(6 downto 6);
ap_CS_fsm_state70 <= ap_CS_fsm(69 downto 69);
ap_CS_fsm_state75 <= ap_CS_fsm(74 downto 74);
ap_CS_fsm_state76 <= ap_CS_fsm(75 downto 75);
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state19, tmp_127_fu_199_p2)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_CS_fsm_state1 = ap_const_lv1_1)) or ((ap_const_lv1_1 = ap_CS_fsm_state19) and (ap_const_lv1_0 = tmp_127_fu_199_p2)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_CS_fsm_state1 = ap_const_lv1_1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state19, tmp_127_fu_199_p2)
begin
if (((ap_const_lv1_1 = ap_CS_fsm_state19) and (ap_const_lv1_0 = tmp_127_fu_199_p2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
grp_fu_132_p0_assign_proc : process(reg_159, reg_165, tmp_186_i_reg_414, ret_i_i_i_i_i_fu_339_p1, ap_CS_fsm_state70, ap_CS_fsm_state7, ap_CS_fsm_state13, ap_CS_fsm_state26)
begin
if (((ap_const_lv1_1 = ap_CS_fsm_state70))) then
grp_fu_132_p0 <= ret_i_i_i_i_i_fu_339_p1;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state26))) then
grp_fu_132_p0 <= tmp_186_i_reg_414;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state13))) then
grp_fu_132_p0 <= reg_165;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state7))) then
grp_fu_132_p0 <= reg_159;
else
grp_fu_132_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_132_p1_assign_proc : process(amp, tmp_186_i_reg_414, ap_CS_fsm_state70, ap_CS_fsm_state7, ap_CS_fsm_state13, ap_CS_fsm_state26)
begin
if (((ap_const_lv1_1 = ap_CS_fsm_state70))) then
grp_fu_132_p1 <= amp;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state26))) then
grp_fu_132_p1 <= tmp_186_i_reg_414;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state13))) then
grp_fu_132_p1 <= ap_const_lv64_3FD0000000000000;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state7))) then
grp_fu_132_p1 <= ap_const_lv64_400921FB54442D18;
else
grp_fu_132_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_146_p0_assign_proc : process(ap_CS_fsm_state1, radius, step, ap_CS_fsm_state12, ap_CS_fsm_state20, tmp_i_fu_231_p2)
begin
if (((ap_const_lv1_1 = ap_CS_fsm_state20))) then
grp_fu_146_p0 <= tmp_i_fu_231_p2;
elsif (((ap_const_lv1_1 = ap_CS_fsm_state12))) then
grp_fu_146_p0 <= radius;
elsif (((ap_CS_fsm_state1 = ap_const_lv1_1))) then
grp_fu_146_p0 <= step;
else
grp_fu_146_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_151_p0 <= std_logic_vector(unsigned(scenario_source_y) - unsigned(y_assign_reg_107));
grp_sin_cos_range_redux_s_fu_119_ap_start <= ap_reg_grp_sin_cos_range_redux_s_fu_119_ap_start;
i_fu_205_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(x_assign_reg_84));
j_fu_221_p2 <= std_logic_vector(unsigned(y_assign_reg_107) + unsigned(ap_const_lv32_1));
next_mul_fu_189_p2 <= std_logic_vector(unsigned(ap_const_lv64_64) + unsigned(phi_mul_reg_96));
notlhs1_fu_258_p2 <= "0" when (tmp_177_fu_249_p4 = ap_const_lv11_7FF) else "1";
notlhs_fu_281_p2 <= "0" when (tmp_175_fu_267_p4 = ap_const_lv11_7FF) else "1";
notrhs2_fu_179_p2 <= "1" when (tmp_315_fu_175_p1 = ap_const_lv52_0) else "0";
notrhs_fu_287_p2 <= "1" when (tmp_317_fu_277_p1 = ap_const_lv52_0) else "0";
p_Result_s_fu_332_p3 <= (ap_const_lv1_0 & tmp_318_reg_456);
p_Val2_s_fu_324_p1 <= grp_sin_cos_range_redux_s_fu_119_ap_return;
ret_i_i_i_i_i_fu_339_p1 <= p_Result_s_fu_332_p3;
tmp_127_fu_199_p2 <= "1" when (signed(x_assign_reg_84) < signed(ny)) else "0";
tmp_129_fu_215_p2 <= "1" when (signed(y_assign_reg_107) < signed(nx)) else "0";
tmp_175_fu_267_p4 <= tmp_192_i_to_int_fu_264_p1(62 downto 52);
tmp_177_fu_249_p4 <= tmp_193_i_to_int_reg_363(62 downto 52);
tmp_178_fu_293_p2 <= (notrhs_fu_287_p2 or notlhs_fu_281_p2);
tmp_179_fu_299_p2 <= (notrhs2_reg_368 or notlhs1_reg_409);
tmp_180_fu_303_p2 <= (tmp_178_fu_293_p2 and tmp_179_fu_299_p2);
tmp_182_fu_309_p2 <= (tmp_180_fu_303_p2 and tmp_181_fu_142_p2);
tmp_192_i_to_int_fu_264_p1 <= tmp_192_i_reg_441;
tmp_193_i_to_int_fu_171_p1 <= reg_159;
tmp_252_fu_319_p2 <= std_logic_vector(unsigned(tmp_316_reg_373) + unsigned(tmp_319_fu_315_p1));
tmp_253_cast_fu_344_p1 <= std_logic_vector(resize(unsigned(tmp_252_reg_451),64));
tmp_315_fu_175_p1 <= tmp_193_i_to_int_fu_171_p1(52 - 1 downto 0);
tmp_316_fu_185_p1 <= phi_mul_reg_96(15 - 1 downto 0);
tmp_317_fu_277_p1 <= tmp_192_i_to_int_fu_264_p1(52 - 1 downto 0);
tmp_318_fu_328_p1 <= p_Val2_s_fu_324_p1(63 - 1 downto 0);
tmp_319_fu_315_p1 <= y_assign_reg_107(15 - 1 downto 0);
tmp_i_fu_231_p2 <= std_logic_vector(unsigned(scenario_source_x) - unsigned(x_assign_reg_84));
uc_address0 <= tmp_253_cast_fu_344_p1(14 - 1 downto 0);
uc_ce0_assign_proc : process(ap_CS_fsm_state76)
begin
if (((ap_const_lv1_1 = ap_CS_fsm_state76))) then
uc_ce0 <= ap_const_logic_1;
else
uc_ce0 <= ap_const_logic_0;
end if;
end process;
uc_d0 <= tmp_130_reg_466;
uc_we0_assign_proc : process(tmp_182_reg_447, ap_CS_fsm_state76)
begin
if ((((ap_const_lv1_1 = ap_CS_fsm_state76) and not((ap_const_lv1_0 = tmp_182_reg_447))))) then
uc_we0 <= ap_const_logic_1;
else
uc_we0 <= ap_const_logic_0;
end if;
end process;
end behav;
|
--Guia 1, ejercicio 3
--Alumno: <NAME>
--Legajo: 1595659
--GitLab User: toordonez
--Mail: <EMAIL>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity guiaDeClase01_03 is
Generic ( N: NATURAL );
Port (
a : in STD_LOGIC_VECTOR (N-1 downto 0);
c : in STD_LOGIC_VECTOR (N-1 downto 0);
s : out STD_LOGIC_VECTOR (N-1 downto 0)
);
end guiaDeClase01_03;
architecture ARCH_guiaDeClase01_03 of guiaDeClase01_03 is
begin
E1: FOR i IN 0 to 3 generate
s(i) <= a(i) when c(i) = '1' else
'Z';
end generate;
end ARCH_guiaDeClase01_03;
|
-- MIT License
--
-- Copyright (c) 2017 <NAME> - <EMAIL>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_3to8 is
Port (
des: in std_logic_vector(2 downto 0);
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
Q4 : out std_logic;
Q5 : out std_logic;
Q6 : out std_logic;
Q7 : out std_logic
);
end decoder_3to8;
architecture Behavioral of decoder_3to8 is
begin
Q0<= '1' after 1ns when des = "000" else '0' after 1ns;
Q1<= '1' after 1ns when des = "001" else '0' after 1ns;
Q2<= '1' after 1ns when des = "010" else '0' after 1ns;
Q3<= '1' after 1ns when des = "011" else '0' after 1ns;
Q4<= '1' after 1ns when des = "100" else '0' after 1ns;
Q5<= '1' after 1ns when des = "101" else '0' after 1ns;
Q6<= '1' after 1ns when des = "110" else '0' after 1ns;
Q7<= '1' after 1ns when des = "111" else '0' after 1ns;
end Behavioral;
|
<gh_stars>1-10
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX41A_TOP is
port (
s0_4 : in std_logic_vector(0 to 3); --选择
a,b,c,d : in std_logic; --信号输入
Y : out std_logic --输出
);
end entity MUX41A_TOP;
architecture if_else of mux41A_TOP is
begin
process (s0_4,a,b,c,d)
begin
if (s0_4="0111") then y<=a;
elsif (s0_4="1011") then y<=b;
elsif (s0_4="1101") then y<=c;
elsif (s0_4="1110") then y<=d;
else y<='Z'; --你的错
end if;
end process;
end if_else;
architecture when_else of mux41A_TOP is
begin
y <= a when (s0_4="0111")
else b when (s0_4="1011")
else c when (s0_4="1101")
else d when (s0_4="1110")
else 'Z';
end when_else;
architecture usecase of mux41A_TOP is
begin
process(s0_4,a,b,c,d)
begin
case (s0_4) is
when "0111" => y <= a;
when "1011" => y <= b;
when "1101" => y <= c;
when "1110" => y <= d;
when others => null；
end case;
end process;
end usecase;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_register is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
data_out : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
write_data : in STD_LOGIC;
enable : in STD_LOGIC);
end shift_register;
architecture Behavioral of shift_register is
signal data : STD_LOGIC_VECTOR(9 downto 0);
begin
process(clock)
begin
if (clock'event and clock='1') then
if (reset='1') then
data <= (others => '0');
else
if write_data = '1' then
data(8 downto 1) <= data_in;
data(0) <= '0';
data(9) <= '1';
elsif enable = '1' then
data(8 downto 0) <= data(9 downto 1);
data(9) <= '0';
data_out <= data(0);
else
data <= data;
end if;
end if ;
end if ;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- File : TimingClkSwitcherTb.vhd
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: Testbeed for TimingClkSwitcher
-------------------------------------------------------------------------------
-- This file is part of 'Development Board Misc. Utilities Library'
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'Development Board Misc. Utilities Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
use surf.AxiLiteMasterPkg.all;
use surf.I2cPkg.all;
library dev_board_misc_utils;
library unisim;
use unisim.vcomponents.all;
entity TimingClkSwitcherTb is
end entity TimingClkSwitcherTb;
architecture impl of TimingClkSwitcherTb is
constant AS_C : natural := 1;
constant DS_C : natural := 1;
constant AB_C : natural := 8*AS_C;
constant DB_C : natural := 8*DS_C;
constant I2C_SLV_C : slv := "1110100";
constant I2C_ADDR_C : natural := to_integer(unsigned(I2C_SLV_C));
constant TPD_C : time := 0 ns;
constant DEVMAP_C : I2cAxiLiteDevArray := (
0 => MakeI2cAxiLiteDevType( I2C_SLV_C, 8, 1, '1' ),
1 => MakeI2cAxiLiteDevType( I2C_SLV_C, 8, 8, '1' )
);
signal rama : slv(AB_C-1 downto 0);
signal wdat : slv(DB_C-1 downto 0);
signal rdat : slv(DB_C-1 downto 0) := x"a5";
signal ren : sl;
signal wen : sl;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal iicClk : sl := '0';
signal scl, sda : sl;
signal axilClk : sl := '0';
signal axilRst : sl := '1';
signal arm : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
signal ars : AxiLiteReadSlaveType;
signal awm : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
signal aws : AxiLiteWriteSlaveType;
signal bsy : sl := '0';
constant HP : time := 5 ns;
signal txRst : sl;
signal clkSel : sl := '1';
signal txRstReg : sl := '0';
signal count : integer := 0;
signal bsyDelay : natural := 0;
signal running : boolean := true;
type RegArray is array (natural range 7 to 12) of slv(DB_C - 1 downto 0);
signal r7to12 : RegArray := (
7 => ("000" & "00001"),
8 => ("11" & "000010"),
9 => x"BC",
10 => x"01",
11 => x"1E",
12 => x"B9"
);
signal r135 : slv(DB_C - 1 downto 0) := (others => '0');
signal r137 : slv(DB_C - 1 downto 0) := (others => '0');
begin
P_WR : process ( axilClk ) is
variable a : natural;
variable v135 : slv(r135'range);
variable dly : natural;
begin
if ( rising_edge( axilClk ) ) then
v135 := r135;
dly := bsyDelay;
a := to_integer(unsigned(rama));
if ( wen = '1' ) then
case ( a ) is
when 135 =>
v135 := wdat;
if ( wdat(0) = '1' ) then
dly := 100;
else
v135(0) := r135(0); -- canot reset
end if;
when 137 =>
r137 <= wdat;
when 7|8|9|10|11|12 =>
r7to12(a) <= wdat;
when others =>
end case;
end if;
if ( bsyDelay /= 0 ) then
dly := bsyDelay - 1;
if (dly = 0) then
v135(0) := '0';
end if;
end if;
bsyDelay <= dly;
r135 <= v135;
end if;
end process P_WR;
bsy <= r135(0);
P_RD : process( rama, r7to12, r135, r137 ) is
variable v : slv(rdat'range);
variable a : natural;
begin
v := x"A5";
a := to_integer(unsigned(rama));
case ( a ) is
when 135 => v := r135;
when 137 => v := r137;
when 7|8|9|10|11|12 =>
v := r7to12(a);
when others=>
end case;
rdat <= v;
end process P_RD;
U_DUT : entity dev_board_misc_utils.TimingClkSwitcher(TimingClkSwitcherSi570)
generic map (
TPD_G => TPD_C,
CLOCK_AXIL_BASE_ADDR_G => x"0000_0400",
TCASW_AXIL_BASE_ADDR_G => x"0000_0000",
AXIL_FREQ_G => 6.0E2
)
port map (
axilClk => axilClk,
axilRst => axilRst,
clkSel => clkSel,
txRst => txRst,
mAxilWriteMaster => awm,
mAxilWriteSlave => aws,
mAxilReadMaster => arm,
mAxilReadSlave => ars
);
P_CLK : process is
begin
if ( running ) then
axilClk <= not axilClk;
iicClk <= not iicClk;
wait for HP;
axilClk <= not axilClk;
wait for HP;
axilClk <= not axilClk;
wait for HP;
axilClk <= not axilClk;
wait for HP;
axilClk <= not axilClk;
wait for HP;
else
report "TEST PASSED";
wait;
end if;
end process P_CLK;
P_CNT : process(axilClk) is
variable c: integer;
begin
if ( rising_edge(axilClk) ) then
c := count + 1;
case count is
when 15 =>
axilRst <= '0';
-- when 30 => running <= false;
when others =>
end case;
count <= c;
end if;
end process P_CNT;
U_I2CM : entity surf.AxiI2cRegMaster
generic map (
TPD_G => TPD_C,
DEVICE_MAP_G => DEVMAP_C,
I2C_SCL_FREQ_G => 1.0,
I2C_MIN_PULSE_G => 0.1,
AXI_CLK_FREQ_G => 20.0
)
port map
(
scl => scl,
sda => sda,
axiReadMaster => arm,
axiReadSlave => ars,
axiWriteMaster => awm,
axiWriteSlave => aws,
axiClk => axilClk,
axiRst => axilRst
);
U_SCLBUF : IOBUF
port map (
IO => scl,
I => i2co.scl,
T => i2co.scloen,
O => i2ci.scl
);
U_SDABUF : IOBUF
port map (
IO => sda,
I => i2co.sda,
T => i2co.sdaoen,
O => i2ci.sda
);
sda <= 'H';
scl <= 'H';
U_Slv : entity surf.I2cRegSlave
generic map (
TPD_G => TPD_C,
I2C_ADDR_G => I2C_ADDR_C,
ADDR_SIZE_G => AS_C,
FILTER_G => 2
)
port map (
clk => axilClk,
addr => rama,
wrEn => wen,
wrData => wdat,
rdEn => ren,
rdData => rdat,
i2ci => i2ci,
i2co => i2co
);
P_CHECKER : process (axilClk) is
begin
if ( rising_edge( axilClk ) ) then
txRstReg <= txRst;
if ( txRst = '0' and txRstReg = '1' ) then
if ( clkSel = '1' ) then
assert r7to12( 7) = x"60" severity failure;
assert r7to12( 8) = x"42" severity failure;
assert r7to12( 9) = x"d8" severity failure;
assert r7to12(10) = x"01" severity failure;
assert r7to12(11) = x"2a" severity failure;
assert r7to12(12) = x"31" severity failure;
clkSel <= '0';
else
assert r7to12( 7) = x"E0" severity failure;
assert r7to12( 8) = x"42" severity failure;
assert r7to12( 9) = x"dd" severity failure;
assert r7to12(10) = x"0b" severity failure;
assert r7to12(11) = x"69" severity failure;
assert r7to12(12) = x"b2" severity failure;
running <= false;
end if;
end if;
end if;
end process P_CHECKER;
end architecture impl;
|
<filename>debouncer/debouncer_tb.vhd<gh_stars>10-100
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.bookUtility.ALL; -- for toString
ENTITY debouncer_tb IS
END;
ARCHITECTURE bench OF debouncer_tb IS
SIGNAL tD, tQ : std_logic;
SIGNAL tReset : STD_LOGIC;
SIGNAL tClk : STD_LOGIC := '0';
SIGNAL clockEnable : STD_LOGIC := '1';
BEGIN
clock : PROCESS
BEGIN
WHILE clockEnable = '1' LOOP
WAIT FOR 3 ps;
tClk <= NOT tClk;
-- REPORT "Clock tick [" & std_logic'image(tClk) & "]";
END LOOP;
WAIT;
END PROCESS;
testing : PROCESS
BEGIN
tReset <= '1';
tD <= '0';
WAIT FOR 1 ns;
tReset <= '0';
WAIT FOR 1 ns;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 10 ns;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 10 ns;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 14 ns;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 10 ps;
tD <= '1';
WAIT FOR 10 ps;
tD <= '0';
WAIT FOR 5 ns;
-- end
clockEnable <= '0';
REPORT "Test OK";
WAIT;
END PROCESS;
UUT : ENTITY work.debouncer PORT MAP(tClk, tReset, tD, tQ);
END bench;
|
<filename>firmware/targets/SmurfKcu1500RssiOffload10GbE/hdl/SmurfKcu1500RssiOffload10GbE.vhd
-------------------------------------------------------------------------------
-- File : SmurfKcu1500RssiOffload10GbE.vhd
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- This file is part of 'axi-pcie-dev'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'axi-pcie-dev', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiPkg.all;
use surf.AxiLitePkg.all;
use surf.AxiStreamPkg.all;
use surf.SsiPkg.all;
library axi_pcie_core;
use axi_pcie_core.MigPkg.all;
use work.AppPkg.all;
entity SmurfKcu1500RssiOffload10GbE is
generic (
TPD_G : time := 1 ns;
BUILD_INFO_G : BuildInfoType);
port (
---------------------
-- Application Ports
---------------------
-- QSFP[0] Ports
qsfp0RefClkP : in slv(1 downto 0);
qsfp0RefClkN : in slv(1 downto 0);
qsfp0RxP : in slv(3 downto 0);
qsfp0RxN : in slv(3 downto 0);
qsfp0TxP : out slv(3 downto 0);
qsfp0TxN : out slv(3 downto 0);
-- QSFP[1] Ports
qsfp1RefClkP : in slv(1 downto 0);
qsfp1RefClkN : in slv(1 downto 0);
qsfp1RxP : in slv(3 downto 0);
qsfp1RxN : in slv(3 downto 0);
qsfp1TxP : out slv(3 downto 0);
qsfp1TxN : out slv(3 downto 0);
-- DDR Ports
ddrClkP : in slv(3 downto 0);
ddrClkN : in slv(3 downto 0);
ddrOut : out DdrOutArray(3 downto 0);
ddrInOut : inout DdrInOutArray(3 downto 0);
--------------
-- Core Ports
--------------
-- System Ports
emcClk : in sl;
userClkP : in sl;
userClkN : in sl;
-- QSFP[0] Ports
qsfp0RstL : out sl;
qsfp0LpMode : out sl;
qsfp0ModSelL : out sl;
qsfp0ModPrsL : in sl;
-- QSFP[1] Ports
qsfp1RstL : out sl;
qsfp1LpMode : out sl;
qsfp1ModSelL : out sl;
qsfp1ModPrsL : in sl;
-- Boot Memory Ports
flashCsL : out sl;
flashMosi : out sl;
flashMiso : in sl;
flashHoldL : out sl;
flashWp : out sl;
-- PCIe Ports
pciRstL : in sl;
pciRefClkP : in sl;
pciRefClkN : in sl;
pciRxP : in slv(7 downto 0);
pciRxN : in slv(7 downto 0);
pciTxP : out slv(7 downto 0);
pciTxN : out slv(7 downto 0);
-- Extended PCIe Ports
pciExtRefClkP : in sl;
pciExtRefClkN : in sl;
pciExtRxP : in slv(7 downto 0);
pciExtRxN : in slv(7 downto 0);
pciExtTxP : out slv(7 downto 0);
pciExtTxN : out slv(7 downto 0));
end SmurfKcu1500RssiOffload10GbE;
architecture top_level of SmurfKcu1500RssiOffload10GbE is
constant CLK_FREQUENCY_C : real := 156.25E+6; -- units of Hz
constant NUM_AXIL_MASTERS_C : natural := 5;
constant AXIL_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := (
0 => (
baseAddr => x"0008_0000",
addrBits => 19,
connectivity => x"FFFF"),
1 => (
baseAddr => x"0010_0000",
addrBits => 20,
connectivity => x"FFFF"),
2 => (
baseAddr => x"0020_0000",
addrBits => 21,
connectivity => x"FFFF"),
3 => (
baseAddr => x"0040_0000",
addrBits => 22,
connectivity => x"FFFF"),
4 => (
baseAddr => x"0080_0000",
addrBits => 23,
connectivity => x"FFFF"));
signal bar0WriteMasters : AxiLiteWriteMasterArray(1 downto 0);
signal bar0WriteSlaves : AxiLiteWriteSlaveArray(1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C);
signal bar0ReadMasters : AxiLiteReadMasterArray(1 downto 0);
signal bar0ReadSlaves : AxiLiteReadSlaveArray(1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C);
signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C);
signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C);
signal userClk156 : sl;
signal axilClk : sl;
signal axilRst : sl;
signal axilReset : sl;
signal dmaPriClk : sl;
signal dmaPriRst : sl;
signal dmaPriObMasters : AxiStreamMasterArray(NUM_RSSI_C-1 downto 0);
signal dmaPriObSlaves : AxiStreamSlaveArray(NUM_RSSI_C-1 downto 0);
signal dmaPriIbMasters : AxiStreamMasterArray(NUM_RSSI_C-1 downto 0);
signal dmaPriIbSlaves : AxiStreamSlaveArray(NUM_RSSI_C-1 downto 0);
signal dmaSecClk : sl;
signal dmaSecRst : sl;
signal dmaSecObMasters : AxiStreamMasterArray(NUM_RSSI_C-1 downto 0);
signal dmaSecObSlaves : AxiStreamSlaveArray(NUM_RSSI_C-1 downto 0);
signal dmaSecIbMasters : AxiStreamMasterArray(NUM_RSSI_C-1 downto 0);
signal dmaSecIbSlaves : AxiStreamSlaveArray(NUM_RSSI_C-1 downto 0);
signal axiClk : sl;
signal axiRst : sl;
signal axiReset : sl;
signal ddrClk : slv((NUM_RSSI_C/2)-1 downto 0);
signal ddrRst : slv((NUM_RSSI_C/2)-1 downto 0);
signal ddrWriteMasters : AxiWriteMasterArray((NUM_RSSI_C/2)-1 downto 0);
signal ddrWriteSlaves : AxiWriteSlaveArray((NUM_RSSI_C/2)-1 downto 0);
signal ddrReadMasters : AxiReadMasterArray((NUM_RSSI_C/2)-1 downto 0);
signal ddrReadSlaves : AxiReadSlaveArray((NUM_RSSI_C/2)-1 downto 0);
begin
-----------------------
-- AXI-Lite Clock/Reset
-----------------------
U_axilClk : entity surf.ClockManagerUltraScale
generic map(
TPD_G => TPD_G,
TYPE_G => "MMCM",
INPUT_BUFG_G => true,
FB_BUFG_G => true,
RST_IN_POLARITY_G => '1',
NUM_CLOCKS_G => 2,
-- MMCM attributes
CLKIN_PERIOD_G => 6.4, -- 156.25 MHz
CLKFBOUT_MULT_G => 8, -- 1.25GHz = 8 x 156.25 MHz
-- CLKOUT0_DIVIDE_F_G => 10.0, -- 125 MHz (125 MHz x 128b = 16.0Gb/s > 10GbE)
CLKOUT0_DIVIDE_F_G => 12.5, -- 100 MHz (100 MHz x 128b = 12.8Gb/s > 10GbE)
CLKOUT1_DIVIDE_G => 8) -- 156.25 MHz (must match CLK_FREQUENCY_C)
port map(
-- Clock Input
clkIn => userClk156,
rstIn => dmaPriRst,
-- Clock Outputs
clkOut(0) => axiClk,
clkOut(1) => axilClk,
-- Reset Outputs
rstOut(0) => axiRst,
rstOut(1) => axilRst);
U_axiRst : entity surf.RstPipeline
generic map (
TPD_G => TPD_G)
port map (
clk => axiClk,
rstIn => axiRst,
rstOut => axiReset);
U_axilRst : entity surf.RstPipeline
generic map (
TPD_G => TPD_G)
port map (
clk => axilClk,
rstIn => axilRst,
rstOut => axilReset);
-----------------
-- MIG[0] IP Core
-----------------
U_Mig0 : entity axi_pcie_core.Mig0
generic map (
TPD_G => TPD_G)
port map (
extRst => dmaPriRst,
-- AXI MEM Interface
axiClk => ddrClk(2),
axiRst => ddrRst(2),
axiWriteMaster => ddrWriteMasters(2),
axiWriteSlave => ddrWriteSlaves(2),
axiReadMaster => ddrReadMasters(2),
axiReadSlave => ddrReadSlaves(2),
-- DDR Ports
ddrClkP => ddrClkP(0),
ddrClkN => ddrClkN(0),
ddrOut => ddrOut(0),
ddrInOut => ddrInOut(0));
-----------------
-- MIG[2] IP Core
-----------------
U_Mig2 : entity axi_pcie_core.Mig2
generic map (
TPD_G => TPD_G)
port map (
extRst => dmaPriRst,
-- AXI MEM Interface
axiClk => ddrClk(1),
axiRst => ddrRst(1),
axiWriteMaster => ddrWriteMasters(1),
axiWriteSlave => ddrWriteSlaves(1),
axiReadMaster => ddrReadMasters(1),
axiReadSlave => ddrReadSlaves(1),
-- DDR Ports
ddrClkP => ddrClkP(2),
ddrClkN => ddrClkN(2),
ddrOut => ddrOut(2),
ddrInOut => ddrInOut(2));
-----------------
-- MIG[3] IP Core
-----------------
U_Mig3 : entity axi_pcie_core.Mig3
generic map (
TPD_G => TPD_G)
port map (
extRst => dmaPriRst,
-- AXI MEM Interface
axiClk => ddrClk(0),
axiRst => ddrRst(0),
axiWriteMaster => ddrWriteMasters(0),
axiWriteSlave => ddrWriteSlaves(0),
axiReadMaster => ddrReadMasters(0),
axiReadSlave => ddrReadSlaves(0),
-- DDR Ports
ddrClkP => ddrClkP(3),
ddrClkN => ddrClkN(3),
ddrOut => ddrOut(3),
ddrInOut => ddrInOut(3));
---------------------
-- PCIE/DMA Interface
---------------------
U_Core : entity axi_pcie_core.XilinxKcu1500Core
generic map (
TPD_G => TPD_G,
BUILD_INFO_G => BUILD_INFO_G,
DMA_AXIS_CONFIG_G => APP_AXIS_CONFIG_C,
DMA_SIZE_G => NUM_RSSI_C)
port map (
------------------------
-- Top Level Interfaces
------------------------
userClk156 => userClk156,
-- DMA Interfaces
dmaClk => dmaPriClk,
dmaRst => dmaPriRst,
dmaObMasters => dmaPriObMasters,
dmaObSlaves => dmaPriObSlaves,
dmaIbMasters => dmaPriIbMasters,
dmaIbSlaves => dmaPriIbSlaves,
-- Application AXI-Lite Interfaces [0x00080000:0x00FFFFFF] (appClk domain)
appClk => axilClk,
appRst => axilReset,
appReadMaster => bar0ReadMasters(0),
appReadSlave => bar0ReadSlaves(0),
appWriteMaster => bar0WriteMasters(0),
appWriteSlave => bar0WriteSlaves(0),
--------------
-- Core Ports
--------------
-- System Ports
emcClk => emcClk,
userClkP => userClkP,
userClkN => userClkN,
-- QSFP[0] Ports
qsfp0RstL => qsfp0RstL,
qsfp0LpMode => qsfp0LpMode,
qsfp0ModSelL => qsfp0ModSelL,
qsfp0ModPrsL => qsfp0ModPrsL,
-- QSFP[1] Ports
qsfp1RstL => qsfp1RstL,
qsfp1LpMode => qsfp1LpMode,
qsfp1ModSelL => qsfp1ModSelL,
qsfp1ModPrsL => qsfp1ModPrsL,
-- Boot Memory Ports
flashCsL => flashCsL,
flashMosi => flashMosi,
flashMiso => flashMiso,
flashHoldL => flashHoldL,
flashWp => flashWp,
-- PCIe Ports
pciRstL => pciRstL,
pciRefClkP => pciRefClkP,
pciRefClkN => pciRefClkN,
pciRxP => pciRxP,
pciRxN => pciRxN,
pciTxP => pciTxP,
pciTxN => pciTxN);
U_ExtendedCore : entity axi_pcie_core.XilinxKcu1500PcieExtendedCore
generic map (
TPD_G => TPD_G,
BUILD_INFO_G => BUILD_INFO_G,
DMA_AXIS_CONFIG_G => APP_AXIS_CONFIG_C,
DMA_SIZE_G => NUM_RSSI_C)
port map (
------------------------
-- Top Level Interfaces
------------------------
-- DMA Interfaces
dmaClk => dmaSecClk,
dmaRst => dmaSecRst,
dmaObMasters => dmaSecObMasters,
dmaObSlaves => dmaSecObSlaves,
dmaIbMasters => dmaSecIbMasters,
dmaIbSlaves => dmaSecIbSlaves,
-- Application AXI-Lite Interfaces [0x00080000:0x00FFFFFF] (appClk domain)
appClk => axilClk,
appRst => axilReset,
appReadMaster => bar0ReadMasters(1),
appReadSlave => bar0ReadSlaves(1),
appWriteMaster => bar0WriteMasters(1),
appWriteSlave => bar0WriteSlaves(1),
--------------
-- Core Ports
--------------
-- Extended PCIe Ports
pciRstL => pciRstL,
pciExtRefClkP => pciExtRefClkP,
pciExtRefClkN => pciExtRefClkN,
pciExtRxP => pciExtRxP,
pciExtRxN => pciExtRxN,
pciExtTxP => pciExtTxP,
pciExtTxN => pciExtTxN);
----------------
-- AXI-Lite XBAR
----------------
U_XBAR : entity surf.AxiLiteCrossbar
generic map (
TPD_G => TPD_G,
NUM_SLAVE_SLOTS_G => 2,
NUM_MASTER_SLOTS_G => NUM_AXIL_MASTERS_C,
MASTERS_CONFIG_G => AXIL_CONFIG_C)
port map (
axiClk => axilClk,
axiClkRst => axilReset,
sAxiWriteMasters => bar0WriteMasters,
sAxiWriteSlaves => bar0WriteSlaves,
sAxiReadMasters => bar0ReadMasters,
sAxiReadSlaves => bar0ReadSlaves,
mAxiWriteMasters => axilWriteMasters,
mAxiWriteSlaves => axilWriteSlaves,
mAxiReadMasters => axilReadMasters,
mAxiReadSlaves => axilReadSlaves);
------------------
-- RSSI/ETH Module
------------------
U_Hardware : entity work.Hardware
generic map (
TPD_G => TPD_G,
CLK_FREQUENCY_G => CLK_FREQUENCY_C,
AXI_BASE_ADDR_G => AXIL_CONFIG_C(4).baseAddr)
port map (
------------------------
-- Top Level Interfaces
------------------------
-- AXI-Lite Interface (axilClk domain)
axilClk => axilClk,
axilRst => axilReset,
axilReadMaster => axilReadMasters(4),
axilReadSlave => axilReadSlaves(4),
axilWriteMaster => axilWriteMasters(4),
axilWriteSlave => axilWriteSlaves(4),
-- Primary DMA Interface (dmaPriClk domain)
dmaPriClk => dmaPriClk,
dmaPriRst => dmaPriRst,
dmaPriObMasters => dmaPriObMasters,
dmaPriObSlaves => dmaPriObSlaves,
dmaPriIbMasters => dmaPriIbMasters,
dmaPriIbSlaves => dmaPriIbSlaves,
-- Secondary DMA Interface (dmaSecClk domain)
dmaSecClk => dmaSecClk,
dmaSecRst => dmaSecRst,
dmaSecObMasters => dmaSecObMasters,
dmaSecObSlaves => dmaSecObSlaves,
dmaSecIbMasters => dmaSecIbMasters,
dmaSecIbSlaves => dmaSecIbSlaves,
-- DDR Memory Interface (ddrClk domain)
ddrClk => ddrClk,
ddrRst => ddrRst,
ddrWriteMasters => ddrWriteMasters,
ddrWriteSlaves => ddrWriteSlaves,
ddrReadMasters => ddrReadMasters,
ddrReadSlaves => ddrReadSlaves,
-- User AXI Clock and Reset
axiClk => axiClk,
axiRst => axiReset,
------------------
-- Hardware Ports
------------------
-- QSFP[0] Ports
qsfp0RefClkP => qsfp0RefClkP,
qsfp0RefClkN => qsfp0RefClkN,
qsfp0RxP => qsfp0RxP,
qsfp0RxN => qsfp0RxN,
qsfp0TxP => qsfp0TxP,
qsfp0TxN => qsfp0TxN,
-- QSFP[1] Ports
qsfp1RefClkP => qsfp1RefClkP,
qsfp1RefClkN => qsfp1RefClkN,
qsfp1RxP => qsfp1RxP,
qsfp1RxN => qsfp1RxN,
qsfp1TxP => qsfp1TxP,
qsfp1TxN => qsfp1TxN);
end top_level;
|
<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
use work.Arke_pkg.all;
entity Listener is
port(
clk: in std_logic;
rst: in std_logic;
writeCrtl: out std_logic;
tx_req: in std_logic;
stall_ack: out std_logic;
full: in std_logic;
data_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
eop_in: in std_logic;
data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
eop_out: out std_logic
);
end Listener;
architecture listener_behav of Listener is
type state is (waiting, syncComunication, asyncCommunication, holdAck, finnish);
signal currentListState: state;
signal txReq_reg: std_logic;
signal ack: std_logic;
signal reqTransition: std_logic;
signal reqTransition_reg: std_logic;
begin
reqTransition <= tx_req xor txReq_reg;
process(clk, rst)
begin
if(rst='1')then
reqTransition_reg <= '0';
txReq_reg <= tx_req;
ack <= '0';
elsif(rising_edge(clk))then
-- register the REQ edge for posterior use
reqTransition_reg <= reqTransition or reqTransition_reg;
txReq_reg <= tx_req;
case currentListState is
when waiting => -- Waits here until a header flit comes. Then select the type of the operation, Normal or Async
reqTransition_reg <= '0';
if tx_req = '1' and full = '0' then
if data_in(DATA_WIDTH-1) = '1' then
currentListState <= asyncCommunication;
ack <= '0';
else
currentListState <= syncComunication;
end if;
else
currentListState <= waiting;
end if;
when syncComunication =>
if eop_in = '1' and tx_req = '1' and full = '0' then
currentListState <= waiting;
else
currentListState <= syncComunication;
end if;
when asyncCommunication =>
if (reqTransition = '1' or reqTransition_reg = '1') then
ack <= not ack;
reqTransition_reg <= '0';
if full = '0' then
currentListState <= asyncCommunication;
else
currentListState <= holdAck;
end if;
elsif eop_in = '1' then
currentListState <= waiting;
ack <= '1';
end if;
--if (reqTransition = '1' or reqTransition_reg = '1') and full = '0' then
-- currentListState <= holdAck;
-- ack <= not ack;
-- reqTransition_reg <= '0';
--elsif eop_in = '1' then
-- currentListState <= waiting;
-- ack <= '1';
--else
-- currentListState <= asyncCommunication;
--end if;
when holdAck =>
if full = '1' then -- holds until there is space in the output queue for the next flit
currentListState <= holdAck;
else
currentListState <= asyncCommunication;
end if;
when finnish =>
-- comunicate that the last flit was saved
ack <= '1';
currentListState <= waiting;
when others =>
currentListState <= waiting;
end case;
end if;
end process;
--writeCrtl <= '1' when (((currentListState = waiting and data_in(DATA_WIDTH-1) = '0') or currentListState = syncComunication) and tx_req = '1') or
writeCrtl <= '1' when ((currentListState = waiting or currentListState = syncComunication) and tx_req = '1') or
(currentListState = asyncCommunication and (reqTransition = '1' or reqTransition_reg = '1' or eop_in = '1')) else '0';
stall_ack <= not full when currentListState = waiting or currentListState = syncComunication else
ack when currentListState = asyncCommunication or currentListState = holdAck or currentListState = finnish else
'0';
data_out <= data_in;
eop_out <= eop_in;
end listener_behav;
|
----------------------------------------------------------------------------------
--Copyright 2020 <NAME>
--Licensed under the Apache License, Version 2.0 (the "License"); you may not
--use this file except in compliance with the License. You may obtain a copy of
--the License at
-- http://www.apache.org/licenses/LICENSE-2.0
--Unless required by applicable law or agreed to in writing, software distributed
--under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES
--OR CONDITIONS OF ANY KIND, either express or implied. See the License for
--the specific language governing permissions and limitations under the License.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library stdblocks;
use stdblocks.sync_lib.all;
entity spi_irq_ctrl is
port (
--general
rst_i : in std_logic;
mclk_i : in std_logic;
master_irq_o : out std_logic;
vector_irq_o : out std_logic_vector(7 downto 0);
vector_irq_i : in std_logic_vector(7 downto 0);
vector_clr_i : in std_logic_vector(7 downto 0);
vector_msk_i : in std_logic_vector(7 downto 0)
);
end spi_irq_ctrl;
architecture behavioral of spi_irq_ctrl is
begin
irq_p : process(rst_i, mclk_i)
variable irq_flag : std_logic_vector(7 downto 0);
begin
if rst_i = '1' then
vector_irq_o <= "00000000";
irq_flag := "00000000";
master_irq_o <= '0';
elsif mclk_i = '1' and mclk_i'event then
for j in 7 downto 0 loop
if vector_msk_i(j) = '1' then
irq_flag(j) := '0';
elsif vector_clr_i(j) = '1' then
irq_flag(j) := '0';
elsif vector_irq_i(j) = '1' then
irq_flag(j) := '1';
end if;
vector_irq_o(j) <= irq_flag(j);
end loop;
--output
if irq_flag /= "00000000" then
master_irq_o <= '1';
else
master_irq_o <= '0';
end if;
end if;
end process;
end behavioral;
|
<gh_stars>1-10
-- ECE 378 - Final Project
-- 16-bit Microprocessor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DividerFSM is
Port ( clock : in STD_LOGIC;
resetn : in STD_LOGIC;
cout : in STD_LOGIC;
E : in STD_LOGIC;
zC : in STD_LOGIC;
LAB : out STD_LOGIC;
EA : out STD_LOGIC;
EC : out STD_LOGIC;
sclrC : out STD_LOGIC;
sclrR : out STD_LOGIC;
LR : out STD_LOGIC;
ER : out STD_LOGIC;
done : out STD_LOGIC);
end DividerFSM;
architecture struct of DividerFSM is
type state is (S1, S2, S3);
signal y: state;
begin
Transitions: process (clock, resetn, E, zC)
begin
if resetn = '0' then
y <= S1;
elsif (clock'event and clock = '1') then
case y is
when S1 =>
if E = '1' then y <= S2; else y <= S1; end if;
when S2 =>
if zC = '1' then y <= S3; else y <= S2; end if;
when S3 =>
if E = '1' then y <= S3; else y <= S1; end if;
end case;
end if;
end process;
Outputs: process (cout, E, zC, y)
begin
LAB <= '0';
EA <= '0';
EC <= '0';
sclrC <= '0';
sclrR <= '0';
LR <= '0';
ER <= '0';
done <= '0';
case y is
when S1 =>
sclrR <= '1';
ER <= '1';
EC <= '1';
sclrC <= '1';
if E = '1' then
LAB <= '1';
EA <= '1';
end if;
when S2 =>
ER <= '1';
EA <= '1';
if cout = '1' then
LR <= '1';
end if;
if zC = '0' then
EC <= '1';
end if;
when S3 =>
done <= '1';
end case;
end process;
end struct;
|
<reponame>necaticakaci/manta-c211
-- <NAME> - Benzetim (Testbench)
-- 2021
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.MANTA.ALL;
entity BENZETIM is
end BENZETIM;
architecture behavior of BENZETIM is
signal saat, reset : std_logic := '0';
signal giris: std_logic_vector(giris_port_genisligi-1 downto 0);
signal cikis: std_logic_vector(cikis_port_genisligi-1 downto 0);
begin
k1 : entity WORK.KABUK port map (saat, reset, giris, cikis);
reset <= '1'after 1 ns, '0' after 2 ns;
saat <= not saat after 10 ns;
giris <= x"2F";
end;
|
<filename>fpga/top-orangecrab0.2.vhdl<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_types.all;
entity toplevel is
generic (
MEMORY_SIZE : integer := 0;
RAM_INIT_FILE : string := "firmware.hex";
RESET_LOW : boolean := true;
CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000;
HAS_FPU : boolean := false;
HAS_BTC : boolean := false;
USE_LITEDRAM : boolean := false;
NO_BRAM : boolean := true;
DISABLE_FLATTEN_CORE : boolean := true;
SCLK_STARTUPE2 : boolean := false;
SPI_FLASH_OFFSET : integer := 4194304;
SPI_FLASH_DEF_CKDV : natural := 1;
SPI_FLASH_DEF_QUAD : boolean := true;
LOG_LENGTH : natural := 0;
UART_IS_16550 : boolean := true;
HAS_UART1 : boolean := false;
HAS_UARTUSB : boolean := true;
USE_LITESDCARD : boolean := true;
ICACHE_NUM_LINES : natural := 32;
NGPIO : natural := 0
);
port(
ext_clk : in std_ulogic;
ext_rst_n : in std_ulogic;
-- UART0 signals:
pin_gpio_0 : out std_ulogic;
pin_gpio_1 : in std_ulogic;
-- USB signals:
usb_d_p : in std_ulogic;
usb_d_n : in std_ulogic;
usb_pullup : out std_ulogic;
-- LEDs
led0_b : out std_ulogic;
led0_g : out std_ulogic;
led0_r : out std_ulogic;
-- SPI
spi_flash_cs_n : out std_ulogic;
spi_flash_mosi : inout std_ulogic;
spi_flash_miso : inout std_ulogic;
spi_flash_wp_n : inout std_ulogic;
spi_flash_hold_n : inout std_ulogic;
-- SD card wires
sdcard_data : inout std_ulogic_vector(3 downto 0);
sdcard_cmd : inout std_ulogic;
sdcard_clk : out std_ulogic;
sdcard_cd : in std_ulogic;
-- DRAM wires
ddram_a : out std_ulogic_vector(13 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
-- only the positive differential pin is instantiated
--ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
--ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
ddram_gnd : out std_ulogic_vector(1 downto 0);
ddram_vccio : out std_ulogic_vector(5 downto 0)
);
end entity toplevel;
architecture behaviour of toplevel is
-- Reset signals:
signal soc_rst : std_ulogic;
signal pll_rst : std_ulogic;
-- Internal clock signals:
signal system_clk : std_ulogic;
signal system_clk_locked : std_ulogic;
-- External IOs from the SoC
signal wb_ext_io_in : wb_io_master_out;
signal wb_ext_io_out : wb_io_slave_out;
signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic;
signal wb_ext_is_sdcard : std_ulogic;
-- DRAM main data wishbone connection
signal wb_dram_in : wishbone_master_out;
signal wb_dram_out : wishbone_slave_out;
-- DRAM control wishbone connection
signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
-- LiteSDCard connection
signal ext_irq_sdcard : std_ulogic := '0';
signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
signal wb_sddma_in : wb_io_slave_out;
signal wb_sddma_nr : wb_io_master_out;
signal wb_sddma_ir : wb_io_slave_out;
-- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic;
-- Control/status
signal core_alt_reset : std_ulogic;
-- Status LED
signal led0_b_pwm : std_ulogic;
signal led0_r_pwm : std_ulogic;
signal led0_g_pwm : std_ulogic;
-- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
signal pwm_counter : std_ulogic_vector(8 downto 0);
-- SPI flash
signal spi_sck : std_ulogic;
signal spi_cs_n : std_ulogic;
signal spi_sdat_o : std_ulogic_vector(3 downto 0);
signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
signal spi_sdat_i : std_ulogic_vector(3 downto 0);
-- GPIO
signal gpio_in : std_ulogic_vector(NGPIO - 1 downto 0);
signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0);
signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0);
-- Fixup various memory sizes based on generics
function get_bram_size return natural is
begin
if USE_LITEDRAM and NO_BRAM then
return 0;
else
return MEMORY_SIZE;
end if;
end function;
function get_payload_size return natural is
begin
if USE_LITEDRAM and NO_BRAM then
return MEMORY_SIZE;
else
return 0;
end if;
end function;
constant BRAM_SIZE : natural := get_bram_size;
constant PAYLOAD_SIZE : natural := get_payload_size;
COMPONENT USRMCLK
PORT(
USRMCLKI : IN STD_ULOGIC;
USRMCLKTS : IN STD_ULOGIC
);
END COMPONENT;
attribute syn_noprune: boolean ;
attribute syn_noprune of USRMCLK: component is true;
begin
-- Main SoC
soc0: entity work.soc
generic map(
MEMORY_SIZE => BRAM_SIZE,
RAM_INIT_FILE => RAM_INIT_FILE,
SIM => false,
CLK_FREQ => CLK_FREQUENCY,
HAS_FPU => HAS_FPU,
HAS_BTC => HAS_BTC,
HAS_DRAM => USE_LITEDRAM,
DRAM_SIZE => 256 * 1024 * 1024,
DRAM_INIT_SIZE => PAYLOAD_SIZE,
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
HAS_SPI_FLASH => true,
SPI_FLASH_DLINES => 4,
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
LOG_LENGTH => LOG_LENGTH,
UART0_IS_16550 => UART_IS_16550,
HAS_UART1 => HAS_UART1,
HAS_UARTUSB => HAS_UARTUSB,
HAS_SD_CARD => USE_LITESDCARD,
ICACHE_NUM_LINES => ICACHE_NUM_LINES,
HAS_SHORT_MULT => true,
NGPIO => NGPIO
)
port map (
-- System signals
system_clk => system_clk,
clk_48 => ext_clk,
rst => soc_rst,
-- UART signals
uart0_txd => pin_gpio_0,
uart0_rxd => pin_gpio_1,
usb_d_p => usb_d_p,
usb_d_n => usb_d_n,
usb_pullup => usb_pullup,
-- UART1 signals
--uart1_txd => uart_pmod_tx,
--uart1_rxd => uart_pmod_rx,
-- SPI signals
spi_flash_sck => spi_sck,
spi_flash_cs_n => spi_cs_n,
spi_flash_sdat_o => spi_sdat_o,
spi_flash_sdat_oe => spi_sdat_oe,
spi_flash_sdat_i => spi_sdat_i,
-- GPIO signals
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_dir => gpio_dir,
-- External interrupts
ext_irq_sdcard => ext_irq_sdcard,
-- DRAM wishbone
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
-- IO wishbone
wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init,
wb_ext_is_sdcard => wb_ext_is_sdcard,
-- DMA wishbone
wishbone_dma_in => wb_sddma_in,
wishbone_dma_out => wb_sddma_out,
alt_reset => core_alt_reset
);
--uart_pmod_rts_n <= '0';
-- SPI Flash
--
-- Note: Unlike many other boards, the SPI flash on the Arty has
-- an actual pin to generate the clock and doesn't require to use
-- the STARTUPE2 primitive.
--
spi_flash_cs_n <= spi_cs_n;
spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
spi_sdat_i(0) <= spi_flash_mosi;
spi_sdat_i(1) <= spi_flash_miso;
spi_sdat_i(2) <= spi_flash_wp_n;
spi_sdat_i(3) <= spi_flash_hold_n;
--spi_sclk_startupe2: if SCLK_STARTUPE2 generate
-- spi_flash_clk <= 'Z';
-- -- matt
-- --STARTUPE2_INST: STARTUPE2
-- -- port map (
-- -- CLK => '0',
-- -- GSR => '0',
-- -- GTS => '0',
-- -- KEYCLEARB => '0',
-- -- PACK => '0',
-- -- USRCCLKO => spi_sck,
-- -- USRCCLKTS => '0',
-- -- USRDONEO => '1',
-- -- USRDONETS => '0'
-- -- );
--end generate;
--spi_direct_sclk: if not SCLK_STARTUPE2 generate
-- spi_flash_clk <= spi_sck;
--end generate;
uclk: USRMCLK port map (
USRMCLKI => spi_sck,
USRMCLKTS => '0'
);
nodram: if not USE_LITEDRAM generate
signal ddram_clk_dummy : std_ulogic;
begin
reset_controller: entity work.soc_reset
generic map(
RESET_LOW => RESET_LOW
)
port map(
ext_clk => ext_clk,
pll_clk => system_clk,
pll_locked_in => system_clk_locked,
ext_rst_in => ext_rst_n,
pll_rst_out => pll_rst,
rst_out => soc_rst
);
clkgen: entity work.clock_generator
generic map(
CLK_INPUT_HZ => CLK_INPUT,
CLK_OUTPUT_HZ => CLK_FREQUENCY
)
port map(
ext_clk => ext_clk,
pll_rst_in => pll_rst,
pll_clk_out => system_clk,
pll_locked_out => system_clk_locked
);
led0_b_pwm <= '1';
led0_r_pwm <= '1';
led0_g_pwm <= '0';
core_alt_reset <= '0';
-- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed
-- it a constant '0'.
-- matt
--dummy_dram_clk: OBUFDS
-- port map (
-- O => ddram_clk_p,
-- OB => ddram_clk_n,
-- I => ddram_clk_dummy
-- );
--ddram_clk_dummy <= '0';
end generate;
has_dram: if USE_LITEDRAM generate
signal dram_init_done : std_ulogic;
signal dram_init_error : std_ulogic;
signal dram_sys_rst : std_ulogic;
signal rst_gen_rst : std_ulogic;
begin
-- Eventually dig out the frequency from
-- litesdram generate.py sys_clk_freq
-- but for now, assert it's 48Mhz for orangecrab
assert CLK_FREQUENCY = 48000000;
reset_controller: entity work.soc_reset
generic map(
RESET_LOW => RESET_LOW,
PLL_RESET_BITS => 18,
SOC_RESET_BITS => 1
)
port map(
ext_clk => ext_clk,
pll_clk => system_clk,
pll_locked_in => system_clk_locked,
ext_rst_in => ext_rst_n,
pll_rst_out => pll_rst,
rst_out => rst_gen_rst
);
-- Generate SoC reset
soc_rst_gen: process(system_clk)
begin
if ext_rst_n = '0' then
soc_rst <= '1';
elsif rising_edge(system_clk) then
soc_rst <= dram_sys_rst or not system_clk_locked;
end if;
end process;
dram: entity work.litedram_wrapper
generic map(
DRAM_ABITS => 24,
DRAM_ALINES => 14,
DRAM_DLINES => 16,
DRAM_PORT_WIDTH => 128,
PAYLOAD_FILE => RAM_INIT_FILE,
PAYLOAD_SIZE => PAYLOAD_SIZE
)
port map(
clk_in => ext_clk,
rst => pll_rst,
system_clk => system_clk,
system_reset => dram_sys_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked,
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_ctrl_in => wb_ext_io_in,
wb_ctrl_out => wb_dram_ctrl_out,
wb_ctrl_is_csr => wb_ext_is_dram_csr,
wb_ctrl_is_init => wb_ext_is_dram_init,
init_done => dram_init_done,
init_error => dram_init_error,
ddram_a => ddram_a,
ddram_ba => ddram_ba,
ddram_ras_n => ddram_ras_n,
ddram_cas_n => ddram_cas_n,
ddram_we_n => ddram_we_n,
ddram_cs_n => ddram_cs_n,
ddram_dm => ddram_dm,
ddram_dq => ddram_dq,
ddram_dqs_p => ddram_dqs_p,
ddram_clk_p => ddram_clk_p,
-- only the positive differential pin is instantiated
--ddram_dqs_n => ddram_dqs_n,
--ddram_clk_n => ddram_clk_n,
ddram_cke => ddram_cke,
ddram_odt => ddram_odt,
ddram_reset_n => ddram_reset_n
);
ddram_gnd <= "00";
-- for power consumption.
-- https://github.com/orangecrab-fpga/orangecrab-hardware/issues/19#issuecomment-683479378
ddram_vccio <= "111111";
led0_b_pwm <= not dram_init_done;
led0_r_pwm <= dram_init_error;
led0_g_pwm <= dram_init_done and not dram_init_error;
end generate;
-- SD card pmod
has_sdcard : if USE_LITESDCARD generate
component litesdcard_core port (
clk : in std_ulogic;
rst : in std_ulogic;
-- wishbone for accessing control registers
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
wb_ctrl_cyc : in std_ulogic;
wb_ctrl_stb : in std_ulogic;
wb_ctrl_ack : out std_ulogic;
wb_ctrl_we : in std_ulogic;
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
wb_ctrl_err : out std_ulogic;
-- wishbone for SD card core to use for DMA
wb_dma_adr : out std_ulogic_vector(29 downto 0);
wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
wb_dma_sel : out std_ulogic_vector(3 downto 0);
wb_dma_cyc : out std_ulogic;
wb_dma_stb : out std_ulogic;
wb_dma_ack : in std_ulogic;
wb_dma_we : out std_ulogic;
wb_dma_cti : out std_ulogic_vector(2 downto 0);
wb_dma_bte : out std_ulogic_vector(1 downto 0);
wb_dma_err : in std_ulogic;
-- connections to SD card
sdcard_data : inout std_ulogic_vector(3 downto 0);
sdcard_cmd : inout std_ulogic;
sdcard_clk : out std_ulogic;
sdcard_cd : in std_ulogic;
irq : out std_ulogic
);
end component;
signal wb_sdcard_cyc : std_ulogic;
signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
begin
litesdcard : litesdcard_core
port map (
clk => system_clk,
rst => soc_rst,
wb_ctrl_adr => wb_sdcard_adr,
wb_ctrl_dat_w => wb_ext_io_in.dat,
wb_ctrl_dat_r => wb_sdcard_out.dat,
wb_ctrl_sel => wb_ext_io_in.sel,
wb_ctrl_cyc => wb_sdcard_cyc,
wb_ctrl_stb => wb_ext_io_in.stb,
wb_ctrl_ack => wb_sdcard_out.ack,
wb_ctrl_we => wb_ext_io_in.we,
wb_ctrl_cti => "000",
wb_ctrl_bte => "00",
wb_ctrl_err => open,
wb_dma_adr => wb_sddma_nr.adr,
wb_dma_dat_w => wb_sddma_nr.dat,
wb_dma_dat_r => wb_sddma_ir.dat,
wb_dma_sel => wb_sddma_nr.sel,
wb_dma_cyc => wb_sddma_nr.cyc,
wb_dma_stb => wb_sddma_nr.stb,
wb_dma_ack => wb_sddma_ir.ack,
wb_dma_we => wb_sddma_nr.we,
wb_dma_cti => open,
wb_dma_bte => open,
wb_dma_err => '0',
sdcard_data => sdcard_data,
sdcard_cmd => sdcard_cmd,
sdcard_clk => sdcard_clk,
sdcard_cd => sdcard_cd,
irq => ext_irq_sdcard
);
-- Gate cyc with chip select from SoC
wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
wb_sdcard_out.stall <= not wb_sdcard_out.ack;
-- Convert non-pipelined DMA wishbone to pipelined by suppressing
-- non-acknowledged strobes
process(system_clk)
begin
if rising_edge(system_clk) then
wb_sddma_out <= wb_sddma_nr;
if wb_sddma_stb_sent = '1' or
(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
wb_sddma_out.stb <= '0';
end if;
if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
wb_sddma_stb_sent <= '0';
elsif wb_sddma_in.stall = '0' then
wb_sddma_stb_sent <= wb_sddma_nr.stb;
end if;
wb_sddma_ir <= wb_sddma_in;
end if;
end process;
end generate;
-- Mux WB response on the IO bus
wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else
wb_dram_ctrl_out;
leds_pwm : process(system_clk)
begin
if rising_edge(system_clk) then
pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
if pwm_counter(8 downto 4) = "00000" then
led0_b <= led0_b_pwm;
led0_r <= led0_r_pwm;
led0_g <= led0_g_pwm;
else
led0_b <= '0';
led0_r <= '0';
led0_g <= '0';
end if;
end if;
end process;
end architecture behaviour;
|
<reponame>eshopper99/pacman<gh_stars>0
--
-- A simulation model of Pacman hardware
-- Copyright (c) MikeJ & CarlW - January 2006
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email <EMAIL>
--
-- Revision list
--
-- version 003 Jan 2006 release, general tidy up
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.pkg_pacman.all;
entity X74_157 is
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
G : in std_logic;
S : in std_logic
);
end;
architecture RTL of X74_157 is
begin
p_y_comb : process(S,G,A,B)
begin
for i in 0 to 3 loop
-- quad 2 line to 1 line mux (true logic)
if (G = '1') then
Y(i) <= '0';
else
if (S = '0') then
Y(i) <= A(i);
else
Y(i) <= B(i);
end if;
end if;
end loop;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.pkg_pacman.all;
entity X74_257 is
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
S : in std_logic
);
end;
architecture RTL of X74_257 is
signal ab : std_logic_vector (3 downto 0);
begin
Y <= ab; -- no tristate
p_ab : process(S,A,B)
begin
for i in 0 to 3 loop
if (S = '0') then
AB(i) <= A(i);
else
AB(i) <= B(i);
end if;
end loop;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.pkg_pacman.all;
entity PACMAN_VRAM_ADDR is
port (
AB : out std_logic_vector (11 downto 0);
H256_L : in std_logic;
H128 : in std_logic;
H64 : in std_logic;
H32 : in std_logic;
H16 : in std_logic;
H8 : in std_logic;
H4 : in std_logic;
H2 : in std_logic;
H1 : in std_logic;
V128 : in std_logic;
V64 : in std_logic;
V32 : in std_logic;
V16 : in std_logic;
V8 : in std_logic;
V4 : in std_logic;
V2 : in std_logic;
V1 : in std_logic;
FLIP : in std_logic
);
end;
architecture RTL of PACMAN_VRAM_ADDR is
signal v128p : std_logic;
signal v64p : std_logic;
signal v32p : std_logic;
signal v16p : std_logic;
signal v8p : std_logic;
signal h128p : std_logic;
signal h64p : std_logic;
signal h32p : std_logic;
signal h16p : std_logic;
signal h8p : std_logic;
signal sel : std_logic;
signal y157 : std_logic_vector (11 downto 0);
component X74_157
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
G : in std_logic;
S : in std_logic
);
end component;
component X74_257
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
S : in std_logic
);
end component;
begin
p_vp_comb : process(FLIP, V8, V16, V32, V64, V128)
begin
v128p <= FLIP xor V128;
v64p <= FLIP xor V64;
v32p <= FLIP xor V32;
v16p <= FLIP xor V16;
v8p <= FLIP xor V8;
end process;
p_hp_comb : process(FLIP, H8, H16, H32, H64, H128)
begin
H128P <= FLIP xor H128;
H64P <= FLIP xor H64;
H32P <= FLIP xor H32;
H16P <= FLIP xor H16;
H8P <= FLIP xor H8;
end process;
p_sel : process(H16, H32, H64)
begin
sel <= not((H32 xor H16) or (H32 xor H64));
end process;
--p_oe257 : process(H2)
--begin
-- oe <= not(H2);
--end process;
U6 : X74_157
port map(
Y => y157(11 downto 8),
B(3) => '0',
B(2) => H4,
B(1) => h64p,
B(0) => h64p,
A => "1111",
G => '0',
S => sel
);
U5 : X74_157
port map(
Y => y157(7 downto 4),
B(3) => h64p,
B(2) => h64p,
B(1) => h8p,
B(0) => v128p,
A => "1111",
G => '0',
S => sel
);
U4 : X74_157
port map(
Y => y157(3 downto 0),
B(3) => v64p,
B(2) => v32p,
B(1) => v16p,
B(0) => v8p,
A(3) => H64,
A(2) => H32,
A(1) => H16,
A(0) => H4,
G => '0',
S => sel
);
U3 : X74_257
port map(
Y => AB(11 downto 8),
B(3) => '0',
B(2) => H4,
B(1) => v128p,
B(0) => v64p,
A => y157(11 downto 8),
S => H256_L
);
U2 : X74_257
port map(
Y => AB(7 downto 4),
B(3) => v32p,
B(2) => v16p,
B(1) => v8p,
B(0) => h128p,
A => y157(7 downto 4),
S => H256_L
);
U1 : X74_257
port map(
Y => AB(3 downto 0),
B(3) => h64p,
B(2) => h32p,
B(1) => h16p,
B(0) => h8p,
A => y157(3 downto 0),
S => H256_L
);
end RTL;
|
<reponame>sputnixru/PothosZynq
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9552)
`protect data_block
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|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity regsync_tb is
-- Port ( );
end regsync_tb;
architecture Behavioral of regsync_tb is
signal clk_int: std_logic := '0';
signal rst_int, load_int: std_logic;
signal q_int, d_int: std_logic_vector(3 downto 0);
constant t_per: time := 20 ns;
component register_synch_load is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (3 downto 0);
load : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end component;
begin
uut: register_synch_load
port map(
d => d_int,
q => q_int,
load => load_int,
clk => clk_int,
rst => rst_int
);
tiktok: process
begin
wait for t_per/2;
clk_int <= not clk_int;
wait for t_per/2;
clk_int <= not clk_int;
end process;
main: process
begin
d_int <= "0000";
rst_int <= '0';
load_int <= '0';
wait for t_per;
d_int <= "0101";
wait for t_per;
wait for t_per;
load_int <= '1';
wait for t_per;
load_int <= '0';
wait for t_per;
d_int <= "1001";
wait for t_per;
wait for t_per;
load_int <= '1';
wait for t_per;
load_int <= '0';
wait for t_per;
rst_int <= '1';
wait for t_per;
wait for t_per;
load_int <= '1';
wait for t_per;
load_int <= '0';
wait for t_per;
rst_int <= '0';
wait;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity eight_bit_equal is
port ( a, b : in std_logic_vector(7 downto 0);
aeqb : out std_logic);
end eight_bit_equal;
architecture arch of eight_bit_equal is
component equal
port (
I0, I1 : in std_logic;
Eq: out std_logic);
end component;
signal e0, e1, e2, e3, e4, e5, e6, e7 : std_logic;
begin
H1: equal port map(i0=>a(0), i1=>b(0), eq=>e0);
H2: equal port map(i0=>a(1), i1=>b(1), eq=>e1);
H3: equal port map(i0=>a(2), i1=>b(2), eq=>e2);
H4: equal port map(i0=>a(3), i1=>b(3), eq=>e3);
H5: equal port map(i0=>a(4), i1=>b(4), eq=>e4);
H6: equal port map(i0=>a(5), i1=>b(5), eq=>e5);
H7: equal port map(i0=>a(6), i1=>b(6), eq=>e6);
H8: equal port map(i0=>a(7), i1=>b(7), eq=>e7);
aeqb <= e0 and e1 and e2 and e3 and e4 and e5 and e6 and e7;
end arch;
|
<gh_stars>10-100
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
entity oscilloscope_tb is
end oscilloscope_tb;
architecture arch of oscilloscope_tb is
component oscilloscope is
generic (
ADC_DATA_WIDTH : integer := 12;
MAX_UPSAMPLE : integer := 4;
MAX_DOWNSAMPLE : integer := 3
);
port (
clock : in std_logic;
reset : in std_logic;
horizontal_scale : in std_logic_vector(31 downto 0); -- us/div
vertical_scale : in std_logic_vector(31 downto 0) := x"00000200"; -- mV/div
upsample : in integer range 0 to MAX_UPSAMPLE; -- upsampling rate is 2 ** upsample
downsample : in integer range 0 to MAX_DOWNSAMPLE; -- downsampling rate is 2 ** downsample
interpolation_enable : in std_logic := '1';
trigger_type : in std_logic := '1'; -- '1' for rising edge, '0' for falling edge
trigger_ref : in std_logic_vector(ADC_DATA_WIDTH - 1 downto 0) := x"800";
trigger_correction_enable : in std_logic := '1';
adc_data : in std_logic_vector(ADC_DATA_WIDTH - 1 downto 0);
adc_sample : in std_logic;
pixel_clock : out std_logic;
hsync, vsync : out std_logic;
r, g, b : out std_logic_vector(7 downto 0)
);
end component;
component analog_waveform_generator is
generic (N : integer);
port (
clock : in std_logic;
reset : in std_logic;
update : in std_logic := '1';
frequency_control : in std_logic_vector(N-1 downto 0);
analog_waveform : out std_logic_vector(7 downto 0)
);
end component;
constant HI : std_logic := '1';
constant LOW : std_logic := '0';
constant space : string := " ";
constant colon : string := ":";
constant clock_period : time := 20 ns;
constant sample_period : time := 2 us;
signal clock : std_logic;
signal reset : std_logic;
signal horizontal_scale : std_logic_vector(31 downto 0);
signal upsample : integer range 0 to 4;
signal downsample : integer range 0 to 3;
signal adc_data : std_logic_vector(11 downto 0);
signal adc_sample : std_logic;
signal frequency_control : std_logic_vector(15 downto 0);
signal analog_waveform : std_logic_vector(7 downto 0);
signal pixel_clock : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal r : std_logic_vector(7 downto 0);
signal g : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
begin
dut : oscilloscope
port map (
clock => clock,
reset => reset,
horizontal_scale => horizontal_scale,
upsample => upsample,
downsample => downsample,
adc_data => adc_data,
adc_sample => adc_sample,
pixel_clock => pixel_clock,
hsync => hsync,
vsync => vsync,
r => r,
g => g,
b => b
);
sig_gen : analog_waveform_generator
generic map (N => 16)
port map (
clock => clock,
reset => reset,
frequency_control => frequency_control,
analog_waveform => analog_waveform
);
adc_data <= analog_waveform & "0000";
clock_process : process
begin
clock <= '0';
wait for clock_period / 2;
clock <= '1';
wait for clock_period / 2;
end process;
sampling_process : process
begin
adc_sample <= '0';
wait for sample_period - clock_period;
adc_sample <= '1';
wait for clock_period;
end process;
output_process : process (clock)
file vga_log : text is out "test-results/oscilloscope_log.txt";
variable vga_line : line;
begin
if (rising_edge(clock)) then
write(vga_line, now);
write(vga_line, colon & space);
write(vga_line, hsync);
write(vga_line, space);
write(vga_line, vsync);
write(vga_line, space);
write(vga_line, r);
write(vga_line, space);
write(vga_line, g);
write(vga_line, space);
write(vga_line, b);
writeline(vga_log, vga_line);
end if;
end process;
test_process : process
begin
reset <= '1';
wait until rising_edge(clock);
reset <= '0';
-- 1 kHz
upsample <= 0;
downsample <= 1;
horizontal_scale <= std_logic_vector(to_unsigned(256, 32));
frequency_control <= x"0083";
wait for 14 ms;
wait for 14 ms;
-- 10 kHz
upsample <= 2;
downsample <= 0;
horizontal_scale <= std_logic_vector(to_unsigned(32, 32));
frequency_control <= x"051F";
wait for 14 ms;
wait for 14 ms;
-- 100 kHz
upsample <= 4;
horizontal_scale <= std_logic_vector(to_unsigned(8, 32));
frequency_control <= x"3333";
wait for 14 ms;
-- 200 kHz
frequency_control <= x"6666";
wait for 14 ms;
wait;
end process;
end architecture;
|
<filename>priority/priority.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority is
port (
sel : in std_logic_vector(7 downto 0);
code : out unsigned(2 downto 0)
);
end priority;
architecture imp of priority is
begin
code <= "000" when sel(0) = '1' else
"001" when sel(1) = '1' else
"010" when sel(2) = '1' else
"011" when sel(3) = '1' else
"100" when sel(4) = '1' else
"101" when sel(5) = '1' else
"110" when sel(6) = '1' else
"111";
end imp;
|
<reponame>McDeggy/KVM_prototype
-- generated by newgenasym Tue May 08 15:18:08 2018
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity adv7511kstz is
port (
AVDD: INOUT STD_LOGIC;
AVDD_2: INOUT STD_LOGIC;
AVDD_3: INOUT STD_LOGIC;
BGVDD: INOUT STD_LOGIC;
CEC: INOUT STD_LOGIC;
CEC_CLK: INOUT STD_LOGIC;
CLK: INOUT STD_LOGIC;
D0: INOUT STD_LOGIC;
D1: INOUT STD_LOGIC;
D10: INOUT STD_LOGIC;
D11: INOUT STD_LOGIC;
D12: INOUT STD_LOGIC;
D13: INOUT STD_LOGIC;
D14: INOUT STD_LOGIC;
D15: INOUT STD_LOGIC;
D16: INOUT STD_LOGIC;
D17: INOUT STD_LOGIC;
D18: INOUT STD_LOGIC;
D19: INOUT STD_LOGIC;
D2: INOUT STD_LOGIC;
D20: INOUT STD_LOGIC;
D21: INOUT STD_LOGIC;
D22: INOUT STD_LOGIC;
D23: INOUT STD_LOGIC;
D24: INOUT STD_LOGIC;
D25: INOUT STD_LOGIC;
D26: INOUT STD_LOGIC;
D27: INOUT STD_LOGIC;
D28: INOUT STD_LOGIC;
D29: INOUT STD_LOGIC;
D3: INOUT STD_LOGIC;
D30: INOUT STD_LOGIC;
D31: INOUT STD_LOGIC;
D32: INOUT STD_LOGIC;
D33: INOUT STD_LOGIC;
D34: INOUT STD_LOGIC;
D35: INOUT STD_LOGIC;
D4: INOUT STD_LOGIC;
D5: INOUT STD_LOGIC;
D6: INOUT STD_LOGIC;
D7: INOUT STD_LOGIC;
D8: INOUT STD_LOGIC;
D9: INOUT STD_LOGIC;
DDCSCL: INOUT STD_LOGIC;
DDCSDA: INOUT STD_LOGIC;
DE: INOUT STD_LOGIC;
DSD0: INOUT STD_LOGIC;
DSD1: INOUT STD_LOGIC;
DSD2: INOUT STD_LOGIC;
DSD3: INOUT STD_LOGIC;
DSD4: INOUT STD_LOGIC;
DSD5: INOUT STD_LOGIC;
DSD_CLK: INOUT STD_LOGIC;
DVDD: INOUT STD_LOGIC;
DVDD_2: INOUT STD_LOGIC;
DVDD_3: INOUT STD_LOGIC;
DVDD_4: INOUT STD_LOGIC;
DVDD_5: INOUT STD_LOGIC;
GND: INOUT STD_LOGIC;
GND_10: INOUT STD_LOGIC;
GND_11: INOUT STD_LOGIC;
GND_2: INOUT STD_LOGIC;
GND_3: INOUT STD_LOGIC;
GND_4: INOUT STD_LOGIC;
GND_5: INOUT STD_LOGIC;
GND_6: INOUT STD_LOGIC;
GND_7: INOUT STD_LOGIC;
GND_8: INOUT STD_LOGIC;
GND_9: INOUT STD_LOGIC;
\heac+\: INOUT STD_LOGIC;
\heac-\: INOUT STD_LOGIC;
HPD: INOUT STD_LOGIC;
HSYNC: INOUT STD_LOGIC;
INT: INOUT STD_LOGIC;
ISO0: INOUT STD_LOGIC;
ISO1: INOUT STD_LOGIC;
ISO2: INOUT STD_LOGIC;
ISO3: INOUT STD_LOGIC;
LRCLK: INOUT STD_LOGIC;
MCLK: INOUT STD_LOGIC;
MVDD: INOUT STD_LOGIC;
PD: INOUT STD_LOGIC;
PLVDD: INOUT STD_LOGIC;
PVDD: INOUT STD_LOGIC;
PVDD_2: INOUT STD_LOGIC;
R_EXT: INOUT STD_LOGIC;
SCL: INOUT STD_LOGIC;
SCLK: INOUT STD_LOGIC;
SDA: INOUT STD_LOGIC;
SPDIF: INOUT STD_LOGIC;
SPDIF_OUT: INOUT STD_LOGIC;
SYNC: INOUT STD_LOGIC;
\tx0+\: INOUT STD_LOGIC;
\tx0-\: INOUT STD_LOGIC;
\tx1+\: INOUT STD_LOGIC;
\tx1-\: INOUT STD_LOGIC;
\tx2+\: INOUT STD_LOGIC;
\tx2-\: INOUT STD_LOGIC;
\txc+\: INOUT STD_LOGIC;
\txc-\: INOUT STD_LOGIC);
end adv7511kstz;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
entity AddSub8Bit is
port (A,B: in STD_Logic_Vector(7 downto 0);
bool: in bit;
carry: out std_logic;
sum: out std_logic_vector(7 downto 0));
end AddSub8Bit;
-------------------------------------------------
architecture behavioral of AddSub8Bit is
signal result: std_logic_vector (8 downto 0);
begin
result <= ('0' & A) + ('0' & B) when bool = '0' else ('0' & A) - ('0' & B);
sum <= result(7 downto 0);
carry <= result(8);
end behavioral;
|
-- Testbench for FD
--
-- SPDX-FileCopyrightText: (c) 2020 <NAME> <<EMAIL>>
-- SPDX-License-Identifier: Apache-2.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_openfd_core is
end;
architecture behav of tb_openfd_core is
constant period : time := 10 ns;
signal clk_i : std_logic;
signal rst_n_i : std_logic;
signal trigger_o : std_logic;
signal coarse_i : std_logic_vector(31 downto 0);
signal fine_i : std_logic_vector(15 downto 0);
signal valid_i : std_logic;
signal pulse : std_logic;
signal cur_cycles : std_logic_vector(31 downto 0);
signal done : boolean := false;
begin
dut: entity work.openfd_core
generic map (
plen => 7)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
cur_cycles_i => cur_cycles,
coarse_i => coarse_i,
fine_i => fine_i,
valid_i => valid_i,
out_o => pulse);
process
begin
clk_i <= '0';
wait for period / 2;
clk_i <= '1';
wait for period / 2;
if done then
wait;
end if;
end process;
-- Cur_cycles
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cur_cycles <= (others => '0');
else
cur_cycles <= std_logic_vector(unsigned(cur_cycles) + 1);
end if;
end if;
end process;
process
variable t1: time;
begin
rst_n_i <= '0';
valid_i <= '0';
wait for 2 * period;
wait until rising_edge(clk_i);
rst_n_i <= '1';
assert cur_cycles = x"0000_0000";
wait until cur_cycles = x"0000_0001";
t1 := now;
report "cur_cycles = 1";
-- Setup.
coarse_i <= x"0000_0004";
fine_i <= x"001b"; -- 27
valid_i <= '1';
wait until rising_edge (clk_i);
valid_i <= '0';
wait until rising_edge (pulse);
assert now = t1 + 3 * period + 27 * 100 ps;
report "done";
done <= true;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- Title : Full-adder
-- Project : Number Theoretical Transform
-------------------------------------------------------------------------------
-- File : fa.vhd
-- Author : <NAME> <<EMAIL>>
-- Company :
-- Date : 2021
-------------------------------------------------------------------------------
-- Copyright (c) 2021 <NAME> and <NAME>
-- <<EMAIL>>
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity FullAdder is
port (A, B, CI : in std_logic; -- operands
S, CO : out std_logic); -- sum and carry out
end FullAdder;
-------------------------------------------------------------------------------
architecture behavior of FullAdder is
signal Auns, Buns, CIuns, Suns : unsigned(1 downto 0); -- unsigned temp
begin
Auns <= '0' & A;
Buns <= '0' & B;
CIuns <= '0' & CI;
Suns <= Auns + Buns + CIuns;
S <= Suns(0);
CO <= Suns(1);
end behavior;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/21/2021 07:27:29 PM
-- Design Name:
-- Module Name: led_bar - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std. all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sound_signal is
Port (
clk_i : in std_logic; -- main clock
dist_i : in integer; --distance input
buzzer : out std_logic --buzzer output
);
end sound_signal;
architecture Behavioral of sound_signal is
--t_state creates new type of variable with declared values
type t_state is (CM10, CM20, CM30, CM40, CM60, CM80, CM100, CM120, CM140, CM160, LOW);
signal s_state : t_state; --creates signal according to t_state
signal s_en : std_logic; --signal for buzzer frequency (normally frequecy should be 2,4kHz due to simulation lenght we used clock frequency)
--signal s_reset : std_logic ;
signal s_cnt : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0000_0000"; --buzzer counter signal
signal s_cnt_1 : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0000_0000"; --break counter signal
--constants for time delay
--if we change constatns value time of beep or break will be longer or shorter
constant c_DELAY_100ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0000_0010";
constant c_DELAY_200ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0000_0100";
constant c_DELAY_300ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0000_1000";
constant c_DELAY_400ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0000_1010";
constant c_DELAY_500ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0001_0101";
constant c_DELAY_600ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0010_0110";
constant c_DELAY_700ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0011_0111";
constant c_DELAY_800ms : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0101_1100";
constant c_DELAY_1s : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_1111_0000";
constant c_DELAY_BEEP : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0001_0101";
constant c_ZERO : unsigned(28 - 1 downto 0) := b"0000_0000_0000_0000_0000_0000_0000";
begin
clk_en0 : entity work.clock_enable --instance copy of clock_enable entity
generic map(
g_MAX => 100
)
port map(
clk => clk_i,
reset => '0',
ce_o => s_en
);
--following the distance sets time of PWM and break on buzzer output
sound : process(clk_i)
begin
if (rising_edge(clk_i)) then
if (dist_i <= 580) then --if the distance in condition is verified
if (s_state /= CM10) then --and s_state value isn't set
s_state <= CM10; --sets s_state
s_cnt <= c_ZERO; --null counters
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 1160) then
if (s_state /= CM20) then
s_state <= CM20;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 1740) then
if (s_state /= CM30) then
s_state <= CM30;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 2320) then
if (s_state /= CM40) then
s_state <= CM40;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 3480) then
if (s_state /= CM60) then
s_state <= CM60;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 4640) then
if (s_state /= CM80) then
s_state <= CM80;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 5800) then
if (s_state /= CM100) then
s_state <= CM100;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 6960) then
if (s_state /= CM120) then
s_state <= CM120;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 8120) then
if (s_state /= CM140) then
s_state <= CM140;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i <= 9280) then
if (s_state /= CM160) then
s_state <= CM160;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
elsif (dist_i > 9280) then
if (s_state /= LOW) then
s_state <= LOW;
s_cnt <= c_ZERO;
s_cnt_1 <= c_ZERO;
end if;
end if;
end if;
case s_state is
when CM10 =>
buzzer <= clk_i; --sets constant PWM on buzzer
when CM20 => --if s_state same as condition(CM20)
if (s_cnt < c_DELAY_BEEP) then --if counter is smaller then beep time
buzzer <= clk_i; --sets buzzer to s_en state (used clk_i instead for simulation lenght)
s_cnt <= s_cnt + 1; --add 1 to counter
s_cnt_1 <= c_ZERO; --null counter2
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_100ms) then --if counter for beep time is in time range, counter2 starts to count
buzzer <= '0'; --turn of buzzer
s_cnt_1 <= s_cnt_1 + 1; --add 1 to counter2
elsif (s_cnt_1 = c_DELAY_100ms) then --if counter2 is same as delay
s_cnt_1 <= c_ZERO; --null counters
s_cnt <= c_ZERO;
end if;
when CM30 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_200ms) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_200ms) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when CM40 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_300ms) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_300ms) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when CM60 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_400ms) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_400ms) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when CM80 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_500ms) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_500ms) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when CM100 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_600ms) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_600ms) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when CM120 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_700ms) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_700ms) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when CM140 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_800ms) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_800ms) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when CM160 =>
if (s_cnt < c_DELAY_BEEP) then
buzzer <= clk_i;
s_cnt <= s_cnt + 1;
s_cnt_1 <= c_ZERO;
elsif (s_cnt = c_DELAY_BEEP) and (s_cnt_1 < c_DELAY_1s) then
buzzer <= '0';
s_cnt_1 <= s_cnt_1 + 1;
elsif (s_cnt_1 = c_DELAY_1s) then
s_cnt_1 <= c_ZERO;
s_cnt <= c_ZERO;
end if;
when LOW => --if the distance is too high
buzzer <= '0'; --counter and buzzer are disabled
when others =>
end case;
end process;
end Behavioral;
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`protect end_protected
|
<filename>Vivado_HLS_Tutorial/Design_Analysis/lab1/dct_prj/solution1/syn/vhdl/dct.vhd
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dct is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
input_r_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
input_r_ce0 : OUT STD_LOGIC;
input_r_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
output_r_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
output_r_ce0 : OUT STD_LOGIC;
output_r_we0 : OUT STD_LOGIC;
output_r_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of dct is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"dct,hls_ip_2015_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.790000,HLS_SYN_LAT=3959,HLS_SYN_TPT=none,HLS_SYN_MEM=5,HLS_SYN_DSP=1,HLS_SYN_FF=272,HLS_SYN_LUT=354}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_24 : BOOLEAN;
signal r_fu_162_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal r_reg_309 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_51 : BOOLEAN;
signal tmp_i_fu_172_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_i_reg_314 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond1_i_fu_156_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_addr_cast_fu_188_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_addr_cast_reg_319 : STD_LOGIC_VECTOR (7 downto 0);
signal c_fu_202_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal c_reg_327 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_68 : BOOLEAN;
signal exitcond_i_fu_196_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_addr1_fu_222_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_addr1_reg_337 : STD_LOGIC_VECTOR (7 downto 0);
signal r_1_fu_237_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal r_1_reg_345 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_84 : BOOLEAN;
signal tmp_i5_fu_247_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_i5_reg_350 : STD_LOGIC_VECTOR (5 downto 0);
signal exitcond1_i3_fu_231_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_addr2_cast_fu_263_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_addr2_cast_reg_355 : STD_LOGIC_VECTOR (7 downto 0);
signal c_1_fu_277_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal c_1_reg_363 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_100 : BOOLEAN;
signal exitcond_i7_fu_271_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_i_fu_297_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_i_reg_373 : STD_LOGIC_VECTOR (5 downto 0);
signal buf_2d_in_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal buf_2d_in_ce0 : STD_LOGIC;
signal buf_2d_in_we0 : STD_LOGIC;
signal buf_2d_in_d0 : STD_LOGIC_VECTOR (15 downto 0);
signal buf_2d_in_q0 : STD_LOGIC_VECTOR (15 downto 0);
signal buf_2d_out_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal buf_2d_out_ce0 : STD_LOGIC;
signal buf_2d_out_we0 : STD_LOGIC;
signal buf_2d_out_d0 : STD_LOGIC_VECTOR (15 downto 0);
signal buf_2d_out_q0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_dct_dct_2d_fu_148_ap_start : STD_LOGIC;
signal grp_dct_dct_2d_fu_148_ap_done : STD_LOGIC;
signal grp_dct_dct_2d_fu_148_ap_idle : STD_LOGIC;
signal grp_dct_dct_2d_fu_148_ap_ready : STD_LOGIC;
signal grp_dct_dct_2d_fu_148_in_block_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_dct_dct_2d_fu_148_in_block_ce0 : STD_LOGIC;
signal grp_dct_dct_2d_fu_148_in_block_q0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_dct_dct_2d_fu_148_out_block_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_dct_dct_2d_fu_148_out_block_ce0 : STD_LOGIC;
signal grp_dct_dct_2d_fu_148_out_block_we0 : STD_LOGIC;
signal grp_dct_dct_2d_fu_148_out_block_d0 : STD_LOGIC_VECTOR (15 downto 0);
signal r_i_reg_104 : STD_LOGIC_VECTOR (3 downto 0);
signal c_i_reg_115 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_156 : BOOLEAN;
signal r_i2_reg_126 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_165 : BOOLEAN;
signal c_i6_reg_137 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_179 : BOOLEAN;
signal grp_dct_dct_2d_fu_148_ap_start_ap_start_reg : STD_LOGIC := '0';
signal tmp_6_i_fu_213_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_227_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_292_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_i_fu_302_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_fu_168_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_1_fu_180_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal c_i_cast6_fu_192_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_5_i_fu_208_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_7_i_trn_cast_fu_218_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_fu_243_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_3_fu_255_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_8_i_trn_cast_fu_283_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_addr3_fu_287_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal c_i6_cast2_fu_267_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
component dct_dct_2d IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
in_block_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
in_block_ce0 : OUT STD_LOGIC;
in_block_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
out_block_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
out_block_ce0 : OUT STD_LOGIC;
out_block_we0 : OUT STD_LOGIC;
out_block_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component dct_dct_2d_row_outbuf IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (5 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (15 downto 0);
q0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
buf_2d_in_U : component dct_dct_2d_row_outbuf
generic map (
DataWidth => 16,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => buf_2d_in_address0,
ce0 => buf_2d_in_ce0,
we0 => buf_2d_in_we0,
d0 => buf_2d_in_d0,
q0 => buf_2d_in_q0);
buf_2d_out_U : component dct_dct_2d_row_outbuf
generic map (
DataWidth => 16,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => buf_2d_out_address0,
ce0 => buf_2d_out_ce0,
we0 => buf_2d_out_we0,
d0 => buf_2d_out_d0,
q0 => buf_2d_out_q0);
grp_dct_dct_2d_fu_148 : component dct_dct_2d
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_dct_dct_2d_fu_148_ap_start,
ap_done => grp_dct_dct_2d_fu_148_ap_done,
ap_idle => grp_dct_dct_2d_fu_148_ap_idle,
ap_ready => grp_dct_dct_2d_fu_148_ap_ready,
in_block_address0 => grp_dct_dct_2d_fu_148_in_block_address0,
in_block_ce0 => grp_dct_dct_2d_fu_148_in_block_ce0,
in_block_q0 => grp_dct_dct_2d_fu_148_in_block_q0,
out_block_address0 => grp_dct_dct_2d_fu_148_out_block_address0,
out_block_ce0 => grp_dct_dct_2d_fu_148_out_block_ce0,
out_block_we0 => grp_dct_dct_2d_fu_148_out_block_we0,
out_block_d0 => grp_dct_dct_2d_fu_148_out_block_d0);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_dct_dct_2d_fu_148_ap_start_ap_start_reg assign process. --
grp_dct_dct_2d_fu_148_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_dct_dct_2d_fu_148_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond1_i_fu_156_p2 = ap_const_lv1_0)))) then
grp_dct_dct_2d_fu_148_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_dct_dct_2d_fu_148_ap_ready)) then
grp_dct_dct_2d_fu_148_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_i6_reg_137 assign process. --
c_i6_reg_137_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
c_i6_reg_137 <= c_1_reg_363;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = exitcond1_i3_fu_231_p2))) then
c_i6_reg_137 <= ap_const_lv4_0;
end if;
end if;
end process;
-- c_i_reg_115 assign process. --
c_i_reg_115_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
c_i_reg_115 <= c_reg_327;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond1_i_fu_156_p2 = ap_const_lv1_0))) then
c_i_reg_115 <= ap_const_lv4_0;
end if;
end if;
end process;
-- r_i2_reg_126 assign process. --
r_i2_reg_126_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = exitcond_i7_fu_271_p2)))) then
r_i2_reg_126 <= r_1_reg_345;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_logic_0 = grp_dct_dct_2d_fu_148_ap_done)))) then
r_i2_reg_126 <= ap_const_lv4_0;
end if;
end if;
end process;
-- r_i_reg_104 assign process. --
r_i_reg_104_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = exitcond_i_fu_196_p2)))) then
r_i_reg_104 <= r_reg_309;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
r_i_reg_104 <= ap_const_lv4_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
c_1_reg_363 <= c_1_fu_277_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
c_reg_327 <= c_fu_202_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = exitcond_i_fu_196_p2))) then
p_addr1_reg_337 <= p_addr1_fu_222_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = exitcond1_i3_fu_231_p2))) then
p_addr2_cast_reg_355(6 downto 3) <= p_addr2_cast_fu_263_p1(6 downto 3);
tmp_i5_reg_350(5 downto 3) <= tmp_i5_fu_247_p3(5 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond1_i_fu_156_p2 = ap_const_lv1_0))) then
p_addr_cast_reg_319(6 downto 3) <= p_addr_cast_fu_188_p1(6 downto 3);
tmp_i_reg_314(5 downto 3) <= tmp_i_fu_172_p3(5 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
r_1_reg_345 <= r_1_fu_237_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
r_reg_309 <= r_fu_162_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = exitcond_i7_fu_271_p2))) then
tmp_9_i_reg_373 <= tmp_9_i_fu_297_p2;
end if;
end if;
end process;
tmp_i_reg_314(2 downto 0) <= "000";
p_addr_cast_reg_319(2 downto 0) <= "000";
p_addr_cast_reg_319(7) <= '0';
tmp_i5_reg_350(2 downto 0) <= "000";
p_addr2_cast_reg_355(2 downto 0) <= "000";
p_addr2_cast_reg_355(7) <= '0';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond1_i_fu_156_p2, exitcond_i_fu_196_p2, exitcond1_i3_fu_231_p2, exitcond_i7_fu_271_p2, grp_dct_dct_2d_fu_148_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((exitcond1_i_fu_156_p2 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st3_fsm_2 =>
if (not((ap_const_lv1_0 = exitcond_i_fu_196_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st5_fsm_4 =>
if (not((ap_const_logic_0 = grp_dct_dct_2d_fu_148_ap_done))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
if (not((ap_const_lv1_0 = exitcond1_i3_fu_231_p2))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
if (not((ap_const_lv1_0 = exitcond_i7_fu_271_p2))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st6_fsm_5, exitcond1_i3_fu_231_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = exitcond1_i3_fu_231_p2)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st6_fsm_5, exitcond1_i3_fu_231_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = exitcond1_i3_fu_231_p2)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_100 assign process. --
ap_sig_bdd_100_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_100 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_156 assign process. --
ap_sig_bdd_156_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_156 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_165 assign process. --
ap_sig_bdd_165_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_165 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_179 assign process. --
ap_sig_bdd_179_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_179 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_24 assign process. --
ap_sig_bdd_24_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_24 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_51 assign process. --
ap_sig_bdd_51_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_51 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_68 assign process. --
ap_sig_bdd_68_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_68 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_84 assign process. --
ap_sig_bdd_84_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_84 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_24)
begin
if (ap_sig_bdd_24) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_51)
begin
if (ap_sig_bdd_51) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_68)
begin
if (ap_sig_bdd_68) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_156)
begin
if (ap_sig_bdd_156) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_165)
begin
if (ap_sig_bdd_165) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_84)
begin
if (ap_sig_bdd_84) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_100)
begin
if (ap_sig_bdd_100) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_179)
begin
if (ap_sig_bdd_179) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- buf_2d_in_address0 assign process. --
buf_2d_in_address0_assign_proc : process(grp_dct_dct_2d_fu_148_in_block_address0, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st5_fsm_4, tmp_4_fu_227_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
buf_2d_in_address0 <= tmp_4_fu_227_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
buf_2d_in_address0 <= grp_dct_dct_2d_fu_148_in_block_address0;
else
buf_2d_in_address0 <= "XXXXXX";
end if;
end process;
-- buf_2d_in_ce0 assign process. --
buf_2d_in_ce0_assign_proc : process(grp_dct_dct_2d_fu_148_in_block_ce0, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st5_fsm_4)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
buf_2d_in_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
buf_2d_in_ce0 <= grp_dct_dct_2d_fu_148_in_block_ce0;
else
buf_2d_in_ce0 <= ap_const_logic_0;
end if;
end process;
buf_2d_in_d0 <= input_r_q0;
-- buf_2d_in_we0 assign process. --
buf_2d_in_we0_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
buf_2d_in_we0 <= ap_const_logic_1;
else
buf_2d_in_we0 <= ap_const_logic_0;
end if;
end process;
-- buf_2d_out_address0 assign process. --
buf_2d_out_address0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, grp_dct_dct_2d_fu_148_out_block_address0, ap_sig_cseq_ST_st5_fsm_4, tmp_5_fu_292_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
buf_2d_out_address0 <= tmp_5_fu_292_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
buf_2d_out_address0 <= grp_dct_dct_2d_fu_148_out_block_address0;
else
buf_2d_out_address0 <= "XXXXXX";
end if;
end process;
-- buf_2d_out_ce0 assign process. --
buf_2d_out_ce0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, grp_dct_dct_2d_fu_148_out_block_ce0, ap_sig_cseq_ST_st5_fsm_4)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
buf_2d_out_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
buf_2d_out_ce0 <= grp_dct_dct_2d_fu_148_out_block_ce0;
else
buf_2d_out_ce0 <= ap_const_logic_0;
end if;
end process;
buf_2d_out_d0 <= grp_dct_dct_2d_fu_148_out_block_d0;
-- buf_2d_out_we0 assign process. --
buf_2d_out_we0_assign_proc : process(grp_dct_dct_2d_fu_148_out_block_we0, ap_sig_cseq_ST_st5_fsm_4)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
buf_2d_out_we0 <= grp_dct_dct_2d_fu_148_out_block_we0;
else
buf_2d_out_we0 <= ap_const_logic_0;
end if;
end process;
c_1_fu_277_p2 <= std_logic_vector(unsigned(c_i6_reg_137) + unsigned(ap_const_lv4_1));
c_fu_202_p2 <= std_logic_vector(unsigned(c_i_reg_115) + unsigned(ap_const_lv4_1));
c_i6_cast2_fu_267_p1 <= std_logic_vector(resize(unsigned(c_i6_reg_137),6));
c_i_cast6_fu_192_p1 <= std_logic_vector(resize(unsigned(c_i_reg_115),6));
exitcond1_i3_fu_231_p2 <= "1" when (r_i2_reg_126 = ap_const_lv4_8) else "0";
exitcond1_i_fu_156_p2 <= "1" when (r_i_reg_104 = ap_const_lv4_8) else "0";
exitcond_i7_fu_271_p2 <= "1" when (c_i6_reg_137 = ap_const_lv4_8) else "0";
exitcond_i_fu_196_p2 <= "1" when (c_i_reg_115 = ap_const_lv4_8) else "0";
grp_dct_dct_2d_fu_148_ap_start <= grp_dct_dct_2d_fu_148_ap_start_ap_start_reg;
grp_dct_dct_2d_fu_148_in_block_q0 <= buf_2d_in_q0;
input_r_address0 <= tmp_6_i_fu_213_p1(6 - 1 downto 0);
-- input_r_ce0 assign process. --
input_r_ce0_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
input_r_ce0 <= ap_const_logic_1;
else
input_r_ce0 <= ap_const_logic_0;
end if;
end process;
output_r_address0 <= tmp_3_i_fu_302_p1(6 - 1 downto 0);
-- output_r_ce0 assign process. --
output_r_ce0_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
output_r_ce0 <= ap_const_logic_1;
else
output_r_ce0 <= ap_const_logic_0;
end if;
end process;
output_r_d0 <= buf_2d_out_q0;
-- output_r_we0 assign process. --
output_r_we0_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then
output_r_we0 <= ap_const_logic_1;
else
output_r_we0 <= ap_const_logic_0;
end if;
end process;
p_addr1_fu_222_p2 <= std_logic_vector(unsigned(tmp_7_i_trn_cast_fu_218_p1) + unsigned(p_addr_cast_reg_319));
p_addr2_cast_fu_263_p1 <= std_logic_vector(resize(unsigned(tmp_3_fu_255_p3),8));
p_addr3_fu_287_p2 <= std_logic_vector(unsigned(tmp_8_i_trn_cast_fu_283_p1) + unsigned(p_addr2_cast_reg_355));
p_addr_cast_fu_188_p1 <= std_logic_vector(resize(unsigned(tmp_1_fu_180_p3),8));
r_1_fu_237_p2 <= std_logic_vector(unsigned(r_i2_reg_126) + unsigned(ap_const_lv4_1));
r_fu_162_p2 <= std_logic_vector(unsigned(r_i_reg_104) + unsigned(ap_const_lv4_1));
tmp_1_fu_180_p3 <= (r_i_reg_104 & ap_const_lv3_0);
tmp_2_fu_243_p1 <= r_i2_reg_126(3 - 1 downto 0);
tmp_3_fu_255_p3 <= (r_i2_reg_126 & ap_const_lv3_0);
tmp_3_i_fu_302_p1 <= std_logic_vector(resize(unsigned(tmp_9_i_reg_373),64));
tmp_4_fu_227_p1 <= std_logic_vector(resize(unsigned(p_addr1_reg_337),64));
tmp_5_fu_292_p1 <= std_logic_vector(resize(unsigned(p_addr3_fu_287_p2),64));
tmp_5_i_fu_208_p2 <= std_logic_vector(unsigned(tmp_i_reg_314) + unsigned(c_i_cast6_fu_192_p1));
tmp_6_i_fu_213_p1 <= std_logic_vector(resize(unsigned(tmp_5_i_fu_208_p2),64));
tmp_7_i_trn_cast_fu_218_p1 <= std_logic_vector(resize(unsigned(c_i_reg_115),8));
tmp_8_i_trn_cast_fu_283_p1 <= std_logic_vector(resize(unsigned(c_i6_reg_137),8));
tmp_9_i_fu_297_p2 <= std_logic_vector(unsigned(tmp_i5_reg_350) + unsigned(c_i6_cast2_fu_267_p1));
tmp_fu_168_p1 <= r_i_reg_104(3 - 1 downto 0);
tmp_i5_fu_247_p3 <= (tmp_2_fu_243_p1 & ap_const_lv3_0);
tmp_i_fu_172_p3 <= (tmp_fu_168_p1 & ap_const_lv3_0);
end behav;
|
rom_inst : rom PORT MAP (
address_a => address_a_sig,
address_b => address_b_sig,
clock => clock_sig,
q_a => q_a_sig,
q_b => q_b_sig
);
|
<gh_stars>1-10
library verilog;
use verilog.vl_types.all;
entity Test_ALU is
end Test_ALU;
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:48:16 12/22/2009
-- Design Name:
-- Module Name: d_ff - d_ff_beh
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity d_ff is
generic ( n : integer := 8);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC_VECTOR ((n - 1) downto 0);
q : out STD_LOGIC_VECTOR ((n - 1) downto 0));
end d_ff;
architecture d_ff_beh of d_ff is
begin
process(clk, rst) begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end d_ff_beh;
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-08T14:25:09+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package enforcement_types_AlphabetEnforcer is
type enforced_signals_AlphabetEnforcer is record
--put the enforced signals in here
A : std_logic;
B : std_logic;
C : std_logic;
D : std_logic;
L : std_logic;
end record;
end enforcement_types_AlphabetEnforcer;
|
<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
entity parking_phase2 is
port( KEY : in std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
LEDR : out std_logic_vector(1 downto 0);
LEDG : out std_logic_vector(8 downto 8));
end parking_phase2;
architecture Shell of parking_phase2 is
signal s_key_start, s_pulseOut, s_clk_2hz: std_logic;
begin
t1: entity work.timer(Behavioral)
generic map(TIME_S => 10) -- Time in seconds (10 s)
port map(clk => CLOCK_50,
start => s_key_start,
pulseOut_10 => s_pulseOut,
pulseOut_8 => LEDR(1),
pulseOut_1 => LEDR(0));
f2: entity work.freqDivider(Behavioral)
generic map(DIV_FACTOR => 25E6)
port map( clkIn => CLOCK_50,
clkOut => s_clk_2hz);
LEDG(8) <= s_pulseOut and s_clk_2hz;
s_key_start<= not KEY(0);
end Shell;
|
----------------------------------------------------------------------------------
-- Company: none
-- Engineer: <NAME> and <NAME>
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rat_cpu is
Port( IN_PORT : in STD_LOGIC_VECTOR(7 downto 0);
INT_IN, RST : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_PORT : out STD_LOGIC_VECTOR(7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR(7 downto 0);
IO_OE : out STD_LOGIC);
end rat_cpu;
architecture rat_cpu_a of rat_cpu is
component prog_rom is
Port( ADDRESS : in STD_LOGIC_VECTOR(9 downto 0);
CLK : in STD_LOGIC;
TRISTATE_IN : in STD_LOGIC_VECTOR(7 downto 0);
INSTRUCTION : out STD_LOGIC_VECTOR(17 downto 0));
end component;
component flag_reg is
Port( IN_FLAG, SAVE : in STD_LOGIC; --flag input // save the flag value (?)
LD, SET, CLR : in STD_LOGIC; --load the out_flag with the in_flag value // set the flag to '1' // clear the flag to '0'
CLK, RESTORE : in STD_LOGIC; --system clock // restore the flag value (?)
OUT_FLAG : out STD_LOGIC); --flag output
end component;
component program_counter is
Port( CLK, RST, OE : in STD_LOGIC;
LOAD : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(1 downto 0);
FROM_IMMED : in STD_LOGIC_VECTOR(9 downto 0);
FROM_STACK : in STD_LOGIC_VECTOR(9 downto 0);
PC_COUNT : out STD_LOGIC_VECTOR(9 downto 0);
PC_TRI : inout STD_LOGIC_VECTOR(9 downto 0));
end component;
component stack_pointer is
Port( INC_DEC : in STD_LOGIC_VECTOR (1 downto 0);
D_IN : in STD_LOGIC_VECTOR (7 downto 0);
WE, RST, CLK : in STD_LOGIC;
STK_PNTR : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component scratch_pad is
Port( FROM_IMMED : in STD_LOGIC_VECTOR(7 downto 0);
FROM_SP : in STD_LOGIC_VECTOR(7 downto 0);
FROM_RF : in STD_LOGIC_VECTOR(7 downto 0);
FROM_SP_DEC : in STD_LOGIC_VECTOR(7 downto 0);
SCR_ADDR_SEL : in STD_LOGIC_VECTOR(1 downto 0);
SCR_WE, SCR_OE : in STD_LOGIC;
CLK : in STD_LOGIC;
SP_DATA : inout STD_LOGIC_VECTOR(9 downto 0));
end component;
component alu
Port( SEL : in STD_LOGIC_VECTOR(3 downto 0);
A, B_FROM_REG : in STD_LOGIC_VECTOR(7 downto 0);
B_FROM_INSTR : in STD_LOGIC_VECTOR(7 downto 0);
C_IN, MUX_SEL : in STD_LOGIC;
SUM : out STD_LOGIC_VECTOR(7 downto 0);
C_FLAG, Z_FLAG : out STD_LOGIC);
end component;
component register_file
Port( FROM_IN_PORT : in STD_LOGIC_VECTOR(7 downto 0);
FROM_TRI_STATE : in STD_LOGIC_VECTOR(7 downto 0);
FROM_ALU : in STD_LOGIC_VECTOR(7 downto 0);
RF_MUX_SEL : in STD_LOGIC_VECTOR(1 downto 0);
ADRX, ADRY : in STD_LOGIC_VECTOR(4 downto 0);
WE, CLK, DX_OE : in STD_LOGIC;
DX_OUT, DY_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component control_unit
Port( CLK, C, Z, INT, RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0); --From the instruction register
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD, PC_OE, SP_LD, RESET : out STD_LOGIC; --Load PC EN // PC output enable // stack pointer load // Reset PC and SP
PC_MUX_SEL, INC_DEC : out STD_LOGIC_VECTOR (1 downto 0); --PC mux sel// SP input mux sel
ALU_MUX_SEL : out STD_LOGIC; --alu mux sel
RF_WR, RF_OE, SCR_WR, SCR_OE : out STD_LOGIC; --RF Write EN // RF Tristate Output // SP write EN // SP output EN
RF_WR_SEL, SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0); -- Reg File Mux // sp mux sel
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
C_FLAG_SAVE, C_FLAG_RESTORE : out STD_LOGIC; -- C flag save and restore
Z_FLAG_SAVE, Z_FLAG_RESTORE : out STD_LOGIC; -- Z flag save and restore
C_FLAG_LD, C_FLAG_SET, C_FLAG_CLR : out STD_LOGIC; -- C flag set, clear, and load
Z_FLAG_LD, Z_FLAG_SET, Z_FLAG_CLR : out STD_LOGIC; -- Z flag set, clear, and load
I_FLAG_SET, I_FLAG_CLR, IO_OE : out STD_LOGIC); -- Set Interrupt // clear interrupt // I/O enable
end component;
signal CU_RESET_i, I_COMB_i : STD_LOGIC;
signal C_IN_i, Z_IN_i, C_OUT_i, Z_OUT_i : STD_LOGIC;
signal C_LD_i, Z_LD_i, C_SET_i, Z_SET_i : STD_LOGIC;
signal C_CLR_i, Z_CLR_i, I_SET_i, I_CLR_i : STD_LOGIC;
signal PC_LD_i, PC_OE_i, RF_OE_i, RF_WR_i : STD_LOGIC;
signal ALU_MUX_SEL_i, I_OUT_i, SP_LD_i : STD_LOGIC;
signal SCR_WR_i, SCR_OE_i, Z_SAVE_i : STD_LOGIC;
signal C_RESTORE_i, Z_RESTORE_i, C_SAVE_i : STD_LOGIC;
signal INC_DEC_i, RF_WR_SEL_i : STD_LOGIC_VECTOR(1 downto 0);
signal SCR_ADDR_SEL_i, PC_MUX_SEL_i : STD_LOGIC_VECTOR(1 downto 0);
signal ALU_SEL_i : STD_LOGIC_VECTOR(3 downto 0);
signal ALU_OUT_i, ADRY_OUT_i : STD_LOGIC_VECTOR(7 downto 0);
signal STK_PNTR_OUT_i : STD_LOGIC_VECTOR(7 downto 0);
signal TRISTATE_BUS_i, PC_COUNT_i : STD_LOGIC_VECTOR(9 downto 0);
signal INSTRUCTION_i : STD_LOGIC_VECTOR(17 downto 0);
begin
out_port <= tristate_bus_i(7 downto 0);
port_id <= instruction_i(7 downto 0);
i_comb_i <= int_in and i_out_i;
prog_rom1 : prog_rom port map(
address => pc_count_i,
instruction => instruction_i,
tristate_in => tristate_bus_i(7 downto 0),
clk => clk);
c_flag : flag_reg port map(
in_flag => c_in_i,
ld => c_ld_i,
set => c_set_i,
clr => c_clr_i,
clk => clk,
restore => c_restore_i,
save => c_save_i,
out_flag => c_out_i);
z_flag : flag_reg port map(
in_flag => z_in_i,
ld => z_ld_i,
set => z_set_i,
clr => z_clr_i,
clk => clk,
restore => z_restore_i,
save => z_save_i,
out_flag => z_out_i);
i_flag : flag_reg port map(
in_flag => '0',
ld => '0',
set => i_set_i,
clr => i_clr_i,
clk => clk,
restore => '0',
save => '0',
out_flag => i_out_i);
program_counter1 : program_counter port map(
clk => clk,
rst => cu_reset_i,
load => pc_ld_i,
oe => pc_oe_i,
sel => pc_mux_sel_i,
from_immed => instruction_i(12 downto 3),
from_stack => tristate_bus_i,
pc_count => pc_count_i,
pc_tri => tristate_bus_i);
stack_pointer1 : stack_pointer port map(
inc_dec => inc_dec_i,
d_in => tristate_bus_i(7 downto 0),
we => sp_ld_i,
rst => cu_reset_i,
clk => clk,
stk_pntr => stk_pntr_out_i);
scratch_pad1: scratch_pad port map(
clk => clk,
scr_we => scr_wr_i,
scr_oe => scr_oe_i,
scr_addr_sel => scr_addr_sel_i,
from_immed => instruction_i(7 downto 0),
from_sp => stk_pntr_out_i,
from_sp_dec => stk_pntr_out_i, --This is correct, deincrement is done INTERNALLY
from_rf => adry_out_i,
sp_data => tristate_bus_i);
alu1 : alu port map(
sel => alu_sel_i,
a => tristate_bus_i(7 downto 0),
b_from_reg => adry_out_i,
b_from_instr => instruction_i(7 downto 0),
c_in => c_out_i,
mux_sel => alu_mux_sel_i,
sum => alu_out_i,
c_flag => c_in_i,
z_flag => z_in_i);
register_file1 : register_file port map(
from_in_port => in_port,
from_tri_state => tristate_bus_i(7 downto 0),
from_alu => alu_out_i,
rf_mux_sel => rf_wr_sel_i,
adrx => instruction_i(12 downto 8),
adry => instruction_i(7 downto 3),
we => rf_wr_i,
clk => clk,
dx_oe => rf_oe_i,
dx_out => tristate_bus_i(7 downto 0),
dy_out => adry_out_i);
control_unit1 : control_unit port map(
clk => clk,
c => c_out_i,
z => z_out_i,
int => i_comb_i,
rst => rst,
opcode_hi_5 => instruction_i(17 downto 13),
opcode_lo_2 => instruction_i(1 downto 0),
reset => cu_reset_i,
pc_ld => pc_ld_i,
pc_oe => pc_oe_i,
pc_mux_sel => pc_mux_sel_i,
sp_ld => sp_ld_i,
inc_dec => inc_dec_i,
rf_wr => rf_wr_i,
rf_oe => rf_oe_i,
rf_wr_sel => rf_wr_sel_i,
scr_wr => scr_wr_i,
scr_oe => scr_oe_i,
scr_addr_sel => scr_addr_sel_i,
alu_mux_sel => alu_mux_sel_i,
alu_sel => alu_sel_i,
c_flag_restore => c_restore_i,
c_flag_save => c_save_i,
c_flag_ld => c_ld_i,
c_flag_set => c_set_i,
c_flag_clr => c_clr_i,
z_flag_restore => z_restore_i,
z_flag_save => z_save_i,
z_flag_ld => z_ld_i,
z_flag_set => z_set_i,
z_flag_clr => z_clr_i,
i_flag_set => i_set_i,
i_flag_clr => i_clr_i,
io_oe => io_oe);
end rat_cpu_a;
|
--
-- Cronômetro em VHDL
--
-- Criado por <NAME> e <NAME>
--
library IEEE;
use IEEE.std_logic_1164.all;
entity chronometer is port
(
un_cen : out std_logic_vector(6 downto 0);
ten_cen : out std_logic_vector(6 downto 0);
un_sec : out std_logic_vector(6 downto 0);
ten_sec : out std_logic_vector(6 downto 0);
enable : in bit;
reset : in bit;
clk_50MHz : in bit
);
end chronometer;
architecture arch of chronometer is
signal clk : bit;
signal en : bit := '0';
begin
pause: process(enable)
begin
if(enable = '1') then
en <= not en;
end if;
end process pause;
divisor: process(clk_50MHz)
variable k : integer range 0 to 500000;
begin
if(en = '1') then
if(clk_50MHz = '1' and clk_50MHz'event) then
if(k > 250000) then
clk <= '1';
k := k + 1;
if(k = 500000) then
k := 0;
end if;
else
k := k + 1;
clk <= '0';
end if;
end if;
end if;
end process divisor;
counter: process(clk)
variable count : integer range 0 to 10;
variable count2 : integer range 0 to 10;
variable count3 : integer range 0 to 10;
variable count4 : integer range 0 to 6;
begin
if(reset = '0') then
count := 0;
count2 := 0;
count3 := 0;
count4 := 0;
else if(clk = '1' and clk'event) then
count := count + 1;
if(count = 10) then
count := 0;
count2 := count2 + 1;
if(count2 = 10) then
count2 := 0;
count3 := count3 + 1;
if(count3 = 10) then
count3 := 0;
count4 := count4 + 1;
if(count4 = 6) then
count4 := 0;
end if;
end if;
end if;
end if;
end if;
end if;
case count is
when 0 => un_cen <= "0000001";
when 1 => un_cen <= "1001111";
when 2 => un_cen <= "0010010";
when 3 => un_cen <= "0000110";
when 4 => un_cen <= "1001100";
when 5 => un_cen <= "0100100";
when 6 => un_cen <= "0100000";
when 7 => un_cen <= "0001111";
when 8 => un_cen <= "0000000";
when 9 => un_cen <= "0000100";
when others => un_cen <= "1111111";
end case;
case count2 is
when 0 => ten_cen <= "0000001";
when 1 => ten_cen <= "1001111";
when 2 => ten_cen <= "0010010";
when 3 => ten_cen <= "0000110";
when 4 => ten_cen <= "1001100";
when 5 => ten_cen <= "0100100";
when 6 => ten_cen <= "0100000";
when 7 => ten_cen <= "0001111";
when 8 => ten_cen <= "0000000";
when 9 => ten_cen <= "0000100";
when others => ten_cen <= "1111111";
end case;
case count3 is
when 0 => un_sec <= "0000001";
when 1 => un_sec <= "1001111";
when 2 => un_sec <= "0010010";
when 3 => un_sec <= "0000110";
when 4 => un_sec <= "1001100";
when 5 => un_sec <= "0100100";
when 6 => un_sec <= "0100000";
when 7 => un_sec <= "0001111";
when 8 => un_sec <= "0000000";
when 9 => un_sec <= "0000100";
when others => un_sec <= "1111111";
end case;
case count4 is
when 0 => ten_sec <= "0000001";
when 1 => ten_sec <= "1001111";
when 2 => ten_sec <= "0010010";
when 3 => ten_sec <= "0000110";
when 4 => ten_sec <= "1001100";
when 5 => ten_sec <= "0100100";
when 6 => ten_sec <= "0100000";
when others => ten_sec <= "1111111";
end case;
end process counter;
end arch;
|
<filename>extras/FPGA/SWV/SWO_tb.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:36:32 01/26/2012
-- Design Name:
-- Module Name: C:/work/HW/fpga/xilinx/ARM_Cores/SWV/SWO_tb.vhd
-- Project Name: SWV
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SWO
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY SWO_tb IS
END SWO_tb;
ARCHITECTURE behavior OF SWO_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SWO
PORT(
CODR : IN std_logic_vector(12 downto 0);
SPPR : IN std_logic_vector(1 downto 0);
TRACECLKIN : IN std_logic;
TRESETn : IN std_logic;
TRACESWO : OUT std_logic;
-- ATCLK : IN std_logic;
-- ATCLKEN : IN std_logic;
-- ATRESETn : IN std_logic;
ATDATA : IN std_logic_vector(7 downto 0);
-- ATID : IN std_logic_vector(6 downto 0);
ATVALID : IN std_logic;
ATREADY : OUT std_logic--;
-- AFVALID : OUT std_logic;
-- AFREADY : IN std_logic
);
END COMPONENT;
--Inputs
signal CODR : std_logic_vector(12 downto 0) := "0000000000000";
signal SPPR : std_logic_vector(1 downto 0) := "10";
signal TRACECLKIN : std_logic := '1';
signal TRESETn : std_logic := '1';
-- signal ATCLK : std_logic := '0';
-- signal ATCLKEN : std_logic := '0';
-- signal ATRESETn : std_logic := '0';
signal ATDATA : std_logic_vector(7 downto 0) := (others => '0');
-- signal ATID : std_logic_vector(6 downto 0) := (others => '0');
signal ATVALID : std_logic := '0';
-- signal AFREADY : std_logic := '0';
--Outputs
signal TRACESWO : std_logic;
signal ATREADY : std_logic;
-- signal AFVALID : std_logic;
-- Clock period definitions
constant TRACECLKIN_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SWO PORT MAP (
CODR => CODR,
SPPR => SPPR,
TRACECLKIN => TRACECLKIN,
TRESETn => TRESETn,
TRACESWO => TRACESWO,
-- ATCLK => ATCLK,
-- ATCLKEN => ATCLKEN,
-- ATRESETn => ATRESETn,
ATDATA => ATDATA,
-- ATID => ATID,
ATVALID => ATVALID,
ATREADY => ATREADY--,
-- AFVALID => AFVALID,
-- AFREADY => AFREADY
);
-- Clock process definitions
ATCLK_process :process
begin
TRACECLKIN <= '1';
wait for TRACECLKIN_period/2;
TRACECLKIN <= '0';
wait for TRACECLKIN_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ms.
TRESETn <= '1';
wait for TRACECLKIN_period * 10;
TRESETn <= '0';
loop
wait for TRACECLKIN_period;
if(ATREADY = '1') then
ATDATA <= ATDATA + '1';
ATVALID <= '1';
else
ATVALID <= '0';
end if;
end loop;
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: <NAME> A01203712
--
-- Create Date: 09:10:21 09/04/2015
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: 14.7
-- Description: Implementation of a Arithmetic Logic Unit
-- Pedroni's book page 76
-- Dependencies: Nope
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments: Divide and conquer using KISS principle
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;
entity ALU is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Behavioral of ALU is
--embbeded signals
-- Result from Logic Unit
signal res_LU : STD_LOGIC_VECTOR (7 downto 0);
-- Result from Arithmetic Unit
signal res_AU : STD_LOGIC_VECTOR (7 downto 0);
begin
ArithmeticUnit: process(a, b, cin, sel)
VARIABLE bufer: STD_LOGIC_VECTOR (2 downto 0);
begin
bufer := sel(0) & sel(1) & sel(2);
case bufer is
when "000" =>
res_AU <= a;
when "001" =>
res_AU <= a + x"01";
when "010" =>
res_AU <= a - x"01";
when "011" =>
res_AU <= b;
when "100" =>
res_AU <= b + x"01";
when "101" =>
res_AU <= b - x"01";
when "110" =>
res_AU <= a + b;
when others =>
res_AU <= a + b + cin;
end case;
end process ArithmeticUnit;
LogicUnit: process(a, b, sel)
VARIABLE bufer: STD_LOGIC_VECTOR (2 downto 0);
begin
bufer := sel(0) & sel(1) & sel(2);
case bufer is
when "000" =>
res_LU <= not a;
when "001" =>
res_LU <= not b;
when "010" =>
res_LU <= a and b;
when "011" =>
res_LU <= a or b;
when "100" =>
res_LU <= a nand b;
when "101" =>
res_LU <= a nor b;
when "110" =>
res_LU <= a xor b;
when others =>
res_LU <= a xnor b;
end case;
end process LogicUnit;
-- Multiplexor
y <= res_AU when sel(3) = '0' else
res_LU;
end Behavioral;
|
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; <NAME>
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by <NAME> 15 Jun 94
--| 2. Removed all std_ulogic_vector support, <NAME>, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, <NAME>, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by <NAME>, <EMAIL>. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
|
-- XGEN: Autogenerated File
library IEEE;
library work;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.HDPython_core.all;
use work.axisStream_slv32.all;
use work.klm_globals_pack.all;
use work.register_t_pack.all;
use work.v_symbol_pack.all;
entity InputDelay_print is
port(
ConfigIn_s2m : out axiStream_slv32_s2m := axiStream_slv32_s2m_ctr;
ConfigIn_m2s : in axiStream_slv32_m2s := axiStream_slv32_m2s_ctr;
globals : in klm_globals := klm_globals_ctr;
globals_clk : in std_logic := std_logic_ctr(0, 1)
);
end entity;
architecture rtl of InputDelay_print is
--------------------------InputDelay_print-----------------
signal counter : integer := integer_ctr(0, 32);
signal d : slv32 := std_logic_vector_ctr(0, 32);
-------------------------- end InputDelay_print-----------------
begin
-- begin architecture
-----------------------------------
proc : process(globals_clk, ConfigIn_m2s) is
variable ax_slave : axiStream_slv32_slave := axiStream_slv32_slave_ctr;
begin
pull( self => ax_slave, rx => ConfigIn_m2s);
if rising_edge(globals_clk) then
enter_rising_edge(self => ax_slave);
counter <= counter + 1;
if (isReceivingData_0(self => ax_slave)) then
get_value_01_rshift(self => ax_slave, rhs => d);
end if;
if (counter > 15) then
counter <= 0;
end if;
exit_rising_edge(self => ax_slave);
end if;
push( self => ax_slave, rx => ConfigIn_s2m);
end process;
-- end architecture
end architecture;
|
<reponame>VanderSant/PCS3115_Sistemas-Digitais-I
------------------------------------------------------
--! @file mux_2to1.vhdl
--! @brief
--! @author <NAME> (<EMAIL>)
--! @date 06/2020
-------------------------------------------------------
entity mux_2to1 is
port
(
SEL : in bit;
A : in bit;
B : in bit;
Y : out bit
);
end entity;
architecture with_select of mux_2to1 is
begin
with SEL select
Y <= A when '0',
B when '1',
'0' when others;
end architecture;
|
<gh_stars>1-10
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2020.1
-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity absorb_block is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
output_r_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
output_r_ce0 : OUT STD_LOGIC;
output_r_we0 : OUT STD_LOGIC;
output_r_d0 : OUT STD_LOGIC_VECTOR (15 downto 0);
input_r_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
input_r_ce0 : OUT STD_LOGIC;
input_r_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
input_r_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
input_r_ce1 : OUT STD_LOGIC;
input_r_q1 : IN STD_LOGIC_VECTOR (15 downto 0);
outlen : IN STD_LOGIC_VECTOR (5 downto 0);
inlen : IN STD_LOGIC_VECTOR (7 downto 0);
reset : IN STD_LOGIC_VECTOR (0 downto 0);
start_word : IN STD_LOGIC_VECTOR (7 downto 0);
begin_r : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (7 downto 0) );
end;
architecture behav of absorb_block is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (13 downto 0) := "00000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (13 downto 0) := "00000000010000";
constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000100000";
constant ap_ST_fsm_pp1_stage1 : STD_LOGIC_VECTOR (13 downto 0) := "00000001000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (13 downto 0) := "00000010000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (13 downto 0) := "00000100000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (13 downto 0) := "00001000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (13 downto 0) := "00010000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (13 downto 0) := "00100000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (13 downto 0) := "01000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (13 downto 0) := "10000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110";
constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101";
constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_6 : STD_LOGIC_VECTOR (2 downto 0) := "110";
constant ap_const_lv3_7 : STD_LOGIC_VECTOR (2 downto 0) := "111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv16_15 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000010101";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv11_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_const_lv11_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000000011";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
signal ap_CS_fsm : STD_LOGIC_VECTOR (13 downto 0) := "00000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal p_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_20 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_21 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_22 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_23 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal p_24 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal i_1_reg_376 : STD_LOGIC_VECTOR (7 downto 0);
signal p_1_rec_reg_387 : STD_LOGIC_VECTOR (63 downto 0);
signal begin_read_read_fu_236_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal reset_read_read_fu_248_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal inlen_cast_fu_642_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal inlen_cast_reg_1428 : STD_LOGIC_VECTOR (15 downto 0);
signal i_fu_652_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal icmp_ln766_fu_808_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln766_reg_1441 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal sum_fu_831_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal sum_reg_1449 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal icmp_ln742_fu_813_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal end_fu_849_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal end_reg_1455 : STD_LOGIC_VECTOR (4 downto 0);
signal zext_ln742_fu_857_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln742_reg_1463 : STD_LOGIC_VECTOR (7 downto 0);
signal trunc_ln6_reg_1468 : STD_LOGIC_VECTOR (2 downto 0);
signal trunc_ln742_fu_900_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal trunc_ln742_reg_1473 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal zext_ln747_fu_904_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln747_reg_1481 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln752_cast_fu_907_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln752_cast_reg_1486 : STD_LOGIC_VECTOR (7 downto 0);
signal add_ln752_fu_954_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal add_ln752_reg_1491 : STD_LOGIC_VECTOR (63 downto 0);
signal icmp_ln752_fu_960_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln752_reg_1496 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
signal ap_block_state6_pp1_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp1_stage0_iter1 : BOOLEAN;
signal ap_block_pp1_stage0_11001 : BOOLEAN;
signal empty_41_fu_965_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal empty_41_reg_1500 : STD_LOGIC_VECTOR (10 downto 0);
signal trunc_ln760_fu_995_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal trunc_ln760_reg_1516 : STD_LOGIC_VECTOR (4 downto 0);
signal empty_42_fu_999_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal empty_42_reg_1520 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp1_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage1 : signal is "none";
signal ap_block_state7_pp1_stage1_iter0 : BOOLEAN;
signal ap_block_pp1_stage1_11001 : BOOLEAN;
signal grp_fu_577_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal input_load_1_reg_1525 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
signal empty_43_fu_1003_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal empty_43_reg_1530 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_587_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal input_load_9_1_reg_1535 : STD_LOGIC_VECTOR (7 downto 0);
signal add_ln761_fu_1097_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal add_ln761_reg_1675 : STD_LOGIC_VECTOR (63 downto 0);
signal i_16_fu_1103_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_16_reg_1680 : STD_LOGIC_VECTOR (7 downto 0);
signal icmp_ln764_fu_1289_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln764_reg_1685 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal or_ln766_fu_1310_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_ln766_reg_1690 : STD_LOGIC_VECTOR (0 downto 0);
signal sub_ln772_fu_1316_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal grp_KeccakF1600_StatePer_fu_519_ap_ready : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_ap_done : STD_LOGIC;
signal ap_predicate_op285_call_state10 : BOOLEAN;
signal ap_block_state10_on_subcall_done : BOOLEAN;
signal ret_end_1_fu_1320_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal i_17_fu_1331_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_17_reg_1707 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal shl_ln_fu_1337_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal shl_ln_reg_1712 : STD_LOGIC_VECTOR (4 downto 0);
signal icmp_ln787_fu_1326_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal j_fu_1351_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal r_4_fu_1404_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal icmp_ln790_fu_1345_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp1_stage0_subdone : BOOLEAN;
signal ap_condition_pp1_exit_iter0_state6 : STD_LOGIC;
signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
signal ap_block_pp1_stage1_subdone : BOOLEAN;
signal grp_KeccakF1600_StatePer_fu_519_ap_start : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_ap_idle : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_0_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_0_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_5_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_5_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_10_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_10_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_15_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_15_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_20_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_20_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_1_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_1_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_6_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_6_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_11_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_11_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_16_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_16_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_21_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_21_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_2_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_2_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_7_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_7_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_12_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_12_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_17_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_17_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_22_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_22_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_3_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_3_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_8_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_8_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_13_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_13_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_18_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_18_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_23_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_23_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_4_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_4_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_9_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_9_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_14_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_14_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_19_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_19_o_ap_vld : STD_LOGIC;
signal grp_KeccakF1600_StatePer_fu_519_p_24_o : STD_LOGIC_VECTOR (63 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_p_24_o_ap_vld : STD_LOGIC;
signal ap_phi_mux_i_0_phi_fu_324_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_0_reg_320 : STD_LOGIC_VECTOR (4 downto 0);
signal icmp_ln734_fu_646_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_15_reg_331 : STD_LOGIC_VECTOR (7 downto 0);
signal p_02_reg_343 : STD_LOGIC_VECTOR (15 downto 0);
signal ret_end_0_reg_353 : STD_LOGIC_VECTOR (4 downto 0);
signal p_01_idx_reg_364 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_phi_mux_i_1_phi_fu_379_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp1_stage0 : BOOLEAN;
signal ap_phi_mux_p_1_rec_phi_fu_391_p4 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_phi_reg_pp1_iter0_UnifiedRetVal_i_reg_399 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_phi_mux_i_2_phi_fu_458_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal i_2_reg_454 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal ap_phi_mux_r_1_phi_fu_468_p18 : STD_LOGIC_VECTOR (63 downto 0);
signal j_0_reg_489 : STD_LOGIC_VECTOR (2 downto 0);
signal r_2_reg_500 : STD_LOGIC_VECTOR (63 downto 0);
signal p_0_reg_510 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_KeccakF1600_StatePer_fu_519_ap_start_reg : STD_LOGIC := '0';
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal p_01_idx22_cast_fu_974_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal zext_ln757_fu_990_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal zext_ln758_fu_1017_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp1_stage1 : BOOLEAN;
signal zext_ln759_fu_1032_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal zext_ln792_1_fu_1389_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal xor_ln760_fu_1133_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Result_s_fu_875_p4 : STD_LOGIC_VECTOR (63 downto 0);
signal zext_ln746_fu_819_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln746_fu_823_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal trunc_ln746_1_fu_827_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal icmp_ln747_fu_843_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal add_ln746_1_fu_837_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_14_fu_861_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal xor_ln784_fu_869_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal empty_40_fu_914_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal umax12_fu_920_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal umax12_cast_fu_928_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_cast55_fu_910_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal sub_ln752_fu_932_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_13_fu_938_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal sext_ln752_fu_946_p1 : STD_LOGIC_VECTOR (33 downto 0);
signal zext_ln752_fu_950_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_01_idx22_fu_969_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal or_ln757_fu_979_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal add_ln757_fu_985_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal or_ln758_fu_1007_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal add_ln758_fu_1012_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal or_ln759_fu_1022_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal add_ln759_fu_1027_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal empty_45_fu_1113_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal empty_44_fu_1109_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_7_fu_1117_p9 : STD_LOGIC_VECTOR (63 downto 0);
signal icmp_ln766_2_fu_1299_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln766_1_fu_1294_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal and_ln766_fu_1305_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal trunc_ln792_fu_1367_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal trunc_ln8_fu_1357_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln792_fu_1380_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal add_ln792_fu_1384_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal r_3_fu_1394_p4 : STD_LOGIC_VECTOR (47 downto 0);
signal ap_return_preg : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (13 downto 0);
signal ap_idle_pp1 : STD_LOGIC;
signal ap_enable_pp1 : STD_LOGIC;
signal ap_condition_379 : BOOLEAN;
signal ap_condition_193 : BOOLEAN;
component KeccakF1600_StatePer IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_0_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_0_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_0_o_ap_vld : OUT STD_LOGIC;
p_5_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_5_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_5_o_ap_vld : OUT STD_LOGIC;
p_10_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_10_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_10_o_ap_vld : OUT STD_LOGIC;
p_15_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_15_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_15_o_ap_vld : OUT STD_LOGIC;
p_20_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_20_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_20_o_ap_vld : OUT STD_LOGIC;
p_1_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_1_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_1_o_ap_vld : OUT STD_LOGIC;
p_6_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_6_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_6_o_ap_vld : OUT STD_LOGIC;
p_11_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_11_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_11_o_ap_vld : OUT STD_LOGIC;
p_16_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_16_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_16_o_ap_vld : OUT STD_LOGIC;
p_21_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_21_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_21_o_ap_vld : OUT STD_LOGIC;
p_2_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_2_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_2_o_ap_vld : OUT STD_LOGIC;
p_7_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_7_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_7_o_ap_vld : OUT STD_LOGIC;
p_12_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_12_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_12_o_ap_vld : OUT STD_LOGIC;
p_17_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_17_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_17_o_ap_vld : OUT STD_LOGIC;
p_22_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_22_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_22_o_ap_vld : OUT STD_LOGIC;
p_3_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_3_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_3_o_ap_vld : OUT STD_LOGIC;
p_8_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_8_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_8_o_ap_vld : OUT STD_LOGIC;
p_13_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_13_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_13_o_ap_vld : OUT STD_LOGIC;
p_18_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_18_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_18_o_ap_vld : OUT STD_LOGIC;
p_23_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_23_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_23_o_ap_vld : OUT STD_LOGIC;
p_4_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_4_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_4_o_ap_vld : OUT STD_LOGIC;
p_9_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_9_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_9_o_ap_vld : OUT STD_LOGIC;
p_14_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_14_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_14_o_ap_vld : OUT STD_LOGIC;
p_19_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_19_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_19_o_ap_vld : OUT STD_LOGIC;
p_24_i : IN STD_LOGIC_VECTOR (63 downto 0);
p_24_o : OUT STD_LOGIC_VECTOR (63 downto 0);
p_24_o_ap_vld : OUT STD_LOGIC );
end component;
begin
grp_KeccakF1600_StatePer_fu_519 : component KeccakF1600_StatePer
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_KeccakF1600_StatePer_fu_519_ap_start,
ap_done => grp_KeccakF1600_StatePer_fu_519_ap_done,
ap_idle => grp_KeccakF1600_StatePer_fu_519_ap_idle,
ap_ready => grp_KeccakF1600_StatePer_fu_519_ap_ready,
p_0_i => p_0,
p_0_o => grp_KeccakF1600_StatePer_fu_519_p_0_o,
p_0_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_0_o_ap_vld,
p_5_i => p_5,
p_5_o => grp_KeccakF1600_StatePer_fu_519_p_5_o,
p_5_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_5_o_ap_vld,
p_10_i => p_10,
p_10_o => grp_KeccakF1600_StatePer_fu_519_p_10_o,
p_10_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_10_o_ap_vld,
p_15_i => p_15,
p_15_o => grp_KeccakF1600_StatePer_fu_519_p_15_o,
p_15_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_15_o_ap_vld,
p_20_i => p_20,
p_20_o => grp_KeccakF1600_StatePer_fu_519_p_20_o,
p_20_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_20_o_ap_vld,
p_1_i => p_1,
p_1_o => grp_KeccakF1600_StatePer_fu_519_p_1_o,
p_1_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_1_o_ap_vld,
p_6_i => p_6,
p_6_o => grp_KeccakF1600_StatePer_fu_519_p_6_o,
p_6_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_6_o_ap_vld,
p_11_i => p_11,
p_11_o => grp_KeccakF1600_StatePer_fu_519_p_11_o,
p_11_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_11_o_ap_vld,
p_16_i => p_16,
p_16_o => grp_KeccakF1600_StatePer_fu_519_p_16_o,
p_16_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_16_o_ap_vld,
p_21_i => p_21,
p_21_o => grp_KeccakF1600_StatePer_fu_519_p_21_o,
p_21_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_21_o_ap_vld,
p_2_i => p_2,
p_2_o => grp_KeccakF1600_StatePer_fu_519_p_2_o,
p_2_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_2_o_ap_vld,
p_7_i => p_7,
p_7_o => grp_KeccakF1600_StatePer_fu_519_p_7_o,
p_7_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_7_o_ap_vld,
p_12_i => p_12,
p_12_o => grp_KeccakF1600_StatePer_fu_519_p_12_o,
p_12_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_12_o_ap_vld,
p_17_i => p_17,
p_17_o => grp_KeccakF1600_StatePer_fu_519_p_17_o,
p_17_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_17_o_ap_vld,
p_22_i => p_22,
p_22_o => grp_KeccakF1600_StatePer_fu_519_p_22_o,
p_22_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_22_o_ap_vld,
p_3_i => p_3,
p_3_o => grp_KeccakF1600_StatePer_fu_519_p_3_o,
p_3_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_3_o_ap_vld,
p_8_i => p_8,
p_8_o => grp_KeccakF1600_StatePer_fu_519_p_8_o,
p_8_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_8_o_ap_vld,
p_13_i => p_13,
p_13_o => grp_KeccakF1600_StatePer_fu_519_p_13_o,
p_13_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_13_o_ap_vld,
p_18_i => p_18,
p_18_o => grp_KeccakF1600_StatePer_fu_519_p_18_o,
p_18_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_18_o_ap_vld,
p_23_i => p_23,
p_23_o => grp_KeccakF1600_StatePer_fu_519_p_23_o,
p_23_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_23_o_ap_vld,
p_4_i => p_4,
p_4_o => grp_KeccakF1600_StatePer_fu_519_p_4_o,
p_4_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_4_o_ap_vld,
p_9_i => p_9,
p_9_o => grp_KeccakF1600_StatePer_fu_519_p_9_o,
p_9_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_9_o_ap_vld,
p_14_i => p_14,
p_14_o => grp_KeccakF1600_StatePer_fu_519_p_14_o,
p_14_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_14_o_ap_vld,
p_19_i => p_19,
p_19_o => grp_KeccakF1600_StatePer_fu_519_p_19_o,
p_19_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_19_o_ap_vld,
p_24_i => p_24,
p_24_o => grp_KeccakF1600_StatePer_fu_519_p_24_o,
p_24_o_ap_vld => grp_KeccakF1600_StatePer_fu_519_p_24_o_ap_vld);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state6) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
else
if ((((ap_const_boolean_0 = ap_block_pp1_stage1_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage1)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv8_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
ap_return_preg <= p_0_reg_510;
end if;
end if;
end if;
end process;
grp_KeccakF1600_StatePer_fu_519_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_KeccakF1600_StatePer_fu_519_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state11) or ((ap_const_logic_1 = ap_CS_fsm_state9) and (or_ln766_fu_1310_p2 = ap_const_lv1_1) and (icmp_ln764_fu_1289_p2 = ap_const_lv1_1)))) then
grp_KeccakF1600_StatePer_fu_519_ap_start_reg <= ap_const_logic_1;
elsif ((grp_KeccakF1600_StatePer_fu_519_ap_ready = ap_const_logic_1)) then
grp_KeccakF1600_StatePer_fu_519_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_193)) then
if ((ap_const_boolean_1 = ap_condition_379)) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_24;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_17) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_23;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_16) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_22;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_15) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_21;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_14) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_20;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_13) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_19;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_12) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_18;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_11) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_17;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_10) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_16;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_F) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_15;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_E) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_14;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_D) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_13;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_C) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_12;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_B) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_11;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_A) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_10;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_9) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_9;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_8) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_8;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_7) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_7;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_6) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_6;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_5) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_5;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_4) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_4;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_3) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_3;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_2) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_2;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_1) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_1;
elsif (((trunc_ln760_reg_1516 = ap_const_lv5_0) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= p_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399 <= ap_phi_reg_pp1_iter0_UnifiedRetVal_i_reg_399;
end if;
end if;
end if;
end process;
i_0_reg_320_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((reset_read_read_fu_248_p2 = ap_const_lv1_1) and (begin_read_read_fu_236_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_0_reg_320 <= ap_const_lv5_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
i_0_reg_320 <= i_fu_652_p2;
end if;
end if;
end process;
i_15_reg_331_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_state10_on_subcall_done) and (ap_const_logic_1 = ap_CS_fsm_state10))) then
i_15_reg_331 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_15_reg_331 <= start_word;
end if;
end if;
end process;
i_1_reg_376_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
i_1_reg_376 <= i_16_reg_1680;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
i_1_reg_376 <= i_15_reg_331;
end if;
end if;
end process;
i_2_reg_454_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (icmp_ln790_fu_1345_p2 = ap_const_lv1_1))) then
i_2_reg_454 <= i_17_reg_1707;
elsif (((grp_KeccakF1600_StatePer_fu_519_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
i_2_reg_454 <= ap_const_lv3_0;
end if;
end if;
end process;
j_0_reg_489_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (icmp_ln790_fu_1345_p2 = ap_const_lv1_0))) then
j_0_reg_489 <= j_fu_1351_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
j_0_reg_489 <= ap_const_lv3_0;
end if;
end if;
end process;
p_0_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_0 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_0) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_0 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_0_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_0_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_0 <= grp_KeccakF1600_StatePer_fu_519_p_0_o;
end if;
end if;
end process;
p_01_idx_reg_364_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_state10_on_subcall_done) and (ap_const_logic_1 = ap_CS_fsm_state10))) then
p_01_idx_reg_364 <= add_ln752_reg_1491;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
p_01_idx_reg_364 <= ap_const_lv64_0;
end if;
end if;
end process;
p_02_reg_343_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_state10_on_subcall_done) and (ap_const_logic_1 = ap_CS_fsm_state10))) then
p_02_reg_343 <= sub_ln772_fu_1316_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
p_02_reg_343 <= inlen_cast_reg_1428;
end if;
end if;
end process;
p_0_reg_510_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((begin_read_read_fu_236_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
p_0_reg_510 <= start_word;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and ((icmp_ln787_fu_1326_p2 = ap_const_lv1_1) or (icmp_ln766_reg_1441 = ap_const_lv1_1)))) then
p_0_reg_510 <= zext_ln742_reg_1463;
end if;
end if;
end process;
p_1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_1 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_1) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_1 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_1_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_1_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_1 <= grp_KeccakF1600_StatePer_fu_519_p_1_o;
end if;
end if;
end process;
p_10_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_10 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_A) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_10 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_10_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_10_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_10 <= grp_KeccakF1600_StatePer_fu_519_p_10_o;
end if;
end if;
end process;
p_11_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_11 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_B) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_11 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_11_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_11_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_11 <= grp_KeccakF1600_StatePer_fu_519_p_11_o;
end if;
end if;
end process;
p_12_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_12 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_C) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_12 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_12_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_12_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_12 <= grp_KeccakF1600_StatePer_fu_519_p_12_o;
end if;
end if;
end process;
p_13_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_13 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_D) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_13 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_13_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_13_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_13 <= grp_KeccakF1600_StatePer_fu_519_p_13_o;
end if;
end if;
end process;
p_14_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_14 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_E) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_14 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_14_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_14_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_14 <= grp_KeccakF1600_StatePer_fu_519_p_14_o;
end if;
end if;
end process;
p_15_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_15 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_F) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_15 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_15_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_15_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_15 <= grp_KeccakF1600_StatePer_fu_519_p_15_o;
end if;
end if;
end process;
p_16_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_10) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_16 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_10) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_16 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_16_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_16_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_16 <= grp_KeccakF1600_StatePer_fu_519_p_16_o;
end if;
end if;
end process;
p_17_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_11) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_17 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_11) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_17 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_17_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_17_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_17 <= grp_KeccakF1600_StatePer_fu_519_p_17_o;
end if;
end if;
end process;
p_18_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_12) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_18 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_12) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_18 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_18_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_18_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_18 <= grp_KeccakF1600_StatePer_fu_519_p_18_o;
end if;
end if;
end process;
p_19_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_13) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_19 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_13) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_19 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_19_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_19_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_19 <= grp_KeccakF1600_StatePer_fu_519_p_19_o;
end if;
end if;
end process;
p_1_rec_reg_387_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
p_1_rec_reg_387 <= add_ln761_reg_1675;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
p_1_rec_reg_387 <= ap_const_lv64_0;
end if;
end if;
end process;
p_2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_2) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_2 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_2) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_2 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_2_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_2_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_2 <= grp_KeccakF1600_StatePer_fu_519_p_2_o;
end if;
end if;
end process;
p_20_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_14) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_20 <= xor_ln760_fu_1133_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (icmp_ln742_fu_813_p2 = ap_const_lv1_1) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
p_20 <= p_Result_s_fu_875_p4;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_14) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_20 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_20_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_20_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_20 <= grp_KeccakF1600_StatePer_fu_519_p_20_o;
end if;
end if;
end process;
p_21_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_15) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_21 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_15) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_21 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_21_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_21_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_21 <= grp_KeccakF1600_StatePer_fu_519_p_21_o;
end if;
end if;
end process;
p_22_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_16) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_22 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_16) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_22 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_22_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_22_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_22 <= grp_KeccakF1600_StatePer_fu_519_p_22_o;
end if;
end if;
end process;
p_23_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_17) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_23 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_17) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_23 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_23_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_23_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_23 <= grp_KeccakF1600_StatePer_fu_519_p_23_o;
end if;
end if;
end process;
p_24_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and ((trunc_ln760_reg_1516 = ap_const_lv5_18) or ((trunc_ln760_reg_1516 = ap_const_lv5_19) or ((trunc_ln760_reg_1516 = ap_const_lv5_1A) or ((trunc_ln760_reg_1516 = ap_const_lv5_1B) or ((trunc_ln760_reg_1516 = ap_const_lv5_1C) or ((trunc_ln760_reg_1516 = ap_const_lv5_1D) or ((trunc_ln760_reg_1516 = ap_const_lv5_1E) or (trunc_ln760_reg_1516 = ap_const_lv5_1F)))))))))) then
p_24 <= xor_ln760_fu_1133_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (((((((((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_1E) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0)) or ((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_1F) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) or ((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_1D) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) or ((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_1C) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) or ((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_1B) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) or ((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_1A) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) or ((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_19) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) or ((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_18) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))))) then
p_24 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_24_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_24_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_24 <= grp_KeccakF1600_StatePer_fu_519_p_24_o;
end if;
end if;
end process;
p_3_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_3) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_3 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_3) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_3 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_3_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_3_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_3 <= grp_KeccakF1600_StatePer_fu_519_p_3_o;
end if;
end if;
end process;
p_4_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_4) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_4 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_4) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_4 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_4_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_4_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_4 <= grp_KeccakF1600_StatePer_fu_519_p_4_o;
end if;
end if;
end process;
p_5_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_5) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_5 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_5) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_5 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_5_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_5_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_5 <= grp_KeccakF1600_StatePer_fu_519_p_5_o;
end if;
end if;
end process;
p_6_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_6) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_6 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_6) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_6 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_6_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_6_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_6 <= grp_KeccakF1600_StatePer_fu_519_p_6_o;
end if;
end if;
end process;
p_7_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_7) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_7 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_7) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_7 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_7_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_7_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_7 <= grp_KeccakF1600_StatePer_fu_519_p_7_o;
end if;
end if;
end process;
p_8_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_8) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_8 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_8) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_8 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_8_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_8_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_8 <= grp_KeccakF1600_StatePer_fu_519_p_8_o;
end if;
end if;
end process;
p_9_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (trunc_ln760_reg_1516 = ap_const_lv5_9) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
p_9 <= xor_ln760_fu_1133_p2;
elsif (((ap_phi_mux_i_0_phi_fu_324_p4 = ap_const_lv5_9) and (ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
p_9 <= ap_const_lv64_0;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state12) and (grp_KeccakF1600_StatePer_fu_519_p_9_o_ap_vld = ap_const_logic_1)) or ((ap_predicate_op285_call_state10 = ap_const_boolean_1) and (grp_KeccakF1600_StatePer_fu_519_p_9_o_ap_vld = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state10)))) then
p_9 <= grp_KeccakF1600_StatePer_fu_519_p_9_o;
end if;
end if;
end process;
r_2_reg_500_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (icmp_ln790_fu_1345_p2 = ap_const_lv1_0))) then
r_2_reg_500 <= r_4_fu_1404_p1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
r_2_reg_500 <= ap_phi_mux_r_1_phi_fu_468_p18;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
add_ln752_reg_1491 <= add_ln752_fu_954_p2;
trunc_ln742_reg_1473 <= trunc_ln742_fu_900_p1;
zext_ln747_reg_1481(4 downto 0) <= zext_ln747_fu_904_p1(4 downto 0);
zext_ln752_cast_reg_1486(4 downto 0) <= zext_ln752_cast_fu_907_p1(4 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage1) and (ap_const_boolean_0 = ap_block_pp1_stage1_11001) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
add_ln761_reg_1675 <= add_ln761_fu_1097_p2;
i_16_reg_1680 <= i_16_fu_1103_p2;
input_load_1_reg_1525 <= input_r_q0(15 downto 8);
input_load_9_1_reg_1535 <= input_r_q1(15 downto 8);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln752_fu_960_p2 = ap_const_lv1_1))) then
empty_41_reg_1500 <= empty_41_fu_965_p1;
trunc_ln760_reg_1516 <= trunc_ln760_fu_995_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage1) and (ap_const_boolean_0 = ap_block_pp1_stage1_11001) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
empty_42_reg_1520 <= empty_42_fu_999_p1;
empty_43_reg_1530 <= empty_43_fu_1003_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (icmp_ln742_fu_813_p2 = ap_const_lv1_0))) then
end_reg_1455 <= end_fu_849_p3;
sum_reg_1449 <= sum_fu_831_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
i_17_reg_1707 <= i_17_fu_1331_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
icmp_ln752_reg_1496 <= icmp_ln752_fu_960_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
icmp_ln764_reg_1685 <= icmp_ln764_fu_1289_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
icmp_ln766_reg_1441 <= icmp_ln766_fu_808_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
inlen_cast_reg_1428(7 downto 0) <= inlen_cast_fu_642_p1(7 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (icmp_ln764_fu_1289_p2 = ap_const_lv1_1))) then
or_ln766_reg_1690 <= or_ln766_fu_1310_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_state10_on_subcall_done) and (ap_const_logic_1 = ap_CS_fsm_state10))) then
ret_end_0_reg_353 <= ret_end_1_fu_1320_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
shl_ln_reg_1712(4 downto 2) <= shl_ln_fu_1337_p3(4 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (icmp_ln742_fu_813_p2 = ap_const_lv1_1) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
trunc_ln6_reg_1468 <= outlen(5 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (icmp_ln742_fu_813_p2 = ap_const_lv1_1))) then
zext_ln742_reg_1463(4 downto 0) <= zext_ln742_fu_857_p1(4 downto 0);
end if;
end if;
end process;
inlen_cast_reg_1428(15 downto 8) <= "00000000";
zext_ln742_reg_1463(7 downto 5) <= "000";
zext_ln747_reg_1481(15 downto 5) <= "00000000000";
zext_ln752_cast_reg_1486(7 downto 5) <= "000";
shl_ln_reg_1712(1 downto 0) <= "00";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, begin_read_read_fu_236_p2, reset_read_read_fu_248_p2, ap_CS_fsm_state2, icmp_ln766_reg_1441, ap_CS_fsm_state4, icmp_ln742_fu_813_p2, icmp_ln752_fu_960_p2, ap_enable_reg_pp1_iter0, ap_CS_fsm_state10, grp_KeccakF1600_StatePer_fu_519_ap_done, ap_block_state10_on_subcall_done, ap_CS_fsm_state13, icmp_ln787_fu_1326_p2, ap_CS_fsm_state14, icmp_ln790_fu_1345_p2, ap_block_pp1_stage0_subdone, ap_block_pp1_stage1_subdone, icmp_ln734_fu_646_p2, ap_CS_fsm_state12)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((reset_read_read_fu_248_p2 = ap_const_lv1_1) and (begin_read_read_fu_236_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
elsif (((reset_read_read_fu_248_p2 = ap_const_lv1_0) and (begin_read_read_fu_236_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
elsif (((begin_read_read_fu_236_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state15;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (icmp_ln734_fu_646_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (icmp_ln742_fu_813_p2 = ap_const_lv1_1) and (icmp_ln766_reg_1441 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state13;
elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (icmp_ln742_fu_813_p2 = ap_const_lv1_1) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
when ap_ST_fsm_pp1_stage0 =>
if ((not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (icmp_ln752_fu_960_p2 = ap_const_lv1_0))) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage1;
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (icmp_ln752_fu_960_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_pp1_stage1 =>
if ((ap_const_boolean_0 = ap_block_pp1_stage1_subdone)) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage1;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
if (((ap_const_boolean_0 = ap_block_state10_on_subcall_done) and (ap_const_logic_1 = ap_CS_fsm_state10))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
if (((grp_KeccakF1600_StatePer_fu_519_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state12;
end if;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and ((icmp_ln787_fu_1326_p2 = ap_const_lv1_1) or (icmp_ln766_reg_1441 = ap_const_lv1_1)))) then
ap_NS_fsm <= ap_ST_fsm_state15;
else
ap_NS_fsm <= ap_ST_fsm_state14;
end if;
when ap_ST_fsm_state14 =>
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (icmp_ln790_fu_1345_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state14;
end if;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXX";
end case;
end process;
add_ln746_1_fu_837_p2 <= std_logic_vector(unsigned(trunc_ln746_fu_823_p1) + unsigned(trunc_ln746_1_fu_827_p1));
add_ln752_fu_954_p2 <= std_logic_vector(unsigned(zext_ln752_fu_950_p1) + unsigned(p_01_idx_reg_364));
add_ln757_fu_985_p2 <= std_logic_vector(unsigned(or_ln757_fu_979_p2) + unsigned(trunc_ln742_reg_1473));
add_ln758_fu_1012_p2 <= std_logic_vector(unsigned(or_ln758_fu_1007_p2) + unsigned(trunc_ln742_reg_1473));
add_ln759_fu_1027_p2 <= std_logic_vector(unsigned(or_ln759_fu_1022_p2) + unsigned(trunc_ln742_reg_1473));
add_ln761_fu_1097_p2 <= std_logic_vector(unsigned(p_1_rec_reg_387) + unsigned(ap_const_lv64_4));
add_ln792_fu_1384_p2 <= std_logic_vector(unsigned(zext_ln792_fu_1380_p1) + unsigned(shl_ln_reg_1712));
and_ln766_fu_1305_p2 <= (icmp_ln766_reg_1441 and icmp_ln766_2_fu_1299_p2);
ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(5);
ap_CS_fsm_pp1_stage1 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(8);
ap_CS_fsm_state11 <= ap_CS_fsm(9);
ap_CS_fsm_state12 <= ap_CS_fsm(10);
ap_CS_fsm_state13 <= ap_CS_fsm(11);
ap_CS_fsm_state14 <= ap_CS_fsm(12);
ap_CS_fsm_state15 <= ap_CS_fsm(13);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state9 <= ap_CS_fsm(7);
ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage1_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage1_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_on_subcall_done_assign_proc : process(grp_KeccakF1600_StatePer_fu_519_ap_done, ap_predicate_op285_call_state10)
begin
ap_block_state10_on_subcall_done <= ((grp_KeccakF1600_StatePer_fu_519_ap_done = ap_const_logic_0) and (ap_predicate_op285_call_state10 = ap_const_boolean_1));
end process;
ap_block_state6_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp1_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp1_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_193_assign_proc : process(ap_CS_fsm_pp1_stage1, ap_block_pp1_stage1_11001, ap_enable_reg_pp1_iter0)
begin
ap_condition_193 <= ((ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage1) and (ap_const_boolean_0 = ap_block_pp1_stage1_11001));
end process;
ap_condition_379_assign_proc : process(icmp_ln752_reg_1496, trunc_ln760_reg_1516)
begin
ap_condition_379 <= (((((((((trunc_ln760_reg_1516 = ap_const_lv5_1E) and (icmp_ln752_reg_1496 = ap_const_lv1_1)) or ((trunc_ln760_reg_1516 = ap_const_lv5_1F) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) or ((trunc_ln760_reg_1516 = ap_const_lv5_1D) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) or ((trunc_ln760_reg_1516 = ap_const_lv5_1C) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) or ((trunc_ln760_reg_1516 = ap_const_lv5_1B) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) or ((trunc_ln760_reg_1516 = ap_const_lv5_1A) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) or ((trunc_ln760_reg_1516 = ap_const_lv5_19) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) or ((trunc_ln760_reg_1516 = ap_const_lv5_18) and (icmp_ln752_reg_1496 = ap_const_lv1_1)));
end process;
ap_condition_pp1_exit_iter0_state6_assign_proc : process(icmp_ln752_fu_960_p2)
begin
if ((icmp_ln752_fu_960_p2 = ap_const_lv1_0)) then
ap_condition_pp1_exit_iter0_state6 <= ap_const_logic_1;
else
ap_condition_pp1_exit_iter0_state6 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state15)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state15) or ((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter1)
begin
if (((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0))) then
ap_idle_pp1 <= ap_const_logic_1;
else
ap_idle_pp1 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_i_0_phi_fu_324_p4 <= i_0_reg_320;
ap_phi_mux_i_1_phi_fu_379_p4_assign_proc : process(i_1_reg_376, icmp_ln752_reg_1496, ap_CS_fsm_pp1_stage0, i_16_reg_1680, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_mux_i_1_phi_fu_379_p4 <= i_16_reg_1680;
else
ap_phi_mux_i_1_phi_fu_379_p4 <= i_1_reg_376;
end if;
end process;
ap_phi_mux_i_2_phi_fu_458_p4 <= i_2_reg_454;
ap_phi_mux_p_1_rec_phi_fu_391_p4_assign_proc : process(p_1_rec_reg_387, icmp_ln752_reg_1496, ap_CS_fsm_pp1_stage0, add_ln761_reg_1675, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (icmp_ln752_reg_1496 = ap_const_lv1_1))) then
ap_phi_mux_p_1_rec_phi_fu_391_p4 <= add_ln761_reg_1675;
else
ap_phi_mux_p_1_rec_phi_fu_391_p4 <= p_1_rec_reg_387;
end if;
end process;
ap_phi_mux_r_1_phi_fu_468_p18_assign_proc : process(p_0, p_1, p_2, p_3, p_4, p_5, p_6, p_7, p_24, icmp_ln766_reg_1441, ap_CS_fsm_state13, icmp_ln787_fu_1326_p2, ap_phi_mux_i_2_phi_fu_458_p4)
begin
if (not((ap_const_boolean_1 = ap_const_boolean_1))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_24;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_7) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_7;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_6) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_6;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_5) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_5;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_4) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_4;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_3) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_3;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_2) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_2;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_1) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_1;
elsif (((ap_phi_mux_i_2_phi_fu_458_p4 = ap_const_lv3_0) and (ap_const_logic_1 = ap_CS_fsm_state13) and (icmp_ln787_fu_1326_p2 = ap_const_lv1_0) and (icmp_ln766_reg_1441 = ap_const_lv1_0))) then
ap_phi_mux_r_1_phi_fu_468_p18 <= p_0;
else
ap_phi_mux_r_1_phi_fu_468_p18 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
ap_phi_reg_pp1_iter0_UnifiedRetVal_i_reg_399 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
ap_predicate_op285_call_state10_assign_proc : process(icmp_ln764_reg_1685, or_ln766_reg_1690)
begin
ap_predicate_op285_call_state10 <= ((or_ln766_reg_1690 = ap_const_lv1_1) and (icmp_ln764_reg_1685 = ap_const_lv1_1));
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state15)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(p_0_reg_510, ap_return_preg, ap_CS_fsm_state15)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state15)) then
ap_return <= p_0_reg_510;
else
ap_return <= ap_return_preg;
end if;
end process;
begin_read_read_fu_236_p2 <= begin_r;
empty_40_fu_914_p2 <= "1" when (unsigned(i_15_reg_331) > unsigned(zext_ln752_cast_fu_907_p1)) else "0";
empty_41_fu_965_p1 <= ap_phi_mux_p_1_rec_phi_fu_391_p4(11 - 1 downto 0);
empty_42_fu_999_p1 <= input_r_q0(8 - 1 downto 0);
empty_43_fu_1003_p1 <= input_r_q1(8 - 1 downto 0);
empty_44_fu_1109_p1 <= input_r_q0(8 - 1 downto 0);
empty_45_fu_1113_p1 <= input_r_q1(8 - 1 downto 0);
end_fu_849_p3 <=
add_ln746_1_fu_837_p2 when (icmp_ln747_fu_843_p2(0) = '1') else
ap_const_lv5_15;
grp_KeccakF1600_StatePer_fu_519_ap_start <= grp_KeccakF1600_StatePer_fu_519_ap_start_reg;
grp_fu_577_p4 <= input_r_q0(15 downto 8);
grp_fu_587_p4 <= input_r_q1(15 downto 8);
i_16_fu_1103_p2 <= std_logic_vector(unsigned(i_1_reg_376) + unsigned(ap_const_lv8_1));
i_17_fu_1331_p2 <= std_logic_vector(unsigned(i_2_reg_454) + unsigned(ap_const_lv3_1));
i_fu_652_p2 <= std_logic_vector(unsigned(i_0_reg_320) + unsigned(ap_const_lv5_1));
icmp_ln734_fu_646_p2 <= "1" when (i_0_reg_320 = ap_const_lv5_19) else "0";
icmp_ln742_fu_813_p2 <= "1" when (p_02_reg_343 = ap_const_lv16_0) else "0";
icmp_ln747_fu_843_p2 <= "1" when (unsigned(sum_fu_831_p2) < unsigned(ap_const_lv16_15)) else "0";
icmp_ln752_fu_960_p2 <= "1" when (unsigned(ap_phi_mux_i_1_phi_fu_379_p4) < unsigned(zext_ln752_cast_reg_1486)) else "0";
icmp_ln764_fu_1289_p2 <= "1" when (end_reg_1455 = ap_const_lv5_15) else "0";
icmp_ln766_1_fu_1294_p2 <= "0" when (sum_reg_1449 = ap_const_lv16_15) else "1";
icmp_ln766_2_fu_1299_p2 <= "1" when (p_02_reg_343 = ap_const_lv16_15) else "0";
icmp_ln766_fu_808_p2 <= "1" when (outlen = ap_const_lv6_0) else "0";
icmp_ln787_fu_1326_p2 <= "1" when (i_2_reg_454 = trunc_ln6_reg_1468) else "0";
icmp_ln790_fu_1345_p2 <= "1" when (j_0_reg_489 = ap_const_lv3_4) else "0";
inlen_cast_fu_642_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(inlen),16));
input_r_address0_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_CS_fsm_pp1_stage1, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0, p_01_idx22_cast_fu_974_p1, zext_ln758_fu_1017_p1, ap_block_pp1_stage1)
begin
if ((ap_enable_reg_pp1_iter0 = ap_const_logic_1)) then
if (((ap_const_boolean_0 = ap_block_pp1_stage1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage1))) then
input_r_address0 <= zext_ln758_fu_1017_p1(10 - 1 downto 0);
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
input_r_address0 <= p_01_idx22_cast_fu_974_p1(10 - 1 downto 0);
else
input_r_address0 <= "XXXXXXXXXX";
end if;
else
input_r_address0 <= "XXXXXXXXXX";
end if;
end process;
input_r_address1_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_CS_fsm_pp1_stage1, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0, zext_ln757_fu_990_p1, ap_block_pp1_stage1, zext_ln759_fu_1032_p1)
begin
if ((ap_enable_reg_pp1_iter0 = ap_const_logic_1)) then
if (((ap_const_boolean_0 = ap_block_pp1_stage1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage1))) then
input_r_address1 <= zext_ln759_fu_1032_p1(10 - 1 downto 0);
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
input_r_address1 <= zext_ln757_fu_990_p1(10 - 1 downto 0);
else
input_r_address1 <= "XXXXXXXXXX";
end if;
else
input_r_address1 <= "XXXXXXXXXX";
end if;
end process;
input_r_ce0_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_block_pp1_stage0_11001, ap_CS_fsm_pp1_stage1, ap_block_pp1_stage1_11001, ap_enable_reg_pp1_iter0)
begin
if ((((ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage1) and (ap_const_boolean_0 = ap_block_pp1_stage1_11001)) or ((ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001)))) then
input_r_ce0 <= ap_const_logic_1;
else
input_r_ce0 <= ap_const_logic_0;
end if;
end process;
input_r_ce1_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_block_pp1_stage0_11001, ap_CS_fsm_pp1_stage1, ap_block_pp1_stage1_11001, ap_enable_reg_pp1_iter0)
begin
if ((((ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage1) and (ap_const_boolean_0 = ap_block_pp1_stage1_11001)) or ((ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001)))) then
input_r_ce1 <= ap_const_logic_1;
else
input_r_ce1 <= ap_const_logic_0;
end if;
end process;
j_fu_1351_p2 <= std_logic_vector(unsigned(j_0_reg_489) + unsigned(ap_const_lv3_1));
or_ln757_fu_979_p2 <= (empty_41_fu_965_p1 or ap_const_lv11_1);
or_ln758_fu_1007_p2 <= (empty_41_reg_1500 or ap_const_lv11_2);
or_ln759_fu_1022_p2 <= (empty_41_reg_1500 or ap_const_lv11_3);
or_ln766_fu_1310_p2 <= (icmp_ln766_1_fu_1294_p2 or and_ln766_fu_1305_p2);
output_r_address0 <= zext_ln792_1_fu_1389_p1(4 - 1 downto 0);
output_r_ce0_assign_proc : process(ap_CS_fsm_state14)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
output_r_ce0 <= ap_const_logic_1;
else
output_r_ce0 <= ap_const_logic_0;
end if;
end process;
output_r_d0 <= (trunc_ln792_fu_1367_p1 & trunc_ln8_fu_1357_p4);
output_r_we0_assign_proc : process(ap_CS_fsm_state14, icmp_ln790_fu_1345_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (icmp_ln790_fu_1345_p2 = ap_const_lv1_0))) then
output_r_we0 <= ap_const_logic_1;
else
output_r_we0 <= ap_const_logic_0;
end if;
end process;
p_01_idx22_cast_fu_974_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_01_idx22_fu_969_p2),64));
p_01_idx22_fu_969_p2 <= std_logic_vector(unsigned(empty_41_fu_965_p1) + unsigned(trunc_ln742_reg_1473));
p_Result_7_fu_1117_p9 <= (((((((empty_45_fu_1113_p1 & grp_fu_587_p4) & empty_44_fu_1109_p1) & grp_fu_577_p4) & empty_43_reg_1530) & input_load_9_1_reg_1535) & empty_42_reg_1520) & input_load_1_reg_1525);
p_Result_s_fu_875_p4_proc : process(p_20, xor_ln784_fu_869_p2)
begin
p_Result_s_fu_875_p4 <= p_20;
p_Result_s_fu_875_p4(63) <= xor_ln784_fu_869_p2(0);
end process;
p_cast55_fu_910_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_15_reg_331),9));
r_3_fu_1394_p4 <= r_2_reg_500(63 downto 16);
r_4_fu_1404_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r_3_fu_1394_p4),64));
reset_read_read_fu_248_p2 <= reset;
ret_end_1_fu_1320_p3 <=
ap_const_lv5_0 when (icmp_ln764_reg_1685(0) = '1') else
end_reg_1455;
sext_ln752_fu_946_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_13_fu_938_p3),34));
shl_ln_fu_1337_p3 <= (i_2_reg_454 & ap_const_lv2_0);
sub_ln752_fu_932_p2 <= std_logic_vector(unsigned(umax12_cast_fu_928_p1) - unsigned(p_cast55_fu_910_p1));
sub_ln772_fu_1316_p2 <= std_logic_vector(unsigned(sum_reg_1449) - unsigned(zext_ln747_reg_1481));
sum_fu_831_p2 <= std_logic_vector(unsigned(p_02_reg_343) + unsigned(zext_ln746_fu_819_p1));
tmp_13_fu_938_p3 <= (sub_ln752_fu_932_p2 & ap_const_lv2_0);
tmp_14_fu_861_p3 <= p_20(63 downto 63);
trunc_ln742_fu_900_p1 <= p_01_idx_reg_364(11 - 1 downto 0);
trunc_ln746_1_fu_827_p1 <= p_02_reg_343(5 - 1 downto 0);
trunc_ln746_fu_823_p1 <= i_15_reg_331(5 - 1 downto 0);
trunc_ln760_fu_995_p1 <= ap_phi_mux_i_1_phi_fu_379_p4(5 - 1 downto 0);
trunc_ln792_fu_1367_p1 <= r_2_reg_500(8 - 1 downto 0);
trunc_ln8_fu_1357_p4 <= r_2_reg_500(15 downto 8);
umax12_cast_fu_928_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(umax12_fu_920_p3),9));
umax12_fu_920_p3 <=
i_15_reg_331 when (empty_40_fu_914_p2(0) = '1') else
zext_ln752_cast_fu_907_p1;
xor_ln760_fu_1133_p2 <= (p_Result_7_fu_1117_p9 xor ap_phi_reg_pp1_iter1_UnifiedRetVal_i_reg_399);
xor_ln784_fu_869_p2 <= (tmp_14_fu_861_p3 xor ap_const_lv1_1);
zext_ln742_fu_857_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ret_end_0_reg_353),8));
zext_ln746_fu_819_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_15_reg_331),16));
zext_ln747_fu_904_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(end_reg_1455),16));
zext_ln752_cast_fu_907_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(end_reg_1455),8));
zext_ln752_fu_950_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(sext_ln752_fu_946_p1),64));
zext_ln757_fu_990_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln757_fu_985_p2),64));
zext_ln758_fu_1017_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln758_fu_1012_p2),64));
zext_ln759_fu_1032_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln759_fu_1027_p2),64));
zext_ln792_1_fu_1389_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln792_fu_1384_p2),64));
zext_ln792_fu_1380_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_reg_489),5));
end behav;
|
<reponame>toebs88/SCAM<filename>example/RISCV_MS/RTL/SCAM_Model_types.vhd<gh_stars>1-10
--
-- Created by deutschmann on 14.02.18
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package SCAM_Model_types is
-- Memory size in Byte
constant MEM_SIZE : integer := 65536;
subtype bool is Boolean;
subtype int is Integer;
type ALUfuncType is (ALU_ADD,ALU_AND,ALU_COPY1,ALU_OR,ALU_SLL,ALU_SLT,ALU_SLTU,ALU_SRA,ALU_SRL,ALU_SUB,ALU_X,ALU_XOR);
type ALUopType is (OP_IMM,OP_PC,OP_REG,OP_X);
type ME_AccessType is (ME_RD,ME_WR,ME_X);
type ME_MaskType is (MT_B,MT_BU,MT_H,MT_HU,MT_W,MT_X);
type AccessType_Reg is (REG_RD,REG_WR);
type EncType is (ENC_B,ENC_ERR,ENC_I_I,ENC_I_L,ENC_I_J,ENC_J,ENC_R,ENC_S,ENC_U);
type InstrType is (INSTR_ADD,INSTR_ADDI,INSTR_AND,INSTR_ANDI,INSTR_AUIPC,INSTR_BEQ,INSTR_BGE,INSTR_BGEU,INSTR_BLT,INSTR_BLTU,INSTR_BNE,INSTR_JAL,INSTR_JALR,INSTR_LB,INSTR_LBU,INSTR_LH,INSTR_LHU,INSTR_LUI,INSTR_LW,INSTR_OR,INSTR_ORI,INSTR_SB,INSTR_SH,INSTR_SLL,INSTR_SLLI,INSTR_SLT,INSTR_SLTI,INSTR_SLTU,INSTR_SLTUI,INSTR_SRA,INSTR_SRAI,INSTR_SRL,INSTR_SRLI,INSTR_SUB,INSTR_SW,INSTR_UNKNOWN,INSTR_XOR,INSTR_XORI);
type PCselType is (PC_4,PC_BR,PC_EXC,PC_J,PC_JR);
type WBselType is (WB_ALU,WB_MEM,WB_PC4,WB_X);
type Cpath_SECTIONS is (requestInstr, receiveInstr, decode, setControl, readRegisterFile, requestALU, executeALU, evaluateALUresult, writeMemory, readMemory, writeBack);
type Mem_SECTIONS is (read, write);
type ALUtoCtl_IF is record
ALU_result : Unsigned (31 downto 0);
end record;
type CtlToALU_IF is record
alu_fun : ALUfuncType;
imm : Unsigned (31 downto 0);
op1_sel : ALUopType;
op2_sel : ALUopType;
pc_reg : Unsigned (31 downto 0);
reg1_contents : Unsigned (31 downto 0);
reg2_contents : Unsigned (31 downto 0);
end record;
type CtlToRegs_IF is record
dst : Unsigned (4 downto 0);
dst_data : Unsigned (31 downto 0);
req : AccessType_Reg;
src1 : Unsigned (4 downto 0);
src2 : Unsigned (4 downto 0);
end record;
type DecodedInstr is record
encType : EncType;
imm : Unsigned (31 downto 0);
instrType : InstrType;
rd_addr : Unsigned (4 downto 0);
rs1_addr : Unsigned (4 downto 0);
rs2_addr : Unsigned (4 downto 0);
end record;
type CUtoME_IF is record
addrIn : Unsigned (31 downto 0);
dataIn : Unsigned (31 downto 0);
mask : ME_MaskType;
req : ME_AccessType;
end record;
type MEtoCU_IF is record
loadedData: unsigned (31 downto 0);
end record;
type RegsToCtl_IF is record
contents1 : Unsigned (31 downto 0);
contents2 : Unsigned (31 downto 0);
end record;
type register_file is array (1 to 31) of Unsigned (31 downto 0);
type ram_type is array (0 to (MEM_SIZE-1)) of Unsigned (7 downto 0);
end package SCAM_Model_types;
|
<reponame>Hilson-Alex/mips-vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity somador is
port (i_a : IN std_logic_vector(31 downto 0); --entrada do valor A (inteiro)
i_b : IN std_logic_vector(31 downto 0); --entrada do valor B (inteiro)
o_c : OUT std_logic_vector(31 downto 0) -- saída do valor C (inteiro)
);
end somador;
ARCHITECTURE soma OF somador IS
signal w_a, w_b, w_c : INTEGER;
BEGIN
w_a <= to_integer(unsigned(i_a));
w_b <= to_integer(signed(i_b));
w_c <= w_a + w_b;
o_c <= std_logic_vector(to_unsigned(w_c, o_c'length));
END soma;
|
<filename>simulation/modelsim/verilog_libs/altera_ver/dffea/_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffea is
port(
d : in vl_logic;
clk : in vl_logic;
ena : in vl_logic;
clrn : in vl_logic;
prn : in vl_logic;
aload : in vl_logic;
adata : in vl_logic;
q : out vl_logic
);
end dffea;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux8_16bit_tb is
-- Port ( );
end mux8_16bit_tb;
architecture Behavioral of mux8_16bit_tb is
-- declare component to test
component mux8_16bit is
Port (
In0 : in std_logic_vector(15 downto 0);
In1 : in std_logic_vector(15 downto 0);
In2 : in std_logic_vector(15 downto 0);
In3 : in std_logic_vector(15 downto 0);
In4 : in std_logic_vector(15 downto 0);
In5 : in std_logic_vector(15 downto 0);
In6 : in std_logic_vector(15 downto 0);
In7 : in std_logic_vector(15 downto 0);
S0 : in std_logic;
S1 : in std_logic;
S2 : in std_logic;
Z : out std_logic_vector(15 downto 0));
end component;
-- signals for tests (initialise to 0)
--inputs
signal In0 : std_logic_vector(15 downto 0):= x"0000";
signal In1 : std_logic_vector(15 downto 0):= x"0000";
signal In2 : std_logic_vector(15 downto 0):= x"0000";
signal In3 : std_logic_vector(15 downto 0):= x"0000";
signal In4 : std_logic_vector(15 downto 0):= x"0000";
signal In5 : std_logic_vector(15 downto 0):= x"0000";
signal In6 : std_logic_vector(15 downto 0):= x"0000";
signal In7 : std_logic_vector(15 downto 0):= x"0000";
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
signal S2 : std_logic := '0';
--outputs
signal Z : std_logic_vector(15 downto 0):= x"0000";
begin
-- instantiate component for test, connect ports to internal signals
UUT: mux8_16bit
Port Map(
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => In6,
In7 => In7,
S0 => S0,
S1 => S1,
S2 => S2,
Z => Z
);
simulation_process :process
begin
In0 <= x"00AA";
In1 <= x"00BB";
In2 <= x"00CC";
In3 <= x"00DD";
In4 <= x"00EE";
In5 <= x"00FF";
In6 <= x"0AAA";
In7 <= x"0BBB";
--Select line 0 and send 0x00AA to output line Z
S0 <= '0';
S1 <= '0';
S2 <= '0';
wait for 5ns;
--Select line 1 and send 0x00BB to output line Z
S0 <= '0';
S1 <= '0';
S2 <= '1';
wait for 5ns;
--Select line 2 and send 0x00CC to output line Z
S0 <= '0';
S1 <= '1';
S2 <= '0';
wait for 5ns;
--Select line 3 and send 0x00DD to output line Z
S0 <= '0';
S1 <= '1';
S2 <= '1';
wait for 5ns;
--Select line 4 and send 0x00EE to output line Z
S0 <= '1';
S1 <= '0';
S2 <= '0';
wait for 5ns;
--Select line 5 and send 0x00FF to output line Z
S0 <= '1';
S1 <= '0';
S2 <= '1';
wait for 5ns;
--Select line 6 and send 0x0AAA to output line Z
S0 <= '1';
S1 <= '1';
S2 <= '0';
wait for 5ns;
--Select line 7 and send 0x0BBB to output line Z
S0 <= '1';
S1 <= '1';
S2 <= '1';
wait for 5ns;
end process;
end Behavioral;
|
<filename>Sources/ospboard/opt/osp/src/osp-wearable-fpga/src/fmexg_core.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fmexg_core is
port(
clock: in std_logic;
--
spi_clk, spi_cs: in std_logic;
spi_miso: out std_logic;
adc_clk, adc_pdwn: out std_logic;
adc_data: in std_logic_vector(11 downto 0);
interrupt: out std_logic;
fmexg_mic_sync: in std_logic
);
end entity;
architecture a of fmexg_core is
signal counter_div12: unsigned(2 downto 0);
signal clkdiv12: std_logic;
--signal fifo_readclk: std_logic;
signal spi_bit_ctr: unsigned(2 downto 0);
signal spi_byte_ctr: unsigned(1 downto 0);
signal fifo_readclk_en: std_logic;
signal first_sample: unsigned(11 downto 0);
signal two_samples: unsigned(23 downto 0);
--signal fifo_bit: unsigned(3 downto 0);
--signal hacky_fix: unsigned(1 downto 0);
--signal spi_data: std_logic;
--signal interrupt_counter: unsigned(7 downto 0);
signal fifo_Data: std_logic_vector(11 downto 0);
signal fifo_WrClock: std_logic;
signal fifo_RdClock: std_logic;
signal fifo_WrEn: std_logic;
signal fifo_RdEn: std_logic;
signal fifo_Reset: std_logic;
signal fifo_RPReset: std_logic;
signal fifo_Q: std_logic_vector(11 downto 0);
signal fifo_Q_u: unsigned(11 downto 0);
signal fifo_Empty: std_logic;
signal fifo_Full: std_logic;
signal fifo_AlmostEmpty: std_logic;
signal fifo_AlmostFull: std_logic;
signal rampcounter: unsigned(11 downto 0);
component fmexg_fifo_8k_1025 is
port (
Data: in std_logic_vector(11 downto 0);
WrClock: in std_logic;
RdClock: in std_logic;
WrEn: in std_logic;
RdEn: in std_logic;
Reset: in std_logic;
RPReset: in std_logic;
Q: out std_logic_vector(11 downto 0);
Empty: out std_logic;
Full: out std_logic;
AlmostEmpty: out std_logic;
AlmostFull: out std_logic
);
end component;
begin
adc_pdwn <= '0';
process(clock) is begin
if rising_edge(clock) then
counter_div12 <= counter_div12 + 1;
if counter_div12 = "101" then
counter_div12 <= "000";
clkdiv12 <= not clkdiv12;
end if;
end if;
end process;
adc_clk <= not clkdiv12;
process(clkdiv12) is begin
if falling_edge(clkdiv12) then
rampcounter <= rampcounter + 1;
--interrupt_counter <= interrupt_counter + 1;
end if;
end process;
interrupt <= fifo_AlmostFull; --and (and interrupt_counter);
fifo: fmexg_fifo_8k_1025 port map(
Data => fifo_Data,
WrClock => fifo_WrClock,
RdClock => fifo_RdClock,
WrEn => fifo_WrEn,
RdEn => fifo_RdEn,
Reset => fifo_Reset,
RPReset => fifo_RPReset,
Q => fifo_Q,
Empty => fifo_Empty,
Full => fifo_Full,
AlmostEmpty => fifo_AlmostEmpty,
AlmostFull => fifo_AlmostFull
);
fifo_Q_u <= unsigned(fifo_Q);
fifo_Data <= "100000000000" when fmexg_mic_sync = '1' else adc_data; --std_logic_vector(rampcounter);
fifo_WrClock <= clkdiv12;
fifo_RdClock <= spi_clk;
fifo_WrEn <= '1';
fifo_RdEn <= fifo_readclk_en;
fifo_Reset <= '0';
fifo_RPReset <= '0';
process(spi_clk) is begin
if falling_edge(spi_clk) then
if spi_cs = '0' then
two_samples <= '0' & two_samples(23 downto 1);
-- Read new data on second-to-last two rising edges
if spi_byte_ctr = "10" and (spi_bit_ctr = "110" or spi_bit_ctr = "111") then
fifo_readclk_en <= '1';
else
fifo_readclk_en <= '0';
end if;
if spi_byte_ctr = "10" and spi_bit_ctr = "111" then
--Falling edge of second-to-last clock pulse
--Register first sample of pair
first_sample <= unsigned(fifo_Q);
elsif spi_byte_ctr = "00" and spi_bit_ctr = "000" then
--Falling edge of last clock pulse
--Register two samples, swizzle bits
--VHDL does NOT allow e.g. a(7 downto 0) <= b(0 to 7) to reverse a vector
two_samples <= fifo_Q_u(4)
& fifo_Q_u(5)
& fifo_Q_u(6)
& fifo_Q_u(7)
& fifo_Q_u(8)
& fifo_Q_u(9)
& fifo_Q_u(10)
& fifo_Q_u(11)
& first_sample(8)
& first_sample(9)
& first_sample(10)
& first_sample(11)
& fifo_Q_u(0)
& fifo_Q_u(1)
& fifo_Q_u(2)
& fifo_Q_u(3)
& first_sample(0)
& first_sample(1)
& first_sample(2)
& first_sample(3)
& first_sample(4)
& first_sample(5)
& first_sample(6)
& first_sample(7);
end if;
end if;
end if;
end process;
spi_miso <= two_samples(0);
process(spi_clk, spi_cs) is begin
if spi_cs = '1' then
spi_bit_ctr <= "000";
spi_byte_ctr <= "00";
elsif rising_edge(spi_clk) then
--Increment bit (8) and byte (3) counters
if spi_bit_ctr = "111" then
if spi_byte_ctr = "10" then
spi_byte_ctr <= "00";
else
spi_byte_ctr <= spi_byte_ctr + 1;
end if;
end if;
spi_bit_ctr <= spi_bit_ctr + 1;
end if;
end process;
end architecture;
|
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