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<filename>hardware/src/host_channel/channel_DVCtoDNC.vhd<gh_stars>1-10
--------------------------------------------------------------------------------
-- Entity: channel_DVCtoDNC
--------------------------------------------------------------------------------
-- Copyright ... 2011
-- Filename : channel_DVCtoDNC.vhd
-- Creation date : 2011-09-07
-- Author(s) : dornbusc
-- Version : 1.00
-- Description : <short description>
--------------------------------------------------------------------------------
-- File History:
-- Date Version Author Comment
-- 2011-09-07 1.00 dornbusc Creation of File
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity channel_DVCtoDNC is
generic(
data_bits : natural --! data width of the channel (in bits).
);
port(
clk : in std_logic; --! input clock
i_data : in std_logic_vector(data_bits-1 downto 0);
i_vld : in std_logic;
i_cont : out std_logic;
o_data : out std_logic_vector(data_bits-1 downto 0);
o_new : out std_logic;
o_cont : in std_logic
);
end channel_DVCtoDNC;
architecture arch of channel_DVCtoDNC is
signal new_sig : std_logic;
begin
inst_output_ctrl: entity work.output_ctrl
port map(
clk => clk,
s_cont => i_cont,
s_vld => i_vld,
o_cont => o_cont,
o_new => new_sig
);
inst_output_buf : entity work.output_buf
generic map(
data_bits => data_bits
)
port map(
clk => clk,
s_data => i_data,
o_new => new_sig,
o_data => o_data
);
o_new <= new_sig;
end arch;
|
<reponame>AsciiShell/hse_hlimds_labs
component multiprocessor_tutorial_main_system is
port (
clk_clk_in_reset_reset_n : in std_logic := 'X'; -- reset_n
clk_in_clk : in std_logic := 'X' -- clk
);
end component multiprocessor_tutorial_main_system;
u0 : component multiprocessor_tutorial_main_system
port map (
clk_clk_in_reset_reset_n => CONNECTED_TO_clk_clk_in_reset_reset_n, -- clk_clk_in_reset.reset_n
clk_in_clk => CONNECTED_TO_clk_in_clk -- clk_in.clk
);
|
<reponame>tolgakarakurt/32x32-combinational-multipliers<gh_stars>1-10
------------------------------------------------------------------------------------------
--Karakurt--------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY A_register_8b_dp_tb IS
END ENTITY;
ARCHITECTURE tb OF A_register_8b_dp_tb IS
-- Component Declaration for the Unit Under Test (UUT)
------------------------------------------------------------------------------------------
COMPONENT A_register_8b_dp
PORT(clk : IN STD_LOGIC;
op : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
F : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
A : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------------------------------------------------------------------------
--Inputs
SIGNAL clk_tb : STD_LOGIC := '0';
SIGNAL op_tb : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL F_tb : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
--Outputs
SIGNAL A_tb : STD_LOGIC_VECTOR(7 DOWNTO 0);
CONSTANT period : time := 6 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: A_register_8b_dp
PORT MAP (clk => clk_tb,
op => op_tb,
F => F_tb,
A => A_tb
);
clk_tb <= NOT clk_tb after period/2;
op_tb <= "0000000", "1111111" AFTER 50 ns, "1010101" AFTER 100 ns, "0101010" AFTER 150 ns, "0010011" AFTER 200 ns, "1011100" AFTER 250 ns;
F_tb <= "00000000", "11111111" AFTER 50 ns, "01010101" AFTER 100 ns, "10011001" AFTER 150 ns, "00110011" AFTER 200 ns, "10001000" AFTER 250 ns;
stop: PROCESS
BEGIN
WAIT FOR 300 ns; -- Total Simulation Time
ASSERT FALSE
REPORT "Simulation ended by TK at" & time'image(now)
SEVERITY FAILURE;
END PROCESS;
END tb;
------------------------------------------------------------------------------------------
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleEnum IS
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_in0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF SimpleEnum IS
TYPE fsmT IS (send0, send1);
SIGNAL fsmSt : fsmt := send0;
SIGNAL fsmSt_next : fsmt;
BEGIN
assig_process_fsmSt: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
fsmSt <= send0;
ELSE
fsmSt <= fsmSt_next;
END IF;
END IF;
END PROCESS;
assig_process_fsmSt_next: PROCESS(fsmSt, s_in0, s_in1)
BEGIN
IF fsmSt = send0 THEN
s_out <= s_in0;
fsmSt_next <= send1;
ELSE
s_out <= s_in1;
fsmSt_next <= send0;
END IF;
END PROCESS;
END ARCHITECTURE;
|
<filename>CertificationSystem_M2S090TS/hdl/gv_sha256.vhd
----------------------------------------------------------------------------------
-- Author: <NAME>, <EMAIL>, <EMAIL>, <EMAIL>
--
-- Create Date: 01:21:32 05/05/2016
-- Design Name: gv_sha256
-- Module Name: GV_SHA256 toplevel
-- Project Name: GV_SHA256 engine
-- Target Devices: Spartan-6 LX45
-- Tool versions: ISE 14.7
-- Description:
--
-- This is the gv_sha256 engine top level.
-- The gv_sha256 is a stream hash engine, i.e., the data words are hashed as a stream of words read from an input bus, with
-- control inputs for BEGIN/END of the message data stream. The input bus is a 32bit word bus, with a byte lane selector to signalize
-- how many bytes are valid in the last word.
--
-- The core is a structural integration of the logic blocks for the SHA256 engine, with the internal datapath and controlpath wires.
--
-- Written in synthesizable VHDL, the hash engine is a low resource, area-efficient implementation of the FIPS-180-4 SHA256 hash algorithm.
-- Designed around the core registers and combinational hash functions as a 768bit-wide engine, the engine takes 64+1 clocks to
-- compute a hash block.
--
-- It is designed for stand-alone ASIC functions and 32-bit bus interfaces for generic processor integration.
--
-- The data input port is organized as a 32bit word write register, with flow control and begin/end signals.
-- The 256bit result register is organized as 8 x 32bit registers that can be read simultaneously.
--
-- This implementation is a conservative implementation of the approved FIPS-180-4 algorithm, with a fair compromise of resources,
-- comprising of only 32 registers of 32bit words for the hash engine, with a single-cycle combinational logic for each algorithm step.
-- The combinational logic depth of the engine is 10 logic layers. For a process with 650ps of average (Tpd + Tsu), this core can
-- be synthesized to 75MHz system clock.
--
-- The GV_SHA256 is a basic cryptographic block, used by almost all encryption and digital signature schemes.
--
-- Applications include low-cost CyberPhysical Systems and also fast backend crypto functions for realtime hashing of packet data.
-- It is used in the GridVortex CyberSec IP, as a base for the fused HMAC-SHA256, HKDF, HMAC-SHA256-DRBG, and the SP-800 TRNG Entropy Source.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
--
-- Author(s): <NAME>, <EMAIL>, <EMAIL>, <EMAIL>
--
-- Copyright (C) 2016 <NAME>
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification.
-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath.
-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed.
-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed.
-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block, added lookahead register feedback.
-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'.
--
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gv_sha256 is
port (
-- clock and core enable
clk_i : in std_logic := 'U'; -- system clock
ce_i : in std_logic := 'U'; -- core clock enable
-- input data
di_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- big endian input message words
bytes_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- valid bytes in input word
-- start/end commands
start_i : in std_logic := 'U'; -- reset the engine and start a new hash
end_i : in std_logic := 'U'; -- marks end of last block data input
-- handshake
di_req_o : out std_logic; -- requests data input for next word
di_wr_i : in std_logic := 'U'; -- high for di_i valid, low for hold
error_o : out std_logic; -- signalizes error. output data is invalid
do_valid_o : out std_logic; -- when high, the output is valid
-- 256bit output registers
H0_o : out std_logic_vector (31 downto 0);
H1_o : out std_logic_vector (31 downto 0);
H2_o : out std_logic_vector (31 downto 0);
H3_o : out std_logic_vector (31 downto 0);
H4_o : out std_logic_vector (31 downto 0);
H5_o : out std_logic_vector (31 downto 0);
H6_o : out std_logic_vector (31 downto 0);
H7_o : out std_logic_vector (31 downto 0)
);
end gv_sha256;
architecture rtl of gv_sha256 is
-- internal register data values
signal R0_data : std_logic_vector (31 downto 0);
signal R1_data : std_logic_vector (31 downto 0);
signal R2_data : std_logic_vector (31 downto 0);
signal R3_data : std_logic_vector (31 downto 0);
signal R4_data : std_logic_vector (31 downto 0);
signal R5_data : std_logic_vector (31 downto 0);
signal R6_data : std_logic_vector (31 downto 0);
signal R7_data : std_logic_vector (31 downto 0);
-- initial hash data values
signal K0_data : std_logic_vector (31 downto 0);
signal K1_data : std_logic_vector (31 downto 0);
signal K2_data : std_logic_vector (31 downto 0);
signal K3_data : std_logic_vector (31 downto 0);
signal K4_data : std_logic_vector (31 downto 0);
signal K5_data : std_logic_vector (31 downto 0);
signal K6_data : std_logic_vector (31 downto 0);
signal K7_data : std_logic_vector (31 downto 0);
-- hash result lookahead port
signal N0_data : std_logic_vector (31 downto 0);
signal N1_data : std_logic_vector (31 downto 0);
signal N2_data : std_logic_vector (31 downto 0);
signal N3_data : std_logic_vector (31 downto 0);
signal N4_data : std_logic_vector (31 downto 0);
signal N5_data : std_logic_vector (31 downto 0);
signal N6_data : std_logic_vector (31 downto 0);
signal N7_data : std_logic_vector (31 downto 0);
-- hash result data
signal H0_data : std_logic_vector (31 downto 0);
signal H1_data : std_logic_vector (31 downto 0);
signal H2_data : std_logic_vector (31 downto 0);
signal H3_data : std_logic_vector (31 downto 0);
signal H4_data : std_logic_vector (31 downto 0);
signal H5_data : std_logic_vector (31 downto 0);
signal H6_data : std_logic_vector (31 downto 0);
signal H7_data : std_logic_vector (31 downto 0);
-- message schedule word datapath
signal Mi_data : std_logic_vector (31 downto 0);
signal Wt_data : std_logic_vector (31 downto 0);
-- coefficients ROMs
signal Kt_data : std_logic_vector (31 downto 0);
signal Kt_addr : std_logic_vector (5 downto 0);
-- padding control
signal words_sel : std_logic_vector (1 downto 0);
signal bytes_ena : std_logic_vector (3 downto 0);
signal one_insert : std_logic;
signal msg_bitlen : std_logic_vector (63 downto 0);
signal pad_data : std_logic_vector (31 downto 0);
-- block mux selectors
signal sch_ld : std_logic;
signal core_ld : std_logic;
signal oregs_ld : std_logic;
-- block clock enables
signal sch_ce : std_logic;
signal core_ce : std_logic;
signal oregs_ce : std_logic;
-- output data valid / error
signal data_valid : std_logic;
signal error_pad : std_logic;
signal error_ctrl : std_logic;
begin
--=============================================================================================
-- INTERNAL COMPONENT INSTANTIATIONS AND CONNECTIONS
--=============================================================================================
-- control path core logic
Inst_sha256_control: entity work.sha256_control(rtl)
port map(
-- inputs
clk_i => clk_i,
ce_i => ce_i,
bytes_i => bytes_i,
wr_i => di_wr_i,
start_i => start_i,
end_i => end_i,
error_i => error_pad,
-- output control signals
bitlen_o => msg_bitlen,
words_sel_o => words_sel,
Kt_addr_o => Kt_addr,
sch_ld_o => sch_ld,
core_ld_o => core_ld,
oregs_ld_o => oregs_ld,
sch_ce_o => sch_ce,
core_ce_o => core_ce,
oregs_ce_o => oregs_ce,
one_insert_o => one_insert,
bytes_ena_o => bytes_ena,
di_req_o => di_req_o,
data_valid_o => data_valid,
error_o => error_ctrl
);
-- datapath: sha256 byte padding
Inst_sha256_padding: entity work.sha256_padding(rtl)
port map(
words_sel_i => words_sel,
one_insert_i => one_insert,
bytes_ena_i => bytes_ena,
bitlen_i => msg_bitlen,
di_i => di_i,
do_o => Mi_data,
error_o => error_pad
);
-- datapath: sha256 message schedule
Inst_sha256_msg_sch: entity work.sha256_msg_sch(rtl)
port map(
clk_i => clk_i,
ce_i => sch_ce,
ld_i => sch_ld,
M_i => Mi_data,
Wt_o => Wt_data
);
-- datapath: sha256 core logic
Inst_sha256_hash_core: entity work.sha256_hash_core(rtl)
port map(
clk_i => clk_i,
ce_i => core_ce,
ld_i => core_ld,
-- initial hash data values
A_i => N0_data,
B_i => N1_data,
C_i => N2_data,
D_i => N3_data,
E_i => N4_data,
F_i => N5_data,
G_i => N6_data,
H_i => N7_data,
-- block hash values
A_o => R0_data,
B_o => R1_data,
C_o => R2_data,
D_o => R3_data,
E_o => R4_data,
F_o => R5_data,
G_o => R6_data,
H_o => R7_data,
-- key coefficients
Kt_i => Kt_data,
-- message schedule word input
Wt_i => Wt_data
);
-- datapath: sha256 output registers
Inst_sha256_regs: entity work.sha256_regs(rtl)
port map(
clk_i => clk_i,
ce_i => oregs_ce,
ld_i => oregs_ld,
-- register data from the core logic
A_i => R0_data,
B_i => R1_data,
C_i => R2_data,
D_i => R3_data,
E_i => R4_data,
F_i => R5_data,
G_i => R6_data,
H_i => R7_data,
-- initial hash values
K0_i => K0_data,
K1_i => K1_data,
K2_i => K2_data,
K3_i => K3_data,
K4_i => K4_data,
K5_i => K5_data,
K6_i => K6_data,
K7_i => K7_data,
-- lookahead output hash values, one pipeline advanced
N0_o => N0_data,
N1_o => N1_data,
N2_o => N2_data,
N3_o => N3_data,
N4_o => N4_data,
N5_o => N5_data,
N6_o => N6_data,
N7_o => N7_data,
-- output hash values
H0_o => H0_data,
H1_o => H1_data,
H2_o => H2_data,
H3_o => H3_data,
H4_o => H4_data,
H5_o => H5_data,
H6_o => H6_data,
H7_o => H7_data
);
-- coefficients ROM: modelled as an asynchronously addressable ROM
Inst_sha256_kt_rom: entity work.sha256_kt_rom(behavioral)
port map(
addr_i => Kt_addr,
dout_o => Kt_data
);
-- init output data ROM: modelled as a statically defined constant
Inst_sha256_ki_rom: entity work.sha256_ki_rom(behavioral)
port map(
K0_o => K0_data,
K1_o => K1_data,
K2_o => K2_data,
K3_o => K3_data,
K4_o => K4_data,
K5_o => K5_data,
K6_o => K6_data,
K7_o => K7_data
);
--=============================================================================================
-- OUTPUTS LOGIC
--=============================================================================================
error_o_proc: error_o <= error_ctrl;
do_valid_o_proc: do_valid_o <= data_valid;
H0_o_proc: H0_o <= H0_data;
H1_o_proc: H1_o <= H1_data;
H2_o_proc: H2_o <= H2_data;
H3_o_proc: H3_o <= H3_data;
H4_o_proc: H4_o <= H4_data;
H5_o_proc: H5_o <= H5_data;
H6_o_proc: H6_o <= H6_data;
H7_o_proc: H7_o <= H7_data;
end rtl;
|
<gh_stars>10-100
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, <NAME>
-- Copyright (C) 2015 - 2017, <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgprbank
-- File: grgprbank.vhd
-- Author: <NAME> - <NAME>
-- Description: General purpose register bank
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity grgprbank is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval : integer := 0;
extrst : integer := 0;
rdataen: integer := 0;
wproten: integer := 0;
partrstmsk: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0);
resval : in std_logic_vector(nregs*regbits-1 downto 0);
rdata : in std_logic_vector(nregs*regbits-1 downto 0);
wprot : in std_logic_vector(nregs-1 downto 0);
partrst : in std_ulogic
);
end;
architecture rtl of grgprbank is
constant nregsp2: integer := 2**log2(nregs);
subtype regtype is std_logic_vector(regbits-1 downto 0);
type regbank is array(nregsp2-1 downto 0) of regtype;
type grgprbank_regs is record
regs: regbank;
end record;
signal r,nr: grgprbank_regs;
constant pconfig: apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GPREGBANK, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
begin
comb: process(r,rst,apbi,resval,rdata,wprot,partrst)
variable v: grgprbank_regs;
variable o: apb_slv_out_type;
variable rd: regbank;
variable wprotx: std_logic_vector(nregsp2-1 downto 0);
begin
-- Init vars
v := r;
o := apb_none;
o.pindex := pindex;
o.pconfig := pconfig;
for x in nregs-1 downto 0 loop
rd(x) := rdata(x*regbits+regbits-1 downto x*regbits);
end loop;
wprotx := (others => '0');
wprotx(nregs-1 downto 0) := wprot;
-- APB Interface
if nregs > 1 then
o.prdata(regbits-1 downto 0) := r.regs(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2))));
if rdataen /= 0 then
o.prdata(regbits-1 downto 0) := rd(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2))));
end if;
if apbi.penable='1' and apbi.psel(pindex)='1' and apbi.pwrite='1' then
if wproten=0 or (wprotx(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2))))='0') then
v.regs(to_integer(unsigned(apbi.paddr(1+log2(nregs) downto 2)))) := apbi.pwdata(regbits-1 downto 0);
end if;
end if;
else
o.prdata(regbits-1 downto 0) := r.regs(0);
if apbi.penable='1' and apbi.psel(pindex)='1' and apbi.pwrite='1' then
v.regs(0) := apbi.pwdata(regbits-1 downto 0);
end if;
end if;
-- Partial reset
if partrstmsk/=0 then
if partrst='0' then
for x in 0 to nregs-1 loop
if ((partrstmsk / (2**x)) mod 2) = 1 then
if extrst=0 then
v.regs(x) := std_logic_vector(to_unsigned(rstval,regbits));
else
v.regs(x) := resval(x*regbits+regbits-1 downto x*regbits);
end if;
end if;
end loop;
end if;
end if;
-- Reset
if rst='0' then
v.regs := (others => std_logic_vector(to_unsigned(rstval,regbits)));
if extrst/=0 then
for x in nregs-1 downto 0 loop
v.regs(x) := resval(x*regbits+regbits-1 downto x*regbits);
end loop;
end if;
end if;
-- clear unused part of reg bank so it can be pruned
if nregs < nregsp2 then
for x in nregsp2-1 downto nregs loop
v.regs(x) := (others => '0');
end loop;
end if;
-- Drive outputs
nr <= v;
apbo <= o;
for x in nregs-1 downto 0 loop
rego(x*regbits+regbits-1 downto x*regbits) <= r.regs(x);
end loop;
end process;
regs: process(clk)
begin
if rising_edge(clk) then r <= nr; end if;
end process;
end;
|
--
-- Copyright (c) 2018, UPC
-- All rights reserved.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.param_disenyo_pkg.all;
use work.cte_tipos_deco_camino_pkg.all;
use work.componentes_secuenciamiento_PreSecu_pkg.all;
use work.RegDes_pkg.all;
entity RErsec is
port(reloj, pcero, I: in std_logic;
opSEC: in st_opSEC;
ErPre: in std_logic;
msecuseg: out std_logic);
end RErsec;
architecture comporta of RErsec is
signal opSEC_A4: st_opSEC;
begin
RA4_opSEC: RDI_N generic map (tam => num_opSEC)
port map (reloj => reloj, pcero => pcero, I => I, e => opSEC, s => opSEC_A4);
R_Ersec: Ersec port map (opSEC => opSEC_A4, ErPre => ErPre, msecuseg => msecuseg);
end;
|
<gh_stars>10-100
------------------------------------------------------------------------------------------------
-- Copyright (c) 2011 <NAME>
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the copyright holder nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-- IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ------------------------------------------------------------------------------------------------
-- ------------------------------------------------------------------------------------------------
-- Generates a sticky-bit for rounding purpose. During alignment of the exponents the C operand is
-- shifted to the right. If bits are shifted out of the range of this operand, these bits are
-- logically or'ed into a sticky-bit. In other words, during shift, if a '1' is shifted out of the
-- range then the sticky bit becomes '1' and stays '1'. This sticky-bit is used to indicate that
-- the intermediate result is inexact.
-- ------------------------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.alu_pkg_lvl1.all;
use work.alu_pkg_lvl2.all;
entity stickybit_generation is
port(
significand_c_in : in std_logic_vector(SIGNIFICANDWIDTH downto 0); -- the entire significand of operand C
shift_in : in std_logic_vector(log2_ceil(3*(HIDDENBIT+SIGNIFICANDWIDTH)+GUARDBITS) downto 0); -- the alignment shift for C
sticky_out : out std_logic -- the primary sticky-bit (caused by alignment only)
);
end stickybit_generation;
architecture rtl of stickybit_generation is
begin
combinatorial : process(significand_c_in, shift_in)
variable newshift : integer;
variable reduce : std_logic_vector(SIGNIFICANDWIDTH downto 0);
variable shift : std_logic_vector(2*(SIGNIFICANDWIDTH+HIDDENBIT)-1 downto 0);
begin
-- C shifted out of range entirely, it does not matter how far, just or-reduce the significand
-- of C into a sticky-bit.
if(unsigned(shift_in) >= (3*(SIGNIFICANDWIDTH+HIDDENBIT)+GUARDBITS)) then
reduce := significand_c_in;
-- C stays entirely within range, no bits are shifted out so sticky-bit is '0'.
elsif(unsigned(shift_in) < (2*(SIGNIFICANDWIDTH+HIDDENBIT)+GUARDBITS+1)) then
reduce := (others => '0');
-- only partially shifted out of range, compute which part is shifted out.
else
-- Or-reduce only the bits shifted out of the range.
newshift := to_integer(unsigned(shift_in) - (2*(SIGNIFICANDWIDTH+HIDDENBIT)+2));
shift := (others => '0');
shift(shift'left downto (shift'left-(SIGNIFICANDWIDTH))) := significand_c_in;
shift := std_logic_vector(shift_right(unsigned(shift),newshift));
reduce := shift(SIGNIFICANDWIDTH downto 0);
end if;
sticky_out <= or_reduce(reduce);
end process;
end rtl;
|
library verilog;
use verilog.vl_types.all;
entity oper_less_than is
generic(
width_a : integer := 6;
width_b : integer := 6;
sgate_representation: integer := 0;
width_max : vl_notype
);
port(
a : in vl_logic_vector;
b : in vl_logic_vector;
cin : in vl_logic;
o : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of sgate_representation : constant is 1;
attribute mti_svvh_generic_type of width_max : constant is 3;
end oper_less_than;
|
-- ----------------------------------------------------------------------------
-- FILE: ddr2rxiq.vhd
-- DESCRIPTION: Take data from ddri and convert to RXIQ
-- DATE: Mar 31, 2015
-- AUTHOR(s): <NAME>
-- REVISIONS:
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity ddr2rxiq is
port(
reset_n : in std_logic; ---input reset active low
clk : in std_logic;
dil : in std_logic_vector(12 downto 0);
dih : in std_logic_vector(12 downto 0);
rxiqsel : out std_logic;
rxdA : out std_logic_vector(11 downto 0);
rxdB : out std_logic_vector(11 downto 0);
AI : out std_logic_vector(11 downto 0);
AQ : out std_logic_vector(11 downto 0);
BI : out std_logic_vector(11 downto 0);
BQ : out std_logic_vector(11 downto 0)
);
end entity ddr2rxiq;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture ddr2rxiq_arch of ddr2rxiq is
signal rai, raid1 : std_logic_vector(11 downto 0);
signal raq : std_logic_vector(11 downto 0);
signal rbi : std_logic_vector(11 downto 0);
signal rbq : std_logic_vector(11 downto 0);
begin
-- A channel
process(clk, reset_n)
begin
if(reset_n = '0') then
rai <= (others => '0');
raq <= (others => '0');
raid1 <= (others => '0');
elsif (clk'event and clk = '1') then
if dih(12) = '0' then
rai <= dih(11 downto 0);
raq <= dil(11 downto 0);
raid1 <= rai;
end if;
end if;
end process;
-- B channel
process(clk, reset_n)
begin
if(reset_n = '0') then
rbi <= (others => '0');
rbq <= (others => '0');
elsif (clk'event and clk = '1') then
if dih(12) = '1' then
rbi <= dih(11 downto 0);
rbq <= dil(11 downto 0);
end if;
end if;
end process;
rxiqsel <= dih(12);
rxdA <= raid1 when dih(12) = '1' else raq;
rxdB <= rbi when dih(12) = '1' else rbq;
AI <= rai;
AQ <= raq;
BI <= rbi;
BQ <= rbq;
end architecture;
|
<filename>packages/pkg_directions.vhd
package PROJECT_DIRECTION_PKG is
constant D_UP : integer range 0 to 3 := 0;
constant D_RIGHT : integer range 0 to 3 := 1;
constant D_DOWN : integer range 0 to 3 := 2;
constant D_LEFT : integer range 0 to 3 := 3;
subtype direction_type is integer range 0 to 3;
end package;
|
library IEEE;
library work;
use work.commonPackage.all;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity control_unit is
port (
clk : in std_logic;
clear_rst : in std_logic;
output_reg : out rpn_type_register;
add_input : in std_logic;
subtract_input : in std_logic;
multiply_input : in std_logic;
divide_input : in std_logic;
enter_input : in std_logic;
s_ascii_out_input : in std_logic;
input_keypad_input : in std_logic_vector(3 downto 0 );
-- outputs
output_string_output : out string(3 downto 1);
-- error_out_of_bound_output : out std_logic;
test_led : out std_logic_vector(2 downto 0);
error_out_of_bound : out std_logic;
error_division_by_zero : out std_logic
);
end control_unit;
architecture Behavioral of control_unit is
-- signal test_led : std_logic_vector(3 downto 0) := "0000";
signal reg : rpn_type_register := (others => ( others => '0'));
signal add : std_logic;
signal last_add_state : std_logic;
signal subtract : std_logic;
signal last_subtract_state : std_logic;
signal multiply : std_logic;
signal last_multiply_state : std_logic;
signal divide : std_logic;
signal last_divide_state : std_logic;
signal enter : std_logic;
signal last_enter_state : std_logic;
signal int_data : integer;
signal output_string : string(3 downto 1) := " ";
signal signed_output : signed( DATA_SIZE -1 DOWNTO 0);
signal operation_signal : std_logic_vector(4 - 1 downto 0);
signal s_ascii_out : std_logic ;
signal last_keypress_state : std_logic;
signal keypad_input : std_logic_vector(3 downto 0 );
signal error_check : signed( DATA_SIZE DOWNTO 0);
-- error string
-- signal error_out_of_bound : std_logic;
-- signal error_division_by_zero : std_logic;
-- signal temp_for_error_testing : signed(DATA_SIZE - 1 downto 0);
-- signal input2_signal : signed(DATA_SIZE - 1 downto 0);
-- signal input1_signal : signed(DATA_SIZE - 1 DOWNTO 0);
-- division circuit dummies
-- signal signal_busy : std_logic;
-- signal mul_result : std_logic_vector(2 * DATA_SIZE - 1 downto 0);
-- signal signal_s : std_logic;
-- signal done : std_logic;
-- signal hello_temp : std_logic_vector(DATA_SIZE - 1 downto 0);
-- component ALU is
-- Port (
-- clk : in std_logic;
-- Reset : in std_logic;
-- input1 : in signed(DATA_SIZE - 1 DOWNTO 0);
-- input2 : in signed(DATA_SIZE - 1 DOWNTO 0);
-- output : out signed(DATA_SIZE - 1 DOWNTO 0);
-- operation : in std_logic_vector(4 - 1 downto 0)
-- );
-- end component;
-- component division_controller IS
-- PORT(
-- clock : IN STD_LOGIC; --system clock
-- reset_n : IN STD_LOGIC; --resets on logic low
-- enable : IN STD_LOGIC; --signal high for division to start
-- busy : OUT STD_LOGIC; --goes high when busy, low when done
-- divisor : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --2 digit divisor
-- dividend : IN STD_LOGIC_VECTOR(23 DOWNTO 0); --6 digit dividend
-- quotient : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);--6 digit quotient result
-- remainder : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --2 digit remainder result
-- subtrahend : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);--output to bcd adder
-- minuend : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);--output to bcd adder
-- result : IN STD_LOGIC_VECTOR(11 DOWNTO 0)); --input from bcd adder
-- END component;
component multiply_CIR IS
GENERIC
(
N : integer;
NN : integer -- stands for 2 * N
);
PORT (
Clock : IN STD_LOGIC ;
Resetn : IN STD_LOGIC ;
Load_A, Load_B, s : IN STD_LOGIC ;
DataA : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
DataB : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
P_out : out STD_LOGIC_VECTOR(NN-1 DOWNTO 0);
Done : OUT STD_LOGIC
);
END component ;
signal signal_s : std_logic;
signal load_A_signal : std_logic;
signal load_B_signal : std_logic;
signal dataB_temp : std_logic_vector(DATA_SIZE - 1 downto 0);
signal dataA_temp : std_logic_vector(DATA_SIZE - 1 downto 0);
signal mul_result : std_logic_vector(2 * DATA_SIZE - 1 downto 0);
signal done : std_logic;
type mul_state is (stop, go);
signal current_mul_state : mul_state;
signal to_temp : STD_LOGIC_VECTOR(DATA_SIZE - 1 DOWNTO 0);
begin
-- with current_mul_state select test_led(1 downto 0)
-- <= "10" when go,
-- "01" when others;
-- test_led(2) <= done;
dataB_temp <= std_logic_vector(to_signed(int_data, reg(0)'length));
dataA_temp <= std_logic_vector(reg(0));
-- to_temp <= mul_result(2 * DATA_SIZE -1 DOWNTO DATA_SIZE);
-- with to_temp select
-- error_out_of_bound <= '0' when "00000000000",
-- '1' when others;
-- process(error_check, clear_rst)
-- begin
-- if clear_rst = '0' then
-- error_out_of_bound <= '0';
-- end process;
mul_FSM : process(clear_rst, clk)
begin
if clear_rst = '0' then
current_mul_state <= stop;
test_led <= "000";
elsif rising_edge(clk) then
case current_mul_state is
when stop =>
if multiply = '1' and last_multiply_state = '0' then
current_mul_state <= go;
test_led(1 downto 0) <= "00";
test_led(2) <= '1';
else
current_mul_state <= stop;
test_led(1 downto 0) <= "01";
end if;
when go =>
if done = '1' then -- done! can go to stable state multiply = '1' and last_multiply_state = '0' and
current_mul_state <= stop;
test_led(1 downto 0) <= "10";
else
current_mul_state <= go; -- remain in multiplication period
test_led(1 downto 0) <= "11";
end if;
end case;
last_multiply_state <= multiply;
end if;
end process;
test : process(current_mul_state)
begin
if current_mul_state = go then
signal_s <= '1';
load_A_signal <= '0';
load_B_signal <= '0';
elsif current_mul_state = stop then
signal_s <= '0';
load_A_signal <= '1';
load_B_signal <= '1';
end if;
end process;
-- mul_data_FSM : process(current_mul_state)
-- begin
-- if current_mul_state = go then--multiply = '1' and last_multiply_state = '0' then
---- operation_signal <= "0100";
---- reg(0) <= signed_output;
---- reg(0) <= reg(0) * to_signed(int_data, reg(0)'length);
-- reg(0) <= signed(mul_result(DATA_SIZE -1 DOWNTO 0));
-- output_string <= " ";
-- end if;
-- end process;
mul_uut : multiply_CIR
GENERIC map
(
N => DATA_SIZE,
NN => 2 * DATA_SIZE
)
PORT map(
Clock => CLK,
Resetn => clear_rst,
s => signal_s,
Load_A => load_A_signal,
Load_B => load_B_signal,
DataA => dataA_temp,
DataB => dataB_temp,
P_out => mul_result,
Done => done
);
-- division_uut : division_controller port map (
-- clock => clk,
-- reset_n => clear_rst,
-- enable => '1',
-- busy => signal_busy,
-- divisor : std_logic_vector(to_signed(int_data, reg(0)'length)),
-- dividend : std_logic_vector(reg(0)),
-- quotient : division_result,
-- remainder : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --2 digit remainder result
-- subtrahend : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);--output to bcd adder
-- minuend : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);--output to bcd adder
-- result : IN STD_LOGIC_VECTOR(11 DOWNTO 0)); --input from bcd adder
-- test_led <= keypad_input;
-- input2_signal <= to_signed(int_data, reg(0)'length); -- good
-- input1_signal <= reg(0); -- good
-- process(operation_signal)
-- begin
-- case operation_signal is
-- when "0001" => signed_output <= input2_signal + input1_signal;
-- when "0010" => signed_output <= input2_signal - input1_signal;
-- when "0100" => signed_output <= input2_signal + input1_signal;
-- when "1000" => signed_output <= input2_signal - input1_signal;
-- when others => signed_output <= REGISTER_ZERO;
-- end case;
-- end process;
-- ALU_uut : ALU port map
-- (
-- clk => clk,
-- Reset => clear_rst,
-- input1 => input1_signal,
-- input2 => input2_signal,
-- output => signed_output,
-- operation => operation_signal
-- );
-- error_check : process(clk)
-- begin
-- temp_for_error_testing <= reg(1) + reg(0);
-- if ( add = '1' and last_add_state = '0' ) then
-- if (reg(1)(MOST_SIGNIFICANT_BIT_NUMBER) = '0' and reg(0)(MOST_SIGNIFICANT_BIT_NUMBER) = '0'
-- and temp_for_error_testing(MOST_SIGNIFICANT_BIT_NUMBER) = '1')
-- OR (reg(1)(MOST_SIGNIFICANT_BIT_NUMBER) = '1' and reg(0)(MOST_SIGNIFICANT_BIT_NUMBER) = '1'
-- and temp_for_error_testing(MOST_SIGNIFICANT_BIT_NUMBER) = '0') then
-- error_out_of_bound <= '1';
-- else
-- error_out_of_bound <= '0';
-- end if;
-- elsif ( subtract = '1' and last_subtract_state = '0' ) then
-- if (reg(1)(MOST_SIGNIFICANT_BIT_NUMBER) = '0' and reg(0)(MOST_SIGNIFICANT_BIT_NUMBER) = '0'
-- and temp_for_error_testing(MOST_SIGNIFICANT_BIT_NUMBER) = '1')
-- OR (reg(1)(MOST_SIGNIFICANT_BIT_NUMBER) = '1' and reg(0)(MOST_SIGNIFICANT_BIT_NUMBER) = '1'
-- and temp_for_error_testing(MOST_SIGNIFICANT_BIT_NUMBER) = '0') then
-- error_out_of_bound <= '1';
-- else
-- error_out_of_bound <= '0';
-- end if;
-- end if;
-- end process;
rpn_calculator : process(clk, clear_rst)
begin
if clear_rst = '0' then
reg <= (others => ( others => '0'));
output_string <= " ";
error_division_by_zero <= '0';
error_out_of_bound <= '0';
elsif rising_edge(clk) then
if add = '1' and last_add_state = '0' and current_mul_state = stop then
-- operation_signal <= "0001";
-- reg(0) <= signed_output;
reg(0) <= reg(0) + to_signed(int_data, reg(0)'length);
output_string <= " ";
error_check <= ('0' & reg(0)) + ('0' & to_signed(int_data, reg(0)'length));
-- signal_s <= '0';
-- load_A_signal <= '1';
-- load_B_signal <= '1';
elsif subtract = '1' and last_subtract_state = '0' and current_mul_state = stop then
-- operation_signal <= "0010";
-- reg(0) <= signed_output;
reg(0) <= reg(0) - to_signed(int_data, reg(0)'length);
output_string <= " ";
error_check <= ('0' & reg(0)) - ('0' & to_signed(int_data, reg(0)'length));
elsif current_mul_state = go then--multiply = '1' and last_multiply_state = '0' then
reg(0) <= signed(mul_result(DATA_SIZE -1 DOWNTO 0));
output_string <= " ";
to_temp <= mul_result(2 * DATA_SIZE -1 DOWNTO DATA_SIZE);
if to_temp = "00000000000" then
error_out_of_bound <= '0';
else
error_out_of_bound <= '1';
end if;
--error_check <= reg(0) + to_signed(int_data, reg(0)'length);
elsif divide = '1' and last_divide_state = '0' then
reg(0) <= reg(0) / to_signed(int_data, reg(0)'length);
output_string <= " ";
error_check <= ('0' & reg(0)) / ('0' & to_signed(int_data, reg(0)'length));
if to_signed(int_data, reg(0)'length) = "00000000000" then
error_division_by_zero <= '1';
else
error_division_by_zero <= '0';
end if;
-- append the third string from right
elsif output_string = " " and keypad_input = "0001" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '1';
int_data <= 1;
elsif output_string = " " and keypad_input = "0010" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '2';
int_data <= 2;
elsif output_string = " " and keypad_input = "0011" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '3';
int_data <= 3;
elsif output_string = " " and keypad_input = "0100" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '4';
int_data <= 4;
elsif output_string = " " and keypad_input = "0101" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '5';
int_data <= 5;
elsif output_string = " " and keypad_input = "0110" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '6';
int_data <= 6;
elsif output_string = " " and keypad_input = "0111" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '7';
int_data <= 7;
elsif output_string = " " and keypad_input = "1000" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '8';
int_data <= 8;
elsif output_string = " " and keypad_input = "1001" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '9';
int_data <= 9;
elsif output_string = " " and keypad_input = "0000" and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(3) <= '0';
int_data <= 0;
-- append the second string from right
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0001"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '1';
int_data <= (int_data * 10) + 1;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0010"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '2';
int_data <= (int_data * 10) + 2;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0011"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '3';
int_data <= (int_data * 10) + 3;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0100"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '4';
int_data <= (int_data * 10) + 4;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0101"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '5';
int_data <= (int_data * 10) + 5;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0110"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '6';
int_data <= (int_data * 10) + 6;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0111"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '7';
int_data <= (int_data * 10) + 7;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "1000"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '8';
int_data <= (int_data * 10) + 8;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "1001"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '9';
int_data <= (int_data * 10) + 9;
elsif output_string(3) /= ' ' and output_string(2 downto 1) = " " and keypad_input = "0000"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(2) <= '0';
int_data <= (int_data * 10) + 0;
-- append the first string from right
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0001"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '1';
int_data <= (int_data * 10) + 1;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0010"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '2';
int_data <= (int_data * 10) + 2;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0011"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '3';
int_data <= (int_data * 10) + 3;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0100"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '4';
int_data <= (int_data * 10) + 4;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0101"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '5';
int_data <= (int_data * 10) + 5;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0110"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '6';
int_data <= (int_data * 10) + 6;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0111"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '7';
int_data <= (int_data * 10) + 7;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "1000"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '8';
int_data <= (int_data * 10) + 8;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "1001"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '9';
int_data <= (int_data * 10) + 9;
elsif output_string(3) /= ' ' and output_string(2) /= ' ' and output_string(1) = ' ' and keypad_input = "0000"
and (s_ascii_out = '1' and last_keypress_state = '0') then
output_string(1) <= '0';
int_data <= (int_data * 10) + 0;
end if;
last_add_state <= add;
last_subtract_state <= subtract;
last_divide_state <= divide;
last_enter_state <= enter;
last_keypress_state <= s_ascii_out;
--last_keypad_input_state <= keypad_input;
end if;
end process;
-- inputs
-- signals <= entity inputs
add <= add_input;
subtract <= subtract_input;
multiply <= multiply_input;
divide <= divide_input;
enter <= enter_input;
s_ascii_out <= s_ascii_out_input;
keypad_input <= input_keypad_input;
-- output
-- entity outputs <= signals
output_string_output <= output_string;
output_reg <= reg;
end Behavioral;
|
library IEEE;
use ieee.std_logic_1164.all;
entity MUX81_GENERIC is
generic(NBIT: integer);
Port( a:In std_logic_vector(NBIT-1 downto 0);
b: In std_logic_vector(NBIT-1 downto 0);
c: In std_logic_vector(NBIT-1 downto 0);
d: In std_logic_vector(NBIT-1 downto 0);
e: In std_logic_vector(NBIT-1 downto 0);
f: In std_logic_vector(NBIT-1 downto 0);
g: In std_logic_vector(NBIT-1 downto 0);
h: In std_logic_vector(NBIT-1 downto 0);
sel: In std_logic_vector(2 downto 0);
Y: Out std_logic_vector(NBIT-1 downto 0));
end entity;
architecture BEHAVIORAL of MUX81_GENERIC is
begin
process (a, b, c, d, e, f, g, h, sel)
begin
if sel="111" then Y <= a;
elsif sel="110" then Y<= b;
elsif sel="101" then Y <= c;
elsif sel="100" then Y <= d;
elsif sel="011" then Y <= e;
elsif sel="010" then Y<= f;
elsif sel="001" then Y <= g;
else Y <= h;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Multiformat Division and Square Root
-- Project :
-------------------------------------------------------------------------------
-- File : fp_divsqrt_multi.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : Integrated Systems Laboratory, ETH Zurich
-- Created : 2018-04-08
-- Last update: 2018-10-10
-- Platform : ModelSim (simulation), Synopsys (synthesis)
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2018 ETH Zurich and University of Bologna.
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License"); you may not use this file except in
-- compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-- or agreed to in writing, software, hardware and materials distributed under
-- this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the
-- specific language governing permissions and limitations under the License.
-------------------------------------------------------------------------------
library IEEE, work;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.fpnew_pkg.all;
use work.fpnew_fmts_pkg.all;
use work.fpnew_comps_pkg.all;
entity fp_divsqrt_multi is
generic (
FORMATS : activeFormats_t := (Active => (FP32 to FP16ALT => true, others => false),
Encoding => DEFAULTENCODING);
LATENCY : natural := 0;
TAG_WIDTH : natural := 0);
port (
Clk_CI : in std_logic;
Reset_RBI : in std_logic;
---------------------------------------------------------------------------
A_DI, B_DI : in std_logic_vector(MAXWIDTH(FORMATS)-1 downto 0);
ABox_SI, BBox_SI : in fmtLogic_t;
RoundMode_SI : in rvRoundingMode_t;
Op_SI : in fpOp_t;
OpMod_SI : in std_logic;
FpFmt_SI : in fpFmt_t;
Tag_DI : in std_logic_vector(TAG_WIDTH-1 downto 0);
PrecCtl_SI : in std_logic_vector(6 downto 0);
---------------------------------------------------------------------------
InValid_SI : in std_logic;
InReady_SO : out std_logic;
Flush_SI : in std_logic;
---------------------------------------------------------------------------
Z_DO : out std_logic_vector(MAXWIDTH(FORMATS)-1 downto 0);
Status_DO : out rvStatus_t;
Tag_DO : out std_logic_vector(TAG_WIDTH-1 downto 0);
Zext_SO : out std_logic;
---------------------------------------------------------------------------
OutValid_SO : out std_logic;
OutReady_SI : in std_logic);
end entity fp_divsqrt_multi;
architecture iterative_lei of fp_divsqrt_multi is
-----------------------------------------------------------------------------
-- Constant Definitions
-----------------------------------------------------------------------------
constant FP_WIDTH : natural := MAXWIDTH(FORMATS);
-----------------------------------------------------------------------------
-- Type Definitions
-----------------------------------------------------------------------------
type t_ffsmState is (IDLE, BUSY, HOLD);
type t_pipeDataSrc is (DIRECT, HOLDREG);
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
-- Input Handshaking
signal InReady_S : std_logic;
signal IsInFP8_S : boolean;
-- DivSqrt input side
signal DivValid_S, SqrtValid_S : std_logic;
signal DivSqrtReady_S : std_logic;
signal A_D, B_D : std_logic_vector(63 downto 0);
signal Fmt_S : std_logic_vector(1 downto 0);
-- DivSqrt output side
signal DivSqrtDone_S : std_logic;
signal DivSqrtResultPre_D : std_logic_vector(63 downto 0);
signal DivSqrtResult_D : std_logic_vector(Z_DO'range);
signal DivSqrtStatusSlv_D : std_logic_vector(4 downto 0);
signal DivSqrtStatus_D : rvStatus_t;
-- Tag buffer
signal CurrentTag_DP : std_logic_vector(TAG_WIDTH-1 downto 0);
signal IsOutFP8_SP : boolean;
-- Output holding
signal HoldResult_S : std_logic;
signal HoldResult_DP : std_logic_vector(Z_DO'range);
signal HoldStatus_DP : rvStatus_t;
-- Output pipelining
signal PipeInValid_S, PipeInReady_S : std_logic;
signal PipeInDataSel_S : t_pipeDataSrc;
signal PipeInResult_D : std_logic_vector(Z_DO'range);
signal PipeInStatus_D : rvStatus_t;
-- FSM states
signal State_DP, State_DN : t_ffsmState;
-----------------------------------------------------------------------------
-- Component Declarations
-----------------------------------------------------------------------------
component div_sqrt_top_mvp is
port (
Clk_CI : in std_logic;
Rst_RBI : in std_logic;
Div_start_SI : in std_logic;
Sqrt_start_SI : in std_logic;
Operand_a_DI : in std_logic_vector(63 downto 0);
Operand_b_DI : in std_logic_vector(63 downto 0);
RM_SI : in std_logic_vector(2 downto 0);
Precision_ctl_SI : in std_logic_vector(5 downto 0);
Format_sel_SI : in std_logic_vector(1 downto 0);
Kill_SI : in std_logic;
Result_DO : out std_logic_vector(63 downto 0);
Fflags_SO : out std_logic_vector(4 downto 0);
Ready_SO : out std_logic;
Done_SO : out std_logic);
end component div_sqrt_top_mvp;
begin -- architecture iterative_lei
-----------------------------------------------------------------------------
-- Input side signals
-----------------------------------------------------------------------------
-- Format encoding of unit
with FpFmt_SI select
Fmt_S <=
"00" when FP32,
"01" when FP64,
"10" when FP16,
"11" when FP16ALT,
"10" when others; -- map fp8 to fp16
IsInFP8_S <= FpFmt_SI = FP8;
-- Map FP8 onto FP16
A_D <= std_logic_vector(resize(unsigned(A_DI), 64) sll 8) when IsInFP8_S else
std_logic_vector(resize(unsigned(A_DI), 64));
B_D <= std_logic_vector(resize(unsigned(B_DI), 64) sll 8) when IsInFP8_S else
std_logic_vector(resize(unsigned(B_DI), 64));
-- Upstream ready given by FSM
InReady_SO <= InReady_S;
-----------------------------------------------------------------------------
-- Control
-----------------------------------------------------------------------------
-- Operation is only started when the control FSM is ready
DivValid_S <= InValid_SI and to_sl(Op_SI = DIV) and InReady_S and not Flush_SI;
SqrtValid_S <= InValid_SI and to_sl(Op_SI /= DIV) and InReady_S and not Flush_SI;
-- FSM process
p_flagFSM : process (all) is
begin
-- Default Assignments
InReady_S <= '0';
PipeInValid_S <= '0';
PipeInDataSel_S <= DIRECT; -- Divsqrt feeds pipeline directly
HoldResult_S <= '0'; -- Don't save divsqrt output to hold
State_DN <= State_DP; -- By default, stay in the same state
-- FSM
case State_DP is
-- Waiting for work
when IDLE =>
InReady_S <= '1'; -- We're ready
-- New work arrives
-- if (DivValid_S or SqrtValid_S) = '1' then
if ((DivValid_S or SqrtValid_S) and DivSqrtReady_S) = '1' then
State_DN <= BUSY;
end if;
-- Operation in progress
when BUSY =>
-- Wait until divsqrt is done
if DivSqrtDone_S = '1' then
PipeInValid_S <= '1'; -- Apply outputs to Pipeline
-- The result will be processed downstream
if PipeInReady_S = '1' then
State_DN <= IDLE; -- We can go back to idling
-- ..unless there is another incoming instruction
-- if InValid_SI = '1' then
if (InValid_SI and DivSqrtReady_S) = '1' then
InReady_S <= '1'; -- We take the next instruction
State_DN <= BUSY; -- And stay busy with it
end if;
-- The downstream pipeline is not ready for us
else
HoldResult_S <= '1'; -- Activate the hold register
State_DN <= HOLD; -- Wait until the pipeline is unstuck
end if;
end if;
-- Holding data for output pipe
when HOLD =>
PipeInDataSel_S <= HOLDREG; -- Apply data from hold reg to pipe
PipeInValid_S <= '1'; -- We have valid data
-- Wait until result will be processed downstream
if PipeInReady_S = '1' then
State_DN <= IDLE; -- We can go back to idling
-- ..unless there is another incoming instruction
-- if InValid_SI = '1' then
if (InValid_SI and DivSqrtReady_S) = '1' then
InReady_S <= '1'; -- We take the next instruction
State_DN <= BUSY; -- And stay busy with it
end if;
end if;
end case;
-- Flushing overrides the other actions
if Flush_SI = '1' then
PipeInValid_S <= '0'; -- Don't commit to pipe
State_DN <= IDLE; -- Go back to default state
end if;
end process p_flagFSM;
-----------------------------------------------------------------------------
-- Instance of multifmt div/sqrt unit
-----------------------------------------------------------------------------
i_fp_divsqrt : div_sqrt_top_mvp
port map (
Clk_CI => Clk_CI,
Rst_RBI => Reset_RBI,
Div_start_SI => DivValid_S,
Sqrt_start_SI => SqrtValid_S,
Operand_a_DI => A_D,
Operand_b_DI => B_D,
RM_SI => to_slv(RoundMode_SI),
Precision_ctl_SI => PrecCtl_SI(5 downto 0),
Format_sel_SI => Fmt_S,
Kill_SI => Flush_SI,
Result_DO => DivSqrtResultPre_D,
Fflags_SO => DivSqrtStatusSlv_D,
Ready_SO => DivSqrtReady_S,
Done_SO => DivSqrtDone_S);
DivSqrtResult_D <= std_logic_vector(resize(unsigned(DivSqrtResultPre_D), Z_DO'length) srl 8) when IsOutFP8_SP else
std_logic_vector(resize(unsigned(DivSqrtResultPre_D), Z_DO'length));
DivSqrtStatus_D <= to_rvStatus(DivSqrtStatusSlv_D);
-----------------------------------------------------------------------------
-- Tag Buffer and output hold register, also FSM state keeping
-----------------------------------------------------------------------------
p_registers : process (Clk_CI, Reset_RBI) is
begin -- process p_tagBuffer
if Reset_RBI = '0' then -- asynchronous reset (active low)
--FSM state--------------------------------------------------------------
State_DP <= IDLE;
--Tag Buffer-------------------------------------------------------------
CurrentTag_DP <= (others => '0');
IsOutFP8_SP <= false;
--Hold Register----------------------------------------------------------
HoldResult_DP <= (others => '0');
HoldStatus_DP <= (others => '0');
elsif Clk_CI'event and Clk_CI = '1' then -- rising clock edge
-- Advance FSM state
State_DP <= State_DN;
-- Only store tag if a new operation starts
if (DivValid_S or SqrtValid_S) = '1' then
CurrentTag_DP <= Tag_DI;
IsOutFP8_SP <= IsInFP8_S;
end if;
-- Hold register is enabled if needed
if HoldResult_S = '1' then
HoldResult_DP <= DivSqrtResult_D;
HoldStatus_DP <= DivSqrtStatus_D;
end if;
end if;
end process p_registers;
-----------------------------------------------------------------------------
-- Pipeline registers at the outputs of the unit
-----------------------------------------------------------------------------
PipeInResult_D <= HoldResult_DP when PipeInDataSel_S = HOLDREG else DivSqrtResult_D;
PipeInStatus_D <= HoldStatus_DP when PipeInDataSel_S = HOLDREG else DivSqrtStatus_D;
i_fp_pipe : fp_pipe
generic map (
WIDTH => FP_WIDTH,
LATENCY => LATENCY,
TAG_WIDTH => TAG_WIDTH)
port map (
Clk_CI => Clk_CI,
Reset_RBI => Reset_RBI,
Result_DI => PipeInResult_D,
Status_DI => PipeInStatus_D,
Tag_DI => CurrentTag_DP,
InValid_SI => PipeInValid_S,
InReady_SO => PipeInReady_S,
Flush_SI => Flush_SI,
ResultPiped_DO => Z_DO,
StatusPiped_DO => Status_DO,
TagPiped_DO => Tag_DO,
OutValid_SO => OutValid_SO,
OutReady_SI => OutReady_SI);
Zext_SO <= '0'; -- always NaN-box
end architecture iterative_lei;
|
<gh_stars>0
-----------------------------
--! @author <NAME>
--! @date 18.03.2021
--! @file delay_line.vhd
--! @version C
--! @copyright Copyright (c) 2021 <NAME>
--!
--! @brief Project name: Delay line
--! Module name: Delay line module
--!
--! @details Delay line module for Xilinx 7 series. Its length can be configurable from the top module.
--! The Delay line consists of MUXes(CARRY4 primitives) and D flip Flops at the output.
--! -------------------------------------------------------------
--! ***CARRY4*** (description from *Xilinx 7 Series FPGA Libraries Guide for HDL Designs*)
--! Primitive: Fast Carry Logic with Look Ahead
--! **Introduction**
--! This circuit design represents the fast carry logic for a slice. The carry chain consists of a series of four MUXes
--! and four XORs that connect to the other logic (LUTs) in the slice via dedicated routes to form more complex
--! functions. The fast carry logic is useful for building arithmetic functions like adders, counters, subtractors and
--! add/subs, as well as such other logic functions as wide comparators, address decoders, and some logic gates
--! (specifically, AND and OR).
--! **Port Descriptions**
--! ```
--! | Port | Direction | Width | Function |
--! | ------ | --------- | ----- | ------------------------------------------ |
--! | O | Output | 4 | Carry chain XOR general data out |
--! | CO | Output | 4 | Carry-out of each stage of the carry chain |
--! | DI | Input | 4 | Carry-MUX data input |
--! | S | Input | 4 | Carry-MUX select line |
--! | CYINIT | Input | 1 | Carry-in initialization input |
--! | CI | Input | 1 | Carry cascade input |
--! ```
--! -------------------------------------------------------------
--! **Revision:**
--! A - initial design
--! B - Long delay line test without D-Flip-Flops
--! C - Add XOR output and nReset input
--! D -
--! -----------------------------
LIBRARY IEEE; --always use this library
USE ieee.std_logic_unsigned.ALL; --extends the std_logic_arith library
USE ieee.std_logic_arith.ALL; --basic arithmetic operations for representing integers in standard ways
USE IEEE.numeric_std.ALL; --use this library if arithmetic required
USE IEEE.std_logic_1164.ALL; --always use this library
LIBRARY UNISIM; -- Xilinx primitive
USE UNISIM.vcomponents.ALL; -- Xilinx primitive
ENTITY delay_line IS
GENERIC (
g_DL_ELEMENT_COUNT : INTEGER := 16; --! Count of delay elements in the module. Four delay elements are in one CARRY4 primitive. The minimal number of CARRY4 blocks are 2, e.i. minimal delay element count are 2*4=8.
g_LOCATION : STRING := "SLICE_X1Y1" --! Location of the first CARRY4 block
);
PORT (
i_clk : IN STD_LOGIC; --! Main clock for D-Flip-Flops
i_trigger_in : IN STD_LOGIC; --! Input of delay line
o_dff_q : OUT STD_LOGIC_VECTOR(g_DL_ELEMENT_COUNT - 1 DOWNTO 0); -- thermometer time code
i_D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --! DI for CARRY4 block
i_S : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --! S for CARRY4 block
o_loop_out : OUT STD_LOGIC; --! Output of delay line
i_nReset : IN std_logic; --! Synchronous reset input for D-Flip-Flops
i_clock_enable: IN std_logic --! Clock enable input for D-Flip-Flops
);
END delay_line;
--define inside of the module
ARCHITECTURE rtl OF delay_line IS
--define components to use
SIGNAL w_CO : STD_LOGIC_VECTOR(g_DL_ELEMENT_COUNT - 1 DOWNTO 0) := (OTHERS => '0'); --! CO vector from Carry-out of each stage of the carry chain
SIGNAL w_O : STD_LOGIC_VECTOR(g_DL_ELEMENT_COUNT - 1 DOWNTO 0) := (OTHERS => '0'); --! CO vector from Carry-out of each stage of the carry chain
-- Preserve the hierarchy of instance CARRY4
ATTRIBUTE KEEP_HIERARCHY : STRING;
ATTRIBUTE KEEP_HIERARCHY OF CARRY4_first : LABEL IS "TRUE";
ATTRIBUTE KEEP_HIERARCHY OF CARRY4_last : LABEL IS "TRUE";
-- Designates instantiated register instance CARRY4 to be placed
-- in SLICE site SLICE_X0Y0
ATTRIBUTE LOC : STRING;
ATTRIBUTE LOC OF CARRY4_first : LABEL IS g_LOCATION;
ATTRIBUTE keep : STRING;
ATTRIBUTE keep OF i_clk : SIGNAL IS "true";
ATTRIBUTE keep OF i_trigger_in : SIGNAL IS "true";
ATTRIBUTE keep OF w_CO : SIGNAL IS "true";
ATTRIBUTE keep OF w_O : SIGNAL IS "true";
ATTRIBUTE keep OF o_dff_q : SIGNAL IS "true";
BEGIN
--------------------------------------------------------------------------
--! CARRY4: Fast Carry Logic Component
--! 7 Series
--! Xilinx HDL Libraries Guide, version 2012.2
CARRY4_first : CARRY4 PORT MAP(
CO => w_CO(3 DOWNTO 0), --! 4-bit carry out
O => w_O(3 DOWNTO 0), --! 4-bit carry chain XOR data out
CI => '0', --! 1-bit carry cascade input
CYINIT => i_trigger_in, --! 1-bit carry initialization
DI => i_D, --! 4-bit carry-MUX data in
S => i_S --! 4-bit carry-MUX select input
);
CARRY4_gen : FOR I IN 1 TO (g_DL_ELEMENT_COUNT/4) - 2 GENERATE CARRY4_inst_next : COMPONENT CARRY4
PORT MAP(
CO => w_CO(I * 4 + 3 DOWNTO I * 4), -- 4-bit carry out
O => w_O(I * 4 + 3 DOWNTO I * 4), -- 4-bit carry chain XOR data out
CI => w_CO(I * 4 - 1), -- 1-bit carry cascade input
CYINIT => '0', -- 1-bit carry initialization
DI => i_D, -- 4-bit carry-MUX data in
S => i_S -- 4-bit carry-MUX select input
);
END GENERATE;
--! CARRY4: Fast Carry Logic Component
CARRY4_last : CARRY4 PORT MAP(
CO => w_CO(g_DL_ELEMENT_COUNT - 1 DOWNTO g_DL_ELEMENT_COUNT - 4), -- 4-bit carry out
O => w_O(g_DL_ELEMENT_COUNT - 1 DOWNTO g_DL_ELEMENT_COUNT - 4), -- 4-bit carry chain XOR data out
CI => w_CO(g_DL_ELEMENT_COUNT - 4 - 1), -- 1-bit carry cascade input
CYINIT => '0', -- 1-bit carry initialization
DI => i_D, -- 4-bit carry-MUX data in
S => i_S -- 4-bit carry-MUX select input
);
-- End_of_CARRY4_inst instantiation
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--! FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
--! Clock Enable (pos_edge clk).
--! 7 Series
--! Xilinx HDL Libraries Guide, version 2012.2
DFF_CO_gen : FOR I IN 0 TO g_DL_ELEMENT_COUNT - 1 GENERATE FDRE_inst : COMPONENT FDRE
generic map (
INIT => '0') --! Initial value of register ('0' or '1')
PORT MAP(
Q => o_dff_q(I), --! Data output
C => i_clk, --! Clock input
CE => i_clock_enable, --! Clock enable input
R => i_nReset, --! Synchronous reset input
D => w_CO(I) --! Data input
);
END GENERATE;
-- End of FDRE_inst instantiation
--------------------------------------------------------------------------------
---------------------------------------------------------------------------
--! FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
--! Clock Enable (pos_edge clk).
--! 7 Series
--! Xilinx HDL Libraries Guide, version 2012.2
DFF_O_gen : FOR I IN 0 TO g_DL_ELEMENT_COUNT - 1 GENERATE FDRE_inst : COMPONENT FDRE
generic map (
INIT => '0') --! Initial value of register ('0' or '1')
PORT MAP(
-- Q => o_dff_q(I), --! Data output
C => i_clk, --! Clock input
CE => i_clock_enable, --! Clock enable input
R => i_nReset, --! Synchronous reset input
D => w_O(I) --! Data input
);
END GENERATE;
-- End of FDRE_inst instantiation
--------------------------------------------------------------------------------
o_loop_out <= w_CO(g_DL_ELEMENT_COUNT - 1); --! last element of delay line
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity tb_Klok is
end tb_Klok;
architecture tb of tb_Klok is
component VGA
port (CLK : in std_logic;
BTNL: in std_logic;
BTNR: in std_logic;
BTNU: in std_logic;
BTND: in std_logic;
BTNC: in std_logic );
end component;
signal simClock: std_logic:='0';
signal L: std_logic:='0';
signal R: std_logic:='0';
signal U: std_logic:='0';
signal D: std_logic:='0';
signal C: std_logic:='0';
begin
dut : VGA
port map (
CLK => simClock,
BTNL => L,
BTNR => R,
BTND => D,
BTNU => U,
BTNC => C
);
stimuli : process
begin
L <= '0';
R <= '0';
U <= '0';
D <= '0';
C <= '0';
LoopClock: while(true)loop
simClock <= not(simClock);
wait for 5 ns; --periode wordt 10ns => 100Mhz
end loop;
end process;
end tb;
|
--------------------------------------------------------------------------------
-- __ _ _ _ --
-- / _(_) | | | | --
-- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | --
-- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | --
-- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | --
-- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| --
-- | | --
-- |_| --
-- --
-- --
-- Peripheral-NTM for MPSoC --
-- Neural Turing Machine for MPSoC --
-- --
--------------------------------------------------------------------------------
-- Copyright (c) 2020-2021 by the author(s)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--------------------------------------------------------------------------------
-- Author(s):
-- <NAME> <<EMAIL>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ntm_arithmetic_pkg.all;
use work.ntm_integer_pkg.all;
entity ntm_integer_stimulus is
generic (
-- SYSTEM-SIZE
DATA_SIZE : integer := 32;
CONTROL_SIZE : integer := 64;
X : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- x in 0 to X-1
Y : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- y in 0 to Y-1
N : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- j in 0 to N-1
W : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- k in 0 to W-1
L : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- l in 0 to L-1
R : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)) -- i in 0 to R-1
);
port (
-- GLOBAL
CLK : out std_logic;
RST : out std_logic;
-----------------------------------------------------------------------
-- STIMULUS SCALAR
-----------------------------------------------------------------------
-- SCALAR ADDER
-- CONTROL
SCALAR_INTEGER_ADDER_START : out std_logic;
SCALAR_INTEGER_ADDER_READY : in std_logic;
SCALAR_INTEGER_ADDER_OPERATION : out std_logic;
-- DATA
SCALAR_INTEGER_ADDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_ADDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_ADDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_ADDER_OVERFLOW_OUT : in std_logic;
-- SCALAR MULTIPLIER
-- CONTROL
SCALAR_INTEGER_MULTIPLIER_START : out std_logic;
SCALAR_INTEGER_MULTIPLIER_READY : in std_logic;
-- DATA
SCALAR_INTEGER_MULTIPLIER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_MULTIPLIER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_MULTIPLIER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_MULTIPLIER_OVERFLOW_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
-- SCALAR DIVIDER
-- CONTROL
SCALAR_INTEGER_DIVIDER_START : out std_logic;
SCALAR_INTEGER_DIVIDER_READY : in std_logic;
-- DATA
SCALAR_INTEGER_DIVIDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_DIVIDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_DIVIDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
SCALAR_INTEGER_DIVIDER_REMAINDER_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
-----------------------------------------------------------------------
-- STIMULUS VECTOR
-----------------------------------------------------------------------
-- VECTOR ADDER
-- CONTROL
VECTOR_INTEGER_ADDER_START : out std_logic;
VECTOR_INTEGER_ADDER_READY : in std_logic;
VECTOR_INTEGER_ADDER_OPERATION : out std_logic;
VECTOR_INTEGER_ADDER_DATA_A_IN_ENABLE : out std_logic;
VECTOR_INTEGER_ADDER_DATA_B_IN_ENABLE : out std_logic;
VECTOR_INTEGER_ADDER_DATA_OUT_ENABLE : in std_logic;
-- DATA
VECTOR_INTEGER_ADDER_SIZE_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
VECTOR_INTEGER_ADDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_ADDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_ADDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_ADDER_OVERFLOW_OUT : in std_logic;
-- VECTOR MULTIPLIER
-- CONTROL
VECTOR_INTEGER_MULTIPLIER_START : out std_logic;
VECTOR_INTEGER_MULTIPLIER_READY : in std_logic;
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN_ENABLE : out std_logic;
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN_ENABLE : out std_logic;
VECTOR_INTEGER_MULTIPLIER_DATA_OUT_ENABLE : in std_logic;
-- DATA
VECTOR_INTEGER_MULTIPLIER_SIZE_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_MULTIPLIER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_MULTIPLIER_OVERFLOW_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
-- VECTOR DIVIDER
-- CONTROL
VECTOR_INTEGER_DIVIDER_START : out std_logic;
VECTOR_INTEGER_DIVIDER_READY : in std_logic;
VECTOR_INTEGER_DIVIDER_DATA_A_IN_ENABLE : out std_logic;
VECTOR_INTEGER_DIVIDER_DATA_B_IN_ENABLE : out std_logic;
VECTOR_INTEGER_DIVIDER_DATA_OUT_ENABLE : in std_logic;
-- DATA
VECTOR_INTEGER_DIVIDER_SIZE_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
VECTOR_INTEGER_DIVIDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_DIVIDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_DIVIDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
VECTOR_INTEGER_DIVIDER_REMAINDER_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
-----------------------------------------------------------------------
-- STIMULUS MATRIX
-----------------------------------------------------------------------
-- MATRIX ADDER
-- CONTROL
MATRIX_INTEGER_ADDER_START : out std_logic;
MATRIX_INTEGER_ADDER_READY : in std_logic;
MATRIX_INTEGER_ADDER_OPERATION : out std_logic;
MATRIX_INTEGER_ADDER_DATA_A_IN_I_ENABLE : out std_logic;
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE : out std_logic;
MATRIX_INTEGER_ADDER_DATA_B_IN_I_ENABLE : out std_logic;
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE : out std_logic;
MATRIX_INTEGER_ADDER_DATA_OUT_I_ENABLE : in std_logic;
MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE : in std_logic;
-- DATA
MATRIX_INTEGER_ADDER_SIZE_I_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
MATRIX_INTEGER_ADDER_SIZE_J_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
MATRIX_INTEGER_ADDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_ADDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_ADDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_ADDER_OVERFLOW_OUT : in std_logic;
-- MATRIX MULTIPLIER
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_START : out std_logic;
MATRIX_INTEGER_MULTIPLIER_READY : in std_logic;
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE : out std_logic;
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE : out std_logic;
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE : out std_logic;
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE : out std_logic;
MATRIX_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE : in std_logic;
MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE : in std_logic;
-- DATA
MATRIX_INTEGER_MULTIPLIER_SIZE_I_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_MULTIPLIER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_MULTIPLIER_OVERFLOW_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
-- MATRIX DIVIDER
-- CONTROL
MATRIX_INTEGER_DIVIDER_START : out std_logic;
MATRIX_INTEGER_DIVIDER_READY : in std_logic;
MATRIX_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE : out std_logic;
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE : out std_logic;
MATRIX_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE : out std_logic;
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE : out std_logic;
MATRIX_INTEGER_DIVIDER_DATA_OUT_I_ENABLE : in std_logic;
MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE : in std_logic;
-- DATA
MATRIX_INTEGER_DIVIDER_SIZE_I_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
MATRIX_INTEGER_DIVIDER_SIZE_J_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
MATRIX_INTEGER_DIVIDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_DIVIDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_DIVIDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
MATRIX_INTEGER_DIVIDER_REMAINDER_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
-----------------------------------------------------------------------
-- STIMULUS TENSOR
-----------------------------------------------------------------------
-- TENSOR ADDER
-- CONTROL
TENSOR_INTEGER_ADDER_START : out std_logic;
TENSOR_INTEGER_ADDER_READY : in std_logic;
TENSOR_INTEGER_ADDER_OPERATION : out std_logic;
TENSOR_INTEGER_ADDER_DATA_A_IN_I_ENABLE : out std_logic;
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE : out std_logic;
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE : out std_logic;
TENSOR_INTEGER_ADDER_DATA_B_IN_I_ENABLE : out std_logic;
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE : out std_logic;
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE : out std_logic;
TENSOR_INTEGER_ADDER_DATA_OUT_I_ENABLE : in std_logic;
TENSOR_INTEGER_ADDER_DATA_OUT_J_ENABLE : in std_logic;
TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE : in std_logic;
-- DATA
TENSOR_INTEGER_ADDER_SIZE_I_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_ADDER_SIZE_J_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_ADDER_SIZE_K_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_ADDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_ADDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_ADDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_ADDER_OVERFLOW_OUT : in std_logic;
-- TENSOR MULTIPLIER
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_START : out std_logic;
TENSOR_INTEGER_MULTIPLIER_READY : in std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE : out std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE : out std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE : out std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE : out std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE : out std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE : out std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE : in std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE : in std_logic;
TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE : in std_logic;
-- DATA
TENSOR_INTEGER_MULTIPLIER_SIZE_I_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_MULTIPLIER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_MULTIPLIER_OVERFLOW_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
-- TENSOR DIVIDER
-- CONTROL
TENSOR_INTEGER_DIVIDER_START : out std_logic;
TENSOR_INTEGER_DIVIDER_READY : in std_logic;
TENSOR_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE : out std_logic;
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE : out std_logic;
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE : out std_logic;
TENSOR_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE : out std_logic;
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE : out std_logic;
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE : out std_logic;
TENSOR_INTEGER_DIVIDER_DATA_OUT_I_ENABLE : in std_logic;
TENSOR_INTEGER_DIVIDER_DATA_OUT_J_ENABLE : in std_logic;
TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE : in std_logic;
-- DATA
TENSOR_INTEGER_DIVIDER_SIZE_I_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_DIVIDER_SIZE_J_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_DIVIDER_SIZE_K_IN : out std_logic_vector(CONTROL_SIZE-1 downto 0);
TENSOR_INTEGER_DIVIDER_DATA_A_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_DIVIDER_DATA_B_IN : out std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_DIVIDER_DATA_OUT : in std_logic_vector(DATA_SIZE-1 downto 0);
TENSOR_INTEGER_DIVIDER_REMAINDER_OUT : in std_logic_vector(DATA_SIZE-1 downto 0)
);
end entity;
architecture ntm_integer_stimulus_architecture of ntm_integer_stimulus is
-----------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------
constant PERIOD : time := 10 ns;
constant WAITING : time := 50 ns;
constant WORKING : time := 1 ms;
constant ZERO_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(0, CONTROL_SIZE));
constant ONE_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(1, CONTROL_SIZE));
constant TWO_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(2, CONTROL_SIZE));
constant THREE_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(3, CONTROL_SIZE));
constant ZERO_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(0, DATA_SIZE));
constant ONE_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(1, DATA_SIZE));
constant TWO_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(2, DATA_SIZE));
constant THREE_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(3, DATA_SIZE));
constant FULL : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '1');
constant EMPTY : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
constant EULER : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------
-- LOOP
signal index_i_loop : std_logic_vector(CONTROL_SIZE-1 downto 0);
signal index_j_loop : std_logic_vector(CONTROL_SIZE-1 downto 0);
signal index_k_loop : std_logic_vector(CONTROL_SIZE-1 downto 0);
-- GLOBAL
signal clk_int : std_logic;
signal rst_int : std_logic;
-- CONTROL
signal start_int : std_logic;
begin
-----------------------------------------------------------------------
-- Body
-----------------------------------------------------------------------
-- clk generation
clk_process : process
begin
clk_int <= '1';
wait for PERIOD/2;
clk_int <= '0';
wait for PERIOD/2;
end process;
CLK <= clk_int;
-- rst generation
rst_process : process
begin
rst_int <= '0';
wait for WAITING;
rst_int <= '1';
wait for WORKING;
end process;
RST <= rst_int;
-- start generation
start_process : process
begin
start_int <= '0';
wait for WAITING;
start_int <= '1';
wait for PERIOD;
start_int <= '0';
wait for WORKING;
end process;
-- SCALAR-FUNCTIONALITY
SCALAR_INTEGER_ADDER_START <= start_int;
SCALAR_INTEGER_MULTIPLIER_START <= start_int;
SCALAR_INTEGER_DIVIDER_START <= start_int;
-- VECTOR-FUNCTIONALITY
VECTOR_INTEGER_ADDER_START <= start_int;
VECTOR_INTEGER_MULTIPLIER_START <= start_int;
VECTOR_INTEGER_DIVIDER_START <= start_int;
-- MATRIX-FUNCTIONALITY
MATRIX_INTEGER_ADDER_START <= start_int;
MATRIX_INTEGER_MULTIPLIER_START <= start_int;
MATRIX_INTEGER_DIVIDER_START <= start_int;
-- TENSOR-FUNCTIONALITY
TENSOR_INTEGER_ADDER_START <= start_int;
TENSOR_INTEGER_MULTIPLIER_START <= start_int;
TENSOR_INTEGER_DIVIDER_START <= start_int;
-----------------------------------------------------------------------
-- STIMULUS
-----------------------------------------------------------------------
main_test : process
begin
-------------------------------------------------------------------
-- SCALAR-INTEGER
-------------------------------------------------------------------
if (STIMULUS_NTM_SCALAR_INTEGER_ADDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_SCALAR_ADDER_TEST ";
-------------------------------------------------------------------
-- CONTROL
SCALAR_INTEGER_ADDER_OPERATION <= '0';
if (STIMULUS_NTM_SCALAR_INTEGER_ADDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_SCALAR_ADDER_CASE 0 ";
-------------------------------------------------------------------
SCALAR_INTEGER_ADDER_DATA_A_IN <= SCALAR_SAMPLE_A;
SCALAR_INTEGER_ADDER_DATA_B_IN <= SCALAR_SAMPLE_B;
end if;
if (STIMULUS_NTM_SCALAR_INTEGER_ADDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_SCALAR_ADDER_CASE 1 ";
-------------------------------------------------------------------
SCALAR_INTEGER_ADDER_DATA_A_IN <= SCALAR_SAMPLE_B;
SCALAR_INTEGER_ADDER_DATA_B_IN <= SCALAR_SAMPLE_A;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_SCALAR_INTEGER_MULTIPLIER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_SCALAR_MULTIPLIER_TEST ";
-------------------------------------------------------------------
if (STIMULUS_NTM_SCALAR_INTEGER_MULTIPLIER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_SCALAR_MULTIPLIER_CASE 0 ";
-------------------------------------------------------------------
SCALAR_INTEGER_MULTIPLIER_DATA_A_IN <= SCALAR_SAMPLE_A;
SCALAR_INTEGER_MULTIPLIER_DATA_B_IN <= SCALAR_SAMPLE_B;
end if;
if (STIMULUS_NTM_SCALAR_INTEGER_MULTIPLIER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_SCALAR_MULTIPLIER_CASE 1 ";
-------------------------------------------------------------------
SCALAR_INTEGER_MULTIPLIER_DATA_A_IN <= SCALAR_SAMPLE_B;
SCALAR_INTEGER_MULTIPLIER_DATA_B_IN <= SCALAR_SAMPLE_A;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_SCALAR_INTEGER_DIVIDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_SCALAR_DIVIDER_TEST ";
-------------------------------------------------------------------
if (STIMULUS_NTM_SCALAR_INTEGER_DIVIDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_SCALAR_DIVIDER_CASE 0 ";
-------------------------------------------------------------------
SCALAR_INTEGER_DIVIDER_DATA_A_IN <= SCALAR_SAMPLE_A;
SCALAR_INTEGER_DIVIDER_DATA_B_IN <= SCALAR_SAMPLE_B;
end if;
if (STIMULUS_NTM_SCALAR_INTEGER_DIVIDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_SCALAR_DIVIDER_CASE 1 ";
-------------------------------------------------------------------
SCALAR_INTEGER_DIVIDER_DATA_A_IN <= SCALAR_SAMPLE_B;
SCALAR_INTEGER_DIVIDER_DATA_B_IN <= SCALAR_SAMPLE_A;
end if;
wait for WORKING;
end if;
-------------------------------------------------------------------
-- VECTOR-INTEGER
-------------------------------------------------------------------
if (STIMULUS_NTM_VECTOR_INTEGER_ADDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_VECTOR_ADDER_TEST ";
-------------------------------------------------------------------
-- CONTROL
VECTOR_INTEGER_ADDER_OPERATION <= '0';
-- DATA
VECTOR_INTEGER_ADDER_SIZE_IN <= THREE_CONTROL;
if (STIMULUS_NTM_VECTOR_INTEGER_ADDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_VECTOR_ADDER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
VECTOR_INTEGER_ADDER_DATA_A_IN <= ZERO_DATA;
VECTOR_INTEGER_ADDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
VECTOR_INTEGER_ADDER_FIRST_RUN : loop
if (VECTOR_INTEGER_ADDER_DATA_OUT_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(VECTOR_INTEGER_ADDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_ADDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_ADDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_ADDER_DATA_A_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_ADDER_DATA_B_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= ZERO_CONTROL;
elsif ((VECTOR_INTEGER_ADDER_DATA_OUT_ENABLE = '1' or VECTOR_INTEGER_ADDER_START = '1') and (unsigned(index_i_loop) < unsigned(VECTOR_INTEGER_ADDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_ADDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_ADDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_ADDER_DATA_A_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_ADDER_DATA_B_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
else
-- CONTROL
VECTOR_INTEGER_ADDER_DATA_A_IN_ENABLE <= '0';
VECTOR_INTEGER_ADDER_DATA_B_IN_ENABLE <= '0';
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit VECTOR_INTEGER_ADDER_FIRST_RUN when VECTOR_INTEGER_ADDER_READY = '1';
end loop VECTOR_INTEGER_ADDER_FIRST_RUN;
end if;
if (STIMULUS_NTM_VECTOR_INTEGER_ADDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_VECTOR_ADDER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
VECTOR_INTEGER_ADDER_DATA_A_IN <= ZERO_DATA;
VECTOR_INTEGER_ADDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
VECTOR_INTEGER_ADDER_SECOND_RUN : loop
if (VECTOR_INTEGER_ADDER_DATA_OUT_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(VECTOR_INTEGER_ADDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_ADDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_ADDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_ADDER_DATA_A_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_ADDER_DATA_B_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= ZERO_CONTROL;
elsif ((VECTOR_INTEGER_ADDER_DATA_OUT_ENABLE = '1' or VECTOR_INTEGER_ADDER_START = '1') and (unsigned(index_i_loop) < unsigned(VECTOR_INTEGER_ADDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_ADDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_ADDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_ADDER_DATA_A_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_ADDER_DATA_B_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
else
-- CONTROL
VECTOR_INTEGER_ADDER_DATA_A_IN_ENABLE <= '0';
VECTOR_INTEGER_ADDER_DATA_B_IN_ENABLE <= '0';
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit VECTOR_INTEGER_ADDER_SECOND_RUN when VECTOR_INTEGER_ADDER_READY = '1';
end loop VECTOR_INTEGER_ADDER_SECOND_RUN;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_VECTOR_INTEGER_MULTIPLIER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_VECTOR_MULTIPLIER_TEST ";
-------------------------------------------------------------------
-- DATA
VECTOR_INTEGER_MULTIPLIER_SIZE_IN <= THREE_CONTROL;
if (STIMULUS_NTM_VECTOR_INTEGER_MULTIPLIER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_VECTOR_MULTIPLIER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN <= ZERO_DATA;
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
VECTOR_INTEGER_MULTIPLIER_FIRST_RUN : loop
if (VECTOR_INTEGER_MULTIPLIER_DATA_OUT_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(VECTOR_INTEGER_MULTIPLIER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= ZERO_CONTROL;
elsif ((VECTOR_INTEGER_MULTIPLIER_DATA_OUT_ENABLE = '1' or VECTOR_INTEGER_MULTIPLIER_START = '1') and (unsigned(index_i_loop) < unsigned(VECTOR_INTEGER_MULTIPLIER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
else
-- CONTROL
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN_ENABLE <= '0';
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN_ENABLE <= '0';
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit VECTOR_INTEGER_MULTIPLIER_FIRST_RUN when VECTOR_INTEGER_MULTIPLIER_READY = '1';
end loop VECTOR_INTEGER_MULTIPLIER_FIRST_RUN;
end if;
if (STIMULUS_NTM_VECTOR_INTEGER_MULTIPLIER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_VECTOR_MULTIPLIER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN <= ZERO_DATA;
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
VECTOR_INTEGER_MULTIPLIER_SECOND_RUN : loop
if (VECTOR_INTEGER_MULTIPLIER_DATA_OUT_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(VECTOR_INTEGER_MULTIPLIER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= ZERO_CONTROL;
elsif ((VECTOR_INTEGER_MULTIPLIER_DATA_OUT_ENABLE = '1' or VECTOR_INTEGER_MULTIPLIER_START = '1') and (unsigned(index_i_loop) < unsigned(VECTOR_INTEGER_MULTIPLIER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
else
-- CONTROL
VECTOR_INTEGER_MULTIPLIER_DATA_A_IN_ENABLE <= '0';
VECTOR_INTEGER_MULTIPLIER_DATA_B_IN_ENABLE <= '0';
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit VECTOR_INTEGER_MULTIPLIER_SECOND_RUN when VECTOR_INTEGER_MULTIPLIER_READY = '1';
end loop VECTOR_INTEGER_MULTIPLIER_SECOND_RUN;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_VECTOR_INTEGER_DIVIDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_VECTOR_DIVIDER_TEST ";
-------------------------------------------------------------------
-- DATA
VECTOR_INTEGER_DIVIDER_SIZE_IN <= THREE_CONTROL;
if (STIMULUS_NTM_VECTOR_INTEGER_DIVIDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_VECTOR_DIVIDER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
VECTOR_INTEGER_DIVIDER_DATA_A_IN <= ZERO_DATA;
VECTOR_INTEGER_DIVIDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
VECTOR_INTEGER_DIVIDER_FIRST_RUN : loop
if (VECTOR_INTEGER_DIVIDER_DATA_OUT_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(VECTOR_INTEGER_DIVIDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_DIVIDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_DIVIDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_DIVIDER_DATA_A_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_DIVIDER_DATA_B_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= ZERO_CONTROL;
elsif ((VECTOR_INTEGER_DIVIDER_DATA_OUT_ENABLE = '1' or VECTOR_INTEGER_DIVIDER_START = '1') and (unsigned(index_i_loop) < unsigned(VECTOR_INTEGER_DIVIDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_DIVIDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_DIVIDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_DIVIDER_DATA_A_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_DIVIDER_DATA_B_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
else
-- CONTROL
VECTOR_INTEGER_DIVIDER_DATA_A_IN_ENABLE <= '0';
VECTOR_INTEGER_DIVIDER_DATA_B_IN_ENABLE <= '0';
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit VECTOR_INTEGER_DIVIDER_FIRST_RUN when VECTOR_INTEGER_DIVIDER_READY = '1';
end loop VECTOR_INTEGER_DIVIDER_FIRST_RUN;
end if;
if (STIMULUS_NTM_VECTOR_INTEGER_DIVIDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_VECTOR_DIVIDER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
VECTOR_INTEGER_DIVIDER_DATA_A_IN <= ZERO_DATA;
VECTOR_INTEGER_DIVIDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
VECTOR_INTEGER_DIVIDER_SECOND_RUN : loop
if (VECTOR_INTEGER_DIVIDER_DATA_OUT_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(VECTOR_INTEGER_DIVIDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_DIVIDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_DIVIDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_DIVIDER_DATA_A_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_DIVIDER_DATA_B_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= ZERO_CONTROL;
elsif ((VECTOR_INTEGER_DIVIDER_DATA_OUT_ENABLE = '1' or VECTOR_INTEGER_DIVIDER_START = '1') and (unsigned(index_i_loop) < unsigned(VECTOR_INTEGER_DIVIDER_SIZE_IN)-unsigned(ONE_CONTROL))) then
-- CONTROL
VECTOR_INTEGER_DIVIDER_DATA_A_IN_ENABLE <= '1';
VECTOR_INTEGER_DIVIDER_DATA_B_IN_ENABLE <= '1';
-- DATA
VECTOR_INTEGER_DIVIDER_DATA_A_IN <= VECTOR_SAMPLE_B(to_integer(unsigned(index_i_loop)));
VECTOR_INTEGER_DIVIDER_DATA_B_IN <= VECTOR_SAMPLE_A(to_integer(unsigned(index_i_loop)));
-- LOOP
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
else
-- CONTROL
VECTOR_INTEGER_DIVIDER_DATA_A_IN_ENABLE <= '0';
VECTOR_INTEGER_DIVIDER_DATA_B_IN_ENABLE <= '0';
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit VECTOR_INTEGER_DIVIDER_SECOND_RUN when VECTOR_INTEGER_DIVIDER_READY = '1';
end loop VECTOR_INTEGER_DIVIDER_SECOND_RUN;
end if;
wait for WORKING;
end if;
-------------------------------------------------------------------
-- MATRIX-INTEGER
-------------------------------------------------------------------
if (STIMULUS_NTM_MATRIX_INTEGER_ADDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_MATRIX_ADDER_TEST ";
-------------------------------------------------------------------
-- CONTROL
MATRIX_INTEGER_ADDER_OPERATION <= '0';
-- DATA
MATRIX_INTEGER_ADDER_SIZE_I_IN <= THREE_CONTROL;
MATRIX_INTEGER_ADDER_SIZE_J_IN <= THREE_CONTROL;
if (STIMULUS_NTM_MATRIX_INTEGER_ADDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_MATRIX_ADDER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= ZERO_DATA;
MATRIX_INTEGER_ADDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
MATRIX_INTEGER_ADDER_FIRST_RUN : loop
if (MATRIX_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_ADDER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_ADDER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_ADDER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
else
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '0';
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '0';
MATRIX_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '0';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '0';
end if;
-- LOOP
if (MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(MATRIX_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
elsif (MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(MATRIX_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
elsif ((MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' or MATRIX_INTEGER_ADDER_START = '1') and (unsigned(index_j_loop) < unsigned(MATRIX_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit MATRIX_INTEGER_ADDER_FIRST_RUN when MATRIX_INTEGER_ADDER_READY = '1';
end loop MATRIX_INTEGER_ADDER_FIRST_RUN;
end if;
if (STIMULUS_NTM_MATRIX_INTEGER_ADDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_MATRIX_ADDER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= ZERO_DATA;
MATRIX_INTEGER_ADDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
MATRIX_INTEGER_ADDER_SECOND_RUN : loop
if (MATRIX_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_ADDER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_ADDER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_ADDER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_ADDER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
else
-- CONTROL
MATRIX_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '0';
MATRIX_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '0';
MATRIX_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '0';
MATRIX_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '0';
end if;
-- LOOP
if (MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(MATRIX_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
elsif (MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(MATRIX_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
elsif ((MATRIX_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' or MATRIX_INTEGER_ADDER_START = '1') and (unsigned(index_j_loop) < unsigned(MATRIX_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit MATRIX_INTEGER_ADDER_SECOND_RUN when MATRIX_INTEGER_ADDER_READY = '1';
end loop MATRIX_INTEGER_ADDER_SECOND_RUN;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_MATRIX_INTEGER_MULTIPLIER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_MATRIX_MULTIPLIER_TEST ";
-------------------------------------------------------------------
-- DATA
MATRIX_INTEGER_MULTIPLIER_SIZE_I_IN <= THREE_CONTROL;
MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN <= THREE_CONTROL;
if (STIMULUS_NTM_MATRIX_INTEGER_MULTIPLIER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_MATRIX_MULTIPLIER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= ZERO_DATA;
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
MATRIX_INTEGER_MULTIPLIER_FIRST_RUN : loop
if (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
else
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '0';
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '0';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '0';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '0';
end if;
-- LOOP
if (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
elsif (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
elsif ((MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' or MATRIX_INTEGER_MULTIPLIER_START = '1') and (unsigned(index_j_loop) < unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit MATRIX_INTEGER_MULTIPLIER_FIRST_RUN when MATRIX_INTEGER_MULTIPLIER_READY = '1';
end loop MATRIX_INTEGER_MULTIPLIER_FIRST_RUN;
end if;
if (STIMULUS_NTM_MATRIX_INTEGER_MULTIPLIER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_MATRIX_MULTIPLIER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= ZERO_DATA;
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
MATRIX_INTEGER_MULTIPLIER_SECOND_RUN : loop
if (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
else
-- CONTROL
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '0';
MATRIX_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '0';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '0';
MATRIX_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '0';
end if;
-- LOOP
if (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
elsif (MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
elsif ((MATRIX_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' or MATRIX_INTEGER_MULTIPLIER_START = '1') and (unsigned(index_j_loop) < unsigned(MATRIX_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit MATRIX_INTEGER_MULTIPLIER_SECOND_RUN when MATRIX_INTEGER_MULTIPLIER_READY = '1';
end loop MATRIX_INTEGER_MULTIPLIER_SECOND_RUN;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_MATRIX_INTEGER_DIVIDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_MATRIX_DIVIDER_TEST ";
-------------------------------------------------------------------
-- DATA
MATRIX_INTEGER_DIVIDER_SIZE_I_IN <= THREE_CONTROL;
MATRIX_INTEGER_DIVIDER_SIZE_J_IN <= THREE_CONTROL;
if (STIMULUS_NTM_MATRIX_INTEGER_DIVIDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_MATRIX_DIVIDER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= ZERO_DATA;
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
MATRIX_INTEGER_DIVIDER_FIRST_RUN : loop
if (MATRIX_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
else
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '0';
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '0';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '0';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '0';
end if;
-- LOOP
if (MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(MATRIX_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
elsif (MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(MATRIX_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
elsif ((MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' or MATRIX_INTEGER_DIVIDER_START = '1') and (unsigned(index_j_loop) < unsigned(MATRIX_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit MATRIX_INTEGER_DIVIDER_FIRST_RUN when MATRIX_INTEGER_DIVIDER_READY = '1';
end loop MATRIX_INTEGER_DIVIDER_FIRST_RUN;
end if;
if (STIMULUS_NTM_MATRIX_INTEGER_DIVIDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_MATRIX_DIVIDER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= ZERO_DATA;
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
MATRIX_INTEGER_DIVIDER_SECOND_RUN : loop
if (MATRIX_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
elsif (MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and unsigned(index_j_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
MATRIX_INTEGER_DIVIDER_DATA_A_IN <= MATRIX_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
MATRIX_INTEGER_DIVIDER_DATA_B_IN <= MATRIX_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)));
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
else
-- CONTROL
MATRIX_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '0';
MATRIX_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '0';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '0';
MATRIX_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '0';
end if;
-- LOOP
if (MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(MATRIX_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
elsif (MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(MATRIX_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(MATRIX_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
elsif ((MATRIX_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' or MATRIX_INTEGER_DIVIDER_START = '1') and (unsigned(index_j_loop) < unsigned(MATRIX_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit MATRIX_INTEGER_DIVIDER_SECOND_RUN when MATRIX_INTEGER_DIVIDER_READY = '1';
end loop MATRIX_INTEGER_DIVIDER_SECOND_RUN;
end if;
wait for WORKING;
end if;
-------------------------------------------------------------------
-- TENSOR-INTEGER
-------------------------------------------------------------------
if (STIMULUS_NTM_TENSOR_INTEGER_ADDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_TENSOR_ADDER_TEST ";
-------------------------------------------------------------------
-- CONTROL
TENSOR_INTEGER_ADDER_OPERATION <= '0';
-- DATA
TENSOR_INTEGER_ADDER_SIZE_I_IN <= THREE_CONTROL;
TENSOR_INTEGER_ADDER_SIZE_J_IN <= THREE_CONTROL;
TENSOR_INTEGER_ADDER_SIZE_K_IN <= THREE_CONTROL;
if (STIMULUS_NTM_TENSOR_INTEGER_ADDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_TENSOR_ADDER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= ZERO_DATA;
TENSOR_INTEGER_ADDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
TENSOR_INTEGER_ADDER_FIRST_RUN : loop
if (TENSOR_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
else
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '0';
end if;
-- LOOP
if (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(TENSOR_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_j_loop) < unsigned(TENSOR_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
index_k_loop <= ZERO_CONTROL;
elsif ((TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' or TENSOR_INTEGER_ADDER_START = '1') and (unsigned(index_k_loop) < unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_k_loop <= std_logic_vector(unsigned(index_k_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit TENSOR_INTEGER_ADDER_FIRST_RUN when TENSOR_INTEGER_ADDER_READY = '1';
end loop TENSOR_INTEGER_ADDER_FIRST_RUN;
end if;
if (STIMULUS_NTM_TENSOR_INTEGER_ADDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_TENSOR_ADDER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= ZERO_DATA;
TENSOR_INTEGER_ADDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
TENSOR_INTEGER_ADDER_SECOND_RUN : loop
if (TENSOR_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_ADDER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_ADDER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '1';
else
-- CONTROL
TENSOR_INTEGER_ADDER_DATA_A_IN_I_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_A_IN_J_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_A_IN_K_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_B_IN_I_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_B_IN_J_ENABLE <= '0';
TENSOR_INTEGER_ADDER_DATA_B_IN_K_ENABLE <= '0';
end if;
-- LOOP
if (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(TENSOR_INTEGER_ADDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_j_loop) < unsigned(TENSOR_INTEGER_ADDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
index_k_loop <= ZERO_CONTROL;
elsif ((TENSOR_INTEGER_ADDER_DATA_OUT_K_ENABLE = '1' or TENSOR_INTEGER_ADDER_START = '1') and (unsigned(index_k_loop) < unsigned(TENSOR_INTEGER_ADDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_k_loop <= std_logic_vector(unsigned(index_k_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit TENSOR_INTEGER_ADDER_SECOND_RUN when TENSOR_INTEGER_ADDER_READY = '1';
end loop TENSOR_INTEGER_ADDER_SECOND_RUN;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_TENSOR_INTEGER_MULTIPLIER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_TENSOR_MULTIPLIER_TEST ";
-------------------------------------------------------------------
-- DATA
TENSOR_INTEGER_MULTIPLIER_SIZE_I_IN <= THREE_CONTROL;
TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN <= THREE_CONTROL;
TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN <= THREE_CONTROL;
if (STIMULUS_NTM_TENSOR_INTEGER_MULTIPLIER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_TENSOR_MULTIPLIER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= ZERO_DATA;
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
TENSOR_INTEGER_MULTIPLIER_FIRST_RUN : loop
if (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
else
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '0';
end if;
-- LOOP
if (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_j_loop) < unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
index_k_loop <= ZERO_CONTROL;
elsif ((TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' or TENSOR_INTEGER_MULTIPLIER_START = '1') and (unsigned(index_k_loop) < unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_k_loop <= std_logic_vector(unsigned(index_k_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit TENSOR_INTEGER_MULTIPLIER_FIRST_RUN when TENSOR_INTEGER_MULTIPLIER_READY = '1';
end loop TENSOR_INTEGER_MULTIPLIER_FIRST_RUN;
end if;
if (STIMULUS_NTM_TENSOR_INTEGER_MULTIPLIER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_TENSOR_MULTIPLIER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= ZERO_DATA;
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
TENSOR_INTEGER_MULTIPLIER_SECOND_RUN : loop
if (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '1';
else
-- CONTROL
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_I_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_J_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_A_IN_K_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_I_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_J_ENABLE <= '0';
TENSOR_INTEGER_MULTIPLIER_DATA_B_IN_K_ENABLE <= '0';
end if;
-- LOOP
if (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_j_loop) < unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
index_k_loop <= ZERO_CONTROL;
elsif ((TENSOR_INTEGER_MULTIPLIER_DATA_OUT_K_ENABLE = '1' or TENSOR_INTEGER_MULTIPLIER_START = '1') and (unsigned(index_k_loop) < unsigned(TENSOR_INTEGER_MULTIPLIER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_k_loop <= std_logic_vector(unsigned(index_k_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit TENSOR_INTEGER_MULTIPLIER_SECOND_RUN when TENSOR_INTEGER_MULTIPLIER_READY = '1';
end loop TENSOR_INTEGER_MULTIPLIER_SECOND_RUN;
end if;
wait for WORKING;
end if;
if (STIMULUS_NTM_TENSOR_INTEGER_DIVIDER_TEST) then
-------------------------------------------------------------------
MONITOR_TEST <= "STIMULUS_NTM_TENSOR_DIVIDER_TEST ";
-------------------------------------------------------------------
-- DATA
TENSOR_INTEGER_DIVIDER_SIZE_I_IN <= THREE_CONTROL;
TENSOR_INTEGER_DIVIDER_SIZE_J_IN <= THREE_CONTROL;
TENSOR_INTEGER_DIVIDER_SIZE_K_IN <= THREE_CONTROL;
if (STIMULUS_NTM_TENSOR_INTEGER_DIVIDER_CASE_0) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_TENSOR_DIVIDER_CASE 0 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= ZERO_DATA;
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
TENSOR_INTEGER_DIVIDER_FIRST_RUN : loop
if (TENSOR_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
else
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '0';
end if;
-- LOOP
if (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(TENSOR_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_j_loop) < unsigned(TENSOR_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
index_k_loop <= ZERO_CONTROL;
elsif ((TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' or TENSOR_INTEGER_DIVIDER_START = '1') and (unsigned(index_k_loop) < unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_k_loop <= std_logic_vector(unsigned(index_k_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit TENSOR_INTEGER_DIVIDER_FIRST_RUN when TENSOR_INTEGER_DIVIDER_READY = '1';
end loop TENSOR_INTEGER_DIVIDER_FIRST_RUN;
end if;
if (STIMULUS_NTM_TENSOR_INTEGER_DIVIDER_CASE_1) then
-------------------------------------------------------------------
MONITOR_CASE <= "STIMULUS_NTM_TENSOR_DIVIDER_CASE 1 ";
-------------------------------------------------------------------
-- INITIAL CONDITIONS
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= ZERO_DATA;
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= ZERO_DATA;
-- LOOP
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
TENSOR_INTEGER_DIVIDER_SECOND_RUN : loop
if (TENSOR_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_i_loop) = unsigned(ZERO_CONTROL) and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_I_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_j_loop) = unsigned(ZERO_CONTROL) and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_J_ENABLE = '1' and TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) = unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and unsigned(index_k_loop) > unsigned(ZERO_CONTROL)) then
-- DATA
TENSOR_INTEGER_DIVIDER_DATA_A_IN <= TENSOR_SAMPLE_B(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
TENSOR_INTEGER_DIVIDER_DATA_B_IN <= TENSOR_SAMPLE_A(to_integer(unsigned(index_i_loop)), to_integer(unsigned(index_j_loop)), to_integer(unsigned(index_k_loop)));
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '1';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '1';
else
-- CONTROL
TENSOR_INTEGER_DIVIDER_DATA_A_IN_I_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_J_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_A_IN_K_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_I_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_J_ENABLE <= '0';
TENSOR_INTEGER_DIVIDER_DATA_B_IN_K_ENABLE <= '0';
end if;
-- LOOP
if (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= ZERO_CONTROL;
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_i_loop) < unsigned(TENSOR_INTEGER_DIVIDER_SIZE_I_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_j_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_i_loop <= std_logic_vector(unsigned(index_i_loop) + unsigned(ONE_CONTROL));
index_j_loop <= ZERO_CONTROL;
index_k_loop <= ZERO_CONTROL;
elsif (TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' and (unsigned(index_j_loop) < unsigned(TENSOR_INTEGER_DIVIDER_SIZE_J_IN)-unsigned(ONE_CONTROL)) and (unsigned(index_k_loop) = unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_j_loop <= std_logic_vector(unsigned(index_j_loop) + unsigned(ONE_CONTROL));
index_k_loop <= ZERO_CONTROL;
elsif ((TENSOR_INTEGER_DIVIDER_DATA_OUT_K_ENABLE = '1' or TENSOR_INTEGER_DIVIDER_START = '1') and (unsigned(index_k_loop) < unsigned(TENSOR_INTEGER_DIVIDER_SIZE_K_IN)-unsigned(ONE_CONTROL))) then
index_k_loop <= std_logic_vector(unsigned(index_k_loop) + unsigned(ONE_CONTROL));
end if;
-- GLOBAL
wait until rising_edge(clk_int);
-- CONTROL
exit TENSOR_INTEGER_DIVIDER_SECOND_RUN when TENSOR_INTEGER_DIVIDER_READY = '1';
end loop TENSOR_INTEGER_DIVIDER_SECOND_RUN;
end if;
wait for WORKING;
end if;
assert false
report "END OF TEST"
severity failure;
end process main_test;
end architecture;
|
<filename>RISCV_withSpecialUnit/RISCV_withSpecialUnit_vhd/DataPath.core/memoryUnit.vhd<gh_stars>1-10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity memoryUnit is
port(
--*INPUTS*--
clock : in std_logic;
reset : in std_logic;
----INPUTS FROM CONTROL WORD---------
en4: in std_logic;--memory stage enable
-----INPUT FROM PREVIOUS STAGE-----------
ALUout:in std_logic_vector(63 downto 0);
DRAMout:in std_logic_vector(31 downto 0);
AddressWfromEXECUTE:in std_logic_vector(63 downto 0);
-----OUTPUTS-----------
LOADDATA: out std_logic_vector(63 downto 0); --LMD register output
ALUtoWBMUX: out std_logic_vector(63 downto 0);
AddressWtoWB:out std_logic_vector(63 downto 0)
);
end memoryUnit;
architecture structural of memoryUnit is
component reg64 is
port(
clock,reset,load : in std_logic;
i : in std_logic_vector(63 downto 0);
o : out std_logic_vector(63 downto 0)
);
end component;
signal LDDATA64: std_logic_vector(63 downto 0);
begin
LDDATA64(31 downto 0)<= DRAMout;
LDDATA64(63 downto 32)<= (others=>DRAMout(31));
LMD_REG : reg64 port map(clock,reset,en4,LDDATA64,LOADDATA);
ALUout_REG: reg64 port map(clock,reset,en4,ALUout,ALUtoWBMUX); -- ALU output register
AddressW_REG: reg64 port map(clock,reset,en4,AddressWfromEXECUTE,AddressWtoWB); -- Addresses register real
end structural;
configuration CFG_memoryUnit of memoryUnit is
for structural
end for;
end CFG_memoryUnit;
configuration CFG_memoryUnit of memoryUnit is
for structural
for all : reg64
use configuration WORK.CFG_reg64;
end for;
end for;
end CFG_memoryUnit;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:15:27 10/22/2017
-- Design Name:
-- Module Name: C:/Users/Stiven/Desktop/ARQUITECTURA/PROCESADOR_III/ALU_PC_MODULE_TB.vhd
-- Project Name: PROCESADOR_III
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU_PC_MODULE
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_PC_MODULE_TB IS
END ALU_PC_MODULE_TB;
ARCHITECTURE behavior OF ALU_PC_MODULE_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU_PC_MODULE
PORT(
NPC : IN std_logic_vector(31 downto 0);
STATIC : IN std_logic_vector(31 downto 0);
PC : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal NPC : std_logic_vector(31 downto 0) := (others => '0');
signal STATIC : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal PC : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU_PC_MODULE PORT MAP (
NPC => NPC,
STATIC => STATIC,
PC => PC
);
-- Stimulus process
stim_proc: process
begin
NPC <= X"0000000F";
STATIC<= X"00000001";
WAIT FOR 10 NS;
NPC <= X"00000007";
STATIC<= X"00000001";
wait;
end process;
END;
|
<filename>fft/tf16.vhd<gh_stars>1-10
-- tf16.vhd
--
-- Created on: 17 Jul 2017
-- Author: <NAME>
--
-- Clock synchronous twiddle factor provider for 16-point FFT.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity tf16 is
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
addr: in std_logic_vector(FFTEXP-2 downto 0); -- address of twiddle factor
w: out complex); -- twiddle factor
end tf16;
architecture behavioral of tf16 is
-- twiddle factors for 16-Point FFT
constant WFACS: complex_arr(0 to (2**(FFTEXP-1))-1) := (
to_complex(1.0, 0.0),
to_complex(0.9239, 0.3827),
to_complex(0.7071, 0.7071),
to_complex(0.3827, 0.9239),
to_complex(0.0, 1.0),
to_complex(-0.3827, 0.9239),
to_complex(-0.7071, 0.7071),
to_complex(-0.9239, 0.3827)
);
signal w_tmp: complex := COMPZERO;
begin
w <= w_tmp;
process(rst, clk) is
begin
if rst = RSTDEF then
w_tmp <= COMPZERO;
elsif rising_edge(clk) then
if swrst = RSTDEF then
w_tmp <= COMPZERO;
elsif en = '1' then
w_tmp <= WFACS(to_integer(unsigned(addr)));
end if;
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity leds_time is
PORT
(
horl : IN STD_LOGIC;
nb_leds : IN INTEGER range 0 to 7;
leds_ctrl : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end leds_time;
ARCHITECTURE a of leds_time is
begin
process(horl)
begin
if (horl'event and horl='1') then
case nb_leds is
when 0 => leds_ctrl <= "00000001";
when 1 => leds_ctrl <= "00000011";
when 2 => leds_ctrl <= "00000111";
when 3 => leds_ctrl <= "00001111";
when 4 => leds_ctrl <= "00011111";
when 5 => leds_ctrl <= "00111111";
when 6 => leds_ctrl <= "01111111";
when 7 => leds_ctrl <= "11111111";
when others => leds_ctrl <= "00000000";
end case;
end if;
end process;
end a ;
|
<reponame>pedrovrc/Laboratorio-Sistemas-Digitais
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity contador10 is
port( clock : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
rci : in STD_LOGIC;
load : in STD_LOGIC;
D : in STD_LOGIC_VECTOR(3 downto 0);
Q : out STD_LOGIC_VECTOR(3 downto 0);
rco : out STD_LOGIC );
end contador10;
architecture contador10_arch of contador10 is
type estado is (ZERO, UM, DOIS, TRES, QUATRO,
CINCO, SEIS, SETE, OITO, NOVE);
signal EstadoAtual, ProxEstado, CarregaEstado: estado;
begin
with D select
CarregaEstado <= ZERO when "0000",
UM when "0001",
DOIS when "0010",
TRES when "0011",
QUATRO when "0100",
CINCO when "0101",
SEIS when "0110",
SETE when "0111",
OITO when "1000",
NOVE when "1001",
ZERO when others;
ProcSinc: process(clock)
begin
if rising_edge(clock) then
EstadoAtual <= ProxEstado;
end if;
end process ProcSinc;
ProcComb: process(EstadoAtual, reset, enable, rci, load, CarregaEstado)
begin
case EstadoAtual is
when ZERO =>
Q <= "0000";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= UM;
else ProxEstado <= ZERO;
end if;
when UM =>
Q <= "0001";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= DOIS;
else ProxEstado <= UM;
end if;
when DOIS =>
Q <= "0010";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= TRES;
else ProxEstado <= DOIS;
end if;
when TRES =>
Q <= "0011";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= QUATRO;
else ProxEstado <= TRES;
end if;
when QUATRO =>
Q <= "0100";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= CINCO;
else ProxEstado <= QUATRO;
end if;
when CINCO =>
Q <= "0101";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= SEIS;
else ProxEstado <= CINCO;
end if;
when SEIS =>
Q <= "0110";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= SETE;
else ProxEstado <= SEIS;
end if;
when SETE =>
Q <= "0111";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= OITO;
else ProxEstado <= SETE;
end if;
when OITO =>
Q <= "1000";
rco <= '1';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= NOVE;
else ProxEstado <= OITO;
end if;
when NOVE =>
Q <= "1001";
rco <= '0';
if reset = '1' then ProxEstado <= ZERO;
elsif load = '1' then ProxEstado <= CarregaEstado;
elsif not(enable) = '1' and not(rci) = '1' then ProxEstado <= ZERO;
else ProxEstado <= NOVE;
end if;
end case;
end process ProcComb;
end contador10_arch;
|
<filename>tb/tb_WasmFpgaControl.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.tb_types.all;
entity tb_WasmFpgaControl is
generic (
stimulus_path : string := "../../../../../simstm/";
stimulus_file : string := "WasmFpgaControl.stm"
);
end;
architecture behavioural of tb_WasmFpgaControl is
constant CLK100M_PERIOD : time := 10 ns;
signal Clk100M : std_logic := '0';
signal Rst : std_logic := '1';
signal nRst : std_logic := '0';
signal WasmFpgaControl_FileIO : T_WasmFpgaControl_FileIO;
signal FileIO_WasmFpgaControl : T_FileIO_WasmFpgaControl;
begin
nRst <= not Rst;
Clk100MGen : process is
begin
Clk100M <= not Clk100M;
wait for CLK100M_PERIOD / 2;
end process;
RstGen : process is
begin
Rst <= '1';
wait for 100ns;
Rst <= '0';
wait;
end process;
tb_FileIO_i : entity work.tb_FileIO
generic map (
stimulus_path => stimulus_path,
stimulus_file => stimulus_file
)
port map (
Clk => Clk100M,
Rst => Rst,
WasmFpgaControl_FileIO => WasmFpgaControl_FileIO,
FileIO_WasmFpgaControl => FileIO_WasmFpgaControl
);
WasmFpgaControl_i : entity work.WasmFpgaControl
port map (
Clk => Clk100M,
nRst => nRst,
Run => FileIO_WasmFpgaControl.Run,
Busy => WasmFpgaControl_FileIO.Busy,
Loader_Adr => open,
Loader_Sel => open,
Loader_DatIn => (others => '0'),
Loader_We => open,
Loader_Stb => open,
Loader_Cyc => open,
Loader_DatOut => open,
Loader_Ack => '0',
Engine_Adr => open,
Engine_Sel => open,
Engine_DatIn => (others => '0'),
Engine_We => open,
Engine_Stb => open,
Engine_Cyc => open,
Engine_DatOut => open,
Engine_Ack => '0'
);
end;
|
-------------------------------------------------------------------------------
-- cadr2_ml401_tb.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use work.wb_pack.all;
entity cadr2_ml401_tb is
end cadr2_ml401_tb;
architecture STRUCTURE of cadr2_ml401_tb is
component cadr2_ml401 is
port (
sys_clk_in : in std_logic;
sys_rst_in : in std_logic
);
end component cadr2_ml401;
-- stimulus file declaration
component STIMULUS is
PORT (
RST : out std_logic;
CLK : out std_logic
);
end component;
signal RST : std_logic;
signal CLK : std_logic;
begin
-- PCI stimulus file
stimulus_i : STIMULUS
port map (
CLK => CLK,
RST => RST
);
system_i : cadr2_ml401
port map (
sys_clk_in => CLK,
sys_rst_in => RST
);
end architecture;
|
<filename>bitvis_vip_axistream/tb/maintenance_tb/axistream_th.vhd
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Include Verification IPs
library bitvis_vip_axistream;
use bitvis_vip_axistream.axistream_bfm_pkg.all;
--=================================================================================================
entity test_harness is
generic(
constant GC_DATA_WIDTH : natural := 32;
constant GC_USER_WIDTH : natural := 1;
constant GC_ID_WIDTH : natural := 1;
constant GC_DEST_WIDTH : natural := 1;
constant GC_DUT_FIFO_DEPTH : natural := 4;
CONSTANT GC_INCLUDE_TUSER : boolean := true -- If tuser is used in AXI interface
);
port(
signal clk : in std_logic;
signal areset : in std_logic;
-- BFM
signal axistream_if_m_VVC2FIFO : inout t_axistream_if( tdata( GC_DATA_WIDTH -1 downto 0),
tkeep( (GC_DATA_WIDTH/8)-1 downto 0),
tuser( GC_USER_WIDTH -1 downto 0),
tstrb( GC_DATA_WIDTH/8 -1 downto 0),
tid( GC_ID_WIDTH -1 downto 0),
tdest( GC_DEST_WIDTH -1 downto 0)
);
signal axistream_if_s_FIFO2VVC : inout t_axistream_if( tdata( GC_DATA_WIDTH -1 downto 0),
tkeep( (GC_DATA_WIDTH/8)-1 downto 0),
tuser( GC_USER_WIDTH -1 downto 0),
tstrb( GC_DATA_WIDTH/8 -1 downto 0),
tid( GC_ID_WIDTH -1 downto 0),
tdest( GC_DEST_WIDTH -1 downto 0)
);
signal axistream_if_m_VVC2VVC : inout t_axistream_if( tdata( GC_DATA_WIDTH -1 downto 0),
tkeep( (GC_DATA_WIDTH/8)-1 downto 0),
tuser( GC_USER_WIDTH -1 downto 0),
tstrb( GC_DATA_WIDTH/8 -1 downto 0),
tid( GC_ID_WIDTH -1 downto 0),
tdest( GC_DEST_WIDTH -1 downto 0)
)
);
end entity test_harness;
--=================================================================================================
architecture struct_simple of test_harness is
signal s_axis_tready : std_logic;
signal s_axis_tvalid : std_logic;
signal s_axis_tdata : std_logic_vector (GC_DATA_WIDTH - 1 downto 0);
signal s_axis_tuser : std_logic_vector (GC_USER_WIDTH - 1 downto 0);
signal s_axis_tkeep : std_logic_vector (GC_DATA_WIDTH/8 - 1 downto 0);
signal s_axis_tlast : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tvalid : std_logic;
signal m_axis_tdata : std_logic_vector (GC_DATA_WIDTH - 1 downto 0);
signal m_axis_tuser : std_logic_vector (GC_USER_WIDTH - 1 downto 0);
signal m_axis_tkeep : std_logic_vector (GC_DATA_WIDTH/8 - 1 downto 0);
signal m_axis_tlast : std_logic;
begin
-- Mapping of interface to signals is done to make TB run in Riviera Pro.
-- Values are not propagated when interface elements are mapped directly
-- to ports. Riviera-PRO version 2018.10.137.7135
axistream_if_m_VVC2FIFO.tready <= s_axis_tready;
s_axis_tvalid <= axistream_if_m_VVC2FIFO.tvalid;
s_axis_tdata <= axistream_if_m_VVC2FIFO.tdata;
s_axis_tuser <= axistream_if_m_VVC2FIFO.tuser;
s_axis_tkeep <= axistream_if_m_VVC2FIFO.tkeep;
s_axis_tlast <= axistream_if_m_VVC2FIFO.tlast;
m_axis_tready <= axistream_if_s_FIFO2VVC.tready;
axistream_if_s_FIFO2VVC.tvalid <= m_axis_tvalid;
axistream_if_s_FIFO2VVC.tdata <= m_axis_tdata;
axistream_if_s_FIFO2VVC.tuser <= m_axis_tuser;
axistream_if_s_FIFO2VVC.tkeep <= m_axis_tkeep;
axistream_if_s_FIFO2VVC.tlast <= m_axis_tlast;
-----------------------------
-- Instantiate a DUT model : a self-made AXI-Stream FIFO
-- (I tried using a Xilinx FIFO IP between the BFMs but could only get verilog files, causing Modelsim licencing issues)
-----------------------------
i_axis_fifo : entity work.axis_fifo
generic map (
GC_DATA_WIDTH => GC_DATA_WIDTH ,
GC_USER_WIDTH => GC_USER_WIDTH ,
GC_FIFO_DEPTH => GC_DUT_FIFO_DEPTH
)
PORT MAP (
rst => areset,
clk => clk,
s_axis_tready => s_axis_tready,
s_axis_tvalid => s_axis_tvalid,
s_axis_tdata => s_axis_tdata,
s_axis_tuser => s_axis_tuser,
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
m_axis_tready => m_axis_tready,
m_axis_tvalid => m_axis_tvalid,
m_axis_tdata => m_axis_tdata,
m_axis_tuser => m_axis_tuser,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
empty => open
);
end struct_simple;
--=================================================================================================
architecture struct_vvc of test_harness is
begin
-----------------------------
-- Instantiate a DUT model : a self-made AXI-Stream FIFO
-- (I tried using a Xilinx FIFO IP between the BFMs but could only get verilog files, causing Modelsim licencing issues)
-----------------------------
i_axis_fifo : entity work.axis_fifo
generic map (
GC_DATA_WIDTH => GC_DATA_WIDTH ,
GC_USER_WIDTH => GC_USER_WIDTH ,
GC_FIFO_DEPTH => GC_DUT_FIFO_DEPTH
)
PORT MAP (
rst => areset,
clk => clk,
s_axis_tready => axistream_if_m_VVC2FIFO.tready,
s_axis_tvalid => axistream_if_m_VVC2FIFO.tvalid,
s_axis_tdata => axistream_if_m_VVC2FIFO.tdata,
s_axis_tuser => axistream_if_m_VVC2FIFO.tuser,
s_axis_tkeep => axistream_if_m_VVC2FIFO.tkeep,
s_axis_tlast => axistream_if_m_VVC2FIFO.tlast,
m_axis_tready => axistream_if_s_FIFO2VVC.tready,
m_axis_tvalid => axistream_if_s_FIFO2VVC.tvalid,
m_axis_tdata => axistream_if_s_FIFO2VVC.tdata,
m_axis_tuser => axistream_if_s_FIFO2VVC.tuser,
m_axis_tkeep => axistream_if_s_FIFO2VVC.tkeep,
m_axis_tlast => axistream_if_s_FIFO2VVC.tlast,
empty => open
);
-- This is not necessary, the BFM can receive 'U' without problems
-- axistream_if_s_FIFO2VVC.tstrb <= (others => '0');
-- axistream_if_s_FIFO2VVC.tid <= (others => '0');
-- axistream_if_s_FIFO2VVC.tdest <= (others => '0');
-- g_Not_Include_tuser: if (not GC_INCLUDE_TUSER) generate
-- axistream_if_s_FIFO2VVC.tuser <= (others => '0');
-- end generate;
-----------------------------
-- vvc/executors
-----------------------------
-- master vvc that transmit to FIFO
i_axistream_vvc_master_VVC2FIFO : entity work.axistream_vvc
generic map(
GC_VVC_IS_MASTER => true,
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_USER_WIDTH => GC_USER_WIDTH,
GC_ID_WIDTH => GC_ID_WIDTH,
GC_DEST_WIDTH => GC_DEST_WIDTH,
GC_INSTANCE_IDX => 0
)
port map(
clk => clk,
axistream_vvc_if => axistream_if_m_VVC2FIFO
);
-- slave vvc that receive from FIFO
i_axistream_vvc_slave_FIFO2VVC : entity work.axistream_vvc
generic map(
GC_VVC_IS_MASTER => false,
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_USER_WIDTH => GC_USER_WIDTH,
GC_ID_WIDTH => GC_ID_WIDTH,
GC_DEST_WIDTH => GC_DEST_WIDTH,
GC_INSTANCE_IDX => 1
)
port map(
clk => clk,
axistream_vvc_if => axistream_if_s_FIFO2VVC
);
--------------------------------------------------------------------
-- master vvc that transmit directly to Slave VVC
i_axistream_vvc_master_VVC2VVC : entity work.axistream_vvc
generic map(
GC_VVC_IS_MASTER => true,
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_USER_WIDTH => GC_USER_WIDTH,
GC_ID_WIDTH => GC_ID_WIDTH,
GC_DEST_WIDTH => GC_DEST_WIDTH,
GC_INSTANCE_IDX => 2
)
port map(
clk => clk,
axistream_vvc_if => axistream_if_m_VVC2VVC
);
-- slave vvc that receive directly from Master VVC
i_axistream_vvc_slave_VVC2VVC : entity work.axistream_vvc
generic map(
GC_VVC_IS_MASTER => false,
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_USER_WIDTH => GC_USER_WIDTH,
GC_ID_WIDTH => GC_ID_WIDTH,
GC_DEST_WIDTH => GC_DEST_WIDTH,
GC_INSTANCE_IDX => 3
)
port map(
clk => clk,
axistream_vvc_if => axistream_if_m_VVC2VVC
);
end struct_vvc;
architecture struct_multiple_vvc of test_harness is
begin
-----------------------------
-- Multiple VVCs just to test await_any_completion
-----------------------------
gen_axistream_vvc_master : for i in 0 to 7 generate
signal axistream_if_m_local : t_axistream_if( tdata( GC_DATA_WIDTH -1 downto 0),
tkeep( (GC_DATA_WIDTH/8)-1 downto 0),
tuser( GC_USER_WIDTH -1 downto 0),
tstrb( GC_DATA_WIDTH/8 -1 downto 0),
tid( GC_ID_WIDTH -1 downto 0),
tdest( GC_DEST_WIDTH -1 downto 0)
);
begin
axistream_if_m_local.tready <= '1';
i_axistream_vvc_master : entity work.axistream_vvc
generic map(
GC_VVC_IS_MASTER => true,
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_USER_WIDTH => GC_USER_WIDTH,
GC_ID_WIDTH => GC_ID_WIDTH,
GC_DEST_WIDTH => GC_DEST_WIDTH,
GC_INSTANCE_IDX => i
)
port map(
clk => clk,
axistream_vvc_if => axistream_if_m_local
);
end generate gen_axistream_vvc_master;
end struct_multiple_vvc;
|
<reponame>AndrewD/ctucanfd_ip_core
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2021-present <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to use, copy, modify, merge, publish, distribute the Component for
-- educational, research, evaluation, self-interest purposes. Using the
-- Component for commercial purposes is forbidden unless previously agreed with
-- Copyright holder.
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- -------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2020 MIT License
--
-- Authors:
-- <NAME> <<EMAIL>>
-- <NAME> <<EMAIL>>
--
-- Project advisors:
-- <NAME> <<EMAIL>>
-- <NAME> <<EMAIL>>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by <NAME> GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Register map implementation of: Control_registers
--------------------------------------------------------------------------------
-- This file is autogenerated, DO NOT EDIT!
Library ieee;
use ieee.std_logic_1164.all;
Library ctu_can_fd_rtl;
use ctu_can_fd_rtl.can_registers_pkg.all;
use ctu_can_fd_rtl.cmn_reg_map_pkg.all;
entity control_registers_reg_map is
generic (
constant DATA_WIDTH : natural := 32;
constant ADDRESS_WIDTH : natural := 8;
constant REGISTERED_READ : boolean := true;
constant CLEAR_READ_DATA : boolean := true;
constant RESET_POLARITY : std_logic := '0';
constant SUP_FILT_A : boolean := true;
constant SUP_TRAFFIC_CTRS : boolean := true;
constant SUP_RANGE : boolean := true;
constant SUP_FILT_C : boolean := true;
constant SUP_FILT_B : boolean := true
);
port (
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal address :in std_logic_vector(address_width - 1 downto 0);
signal w_data :in std_logic_vector(data_width - 1 downto 0);
signal r_data :out std_logic_vector(data_width - 1 downto 0);
signal cs :in std_logic;
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock_1 :in std_logic;
signal lock_2 :in std_logic;
signal control_registers_out :out Control_registers_out_t;
signal control_registers_in :in Control_registers_in_t
);
end entity control_registers_reg_map;
architecture rtl of control_registers_reg_map is
signal reg_sel : std_logic_vector(38 downto 0);
constant ADDR_VECT
: std_logic_vector(233 downto 0) := "100110100101100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(1247 downto 0);
signal read_data_mask_n : std_logic_vector(31 downto 0);
signal control_registers_out_i : Control_registers_out_t;
signal read_mux_ena : std_logic;
begin
----------------------------------------------------------------------------
-- Write address to One-hot decoder
----------------------------------------------------------------------------
address_decoder_control_registers_comp : address_decoder
generic map(
address_width => 6 ,
address_entries => 39 ,
addr_vect => ADDR_VECT ,
registered_out => false ,
reset_polarity => RESET_POLARITY
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
address => address(7 downto 2) ,-- in
enable => cs ,-- in
addr_dec => reg_sel -- out
);
----------------------------------------------------------------------------
-- MODE register
----------------------------------------------------------------------------
mode_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000001111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000001000010000" ,
auto_clear => "0000000000000001" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(1) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.mode -- out
);
----------------------------------------------------------------------------
-- SETTINGS register
----------------------------------------------------------------------------
settings_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000011111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000001000000000" ,
auto_clear => "0000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 16) ,-- in
write => write ,-- in
cs => reg_sel(1) ,-- in
w_be => be(3 downto 2) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.settings -- out
);
----------------------------------------------------------------------------
-- COMMAND register
----------------------------------------------------------------------------
command_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00000000000000000000000011111110" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000011111110" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(3) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.command -- out
);
----------------------------------------------------------------------------
-- INT_STAT register
----------------------------------------------------------------------------
int_stat_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(4) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_stat -- out
);
----------------------------------------------------------------------------
-- INT_ENA_SET register
----------------------------------------------------------------------------
int_ena_set_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(5) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_ena_set -- out
);
----------------------------------------------------------------------------
-- INT_ENA_CLR register
----------------------------------------------------------------------------
int_ena_clr_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(6) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_ena_clr -- out
);
----------------------------------------------------------------------------
-- INT_MASK_SET register
----------------------------------------------------------------------------
int_mask_set_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(7) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_mask_set -- out
);
----------------------------------------------------------------------------
-- INT_MASK_CLR register
----------------------------------------------------------------------------
int_mask_clr_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000111111111111" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(8) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.int_mask_clr -- out
);
----------------------------------------------------------------------------
-- BTR register
----------------------------------------------------------------------------
btr_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "11111111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00010000010100001010000110000101" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(9) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock_2 ,-- in
reg_value => control_registers_out_i.btr -- out
);
----------------------------------------------------------------------------
-- BTR_FD register
----------------------------------------------------------------------------
btr_fd_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "11111111111110111110111110111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00010000001000000110000110000011" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(10) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock_2 ,-- in
reg_value => control_registers_out_i.btr_fd -- out
);
----------------------------------------------------------------------------
-- EWL register
----------------------------------------------------------------------------
ewl_reg_comp : memory_reg
generic map(
data_width => 8 ,
data_mask => "11111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "01100000" ,
auto_clear => "00000000" ,
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(7 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(11) ,-- in
w_be => be(0 downto 0) ,-- in
lock => lock_1 ,-- in
reg_value => control_registers_out_i.ewl -- out
);
----------------------------------------------------------------------------
-- ERP register
----------------------------------------------------------------------------
erp_reg_comp : memory_reg
generic map(
data_width => 8 ,
data_mask => "11111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "10000000" ,
auto_clear => "00000000" ,
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 8) ,-- in
write => write ,-- in
cs => reg_sel(11) ,-- in
w_be => be(1 downto 1) ,-- in
lock => lock_1 ,-- in
reg_value => control_registers_out_i.erp -- out
);
----------------------------------------------------------------------------
-- CTR_PRES register
----------------------------------------------------------------------------
ctr_pres_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00000000000000000001111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000001111000000000" ,
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(14) ,-- in
w_be => be(3 downto 0) ,-- in
lock => lock_1 ,-- in
reg_value => control_registers_out_i.ctr_pres -- out
);
----------------------------------------------------------------------------
-- FILTER_A_MASK register
----------------------------------------------------------------------------
FILTER_A_MASK_present_gen_t : if (SUP_FILT_A = true) generate
filter_a_mask_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(15) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_a_mask -- out
);
end generate FILTER_A_MASK_present_gen_t;
FILTER_A_MASK_present_gen_f : if (SUP_FILT_A = false) generate
control_registers_out_i.filter_a_mask <= "00000000000000000000000000000000";
end generate FILTER_A_MASK_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_A_VAL register
----------------------------------------------------------------------------
FILTER_A_VAL_present_gen_t : if (SUP_FILT_A = true) generate
filter_a_val_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(16) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_a_val -- out
);
end generate FILTER_A_VAL_present_gen_t;
FILTER_A_VAL_present_gen_f : if (SUP_FILT_A = false) generate
control_registers_out_i.filter_a_val <= "00000000000000000000000000000000";
end generate FILTER_A_VAL_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_B_MASK register
----------------------------------------------------------------------------
FILTER_B_MASK_present_gen_t : if (SUP_FILT_B = true) generate
filter_b_mask_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(17) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_b_mask -- out
);
end generate FILTER_B_MASK_present_gen_t;
FILTER_B_MASK_present_gen_f : if (SUP_FILT_B = false) generate
control_registers_out_i.filter_b_mask <= "00000000000000000000000000000000";
end generate FILTER_B_MASK_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_B_VAL register
----------------------------------------------------------------------------
FILTER_B_VAL_present_gen_t : if (SUP_FILT_B = true) generate
filter_b_val_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(18) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_b_val -- out
);
end generate FILTER_B_VAL_present_gen_t;
FILTER_B_VAL_present_gen_f : if (SUP_FILT_B = false) generate
control_registers_out_i.filter_b_val <= "00000000000000000000000000000000";
end generate FILTER_B_VAL_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_C_MASK register
----------------------------------------------------------------------------
FILTER_C_MASK_present_gen_t : if (SUP_FILT_C = true) generate
filter_c_mask_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(19) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_c_mask -- out
);
end generate FILTER_C_MASK_present_gen_t;
FILTER_C_MASK_present_gen_f : if (SUP_FILT_C = false) generate
control_registers_out_i.filter_c_mask <= "00000000000000000000000000000000";
end generate FILTER_C_MASK_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_C_VAL register
----------------------------------------------------------------------------
FILTER_C_VAL_present_gen_t : if (SUP_FILT_C = true) generate
filter_c_val_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(20) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_c_val -- out
);
end generate FILTER_C_VAL_present_gen_t;
FILTER_C_VAL_present_gen_f : if (SUP_FILT_C = false) generate
control_registers_out_i.filter_c_val <= "00000000000000000000000000000000";
end generate FILTER_C_VAL_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_RAN_LOW register
----------------------------------------------------------------------------
FILTER_RAN_LOW_present_gen_t : if (SUP_RANGE = true) generate
filter_ran_low_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(21) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_ran_low -- out
);
end generate FILTER_RAN_LOW_present_gen_t;
FILTER_RAN_LOW_present_gen_f : if (SUP_RANGE = false) generate
control_registers_out_i.filter_ran_low <= "00000000000000000000000000000000";
end generate FILTER_RAN_LOW_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_RAN_HIGH register
----------------------------------------------------------------------------
FILTER_RAN_HIGH_present_gen_t : if (SUP_RANGE = true) generate
filter_ran_high_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "00011111111111111111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000000" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(22) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_ran_high -- out
);
end generate FILTER_RAN_HIGH_present_gen_t;
FILTER_RAN_HIGH_present_gen_f : if (SUP_RANGE = false) generate
control_registers_out_i.filter_ran_high <= "00000000000000000000000000000000";
end generate FILTER_RAN_HIGH_present_gen_f;
----------------------------------------------------------------------------
-- FILTER_CONTROL register
----------------------------------------------------------------------------
filter_control_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "1111111111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000001111" ,
auto_clear => "0000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(23) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.filter_control -- out
);
----------------------------------------------------------------------------
-- RX_SETTINGS register
----------------------------------------------------------------------------
rx_settings_reg_comp : memory_reg
generic map(
data_width => 8 ,
data_mask => "00000001" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000" ,
auto_clear => "00000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(23 downto 16) ,-- in
write => write ,-- in
cs => reg_sel(26) ,-- in
w_be => be(2 downto 2) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.rx_settings -- out
);
----------------------------------------------------------------------------
-- RX_DATA access signallization
----------------------------------------------------------------------------
rx_data_access_signaller_comp : access_signaller
generic map(
reset_polarity => RESET_POLARITY ,
data_width => 32 ,
read_signalling => True ,
write_signalling => False ,
read_signalling_reg => False ,
write_signalling_reg => False
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
cs => reg_sel(27) ,-- in
read => read ,-- in
write => write ,-- in
be => be(3 downto 0) ,-- in
write_signal => open ,-- out
read_signal => control_registers_out_i.rx_data_read -- out
);
----------------------------------------------------------------------------
-- TX_COMMAND register
----------------------------------------------------------------------------
tx_command_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "1111111100000111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000000000" ,
auto_clear => "0000000000000111" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(15 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(29) ,-- in
w_be => be(1 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.tx_command -- out
);
----------------------------------------------------------------------------
-- TX_PRIORITY register
----------------------------------------------------------------------------
tx_priority_reg_comp : memory_reg
generic map(
data_width => 32 ,
data_mask => "01110111011101110111011101110111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "00000000000000000000000000000001" ,
auto_clear => "00000000000000000000000000000000" ,
is_lockable => false
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 0) ,-- in
write => write ,-- in
cs => reg_sel(30) ,-- in
w_be => be(3 downto 0) ,-- in
lock => '0' ,-- in
reg_value => control_registers_out_i.tx_priority -- out
);
----------------------------------------------------------------------------
-- SSP_CFG register
----------------------------------------------------------------------------
ssp_cfg_reg_comp : memory_reg
generic map(
data_width => 16 ,
data_mask => "0000001111111111" ,
reset_polarity => RESET_POLARITY ,
reset_value => "0000000000001010" ,
auto_clear => "0000000000000000" ,
is_lockable => true
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_in => w_data(31 downto 16) ,-- in
write => write ,-- in
cs => reg_sel(32) ,-- in
w_be => be(3 downto 2) ,-- in
lock => lock_2 ,-- in
reg_value => control_registers_out_i.ssp_cfg -- out
);
----------------------------------------------------------------------------
-- Read data multiplexor enable
----------------------------------------------------------------------------
read_data_keep_gen : if (CLEAR_READ_DATA = false) generate
read_mux_ena <= read and cs;
end generate read_data_keep_gen;
read_data_clear_gen : if (CLEAR_READ_DATA = true) generate
read_mux_ena <= '1';
end generate read_data_clear_gen;
----------------------------------------------------------------------------
-- Read data multiplexor
----------------------------------------------------------------------------
data_mux_control_registers_comp : data_mux
generic map(
data_out_width => 32 ,
data_in_width => 1248 ,
sel_width => 6 ,
registered_out => REGISTERED_READ ,
reset_polarity => RESET_POLARITY
)
port map(
clk_sys => clk_sys ,-- in
res_n => res_n ,-- in
data_selector => address(7 downto 2) ,-- in
data_in => read_data_mux_in ,-- in
data_mask_n => read_data_mask_n ,-- in
enable => read_mux_ena ,-- in
data_out => r_data -- out
);
------------------------------------------------------------------------------
-- Read data driver
------------------------------------------------------------------------------
read_data_mux_in <=
-- Adress:152
control_registers_in.timestamp_high &
-- Adress:148
control_registers_in.timestamp_low &
-- Adress:144
control_registers_in.yolo_reg &
-- Adress:140
control_registers_in.debug_register &
-- Adress:136
control_registers_in.tx_fr_ctr &
-- Adress:132
control_registers_in.rx_fr_ctr &
-- Adress:128
control_registers_out_i.ssp_cfg & control_registers_in.trv_delay &
-- Adress:124
"00000000" & control_registers_in.alc & control_registers_in.retr_ctr & control_registers_in.err_capt &
-- Adress:120
control_registers_out_i.tx_priority &
-- Adress:116
control_registers_in.txtb_info & "00000000" & "00000000" &
-- Adress:112
control_registers_in.tx_status &
-- Adress:108
control_registers_in.rx_data &
-- Adress:104
"00000000" & control_registers_out_i.rx_settings & control_registers_in.rx_status &
-- Adress:100
control_registers_in.rx_pointers &
-- Adress:96
control_registers_in.rx_mem_info &
-- Adress:92
control_registers_in.filter_status & control_registers_out_i.filter_control &
-- Adress:88
control_registers_out_i.filter_ran_high &
-- Adress:84
control_registers_out_i.filter_ran_low &
-- Adress:80
control_registers_out_i.filter_c_val &
-- Adress:76
control_registers_out_i.filter_c_mask &
-- Adress:72
control_registers_out_i.filter_b_val &
-- Adress:68
control_registers_out_i.filter_b_mask &
-- Adress:64
control_registers_out_i.filter_a_val &
-- Adress:60
control_registers_out_i.filter_a_mask &
-- Adress:56
"00000000" & "00000000" & "00000000" & "00000000" &
-- Adress:52
control_registers_in.err_fd & control_registers_in.err_norm &
-- Adress:48
control_registers_in.tec & control_registers_in.rec &
-- Adress:44
control_registers_in.fault_state & control_registers_out_i.erp & control_registers_out_i.ewl &
-- Adress:40
control_registers_out_i.btr_fd &
-- Adress:36
control_registers_out_i.btr &
-- Adress:32
"00000000" & "00000000" & "00000000" & "00000000" &
-- Adress:28
"00000000" & "00000000" & control_registers_in.int_mask_set &
-- Adress:24
"00000000" & "00000000" & "00000000" & "00000000" &
-- Adress:20
"00000000" & "00000000" & control_registers_in.int_ena_set &
-- Adress:16
"00000000" & "00000000" & control_registers_in.int_stat &
-- Adress:12
"00000000" & "00000000" & "00000000" & "00000000" &
-- Adress:8
control_registers_in.status &
-- Adress:4
control_registers_out_i.settings & control_registers_out_i.mode &
-- Adress:0
control_registers_in.version & control_registers_in.device_id;
----------------------------------------------------------------------------
-- Read data mask - Byte enables
----------------------------------------------------------------------------
read_data_mask_n <=
be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &
be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &
be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &
be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ;
Control_registers_out <= Control_registers_out_i;
-- <RELEASE_OFF>
----------------------------------------------------------------------------
-- Functional coverage
----------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys);
-- psl device_id_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl version_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl mode_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl mode_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl settings_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl settings_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl status_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl command_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl int_stat_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl int_stat_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl int_ena_set_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl int_ena_set_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl int_ena_clr_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(6)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl int_mask_set_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl int_mask_set_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl int_mask_clr_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(8)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl btr_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl btr_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl btr_fd_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl btr_fd_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl ewl_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(0)='1')))};
-- psl ewl_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(0)='1')))};
-- psl erp_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(1)='1')))};
-- psl erp_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(1)='1')))};
-- psl fault_state_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl rec_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl tec_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl err_norm_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl err_fd_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl ctr_pres_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(14)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_a_mask_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_a_mask_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_a_val_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_a_val_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_b_mask_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_b_mask_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_b_val_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_b_val_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_c_mask_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_c_mask_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_c_val_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_c_val_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_ran_low_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_ran_low_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_ran_high_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_ran_high_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl filter_control_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl filter_control_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl filter_status_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl rx_mem_info_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(24)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl rx_pointers_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(25)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl rx_status_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl rx_settings_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(26)='1') and ((be(2)='1')))};
-- psl rx_settings_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(2)='1')))};
-- psl rx_data_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(27)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl tx_status_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(28)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl tx_command_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(29)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl txtb_info_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(29)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl tx_priority_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl tx_priority_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl err_capt_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(0)='1')))};
-- psl retr_ctr_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(1)='1')))};
-- psl alc_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(2)='1')))};
-- psl trv_delay_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(0)='1') or (be(1)='1')))};
-- psl ssp_cfg_write_access_cov : cover
-- {((cs='1') and (write='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl ssp_cfg_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))};
-- psl rx_fr_ctr_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(33)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl tx_fr_ctr_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(34)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl debug_register_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(35)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl yolo_reg_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(36)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl timestamp_low_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(37)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- psl timestamp_high_read_access_cov : cover
-- {((cs='1') and (read='1') and (reg_sel(38)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
-- <RELEASE_ON>
end architecture rtl;
|
<reponame>roneissu/bonfire-cpu
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:51:42 10/01/2016
-- Design Name:
-- Module Name: /home/thomas/riscv/lxp32-cpu/ut/tb_mult_dsp.vhd
-- Project Name: lxp32riscv
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: lxp32_mul_dsp
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_mult_dsp IS
END tb_mult_dsp;
ARCHITECTURE behavior OF tb_mult_dsp IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT lxp32_mul_dsp
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
ce_i : IN std_logic;
op1_i : IN std_logic_vector(31 downto 0);
op2_i : IN std_logic_vector(31 downto 0);
ce_o : OUT std_logic;
result_o : OUT std_logic_vector(31 downto 0);
result_high_o : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal ce_i : std_logic := '0';
signal op1_i : std_logic_vector(31 downto 0) := (others => '0');
signal op2_i : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal ce_o : std_logic;
signal result_o : std_logic_vector(31 downto 0);
signal result_high_o : std_logic_vector(31 downto 0);
signal result_u : unsigned(63 downto 0);
signal result_s : signed(63 downto 0);
-- Clock period definitions
constant clk_i_period : time := 10 ns;
subtype dword is std_logic_vector(31 downto 0);
function l32(v: integer) return dword is
begin
return std_logic_vector(to_signed(v,32));
end;
BEGIN
result_u <= unsigned(result_high_o & result_o);
result_s <= signed(result_high_o & result_o);
-- Instantiate the Unit Under Test (UUT)
uut: lxp32_mul_dsp PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
op1_i => op1_i,
op2_i => op2_i,
ce_o => ce_o,
result_o => result_o,
result_high_o => result_high_o
);
-- Clock process definitions
clk_i_process :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if ce_o='1' then
-- ce_i<='0';
-- end if;
--
-- end if;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_i_period*3;
op1_i<= l32(5);
op2_i<= l32(-1);
ce_i<='1';
wait for clk_i_period;
ce_i<='0';
wait for clk_i_period*2;
op1_i<= X"00000005";
op2_i<= X"00000005";
ce_i<='1';
wait for clk_i_period;
ce_i<='0';
wait for clk_i_period*2;
op1_i<= X"00001388"; -- dec. 5000
op2_i<= X"00001388";
ce_i<='1';
wait for clk_i_period;
ce_i<='0';
wait for clk_i_period*2;
op1_i<= l32(5000000);
op2_i<= l32(5000000);
ce_i<='1';
wait for clk_i_period;
ce_i<='0';
wait for clk_i_period*2;
op1_i<= l32(5000000);
op2_i<= l32(-3);
ce_i<='1';
wait for clk_i_period;
ce_i<='0';
wait for clk_i_period*2;
wait;
end process;
END;
|
<filename>Lab4/decrement.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decrement is
Port( a1 : in STD_LOGIC_VECTOR(3 downto 0);
out1: out STD_LOGIC_VECTOR(3 downto 0));
end decrement;
architecture Behavioral of decrement is
begin
out1 <= (a1-"0001");
end Behavioral;
|
<gh_stars>1-10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity DECODE_5b4b is
port (IN_5b_i : in std_logic_vector(4 downto 0) ;
clk: in std_logic;
OUT_4b_o : out std_logic_vector(3 downto 0) );
end DECODE_5b4b;
architecture Behaviorial of DECODE_5b4b is
signal q_4b: std_logic_vector(3 downto 0);
begin
q_4b <= "0000" when IN_5b_i ="11110" else
"0001" when IN_5b_i ="01001" else
"0010" when IN_5b_i ="10100" else
"0011" when IN_5b_i ="10101" else
"0100" when IN_5b_i ="01010" else
"0101" when IN_5b_i ="01011" else
"0110" when IN_5b_i ="01110" else
"0111" when IN_5b_i ="01111" else
"1000" when IN_5b_i ="10010" else
"1001" when IN_5b_i ="10011" else
"1010" when IN_5b_i ="10110" else
"1011" when IN_5b_i ="10111" else
"1100" when IN_5b_i ="11010" else
"1101" when IN_5b_i ="11011" else
"1110" when IN_5b_i ="11100" else
"1111" when IN_5b_i ="11101" else
"0000";
process (clk)
begin
if (rising_edge(clk)) then
OUT_4b_o<=q_4b;
end if;
end process;
end Behaviorial;
|
<reponame>veeYceeY/SCiV<filename>src/rtl/peripherals/wb_gpio.vhd<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.pkg_aukv.all;
entity wb_gpio is
port(
i_clk : in std_logic;
i_rst : in std_logic;
o_m_wb : out t_in_wb_master;
i_m_wb : in t_out_wb_master;
i_port_a: in std_logic_vector(31 downto 0);
o_port_b: out std_logic_vector(31 downto 0)
);
end wb_gpio;
architecture behave of wb_gpio is
type mem_type is array(7 downto 0) of std_logic_vector(31 downto 0);
signal mem : mem_type;
signal data : std_logic_vector(31 downto 0);
begin
ri0:entity work.wb_reg_if
port map(
i_clk => i_clk,
i_rst => i_rst,
o_m_wb => o_m_wb,
i_m_wb => i_m_wb,
i_reg0 =>i_port_a ,
o_reg0 =>o_port_b
);
end behave;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (lin64) Build 1846317 Fri Apr 14 18:54:47 MDT 2017
-- Date : Thu Mar 29 11:22:27 2018
-- Host : justin-desktop running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/justin/Vivado/jtag_prog/jtag_prog.srcs/sources_1/ip/fifo_read/fifo_read_stub.vhdl
-- Design : fifo_read
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tftg256-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_read is
Port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end fifo_read;
architecture stub of fifo_read is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,srst,din[7:0],wr_en,rd_en,dout[0:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_4,Vivado 2017.1";
begin
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity singleReg is
port(
R_reset : in std_logic;
R_clock : in std_logic;
Data_in : in std_logic_vector(16-1 downto 0);
R_WriteEnable : in std_logic;
Data_out : out std_logic_vector(16-1 downto 0)
);
end singleReg;
architecture comportamento of singleReg is
signal out_tmp : std_logic_vector(15 downto 0);
begin
process(R_clock, R_reset)
begin
if( R_reset = '1') then
out_tmp <= (out_tmp'range =>'0');
elsif ( rising_edge(R_clock)) then
if( R_WriteEnable = '1' ) then
out_tmp <= Data_in;
end if;
end if;
end process;
Data_out <= out_tmp ;
end comportamento;
|
<reponame>OmarRaed/PipelinedMips
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE stageOnePackage IS
TYPE muxInputs IS array(0 to 31) of std_logic_vector(31 DOWNTO 0);
COMPONENT InstructionMemory IS
PORT (
clk : IN STD_LOGIC ; --CLK SIGNAL
pc : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ; --PC VALUE
instructionOutput : Out STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT INSTRUCTION
) ;
END COMPONENT InstructionMemory ;
COMPONENT AdderFour IS
PORT(
clk : IN STD_LOGIC ;
PCIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ;
PCOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT AdderFour ;
COMPONENT pcRegister IS
PORT(
clk: in std_logic; -- clock
D: in std_logic_vector(31 downto 0); -- data input
Q: out std_logic_vector(31 downto 0)); -- data output
END COMPONENT pcRegister;
COMPONENT mux_2_1 IS
PORT(
sel: IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT mux_2_1;
END PACKAGE stageOnePackage ;
|
<reponame>mkiesinger/mimaFPGA
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity MicroFunctionAddrROM is
Port ( op_addr : in STD_LOGIC_VECTOR (4 downto 0);
func_entry_addr : out STD_LOGIC_VECTOR (7 downto 0));
end MicroFunctionAddrROM;
architecture Behavioral of MicroFunctionAddrROM is
function bin(i : integer) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(i, 8));
end function bin;
type MICRO_FUNCTION_ADRESSES_ROM is array (0 to 31) of STD_LOGIC_VECTOR(7 downto 0);
constant rom : MICRO_FUNCTION_ADRESSES_ROM := (
-- OPC |MNEM |ARG |LOC in u-inst ROM
0 => bin(8), -- 0 |LDC |c |8
1 => bin(12), -- 1 |LDV |[a] |12
2 => bin(20), -- 2 |STV |[a] |20
3 => bin(28), -- 3 |ADD |[a] |28
4 => bin(36), -- 4 |AND |[a] |36
5 => bin(44), -- 5 |OR |[a] |44
6 => bin(52), -- 6 |XOR |[a] |52
7 => bin(60), -- 7 |EQL |[a] |60
8 => bin(68), -- 8 |JMP |a |68
9 => bin(72), -- 9 |JMN |a |72
10 => bin(100), -- A |LDIV |[[a]]|100
11 => bin(112), -- B |LDIV |[[a]]|112
12 => bin(124), -- C |JMS |a |124
13 => bin(136), -- D |JIND |a |136
17 => bin(88), -- F1 |NOT | |88
18 => bin(96), -- F2 |RAR | |96
others => (others => '0')
);
begin
func_entry_addr <= rom(to_integer(unsigned(op_addr)));
end Behavioral;
|
<reponame>marekhudec/VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity traffic is
port ( clk_i: in std_logic;
srst_n_i: in std_logic;
lights_o: out std_logic_vector(6-1 downto 0)
);
end traffic;
architecture traffic of traffic is
type state_type is (green_red, yellow_red, red_red, red_green,red_yellow,red_red_2);
signal state: state_type;
signal s_count: unsigned(3 downto 0);
constant SEC5: unsigned(3 downto 0) := "1111";
constant SEC1: unsigned(3 downto 0) := "0011";
begin
process(clk_i,srst_n_i)
begin
if rising_edge(clk_i) then
if srst_n_i = '0' then
state <= green_red;
s_count <= x"0";
else
case state is
when green_red =>
if s_count < SEC5 then
state <= green_red;
s_count <= s_count +1;
else
state <= yellow_red;
s_count <= x"0";
end if;
when yellow_red =>
if s_count < SEC1 then
state <= yellow_red;
s_count <= s_count +1;
else
state <= red_red;
s_count <= x"0";
end if;
when red_red =>
if s_count < SEC1 then
state <= red_red;
s_count <= s_count + 1;
else
state <= red_green;
s_count <= x"0";
end if;
when red_green =>
if s_count < SEC1 then
state <= red_green;
s_count <= s_count +1;
else
state <= red_yellow;
s_count <= x"0";
end if;
when red_yellow =>
if s_count < SEC1 then
state <= red_yellow;
s_count <= s_count +1;
else
state <= red_red_2;
s_count <= x"0";
end if;
when red_red_2 =>
if s_count < SEC1 then
state <= red_red_2;
s_count <= s_count +1;
else
state <= green_red;
s_count <= x"0";
end if;
when others =>
state <= green_red;
end case;
end if;
end if;
end process;
C2: process(state)
begin
case state is
when green_red => lights_o <= "100001";
when yellow_red => lights_o <= "100010";
when red_red => lights_o<= "100100";
when red_green => lights_o <= "001100";
when red_yellow => lights_o <= "010100";
when red_red_2 => lights_o <= "100100";
when others => lights_o <= "100001";
end case;
end process;
end traffic;
|
----------------------------------------------------------------------------------
-- Developers: <NAME>, <NAME>
--
-- Create Date: 09:25:25 04/30/2020
--
-- Project Name: HC-SR04
-- Target Devices: CoolRunner-II CPLD starter board
-- Description: counter echo pulse and transform BIN to BCD code
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity cntpulse is
port( clk : in std_logic;
start : in std_logic; --TRIGR
stop : in std_logic; --ECHO
bjed : out std_logic_vector(3 downto 0); --bin_jednotky
bdes : out std_logic_vector(3 downto 0); --bin_desitky
bsto : out std_logic_vector(3 downto 0) --bin_stovky
);
end cntpulse;
architecture Behavioral of cntpulse is
signal cnttime : std_logic_vector(13 downto 0):= (Others => '0'); --delka pulzu ECHO
signal stopinside : std_logic := '0'; -- 1 -> citac cita 0 -> citac po resetu
signal bcdconv : std_logic_vector(14 downto 0):= (Others => '0'); -- promenna prevodu
signal stobcdconv : std_logic_vector(2 downto 0):= (Others => '0'); -- pocet cyklu v prevodu
signal sepadd : std_logic_vector(1 downto 0):= (Others => '0'); --pomocna promena pro prevod
begin
pulse : process (clk)
begin
if rising_edge(clk) then
if stop = '1' then -- zacatek scitani
cnttime <= cnttime + 1;
stopinside <= '1';
bjed <= bcdconv(8 downto 5); --prirazeni jednotky
bdes <= bcdconv(12 downto 9); --prirazeni desitky
bsto <= "00" & bcdconv(14 downto 13); --prirazeni stovky
elsif (start = '1' and stopinside = '1') then --reset
bcdconv <= "0000000" & cnttime(13 downto 6); --vzdeleni casu 64 a nasledne prirazeni do promenne prevodu
stopinside <= '0' ;
cnttime <= (Others => '0');
stobcdconv <= (Others => '0');
end if;
if (stop = '1' and stobcdconv < "101") then -- prepocet BIN to BCD
if (bcdconv(8 downto 5) > 4 and sepadd(0) = '0') then -- jednotky
bcdconv(8 downto 5) <= bcdconv(8 downto 5) + 3;
sepadd(0) <='1';
elsif (bcdconv(12 downto 9) > 4 and sepadd(1) = '0') then -- desitky
bcdconv(12 downto 9) <= bcdconv(12 downto 9) + 3;
sepadd(1) <='1';
else
bcdconv <= bcdconv(13 downto 0) & '0'; -- posunuti doleva
stobcdconv <= stobcdconv +1;
sepadd <="00";
end if;
end if;
end if;
end process pulse;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package WasmFpgaBusWshBn_Package is
-- type decalarations ---------------------------------
type WasmFpgaBus_arr_of_std_logic_vector_2_t is
array (natural range <>) of std_logic_vector(1 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_3_t is
array (natural range <>) of std_logic_vector(1 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_4_t is
array (natural range <>) of std_logic_vector(3 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_5_t is
array (natural range <>) of std_logic_vector(4 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_6_t is
array (natural range <>) of std_logic_vector(5 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_7_t is
array (natural range <>) of std_logic_vector(6 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_8_t is
array (natural range <>) of std_logic_vector(7 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_9_t is
array (natural range <>) of std_logic_vector(8 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_10_t is
array (natural range <>) of std_logic_vector(9 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_11_t is
array (natural range <>) of std_logic_vector(10 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_12_t is
array (natural range <>) of std_logic_vector(11 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_13_t is
array (natural range <>) of std_logic_vector(12 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_14_t is
array (natural range <>) of std_logic_vector(13 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_15_t is
array (natural range <>) of std_logic_vector(14 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_16_t is
array (natural range <>) of std_logic_vector(15 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_24_t is
array (natural range <>) of std_logic_vector(23 downto 0);
type WasmFpgaBus_arr_of_std_logic_vector_32_t is
array (natural range <>) of std_logic_vector(31 downto 0);
type T_WasmFpgaBusWshBnDn is
record
Adr : std_logic_vector(23 downto 0);
Sel : std_logic_vector(3 downto 0);
DatIn : std_logic_vector(31 downto 0);
We : std_logic;
Stb : std_logic;
Cyc : std_logic_vector(0 downto 0);
end record;
type array_of_T_WasmFpgaBusWshBnDn is
array (natural range <>) of T_WasmFpgaBusWshBnDn;
type T_WasmFpgaBusWshBnUp is
record
DatOut : std_logic_vector(31 downto 0);
Ack : std_logic;
end record;
type array_of_T_WasmFpgaBusWshBnUp is
array (natural range <>) of T_WasmFpgaBusWshBnUp;
type T_WasmFpgaBusWshBn_UnOccpdRcrd is
record
forRecord_Adr : std_logic_vector(23 downto 0);
forRecord_Sel : std_logic_vector(3 downto 0);
forRecord_We : std_logic;
forRecord_Cyc : std_logic_vector(0 downto 0);
Unoccupied_Ack : std_logic;
end record;
type array_of_T_WasmFpgaBusWshBn_UnOccpdRcrd is
array (natural range <>) of T_WasmFpgaBusWshBn_UnOccpdRcrd;
type T_WasmFpgaBusWshBn_BusBlk is
record
ModuleArea_Adr : std_logic_vector(23 downto 0);
ModuleArea_Sel : std_logic_vector(3 downto 0);
ModuleArea_We : std_logic;
ModuleArea_Stb : std_logic;
ModuleArea_DatOut : std_logic_vector(31 downto 0);
ModuleArea_Cyc : std_logic;
StackArea_Adr : std_logic_vector(23 downto 0);
StackArea_Sel : std_logic_vector(3 downto 0);
StackArea_We : std_logic;
StackArea_Stb : std_logic;
StackArea_DatOut : std_logic_vector(31 downto 0);
StackArea_Cyc : std_logic;
StoreArea_Adr : std_logic_vector(23 downto 0);
StoreArea_Sel : std_logic_vector(3 downto 0);
StoreArea_We : std_logic;
StoreArea_Stb : std_logic;
StoreArea_DatOut : std_logic_vector(31 downto 0);
StoreArea_Cyc : std_logic;
MemoryArea_Adr : std_logic_vector(23 downto 0);
MemoryArea_Sel : std_logic_vector(3 downto 0);
MemoryArea_We : std_logic;
MemoryArea_Stb : std_logic;
MemoryArea_DatOut : std_logic_vector(31 downto 0);
MemoryArea_Cyc : std_logic;
end record;
type array_of_T_WasmFpgaBusWshBn_BusBlk is
array (natural range <>) of T_WasmFpgaBusWshBn_BusBlk;
type T_BusBlk_WasmFpgaBusWshBn is
record
ModuleArea_DatIn: std_logic_vector(31 downto 0);
ModuleArea_Ack : std_logic;
StackArea_DatIn: std_logic_vector(31 downto 0);
StackArea_Ack : std_logic;
StoreArea_DatIn: std_logic_vector(31 downto 0);
StoreArea_Ack : std_logic;
MemoryArea_DatIn: std_logic_vector(31 downto 0);
MemoryArea_Ack : std_logic;
end record;
type array_of_T_BusBlk_WasmFpgaBusWshBn is
array (natural range <>) of T_BusBlk_WasmFpgaBusWshBn;
-- ---------- WebAssembly Bus Block( BusBlk ) ----------
-- BUS:
constant WASMFPGABUS_ADR_BLK_BASE_BusBlk : std_logic_vector(23 downto 0) := x"000000";
constant WASMFPGABUS_ADR_BLK_SIZE_BusBlk : std_logic_vector(23 downto 0) := x"020000";
-- ModuleArea: WebAssembly Module
constant WASMFPGABUS_ADR_BASE_ModuleArea : std_logic_vector(23 downto 0) := std_logic_vector(x"000000" + unsigned(WASMFPGABUS_ADR_BLK_BASE_BusBlk));
constant WASMFPGABUS_ADR_SIZE_ModuleArea : std_logic_vector(23 downto 0) := x"000100";
-- StackArea: WebAssembly Stack
constant WASMFPGABUS_ADR_BASE_StackArea : std_logic_vector(23 downto 0) := std_logic_vector(x"000100" + unsigned(WASMFPGABUS_ADR_BLK_BASE_BusBlk));
constant WASMFPGABUS_ADR_SIZE_StackArea : std_logic_vector(23 downto 0) := x"000100";
-- StoreArea: WebAssembly Store
constant WASMFPGABUS_ADR_BASE_StoreArea : std_logic_vector(23 downto 0) := std_logic_vector(x"000200" + unsigned(WASMFPGABUS_ADR_BLK_BASE_BusBlk));
constant WASMFPGABUS_ADR_SIZE_StoreArea : std_logic_vector(23 downto 0) := x"000100";
-- MemoryArea: WebAssembly Memory Index 0 (1 Page)
constant WASMFPGABUS_ADR_BASE_MemoryArea : std_logic_vector(23 downto 0) := std_logic_vector(x"010000" + unsigned(WASMFPGABUS_ADR_BLK_BASE_BusBlk));
constant WASMFPGABUS_ADR_SIZE_MemoryArea : std_logic_vector(23 downto 0) := x"010003";
end WasmFpgaBusWshBn_Package;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FORWARDING_UNIT is
port(
EX_MEM_REGWRITE : in STD_LOGIC;
MEM_WB_REGWRITE : in STD_LOGIC;
ID_EX_RS : in STD_LOGIC_VECTOR(4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR(4 downto 0);
EX_MEM_RD : in STD_LOGIC_VECTOR(4 downto 0);
MEM_WB_RD : in STD_LOGIC_VECTOR(4 downto 0);
MUX_A : out STD_LOGIC_VECTOR(1 downto 0);
MUX_B : out STD_LOGIC_VECTOR(1 downto 0)
);
end FORWARDING_UNIT;
architecture behaviour of FORWARDING_UNIT is
--Signals
--Variables
begin
forwarder : process (ID_EX_RS, ID_EX_RT)
begin
--EX FORWARDING--
if((EX_MEM_REGWRITE = '1') AND (EX_MEM_RD /= "00000") AND (EX_MEM_RD = ID_EX_RS)) then
MUX_A <= "10";
elsif((EX_MEM_REGWRITE = '1') AND (EX_MEM_RD /= "00000") AND (EX_MEM_RD = ID_EX_RT)) then
MUX_B <= "10";
--MEM FORWARDING--
elsif((MEM_WB_REGWRITE = '1') AND (MEM_WB_RD /= "00000") AND NOT((EX_MEM_REGWRITE = '1') AND (EX_MEM_RD /= "00000") AND (EX_MEM_RD /= ID_EX_RS)) AND (MEM_WB_RD = ID_EX_RS)) then
MUX_A <= "01";
elsif((MEM_WB_REGWRITE = '1') AND (MEM_WB_RD /= "00000") AND NOT ((EX_MEM_REGWRITE = '1') AND (EX_MEM_RD /= "00000") AND (EX_MEM_RD /= ID_EX_RT)) AND (MEM_WB_RD = ID_EX_RT)) then
MUX_B <= "01";
else
MUX_A <= "00";
MUX_B <= "00";
end if;
end process forwarder;
end behaviour;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01/05/2018 03:46:37 PM
-- Design Name:
-- Module Name: uart_mock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_mock is
Port ( o_RX_DV : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR (7 downto 0);
i_clk : in std_logic;
i_fifo_full: in std_logic);
end uart_mock;
architecture Behavioral of uart_mock is
signal wr_enable: std_logic :='0';
begin
process(i_clk) begin
if rising_edge(i_clk) then
o_RX_Byte <= B"01010101";
if i_fifo_full = '0' then
o_RX_DV <= '1';
wr_enable <= '1';
end if;
end if;
end process;
process(i_clk) begin
if rising_edge(i_clk) AND wr_enable='1' then
o_RX_DV <='0';
wr_enable<='0';
end if;
end process;
end Behavioral;
|
<gh_stars>1-10
---------------------------------------------------------------------------
-- Component:
-- Router Channel Receiver
-- Purpose:
-- Router component that handles all inbound traffic on a single link.
--
-- Requires: VHDL-2008
--
-- Written on Jan 26/2021, Updated on May 15/2021
-- Copyright 2021 <NAME>
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
---------------------------------------------------------------------------
-- Library declarations
library ieee;
library work;
-- Use packages
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rx_componentspkg.all;
use work.fifo_componentspkg.all;
use work.noc_parameterspkg.all;
entity rx_top is
generic(
addressWidth : integer := ADDR_DATA_SIZE;
fifoWidth : integer := CHANNEL_DATA_SIZE;
fifoDepth : integer := FIFO_DEPTH
);
port(
-- Basic control signals
clk, rst, networkMode : in std_logic;
-- Packet Define
rx_packet_in : in packet_t;
rx_packet_out : out packet_t;
-- Channel Controls
rx_clearToSend : out clearToSend_t;
rx_channelValid : in channelValid_t;
-- Crossbar Side
channelA_dataAvailable, channelB_dataAvailable : out std_logic;
channelA_popRqst, channelB_popRqst : in std_logic;
rx_ChannelA_select, rx_channelB_select : in std_logic
);
end rx_top;
-- Architecture
architecture rx_top_impl of rx_top is
-- Channel A Signals
signal channelA_popEn_i, channelA_writeEn_i : std_logic;
signal channelA_fifoFull_i, channelA_fifoEmpty_i : std_logic;
-- Signals for concatenation
signal rx_channelA_fifo_in, rx_channelA_fifo_out : std_logic_vector (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE - 1 downto 0);
-- Channel B Signals
signal channelB_popEn_i, channelB_writeEn_i : std_logic;
signal channelB_fifoFull_i, channelB_fifoEmpty_i : std_logic;
-- Signals for concatenation
signal rx_channelB_fifo_in, rx_channelB_fifo_out : std_logic_vector (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE - 1 downto 0);
begin
-- Concatenate everything (Channel A)
rx_channelA_fifo_in (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE - 1 downto ADDR_DATA_SIZE) <= rx_packet_in.dataA;
rx_channelA_fifo_in (ADDR_DATA_SIZE - 1 downto 0) <= rx_packet_in.addrA;
rx_packet_out.dataA <= rx_channelA_fifo_out (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE - 1 downto ADDR_DATA_SIZE);
rx_packet_out.addrA <= rx_channelA_fifo_out (ADDR_DATA_SIZE - 1 downto 0);
-- Concatenate everything (Channel B)
rx_channelB_fifo_in (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE - 1 downto ADDR_DATA_SIZE) <= rx_packet_in.dataB;
rx_channelB_fifo_in (ADDR_DATA_SIZE - 1 downto 0) <= rx_packet_in.addrB;
rx_packet_out.dataB <= rx_channelB_fifo_out (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE - 1 downto ADDR_DATA_SIZE);
rx_packet_out.addrB <= rx_channelB_fifo_out (ADDR_DATA_SIZE - 1 downto 0);
-------------------------------------------
----------- Entity Instantiation ----------
-------------------------------------------
-- Channel A
channelA_FIFO: fifo_normal
generic map
(fifoWidth => (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE), fifoDepth => fifoDepth)
port map (clk => clk, rst => rst, popEn => channelA_popEn_i,
writeEn => channelA_writeEn_i, fifo_full => channelA_fifoFull_i,
fifo_empty => channelA_fifoEmpty_i, dataIn => rx_channelA_fifo_in,
dataOut => rx_channelA_fifo_out);
-- Channel B
channelB_FIFO: fifo_normal
generic map
(fifoWidth => (ADDR_DATA_SIZE + CHANNEL_DATA_SIZE), fifoDepth => fifoDepth)
port map (clk => clk, rst => rst, popEn => channelB_popEn_i,
writeEn => channelB_writeEn_i, fifo_full => channelB_fifoFull_i,
fifo_empty => channelB_fifoEmpty_i, dataIn => rx_channelB_fifo_in,
dataOut => rx_channelB_fifo_out);
-- FSMs
channelB_write_fsm: rx_writefsm
port map
(clk => clk, rst => rst,
fifo_full => channelB_fifoFull_i, fifo_writeEn => channelB_writeEn_i,
rx_channelValid => rx_channelValid.channelValidB,
rx_clearToSend => rx_clearToSend.clearToSendB);
channelA_write_fsm: rx_writefsm
port map
(clk => clk, rst => rst,
fifo_full => channelA_fifoFull_i, fifo_writeEn => channelA_writeEn_i,
rx_channelValid => rx_channelValid.channelValidA,
rx_clearToSend => rx_clearToSend.clearToSendA);
channelB_read_fsm: rx_readfsm
port map
(clk => clk, rst => rst,
fifo_empty => channelB_fifoEmpty_i, fifo_popEn => channelB_popEn_i,
fifo_popRqst => channelB_popRqst, rx_select => rx_channelB_select,
dataAvailable => channelB_DataAvailable);
channelA_read_fsm: rx_readfsm
port map
(clk => clk, rst => rst,
fifo_empty => channelA_fifoEmpty_i, fifo_popEn => channelA_popEn_i,
fifo_popRqst => channelA_popRqst, rx_select => rx_channelA_select,
dataAvailable => channelA_DataAvailable);
end rx_top_impl;
|
-------------------------------------------------------------------------------
-- Title : SSI Protocol: https://confluence.slac.stanford.edu/x/0oyfD
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: This module generates
-- PseudoRandom Binary Sequence (PRBS) on Virtual Channel Lane.
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
use surf.AxiStreamPkg.all;
use surf.SsiPkg.all;
entity SsiPrbsTx is
generic (
-- General Configurations
TPD_G : time := 1 ns;
AXI_EN_G : sl := '1';
AXI_DEFAULT_PKT_LEN_G : slv(31 downto 0) := x"00000FFF";
AXI_DEFAULT_TRIG_DLY_G : slv(31 downto 0) := x"00000000";
-- FIFO Configurations
VALID_THOLD_G : natural := 1;
VALID_BURST_MODE_G : boolean := false;
SYNTH_MODE_G : string := "inferred";
MEMORY_TYPE_G : string := "block";
GEN_SYNC_FIFO_G : boolean := false;
CASCADE_SIZE_G : positive := 1;
FIFO_ADDR_WIDTH_G : positive := 9;
FIFO_PAUSE_THRESH_G : positive := 2**8;
-- PRBS Configurations
PRBS_SEED_SIZE_G : natural range 32 to 512 := 32;
PRBS_TAPS_G : NaturalArray := (0 => 31, 1 => 6, 2 => 2, 3 => 1);
PRBS_INCREMENT_G : boolean := false; -- Increment mode by default instead of PRBS
-- AXI Stream Configurations
MASTER_AXI_STREAM_CONFIG_G : AxiStreamConfigType;
MASTER_AXI_PIPE_STAGES_G : natural range 0 to 16 := 0);
port (
-- Master Port (mAxisClk)
mAxisClk : in sl;
mAxisRst : in sl;
mAxisMaster : out AxiStreamMasterType;
mAxisSlave : in AxiStreamSlaveType;
-- Trigger Signal (locClk domain)
locClk : in sl;
locRst : in sl := '0';
trig : in sl := '1';
packetLength : in slv(31 downto 0) := x"00000FFF";
forceEofe : in sl := '0';
busy : out sl;
tDest : in slv(7 downto 0) := X"00";
tId : in slv(7 downto 0) := X"00";
-- Optional: Axi-Lite Register Interface (locClk domain)
axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
axilWriteSlave : out AxiLiteWriteSlaveType);
end SsiPrbsTx;
architecture rtl of SsiPrbsTx is
constant PRBS_BYTES_C : natural := wordCount(PRBS_SEED_SIZE_G, 8);
constant PRBS_SSI_CONFIG_C : AxiStreamConfigType := (
TSTRB_EN_C => false,
TDATA_BYTES_C => PRBS_BYTES_C,
TDEST_BITS_C => 8,
TID_BITS_C => 8,
TKEEP_MODE_C => MASTER_AXI_STREAM_CONFIG_G.TKEEP_MODE_C,
TUSER_BITS_C => 2,
TUSER_MODE_C => MASTER_AXI_STREAM_CONFIG_G.TUSER_MODE_C);
type StateType is (
IDLE_S,
SEED_RAND_S,
LENGTH_S,
DATA_S);
type RegType is record
busy : sl;
overflow : sl;
length : slv(31 downto 0);
packetLength : slv(31 downto 0);
dataCnt : slv(31 downto 0);
trigDly : slv(31 downto 0);
trigDlyCnt : slv(31 downto 0);
eventCnt : slv(PRBS_SEED_SIZE_G-1 downto 0);
randomData : slv(PRBS_SEED_SIZE_G-1 downto 0);
txAxisMaster : AxiStreamMasterType;
state : StateType;
axiEn : sl;
oneShot : sl;
trig : sl;
trigger : sl;
cntData : sl;
tDest : slv(7 downto 0);
tId : slv(7 downto 0);
axilReadSlave : AxiLiteReadSlaveType;
axilWriteSlave : AxiLiteWriteSlaveType;
end record;
constant REG_INIT_C : RegType := (
busy => '1',
overflow => '0',
length => (others => '0'),
packetLength => AXI_DEFAULT_PKT_LEN_G,
dataCnt => (others => '0'),
trigDly => AXI_DEFAULT_TRIG_DLY_G,
trigDlyCnt => (others => '0'),
eventCnt => toSlv(1, PRBS_SEED_SIZE_G),
randomData => (others => '0'),
txAxisMaster => AXI_STREAM_MASTER_INIT_C,
state => IDLE_S,
axiEn => AXI_EN_G,
oneShot => '0',
trig => '0',
trigger => '0',
cntData => toSl(PRBS_INCREMENT_G),
tDest => X"00",
tId => X"00",
axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C,
axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal txSlave : AxiStreamSlaveType;
signal txCtrl : AxiStreamCtrlType;
begin
assert ((PRBS_SEED_SIZE_G = 32) or (PRBS_SEED_SIZE_G = 64) or (PRBS_SEED_SIZE_G = 128) or (PRBS_SEED_SIZE_G = 256) or (PRBS_SEED_SIZE_G = 512)) report "PRBS_SEED_SIZE_G must be either [32,64,128,256,512]" severity failure;
comb : process (axilReadMaster, axilWriteMaster, forceEofe, locRst,
packetLength, r, tDest, tId, trig, txCtrl, txSlave) is
variable v : RegType;
variable axilStatus : AxiLiteStatusType;
variable axilWriteResp : slv(1 downto 0);
variable axilReadResp : slv(1 downto 0);
begin
-- Latch the current value
v := r;
----------------------------------------------------------------------------------------------
-- Axi-Lite interface
----------------------------------------------------------------------------------------------
axiSlaveWaitTxn(axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave, axilStatus);
if (axilStatus.writeEnable = '1') then
axilWriteResp := ite(axilWriteMaster.awaddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C);
case (axilWriteMaster.awaddr(7 downto 0)) is
when X"00" =>
v.axiEn := axilWriteMaster.wdata(0);
v.trig := axilWriteMaster.wdata(1);
-- BIT2 reserved for busy
-- BIT3 reserved for overflow
-- BIT4 reserved
v.cntData := axilWriteMaster.wdata(5);
when X"04" =>
v.packetLength := axilWriteMaster.wdata(31 downto 0);
when X"08" =>
v.tDest := axilWriteMaster.wdata(7 downto 0);
v.tId := axilWriteMaster.wdata(15 downto 8);
when X"18" =>
v.oneShot := axilWriteMaster.wdata(0);
when X"1C" =>
v.trigDly := axilWriteMaster.wdata(31 downto 0);
when others =>
axilWriteResp := AXI_RESP_DECERR_C;
end case;
axiSlaveWriteResponse(v.axilWriteSlave);
end if;
if (axilStatus.readEnable = '1') then
axilReadResp := ite(axilReadMaster.araddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C);
case (axilReadMaster.araddr(7 downto 0)) is
when X"00" =>
v.axilReadSlave.rdata(0) := r.axiEn;
v.axilReadSlave.rdata(1) := r.trig;
v.axilReadSlave.rdata(2) := r.busy;
v.axilReadSlave.rdata(3) := r.overflow;
-- BIT4 reserved
v.axilReadSlave.rdata(5) := r.cntData;
when X"04" =>
v.axilReadSlave.rdata(31 downto 0) := r.packetLength;
when X"08" =>
v.axilReadSlave.rdata(7 downto 0) := r.tDest;
v.axilReadSlave.rdata(15 downto 8) := r.tId;
when X"0C" =>
v.axilReadSlave.rdata(31 downto 0) := r.dataCnt;
when X"10" =>
if (PRBS_SEED_SIZE_G < 32) then
v.axilReadSlave.rdata(PRBS_SEED_SIZE_G-1 downto 0) := r.eventCnt;
else
v.axilReadSlave.rdata(31 downto 0) := r.eventCnt(31 downto 0);
end if;
when X"14" =>
if (PRBS_SEED_SIZE_G < 32) then
v.axilReadSlave.rdata(PRBS_SEED_SIZE_G-1 downto 0) := r.randomData;
else
v.axilReadSlave.rdata(31 downto 0) := r.randomData(31 downto 0);
end if;
when X"1C" =>
v.axilReadSlave.rdata(31 downto 0):= r.trigDly;
when others =>
axilReadResp := AXI_RESP_DECERR_C;
end case;
axiSlaveReadResponse(v.axilReadSlave);
end if;
-- Check for delay between AXI triggers
if (r.trigDlyCnt = r.trigDly) or (r.trigDly /= v.trigDly) then
v.trigDlyCnt := (others=>'0');
v.trigger := r.trig;
elsif (r.trigger = '0') then
v.trigDlyCnt := r.trigDlyCnt + 1;
end if;
-- Override axi settings if axi not enabled
if (v.axiEn = '0') then
v.trigger := trig;
v.packetLength := packetLength;
v.tDest := tDest;
v.tId := tId;
end if;
-- Check for overflow condition or forced EOFE
if (txCtrl.overflow = '1') or (forceEofe = '1') then
-- Latch the overflow error bit for the data packet
v.overflow := '1';
end if;
-- Check the AXIS flow control
if txSlave.tReady = '1' then
v.txAxisMaster.tValid := '0';
v.txAxisMaster.tLast := '0';
v.txAxisMaster.tUser := (others => '0');
v.txAxisMaster.tKeep := (others => '1');
end if;
-- State Machine
case (r.state) is
----------------------------------------------------------------------
when IDLE_S =>
-- Reset the busy flag
v.busy := '0';
-- Check for a trigger
if (r.trigger = '1') or (r.oneShot = '1') then
-- Reset the one shot
v.oneShot := '0';
v.trigger := '0';
-- Latch the generator seed
v.randomData := r.eventCnt;
-- Set the busy flag
v.busy := '1';
-- Reset the overflow flag
v.overflow := '0';
-- Latch the configuration
v.txAxisMaster.tDest := r.tDest;
v.txAxisMaster.tId := r.tId;
-- Check the packet length request value
if r.packetLength = 0 then
-- Force minimum packet length of 2 (+1)
v.length := toSlv(2, 32);
elsif r.packetLength = 1 then
-- Force minimum packet length of 2 (+1)
v.length := toSlv(2, 32);
else
v.length := r.packetLength;
end if;
-- Next State
v.state := SEED_RAND_S;
end if;
----------------------------------------------------------------------
when SEED_RAND_S =>
-- Check if the FIFO is ready
if v.txAxisMaster.tvalid = '0' then
-- Send the random seed word
v.txAxisMaster.tvalid := '1';
v.txAxisMaster.tData(PRBS_SEED_SIZE_G-1 downto 0) := r.eventCnt;
-- Generate the next random data word
-- for i in 0 to PRBS_SEED_SIZE_G-1 loop
v.randomData := lfsrShift(v.randomData, PRBS_TAPS_G, '0');
-- end loop;
-- Increment the counter
v.eventCnt := r.eventCnt + 1;
-- Increment the counter
v.dataCnt := r.dataCnt + 1;
-- Set the SOF bit
ssiSetUserSof(PRBS_SSI_CONFIG_C, v.txAxisMaster, '1');
-- Next State
v.state := LENGTH_S;
end if;
----------------------------------------------------------------------
when LENGTH_S =>
-- Check if the FIFO is ready
if v.txAxisMaster.tvalid = '0' then
-- Send the upper packetLength value
v.txAxisMaster.tvalid := '1';
v.txAxisMaster.tData := (others => '0');
v.txAxisMaster.tData(31 downto 0) := r.length;
-- Increment the counter
v.dataCnt := r.dataCnt + 1;
-- Next State
v.state := DATA_S;
end if;
----------------------------------------------------------------------
when DATA_S =>
-- Check if the FIFO is ready
if v.txAxisMaster.tvalid = '0' then
-- Send the random data word
v.txAxisMaster.tValid := '1';
-- Check if we are sending PRBS or counter data
if r.cntData = '0' then
-- PRBS data
v.txAxisMaster.tData(PRBS_SEED_SIZE_G-1 downto 0) := r.randomData;
else
-- Counter data
v.txAxisMaster.tData(PRBS_SEED_SIZE_G-1 downto 0) := (others => '0');
v.txAxisMaster.tData(31 downto 0) := r.dataCnt;
end if;
-- Generate the next random data word
-- for i in 0 to PRBS_SEED_SIZE_G-1 loop
v.randomData := lfsrShift(v.randomData, PRBS_TAPS_G, '0');
-- end loop;
-- Increment the counter
v.dataCnt := r.dataCnt + 1;
-- Check the counter
if r.dataCnt = r.length then
-- Reset the counter
v.dataCnt := (others => '0');
-- Set the EOF bit
v.txAxisMaster.tLast := '1';
-- Set the EOFE bit
ssiSetUserEofe(PRBS_SSI_CONFIG_C, v.txAxisMaster, r.overflow);
-- Reset the busy flag
v.busy := '0';
-- Next State
v.state := IDLE_S;
end if;
end if;
----------------------------------------------------------------------
end case;
-- Reset
if (locRst = '1') then
v := REG_INIT_C;
end if;
-- Register the variable for next clock cycle
rin <= v;
-- Outputs
busy <= r.busy;
axilReadSlave <= r.axilReadSlave;
axilWriteSlave <= r.axilWriteSlave;
end process comb;
seq : process (locClk) is
begin
if rising_edge(locClk) then
r <= rin after TPD_G;
end if;
end process seq;
AxiStreamFifo_Inst : entity surf.AxiStreamFifoV2
generic map(
-- General Configurations
TPD_G => TPD_G,
INT_PIPE_STAGES_G => MASTER_AXI_PIPE_STAGES_G,
PIPE_STAGES_G => MASTER_AXI_PIPE_STAGES_G,
SLAVE_READY_EN_G => true,
VALID_THOLD_G => VALID_THOLD_G,
VALID_BURST_MODE_G => VALID_BURST_MODE_G,
-- FIFO configurations
SYNTH_MODE_G => SYNTH_MODE_G,
MEMORY_TYPE_G => MEMORY_TYPE_G,
GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G,
CASCADE_SIZE_G => CASCADE_SIZE_G,
FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G,
FIFO_FIXED_THRESH_G => true,
FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH_G,
CASCADE_PAUSE_SEL_G => (CASCADE_SIZE_G-1),
-- AXI Stream Port Configurations
SLAVE_AXI_CONFIG_G => PRBS_SSI_CONFIG_C,
MASTER_AXI_CONFIG_G => MASTER_AXI_STREAM_CONFIG_G)
port map (
-- Slave Port
sAxisClk => locClk,
sAxisRst => locRst,
sAxisMaster => r.txAxisMaster,
sAxisSlave => txSlave,
sAxisCtrl => txCtrl,
-- Master Port
mAxisClk => mAxisClk,
mAxisRst => mAxisRst,
mAxisMaster => mAxisMaster,
mAxisSlave => mAxisSlave);
end rtl;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
-- Date : Mon Mar 26 12:18:02 2018
-- Host : dots running 64-bit Ubuntu 16.04.4 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/gokul/playground/ece594bb/fpgacc/vcnn/vcnn.srcs/sources_1/bd/vcnnbd/ip/vcnnbd_conv1l_top_0_0/vcnnbd_conv1l_top_0_0_sim_netlist.vhdl
-- Design : vcnnbd_conv1l_top_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_a_tvalid : in STD_LOGIC;
s_axis_a_tready : out STD_LOGIC;
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_a_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_a_tlast : in STD_LOGIC;
s_axis_b_tvalid : in STD_LOGIC;
s_axis_b_tready : out STD_LOGIC;
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_b_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_b_tlast : in STD_LOGIC;
s_axis_c_tvalid : in STD_LOGIC;
s_axis_c_tready : out STD_LOGIC;
s_axis_c_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_c_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_c_tlast : in STD_LOGIC;
s_axis_operation_tvalid : in STD_LOGIC;
s_axis_operation_tready : out STD_LOGIC;
s_axis_operation_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_operation_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_operation_tlast : in STD_LOGIC;
m_axis_result_tvalid : out STD_LOGIC;
m_axis_result_tready : in STD_LOGIC;
m_axis_result_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_result_tuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_result_tlast : out STD_LOGIC
);
attribute C_ACCUM_INPUT_MSB : integer;
attribute C_ACCUM_INPUT_MSB of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 15;
attribute C_ACCUM_LSB : integer;
attribute C_ACCUM_LSB of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is -24;
attribute C_ACCUM_MSB : integer;
attribute C_ACCUM_MSB of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 32;
attribute C_A_FRACTION_WIDTH : integer;
attribute C_A_FRACTION_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 11;
attribute C_A_TDATA_WIDTH : integer;
attribute C_A_TDATA_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_A_TUSER_WIDTH : integer;
attribute C_A_TUSER_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_BRAM_USAGE : integer;
attribute C_BRAM_USAGE of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_B_FRACTION_WIDTH : integer;
attribute C_B_FRACTION_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 11;
attribute C_B_TDATA_WIDTH : integer;
attribute C_B_TDATA_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_B_TUSER_WIDTH : integer;
attribute C_B_TUSER_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_COMPARE_OPERATION : integer;
attribute C_COMPARE_OPERATION of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 8;
attribute C_C_FRACTION_WIDTH : integer;
attribute C_C_FRACTION_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 11;
attribute C_C_TDATA_WIDTH : integer;
attribute C_C_TDATA_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_C_TUSER_WIDTH : integer;
attribute C_C_TUSER_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_C_WIDTH : integer;
attribute C_C_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_FIXED_DATA_UNSIGNED : integer;
attribute C_FIXED_DATA_UNSIGNED of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ABSOLUTE : integer;
attribute C_HAS_ABSOLUTE of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ACCUMULATOR_A : integer;
attribute C_HAS_ACCUMULATOR_A of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ACCUMULATOR_S : integer;
attribute C_HAS_ACCUMULATOR_S of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ACCUM_INPUT_OVERFLOW : integer;
attribute C_HAS_ACCUM_INPUT_OVERFLOW of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ACCUM_OVERFLOW : integer;
attribute C_HAS_ACCUM_OVERFLOW of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ADD : integer;
attribute C_HAS_ADD of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_A_TLAST : integer;
attribute C_HAS_A_TLAST of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_A_TUSER : integer;
attribute C_HAS_A_TUSER of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_B : integer;
attribute C_HAS_B of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_HAS_B_TLAST : integer;
attribute C_HAS_B_TLAST of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_B_TUSER : integer;
attribute C_HAS_B_TUSER of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_C : integer;
attribute C_HAS_C of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_HAS_COMPARE : integer;
attribute C_HAS_COMPARE of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_C_TLAST : integer;
attribute C_HAS_C_TLAST of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_C_TUSER : integer;
attribute C_HAS_C_TUSER of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_DIVIDE : integer;
attribute C_HAS_DIVIDE of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_DIVIDE_BY_ZERO : integer;
attribute C_HAS_DIVIDE_BY_ZERO of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_EXPONENTIAL : integer;
attribute C_HAS_EXPONENTIAL of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_FIX_TO_FLT : integer;
attribute C_HAS_FIX_TO_FLT of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_FLT_TO_FIX : integer;
attribute C_HAS_FLT_TO_FIX of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_FLT_TO_FLT : integer;
attribute C_HAS_FLT_TO_FLT of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_FMA : integer;
attribute C_HAS_FMA of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_HAS_FMS : integer;
attribute C_HAS_FMS of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_INVALID_OP : integer;
attribute C_HAS_INVALID_OP of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_LOGARITHM : integer;
attribute C_HAS_LOGARITHM of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_MULTIPLY : integer;
attribute C_HAS_MULTIPLY of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_OPERATION : integer;
attribute C_HAS_OPERATION of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_OPERATION_TLAST : integer;
attribute C_HAS_OPERATION_TLAST of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_OPERATION_TUSER : integer;
attribute C_HAS_OPERATION_TUSER of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_HAS_RECIP : integer;
attribute C_HAS_RECIP of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_RECIP_SQRT : integer;
attribute C_HAS_RECIP_SQRT of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_RESULT_TLAST : integer;
attribute C_HAS_RESULT_TLAST of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_RESULT_TUSER : integer;
attribute C_HAS_RESULT_TUSER of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_HAS_SQRT : integer;
attribute C_HAS_SQRT of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_SUBTRACT : integer;
attribute C_HAS_SUBTRACT of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_MULT_USAGE : integer;
attribute C_MULT_USAGE of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_OPERATION_TDATA_WIDTH : integer;
attribute C_OPERATION_TDATA_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 8;
attribute C_OPERATION_TUSER_WIDTH : integer;
attribute C_OPERATION_TUSER_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_OPTIMIZATION : integer;
attribute C_OPTIMIZATION of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_RATE : integer;
attribute C_RATE of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 1;
attribute C_RESULT_FRACTION_WIDTH : integer;
attribute C_RESULT_FRACTION_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 11;
attribute C_RESULT_TDATA_WIDTH : integer;
attribute C_RESULT_TDATA_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_RESULT_TUSER_WIDTH : integer;
attribute C_RESULT_TUSER_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 2;
attribute C_RESULT_WIDTH : integer;
attribute C_RESULT_WIDTH of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 16;
attribute C_THROTTLE_SCHEME : integer;
attribute C_THROTTLE_SCHEME of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 4;
attribute C_TLAST_RESOLUTION : integer;
attribute C_TLAST_RESOLUTION of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is "zynq";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 : entity is "floating_point_v7_1_4";
end vcnnbd_conv1l_top_0_0_floating_point_v7_1_4;
architecture STRUCTURE of vcnnbd_conv1l_top_0_0_floating_point_v7_1_4 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_synth_m_axis_result_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_operation_tready_UNCONNECTED : STD_LOGIC;
attribute C_ACCUM_INPUT_MSB of i_synth : label is 15;
attribute C_ACCUM_LSB of i_synth : label is -24;
attribute C_ACCUM_MSB of i_synth : label is 32;
attribute C_A_FRACTION_WIDTH of i_synth : label is 11;
attribute C_A_TDATA_WIDTH of i_synth : label is 16;
attribute C_A_TUSER_WIDTH of i_synth : label is 1;
attribute C_A_WIDTH of i_synth : label is 16;
attribute C_BRAM_USAGE of i_synth : label is 0;
attribute C_B_FRACTION_WIDTH of i_synth : label is 11;
attribute C_B_TDATA_WIDTH of i_synth : label is 16;
attribute C_B_TUSER_WIDTH of i_synth : label is 1;
attribute C_B_WIDTH of i_synth : label is 16;
attribute C_COMPARE_OPERATION of i_synth : label is 8;
attribute C_C_FRACTION_WIDTH of i_synth : label is 11;
attribute C_C_TDATA_WIDTH of i_synth : label is 16;
attribute C_C_TUSER_WIDTH of i_synth : label is 1;
attribute C_C_WIDTH of i_synth : label is 16;
attribute C_FIXED_DATA_UNSIGNED of i_synth : label is 0;
attribute C_HAS_ABSOLUTE of i_synth : label is 0;
attribute C_HAS_ACCUMULATOR_A of i_synth : label is 0;
attribute C_HAS_ACCUMULATOR_S of i_synth : label is 0;
attribute C_HAS_ACCUM_INPUT_OVERFLOW of i_synth : label is 0;
attribute C_HAS_ACCUM_OVERFLOW of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ADD of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_A_TLAST of i_synth : label is 0;
attribute C_HAS_A_TUSER of i_synth : label is 0;
attribute C_HAS_B of i_synth : label is 1;
attribute C_HAS_B_TLAST of i_synth : label is 0;
attribute C_HAS_B_TUSER of i_synth : label is 0;
attribute C_HAS_C of i_synth : label is 1;
attribute C_HAS_COMPARE of i_synth : label is 0;
attribute C_HAS_C_TLAST of i_synth : label is 0;
attribute C_HAS_C_TUSER of i_synth : label is 0;
attribute C_HAS_DIVIDE of i_synth : label is 0;
attribute C_HAS_DIVIDE_BY_ZERO of i_synth : label is 0;
attribute C_HAS_EXPONENTIAL of i_synth : label is 0;
attribute C_HAS_FIX_TO_FLT of i_synth : label is 0;
attribute C_HAS_FLT_TO_FIX of i_synth : label is 0;
attribute C_HAS_FLT_TO_FLT of i_synth : label is 0;
attribute C_HAS_FMA of i_synth : label is 1;
attribute C_HAS_FMS of i_synth : label is 0;
attribute C_HAS_INVALID_OP of i_synth : label is 0;
attribute C_HAS_LOGARITHM of i_synth : label is 0;
attribute C_HAS_MULTIPLY of i_synth : label is 0;
attribute C_HAS_OPERATION of i_synth : label is 0;
attribute C_HAS_OPERATION_TLAST of i_synth : label is 0;
attribute C_HAS_OPERATION_TUSER of i_synth : label is 0;
attribute C_HAS_OVERFLOW of i_synth : label is 1;
attribute C_HAS_RECIP of i_synth : label is 0;
attribute C_HAS_RECIP_SQRT of i_synth : label is 0;
attribute C_HAS_RESULT_TLAST of i_synth : label is 0;
attribute C_HAS_RESULT_TUSER of i_synth : label is 1;
attribute C_HAS_SQRT of i_synth : label is 0;
attribute C_HAS_SUBTRACT of i_synth : label is 0;
attribute C_HAS_UNDERFLOW of i_synth : label is 1;
attribute C_LATENCY of i_synth : label is 1;
attribute C_MULT_USAGE of i_synth : label is 1;
attribute C_OPERATION_TDATA_WIDTH of i_synth : label is 8;
attribute C_OPERATION_TUSER_WIDTH of i_synth : label is 1;
attribute C_OPTIMIZATION of i_synth : label is 1;
attribute C_RATE of i_synth : label is 1;
attribute C_RESULT_FRACTION_WIDTH of i_synth : label is 11;
attribute C_RESULT_TDATA_WIDTH of i_synth : label is 16;
attribute C_RESULT_TUSER_WIDTH of i_synth : label is 2;
attribute C_RESULT_WIDTH of i_synth : label is 16;
attribute C_THROTTLE_SCHEME of i_synth : label is 4;
attribute C_TLAST_RESOLUTION of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
m_axis_result_tlast <= \<const0>\;
s_axis_operation_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_synth: entity work.vcnnbd_conv1l_top_0_0_floating_point_v7_1_4_viv
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
m_axis_result_tdata(15 downto 0) => m_axis_result_tdata(15 downto 0),
m_axis_result_tlast => NLW_i_synth_m_axis_result_tlast_UNCONNECTED,
m_axis_result_tready => '0',
m_axis_result_tuser(1 downto 0) => m_axis_result_tuser(1 downto 0),
m_axis_result_tvalid => m_axis_result_tvalid,
s_axis_a_tdata(15 downto 0) => s_axis_a_tdata(15 downto 0),
s_axis_a_tlast => '0',
s_axis_a_tready => s_axis_a_tready,
s_axis_a_tuser(0) => '0',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_b_tdata(15 downto 0) => s_axis_b_tdata(15 downto 0),
s_axis_b_tlast => '0',
s_axis_b_tready => s_axis_b_tready,
s_axis_b_tuser(0) => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_c_tdata(15 downto 0) => s_axis_c_tdata(15 downto 0),
s_axis_c_tlast => '0',
s_axis_c_tready => s_axis_c_tready,
s_axis_c_tuser(0) => '0',
s_axis_c_tvalid => s_axis_c_tvalid,
s_axis_operation_tdata(7 downto 0) => B"00000000",
s_axis_operation_tlast => '0',
s_axis_operation_tready => NLW_i_synth_s_axis_operation_tready_UNCONNECTED,
s_axis_operation_tuser(0) => '0',
s_axis_operation_tvalid => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vcnnbd_conv1l_top_0_0_fp_mult_add_16bit is
port (
aclk : in STD_LOGIC;
s_axis_a_tvalid : in STD_LOGIC;
s_axis_a_tready : out STD_LOGIC;
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_b_tvalid : in STD_LOGIC;
s_axis_b_tready : out STD_LOGIC;
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_c_tvalid : in STD_LOGIC;
s_axis_c_tready : out STD_LOGIC;
s_axis_c_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_result_tvalid : out STD_LOGIC;
m_axis_result_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_result_tuser : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of vcnnbd_conv1l_top_0_0_fp_mult_add_16bit : entity is "fp_mult_add_16bit,floating_point_v7_1_4,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of vcnnbd_conv1l_top_0_0_fp_mult_add_16bit : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vcnnbd_conv1l_top_0_0_fp_mult_add_16bit : entity is "fp_mult_add_16bit";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of vcnnbd_conv1l_top_0_0_fp_mult_add_16bit : entity is "floating_point_v7_1_4,Vivado 2017.2";
end vcnnbd_conv1l_top_0_0_fp_mult_add_16bit;
architecture STRUCTURE of vcnnbd_conv1l_top_0_0_fp_mult_add_16bit is
signal NLW_U0_m_axis_result_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_operation_tready_UNCONNECTED : STD_LOGIC;
attribute C_ACCUM_INPUT_MSB : integer;
attribute C_ACCUM_INPUT_MSB of U0 : label is 15;
attribute C_ACCUM_LSB : integer;
attribute C_ACCUM_LSB of U0 : label is -24;
attribute C_ACCUM_MSB : integer;
attribute C_ACCUM_MSB of U0 : label is 32;
attribute C_A_FRACTION_WIDTH : integer;
attribute C_A_FRACTION_WIDTH of U0 : label is 11;
attribute C_A_TDATA_WIDTH : integer;
attribute C_A_TDATA_WIDTH of U0 : label is 16;
attribute C_A_TUSER_WIDTH : integer;
attribute C_A_TUSER_WIDTH of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 16;
attribute C_BRAM_USAGE : integer;
attribute C_BRAM_USAGE of U0 : label is 0;
attribute C_B_FRACTION_WIDTH : integer;
attribute C_B_FRACTION_WIDTH of U0 : label is 11;
attribute C_B_TDATA_WIDTH : integer;
attribute C_B_TDATA_WIDTH of U0 : label is 16;
attribute C_B_TUSER_WIDTH : integer;
attribute C_B_TUSER_WIDTH of U0 : label is 1;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_COMPARE_OPERATION : integer;
attribute C_COMPARE_OPERATION of U0 : label is 8;
attribute C_C_FRACTION_WIDTH : integer;
attribute C_C_FRACTION_WIDTH of U0 : label is 11;
attribute C_C_TDATA_WIDTH : integer;
attribute C_C_TDATA_WIDTH of U0 : label is 16;
attribute C_C_TUSER_WIDTH : integer;
attribute C_C_TUSER_WIDTH of U0 : label is 1;
attribute C_C_WIDTH : integer;
attribute C_C_WIDTH of U0 : label is 16;
attribute C_FIXED_DATA_UNSIGNED : integer;
attribute C_FIXED_DATA_UNSIGNED of U0 : label is 0;
attribute C_HAS_ABSOLUTE : integer;
attribute C_HAS_ABSOLUTE of U0 : label is 0;
attribute C_HAS_ACCUMULATOR_A : integer;
attribute C_HAS_ACCUMULATOR_A of U0 : label is 0;
attribute C_HAS_ACCUMULATOR_S : integer;
attribute C_HAS_ACCUMULATOR_S of U0 : label is 0;
attribute C_HAS_ACCUM_INPUT_OVERFLOW : integer;
attribute C_HAS_ACCUM_INPUT_OVERFLOW of U0 : label is 0;
attribute C_HAS_ACCUM_OVERFLOW : integer;
attribute C_HAS_ACCUM_OVERFLOW of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ADD : integer;
attribute C_HAS_ADD of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_A_TLAST : integer;
attribute C_HAS_A_TLAST of U0 : label is 0;
attribute C_HAS_A_TUSER : integer;
attribute C_HAS_A_TUSER of U0 : label is 0;
attribute C_HAS_B : integer;
attribute C_HAS_B of U0 : label is 1;
attribute C_HAS_B_TLAST : integer;
attribute C_HAS_B_TLAST of U0 : label is 0;
attribute C_HAS_B_TUSER : integer;
attribute C_HAS_B_TUSER of U0 : label is 0;
attribute C_HAS_C : integer;
attribute C_HAS_C of U0 : label is 1;
attribute C_HAS_COMPARE : integer;
attribute C_HAS_COMPARE of U0 : label is 0;
attribute C_HAS_C_TLAST : integer;
attribute C_HAS_C_TLAST of U0 : label is 0;
attribute C_HAS_C_TUSER : integer;
attribute C_HAS_C_TUSER of U0 : label is 0;
attribute C_HAS_DIVIDE : integer;
attribute C_HAS_DIVIDE of U0 : label is 0;
attribute C_HAS_DIVIDE_BY_ZERO : integer;
attribute C_HAS_DIVIDE_BY_ZERO of U0 : label is 0;
attribute C_HAS_EXPONENTIAL : integer;
attribute C_HAS_EXPONENTIAL of U0 : label is 0;
attribute C_HAS_FIX_TO_FLT : integer;
attribute C_HAS_FIX_TO_FLT of U0 : label is 0;
attribute C_HAS_FLT_TO_FIX : integer;
attribute C_HAS_FLT_TO_FIX of U0 : label is 0;
attribute C_HAS_FLT_TO_FLT : integer;
attribute C_HAS_FLT_TO_FLT of U0 : label is 0;
attribute C_HAS_FMA : integer;
attribute C_HAS_FMA of U0 : label is 1;
attribute C_HAS_FMS : integer;
attribute C_HAS_FMS of U0 : label is 0;
attribute C_HAS_INVALID_OP : integer;
attribute C_HAS_INVALID_OP of U0 : label is 0;
attribute C_HAS_LOGARITHM : integer;
attribute C_HAS_LOGARITHM of U0 : label is 0;
attribute C_HAS_MULTIPLY : integer;
attribute C_HAS_MULTIPLY of U0 : label is 0;
attribute C_HAS_OPERATION : integer;
attribute C_HAS_OPERATION of U0 : label is 0;
attribute C_HAS_OPERATION_TLAST : integer;
attribute C_HAS_OPERATION_TLAST of U0 : label is 0;
attribute C_HAS_OPERATION_TUSER : integer;
attribute C_HAS_OPERATION_TUSER of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 1;
attribute C_HAS_RECIP : integer;
attribute C_HAS_RECIP of U0 : label is 0;
attribute C_HAS_RECIP_SQRT : integer;
attribute C_HAS_RECIP_SQRT of U0 : label is 0;
attribute C_HAS_RESULT_TLAST : integer;
attribute C_HAS_RESULT_TLAST of U0 : label is 0;
attribute C_HAS_RESULT_TUSER : integer;
attribute C_HAS_RESULT_TUSER of U0 : label is 1;
attribute C_HAS_SQRT : integer;
attribute C_HAS_SQRT of U0 : label is 0;
attribute C_HAS_SUBTRACT : integer;
attribute C_HAS_SUBTRACT of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 1;
attribute C_MULT_USAGE : integer;
attribute C_MULT_USAGE of U0 : label is 1;
attribute C_OPERATION_TDATA_WIDTH : integer;
attribute C_OPERATION_TDATA_WIDTH of U0 : label is 8;
attribute C_OPERATION_TUSER_WIDTH : integer;
attribute C_OPERATION_TUSER_WIDTH of U0 : label is 1;
attribute C_OPTIMIZATION : integer;
attribute C_OPTIMIZATION of U0 : label is 1;
attribute C_RATE : integer;
attribute C_RATE of U0 : label is 1;
attribute C_RESULT_FRACTION_WIDTH : integer;
attribute C_RESULT_FRACTION_WIDTH of U0 : label is 11;
attribute C_RESULT_TDATA_WIDTH : integer;
attribute C_RESULT_TDATA_WIDTH of U0 : label is 16;
attribute C_RESULT_TUSER_WIDTH : integer;
attribute C_RESULT_TUSER_WIDTH of U0 : label is 2;
attribute C_RESULT_WIDTH : integer;
attribute C_RESULT_WIDTH of U0 : label is 16;
attribute C_THROTTLE_SCHEME : integer;
attribute C_THROTTLE_SCHEME of U0 : label is 4;
attribute C_TLAST_RESOLUTION : integer;
attribute C_TLAST_RESOLUTION of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.vcnnbd_conv1l_top_0_0_floating_point_v7_1_4
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
m_axis_result_tdata(15 downto 0) => m_axis_result_tdata(15 downto 0),
m_axis_result_tlast => NLW_U0_m_axis_result_tlast_UNCONNECTED,
m_axis_result_tready => '0',
m_axis_result_tuser(1 downto 0) => m_axis_result_tuser(1 downto 0),
m_axis_result_tvalid => m_axis_result_tvalid,
s_axis_a_tdata(15 downto 0) => s_axis_a_tdata(15 downto 0),
s_axis_a_tlast => '0',
s_axis_a_tready => s_axis_a_tready,
s_axis_a_tuser(0) => '0',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_b_tdata(15 downto 0) => s_axis_b_tdata(15 downto 0),
s_axis_b_tlast => '0',
s_axis_b_tready => s_axis_b_tready,
s_axis_b_tuser(0) => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_c_tdata(15 downto 0) => s_axis_c_tdata(15 downto 0),
s_axis_c_tlast => '0',
s_axis_c_tready => s_axis_c_tready,
s_axis_c_tuser(0) => '0',
s_axis_c_tvalid => s_axis_c_tvalid,
s_axis_operation_tdata(7 downto 0) => B"00000000",
s_axis_operation_tlast => '0',
s_axis_operation_tready => NLW_U0_s_axis_operation_tready_UNCONNECTED,
s_axis_operation_tuser(0) => '0',
s_axis_operation_tvalid => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vcnnbd_conv1l_top_0_0_conv1l_top is
port (
\weight_bram_rd_adddr_reg[8]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
output_bram_wr_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
input_bram_rd_en : out STD_LOGIC;
input_bram_rd_adddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
weight_bram_rd_en : out STD_LOGIC;
weight_bram_rd_adddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
output_bram_wr_wen : out STD_LOGIC;
output_bram_wr_dout : out STD_LOGIC_VECTOR ( 14 downto 0 );
ap_done : out STD_LOGIC;
ap_ready : out STD_LOGIC;
input_bram_rd_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
weight_bram_rd_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
ap_start : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 2 downto 0 );
\conv_wrows_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rstn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vcnnbd_conv1l_top_0_0_conv1l_top : entity is "conv1l_top";
end vcnnbd_conv1l_top_0_0_conv1l_top;
architecture STRUCTURE of vcnnbd_conv1l_top_0_0_conv1l_top is
signal \^ar\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal C : STD_LOGIC_VECTOR ( 4 downto 0 );
signal add_c : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^ap_done\ : STD_LOGIC;
signal ap_done_r_i_1_n_0 : STD_LOGIC;
signal ap_done_r_i_2_n_0 : STD_LOGIC;
signal \^ap_ready\ : STD_LOGIC;
signal ap_ready_r_i_1_n_0 : STD_LOGIC;
signal ap_start_r : STD_LOGIC;
signal ap_start_rr : STD_LOGIC;
signal calc_col_addr : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG : boolean;
attribute MARK_DEBUG of calc_col_addr : signal is std.standard.true;
signal calc_row_addr : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG of calc_row_addr : signal is std.standard.true;
signal col_addr_overflow : STD_LOGIC;
attribute MARK_DEBUG of col_addr_overflow : signal is std.standard.true;
signal col_addr_underflow : STD_LOGIC;
attribute MARK_DEBUG of col_addr_underflow : signal is std.standard.true;
signal conv_iaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute MARK_DEBUG of conv_iaddr : signal is std.standard.true;
signal conv_iaddr_inferred_i_10_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_11_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_12_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_13_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_14_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_15_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_16_n_1 : STD_LOGIC;
signal conv_iaddr_inferred_i_16_n_2 : STD_LOGIC;
signal conv_iaddr_inferred_i_16_n_3 : STD_LOGIC;
signal conv_iaddr_inferred_i_16_n_4 : STD_LOGIC;
signal conv_iaddr_inferred_i_16_n_5 : STD_LOGIC;
signal conv_iaddr_inferred_i_16_n_6 : STD_LOGIC;
signal conv_iaddr_inferred_i_16_n_7 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_1 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_2 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_3 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_4 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_5 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_6 : STD_LOGIC;
signal conv_iaddr_inferred_i_17_n_7 : STD_LOGIC;
signal conv_iaddr_inferred_i_18_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_19_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_1_n_1 : STD_LOGIC;
signal conv_iaddr_inferred_i_1_n_2 : STD_LOGIC;
signal conv_iaddr_inferred_i_1_n_3 : STD_LOGIC;
signal conv_iaddr_inferred_i_20_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_21_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_22_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_23_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_24_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_25_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_2_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_2_n_1 : STD_LOGIC;
signal conv_iaddr_inferred_i_2_n_2 : STD_LOGIC;
signal conv_iaddr_inferred_i_2_n_3 : STD_LOGIC;
signal conv_iaddr_inferred_i_3_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_3_n_1 : STD_LOGIC;
signal conv_iaddr_inferred_i_3_n_2 : STD_LOGIC;
signal conv_iaddr_inferred_i_3_n_3 : STD_LOGIC;
signal conv_iaddr_inferred_i_4_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_5_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_6_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_7_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_8_n_0 : STD_LOGIC;
signal conv_iaddr_inferred_i_9_n_0 : STD_LOGIC;
signal conv_ichnls : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute MARK_DEBUG of conv_ichnls : signal is std.standard.true;
signal \conv_ichnls[0]_i_1_n_0\ : STD_LOGIC;
signal \conv_ichnls[0]_i_2_n_0\ : STD_LOGIC;
signal \conv_ichnls[0]_i_3_n_0\ : STD_LOGIC;
signal \conv_ichnls[1]_i_1_n_0\ : STD_LOGIC;
signal \conv_ichnls[1]_i_2_n_0\ : STD_LOGIC;
signal \conv_ichnls[2]_i_1_n_0\ : STD_LOGIC;
signal \conv_ichnls[2]_i_2_n_0\ : STD_LOGIC;
signal \conv_ichnls[2]_i_3_n_0\ : STD_LOGIC;
signal conv_icols : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG of conv_icols : signal is std.standard.true;
signal \conv_icols[0]_i_1_n_0\ : STD_LOGIC;
signal \conv_icols[1]_i_1_n_0\ : STD_LOGIC;
signal \conv_icols[2]_i_1_n_0\ : STD_LOGIC;
signal \conv_icols[3]_i_1_n_0\ : STD_LOGIC;
signal \conv_icols[4]_i_1_n_0\ : STD_LOGIC;
signal \conv_icols[5]_i_1_n_0\ : STD_LOGIC;
signal \conv_icols[5]_i_2_n_0\ : STD_LOGIC;
signal \conv_icols[5]_i_3_n_0\ : STD_LOGIC;
signal \conv_icols[5]_i_4_n_0\ : STD_LOGIC;
signal \conv_icols[5]_i_5_n_0\ : STD_LOGIC;
signal conv_ip_zeros : STD_LOGIC;
signal conv_ip_zeros_i_1_n_0 : STD_LOGIC;
signal conv_ip_zeros_r : STD_LOGIC_VECTOR ( 1 downto 0 );
signal conv_irows : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG of conv_irows : signal is std.standard.true;
signal \conv_irows[0]_i_1_n_0\ : STD_LOGIC;
signal \conv_irows[1]_i_1_n_0\ : STD_LOGIC;
signal \conv_irows[2]_i_1_n_0\ : STD_LOGIC;
signal \conv_irows[3]_i_1_n_0\ : STD_LOGIC;
signal \conv_irows[4]_i_1_n_0\ : STD_LOGIC;
signal \conv_irows[4]_i_2_n_0\ : STD_LOGIC;
signal \conv_irows[4]_i_3_n_0\ : STD_LOGIC;
signal \conv_irows[4]_i_4_n_0\ : STD_LOGIC;
signal \conv_irows[5]_i_1_n_0\ : STD_LOGIC;
signal \conv_irows[5]_i_2_n_0\ : STD_LOGIC;
signal conv_state : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \conv_state[0]_i_1_n_0\ : STD_LOGIC;
signal \conv_state[1]_i_1_n_0\ : STD_LOGIC;
signal \conv_state[1]_i_2_n_0\ : STD_LOGIC;
signal \conv_state[1]_i_3_n_0\ : STD_LOGIC;
signal \conv_state[2]_i_1_n_0\ : STD_LOGIC;
signal \conv_state[2]_i_2_n_0\ : STD_LOGIC;
signal conv_waddr : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute MARK_DEBUG of conv_waddr : signal is std.standard.true;
signal conv_waddr_inferred_i_10_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_11_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_12_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_13_n_7 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_1 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_2 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_3 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_4 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_5 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_6 : STD_LOGIC;
signal conv_waddr_inferred_i_14_n_7 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_1 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_2 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_3 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_4 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_5 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_6 : STD_LOGIC;
signal conv_waddr_inferred_i_15_n_7 : STD_LOGIC;
signal conv_waddr_inferred_i_17_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_17_n_1 : STD_LOGIC;
signal conv_waddr_inferred_i_17_n_2 : STD_LOGIC;
signal conv_waddr_inferred_i_17_n_3 : STD_LOGIC;
signal conv_waddr_inferred_i_21_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_22_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_22_n_1 : STD_LOGIC;
signal conv_waddr_inferred_i_22_n_2 : STD_LOGIC;
signal conv_waddr_inferred_i_22_n_3 : STD_LOGIC;
signal conv_waddr_inferred_i_23_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_24_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_25_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_26_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_28_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_29_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_2_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_2_n_1 : STD_LOGIC;
signal conv_waddr_inferred_i_2_n_2 : STD_LOGIC;
signal conv_waddr_inferred_i_2_n_3 : STD_LOGIC;
signal conv_waddr_inferred_i_30_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_31_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_32_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_33_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_34_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_35_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_36_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_3_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_3_n_1 : STD_LOGIC;
signal conv_waddr_inferred_i_3_n_2 : STD_LOGIC;
signal conv_waddr_inferred_i_3_n_3 : STD_LOGIC;
signal conv_waddr_inferred_i_4_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_5_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_6_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_7_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_8_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_9_n_0 : STD_LOGIC;
signal conv_wcols : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute MARK_DEBUG of conv_wcols : signal is std.standard.true;
signal \conv_wcols[0]_i_1_n_0\ : STD_LOGIC;
signal \conv_wcols[0]_i_2_n_0\ : STD_LOGIC;
signal \conv_wcols[1]_i_1_n_0\ : STD_LOGIC;
signal \conv_wcols[2]_i_1_n_0\ : STD_LOGIC;
signal \conv_wcols[2]_i_2_n_0\ : STD_LOGIC;
signal conv_wfltrs : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute MARK_DEBUG of conv_wfltrs : signal is std.standard.true;
signal \conv_wfltrs[0]_i_1_n_0\ : STD_LOGIC;
signal \conv_wfltrs[1]_i_1_n_0\ : STD_LOGIC;
signal \conv_wfltrs[2]_i_1_n_0\ : STD_LOGIC;
signal \conv_wfltrs[3]_i_1_n_0\ : STD_LOGIC;
signal \conv_wfltrs[4]_i_1_n_0\ : STD_LOGIC;
signal \conv_wfltrs[4]_i_2_n_0\ : STD_LOGIC;
signal \conv_wfltrs[4]_i_3_n_0\ : STD_LOGIC;
signal \conv_wfltrs[4]_i_4_n_0\ : STD_LOGIC;
signal \conv_wfltrs[4]_i_5_n_0\ : STD_LOGIC;
signal conv_wrows : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute MARK_DEBUG of conv_wrows : signal is std.standard.true;
signal \conv_wrows[0]_i_1_n_0\ : STD_LOGIC;
signal \conv_wrows[1]_i_1_n_0\ : STD_LOGIC;
signal \conv_wrows[2]_i_1_n_0\ : STD_LOGIC;
signal \conv_wrows[2]_i_2_n_0\ : STD_LOGIC;
signal \conv_wrows[2]_i_3_n_0\ : STD_LOGIC;
signal conv_zero_pad_en : STD_LOGIC;
attribute MARK_DEBUG of conv_zero_pad_en : signal is std.standard.true;
signal current_col : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG of current_col : signal is std.standard.true;
signal \current_col[0]_i_1_n_0\ : STD_LOGIC;
signal \current_col[1]_i_1_n_0\ : STD_LOGIC;
signal \current_col[2]_i_1_n_0\ : STD_LOGIC;
signal \current_col[3]_i_1_n_0\ : STD_LOGIC;
signal \current_col[4]_i_1_n_0\ : STD_LOGIC;
signal \current_col[5]_i_1_n_0\ : STD_LOGIC;
signal \current_col[5]_i_2_n_0\ : STD_LOGIC;
signal current_row : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG of current_row : signal is std.standard.true;
signal \current_row[0]_i_1_n_0\ : STD_LOGIC;
signal \current_row[1]_i_1_n_0\ : STD_LOGIC;
signal \current_row[2]_i_1_n_0\ : STD_LOGIC;
signal \current_row[3]_i_1_n_0\ : STD_LOGIC;
signal \current_row[4]_i_1_n_0\ : STD_LOGIC;
signal \current_row[5]_i_1_n_0\ : STD_LOGIC;
signal \current_row[5]_i_2_n_0\ : STD_LOGIC;
signal \current_row[5]_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal in01 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal in01_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \in01_carry__0_i_10_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_11_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_12_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_13_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_1\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_2\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_3\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_4\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_5\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_6\ : STD_LOGIC;
signal \in01_carry__0_i_1_n_7\ : STD_LOGIC;
signal \in01_carry__0_i_2_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_3_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_4_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_5_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_6_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_7_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_8_n_0\ : STD_LOGIC;
signal \in01_carry__0_i_9_n_0\ : STD_LOGIC;
signal \in01_carry__0_n_0\ : STD_LOGIC;
signal \in01_carry__0_n_1\ : STD_LOGIC;
signal \in01_carry__0_n_2\ : STD_LOGIC;
signal \in01_carry__0_n_3\ : STD_LOGIC;
signal \in01_carry__1_i_1_n_0\ : STD_LOGIC;
signal \in01_carry__1_i_2_n_7\ : STD_LOGIC;
signal \in01_carry__1_i_3_n_0\ : STD_LOGIC;
signal in01_carry_i_10_n_0 : STD_LOGIC;
signal in01_carry_i_1_n_0 : STD_LOGIC;
signal in01_carry_i_1_n_1 : STD_LOGIC;
signal in01_carry_i_1_n_2 : STD_LOGIC;
signal in01_carry_i_1_n_3 : STD_LOGIC;
signal in01_carry_i_1_n_4 : STD_LOGIC;
signal in01_carry_i_1_n_5 : STD_LOGIC;
signal in01_carry_i_1_n_6 : STD_LOGIC;
signal in01_carry_i_1_n_7 : STD_LOGIC;
signal in01_carry_i_2_n_0 : STD_LOGIC;
signal in01_carry_i_3_n_0 : STD_LOGIC;
signal in01_carry_i_4_n_0 : STD_LOGIC;
signal in01_carry_i_5_n_0 : STD_LOGIC;
signal in01_carry_i_6_n_0 : STD_LOGIC;
signal in01_carry_i_7_n_0 : STD_LOGIC;
signal in01_carry_i_8_n_0 : STD_LOGIC;
signal in01_carry_i_9_n_0 : STD_LOGIC;
signal in01_carry_n_0 : STD_LOGIC;
signal in01_carry_n_1 : STD_LOGIC;
signal in01_carry_n_2 : STD_LOGIC;
signal in01_carry_n_3 : STD_LOGIC;
signal in02 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \in02_carry__0_i_1_n_0\ : STD_LOGIC;
signal \in02_carry__0_i_2_n_0\ : STD_LOGIC;
signal \in02_carry__0_i_3_n_0\ : STD_LOGIC;
signal \in02_carry__0_n_2\ : STD_LOGIC;
signal \in02_carry__0_n_3\ : STD_LOGIC;
signal in02_carry_i_1_n_0 : STD_LOGIC;
signal in02_carry_i_2_n_0 : STD_LOGIC;
signal in02_carry_i_3_n_0 : STD_LOGIC;
signal in02_carry_i_4_n_0 : STD_LOGIC;
signal in02_carry_n_0 : STD_LOGIC;
signal in02_carry_n_1 : STD_LOGIC;
signal in02_carry_n_2 : STD_LOGIC;
signal in02_carry_n_3 : STD_LOGIC;
signal \in02_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \in02_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \in02_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \in02_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \in02_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \in02_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \in02_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \input_bram_rd_adddr[11]_i_1_n_0\ : STD_LOGIC;
signal \input_bram_rd_adddr[11]_i_3_n_0\ : STD_LOGIC;
signal input_read_req : STD_LOGIC;
signal input_read_req_i_1_n_0 : STD_LOGIC;
signal input_read_req_r : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mac_o : STD_LOGIC_VECTOR ( 15 downto 0 );
signal mac_o_last : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \mac_o_last[0]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[10]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[11]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[12]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[13]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[14]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[15]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[1]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[2]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[3]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[4]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[5]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[6]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[7]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[8]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last[9]_i_1_n_0\ : STD_LOGIC;
signal mac_o_last_relu : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \mac_o_last_relu[0]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[10]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[11]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[12]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[13]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[14]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[1]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[2]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[3]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[4]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[5]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[6]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[7]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[8]_i_1_n_0\ : STD_LOGIC;
signal \mac_o_last_relu[9]_i_1_n_0\ : STD_LOGIC;
signal macinst0_n_0 : STD_LOGIC;
signal macinst0_n_1 : STD_LOGIC;
signal macinst0_n_2 : STD_LOGIC;
signal mult_a : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \mult_a[0]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[10]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[11]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[12]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[13]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[14]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[15]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[1]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[2]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[3]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[4]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[5]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[6]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[7]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[8]_i_1_n_0\ : STD_LOGIC;
signal \mult_a[9]_i_1_n_0\ : STD_LOGIC;
signal mult_b : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \mult_b[0]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[10]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[11]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[12]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[13]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[14]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[15]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[1]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[2]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[3]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[4]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[5]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[6]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[7]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[8]_i_1_n_0\ : STD_LOGIC;
signal \mult_b[9]_i_1_n_0\ : STD_LOGIC;
signal multadd_en : STD_LOGIC;
signal multadd_en_i_1_n_0 : STD_LOGIC;
signal multadd_op_valid : STD_LOGIC;
signal n_output_bram_wr_addr0 : STD_LOGIC_VECTOR ( 13 downto 1 );
signal \n_output_bram_wr_addr0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__0_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__0_n_1\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__0_n_2\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__0_n_3\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_n_0\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_n_1\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_n_2\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__1_n_3\ : STD_LOGIC;
signal \n_output_bram_wr_addr0_carry__2_i_1_n_0\ : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_i_1_n_0 : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_i_2_n_0 : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_i_3_n_0 : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_i_4_n_0 : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_n_0 : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_n_1 : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_n_2 : STD_LOGIC;
signal n_output_bram_wr_addr0_carry_n_3 : STD_LOGIC;
signal \^output_bram_wr_addr\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \output_bram_wr_addr[0]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[10]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[11]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[12]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[13]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[13]_i_2_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[1]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[2]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[3]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[4]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[5]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[6]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[7]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[8]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_addr[9]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[0]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[10]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[11]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[12]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[13]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[14]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[1]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[2]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[3]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[4]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[5]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[6]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[7]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[8]_i_1_n_0\ : STD_LOGIC;
signal \output_bram_wr_dout[9]_i_1_n_0\ : STD_LOGIC;
signal output_bram_wr_wen_i_1_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal row_addr_overflow : STD_LOGIC;
attribute MARK_DEBUG of row_addr_overflow : signal is std.standard.true;
signal row_addr_underflow : STD_LOGIC;
attribute MARK_DEBUG of row_addr_underflow : signal is std.standard.true;
signal sum_col_addr : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG of sum_col_addr : signal is std.standard.true;
signal sum_col_addr_inferred_i_7_n_0 : STD_LOGIC;
signal sum_row_addr : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute MARK_DEBUG of sum_row_addr : signal is std.standard.true;
signal sum_row_addr_inferred_i_7_n_0 : STD_LOGIC;
signal \weight_bram_rd_adddr[0]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[1]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[2]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[3]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[4]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[5]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[6]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[7]_i_1_n_0\ : STD_LOGIC;
signal \weight_bram_rd_adddr[8]_i_1_n_0\ : STD_LOGIC;
signal NLW_conv_iaddr_inferred_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_conv_iaddr_inferred_i_16_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_conv_waddr_inferred_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_conv_waddr_inferred_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_conv_waddr_inferred_i_13_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_conv_waddr_inferred_i_13_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_conv_waddr_inferred_i_27_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_conv_waddr_inferred_i_27_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_in01_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_in01_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_in01_carry__1_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_in01_carry__1_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_in02_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_in02_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_in02_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_macinst0_m_axis_result_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_n_output_bram_wr_addr0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_n_output_bram_wr_addr0_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of ap_done_r_i_2 : label is "soft_lutpair34";
attribute SOFT_HLUTNM of ap_ready_r_i_1 : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \conv_ichnls[2]_i_2\ : label is "soft_lutpair33";
attribute KEEP : string;
attribute KEEP of \conv_ichnls_reg[0]\ : label is "yes";
attribute KEEP of \conv_ichnls_reg[1]\ : label is "yes";
attribute KEEP of \conv_ichnls_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \conv_icols[5]_i_4\ : label is "soft_lutpair44";
attribute KEEP of \conv_icols_reg[0]\ : label is "yes";
attribute KEEP of \conv_icols_reg[1]\ : label is "yes";
attribute KEEP of \conv_icols_reg[2]\ : label is "yes";
attribute KEEP of \conv_icols_reg[3]\ : label is "yes";
attribute KEEP of \conv_icols_reg[4]\ : label is "yes";
attribute KEEP of \conv_icols_reg[5]\ : label is "yes";
attribute SOFT_HLUTNM of \conv_irows[4]_i_3\ : label is "soft_lutpair44";
attribute KEEP of \conv_irows_reg[0]\ : label is "yes";
attribute KEEP of \conv_irows_reg[1]\ : label is "yes";
attribute KEEP of \conv_irows_reg[2]\ : label is "yes";
attribute KEEP of \conv_irows_reg[3]\ : label is "yes";
attribute KEEP of \conv_irows_reg[4]\ : label is "yes";
attribute KEEP of \conv_irows_reg[5]\ : label is "yes";
attribute SOFT_HLUTNM of \conv_state[2]_i_2\ : label is "soft_lutpair33";
attribute KEEP of \conv_wcols_reg[0]\ : label is "yes";
attribute KEEP of \conv_wcols_reg[1]\ : label is "yes";
attribute KEEP of \conv_wcols_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \conv_wfltrs[4]_i_4\ : label is "soft_lutpair38";
attribute KEEP of \conv_wfltrs_reg[0]\ : label is "yes";
attribute KEEP of \conv_wfltrs_reg[1]\ : label is "yes";
attribute KEEP of \conv_wfltrs_reg[2]\ : label is "yes";
attribute KEEP of \conv_wfltrs_reg[3]\ : label is "yes";
attribute KEEP of \conv_wfltrs_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM of \conv_wrows[2]_i_2\ : label is "soft_lutpair38";
attribute KEEP of \conv_wrows_reg[0]\ : label is "yes";
attribute KEEP of \conv_wrows_reg[1]\ : label is "yes";
attribute KEEP of \conv_wrows_reg[2]\ : label is "yes";
attribute KEEP of \current_col_reg[0]\ : label is "yes";
attribute KEEP of \current_col_reg[1]\ : label is "yes";
attribute KEEP of \current_col_reg[2]\ : label is "yes";
attribute KEEP of \current_col_reg[3]\ : label is "yes";
attribute KEEP of \current_col_reg[4]\ : label is "yes";
attribute KEEP of \current_col_reg[5]\ : label is "yes";
attribute KEEP of \current_row_reg[0]\ : label is "yes";
attribute KEEP of \current_row_reg[1]\ : label is "yes";
attribute KEEP of \current_row_reg[2]\ : label is "yes";
attribute KEEP of \current_row_reg[3]\ : label is "yes";
attribute KEEP of \current_row_reg[4]\ : label is "yes";
attribute KEEP of \current_row_reg[5]\ : label is "yes";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[0]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[10]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[11]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[1]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[2]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[3]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[4]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[5]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[6]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[7]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[8]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of \input_bram_rd_adddr_reg[9]\ : label is "xilinx.com:interface:bram:1.0 input_bram_rd ADDR";
attribute X_INTERFACE_INFO of input_bram_rd_en_reg : label is "xilinx.com:interface:bram:1.0 input_bram_rd EN";
attribute SOFT_HLUTNM of \mac_o_last_relu[0]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \mac_o_last_relu[10]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \mac_o_last_relu[11]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \mac_o_last_relu[12]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \mac_o_last_relu[14]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \mac_o_last_relu[1]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \mac_o_last_relu[2]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \mac_o_last_relu[3]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \mac_o_last_relu[4]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \mac_o_last_relu[5]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \mac_o_last_relu[6]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \mac_o_last_relu[7]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \mac_o_last_relu[8]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \mac_o_last_relu[9]_i_1\ : label is "soft_lutpair57";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of macinst0 : label is "fp_mult_add_16bit,floating_point_v7_1_4,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of macinst0 : label is "yes";
attribute x_core_info : string;
attribute x_core_info of macinst0 : label is "floating_point_v7_1_4,Vivado 2017.2";
attribute SOFT_HLUTNM of macinst0_i_1 : label is "soft_lutpair35";
attribute SOFT_HLUTNM of macinst0_i_10 : label is "soft_lutpair42";
attribute SOFT_HLUTNM of macinst0_i_11 : label is "soft_lutpair41";
attribute SOFT_HLUTNM of macinst0_i_12 : label is "soft_lutpair40";
attribute SOFT_HLUTNM of macinst0_i_13 : label is "soft_lutpair37";
attribute SOFT_HLUTNM of macinst0_i_14 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of macinst0_i_15 : label is "soft_lutpair35";
attribute SOFT_HLUTNM of macinst0_i_16 : label is "soft_lutpair39";
attribute SOFT_HLUTNM of macinst0_i_2 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of macinst0_i_3 : label is "soft_lutpair37";
attribute SOFT_HLUTNM of macinst0_i_4 : label is "soft_lutpair39";
attribute SOFT_HLUTNM of macinst0_i_5 : label is "soft_lutpair40";
attribute SOFT_HLUTNM of macinst0_i_6 : label is "soft_lutpair41";
attribute SOFT_HLUTNM of macinst0_i_7 : label is "soft_lutpair42";
attribute SOFT_HLUTNM of macinst0_i_8 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of macinst0_i_9 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \output_bram_wr_addr[0]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \output_bram_wr_addr[10]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \output_bram_wr_addr[11]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \output_bram_wr_addr[12]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \output_bram_wr_addr[13]_i_2\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \output_bram_wr_addr[1]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \output_bram_wr_addr[2]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \output_bram_wr_addr[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \output_bram_wr_addr[4]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \output_bram_wr_addr[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \output_bram_wr_addr[6]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \output_bram_wr_addr[7]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \output_bram_wr_addr[8]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \output_bram_wr_addr[9]_i_1\ : label is "soft_lutpair51";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[0]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[10]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[11]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[12]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[13]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[1]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[2]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[3]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[4]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[5]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[6]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[7]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[8]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_addr_reg[9]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr ADDR";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[0]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[10]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[11]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[12]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[13]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[14]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[1]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[2]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[3]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[4]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[5]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[6]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[7]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[8]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of \output_bram_wr_dout_reg[9]\ : label is "xilinx.com:interface:bram:1.0 output_bram_wr DIN";
attribute X_INTERFACE_INFO of output_bram_wr_wen_reg : label is "xilinx.com:interface:bram:1.0 output_bram_wr WE";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[0]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[1]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[2]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[3]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[4]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[5]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[6]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[7]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of \weight_bram_rd_adddr_reg[8]\ : label is "xilinx.com:interface:bram:1.0 weight_bram_rd ADDR";
attribute X_INTERFACE_INFO of weight_bram_rd_en_reg : label is "xilinx.com:interface:bram:1.0 weight_bram_rd EN";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of weight_bram_rd_en_reg : label is "no";
begin
AR(0) <= \^ar\(0);
ap_done <= \^ap_done\;
ap_ready <= \^ap_ready\;
output_bram_wr_addr(13 downto 0) <= \^output_bram_wr_addr\(13 downto 0);
\_inferred__5/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => sum_row_addr(5),
I1 => sum_row_addr(2),
I2 => sum_row_addr(1),
I3 => sum_row_addr(0),
I4 => sum_row_addr(4),
I5 => sum_row_addr(3),
O => row_addr_overflow
);
\_inferred__6/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => sum_col_addr(5),
I1 => sum_col_addr(2),
I2 => sum_col_addr(1),
I3 => sum_col_addr(0),
I4 => sum_col_addr(4),
I5 => sum_col_addr(3),
O => col_addr_overflow
);
ap_done_r_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFE000C0000"
)
port map (
I0 => ap_done_r_i_2_n_0,
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => conv_wfltrs(4),
I5 => \^ap_done\,
O => ap_done_r_i_1_n_0
);
ap_done_r_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ap_start_rr,
I1 => ap_start_r,
O => ap_done_r_i_2_n_0
);
ap_done_r_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => ap_done_r_i_1_n_0,
Q => \^ap_done\
);
ap_ready_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F3A2"
)
port map (
I0 => \^ap_done\,
I1 => ap_start_r,
I2 => ap_start_rr,
I3 => \^ap_ready\,
O => ap_ready_r_i_1_n_0
);
ap_ready_r_reg: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => ap_ready_r_i_1_n_0,
PRE => \^ar\(0),
Q => \^ap_ready\
);
ap_start_r_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => ap_start,
Q => ap_start_r,
R => '0'
);
ap_start_rr_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => ap_start_r,
Q => ap_start_rr,
R => '0'
);
calc_col_addr_inferred_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => sum_col_addr(4),
I1 => sum_col_addr(0),
I2 => sum_col_addr(1),
I3 => sum_col_addr(2),
I4 => sum_col_addr(3),
I5 => sum_col_addr(5),
O => calc_col_addr(5)
);
calc_col_addr_inferred_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => sum_col_addr(3),
I1 => sum_col_addr(2),
I2 => sum_col_addr(1),
I3 => sum_col_addr(0),
I4 => sum_col_addr(4),
O => calc_col_addr(4)
);
calc_col_addr_inferred_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => sum_col_addr(0),
I1 => sum_col_addr(1),
I2 => sum_col_addr(2),
I3 => sum_col_addr(3),
O => calc_col_addr(3)
);
calc_col_addr_inferred_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => sum_col_addr(1),
I1 => sum_col_addr(0),
I2 => sum_col_addr(2),
O => calc_col_addr(2)
);
calc_col_addr_inferred_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => sum_col_addr(0),
I1 => sum_col_addr(1),
O => calc_col_addr(1)
);
calc_row_addr_inferred_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => sum_row_addr(4),
I1 => sum_row_addr(0),
I2 => sum_row_addr(1),
I3 => sum_row_addr(2),
I4 => sum_row_addr(3),
I5 => sum_row_addr(5),
O => calc_row_addr(5)
);
calc_row_addr_inferred_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => sum_row_addr(3),
I1 => sum_row_addr(2),
I2 => sum_row_addr(1),
I3 => sum_row_addr(0),
I4 => sum_row_addr(4),
O => calc_row_addr(4)
);
calc_row_addr_inferred_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => sum_row_addr(0),
I1 => sum_row_addr(1),
I2 => sum_row_addr(2),
I3 => sum_row_addr(3),
O => calc_row_addr(3)
);
calc_row_addr_inferred_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => sum_row_addr(1),
I1 => sum_row_addr(0),
I2 => sum_row_addr(2),
O => calc_row_addr(2)
);
calc_row_addr_inferred_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => sum_row_addr(0),
I1 => sum_row_addr(1),
O => calc_row_addr(1)
);
conv_iaddr_inferred_i_1: unisim.vcomponents.CARRY4
port map (
CI => conv_iaddr_inferred_i_2_n_0,
CO(3) => NLW_conv_iaddr_inferred_i_1_CO_UNCONNECTED(3),
CO(2) => conv_iaddr_inferred_i_1_n_1,
CO(1) => conv_iaddr_inferred_i_1_n_2,
CO(0) => conv_iaddr_inferred_i_1_n_3,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => conv_iaddr(11 downto 8),
S(3) => conv_iaddr_inferred_i_4_n_0,
S(2) => conv_iaddr_inferred_i_5_n_0,
S(1) => conv_iaddr_inferred_i_6_n_0,
S(0) => conv_iaddr_inferred_i_7_n_0
);
conv_iaddr_inferred_i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_17_n_6,
O => conv_iaddr_inferred_i_10_n_0
);
conv_iaddr_inferred_i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_17_n_7,
O => conv_iaddr_inferred_i_11_n_0
);
conv_iaddr_inferred_i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in02(3),
O => conv_iaddr_inferred_i_12_n_0
);
conv_iaddr_inferred_i_13: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_ichnls(2),
I1 => in02(2),
O => conv_iaddr_inferred_i_13_n_0
);
conv_iaddr_inferred_i_14: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_ichnls(1),
I1 => in02(1),
O => conv_iaddr_inferred_i_14_n_0
);
conv_iaddr_inferred_i_15: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_ichnls(0),
I1 => in02(0),
O => conv_iaddr_inferred_i_15_n_0
);
conv_iaddr_inferred_i_16: unisim.vcomponents.CARRY4
port map (
CI => conv_iaddr_inferred_i_17_n_0,
CO(3) => NLW_conv_iaddr_inferred_i_16_CO_UNCONNECTED(3),
CO(2) => conv_iaddr_inferred_i_16_n_1,
CO(1) => conv_iaddr_inferred_i_16_n_2,
CO(0) => conv_iaddr_inferred_i_16_n_3,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => conv_iaddr_inferred_i_16_n_4,
O(2) => conv_iaddr_inferred_i_16_n_5,
O(1) => conv_iaddr_inferred_i_16_n_6,
O(0) => conv_iaddr_inferred_i_16_n_7,
S(3) => conv_iaddr_inferred_i_18_n_0,
S(2) => conv_iaddr_inferred_i_19_n_0,
S(1) => conv_iaddr_inferred_i_20_n_0,
S(0) => conv_iaddr_inferred_i_21_n_0
);
conv_iaddr_inferred_i_17: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => conv_iaddr_inferred_i_17_n_0,
CO(2) => conv_iaddr_inferred_i_17_n_1,
CO(1) => conv_iaddr_inferred_i_17_n_2,
CO(0) => conv_iaddr_inferred_i_17_n_3,
CYINIT => '0',
DI(3 downto 1) => in02(7 downto 5),
DI(0) => '0',
O(3) => conv_iaddr_inferred_i_17_n_4,
O(2) => conv_iaddr_inferred_i_17_n_5,
O(1) => conv_iaddr_inferred_i_17_n_6,
O(0) => conv_iaddr_inferred_i_17_n_7,
S(3) => conv_iaddr_inferred_i_22_n_0,
S(2) => conv_iaddr_inferred_i_23_n_0,
S(1) => conv_iaddr_inferred_i_24_n_0,
S(0) => conv_iaddr_inferred_i_25_n_0
);
conv_iaddr_inferred_i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01_1(6),
O => conv_iaddr_inferred_i_18_n_0
);
conv_iaddr_inferred_i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01_1(5),
O => conv_iaddr_inferred_i_19_n_0
);
conv_iaddr_inferred_i_2: unisim.vcomponents.CARRY4
port map (
CI => conv_iaddr_inferred_i_3_n_0,
CO(3) => conv_iaddr_inferred_i_2_n_0,
CO(2) => conv_iaddr_inferred_i_2_n_1,
CO(1) => conv_iaddr_inferred_i_2_n_2,
CO(0) => conv_iaddr_inferred_i_2_n_3,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => conv_iaddr(7 downto 4),
S(3) => conv_iaddr_inferred_i_8_n_0,
S(2) => conv_iaddr_inferred_i_9_n_0,
S(1) => conv_iaddr_inferred_i_10_n_0,
S(0) => conv_iaddr_inferred_i_11_n_0
);
conv_iaddr_inferred_i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01_1(4),
O => conv_iaddr_inferred_i_20_n_0
);
conv_iaddr_inferred_i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01_1(3),
O => conv_iaddr_inferred_i_21_n_0
);
conv_iaddr_inferred_i_22: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => in02(7),
I1 => in01_1(2),
O => conv_iaddr_inferred_i_22_n_0
);
conv_iaddr_inferred_i_23: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => in02(6),
I1 => in01_1(1),
O => conv_iaddr_inferred_i_23_n_0
);
conv_iaddr_inferred_i_24: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => in02(5),
I1 => in01_1(0),
O => conv_iaddr_inferred_i_24_n_0
);
conv_iaddr_inferred_i_25: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in02(4),
O => conv_iaddr_inferred_i_25_n_0
);
conv_iaddr_inferred_i_3: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => conv_iaddr_inferred_i_3_n_0,
CO(2) => conv_iaddr_inferred_i_3_n_1,
CO(1) => conv_iaddr_inferred_i_3_n_2,
CO(0) => conv_iaddr_inferred_i_3_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => conv_ichnls(2 downto 0),
O(3 downto 0) => conv_iaddr(3 downto 0),
S(3) => conv_iaddr_inferred_i_12_n_0,
S(2) => conv_iaddr_inferred_i_13_n_0,
S(1) => conv_iaddr_inferred_i_14_n_0,
S(0) => conv_iaddr_inferred_i_15_n_0
);
conv_iaddr_inferred_i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_16_n_4,
O => conv_iaddr_inferred_i_4_n_0
);
conv_iaddr_inferred_i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_16_n_5,
O => conv_iaddr_inferred_i_5_n_0
);
conv_iaddr_inferred_i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_16_n_6,
O => conv_iaddr_inferred_i_6_n_0
);
conv_iaddr_inferred_i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_16_n_7,
O => conv_iaddr_inferred_i_7_n_0
);
conv_iaddr_inferred_i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_17_n_4,
O => conv_iaddr_inferred_i_8_n_0
);
conv_iaddr_inferred_i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_iaddr_inferred_i_17_n_5,
O => conv_iaddr_inferred_i_9_n_0
);
\conv_ichnls[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC9CCCC0C09CCCC0"
)
port map (
I0 => \conv_ichnls[0]_i_2_n_0\,
I1 => conv_ichnls(0),
I2 => conv_state(1),
I3 => conv_state(0),
I4 => conv_state(2),
I5 => \conv_ichnls[0]_i_3_n_0\,
O => \conv_ichnls[0]_i_1_n_0\
);
\conv_ichnls[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => conv_ichnls(2),
I1 => conv_ichnls(1),
I2 => conv_ichnls(0),
O => \conv_ichnls[0]_i_2_n_0\
);
\conv_ichnls[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => conv_wcols(2),
I1 => conv_wcols(1),
I2 => conv_wcols(0),
O => \conv_ichnls[0]_i_3_n_0\
);
\conv_ichnls[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C8C8C8C8FBC8CC88"
)
port map (
I0 => \conv_ichnls[1]_i_2_n_0\,
I1 => conv_ichnls(1),
I2 => conv_state(1),
I3 => \conv_ichnls[2]_i_2_n_0\,
I4 => conv_ichnls(0),
I5 => conv_ichnls(2),
O => \conv_ichnls[1]_i_1_n_0\
);
\conv_ichnls[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DEDEDEDEDE9E9E9E"
)
port map (
I0 => conv_state(1),
I1 => conv_state(0),
I2 => conv_state(2),
I3 => conv_wcols(0),
I4 => conv_wcols(1),
I5 => conv_wcols(2),
O => \conv_ichnls[1]_i_2_n_0\
);
\conv_ichnls[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF007000"
)
port map (
I0 => conv_ichnls(1),
I1 => conv_ichnls(0),
I2 => \conv_ichnls[2]_i_2_n_0\,
I3 => conv_ichnls(2),
I4 => \conv_ichnls[2]_i_3_n_0\,
O => \conv_ichnls[2]_i_1_n_0\
);
\conv_ichnls[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => conv_state(0),
I1 => conv_state(1),
I2 => conv_state(2),
O => \conv_ichnls[2]_i_2_n_0\
);
\conv_ichnls[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAFFFFFFFFAAAA"
)
port map (
I0 => conv_state(1),
I1 => conv_wcols(0),
I2 => conv_wcols(1),
I3 => conv_wcols(2),
I4 => conv_state(2),
I5 => conv_state(0),
O => \conv_ichnls[2]_i_3_n_0\
);
\conv_ichnls_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_ichnls[0]_i_1_n_0\,
Q => conv_ichnls(0)
);
\conv_ichnls_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_ichnls[1]_i_1_n_0\,
Q => conv_ichnls(1)
);
\conv_ichnls_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_ichnls[2]_i_1_n_0\,
Q => conv_ichnls(2)
);
\conv_icols[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCC6C0C600"
)
port map (
I0 => \conv_wcols[0]_i_2_n_0\,
I1 => conv_icols(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => conv_irows(5),
I5 => conv_state(0),
O => \conv_icols[0]_i_1_n_0\
);
\conv_icols[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF807080"
)
port map (
I0 => conv_icols(0),
I1 => \conv_wcols[0]_i_2_n_0\,
I2 => \conv_icols[5]_i_4_n_0\,
I3 => conv_icols(1),
I4 => \conv_icols[5]_i_5_n_0\,
O => \conv_icols[1]_i_1_n_0\
);
\conv_icols[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCC6C0C600"
)
port map (
I0 => \conv_icols[5]_i_2_n_0\,
I1 => conv_icols(2),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => conv_irows(5),
I5 => conv_state(0),
O => \conv_icols[2]_i_1_n_0\
);
\conv_icols[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF807080"
)
port map (
I0 => conv_icols(2),
I1 => \conv_icols[5]_i_2_n_0\,
I2 => \conv_icols[5]_i_4_n_0\,
I3 => conv_icols(3),
I4 => \conv_icols[5]_i_5_n_0\,
O => \conv_icols[3]_i_1_n_0\
);
\conv_icols[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF80007F008000"
)
port map (
I0 => \conv_icols[5]_i_2_n_0\,
I1 => conv_icols(2),
I2 => conv_icols(3),
I3 => \conv_icols[5]_i_4_n_0\,
I4 => conv_icols(4),
I5 => \conv_icols[5]_i_5_n_0\,
O => \conv_icols[4]_i_1_n_0\
);
\conv_icols[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF80007F008000"
)
port map (
I0 => \conv_icols[5]_i_2_n_0\,
I1 => \conv_icols[5]_i_3_n_0\,
I2 => conv_icols(2),
I3 => \conv_icols[5]_i_4_n_0\,
I4 => conv_icols(5),
I5 => \conv_icols[5]_i_5_n_0\,
O => \conv_icols[5]_i_1_n_0\
);
\conv_icols[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8880000"
)
port map (
I0 => conv_icols(0),
I1 => conv_wrows(2),
I2 => conv_wrows(1),
I3 => conv_wrows(0),
I4 => conv_icols(1),
O => \conv_icols[5]_i_2_n_0\
);
\conv_icols[5]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => conv_icols(3),
I1 => conv_icols(4),
O => \conv_icols[5]_i_3_n_0\
);
\conv_icols[5]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => conv_state(2),
I1 => conv_state(1),
I2 => conv_state(0),
O => \conv_icols[5]_i_4_n_0\
);
\conv_icols[5]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFA8"
)
port map (
I0 => conv_state(1),
I1 => conv_state(2),
I2 => conv_irows(5),
I3 => conv_state(0),
O => \conv_icols[5]_i_5_n_0\
);
\conv_icols_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_icols[0]_i_1_n_0\,
Q => conv_icols(0)
);
\conv_icols_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_icols[1]_i_1_n_0\,
Q => conv_icols(1)
);
\conv_icols_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_icols[2]_i_1_n_0\,
Q => conv_icols(2)
);
\conv_icols_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_icols[3]_i_1_n_0\,
Q => conv_icols(3)
);
\conv_icols_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_icols[4]_i_1_n_0\,
Q => conv_icols(4)
);
\conv_icols_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_icols[5]_i_1_n_0\,
Q => conv_icols(5)
);
conv_ip_zeros_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"04440000"
)
port map (
I0 => conv_ichnls(2),
I1 => conv_zero_pad_en,
I2 => conv_ichnls(0),
I3 => conv_ichnls(1),
I4 => \conv_ichnls[2]_i_2_n_0\,
O => conv_ip_zeros_i_1_n_0
);
\conv_ip_zeros_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => conv_ip_zeros,
Q => conv_ip_zeros_r(0),
R => '0'
);
\conv_ip_zeros_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => conv_ip_zeros_r(0),
Q => conv_ip_zeros_r(1),
R => '0'
);
conv_ip_zeros_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => conv_ip_zeros_i_1_n_0,
Q => conv_ip_zeros
);
\conv_irows[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C6C6CCCCCCC0C0C0"
)
port map (
I0 => conv_icols(5),
I1 => conv_irows(0),
I2 => conv_state(2),
I3 => conv_wfltrs(4),
I4 => conv_state(0),
I5 => conv_state(1),
O => \conv_irows[0]_i_1_n_0\
);
\conv_irows[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF807080"
)
port map (
I0 => conv_icols(5),
I1 => conv_irows(0),
I2 => \conv_irows[4]_i_3_n_0\,
I3 => conv_irows(1),
I4 => \conv_irows[4]_i_4_n_0\,
O => \conv_irows[1]_i_1_n_0\
);
\conv_irows[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C6C6CCCCCCC0C0C0"
)
port map (
I0 => \conv_irows[4]_i_2_n_0\,
I1 => conv_irows(2),
I2 => conv_state(2),
I3 => conv_wfltrs(4),
I4 => conv_state(0),
I5 => conv_state(1),
O => \conv_irows[2]_i_1_n_0\
);
\conv_irows[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF807080"
)
port map (
I0 => conv_irows(2),
I1 => \conv_irows[4]_i_2_n_0\,
I2 => \conv_irows[4]_i_3_n_0\,
I3 => conv_irows(3),
I4 => \conv_irows[4]_i_4_n_0\,
O => \conv_irows[3]_i_1_n_0\
);
\conv_irows[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF80007F008000"
)
port map (
I0 => \conv_irows[4]_i_2_n_0\,
I1 => conv_irows(2),
I2 => conv_irows(3),
I3 => \conv_irows[4]_i_3_n_0\,
I4 => conv_irows(4),
I5 => \conv_irows[4]_i_4_n_0\,
O => \conv_irows[4]_i_1_n_0\
);
\conv_irows[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => conv_icols(5),
I1 => conv_irows(0),
I2 => conv_irows(1),
O => \conv_irows[4]_i_2_n_0\
);
\conv_irows[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => conv_state(1),
I1 => conv_state(0),
I2 => conv_state(2),
O => \conv_irows[4]_i_3_n_0\
);
\conv_irows[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"AFEA"
)
port map (
I0 => conv_state(2),
I1 => conv_wfltrs(4),
I2 => conv_state(0),
I3 => conv_state(1),
O => \conv_irows[4]_i_4_n_0\
);
\conv_irows[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C6C6CCCCCCC0C0C0"
)
port map (
I0 => \conv_irows[5]_i_2_n_0\,
I1 => conv_irows(5),
I2 => conv_state(2),
I3 => conv_wfltrs(4),
I4 => conv_state(0),
I5 => conv_state(1),
O => \conv_irows[5]_i_1_n_0\
);
\conv_irows[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => conv_irows(2),
I1 => conv_irows(3),
I2 => conv_irows(4),
I3 => conv_irows(1),
I4 => conv_irows(0),
I5 => conv_icols(5),
O => \conv_irows[5]_i_2_n_0\
);
\conv_irows_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_irows[0]_i_1_n_0\,
Q => conv_irows(0)
);
\conv_irows_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_irows[1]_i_1_n_0\,
Q => conv_irows(1)
);
\conv_irows_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_irows[2]_i_1_n_0\,
Q => conv_irows(2)
);
\conv_irows_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_irows[3]_i_1_n_0\,
Q => conv_irows(3)
);
\conv_irows_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_irows[4]_i_1_n_0\,
Q => conv_irows(4)
);
\conv_irows_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_irows[5]_i_1_n_0\,
Q => conv_irows(5)
);
\conv_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E330E333E330E330"
)
port map (
I0 => \conv_ichnls[0]_i_2_n_0\,
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => ap_start_rr,
I5 => ap_start_r,
O => \conv_state[0]_i_1_n_0\
);
\conv_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFE0"
)
port map (
I0 => \conv_state[1]_i_2_n_0\,
I1 => \conv_state[1]_i_3_n_0\,
I2 => \conv_state[2]_i_2_n_0\,
I3 => conv_state(1),
O => \conv_state[1]_i_1_n_0\
);
\conv_state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000330055F000"
)
port map (
I0 => conv_irows(5),
I1 => conv_wfltrs(4),
I2 => \conv_wcols[0]_i_2_n_0\,
I3 => conv_state(2),
I4 => conv_state(1),
I5 => conv_state(0),
O => \conv_state[1]_i_2_n_0\
);
\conv_state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"33553300F0000000"
)
port map (
I0 => \conv_ichnls[0]_i_3_n_0\,
I1 => \conv_ichnls[0]_i_2_n_0\,
I2 => conv_icols(5),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => conv_state(2),
O => \conv_state[1]_i_3_n_0\
);
\conv_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFFFFFF08080000"
)
port map (
I0 => conv_state(1),
I1 => conv_state(0),
I2 => conv_icols(5),
I3 => \conv_wcols[0]_i_2_n_0\,
I4 => \conv_state[2]_i_2_n_0\,
I5 => conv_state(2),
O => \conv_state[2]_i_1_n_0\
);
\conv_state[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7E7F7E7E"
)
port map (
I0 => conv_state(0),
I1 => conv_state(1),
I2 => conv_state(2),
I3 => ap_start_rr,
I4 => ap_start_r,
O => \conv_state[2]_i_2_n_0\
);
\conv_state_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_state[0]_i_1_n_0\,
Q => conv_state(0)
);
\conv_state_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_state[1]_i_1_n_0\,
Q => conv_state(1)
);
\conv_state_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_state[2]_i_1_n_0\,
Q => conv_state(2)
);
conv_waddr_inferred_i_1: unisim.vcomponents.CARRY4
port map (
CI => conv_waddr_inferred_i_2_n_0,
CO(3 downto 0) => NLW_conv_waddr_inferred_i_1_CO_UNCONNECTED(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => NLW_conv_waddr_inferred_i_1_O_UNCONNECTED(3 downto 1),
O(0) => conv_waddr(8),
S(3 downto 1) => B"000",
S(0) => conv_waddr_inferred_i_4_n_0
);
conv_waddr_inferred_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_ichnls(2),
I1 => conv_waddr_inferred_i_15_n_5,
O => conv_waddr_inferred_i_10_n_0
);
conv_waddr_inferred_i_11: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_ichnls(1),
I1 => conv_waddr_inferred_i_15_n_6,
O => conv_waddr_inferred_i_11_n_0
);
conv_waddr_inferred_i_12: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_ichnls(0),
I1 => conv_waddr_inferred_i_15_n_7,
O => conv_waddr_inferred_i_12_n_0
);
conv_waddr_inferred_i_13: unisim.vcomponents.CARRY4
port map (
CI => conv_waddr_inferred_i_14_n_0,
CO(3 downto 0) => NLW_conv_waddr_inferred_i_13_CO_UNCONNECTED(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => NLW_conv_waddr_inferred_i_13_O_UNCONNECTED(3 downto 1),
O(0) => conv_waddr_inferred_i_13_n_7,
S(3 downto 1) => B"000",
S(0) => \conv_wrows_reg[0]_0\(0)
);
conv_waddr_inferred_i_14: unisim.vcomponents.CARRY4
port map (
CI => conv_waddr_inferred_i_15_n_0,
CO(3) => conv_waddr_inferred_i_14_n_0,
CO(2) => conv_waddr_inferred_i_14_n_1,
CO(1) => conv_waddr_inferred_i_14_n_2,
CO(0) => conv_waddr_inferred_i_14_n_3,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => C(4),
O(3) => conv_waddr_inferred_i_14_n_4,
O(2) => conv_waddr_inferred_i_14_n_5,
O(1) => conv_waddr_inferred_i_14_n_6,
O(0) => conv_waddr_inferred_i_14_n_7,
S(3 downto 1) => S(2 downto 0),
S(0) => conv_waddr_inferred_i_21_n_0
);
conv_waddr_inferred_i_15: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => conv_waddr_inferred_i_15_n_0,
CO(2) => conv_waddr_inferred_i_15_n_1,
CO(1) => conv_waddr_inferred_i_15_n_2,
CO(0) => conv_waddr_inferred_i_15_n_3,
CYINIT => '0',
DI(3 downto 1) => C(3 downto 1),
DI(0) => conv_wcols(0),
O(3) => conv_waddr_inferred_i_15_n_4,
O(2) => conv_waddr_inferred_i_15_n_5,
O(1) => conv_waddr_inferred_i_15_n_6,
O(0) => conv_waddr_inferred_i_15_n_7,
S(3) => conv_waddr_inferred_i_23_n_0,
S(2) => conv_waddr_inferred_i_24_n_0,
S(1) => conv_waddr_inferred_i_25_n_0,
S(0) => conv_waddr_inferred_i_26_n_0
);
conv_waddr_inferred_i_17: unisim.vcomponents.CARRY4
port map (
CI => conv_waddr_inferred_i_22_n_0,
CO(3) => conv_waddr_inferred_i_17_n_0,
CO(2) => conv_waddr_inferred_i_17_n_1,
CO(1) => conv_waddr_inferred_i_17_n_2,
CO(0) => conv_waddr_inferred_i_17_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => in01(6 downto 4),
O(3 downto 1) => \weight_bram_rd_adddr_reg[8]_0\(2 downto 0),
O(0) => C(4),
S(3) => conv_waddr_inferred_i_28_n_0,
S(2) => conv_waddr_inferred_i_29_n_0,
S(1) => conv_waddr_inferred_i_30_n_0,
S(0) => conv_waddr_inferred_i_31_n_0
);
conv_waddr_inferred_i_2: unisim.vcomponents.CARRY4
port map (
CI => conv_waddr_inferred_i_3_n_0,
CO(3) => conv_waddr_inferred_i_2_n_0,
CO(2) => conv_waddr_inferred_i_2_n_1,
CO(1) => conv_waddr_inferred_i_2_n_2,
CO(0) => conv_waddr_inferred_i_2_n_3,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => conv_waddr(7 downto 4),
S(3) => conv_waddr_inferred_i_5_n_0,
S(2) => conv_waddr_inferred_i_6_n_0,
S(1) => conv_waddr_inferred_i_7_n_0,
S(0) => conv_waddr_inferred_i_8_n_0
);
conv_waddr_inferred_i_21: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => conv_wcols(2),
I1 => conv_wcols(1),
I2 => C(4),
O => conv_waddr_inferred_i_21_n_0
);
conv_waddr_inferred_i_22: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => conv_waddr_inferred_i_22_n_0,
CO(2) => conv_waddr_inferred_i_22_n_1,
CO(1) => conv_waddr_inferred_i_22_n_2,
CO(0) => conv_waddr_inferred_i_22_n_3,
CYINIT => '0',
DI(3 downto 1) => in01(3 downto 1),
DI(0) => conv_wrows(0),
O(3 downto 0) => C(3 downto 0),
S(3) => conv_waddr_inferred_i_32_n_0,
S(2) => conv_waddr_inferred_i_33_n_0,
S(1) => conv_waddr_inferred_i_34_n_0,
S(0) => conv_waddr_inferred_i_35_n_0
);
conv_waddr_inferred_i_23: unisim.vcomponents.LUT4
generic map(
INIT => X"A758"
)
port map (
I0 => conv_wcols(1),
I1 => conv_wcols(0),
I2 => conv_wcols(2),
I3 => C(3),
O => conv_waddr_inferred_i_23_n_0
);
conv_waddr_inferred_i_24: unisim.vcomponents.LUT4
generic map(
INIT => X"639C"
)
port map (
I0 => conv_wcols(0),
I1 => conv_wcols(2),
I2 => conv_wcols(1),
I3 => C(2),
O => conv_waddr_inferred_i_24_n_0
);
conv_waddr_inferred_i_25: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => conv_wcols(1),
I1 => conv_wcols(0),
I2 => C(1),
O => conv_waddr_inferred_i_25_n_0
);
conv_waddr_inferred_i_26: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_wcols(0),
I1 => C(0),
O => conv_waddr_inferred_i_26_n_0
);
conv_waddr_inferred_i_27: unisim.vcomponents.CARRY4
port map (
CI => conv_waddr_inferred_i_17_n_0,
CO(3 downto 0) => NLW_conv_waddr_inferred_i_27_CO_UNCONNECTED(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => NLW_conv_waddr_inferred_i_27_O_UNCONNECTED(3 downto 1),
O(0) => \weight_bram_rd_adddr_reg[8]_0\(3),
S(3 downto 1) => B"000",
S(0) => conv_waddr_inferred_i_36_n_0
);
conv_waddr_inferred_i_28: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01(7),
O => conv_waddr_inferred_i_28_n_0
);
conv_waddr_inferred_i_29: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01(6),
O => conv_waddr_inferred_i_29_n_0
);
conv_waddr_inferred_i_3: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => conv_waddr_inferred_i_3_n_0,
CO(2) => conv_waddr_inferred_i_3_n_1,
CO(1) => conv_waddr_inferred_i_3_n_2,
CO(0) => conv_waddr_inferred_i_3_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => conv_ichnls(2 downto 0),
O(3 downto 0) => conv_waddr(3 downto 0),
S(3) => conv_waddr_inferred_i_9_n_0,
S(2) => conv_waddr_inferred_i_10_n_0,
S(1) => conv_waddr_inferred_i_11_n_0,
S(0) => conv_waddr_inferred_i_12_n_0
);
conv_waddr_inferred_i_30: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_wrows(2),
I1 => in01(5),
O => conv_waddr_inferred_i_30_n_0
);
conv_waddr_inferred_i_31: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_wrows(1),
I1 => in01(4),
O => conv_waddr_inferred_i_31_n_0
);
conv_waddr_inferred_i_32: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_wrows(0),
I1 => in01(3),
O => conv_waddr_inferred_i_32_n_0
);
conv_waddr_inferred_i_33: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_wrows(2),
I1 => in01(2),
O => conv_waddr_inferred_i_33_n_0
);
conv_waddr_inferred_i_34: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_wrows(1),
I1 => in01(1),
O => conv_waddr_inferred_i_34_n_0
);
conv_waddr_inferred_i_35: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_wrows(0),
I1 => in01(0),
O => conv_waddr_inferred_i_35_n_0
);
conv_waddr_inferred_i_36: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01(8),
O => conv_waddr_inferred_i_36_n_0
);
conv_waddr_inferred_i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_waddr_inferred_i_13_n_7,
O => conv_waddr_inferred_i_4_n_0
);
conv_waddr_inferred_i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_waddr_inferred_i_14_n_4,
O => conv_waddr_inferred_i_5_n_0
);
conv_waddr_inferred_i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_waddr_inferred_i_14_n_5,
O => conv_waddr_inferred_i_6_n_0
);
conv_waddr_inferred_i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_waddr_inferred_i_14_n_6,
O => conv_waddr_inferred_i_7_n_0
);
conv_waddr_inferred_i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_waddr_inferred_i_14_n_7,
O => conv_waddr_inferred_i_8_n_0
);
conv_waddr_inferred_i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_waddr_inferred_i_15_n_4,
O => conv_waddr_inferred_i_9_n_0
);
\conv_wcols[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC3CCC88CCCCCC00"
)
port map (
I0 => \conv_wcols[0]_i_2_n_0\,
I1 => conv_wcols(0),
I2 => \conv_ichnls[0]_i_2_n_0\,
I3 => conv_state(0),
I4 => conv_state(1),
I5 => conv_state(2),
O => \conv_wcols[0]_i_1_n_0\
);
\conv_wcols[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => conv_wrows(2),
I1 => conv_wrows(1),
I2 => conv_wrows(0),
O => \conv_wcols[0]_i_2_n_0\
);
\conv_wcols[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFC0AA00"
)
port map (
I0 => \conv_wcols[2]_i_2_n_0\,
I1 => conv_wcols(0),
I2 => \conv_ichnls[0]_i_2_n_0\,
I3 => conv_wcols(1),
I4 => \conv_ichnls[2]_i_2_n_0\,
O => \conv_wcols[1]_i_1_n_0\
);
\conv_wcols[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFC000AAAA0000"
)
port map (
I0 => \conv_wcols[2]_i_2_n_0\,
I1 => conv_wcols(0),
I2 => conv_wcols(1),
I3 => \conv_ichnls[0]_i_2_n_0\,
I4 => conv_wcols(2),
I5 => \conv_ichnls[2]_i_2_n_0\,
O => \conv_wcols[2]_i_1_n_0\
);
\conv_wcols[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF66666222"
)
port map (
I0 => conv_state(1),
I1 => conv_state(2),
I2 => conv_wrows(0),
I3 => conv_wrows(1),
I4 => conv_wrows(2),
I5 => conv_state(0),
O => \conv_wcols[2]_i_2_n_0\
);
\conv_wcols_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wcols[0]_i_1_n_0\,
Q => conv_wcols(0)
);
\conv_wcols_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wcols[1]_i_1_n_0\,
Q => conv_wcols(1)
);
\conv_wcols_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wcols[2]_i_1_n_0\,
Q => conv_wcols(2)
);
\conv_wfltrs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0F048"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(1),
I2 => conv_wfltrs(0),
I3 => conv_state(0),
I4 => conv_state(2),
O => \conv_wfltrs[0]_i_1_n_0\
);
\conv_wfltrs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00FF007080"
)
port map (
I0 => conv_irows(5),
I1 => conv_wfltrs(0),
I2 => conv_state(1),
I3 => conv_wfltrs(1),
I4 => conv_state(0),
I5 => conv_state(2),
O => \conv_wfltrs[1]_i_1_n_0\
);
\conv_wfltrs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00FF007080"
)
port map (
I0 => conv_wfltrs(1),
I1 => \conv_wfltrs[4]_i_2_n_0\,
I2 => conv_state(1),
I3 => conv_wfltrs(2),
I4 => conv_state(0),
I5 => conv_state(2),
O => \conv_wfltrs[2]_i_1_n_0\
);
\conv_wfltrs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF00FF007080"
)
port map (
I0 => \conv_wfltrs[4]_i_3_n_0\,
I1 => \conv_wfltrs[4]_i_2_n_0\,
I2 => conv_state(1),
I3 => conv_wfltrs(3),
I4 => conv_state(0),
I5 => conv_state(2),
O => \conv_wfltrs[3]_i_1_n_0\
);
\conv_wfltrs[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF80007F008000"
)
port map (
I0 => \conv_wfltrs[4]_i_2_n_0\,
I1 => \conv_wfltrs[4]_i_3_n_0\,
I2 => conv_wfltrs(3),
I3 => \conv_wfltrs[4]_i_4_n_0\,
I4 => conv_wfltrs(4),
I5 => \conv_wfltrs[4]_i_5_n_0\,
O => \conv_wfltrs[4]_i_1_n_0\
);
\conv_wfltrs[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => conv_wfltrs(0),
I1 => conv_irows(5),
O => \conv_wfltrs[4]_i_2_n_0\
);
\conv_wfltrs[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => conv_wfltrs(1),
I1 => conv_wfltrs(2),
O => \conv_wfltrs[4]_i_3_n_0\
);
\conv_wfltrs[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => conv_state(0),
I1 => conv_state(1),
I2 => conv_state(2),
O => \conv_wfltrs[4]_i_4_n_0\
);
\conv_wfltrs[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => conv_state(0),
I1 => conv_state(2),
O => \conv_wfltrs[4]_i_5_n_0\
);
\conv_wfltrs_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wfltrs[0]_i_1_n_0\,
Q => conv_wfltrs(0)
);
\conv_wfltrs_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wfltrs[1]_i_1_n_0\,
Q => conv_wfltrs(1)
);
\conv_wfltrs_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wfltrs[2]_i_1_n_0\,
Q => conv_wfltrs(2)
);
\conv_wfltrs_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wfltrs[3]_i_1_n_0\,
Q => conv_wfltrs(3)
);
\conv_wfltrs_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wfltrs[4]_i_1_n_0\,
Q => conv_wfltrs(4)
);
\conv_wrows[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C6C6CCCCCC0CC0C0"
)
port map (
I0 => \conv_ichnls[0]_i_3_n_0\,
I1 => conv_wrows(0),
I2 => conv_state(1),
I3 => conv_icols(5),
I4 => conv_state(0),
I5 => conv_state(2),
O => \conv_wrows[0]_i_1_n_0\
);
\conv_wrows[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF807080"
)
port map (
I0 => conv_wrows(0),
I1 => \conv_ichnls[0]_i_3_n_0\,
I2 => \conv_wrows[2]_i_2_n_0\,
I3 => conv_wrows(1),
I4 => \conv_wrows[2]_i_3_n_0\,
O => \conv_wrows[1]_i_1_n_0\
);
\conv_wrows[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF80007F008000"
)
port map (
I0 => conv_wrows(0),
I1 => conv_wrows(1),
I2 => \conv_ichnls[0]_i_3_n_0\,
I3 => \conv_wrows[2]_i_2_n_0\,
I4 => conv_wrows(2),
I5 => \conv_wrows[2]_i_3_n_0\,
O => \conv_wrows[2]_i_1_n_0\
);
\conv_wrows[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => conv_state(2),
I1 => conv_state(0),
I2 => conv_state(1),
O => \conv_wrows[2]_i_2_n_0\
);
\conv_wrows[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"AFDA"
)
port map (
I0 => conv_state(1),
I1 => conv_icols(5),
I2 => conv_state(0),
I3 => conv_state(2),
O => \conv_wrows[2]_i_3_n_0\
);
\conv_wrows_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wrows[0]_i_1_n_0\,
Q => conv_wrows(0)
);
\conv_wrows_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wrows[1]_i_1_n_0\,
Q => conv_wrows(1)
);
\conv_wrows_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \conv_wrows[2]_i_1_n_0\,
Q => conv_wrows(2)
);
conv_zero_pad_en_inferred_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => col_addr_underflow,
I1 => col_addr_overflow,
I2 => row_addr_overflow,
I3 => row_addr_underflow,
O => conv_zero_pad_en
);
\current_col[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_col(0),
I1 => \conv_ichnls[2]_i_3_n_0\,
I2 => calc_col_addr(0),
I3 => \current_col[5]_i_2_n_0\,
O => \current_col[0]_i_1_n_0\
);
\current_col[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_col(1),
I1 => \conv_ichnls[2]_i_3_n_0\,
I2 => calc_col_addr(1),
I3 => \current_col[5]_i_2_n_0\,
O => \current_col[1]_i_1_n_0\
);
\current_col[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_col(2),
I1 => \conv_ichnls[2]_i_3_n_0\,
I2 => calc_col_addr(2),
I3 => \current_col[5]_i_2_n_0\,
O => \current_col[2]_i_1_n_0\
);
\current_col[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_col(3),
I1 => \conv_ichnls[2]_i_3_n_0\,
I2 => calc_col_addr(3),
I3 => \current_col[5]_i_2_n_0\,
O => \current_col[3]_i_1_n_0\
);
\current_col[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_col(4),
I1 => \conv_ichnls[2]_i_3_n_0\,
I2 => calc_col_addr(4),
I3 => \current_col[5]_i_2_n_0\,
O => \current_col[4]_i_1_n_0\
);
\current_col[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_col(5),
I1 => \conv_ichnls[2]_i_3_n_0\,
I2 => calc_col_addr(5),
I3 => \current_col[5]_i_2_n_0\,
O => \current_col[5]_i_1_n_0\
);
\current_col[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => \conv_ichnls[0]_i_3_n_0\,
I1 => conv_state(2),
I2 => conv_state(0),
I3 => conv_state(1),
I4 => col_addr_underflow,
I5 => col_addr_overflow,
O => \current_col[5]_i_2_n_0\
);
\current_col_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_col[0]_i_1_n_0\,
Q => current_col(0)
);
\current_col_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_col[1]_i_1_n_0\,
Q => current_col(1)
);
\current_col_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_col[2]_i_1_n_0\,
Q => current_col(2)
);
\current_col_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_col[3]_i_1_n_0\,
Q => current_col(3)
);
\current_col_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_col[4]_i_1_n_0\,
Q => current_col(4)
);
\current_col_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_col[5]_i_1_n_0\,
Q => current_col(5)
);
\current_row[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_row(0),
I1 => \current_row[5]_i_2_n_0\,
I2 => calc_row_addr(0),
I3 => \current_row[5]_i_3_n_0\,
O => \current_row[0]_i_1_n_0\
);
\current_row[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_row(1),
I1 => \current_row[5]_i_2_n_0\,
I2 => calc_row_addr(1),
I3 => \current_row[5]_i_3_n_0\,
O => \current_row[1]_i_1_n_0\
);
\current_row[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_row(2),
I1 => \current_row[5]_i_2_n_0\,
I2 => calc_row_addr(2),
I3 => \current_row[5]_i_3_n_0\,
O => \current_row[2]_i_1_n_0\
);
\current_row[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_row(3),
I1 => \current_row[5]_i_2_n_0\,
I2 => calc_row_addr(3),
I3 => \current_row[5]_i_3_n_0\,
O => \current_row[3]_i_1_n_0\
);
\current_row[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_row(4),
I1 => \current_row[5]_i_2_n_0\,
I2 => calc_row_addr(4),
I3 => \current_row[5]_i_3_n_0\,
O => \current_row[4]_i_1_n_0\
);
\current_row[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => current_row(5),
I1 => \current_row[5]_i_2_n_0\,
I2 => calc_row_addr(5),
I3 => \current_row[5]_i_3_n_0\,
O => \current_row[5]_i_1_n_0\
);
\current_row[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFA888"
)
port map (
I0 => conv_state(2),
I1 => conv_wrows(2),
I2 => conv_wrows(1),
I3 => conv_wrows(0),
I4 => conv_state(1),
I5 => conv_state(0),
O => \current_row[5]_i_2_n_0\
);
\current_row[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000101010"
)
port map (
I0 => row_addr_underflow,
I1 => row_addr_overflow,
I2 => \conv_icols[5]_i_4_n_0\,
I3 => conv_wrows(0),
I4 => conv_wrows(1),
I5 => conv_wrows(2),
O => \current_row[5]_i_3_n_0\
);
\current_row_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_row[0]_i_1_n_0\,
Q => current_row(0)
);
\current_row_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_row[1]_i_1_n_0\,
Q => current_row(1)
);
\current_row_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_row[2]_i_1_n_0\,
Q => current_row(2)
);
\current_row_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_row[3]_i_1_n_0\,
Q => current_row(3)
);
\current_row_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_row[4]_i_1_n_0\,
Q => current_row(4)
);
\current_row_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \current_row[5]_i_1_n_0\,
Q => current_row(5)
);
\i__carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => current_col(5),
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => current_col(4),
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_col(3),
I1 => current_col(5),
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_col(2),
I1 => current_col(4),
O => \i__carry__0_i_4_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_col(1),
I1 => current_col(3),
O => \i__carry_i_1_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_col(0),
I1 => current_col(2),
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => current_col(1),
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => current_col(0),
O => \i__carry_i_4_n_0\
);
\in00_inferred__0/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => sum_row_addr(4),
I1 => sum_row_addr(3),
I2 => sum_row_addr(5),
I3 => sum_row_addr(0),
I4 => sum_row_addr(1),
I5 => sum_row_addr(2),
O => row_addr_underflow
);
\in00_inferred__2/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => sum_col_addr(4),
I1 => sum_col_addr(3),
I2 => sum_col_addr(5),
I3 => sum_col_addr(0),
I4 => sum_col_addr(1),
I5 => sum_col_addr(2),
O => col_addr_underflow
);
\in00_inferred__4/i_\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum_row_addr(0),
O => calc_row_addr(0)
);
\in00_inferred__5/i_\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum_col_addr(0),
O => calc_col_addr(0)
);
in01_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => in01_carry_n_0,
CO(2) => in01_carry_n_1,
CO(1) => in01_carry_n_2,
CO(0) => in01_carry_n_3,
CYINIT => '0',
DI(3) => in01_carry_i_1_n_6,
DI(2) => in01_carry_i_1_n_7,
DI(1 downto 0) => B"01",
O(3 downto 0) => in01(3 downto 0),
S(3) => in01_carry_i_2_n_0,
S(2) => in01_carry_i_3_n_0,
S(1) => in01_carry_i_4_n_0,
S(0) => in01_carry_i_5_n_0
);
\in01_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => in01_carry_n_0,
CO(3) => \in01_carry__0_n_0\,
CO(2) => \in01_carry__0_n_1\,
CO(1) => \in01_carry__0_n_2\,
CO(0) => \in01_carry__0_n_3\,
CYINIT => '0',
DI(3) => \in01_carry__0_i_1_n_6\,
DI(2) => \in01_carry__0_i_1_n_7\,
DI(1) => in01_carry_i_1_n_4,
DI(0) => in01_carry_i_1_n_5,
O(3 downto 0) => in01(7 downto 4),
S(3) => \in01_carry__0_i_2_n_0\,
S(2) => \in01_carry__0_i_3_n_0\,
S(1) => \in01_carry__0_i_4_n_0\,
S(0) => \in01_carry__0_i_5_n_0\
);
\in01_carry__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => in01_carry_i_1_n_0,
CO(3) => \in01_carry__0_i_1_n_0\,
CO(2) => \in01_carry__0_i_1_n_1\,
CO(1) => \in01_carry__0_i_1_n_2\,
CO(0) => \in01_carry__0_i_1_n_3\,
CYINIT => '0',
DI(3) => \in01_carry__0_i_6_n_0\,
DI(2) => \in01_carry__0_i_7_n_0\,
DI(1) => \in01_carry__0_i_8_n_0\,
DI(0) => \in01_carry__0_i_9_n_0\,
O(3) => \in01_carry__0_i_1_n_4\,
O(2) => \in01_carry__0_i_1_n_5\,
O(1) => \in01_carry__0_i_1_n_6\,
O(0) => \in01_carry__0_i_1_n_7\,
S(3) => \in01_carry__0_i_10_n_0\,
S(2) => \in01_carry__0_i_11_n_0\,
S(1) => \in01_carry__0_i_12_n_0\,
S(0) => \in01_carry__0_i_13_n_0\
);
\in01_carry__0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"F1F58F8F"
)
port map (
I0 => conv_wfltrs(2),
I1 => conv_wfltrs(1),
I2 => conv_wfltrs(4),
I3 => conv_wfltrs(0),
I4 => conv_wfltrs(3),
O => \in01_carry__0_i_10_n_0\
);
\in01_carry__0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0A3F303"
)
port map (
I0 => conv_wfltrs(0),
I1 => conv_wfltrs(4),
I2 => conv_wfltrs(3),
I3 => conv_wfltrs(2),
I4 => conv_wfltrs(1),
O => \in01_carry__0_i_11_n_0\
);
\in01_carry__0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FF0C105"
)
port map (
I0 => conv_wfltrs(3),
I1 => conv_wfltrs(0),
I2 => conv_wfltrs(4),
I3 => conv_wfltrs(1),
I4 => conv_wfltrs(2),
O => \in01_carry__0_i_12_n_0\
);
\in01_carry__0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"9C3C39C9"
)
port map (
I0 => conv_wfltrs(2),
I1 => conv_wfltrs(4),
I2 => conv_wfltrs(1),
I3 => conv_wfltrs(0),
I4 => conv_wfltrs(3),
O => \in01_carry__0_i_13_n_0\
);
\in01_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \in01_carry__0_i_1_n_6\,
I1 => \in01_carry__0_i_1_n_4\,
O => \in01_carry__0_i_2_n_0\
);
\in01_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \in01_carry__0_i_1_n_7\,
I1 => \in01_carry__0_i_1_n_5\,
O => \in01_carry__0_i_3_n_0\
);
\in01_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => in01_carry_i_1_n_4,
I1 => \in01_carry__0_i_1_n_6\,
O => \in01_carry__0_i_4_n_0\
);
\in01_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => in01_carry_i_1_n_5,
I1 => \in01_carry__0_i_1_n_7\,
O => \in01_carry__0_i_5_n_0\
);
\in01_carry__0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A5A5850"
)
port map (
I0 => conv_wfltrs(3),
I1 => conv_wfltrs(0),
I2 => conv_wfltrs(4),
I3 => conv_wfltrs(1),
I4 => conv_wfltrs(2),
O => \in01_carry__0_i_6_n_0\
);
\in01_carry__0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"C9996C6C"
)
port map (
I0 => conv_wfltrs(2),
I1 => conv_wfltrs(4),
I2 => conv_wfltrs(1),
I3 => conv_wfltrs(0),
I4 => conv_wfltrs(3),
O => \in01_carry__0_i_7_n_0\
);
\in01_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"996C"
)
port map (
I0 => conv_wfltrs(1),
I1 => conv_wfltrs(3),
I2 => conv_wfltrs(0),
I3 => conv_wfltrs(2),
O => \in01_carry__0_i_8_n_0\
);
\in01_carry__0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"50AF2AD5"
)
port map (
I0 => conv_wfltrs(3),
I1 => conv_wfltrs(0),
I2 => conv_wfltrs(1),
I3 => conv_wfltrs(4),
I4 => conv_wfltrs(2),
O => \in01_carry__0_i_9_n_0\
);
\in01_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \in01_carry__0_n_0\,
CO(3 downto 0) => \NLW_in01_carry__1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_in01_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => in01(8),
S(3 downto 1) => B"000",
S(0) => \in01_carry__1_i_1_n_0\
);
\in01_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \in01_carry__0_i_1_n_5\,
I1 => \in01_carry__1_i_2_n_7\,
O => \in01_carry__1_i_1_n_0\
);
\in01_carry__1_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \in01_carry__0_i_1_n_0\,
CO(3 downto 0) => \NLW_in01_carry__1_i_2_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_in01_carry__1_i_2_O_UNCONNECTED\(3 downto 1),
O(0) => \in01_carry__1_i_2_n_7\,
S(3 downto 1) => B"000",
S(0) => \in01_carry__1_i_3_n_0\
);
\in01_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"07FF"
)
port map (
I0 => conv_wfltrs(1),
I1 => conv_wfltrs(2),
I2 => conv_wfltrs(3),
I3 => conv_wfltrs(4),
O => \in01_carry__1_i_3_n_0\
);
in01_carry_i_1: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => in01_carry_i_1_n_0,
CO(2) => in01_carry_i_1_n_1,
CO(1) => in01_carry_i_1_n_2,
CO(0) => in01_carry_i_1_n_3,
CYINIT => '0',
DI(3) => in01_carry_i_6_n_0,
DI(2) => conv_wfltrs(0),
DI(1 downto 0) => B"01",
O(3) => in01_carry_i_1_n_4,
O(2) => in01_carry_i_1_n_5,
O(1) => in01_carry_i_1_n_6,
O(0) => in01_carry_i_1_n_7,
S(3) => in01_carry_i_7_n_0,
S(2) => in01_carry_i_8_n_0,
S(1) => in01_carry_i_9_n_0,
S(0) => in01_carry_i_10_n_0
);
in01_carry_i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => conv_wfltrs(0),
O => in01_carry_i_10_n_0
);
in01_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => in01_carry_i_1_n_6,
I1 => in01_carry_i_1_n_4,
O => in01_carry_i_2_n_0
);
in01_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => in01_carry_i_1_n_7,
I1 => in01_carry_i_1_n_5,
O => in01_carry_i_3_n_0
);
in01_carry_i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => in01_carry_i_1_n_6,
O => in01_carry_i_4_n_0
);
in01_carry_i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => in01_carry_i_1_n_7,
O => in01_carry_i_5_n_0
);
in01_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"4BA5"
)
port map (
I0 => conv_wfltrs(2),
I1 => conv_wfltrs(0),
I2 => conv_wfltrs(3),
I3 => conv_wfltrs(1),
O => in01_carry_i_6_n_0
);
in01_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"3CC9"
)
port map (
I0 => conv_wfltrs(1),
I1 => conv_wfltrs(3),
I2 => conv_wfltrs(0),
I3 => conv_wfltrs(2),
O => in01_carry_i_7_n_0
);
in01_carry_i_8: unisim.vcomponents.LUT3
generic map(
INIT => X"C9"
)
port map (
I0 => conv_wfltrs(0),
I1 => conv_wfltrs(2),
I2 => conv_wfltrs(1),
O => in01_carry_i_8_n_0
);
in01_carry_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => conv_wfltrs(0),
I1 => conv_wfltrs(1),
O => in01_carry_i_9_n_0
);
in02_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => in02_carry_n_0,
CO(2) => in02_carry_n_1,
CO(1) => in02_carry_n_2,
CO(0) => in02_carry_n_3,
CYINIT => '0',
DI(3 downto 2) => current_row(1 downto 0),
DI(1 downto 0) => B"01",
O(3 downto 0) => in01_1(3 downto 0),
S(3) => in02_carry_i_1_n_0,
S(2) => in02_carry_i_2_n_0,
S(1) => in02_carry_i_3_n_0,
S(0) => in02_carry_i_4_n_0
);
\in02_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => in02_carry_n_0,
CO(3 downto 2) => \NLW_in02_carry__0_CO_UNCONNECTED\(3 downto 2),
CO(1) => \in02_carry__0_n_2\,
CO(0) => \in02_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => current_row(3 downto 2),
O(3) => \NLW_in02_carry__0_O_UNCONNECTED\(3),
O(2 downto 0) => in01_1(6 downto 4),
S(3) => '0',
S(2) => \in02_carry__0_i_1_n_0\,
S(1) => \in02_carry__0_i_2_n_0\,
S(0) => \in02_carry__0_i_3_n_0\
);
\in02_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => current_row(4),
O => \in02_carry__0_i_1_n_0\
);
\in02_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_row(3),
I1 => current_row(5),
O => \in02_carry__0_i_2_n_0\
);
\in02_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_row(2),
I1 => current_row(4),
O => \in02_carry__0_i_3_n_0\
);
in02_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_row(1),
I1 => current_row(3),
O => in02_carry_i_1_n_0
);
in02_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => current_row(0),
I1 => current_row(2),
O => in02_carry_i_2_n_0
);
in02_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => current_row(1),
O => in02_carry_i_3_n_0
);
in02_carry_i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => current_row(0),
O => in02_carry_i_4_n_0
);
\in02_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \in02_inferred__0/i__carry_n_0\,
CO(2) => \in02_inferred__0/i__carry_n_1\,
CO(1) => \in02_inferred__0/i__carry_n_2\,
CO(0) => \in02_inferred__0/i__carry_n_3\,
CYINIT => '0',
DI(3 downto 2) => current_col(1 downto 0),
DI(1 downto 0) => B"01",
O(3 downto 0) => in02(3 downto 0),
S(3) => \i__carry_i_1_n_0\,
S(2) => \i__carry_i_2_n_0\,
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
\in02_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \in02_inferred__0/i__carry_n_0\,
CO(3) => \NLW_in02_inferred__0/i__carry__0_CO_UNCONNECTED\(3),
CO(2) => \in02_inferred__0/i__carry__0_n_1\,
CO(1) => \in02_inferred__0/i__carry__0_n_2\,
CO(0) => \in02_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => current_col(4 downto 2),
O(3 downto 0) => in02(7 downto 4),
S(3) => \i__carry__0_i_1_n_0\,
S(2) => \i__carry__0_i_2_n_0\,
S(1) => \i__carry__0_i_3_n_0\,
S(0) => \i__carry__0_i_4_n_0\
);
\input_bram_rd_adddr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(0),
I1 => conv_state(2),
O => p_1_in(0)
);
\input_bram_rd_adddr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(10),
I1 => conv_state(2),
O => p_1_in(10)
);
\input_bram_rd_adddr[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"010101010101FF01"
)
port map (
I0 => conv_state(2),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => \input_bram_rd_adddr[11]_i_3_n_0\,
I4 => conv_ichnls(2),
I5 => conv_zero_pad_en,
O => \input_bram_rd_adddr[11]_i_1_n_0\
);
\input_bram_rd_adddr[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(11),
I1 => conv_state(2),
O => p_1_in(11)
);
\input_bram_rd_adddr[11]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080808"
)
port map (
I0 => conv_state(2),
I1 => conv_state(1),
I2 => conv_state(0),
I3 => conv_ichnls(1),
I4 => conv_ichnls(0),
O => \input_bram_rd_adddr[11]_i_3_n_0\
);
\input_bram_rd_adddr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(1),
I1 => conv_state(2),
O => p_1_in(1)
);
\input_bram_rd_adddr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(2),
I1 => conv_state(2),
O => p_1_in(2)
);
\input_bram_rd_adddr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(3),
I1 => conv_state(2),
O => p_1_in(3)
);
\input_bram_rd_adddr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(4),
I1 => conv_state(2),
O => p_1_in(4)
);
\input_bram_rd_adddr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(5),
I1 => conv_state(2),
O => p_1_in(5)
);
\input_bram_rd_adddr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(6),
I1 => conv_state(2),
O => p_1_in(6)
);
\input_bram_rd_adddr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(7),
I1 => conv_state(2),
O => p_1_in(7)
);
\input_bram_rd_adddr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(8),
I1 => conv_state(2),
O => p_1_in(8)
);
\input_bram_rd_adddr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_iaddr(9),
I1 => conv_state(2),
O => p_1_in(9)
);
\input_bram_rd_adddr_reg[0]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(0),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(0)
);
\input_bram_rd_adddr_reg[10]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(10),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(10)
);
\input_bram_rd_adddr_reg[11]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(11),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(11)
);
\input_bram_rd_adddr_reg[1]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(1),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(1)
);
\input_bram_rd_adddr_reg[2]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(2),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(2)
);
\input_bram_rd_adddr_reg[3]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(3),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(3)
);
\input_bram_rd_adddr_reg[4]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(4),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(4)
);
\input_bram_rd_adddr_reg[5]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(5),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(5)
);
\input_bram_rd_adddr_reg[6]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(6),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(6)
);
\input_bram_rd_adddr_reg[7]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(7),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(7)
);
\input_bram_rd_adddr_reg[8]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(8),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(8)
);
\input_bram_rd_adddr_reg[9]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => p_1_in(9),
PRE => \^ar\(0),
Q => input_bram_rd_adddr(9)
);
input_bram_rd_en_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => '1',
Q => input_bram_rd_en
);
input_read_req_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000007000000"
)
port map (
I0 => conv_ichnls(0),
I1 => conv_ichnls(1),
I2 => conv_state(0),
I3 => conv_state(1),
I4 => conv_state(2),
I5 => conv_ichnls(2),
O => input_read_req_i_1_n_0
);
\input_read_req_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => input_read_req,
Q => input_read_req_r(0),
R => '0'
);
\input_read_req_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => input_read_req_r(0),
Q => input_read_req_r(1),
R => '0'
);
input_read_req_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => input_read_req_i_1_n_0,
Q => input_read_req
);
\mac_o_last[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(0),
I1 => mac_o_last(0),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[0]_i_1_n_0\
);
\mac_o_last[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(10),
I1 => mac_o_last(10),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[10]_i_1_n_0\
);
\mac_o_last[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(11),
I1 => mac_o_last(11),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[11]_i_1_n_0\
);
\mac_o_last[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(12),
I1 => mac_o_last(12),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[12]_i_1_n_0\
);
\mac_o_last[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(13),
I1 => mac_o_last(13),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[13]_i_1_n_0\
);
\mac_o_last[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(14),
I1 => mac_o_last(14),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[14]_i_1_n_0\
);
\mac_o_last[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(15),
I1 => mac_o_last(15),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[15]_i_1_n_0\
);
\mac_o_last[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(1),
I1 => mac_o_last(1),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[1]_i_1_n_0\
);
\mac_o_last[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(2),
I1 => mac_o_last(2),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[2]_i_1_n_0\
);
\mac_o_last[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(3),
I1 => mac_o_last(3),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[3]_i_1_n_0\
);
\mac_o_last[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(4),
I1 => mac_o_last(4),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[4]_i_1_n_0\
);
\mac_o_last[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(5),
I1 => mac_o_last(5),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[5]_i_1_n_0\
);
\mac_o_last[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(6),
I1 => mac_o_last(6),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[6]_i_1_n_0\
);
\mac_o_last[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(7),
I1 => mac_o_last(7),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[7]_i_1_n_0\
);
\mac_o_last[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(8),
I1 => mac_o_last(8),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[8]_i_1_n_0\
);
\mac_o_last[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA0AAAACCC0CCCC"
)
port map (
I0 => mac_o(9),
I1 => mac_o_last(9),
I2 => conv_state(2),
I3 => conv_state(1),
I4 => conv_state(0),
I5 => multadd_op_valid,
O => \mac_o_last[9]_i_1_n_0\
);
\mac_o_last_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[0]_i_1_n_0\,
Q => mac_o_last(0)
);
\mac_o_last_reg[10]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[10]_i_1_n_0\,
Q => mac_o_last(10)
);
\mac_o_last_reg[11]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[11]_i_1_n_0\,
Q => mac_o_last(11)
);
\mac_o_last_reg[12]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[12]_i_1_n_0\,
Q => mac_o_last(12)
);
\mac_o_last_reg[13]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[13]_i_1_n_0\,
Q => mac_o_last(13)
);
\mac_o_last_reg[14]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[14]_i_1_n_0\,
Q => mac_o_last(14)
);
\mac_o_last_reg[15]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[15]_i_1_n_0\,
Q => mac_o_last(15)
);
\mac_o_last_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[1]_i_1_n_0\,
Q => mac_o_last(1)
);
\mac_o_last_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[2]_i_1_n_0\,
Q => mac_o_last(2)
);
\mac_o_last_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[3]_i_1_n_0\,
Q => mac_o_last(3)
);
\mac_o_last_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[4]_i_1_n_0\,
Q => mac_o_last(4)
);
\mac_o_last_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[5]_i_1_n_0\,
Q => mac_o_last(5)
);
\mac_o_last_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[6]_i_1_n_0\,
Q => mac_o_last(6)
);
\mac_o_last_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[7]_i_1_n_0\,
Q => mac_o_last(7)
);
\mac_o_last_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[8]_i_1_n_0\,
Q => mac_o_last(8)
);
\mac_o_last_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last[9]_i_1_n_0\,
Q => mac_o_last(9)
);
\mac_o_last_relu[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(0),
I1 => mac_o_last(15),
O => \mac_o_last_relu[0]_i_1_n_0\
);
\mac_o_last_relu[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(10),
I1 => mac_o_last(15),
O => \mac_o_last_relu[10]_i_1_n_0\
);
\mac_o_last_relu[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(11),
I1 => mac_o_last(15),
O => \mac_o_last_relu[11]_i_1_n_0\
);
\mac_o_last_relu[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(12),
I1 => mac_o_last(15),
O => \mac_o_last_relu[12]_i_1_n_0\
);
\mac_o_last_relu[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(13),
I1 => mac_o_last(15),
O => \mac_o_last_relu[13]_i_1_n_0\
);
\mac_o_last_relu[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(14),
I1 => mac_o_last(15),
O => \mac_o_last_relu[14]_i_1_n_0\
);
\mac_o_last_relu[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(1),
I1 => mac_o_last(15),
O => \mac_o_last_relu[1]_i_1_n_0\
);
\mac_o_last_relu[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(2),
I1 => mac_o_last(15),
O => \mac_o_last_relu[2]_i_1_n_0\
);
\mac_o_last_relu[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(3),
I1 => mac_o_last(15),
O => \mac_o_last_relu[3]_i_1_n_0\
);
\mac_o_last_relu[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(4),
I1 => mac_o_last(15),
O => \mac_o_last_relu[4]_i_1_n_0\
);
\mac_o_last_relu[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(5),
I1 => mac_o_last(15),
O => \mac_o_last_relu[5]_i_1_n_0\
);
\mac_o_last_relu[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(6),
I1 => mac_o_last(15),
O => \mac_o_last_relu[6]_i_1_n_0\
);
\mac_o_last_relu[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(7),
I1 => mac_o_last(15),
O => \mac_o_last_relu[7]_i_1_n_0\
);
\mac_o_last_relu[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(8),
I1 => mac_o_last(15),
O => \mac_o_last_relu[8]_i_1_n_0\
);
\mac_o_last_relu[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mac_o_last(9),
I1 => mac_o_last(15),
O => \mac_o_last_relu[9]_i_1_n_0\
);
\mac_o_last_relu_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[0]_i_1_n_0\,
Q => mac_o_last_relu(0)
);
\mac_o_last_relu_reg[10]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[10]_i_1_n_0\,
Q => mac_o_last_relu(10)
);
\mac_o_last_relu_reg[11]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[11]_i_1_n_0\,
Q => mac_o_last_relu(11)
);
\mac_o_last_relu_reg[12]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[12]_i_1_n_0\,
Q => mac_o_last_relu(12)
);
\mac_o_last_relu_reg[13]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[13]_i_1_n_0\,
Q => mac_o_last_relu(13)
);
\mac_o_last_relu_reg[14]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[14]_i_1_n_0\,
Q => mac_o_last_relu(14)
);
\mac_o_last_relu_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[1]_i_1_n_0\,
Q => mac_o_last_relu(1)
);
\mac_o_last_relu_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[2]_i_1_n_0\,
Q => mac_o_last_relu(2)
);
\mac_o_last_relu_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[3]_i_1_n_0\,
Q => mac_o_last_relu(3)
);
\mac_o_last_relu_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[4]_i_1_n_0\,
Q => mac_o_last_relu(4)
);
\mac_o_last_relu_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[5]_i_1_n_0\,
Q => mac_o_last_relu(5)
);
\mac_o_last_relu_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[6]_i_1_n_0\,
Q => mac_o_last_relu(6)
);
\mac_o_last_relu_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[7]_i_1_n_0\,
Q => mac_o_last_relu(7)
);
\mac_o_last_relu_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[8]_i_1_n_0\,
Q => mac_o_last_relu(8)
);
\mac_o_last_relu_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mac_o_last_relu[9]_i_1_n_0\,
Q => mac_o_last_relu(9)
);
macinst0: entity work.vcnnbd_conv1l_top_0_0_fp_mult_add_16bit
port map (
aclk => clk,
m_axis_result_tdata(15 downto 0) => mac_o(15 downto 0),
m_axis_result_tuser(1 downto 0) => NLW_macinst0_m_axis_result_tuser_UNCONNECTED(1 downto 0),
m_axis_result_tvalid => multadd_op_valid,
s_axis_a_tdata(15 downto 0) => mult_a(15 downto 0),
s_axis_a_tready => macinst0_n_0,
s_axis_a_tvalid => multadd_en,
s_axis_b_tdata(15 downto 0) => mult_b(15 downto 0),
s_axis_b_tready => macinst0_n_1,
s_axis_b_tvalid => multadd_en,
s_axis_c_tdata(15 downto 0) => add_c(15 downto 0),
s_axis_c_tready => macinst0_n_2,
s_axis_c_tvalid => multadd_en
);
macinst0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(15),
I1 => multadd_op_valid,
I2 => mac_o_last(15),
O => add_c(15)
);
macinst0_i_10: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(6),
I1 => multadd_op_valid,
I2 => mac_o_last(6),
O => add_c(6)
);
macinst0_i_11: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(5),
I1 => multadd_op_valid,
I2 => mac_o_last(5),
O => add_c(5)
);
macinst0_i_12: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(4),
I1 => multadd_op_valid,
I2 => mac_o_last(4),
O => add_c(4)
);
macinst0_i_13: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(3),
I1 => multadd_op_valid,
I2 => mac_o_last(3),
O => add_c(3)
);
macinst0_i_14: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(2),
I1 => multadd_op_valid,
I2 => mac_o_last(2),
O => add_c(2)
);
macinst0_i_15: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(1),
I1 => multadd_op_valid,
I2 => mac_o_last(1),
O => add_c(1)
);
macinst0_i_16: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(0),
I1 => multadd_op_valid,
I2 => mac_o_last(0),
O => add_c(0)
);
macinst0_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(14),
I1 => multadd_op_valid,
I2 => mac_o_last(14),
O => add_c(14)
);
macinst0_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(13),
I1 => multadd_op_valid,
I2 => mac_o_last(13),
O => add_c(13)
);
macinst0_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(12),
I1 => multadd_op_valid,
I2 => mac_o_last(12),
O => add_c(12)
);
macinst0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(11),
I1 => multadd_op_valid,
I2 => mac_o_last(11),
O => add_c(11)
);
macinst0_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(10),
I1 => multadd_op_valid,
I2 => mac_o_last(10),
O => add_c(10)
);
macinst0_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(9),
I1 => multadd_op_valid,
I2 => mac_o_last(9),
O => add_c(9)
);
macinst0_i_8: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(8),
I1 => multadd_op_valid,
I2 => mac_o_last(8),
O => add_c(8)
);
macinst0_i_9: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_o(7),
I1 => multadd_op_valid,
I2 => mac_o_last(7),
O => add_c(7)
);
\mult_a[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(0),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[0]_i_1_n_0\
);
\mult_a[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(10),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[10]_i_1_n_0\
);
\mult_a[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(11),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[11]_i_1_n_0\
);
\mult_a[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(12),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[12]_i_1_n_0\
);
\mult_a[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(13),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[13]_i_1_n_0\
);
\mult_a[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(14),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[14]_i_1_n_0\
);
\mult_a[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(15),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[15]_i_1_n_0\
);
\mult_a[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(1),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[1]_i_1_n_0\
);
\mult_a[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(2),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[2]_i_1_n_0\
);
\mult_a[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(3),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[3]_i_1_n_0\
);
\mult_a[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(4),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[4]_i_1_n_0\
);
\mult_a[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(5),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[5]_i_1_n_0\
);
\mult_a[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(6),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[6]_i_1_n_0\
);
\mult_a[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(7),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[7]_i_1_n_0\
);
\mult_a[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(8),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[8]_i_1_n_0\
);
\mult_a[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => input_bram_rd_din(9),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_a[9]_i_1_n_0\
);
\mult_a_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[0]_i_1_n_0\,
Q => mult_a(0)
);
\mult_a_reg[10]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[10]_i_1_n_0\,
Q => mult_a(10)
);
\mult_a_reg[11]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[11]_i_1_n_0\,
Q => mult_a(11)
);
\mult_a_reg[12]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[12]_i_1_n_0\,
Q => mult_a(12)
);
\mult_a_reg[13]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[13]_i_1_n_0\,
Q => mult_a(13)
);
\mult_a_reg[14]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[14]_i_1_n_0\,
Q => mult_a(14)
);
\mult_a_reg[15]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[15]_i_1_n_0\,
Q => mult_a(15)
);
\mult_a_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[1]_i_1_n_0\,
Q => mult_a(1)
);
\mult_a_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[2]_i_1_n_0\,
Q => mult_a(2)
);
\mult_a_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[3]_i_1_n_0\,
Q => mult_a(3)
);
\mult_a_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[4]_i_1_n_0\,
Q => mult_a(4)
);
\mult_a_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[5]_i_1_n_0\,
Q => mult_a(5)
);
\mult_a_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[6]_i_1_n_0\,
Q => mult_a(6)
);
\mult_a_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[7]_i_1_n_0\,
Q => mult_a(7)
);
\mult_a_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[8]_i_1_n_0\,
Q => mult_a(8)
);
\mult_a_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_a[9]_i_1_n_0\,
Q => mult_a(9)
);
\mult_b[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(0),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[0]_i_1_n_0\
);
\mult_b[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(10),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[10]_i_1_n_0\
);
\mult_b[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(11),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[11]_i_1_n_0\
);
\mult_b[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(12),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[12]_i_1_n_0\
);
\mult_b[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(13),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[13]_i_1_n_0\
);
\mult_b[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(14),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[14]_i_1_n_0\
);
\mult_b[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(15),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[15]_i_1_n_0\
);
\mult_b[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(1),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[1]_i_1_n_0\
);
\mult_b[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(2),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[2]_i_1_n_0\
);
\mult_b[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(3),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[3]_i_1_n_0\
);
\mult_b[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(4),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[4]_i_1_n_0\
);
\mult_b[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(5),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[5]_i_1_n_0\
);
\mult_b[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(6),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[6]_i_1_n_0\
);
\mult_b[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(7),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[7]_i_1_n_0\
);
\mult_b[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(8),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[8]_i_1_n_0\
);
\mult_b[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => weight_bram_rd_din(9),
I1 => input_read_req_r(1),
I2 => macinst0_n_2,
I3 => macinst0_n_0,
I4 => macinst0_n_1,
I5 => conv_ip_zeros_r(1),
O => \mult_b[9]_i_1_n_0\
);
\mult_b_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[0]_i_1_n_0\,
Q => mult_b(0)
);
\mult_b_reg[10]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[10]_i_1_n_0\,
Q => mult_b(10)
);
\mult_b_reg[11]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[11]_i_1_n_0\,
Q => mult_b(11)
);
\mult_b_reg[12]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[12]_i_1_n_0\,
Q => mult_b(12)
);
\mult_b_reg[13]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[13]_i_1_n_0\,
Q => mult_b(13)
);
\mult_b_reg[14]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[14]_i_1_n_0\,
Q => mult_b(14)
);
\mult_b_reg[15]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[15]_i_1_n_0\,
Q => mult_b(15)
);
\mult_b_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[1]_i_1_n_0\,
Q => mult_b(1)
);
\mult_b_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[2]_i_1_n_0\,
Q => mult_b(2)
);
\mult_b_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[3]_i_1_n_0\,
Q => mult_b(3)
);
\mult_b_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[4]_i_1_n_0\,
Q => mult_b(4)
);
\mult_b_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[5]_i_1_n_0\,
Q => mult_b(5)
);
\mult_b_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[6]_i_1_n_0\,
Q => mult_b(6)
);
\mult_b_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[7]_i_1_n_0\,
Q => mult_b(7)
);
\mult_b_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[8]_i_1_n_0\,
Q => mult_b(8)
);
\mult_b_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \mult_b[9]_i_1_n_0\,
Q => mult_b(9)
);
multadd_en_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0008000"
)
port map (
I0 => conv_ip_zeros_r(1),
I1 => macinst0_n_2,
I2 => macinst0_n_0,
I3 => macinst0_n_1,
I4 => input_read_req_r(1),
O => multadd_en_i_1_n_0
);
multadd_en_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => multadd_en_i_1_n_0,
Q => multadd_en
);
n_output_bram_wr_addr0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => n_output_bram_wr_addr0_carry_n_0,
CO(2) => n_output_bram_wr_addr0_carry_n_1,
CO(1) => n_output_bram_wr_addr0_carry_n_2,
CO(0) => n_output_bram_wr_addr0_carry_n_3,
CYINIT => \^output_bram_wr_addr\(0),
DI(3 downto 0) => B"0000",
O(3 downto 0) => n_output_bram_wr_addr0(4 downto 1),
S(3) => n_output_bram_wr_addr0_carry_i_1_n_0,
S(2) => n_output_bram_wr_addr0_carry_i_2_n_0,
S(1) => n_output_bram_wr_addr0_carry_i_3_n_0,
S(0) => n_output_bram_wr_addr0_carry_i_4_n_0
);
\n_output_bram_wr_addr0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => n_output_bram_wr_addr0_carry_n_0,
CO(3) => \n_output_bram_wr_addr0_carry__0_n_0\,
CO(2) => \n_output_bram_wr_addr0_carry__0_n_1\,
CO(1) => \n_output_bram_wr_addr0_carry__0_n_2\,
CO(0) => \n_output_bram_wr_addr0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => n_output_bram_wr_addr0(8 downto 5),
S(3) => \n_output_bram_wr_addr0_carry__0_i_1_n_0\,
S(2) => \n_output_bram_wr_addr0_carry__0_i_2_n_0\,
S(1) => \n_output_bram_wr_addr0_carry__0_i_3_n_0\,
S(0) => \n_output_bram_wr_addr0_carry__0_i_4_n_0\
);
\n_output_bram_wr_addr0_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(8),
O => \n_output_bram_wr_addr0_carry__0_i_1_n_0\
);
\n_output_bram_wr_addr0_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(7),
O => \n_output_bram_wr_addr0_carry__0_i_2_n_0\
);
\n_output_bram_wr_addr0_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(6),
O => \n_output_bram_wr_addr0_carry__0_i_3_n_0\
);
\n_output_bram_wr_addr0_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(5),
O => \n_output_bram_wr_addr0_carry__0_i_4_n_0\
);
\n_output_bram_wr_addr0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \n_output_bram_wr_addr0_carry__0_n_0\,
CO(3) => \n_output_bram_wr_addr0_carry__1_n_0\,
CO(2) => \n_output_bram_wr_addr0_carry__1_n_1\,
CO(1) => \n_output_bram_wr_addr0_carry__1_n_2\,
CO(0) => \n_output_bram_wr_addr0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => n_output_bram_wr_addr0(12 downto 9),
S(3) => \n_output_bram_wr_addr0_carry__1_i_1_n_0\,
S(2) => \n_output_bram_wr_addr0_carry__1_i_2_n_0\,
S(1) => \n_output_bram_wr_addr0_carry__1_i_3_n_0\,
S(0) => \n_output_bram_wr_addr0_carry__1_i_4_n_0\
);
\n_output_bram_wr_addr0_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(12),
O => \n_output_bram_wr_addr0_carry__1_i_1_n_0\
);
\n_output_bram_wr_addr0_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(11),
O => \n_output_bram_wr_addr0_carry__1_i_2_n_0\
);
\n_output_bram_wr_addr0_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(10),
O => \n_output_bram_wr_addr0_carry__1_i_3_n_0\
);
\n_output_bram_wr_addr0_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(9),
O => \n_output_bram_wr_addr0_carry__1_i_4_n_0\
);
\n_output_bram_wr_addr0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \n_output_bram_wr_addr0_carry__1_n_0\,
CO(3 downto 0) => \NLW_n_output_bram_wr_addr0_carry__2_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_n_output_bram_wr_addr0_carry__2_O_UNCONNECTED\(3 downto 1),
O(0) => n_output_bram_wr_addr0(13),
S(3 downto 1) => B"000",
S(0) => \n_output_bram_wr_addr0_carry__2_i_1_n_0\
);
\n_output_bram_wr_addr0_carry__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(13),
O => \n_output_bram_wr_addr0_carry__2_i_1_n_0\
);
n_output_bram_wr_addr0_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(4),
O => n_output_bram_wr_addr0_carry_i_1_n_0
);
n_output_bram_wr_addr0_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(3),
O => n_output_bram_wr_addr0_carry_i_2_n_0
);
n_output_bram_wr_addr0_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(2),
O => n_output_bram_wr_addr0_carry_i_3_n_0
);
n_output_bram_wr_addr0_carry_i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^output_bram_wr_addr\(1),
O => n_output_bram_wr_addr0_carry_i_4_n_0
);
\output_bram_wr_addr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => conv_state(1),
I1 => \^output_bram_wr_addr\(0),
O => \output_bram_wr_addr[0]_i_1_n_0\
);
\output_bram_wr_addr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(10),
I1 => conv_state(1),
O => \output_bram_wr_addr[10]_i_1_n_0\
);
\output_bram_wr_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(11),
I1 => conv_state(1),
O => \output_bram_wr_addr[11]_i_1_n_0\
);
\output_bram_wr_addr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(12),
I1 => conv_state(1),
O => \output_bram_wr_addr[12]_i_1_n_0\
);
\output_bram_wr_addr[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0301"
)
port map (
I0 => conv_state(1),
I1 => conv_state(0),
I2 => conv_state(2),
I3 => conv_irows(5),
O => \output_bram_wr_addr[13]_i_1_n_0\
);
\output_bram_wr_addr[13]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(13),
I1 => conv_state(1),
O => \output_bram_wr_addr[13]_i_2_n_0\
);
\output_bram_wr_addr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(1),
I1 => conv_state(1),
O => \output_bram_wr_addr[1]_i_1_n_0\
);
\output_bram_wr_addr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(2),
I1 => conv_state(1),
O => \output_bram_wr_addr[2]_i_1_n_0\
);
\output_bram_wr_addr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(3),
I1 => conv_state(1),
O => \output_bram_wr_addr[3]_i_1_n_0\
);
\output_bram_wr_addr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(4),
I1 => conv_state(1),
O => \output_bram_wr_addr[4]_i_1_n_0\
);
\output_bram_wr_addr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(5),
I1 => conv_state(1),
O => \output_bram_wr_addr[5]_i_1_n_0\
);
\output_bram_wr_addr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(6),
I1 => conv_state(1),
O => \output_bram_wr_addr[6]_i_1_n_0\
);
\output_bram_wr_addr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(7),
I1 => conv_state(1),
O => \output_bram_wr_addr[7]_i_1_n_0\
);
\output_bram_wr_addr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(8),
I1 => conv_state(1),
O => \output_bram_wr_addr[8]_i_1_n_0\
);
\output_bram_wr_addr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => n_output_bram_wr_addr0(9),
I1 => conv_state(1),
O => \output_bram_wr_addr[9]_i_1_n_0\
);
\output_bram_wr_addr_reg[0]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[0]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(0)
);
\output_bram_wr_addr_reg[10]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[10]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(10)
);
\output_bram_wr_addr_reg[11]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[11]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(11)
);
\output_bram_wr_addr_reg[12]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[12]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(12)
);
\output_bram_wr_addr_reg[13]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[13]_i_2_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(13)
);
\output_bram_wr_addr_reg[1]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[1]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(1)
);
\output_bram_wr_addr_reg[2]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[2]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(2)
);
\output_bram_wr_addr_reg[3]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[3]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(3)
);
\output_bram_wr_addr_reg[4]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[4]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(4)
);
\output_bram_wr_addr_reg[5]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[5]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(5)
);
\output_bram_wr_addr_reg[6]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[6]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(6)
);
\output_bram_wr_addr_reg[7]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[7]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(7)
);
\output_bram_wr_addr_reg[8]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[8]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(8)
);
\output_bram_wr_addr_reg[9]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \output_bram_wr_addr[13]_i_1_n_0\,
D => \output_bram_wr_addr[9]_i_1_n_0\,
PRE => \^ar\(0),
Q => \^output_bram_wr_addr\(9)
);
\output_bram_wr_dout[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(0),
O => \output_bram_wr_dout[0]_i_1_n_0\
);
\output_bram_wr_dout[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(10),
O => \output_bram_wr_dout[10]_i_1_n_0\
);
\output_bram_wr_dout[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(11),
O => \output_bram_wr_dout[11]_i_1_n_0\
);
\output_bram_wr_dout[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(12),
O => \output_bram_wr_dout[12]_i_1_n_0\
);
\output_bram_wr_dout[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(13),
O => \output_bram_wr_dout[13]_i_1_n_0\
);
\output_bram_wr_dout[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(14),
O => \output_bram_wr_dout[14]_i_1_n_0\
);
\output_bram_wr_dout[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(1),
O => \output_bram_wr_dout[1]_i_1_n_0\
);
\output_bram_wr_dout[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(2),
O => \output_bram_wr_dout[2]_i_1_n_0\
);
\output_bram_wr_dout[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(3),
O => \output_bram_wr_dout[3]_i_1_n_0\
);
\output_bram_wr_dout[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(4),
O => \output_bram_wr_dout[4]_i_1_n_0\
);
\output_bram_wr_dout[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(5),
O => \output_bram_wr_dout[5]_i_1_n_0\
);
\output_bram_wr_dout[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(6),
O => \output_bram_wr_dout[6]_i_1_n_0\
);
\output_bram_wr_dout[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(7),
O => \output_bram_wr_dout[7]_i_1_n_0\
);
\output_bram_wr_dout[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(8),
O => \output_bram_wr_dout[8]_i_1_n_0\
);
\output_bram_wr_dout[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => conv_irows(5),
I1 => conv_state(0),
I2 => conv_state(1),
I3 => conv_state(2),
I4 => mac_o_last_relu(9),
O => \output_bram_wr_dout[9]_i_1_n_0\
);
\output_bram_wr_dout_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[0]_i_1_n_0\,
Q => output_bram_wr_dout(0)
);
\output_bram_wr_dout_reg[10]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[10]_i_1_n_0\,
Q => output_bram_wr_dout(10)
);
\output_bram_wr_dout_reg[11]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[11]_i_1_n_0\,
Q => output_bram_wr_dout(11)
);
\output_bram_wr_dout_reg[12]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[12]_i_1_n_0\,
Q => output_bram_wr_dout(12)
);
\output_bram_wr_dout_reg[13]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[13]_i_1_n_0\,
Q => output_bram_wr_dout(13)
);
\output_bram_wr_dout_reg[14]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[14]_i_1_n_0\,
Q => output_bram_wr_dout(14)
);
\output_bram_wr_dout_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[1]_i_1_n_0\,
Q => output_bram_wr_dout(1)
);
\output_bram_wr_dout_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[2]_i_1_n_0\,
Q => output_bram_wr_dout(2)
);
\output_bram_wr_dout_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[3]_i_1_n_0\,
Q => output_bram_wr_dout(3)
);
\output_bram_wr_dout_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[4]_i_1_n_0\,
Q => output_bram_wr_dout(4)
);
\output_bram_wr_dout_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[5]_i_1_n_0\,
Q => output_bram_wr_dout(5)
);
\output_bram_wr_dout_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[6]_i_1_n_0\,
Q => output_bram_wr_dout(6)
);
\output_bram_wr_dout_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[7]_i_1_n_0\,
Q => output_bram_wr_dout(7)
);
\output_bram_wr_dout_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[8]_i_1_n_0\,
Q => output_bram_wr_dout(8)
);
\output_bram_wr_dout_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => \output_bram_wr_dout[9]_i_1_n_0\,
Q => output_bram_wr_dout(9)
);
output_bram_wr_rst_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rstn,
O => \^ar\(0)
);
output_bram_wr_wen_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => conv_state(2),
I1 => conv_state(1),
I2 => conv_state(0),
I3 => conv_irows(5),
O => output_bram_wr_wen_i_1_n_0
);
output_bram_wr_wen_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => output_bram_wr_wen_i_1_n_0,
Q => output_bram_wr_wen
);
sum_col_addr_inferred_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => sum_col_addr_inferred_i_7_n_0,
I1 => conv_icols(3),
I2 => conv_icols(4),
I3 => conv_icols(5),
O => sum_col_addr(5)
);
sum_col_addr_inferred_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => conv_icols(3),
I1 => sum_col_addr_inferred_i_7_n_0,
I2 => conv_icols(4),
O => sum_col_addr(4)
);
sum_col_addr_inferred_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => sum_col_addr_inferred_i_7_n_0,
I1 => conv_icols(3),
O => sum_col_addr(3)
);
sum_col_addr_inferred_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"EA80157F157FEA80"
)
port map (
I0 => conv_wcols(1),
I1 => conv_wcols(0),
I2 => conv_icols(0),
I3 => conv_icols(1),
I4 => conv_wcols(2),
I5 => conv_icols(2),
O => sum_col_addr(2)
);
sum_col_addr_inferred_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => conv_icols(0),
I1 => conv_wcols(0),
I2 => conv_wcols(1),
I3 => conv_icols(1),
O => sum_col_addr(1)
);
sum_col_addr_inferred_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_icols(0),
I1 => conv_wcols(0),
O => sum_col_addr(0)
);
sum_col_addr_inferred_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEA80EA800000"
)
port map (
I0 => conv_icols(1),
I1 => conv_icols(0),
I2 => conv_wcols(0),
I3 => conv_wcols(1),
I4 => conv_icols(2),
I5 => conv_wcols(2),
O => sum_col_addr_inferred_i_7_n_0
);
sum_row_addr_inferred_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => sum_row_addr_inferred_i_7_n_0,
I1 => conv_irows(3),
I2 => conv_irows(4),
I3 => conv_irows(5),
O => sum_row_addr(5)
);
sum_row_addr_inferred_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => conv_irows(3),
I1 => sum_row_addr_inferred_i_7_n_0,
I2 => conv_irows(4),
O => sum_row_addr(4)
);
sum_row_addr_inferred_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => sum_row_addr_inferred_i_7_n_0,
I1 => conv_irows(3),
O => sum_row_addr(3)
);
sum_row_addr_inferred_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"EA80157F157FEA80"
)
port map (
I0 => conv_wrows(1),
I1 => conv_wrows(0),
I2 => conv_irows(0),
I3 => conv_irows(1),
I4 => conv_wrows(2),
I5 => conv_irows(2),
O => sum_row_addr(2)
);
sum_row_addr_inferred_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => conv_irows(0),
I1 => conv_wrows(0),
I2 => conv_wrows(1),
I3 => conv_irows(1),
O => sum_row_addr(1)
);
sum_row_addr_inferred_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => conv_irows(0),
I1 => conv_wrows(0),
O => sum_row_addr(0)
);
sum_row_addr_inferred_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEA80EA800000"
)
port map (
I0 => conv_irows(1),
I1 => conv_irows(0),
I2 => conv_wrows(0),
I3 => conv_wrows(1),
I4 => conv_irows(2),
I5 => conv_wrows(2),
O => sum_row_addr_inferred_i_7_n_0
);
\weight_bram_rd_adddr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(0),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[0]_i_1_n_0\
);
\weight_bram_rd_adddr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(1),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[1]_i_1_n_0\
);
\weight_bram_rd_adddr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(2),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[2]_i_1_n_0\
);
\weight_bram_rd_adddr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(3),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[3]_i_1_n_0\
);
\weight_bram_rd_adddr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(4),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[4]_i_1_n_0\
);
\weight_bram_rd_adddr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(5),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[5]_i_1_n_0\
);
\weight_bram_rd_adddr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(6),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[6]_i_1_n_0\
);
\weight_bram_rd_adddr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(7),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[7]_i_1_n_0\
);
\weight_bram_rd_adddr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => conv_waddr(8),
I1 => conv_state(2),
O => \weight_bram_rd_adddr[8]_i_1_n_0\
);
\weight_bram_rd_adddr_reg[0]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[0]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(0)
);
\weight_bram_rd_adddr_reg[1]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[1]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(1)
);
\weight_bram_rd_adddr_reg[2]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[2]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(2)
);
\weight_bram_rd_adddr_reg[3]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[3]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(3)
);
\weight_bram_rd_adddr_reg[4]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[4]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(4)
);
\weight_bram_rd_adddr_reg[5]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[5]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(5)
);
\weight_bram_rd_adddr_reg[6]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[6]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(6)
);
\weight_bram_rd_adddr_reg[7]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[7]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(7)
);
\weight_bram_rd_adddr_reg[8]\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => \input_bram_rd_adddr[11]_i_1_n_0\,
D => \weight_bram_rd_adddr[8]_i_1_n_0\,
PRE => \^ar\(0),
Q => weight_bram_rd_adddr(8)
);
weight_bram_rd_en_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => \^ar\(0),
D => '1',
Q => weight_bram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vcnnbd_conv1l_top_0_0 is
port (
clk : in STD_LOGIC;
rstn : in STD_LOGIC;
ap_start : in STD_LOGIC;
ap_ready : out STD_LOGIC;
ap_done : out STD_LOGIC;
input_bram_rd_clk : out STD_LOGIC;
input_bram_rd_rst : out STD_LOGIC;
input_bram_rd_en : out STD_LOGIC;
input_bram_rd_wen : out STD_LOGIC;
input_bram_rd_adddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
input_bram_rd_dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
input_bram_rd_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
weight_bram_rd_clk : out STD_LOGIC;
weight_bram_rd_rst : out STD_LOGIC;
weight_bram_rd_en : out STD_LOGIC;
weight_bram_rd_wen : out STD_LOGIC;
weight_bram_rd_adddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
weight_bram_rd_dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
weight_bram_rd_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
output_bram_wr_clk : out STD_LOGIC;
output_bram_wr_rst : out STD_LOGIC;
output_bram_wr_en : out STD_LOGIC;
output_bram_wr_wen : out STD_LOGIC;
output_bram_wr_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
output_bram_wr_dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
output_bram_wr_in : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of vcnnbd_conv1l_top_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of vcnnbd_conv1l_top_0_0 : entity is "vcnnbd_conv1l_top_0_0,conv1l_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of vcnnbd_conv1l_top_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of vcnnbd_conv1l_top_0_0 : entity is "conv1l_top,Vivado 2017.2";
end vcnnbd_conv1l_top_0_0;
architecture STRUCTURE of vcnnbd_conv1l_top_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal C : STD_LOGIC_VECTOR ( 8 downto 5 );
signal \^clk\ : STD_LOGIC;
signal conv_waddr_inferred_i_16_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_18_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_19_n_0 : STD_LOGIC;
signal conv_waddr_inferred_i_20_n_0 : STD_LOGIC;
signal \^input_bram_rd_rst\ : STD_LOGIC;
signal \^output_bram_wr_dout\ : STD_LOGIC_VECTOR ( 14 downto 0 );
begin
\^clk\ <= clk;
input_bram_rd_clk <= \^clk\;
input_bram_rd_dout(15) <= \<const0>\;
input_bram_rd_dout(14) <= \<const0>\;
input_bram_rd_dout(13) <= \<const0>\;
input_bram_rd_dout(12) <= \<const0>\;
input_bram_rd_dout(11) <= \<const0>\;
input_bram_rd_dout(10) <= \<const0>\;
input_bram_rd_dout(9) <= \<const0>\;
input_bram_rd_dout(8) <= \<const0>\;
input_bram_rd_dout(7) <= \<const0>\;
input_bram_rd_dout(6) <= \<const0>\;
input_bram_rd_dout(5) <= \<const0>\;
input_bram_rd_dout(4) <= \<const0>\;
input_bram_rd_dout(3) <= \<const0>\;
input_bram_rd_dout(2) <= \<const0>\;
input_bram_rd_dout(1) <= \<const0>\;
input_bram_rd_dout(0) <= \<const0>\;
input_bram_rd_rst <= \^input_bram_rd_rst\;
input_bram_rd_wen <= \<const0>\;
output_bram_wr_clk <= \^clk\;
output_bram_wr_dout(15) <= \<const0>\;
output_bram_wr_dout(14 downto 0) <= \^output_bram_wr_dout\(14 downto 0);
output_bram_wr_en <= \<const1>\;
output_bram_wr_rst <= \^input_bram_rd_rst\;
weight_bram_rd_clk <= \^clk\;
weight_bram_rd_dout(15) <= \<const0>\;
weight_bram_rd_dout(14) <= \<const0>\;
weight_bram_rd_dout(13) <= \<const0>\;
weight_bram_rd_dout(12) <= \<const0>\;
weight_bram_rd_dout(11) <= \<const0>\;
weight_bram_rd_dout(10) <= \<const0>\;
weight_bram_rd_dout(9) <= \<const0>\;
weight_bram_rd_dout(8) <= \<const0>\;
weight_bram_rd_dout(7) <= \<const0>\;
weight_bram_rd_dout(6) <= \<const0>\;
weight_bram_rd_dout(5) <= \<const0>\;
weight_bram_rd_dout(4) <= \<const0>\;
weight_bram_rd_dout(3) <= \<const0>\;
weight_bram_rd_dout(2) <= \<const0>\;
weight_bram_rd_dout(1) <= \<const0>\;
weight_bram_rd_dout(0) <= \<const0>\;
weight_bram_rd_rst <= \^input_bram_rd_rst\;
weight_bram_rd_wen <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
conv_waddr_inferred_i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => C(8),
O => conv_waddr_inferred_i_16_n_0
);
conv_waddr_inferred_i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => C(7),
O => conv_waddr_inferred_i_18_n_0
);
conv_waddr_inferred_i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => C(6),
O => conv_waddr_inferred_i_19_n_0
);
conv_waddr_inferred_i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => C(5),
O => conv_waddr_inferred_i_20_n_0
);
inst: entity work.vcnnbd_conv1l_top_0_0_conv1l_top
port map (
AR(0) => \^input_bram_rd_rst\,
S(2) => conv_waddr_inferred_i_18_n_0,
S(1) => conv_waddr_inferred_i_19_n_0,
S(0) => conv_waddr_inferred_i_20_n_0,
ap_done => ap_done,
ap_ready => ap_ready,
ap_start => ap_start,
clk => \^clk\,
\conv_wrows_reg[0]_0\(0) => conv_waddr_inferred_i_16_n_0,
input_bram_rd_adddr(11 downto 0) => input_bram_rd_adddr(11 downto 0),
input_bram_rd_din(15 downto 0) => input_bram_rd_din(15 downto 0),
input_bram_rd_en => input_bram_rd_en,
output_bram_wr_addr(13 downto 0) => output_bram_wr_addr(13 downto 0),
output_bram_wr_dout(14 downto 0) => \^output_bram_wr_dout\(14 downto 0),
output_bram_wr_wen => output_bram_wr_wen,
rstn => rstn,
weight_bram_rd_adddr(8 downto 0) => weight_bram_rd_adddr(8 downto 0),
\weight_bram_rd_adddr_reg[8]_0\(3 downto 0) => C(8 downto 5),
weight_bram_rd_din(15 downto 0) => weight_bram_rd_din(15 downto 0),
weight_bram_rd_en => weight_bram_rd_en
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- filter.vhd
--
-- Copyright (C) 2006 <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Fast 32 channel digital noise filter using a single LUT function for each
-- individual channel. It will filter out all pulses that only appear for half
-- a clock cycle. This way a pulse has to be at least 5-10ns long to be accepted
-- as valid. This is sufficient for sample rates up to 100MHz.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity filter is
port(
la_input : in std_logic_vector (31 downto 0);
la_input180 : in std_logic_vector (31 downto 0);
clock : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end filter;
architecture behavioral of filter is
signal la_input360, la_input180Delay, result : std_logic_vector (31 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
-- determine next result
for i in 31 downto 0 loop
result(i) <= (result(i) or la_input360(i) or la_input(i)) and la_input180Delay(i);
end loop;
-- shift in la_input data
la_input360 <= la_input;
la_input180Delay <= la_input180;
end if;
end process;
output <= result;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity speciescoppyTable1 is
port (clk : in std_logic;
we : in std_logic;
en : in std_logic;
--ssr : in std_logic;
a:in std_logic_vector(31 downto 0);--a1,a2,a3,a4,a5,a6,a7,aa,a1a,a2a,ab,a1b,a2b,ac,a1c,a2c : in std_logic_vector(31 downto 0);
di : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0));
--do1,do2,do3,do4,do5,do6,do7,do8,do1a,do2a,do3a,do1b,do2b,do3b,do1c,do2c,do3c,do1d,do2d,do3d: out std_logic_vector(31 downto 0));
end speciescoppyTable1;
architecture Behavioral of speciescoppyTable1 is
type ram_type is array(0 to BRAM_size) of std_logic_vector(31 downto 0);
signal RAM:ram_type:= (
|
<reponame>mfkiwl/riscv_vhdl-64bit-fault-tolerant
--!
--! Copyright 2020 <NAME>, <EMAIL>
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
entity river_l2serdes is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_l2o : in axi4_l2_out_type;
o_l2i : out axi4_l2_in_type;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type
);
end;
architecture arch_river_l2serdes of river_l2serdes is
-- TODO as generic parameters
constant linew : integer := L1CACHE_LINE_BITS;
constant busw : integer := CFG_SYSBUS_DATA_BITS;
constant lineb : integer := linew / 8;
constant busb : integer := busw / 8;
constant SERDES_BURST_LEN : integer := lineb / busb;
type state_type is (Idle, Read, Write);
type RegistersType is record
state : state_type;
req_len : std_logic_vector(7 downto 0);
b_wait : std_logic;
cacheline : std_logic_vector(linew-1 downto 0);
wstrb : std_logic_vector(lineb-1 downto 0);
rmux : std_logic_vector(SERDES_BURST_LEN-1 downto 0);
end record;
constant R_RESET : RegistersType := (
idle, X"00", '0', (others => '0'), (others => '0'), (others => '0')
);
signal r, rin : RegistersType;
function size2len(size: std_logic_vector)
return std_logic_vector is
variable len: std_logic_vector(7 downto 0);
begin
case size(2 downto 0) is
when "100" => len := X"01";
when "101" => len := X"03";
when "110" => len := X"07";
when "111" => len := X"0F";
when others => len := X"00";
end case;
return len;
end function size2len;
begin
comb : process(i_nrst, i_l2o, i_msti, r)
variable v : RegistersType;
variable v_req_mem_ready : std_logic;
variable vb_line_o : std_logic_vector(linew-1 downto 0);
variable v_r_valid : std_logic;
variable v_w_valid : std_logic;
variable v_w_last : std_logic;
variable v_w_ready : std_logic;
variable vb_len : std_logic_vector(7 downto 0);
variable vb_aw_id : std_logic_vector(CFG_SYSBUS_ID_BITS-1 downto 0);
variable vb_ar_id : std_logic_vector(CFG_SYSBUS_ID_BITS-1 downto 0);
begin
v := r;
v_req_mem_ready := '0';
v_r_valid := '0';
v_w_valid := '0';
v_w_last := '0';
v_w_ready := '0';
vb_len := (others => '0');
vb_aw_id := (others => '0');
vb_ar_id := (others => '0');
vb_aw_id(CFG_CPU_ID_BITS-1 downto 0) := i_l2o.aw_id;
vb_ar_id(CFG_CPU_ID_BITS-1 downto 0) := i_l2o.ar_id;
vb_line_o := r.cacheline;
for i in 0 to SERDES_BURST_LEN-1 loop
if r.rmux(i) = '1' then
vb_line_o((i+1)*busw-1 downto i*busw) := i_msti.r_data;
end if;
end loop;
if i_l2o.b_ready = '1' then
v.b_wait := '0';
end if;
case r.state is
when Idle =>
v_req_mem_ready := '1';
when Read =>
if i_msti.r_valid = '1' then
v.cacheline := vb_line_o;
v.rmux := r.rmux(SERDES_BURST_LEN-2 downto 0) & '0';
if r.req_len = X"00" then
v_r_valid := '1';
v_req_mem_ready := '1';
else
v.req_len := r.req_len - 1;
end if;
end if;
when Write =>
v_w_valid := '1';
if r.req_len = X"00" then
v_w_last := '1';
end if;
if i_msti.w_ready = '1' then
v.cacheline(linew-1 downto linew-busw) := (others => '0');
v.cacheline(linew-busw-1 downto 0) := r.cacheline(linew-1 downto busw);
v.wstrb(lineb-1 downto lineb-busb) := (others => '0');
v.wstrb(lineb-busb-1 downto 0) := r.wstrb(lineb-1 downto busb);
if r.req_len = X"00" then
v_w_ready := '1';
v.b_wait := '1';
v_req_mem_ready := '1';
else
v.req_len := r.req_len - 1;
end if;
end if;
when others =>
end case;
if v_req_mem_ready = '1' then
if (i_l2o.ar_valid and i_msti.ar_ready) = '1' then
v.state := Read;
v.rmux := conv_std_logic_vector(1, SERDES_BURST_LEN);
vb_len := size2len(i_l2o.ar_bits.size);
elsif (i_l2o.aw_valid and i_msti.aw_ready) = '1' then
v.cacheline := i_l2o.w_data; -- Undocumented River (Axi-lite) feature
v.wstrb := i_l2o.w_strb;
v.state := Write;
vb_len := size2len(i_l2o.aw_bits.size);
else
v.state := Idle;
end if;
v.req_len := vb_len;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
o_msto.aw_valid <= i_l2o.aw_valid;
o_msto.aw_bits.addr <= i_l2o.aw_bits.addr;
o_msto.aw_bits.len <= vb_len; -- burst len = len[7:0] + 1
o_msto.aw_bits.size <= "011"; -- 0=1B; 1=2B; 2=4B; 3=8B; ...
o_msto.aw_bits.burst <= "01"; -- 00=FIXED; 01=INCR; 10=WRAP; 11=reserved
o_msto.aw_bits.lock <= i_l2o.aw_bits.lock;
o_msto.aw_bits.cache <= i_l2o.aw_bits.cache;
o_msto.aw_bits.prot <= i_l2o.aw_bits.prot;
o_msto.aw_bits.qos <= i_l2o.aw_bits.qos;
o_msto.aw_bits.region <= i_l2o.aw_bits.region;
o_msto.aw_id <= vb_aw_id;
o_msto.aw_user <= i_l2o.aw_user;
o_msto.w_valid <= v_w_valid;
o_msto.w_last <= v_w_last;
o_msto.w_data <= r.cacheline(busw-1 downto 0);
o_msto.w_strb <= r.wstrb(busb-1 downto 0);
o_msto.w_user <= i_l2o.w_user;
o_msto.b_ready <= i_l2o.b_ready;
o_msto.ar_valid <= i_l2o.ar_valid;
o_msto.ar_bits.addr <= i_l2o.ar_bits.addr;
o_msto.ar_bits.len <= vb_len; -- burst len = len[7:0] + 1
o_msto.ar_bits.size <= "011"; -- 0=1B; 1=2B; 2=4B; 3=8B; ...
o_msto.ar_bits.burst <= "01"; -- 00=FIXED; 01=INCR; 10=WRAP; 11=reserved
o_msto.ar_bits.lock <= i_l2o.ar_bits.lock;
o_msto.ar_bits.cache <= i_l2o.ar_bits.cache;
o_msto.ar_bits.prot <= i_l2o.ar_bits.prot;
o_msto.ar_bits.qos <= i_l2o.ar_bits.qos;
o_msto.ar_bits.region <= i_l2o.ar_bits.region;
o_msto.ar_id <= vb_ar_id;
o_msto.ar_user <= i_l2o.ar_user;
o_msto.r_ready <= i_l2o.r_ready;
o_l2i.aw_ready <= i_msti.aw_ready;
o_l2i.w_ready <= v_w_ready;
o_l2i.b_valid <= i_msti.b_valid and r.b_wait;
o_l2i.b_resp <= i_msti.b_resp;
o_l2i.b_id <= i_msti.b_id(CFG_CPU_ID_BITS-1 downto 0);
o_l2i.b_user <= i_msti.b_user;
o_l2i.ar_ready <= i_msti.ar_ready;
o_l2i.r_valid <= v_r_valid;
o_l2i.r_resp <= i_msti.r_resp;
o_l2i.r_data <= vb_line_o;
o_l2i.r_last <= v_r_valid;
o_l2i.r_id <= i_msti.r_id(CFG_CPU_ID_BITS-1 downto 0);
o_l2i.r_user <= i_msti.r_user;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
<reponame>slow-J/TCD
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/12/2018 11:19:54 AM
-- Design Name:
-- Module Name: logic_circuit_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logic_circuit_2 is
Port (
B : in STD_LOGIC_VECTOR(15 downto 0);
S_in : in STD_LOGIC_VECTOR(1 downto 0);
Y_out : out STD_LOGIC_VECTOR(15 downto 0)
);
end logic_circuit_2;
architecture Behavioral of logic_circuit_2 is
--mux 2-1 component
Component mux_2_1
Port(
I0, S0, S1 : in STD_LOGIC;
Z : out STD_LOGIC
);
End Component;
begin
mux00: mux_2_1 PORT MAP(
I0 => B(0),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(0)
);
mux01: mux_2_1 PORT MAP(
I0 => B(1),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(1)
);
mux02: mux_2_1 PORT MAP(
I0 => B(2),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(2)
);
mux03: mux_2_1 PORT MAP(
I0 => B(3),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(3)
);
mux04: mux_2_1 PORT MAP(
I0 => B(4),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(4)
);
mux05: mux_2_1 PORT MAP(
I0 => B(5),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(5)
);
mux06: mux_2_1 PORT MAP(
I0 => B(6),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(6)
);
mux07: mux_2_1 PORT MAP(
I0 => B(7),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(7)
);
mux08: mux_2_1 PORT MAP(
I0 => B(8),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(8)
);
mux09: mux_2_1 PORT MAP(
I0 => B(9),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(9)
);
mux10: mux_2_1 PORT MAP(
I0 => B(10),
S0 => S_in(0),
S1 => S_in(1),
Z => Y_out(10)
);
end Behavioral;
|
<filename>hardware/src_tb/LWC_TB.vhd
--===============================================================================================--
--! @file LWC_TB.vhd
--! @brief NIST Lightweight Cryptography Testbench
--! @project GMU LWC Package
--! @author Ekawat (ice) Homsirikamol
--! @author <NAME>
--! @copyright Copyright (c) 2015, 2020, 2021, 2022 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @version 1.2.0
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! unrestricted)
--===============================================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.NIST_LWAPI_pkg.all;
use work.LWC_pkg.all;
entity LWC_TB IS
generic(
G_MAX_FAILURES : integer := 0; --! Maximum number of failures before stopping the simulation
G_TEST_MODE : integer := 0; --! 0: normal, 1: stall both sdi/pdi_valid and do_ready, 2: stall sdi/pdi_valid, 3: stall do_ready, 4: Timing (cycle) measurement
G_TEST_IPSTALL : integer := 3; --! Number of cycles to stall pdi_valid
G_TEST_ISSTALL : integer := 3; --! Number of cycles to stall sdi_valid
G_TEST_OSTALL : integer := 3; --! Number of cycles to stall do_ready
G_PERIOD_PS : integer := 10_000; --! Simulation clock period in picoseconds
G_FNAME_PDI : string := "../KAT/v1/pdi.txt"; --! Path to the input file containing cryptotvgen PDI testvector data
G_FNAME_SDI : string := "../KAT/v1/sdi.txt"; --! Path to the input file containing cryptotvgen SDI testvector data
G_FNAME_RDI : string := "../KAT/v1/rdi.txt"; --! Path to the input file containing random data
G_FNAME_DO : string := "../KAT/v1/do.txt"; --! Path to the input file containing cryptotvgen DO testvector data
G_FNAME_LOG : string := "log.txt"; --! Path to the generated log file
G_FNAME_TIMING : string := "timing.txt"; --! Path to the generated timing measurements (when G_TEST_MODE=4)
G_FNAME_FAILED_TVS : string := "failed_testvectors.txt"; --! Path to the generated log of failed testvector words
G_FNAME_RESULT : string := "result.txt"; --! Path to the generated result file containing 0 or 1 -- REDUNDANT / NOT USED
G_PRERESET_WAIT_NS : integer := 0; --! Time (in nanosecods) to wait before reseting UUT. Xilinx GSR takes 100ns, required for post-synth simulation
G_INPUT_DELAY_NS : integer := 0 --! Input delay
);
end LWC_TB;
architecture TB of LWC_TB is
--================================================== Constants ==================================================--
constant W_S : positive := W * PDI_SHARES;
constant SW_S : positive := SW * SDI_SHARES;
constant input_delay : TIME := G_INPUT_DELAY_NS * ns;
constant clk_period : TIME := G_PERIOD_PS * ps;
constant TB_HEAD : string(1 to 6) := "# TB :";
-- can be placed in the middle of a file
constant EOF_HEAD : string(1 to 6) := "###EOF";
constant INS_HEAD : string(1 to 6) := "INS = ";
constant HDR_HEAD : string(1 to 6) := "HDR = ";
constant DAT_HEAD : string(1 to 6) := "DAT = ";
constant STT_HEAD : string(1 to 6) := "STT = ";
constant TESTMODE_TIMING : integer := 4;
--=================================================== Signals ===================================================--
--! stop clock generation
signal stop_clock : boolean := False;
--! initial reset of UUT is complete
signal reset_done : boolean := False;
--=================================================== Wirings ===================================================--
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--! PDI
signal pdi_data : std_logic_vector(W_S - 1 downto 0) := (others => '0');
signal pdi_data_delayed : std_logic_vector(W_S - 1 downto 0) := (others => '0');
signal pdi_valid : std_logic := '0';
signal pdi_valid_delayed : std_logic := '0';
signal pdi_ready : std_logic;
--! SDI
signal sdi_data : std_logic_vector(SW_S - 1 downto 0) := (others => '0');
signal sdi_data_delayed : std_logic_vector(SW_S - 1 downto 0) := (others => '0');
signal sdi_valid : std_logic := '0';
signal sdi_valid_delayed : std_logic := '0';
signal sdi_ready : std_logic;
--! DO
signal do_data : std_logic_vector(W_S - 1 downto 0);
signal do_valid : std_logic;
signal do_last : std_logic;
signal do_ready : std_logic := '0';
signal do_ready_delayed : std_logic := '0';
-- Used only for protected implementations:
-- RDI
signal rdi_data : std_logic_vector(RW - 1 downto 0) := (others => '0');
signal rdi_data_delayed : std_logic_vector(RW - 1 downto 0) := (others => '0');
signal rdi_valid : std_logic := '0';
signal rdi_valid_delayed : std_logic := '0';
signal rdi_ready : std_logic;
-- unshared version of DO
signal do_sum : std_logic_vector(W - 1 downto 0);
-- Counters
signal pdi_operation_count : integer := 0;
signal cycle_counter : natural := 0;
signal num_rand_vectors : natural := 0;
--
signal start_cycle : natural;
signal timing_started : boolean := False;
signal timing_stopped : boolean := False;
--================================================== I/O files ==================================================--
-- cryptotvgen KAT files
file pdi_file : TEXT open READ_MODE is G_FNAME_PDI; -- always required
file sdi_file : TEXT;
file do_file : TEXT open READ_MODE is G_FNAME_DO; -- always required
file rdi_file : TEXT;
-- output files
file log_file : TEXT open write_mode is G_FNAME_LOG;
file timing_file : TEXT;
file result_file : TEXT open write_mode is G_FNAME_RESULT;
file failures_file : TEXT open write_mode is G_FNAME_FAILED_TVS;
--================================================== functions ==================================================--
-- compare received word against expected word
-- returns true if they match or if the unmatched bit was a don't-care
function word_pass(actual, expected : std_logic_vector) return boolean is
begin
for i in expected'range loop
if actual(i) /= expected(i) and expected(i) /= 'X' and expected(i) /= '-' then
return False;
end if;
end loop;
return True;
end function;
-- sum up all shares. Returns do_data if num_shares=1)
function xor_shares(do_data : std_logic_vector; num_shares : positive) return std_logic_vector is
constant share_width : natural := do_data'length / num_shares;
variable ret : std_logic_vector(share_width - 1 downto 0) := do_data(share_width - 1 downto 0);
begin
for i in 1 to num_shares - 1 loop
ret := ret xor do_data((i + 1) * share_width - 1 downto i * share_width);
end loop;
return ret;
end function;
-- TODO re-implement random stalls
impure function get_stalls(max_stalls : integer) return integer is
begin
return max_stalls;
end function;
begin
--===========================================================================================--
-- generate clock
clockProProc : process
begin
if not stop_clock then
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
else
wait;
end if;
end process;
-- generate reset
resetProc : process
begin
report LF & " -- Testvectors: " & G_FNAME_PDI & " " & G_FNAME_SDI & " " & G_FNAME_DO & LF &
" -- Clock Period: " & integer'image(G_PERIOD_PS) & " ps" & LF &
" -- Test Mode: " & integer'image(G_TEST_MODE) & LF &
" -- Max Failures: " & integer'image(G_MAX_FAILURES) & LF & CR severity note;
wait for G_PRERESET_WAIT_NS * ns;
if ASYNC_RSTN then
rst <= '0';
wait for 2 * clk_period;
rst <= '1';
else
rst <= '1';
wait for 2 * clk_period + input_delay;
rst <= '0';
end if;
wait until rising_edge(clk);
wait for clk_period; -- optional
reset_done <= True;
wait;
end process;
cycleCountProc : process(clk)
begin
if reset_done and rising_edge(clk) then
cycle_counter <= cycle_counter + 1;
end if;
end process;
--===========================================================================================--
-- LWC is instantiated as a component for mixed languages simulation
uut : LWC_SCA
port map(
clk => clk,
rst => rst,
pdi_data => pdi_data_delayed,
pdi_valid => pdi_valid_delayed,
pdi_ready => pdi_ready,
sdi_data => sdi_data_delayed,
sdi_valid => sdi_valid_delayed,
sdi_ready => sdi_ready,
do_data => do_data,
do_last => do_last,
do_valid => do_valid,
do_ready => do_ready_delayed,
rdi_data => rdi_data_delayed,
rdi_valid => rdi_valid_delayed,
rdi_ready => rdi_ready
);
--===========================================================================================--
pdi_data_delayed <= transport pdi_data after input_delay;
pdi_valid_delayed <= transport pdi_valid after input_delay;
sdi_data_delayed <= transport sdi_data after input_delay;
sdi_valid_delayed <= transport sdi_valid after input_delay;
do_ready_delayed <= transport do_ready after input_delay;
do_sum <= xor_shares(do_data, PDI_SHARES);
GEN_RDI : if RW > 0 generate
begin
rdi_data_delayed <= transport rdi_data after input_delay;
rdi_valid_delayed <= transport rdi_valid after input_delay;
rdi_proc : process
variable rdi_line : line;
variable rdi_vec : std_logic_vector(RW - 1 downto 0);
variable read_ok : boolean;
begin
report LF & "RW=" & integer'image(RW);
wait until reset_done and rising_edge(clk);
if G_FNAME_RDI'length < 1 then
rdi_data <= (others => '1');
rdi_valid <= '1';
else
file_open(rdi_file, G_FNAME_RDI, READ_MODE);
loop
loop
if endfile(rdi_file) then
assert num_rand_vectors > 0 report "RDI file is empty!" severity failure;
-- report "Reached end of " & G_FNAME_RDI & ", reading from the begining.";
-- re-read from the biginging
file_close(rdi_file);
file_open(rdi_file, G_FNAME_RDI, READ_MODE);
end if;
readline(rdi_file, rdi_line);
if rdi_line'length > 0 then
exit;
end if;
end loop;
if rdi_line'length * 4 < RW then
report "Error: RDI line is shorter than RW " severity failure;
exit; -- exit the loop
end if;
lwc_hread(rdi_line, rdi_vec, read_ok);
if not read_ok then
report "Error while reading " & G_FNAME_RDI severity failure;
exit; -- exit the loop
end if;
rdi_data <= rdi_vec;
rdi_valid <= '1';
wait until rising_edge(clk) and rdi_ready = '1' and rdi_valid_delayed = '1';
num_rand_vectors <= num_rand_vectors + 1;
rdi_valid <= '0';
end loop;
file_close(rdi_file);
end if;
wait; -- until simulation ends
end process;
end generate;
--===========================================================================================--
--====================================== PDI Stimulus =======================================--
tb_read_pdi : process
variable line_data : LINE;
variable word_block : std_logic_vector(W_S - 1 downto 0) := (others => '0');
variable read_ok : boolean;
variable line_head : string(1 to 6);
variable stall_cycles : integer;
variable actkey_ins : boolean;
variable hash_ins : boolean;
-- instruction other than actkey or hash was already sent
variable op_sent : boolean := False;
begin
-- wait for the clock edge after reset is complete
wait until reset_done;
wait until rising_edge(clk);
--
while not endfile(pdi_file) loop
readline(pdi_file, line_data);
read(line_data, line_head, read_ok); --! read line header
if read_ok and (line_head = INS_HEAD) then
pdi_operation_count <= pdi_operation_count + 1;
end if;
if read_ok and (line_head = INS_HEAD or line_head = HDR_HEAD or line_head = DAT_HEAD) then
loop
lwc_hread(line_data, word_block, read_ok);
if not read_ok then
exit;
end if;
actkey_ins := (line_head = INS_HEAD) and (word_block(W - 1 downto W - 4) = INST_ACTKEY);
hash_ins := (line_head = INS_HEAD) and (word_block(W - 1 downto W - 4) = INST_HASH);
-- stalls
if G_TEST_MODE = 1 or G_TEST_MODE = 2 then
stall_cycles := get_stalls(G_TEST_IPSTALL);
if stall_cycles > 0 then
pdi_valid <= '0';
wait for stall_cycles * clk_period;
wait until rising_edge(clk); -- TODO verify number of generated stall cycles
end if;
elsif G_TEST_MODE = TESTMODE_TIMING and line_head = INS_HEAD and (actkey_ins or hash_ins or op_sent) and timing_started then
if not timing_stopped then
pdi_valid <= '0';
wait until rising_edge(clk) and timing_stopped; -- wait for tb_verify_do process to complete timed operation
end if;
timing_started <= False; -- Ack receiving timing_stopped = '1' to tb_verify_do process
end if;
pdi_valid <= '1';
pdi_data <= word_block;
wait until rising_edge(clk) and pdi_ready = '1';
-- NOTE: should never stall here
if G_TEST_MODE = TESTMODE_TIMING and line_head = INS_HEAD then
op_sent := not actkey_ins and not hash_ins;
if not timing_started then
start_cycle <= cycle_counter;
timing_started <= True;
wait for 0 ns; -- yield to update timing_started signal as there could be no wait before next read
end if;
end if;
end loop;
end if;
end loop;
--
pdi_valid <= '0';
if timing_started and not timing_stopped then
wait until timing_stopped;
timing_started <= False;
end if;
wait; -- until simulation ends
end process;
--===========================================================================================--
--====================================== SDI Stimulus =======================================--
tb_read_sdi : process
variable line_data : LINE;
variable word_block : std_logic_vector(SW_S - 1 downto 0);
variable read_ok : boolean;
variable line_head : string(1 to 6);
variable stall_cycles : integer;
begin
wait until reset_done;
wait until rising_edge(clk);
if G_FNAME_SDI'length > 0 then -- set G_FNAME_SDI = "" if sdi is not used (i.e., hash)
file_open(sdi_file, G_FNAME_SDI, READ_MODE);
while not endfile(sdi_file) loop
readline(sdi_file, line_data);
read(line_data, line_head, read_ok);
if read_ok and (line_head = INS_HEAD or line_head = HDR_HEAD or line_head = DAT_HEAD) then
loop
lwc_hread(line_data, word_block, read_ok);
if not read_ok then
exit;
end if;
if G_TEST_MODE = 1 or G_TEST_MODE = 2 then
stall_cycles := get_stalls(G_TEST_ISSTALL);
if stall_cycles > 0 then
sdi_valid <= '0';
wait for stall_cycles * clk_period;
end if;
elsif G_TEST_MODE = TESTMODE_TIMING and not timing_started then
sdi_valid <= '0';
wait until timing_started;
end if;
sdi_valid <= '1';
sdi_data <= word_block;
wait until rising_edge(clk) and sdi_ready = '1';
end loop;
end if;
end loop;
end if;
sdi_valid <= '0';
wait; -- until simulation ends
end process;
--===========================================================================================--
--=================================== DO Verification =======================================--
tb_verify_do : process
variable line_no : integer := 0;
variable line_data : LINE;
variable logMsg : LINE;
variable failMsg : LINE;
variable tb_block : std_logic_vector(20 - 1 downto 0);
variable word_block : std_logic_vector(W - 1 downto 0);
variable read_ok : boolean;
variable preamble : string(1 to 6);
variable word_count : integer := 1;
variable force_exit : boolean := False;
variable failed : boolean := False;
variable msgid : integer;
variable keyid : integer;
variable opcode : std_logic_vector(3 downto 0);
variable num_fails : integer := 0;
variable testcase : integer := 0;
variable stall_cycles : integer;
variable cycles : integer;
variable end_cycle : natural;
variable end_time : TIME;
begin
wait until reset_done;
wait until rising_edge(clk);
if G_TEST_MODE = TESTMODE_TIMING then
file_open(timing_file, G_FNAME_TIMING, WRITE_MODE);
end if;
while not endfile(do_file) and not force_exit loop
loop
if endfile(do_file) then
report "Reached the end of " & G_FNAME_DO;
read_ok := False;
exit;
end if;
readline(do_file, line_data);
line_no := line_no + 1;
if line_data'length > 0 then
read(line_data, preamble, read_ok);
if read_ok then
exit;
end if;
end if;
end loop;
if not read_ok then
exit;
end if;
if preamble = EOF_HEAD then
report "Reached EOF marker in " & G_FNAME_DO severity warning;
force_exit := True;
exit;
elsif preamble = STT_HEAD or preamble = HDR_HEAD or preamble = DAT_HEAD then --valid do.txt lines are: header, data, and status
loop -- processing single line
lwc_hread(line_data, word_block, read_ok); -- read the rest of the line to word_block
if not read_ok then
exit;
end if;
-- stalls
if G_TEST_MODE = 1 or G_TEST_MODE = 3 then
stall_cycles := get_stalls(G_TEST_OSTALL);
if stall_cycles > 0 then
do_ready <= '0';
wait for stall_cycles * clk_period;
-- wait until rising_edge(clk);
end if;
elsif G_TEST_MODE = TESTMODE_TIMING and not timing_started then
-- stall until timing has started from PDI
do_ready <= '0';
timing_stopped <= False;
wait until timing_started;
end if;
do_ready <= '1';
wait until rising_edge(clk) and do_valid = '1';
assert preamble /= STT_HEAD or do_last = '1' report "Status word received, but do_last was not '1'" severity error;
if not word_pass(do_sum, word_block) then
failed := True;
write(logMsg, string'("[Log] Msg ID #") & integer'image(msgid) & string'(" fails at line #") & integer'image(line_no) & string'(" word #") & integer'image(word_count));
writeline(log_file, logMsg);
write(logMsg, string'("[Log] Expected: ") & lwc_to_hstring(word_block) & string'(" Received: ") & lwc_to_hstring(do_sum));
writeline(log_file, logMsg);
report " --- MsgID #" & integer'image(testcase)
& " Data line #" & integer'image(line_no)
& " Word #" & integer'image(word_count)
& " at " & TIME'image(now) & " FAILS ---"
severity error;
report "Expected: " & lwc_to_hstring(word_block)
& " Actual: " & lwc_to_hstring(do_sum) severity error;
write(result_file, string'("fail"));
num_fails := num_fails + 1;
write(failMsg, string'("Failure #") & integer'image(num_fails) & " MsgID: " & integer'image(testcase)); -- & " Operation: ");
write(failMsg, string'(" Line: ") & integer'image(line_no) & " Word: " & integer'image(word_count));
write(failMsg, " Expected: " & lwc_to_hstring(word_block) & " Received: " & lwc_to_hstring(do_data));
if PDI_SHARES > 1 then
write(failMsg, " Received sum: " & lwc_to_hstring(do_sum));
end if;
writeline(failures_file, failMsg);
if num_fails >= G_MAX_FAILURES then
force_exit := True;
exit;
end if;
else
write(logMsg, string'("[Log] Expected: ") & lwc_to_hstring(word_block) & string'(" Received: ") & lwc_to_hstring(do_data) & string'(" Matched!"));
writeline(log_file, logMsg);
end if;
word_count := word_count + 1;
if preamble = STT_HEAD then -- last line of this testcase
if G_TEST_MODE = TESTMODE_TIMING then
assert timing_started;
cycles := cycle_counter - start_cycle;
timing_stopped <= True;
do_ready <= '0'; -- needed as we wait for de-assertion of timing_started
wait until not timing_started;
write(logMsg, integer'image(msgid) & ", " & integer'image(cycles));
writeline(timing_file, logMsg);
report "[Timing] MsgId: " & integer'image(msgid) & ", cycles: " & integer'image(cycles) severity note;
end if;
end if;
end loop; -- end of this line
elsif preamble = TB_HEAD then
testcase := testcase + 1;
lwc_hread(line_data, tb_block, read_ok);
if not read_ok then
exit;
end if;
opcode := tb_block(19 downto 16);
msgid := to_integer(to_01(unsigned(tb_block(7 downto 0))));
write(logMsg, "Testcase #" & integer'image(testcase) & " MsgID:" & integer'image(testcase) & " Op:");
if (opcode = INST_HASH) then
write(logMsg, string'("HASH"));
else
if opcode = INST_ENC then
write(logMsg, string'("ENC"));
elsif opcode = INST_DEC then
write(logMsg, string'("DEC"));
else
write(logMsg, string'("UNKNOWN opcode=") & lwc_to_hstring(opcode));
end if;
keyid := to_integer(to_01(unsigned(tb_block(15 downto 8))));
write(logMsg, string'(" KeyID:") & integer'image(keyid));
end if;
report logMsg.all severity note;
writeline(log_file, logMsg);
end if;
end loop;
--
end_cycle := cycle_counter;
end_time := now;
do_ready <= '0';
wait until rising_edge(clk);
if RW > 0 then
report "Number of consumed random words: " & integer'image(num_rand_vectors) severity note;
end if;
--
if failed then
write(logMsg, string'("[FAIL] "));
else
write(logMsg, string'("[PASS] "));
end if;
file_close(do_file);
write(logMsg, string'("Simulation completed in ") & integer'image(end_cycle) & " cycles.");
-- write(logMsg, string'(" Simulation time: ") & time'image(end_time));
writeline(log_file, logMsg);
--
if G_TEST_MODE = TESTMODE_TIMING then
file_close(timing_file);
end if;
file_close(log_file);
--
if failed then
write(result_file, "1");
report LF & LF & logMsg.all & LF severity failure;
else
write(result_file, "0");
report LF & LF & logMsg.all & LF severity note;
end if;
file_close(result_file);
--
stop_clock <= True;
-- Do not use a 'failure' to end the simulation.
-- Simulators usually exit when there are no event scheduled.
wait;
end process;
end architecture;
|
<reponame>EddieDhakal/Altera-DE2-Lab-solutions<filename>lab1/part1/part1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity part1 is
port(
sw : in std_logic_vector(17 downto 0);
ledr : out std_logic_vector(17 downto 0));
end part1;
architecture arc of part1 is
begin
ledr <= sw;
end arc;
|
<reponame>gustavohfc/RISC-V-Cryptographic-Coprocessor<gh_stars>1-10
library vunit_lib;
context vunit_lib.vunit_context;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.coprocessor_constants.all;
-- 24 bits message ("abc")
entity unit_sha1_test_2_tb IS
generic(
runner_cfg : string
);
end unit_sha1_test_2_tb;
architecture unit_sha1_test_2_tb_arch OF unit_sha1_test_2_tb IS
signal clk : std_logic := '0';
signal start_new_hash : std_logic := '0';
signal write_data_in : std_logic := '0';
signal data_in : unsigned(31 downto 0) := (others => '0');
signal data_in_word_position : unsigned(3 downto 0) := (others => '0');
signal calculate_next_block : std_logic := '0';
signal is_last_block : std_logic := '0';
signal last_block_size : unsigned(9 downto 0) := (others => '0');
signal is_waiting_next_block : std_logic := '0';
signal is_busy : std_logic := '0';
signal is_complete : std_logic := '0';
signal error : sha1_error_type;
signal H0_out : unsigned(31 downto 0) := (others => '0');
signal H1_out : unsigned(31 downto 0) := (others => '0');
signal H2_out : unsigned(31 downto 0) := (others => '0');
signal H3_out : unsigned(31 downto 0) := (others => '0');
signal H4_out : unsigned(31 downto 0) := (others => '0');
begin
sha1 : entity work.sha1
port map(
clk => clk,
start_new_hash => start_new_hash,
write_data_in => write_data_in,
data_in => data_in,
data_in_word_position => data_in_word_position,
calculate_next_block => calculate_next_block,
is_last_block => is_last_block,
last_block_size => last_block_size,
is_waiting_next_block => is_waiting_next_block,
is_busy => is_busy,
is_complete => is_complete,
error => error,
H0_out => H0_out,
H1_out => H1_out,
H2_out => H2_out,
H3_out => H3_out,
H4_out => H4_out
);
clk <= not clk after 10 ps;
main : process
alias A is <<signal sha1.A : unsigned(31 downto 0)>>;
alias B is <<signal sha1.B : unsigned(31 downto 0)>>;
alias C is <<signal sha1.C : unsigned(31 downto 0)>>;
alias D is <<signal sha1.D : unsigned(31 downto 0)>>;
alias E is <<signal sha1.E : unsigned(31 downto 0)>>;
begin
test_runner_setup(runner, runner_cfg);
-- Start new hash
start_new_hash <= '1';
wait until rising_edge(clk);
start_new_hash <= '0';
-- Write the 24 bits message ("abc")
write_data_in <= '1';
data_in <= x"61626300";
data_in_word_position <= x"0";
wait until rising_edge(clk);
write_data_in <= '0';
-- Start calculation
calculate_next_block <= '1';
is_last_block <= '1';
last_block_size <= to_unsigned(24, 10);
wait until rising_edge(clk);
calculate_next_block <= '0';
is_last_block <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk); -- Wait padding step
wait until rising_edge(clk); -- Wait the pre calculation step
-------------------------------------------- Round 1 --------------------------------------------
-- Step 0
wait until rising_edge(clk);
check(A = x"0116fc33");
check(B = x"67452301");
check(C = x"7bf36ae2");
check(D = x"98badcfe");
check(E = x"10325476");
-- Step 1
wait until rising_edge(clk);
check(A = x"8990536d");
check(B = x"0116fc33");
check(C = x"59d148c0");
check(D = x"7bf36ae2");
check(E = x"98badcfe");
-- Step 2
wait until rising_edge(clk);
check(A = x"a1390f08");
check(B = x"8990536d");
check(C = x"c045bf0c");
check(D = x"59d148c0");
check(E = x"7bf36ae2");
-- Step 3
wait until rising_edge(clk);
check(A = x"cdd8e11b");
check(B = x"a1390f08");
check(C = x"626414db");
check(D = x"c045bf0c");
check(E = x"59d148c0");
-- Step 4
wait until rising_edge(clk);
check(A = x"cfd499de");
check(B = x"cdd8e11b");
check(C = x"284e43c2");
check(D = x"626414db");
check(E = x"c045bf0c");
-- Step 5
wait until rising_edge(clk);
check(A = x"3fc7ca40");
check(B = x"cfd499de");
check(C = x"f3763846");
check(D = x"284e43c2");
check(E = x"626414db");
-- Step 6
wait until rising_edge(clk);
check(A = x"993e30c1");
check(B = x"3fc7ca40");
check(C = x"b3f52677");
check(D = x"f3763846");
check(E = x"284e43c2");
-- Step 7
wait until rising_edge(clk);
check(A = x"9e8c07d4");
check(B = x"993e30c1");
check(C = x"0ff1f290");
check(D = x"b3f52677");
check(E = x"f3763846");
-- Step 8
wait until rising_edge(clk);
check(A = x"4b6ae328");
check(B = x"9e8c07d4");
check(C = x"664f8c30");
check(D = x"0ff1f290");
check(E = x"b3f52677");
-- Step 9
wait until rising_edge(clk);
check(A = x"8351f929");
check(B = x"4b6ae328");
check(C = x"27a301f5");
check(D = x"664f8c30");
check(E = x"0ff1f290");
-- Step 10
wait until rising_edge(clk);
check(A = x"fbda9e89");
check(B = x"8351f929");
check(C = x"12dab8ca");
check(D = x"27a301f5");
check(E = x"664f8c30");
-- Step 11
wait until rising_edge(clk);
check(A = x"63188fe4");
check(B = x"fbda9e89");
check(C = x"60d47e4a");
check(D = x"12dab8ca");
check(E = x"27a301f5");
-- Step 12
wait until rising_edge(clk);
check(A = x"4607b664");
check(B = x"63188fe4");
check(C = x"7ef6a7a2");
check(D = x"60d47e4a");
check(E = x"12dab8ca");
-- Step 13
wait until rising_edge(clk);
check(A = x"9128f695");
check(B = x"4607b664");
check(C = x"18c623f9");
check(D = x"7ef6a7a2");
check(E = x"60d47e4a");
-- Step 14
wait until rising_edge(clk);
check(A = x"196bee77");
check(B = x"9128f695");
check(C = x"1181ed99");
check(D = x"18c623f9");
check(E = x"7ef6a7a2");
-- Step 15
wait until rising_edge(clk);
check(A = x"20bdd62f");
check(B = x"196bee77");
check(C = x"644a3da5");
check(D = x"1181ed99");
check(E = x"18c623f9");
-- Step 16
wait until rising_edge(clk);
check(A = x"4e925823");
check(B = x"20bdd62f");
check(C = x"c65afb9d");
check(D = x"644a3da5");
check(E = x"1181ed99");
-- Step 17
wait until rising_edge(clk);
check(A = x"82aa6728");
check(B = x"4e925823");
check(C = x"c82f758b");
check(D = x"c65afb9d");
check(E = x"644a3da5");
-- Step 18
wait until rising_edge(clk);
check(A = x"dc64901d");
check(B = x"82aa6728");
check(C = x"d3a49608");
check(D = x"c82f758b");
check(E = x"c65afb9d");
-- Step 19
wait until rising_edge(clk);
check(A = x"fd9e1d7d");
check(B = x"dc64901d");
check(C = x"20aa99ca");
check(D = x"d3a49608");
check(E = x"c82f758b");
-- Step 20
wait until rising_edge(clk);
check(A = x"1a37b0ca");
check(B = x"fd9e1d7d");
check(C = x"77192407");
check(D = x"20aa99ca");
check(E = x"d3a49608");
-- Step 21
wait until rising_edge(clk);
check(A = x"33a23bfc");
check(B = x"1a37b0ca");
check(C = x"7f67875f");
check(D = x"77192407");
check(E = x"20aa99ca");
-- Step 22
wait until rising_edge(clk);
check(A = x"21283486");
check(B = x"33a23bfc");
check(C = x"868dec32");
check(D = x"7f67875f");
check(E = x"77192407");
-- Step 23
wait until rising_edge(clk);
check(A = x"d541f12d");
check(B = x"21283486");
check(C = x"0ce88eff");
check(D = x"868dec32");
check(E = x"7f67875f");
-- Step 24
wait until rising_edge(clk);
check(A = x"c7567dc6");
check(B = x"d541f12d");
check(C = x"884a0d21");
check(D = x"0ce88eff");
check(E = x"868dec32");
-- Step 25
wait until rising_edge(clk);
check(A = x"48413ba4");
check(B = x"c7567dc6");
check(C = x"75507c4b");
check(D = x"884a0d21");
check(E = x"0ce88eff");
-- Step 26
wait until rising_edge(clk);
check(A = x"be35fbd5");
check(B = x"48413ba4");
check(C = x"b1d59f71");
check(D = x"75507c4b");
check(E = x"884a0d21");
-- Step 27
wait until rising_edge(clk);
check(A = x"4aa84d97");
check(B = x"be35fbd5");
check(C = x"12104ee9");
check(D = x"b1d59f71");
check(E = x"75507c4b");
-- Step 28
wait until rising_edge(clk);
check(A = x"8370b52e");
check(B = x"4aa84d97");
check(C = x"6f8d7ef5");
check(D = x"12104ee9");
check(E = x"b1d59f71");
-- Step 29
wait until rising_edge(clk);
check(A = x"c5fbaf5d");
check(B = x"8370b52e");
check(C = x"d2aa1365");
check(D = x"6f8d7ef5");
check(E = x"12104ee9");
-- Step 30
wait until rising_edge(clk);
check(A = x"1267b407");
check(B = x"c5fbaf5d");
check(C = x"a0dc2d4b");
check(D = x"d2aa1365");
check(E = x"6f8d7ef5");
-- Step 31
wait until rising_edge(clk);
check(A = x"3b845d33");
check(B = x"1267b407");
check(C = x"717eebd7");
check(D = x"a0dc2d4b");
check(E = x"d2aa1365");
-- Step 32
wait until rising_edge(clk);
check(A = x"046faa0a");
check(B = x"3b845d33");
check(C = x"c499ed01");
check(D = x"717eebd7");
check(E = x"a0dc2d4b");
-- Step 33
wait until rising_edge(clk);
check(A = x"2c0ebc11");
check(B = x"046faa0a");
check(C = x"cee1174c");
check(D = x"c499ed01");
check(E = x"717eebd7");
-- Step 34
wait until rising_edge(clk);
check(A = x"21796ad4");
check(B = x"2c0ebc11");
check(C = x"811bea82");
check(D = x"cee1174c");
check(E = x"c499ed01");
-- Step 35
wait until rising_edge(clk);
check(A = x"dcbbb0cb");
check(B = x"21796ad4");
check(C = x"4b03af04");
check(D = x"811bea82");
check(E = x"cee1174c");
-- Step 36
wait until rising_edge(clk);
check(A = x"0f511fd8");
check(B = x"dcbbb0cb");
check(C = x"085e5ab5");
check(D = x"4b03af04");
check(E = x"811bea82");
-- Step 37
wait until rising_edge(clk);
check(A = x"dc63973f");
check(B = x"0f511fd8");
check(C = x"f72eec32");
check(D = x"085e5ab5");
check(E = x"4b03af04");
-- Step 38
wait until rising_edge(clk);
check(A = x"4c986405");
check(B = x"dc63973f");
check(C = x"03d447f6");
check(D = x"f72eec32");
check(E = x"085e5ab5");
-- Step 39
wait until rising_edge(clk);
check(A = x"32de1cba");
check(B = x"4c986405");
check(C = x"f718e5cf");
check(D = x"03d447f6");
check(E = x"f72eec32");
-- Step 40
wait until rising_edge(clk);
check(A = x"fc87dedf");
check(B = x"32de1cba");
check(C = x"53261901");
check(D = x"f718e5cf");
check(E = x"03d447f6");
-- Step 41
wait until rising_edge(clk);
check(A = x"970a0d5c");
check(B = x"fc87dedf");
check(C = x"8cb7872e");
check(D = x"53261901");
check(E = x"f718e5cf");
-- Step 42
wait until rising_edge(clk);
check(A = x"7f193dc5");
check(B = x"970a0d5c");
check(C = x"ff21f7b7");
check(D = x"8cb7872e");
check(E = x"53261901");
-- Step 43
wait until rising_edge(clk);
check(A = x"ee1b1aaf");
check(B = x"7f193dc5");
check(C = x"25c28357");
check(D = x"ff21f7b7");
check(E = x"8cb7872e");
-- Step 44
wait until rising_edge(clk);
check(A = x"40f28e09");
check(B = x"ee1b1aaf");
check(C = x"5fc64f71");
check(D = x"25c28357");
check(E = x"ff21f7b7");
-- Step 45
wait until rising_edge(clk);
check(A = x"1c51e1f2");
check(B = x"40f28e09");
check(C = x"fb86c6ab");
check(D = x"5fc64f71");
check(E = x"25c28357");
-- Step 46
wait until rising_edge(clk);
check(A = x"a01b846c");
check(B = x"1c51e1f2");
check(C = x"503ca382");
check(D = x"fb86c6ab");
check(E = x"5fc64f71");
-- Step 47
wait until rising_edge(clk);
check(A = x"bead02ca");
check(B = x"a01b846c");
check(C = x"8714787c");
check(D = x"503ca382");
check(E = x"fb86c6ab");
-- Step 48
wait until rising_edge(clk);
check(A = x"baf39337");
check(B = x"bead02ca");
check(C = x"2806e11b");
check(D = x"8714787c");
check(E = x"503ca382");
-- Step 49
wait until rising_edge(clk);
check(A = x"120731c5");
check(B = x"baf39337");
check(C = x"afab40b2");
check(D = x"2806e11b");
check(E = x"8714787c");
-- Step 50
wait until rising_edge(clk);
check(A = x"641db2ce");
check(B = x"120731c5");
check(C = x"eebce4cd");
check(D = x"afab40b2");
check(E = x"2806e11b");
-- Step 51
wait until rising_edge(clk);
check(A = x"3847ad66");
check(B = x"641db2ce");
check(C = x"4481cc71");
check(D = x"eebce4cd");
check(E = x"afab40b2");
-- Step 52
wait until rising_edge(clk);
check(A = x"e490436d");
check(B = x"3847ad66");
check(C = x"99076cb3");
check(D = x"4481cc71");
check(E = x"eebce4cd");
-- Step 53
wait until rising_edge(clk);
check(A = x"27e9f1d8");
check(B = x"e490436d");
check(C = x"8e11eb59");
check(D = x"99076cb3");
check(E = x"4481cc71");
-- Step 54
wait until rising_edge(clk);
check(A = x"7b71f76d");
check(B = x"27e9f1d8");
check(C = x"792410db");
check(D = x"8e11eb59");
check(E = x"99076cb3");
-- Step 55
wait until rising_edge(clk);
check(A = x"5e6456af");
check(B = x"7b71f76d");
check(C = x"09fa7c76");
check(D = x"792410db");
check(E = x"8e11eb59");
-- Step 56
wait until rising_edge(clk);
check(A = x"c846093f");
check(B = x"5e6456af");
check(C = x"5edc7ddb");
check(D = x"09fa7c76");
check(E = x"792410db");
-- Step 57
wait until rising_edge(clk);
check(A = x"d262ff50");
check(B = x"c846093f");
check(C = x"d79915ab");
check(D = x"5edc7ddb");
check(E = x"09fa7c76");
-- Step 58
wait until rising_edge(clk);
check(A = x"09d785fd");
check(B = x"d262ff50");
check(C = x"f211824f");
check(D = x"d79915ab");
check(E = x"5edc7ddb");
-- Step 59
wait until rising_edge(clk);
check(A = x"3f52de5a");
check(B = x"09d785fd");
check(C = x"3498bfd4");
check(D = x"f211824f");
check(E = x"d79915ab");
-- Step 60
wait until rising_edge(clk);
check(A = x"d756c147");
check(B = x"3f52de5a");
check(C = x"4275e17f");
check(D = x"3498bfd4");
check(E = x"f211824f");
-- Step 61
wait until rising_edge(clk);
check(A = x"548c9cb2");
check(B = x"d756c147");
check(C = x"8fd4b796");
check(D = x"4275e17f");
check(E = x"3498bfd4");
-- Step 62
wait until rising_edge(clk);
check(A = x"b66c020b");
check(B = x"548c9cb2");
check(C = x"f5d5b051");
check(D = x"8fd4b796");
check(E = x"4275e17f");
-- Step 63
wait until rising_edge(clk);
check(A = x"6b61c9e1");
check(B = x"b66c020b");
check(C = x"9523272c");
check(D = x"f5d5b051");
check(E = x"8fd4b796");
-- Step 64
wait until rising_edge(clk);
check(A = x"19dfa7ac");
check(B = x"6b61c9e1");
check(C = x"ed9b0082");
check(D = x"9523272c");
check(E = x"f5d5b051");
-- Step 65
wait until rising_edge(clk);
check(A = x"101655f9");
check(B = x"19dfa7ac");
check(C = x"5ad87278");
check(D = x"ed9b0082");
check(E = x"9523272c");
-- Step 66
wait until rising_edge(clk);
check(A = x"0c3df2b4");
check(B = x"101655f9");
check(C = x"0677e9eb");
check(D = x"5ad87278");
check(E = x"ed9b0082");
-- Step 67
wait until rising_edge(clk);
check(A = x"78dd4d2b");
check(B = x"0c3df2b4");
check(C = x"4405957e");
check(D = x"0677e9eb");
check(E = x"5ad87278");
-- Step 68
wait until rising_edge(clk);
check(A = x"497093c0");
check(B = x"78dd4d2b");
check(C = x"030f7cad");
check(D = x"4405957e");
check(E = x"0677e9eb");
-- Step 69
wait until rising_edge(clk);
check(A = x"3f2588c2");
check(B = x"497093c0");
check(C = x"de37534a");
check(D = x"030f7cad");
check(E = x"4405957e");
-- Step 70
wait until rising_edge(clk);
check(A = x"c199f8c7");
check(B = x"3f2588c2");
check(C = x"125c24f0");
check(D = x"de37534a");
check(E = x"030f7cad");
-- Step 71
wait until rising_edge(clk);
check(A = x"39859de7");
check(B = x"c199f8c7");
check(C = x"8fc96230");
check(D = x"125c24f0");
check(E = x"de37534a");
-- Step 72
wait until rising_edge(clk);
check(A = x"edb42de4");
check(B = x"39859de7");
check(C = x"f0667e31");
check(D = x"8fc96230");
check(E = x"125c24f0");
-- Step 73
wait until rising_edge(clk);
check(A = x"11793f6f");
check(B = x"edb42de4");
check(C = x"ce616779");
check(D = x"f0667e31");
check(E = x"8fc96230");
-- Step 74
wait until rising_edge(clk);
check(A = x"5ee76897");
check(B = x"11793f6f");
check(C = x"3b6d0b79");
check(D = x"ce616779");
check(E = x"f0667e31");
-- Step 75
wait until rising_edge(clk);
check(A = x"63f7dab7");
check(B = x"5ee76897");
check(C = x"c45e4fdb");
check(D = x"3b6d0b79");
check(E = x"ce616779");
-- Step 76
wait until rising_edge(clk);
check(A = x"a079b7d9");
check(B = x"63f7dab7");
check(C = x"d7b9da25");
check(D = x"c45e4fdb");
check(E = x"3b6d0b79");
-- Step 77
wait until rising_edge(clk);
check(A = x"860d21cc");
check(B = x"a079b7d9");
check(C = x"d8fdf6ad");
check(D = x"d7b9da25");
check(E = x"c45e4fdb");
-- Step 78
wait until rising_edge(clk);
check(A = x"5738d5e1");
check(B = x"860d21cc");
check(C = x"681e6df6");
check(D = x"d8fdf6ad");
check(E = x"d7b9da25");
-- Step 79
wait until rising_edge(clk);
check(A = x"42541b35");
check(B = x"5738d5e1");
check(C = x"21834873");
check(D = x"681e6df6");
check(E = x"d8fdf6ad");
-- Check final result
wait until is_complete = '1';
check(H0_out = x"a9993e36");
check(H1_out = x"4706816a");
check(H2_out = x"ba3e2571");
check(H3_out = x"7850c26c");
check(H4_out = x"9cd0d89d");
test_runner_cleanup(runner);
end process;
end unit_sha1_test_2_tb_arch;
|
-- ========================================
-- [] File Name : types.vhdl
--
-- [] Creation Date : January 2018
--
-- [] Author 1 : <NAME> (<EMAIL>)
--
-- [] Author 2 : <NAME>(<EMAIL>)
-- ========================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package Common is
generic(BUS_WIDTH: INTEGER := 16);
generic(ELEMENT_WIDTH: INTEGER := 32);
type SORT_ELEMENT is STD_LOGIC_VECTOR(ELEMENT_WIDTH - 1 downto 0);
type BMS_BUS is array(BUS_WIDTH - 1 downto 0) of SORT_ELEMENT;
end Common;
|
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
-- The following code must appear in the VHDL architecture header.
library ieee;
use ieee.std_logic_1164.all;
package blk_ram_pkg is
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT blk_ram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
end package blk_ram_pkg;
-- eof
|
<reponame>schubi93/paranut
--------------------------------------------------------------------------------
-- This file is part of the ParaNut project.
--
-- Copyright (C) 2013-2019 <NAME> <<EMAIL>>
-- <NAME>, <<EMAIL>>
-- Hochschule Augsburg, University of Applied Sciences
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation and/or
-- other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Description:
-- Component and type declarations for the mifu module
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library paranut;
use paranut.paranut_config.all;
use paranut.types.all;
use paranut.memu_lib.all;
use paranut.histogram.all;
package ifu is
type ifu_in_type is record
nexti : std_logic;
jump : std_logic;
-- (next, jump) = (1, 1) lets the (current + 2)'th instruction be the jump target.
-- Logically, 'next' is performed before 'jump'. Hence, jump instructions may either sequentially first
-- assert 'next' and then 'jump' or both signals in the same cycle. The former way is required for JAL instructions
-- to get the right return address, which is PC+8 (or NPC+4).
jump_adr : TWord;
flush : std_logic;
-- Histogram...
--hist_enable : std_logic;
end record;
type ifu_in_vector is array (natural range <>) of ifu_in_type;
type ifu_out_type is record
ir : TWord; -- registered outputs
pc : TWord;
npc : TWord;
ir_valid : std_logic;
npc_valid : std_logic;
-- Histogram...
--buf_fill_hist : TWord_Vec(0 to CFG_IFU_IBUF_SIZE+1);
--hist_ctrl : hist_ctrl_type;
end record;
type ifu_out_vector is array (natural range <>) of ifu_out_type;
component mifu_wrapper
port (
clk : in std_logic;
reset : in std_logic;
-- to EXU...
ifui : in ifu_in_type;
ifuo : out ifu_out_type;
-- to MEMU (read port)...
rpi : out readport_in_type;
rpo : in readport_out_type;
-- from CePU...
icache_enable : in std_logic
);
end component;
end package;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.3
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity reduce_2 is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x_V_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
x_V_ce0 : OUT STD_LOGIC;
x_V_q0 : IN STD_LOGIC_VECTOR (12 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (17 downto 0) );
end;
architecture behav of reduce_2 is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_6 : STD_LOGIC_VECTOR (2 downto 0) := "110";
constant ap_const_lv3_7 : STD_LOGIC_VECTOR (2 downto 0) := "111";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal i_4_fu_161_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal i_4_reg_361 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal exitcond3_fu_155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_172_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_18_reg_371 : STD_LOGIC_VECTOR (2 downto 0);
signal i_3_fu_226_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal i_3_reg_378 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal exitcond_fu_220_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_245_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_388 : STD_LOGIC_VECTOR (0 downto 0);
signal right_1_V_1_fu_285_p3 : STD_LOGIC_VECTOR (17 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal right_1_V_2_fu_292_p3 : STD_LOGIC_VECTOR (17 downto 0);
signal grp_reduce_fu_143_ap_return : STD_LOGIC_VECTOR (17 downto 0);
signal p_Val2_8_reg_444 : STD_LOGIC_VECTOR (17 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal grp_reduce_fu_143_ap_ready : STD_LOGIC;
signal grp_reduce_fu_143_ap_done : STD_LOGIC;
signal grp_reduce_fu_143_ap_start : STD_LOGIC;
signal grp_reduce_fu_143_ap_idle : STD_LOGIC;
signal i_reg_97 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal p_Val2_7_reg_108 : STD_LOGIC_VECTOR (17 downto 0);
signal p_Val2_s_reg_120 : STD_LOGIC_VECTOR (17 downto 0);
signal i2_reg_132 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_reduce_fu_143_ap_start_reg : STD_LOGIC := '0';
signal tmp_fu_167_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_240_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal left_7_V_fu_44 : STD_LOGIC_VECTOR (17 downto 0);
signal left_0_V_fu_176_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal left_7_V_1_fu_48 : STD_LOGIC_VECTOR (17 downto 0);
signal left_7_V_2_fu_52 : STD_LOGIC_VECTOR (17 downto 0);
signal left_7_V_3_fu_56 : STD_LOGIC_VECTOR (17 downto 0);
signal left_7_V_4_fu_60 : STD_LOGIC_VECTOR (17 downto 0);
signal left_7_V_5_fu_64 : STD_LOGIC_VECTOR (17 downto 0);
signal left_7_V_6_fu_68 : STD_LOGIC_VECTOR (17 downto 0);
signal left_7_V_7_fu_72 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_fu_232_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal right_0_V_fu_281_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal tmp1_fu_299_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
component reduce IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x_0_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
x_1_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
x_2_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
x_3_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
x_4_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
x_5_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
x_6_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
x_7_V_read : IN STD_LOGIC_VECTOR (17 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (17 downto 0) );
end component;
begin
grp_reduce_fu_143 : component reduce
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_reduce_fu_143_ap_start,
ap_done => grp_reduce_fu_143_ap_done,
ap_idle => grp_reduce_fu_143_ap_idle,
ap_ready => grp_reduce_fu_143_ap_ready,
x_0_V_read => left_7_V_fu_44,
x_1_V_read => left_7_V_1_fu_48,
x_2_V_read => left_7_V_2_fu_52,
x_3_V_read => left_7_V_3_fu_56,
x_4_V_read => left_7_V_4_fu_60,
x_5_V_read => left_7_V_5_fu_64,
x_6_V_read => left_7_V_6_fu_68,
x_7_V_read => left_7_V_7_fu_72,
ap_return => grp_reduce_fu_143_ap_return);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
grp_reduce_fu_143_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_reduce_fu_143_ap_start_reg <= ap_const_logic_0;
else
if (((exitcond_fu_220_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state5))) then
grp_reduce_fu_143_ap_start_reg <= ap_const_logic_1;
elsif ((grp_reduce_fu_143_ap_ready = ap_const_logic_1)) then
grp_reduce_fu_143_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i2_reg_132_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond3_fu_155_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
i2_reg_132 <= ap_const_lv2_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
i2_reg_132 <= i_3_reg_378;
end if;
end if;
end process;
i_reg_97_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
i_reg_97 <= i_4_reg_361;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_97 <= ap_const_lv4_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
i_3_reg_378 <= i_3_fu_226_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_4_reg_361 <= i_4_fu_161_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_1_fu_48(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_2_fu_52(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_3) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_3_fu_56(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_4) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_4_fu_60(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_5) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_5_fu_64(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_6) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_6_fu_68(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_7) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_7_fu_72(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_18_reg_371 = ap_const_lv3_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
left_7_V_fu_44(12 downto 0) <= left_0_V_fu_176_p1(12 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
p_Val2_7_reg_108 <= right_1_V_1_fu_285_p3;
p_Val2_s_reg_120 <= right_1_V_2_fu_292_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (grp_reduce_fu_143_ap_done = ap_const_logic_1))) then
p_Val2_8_reg_444 <= grp_reduce_fu_143_ap_return;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond3_fu_155_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
tmp_18_reg_371 <= tmp_18_fu_172_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_fu_220_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state5))) then
tmp_19_reg_388 <= tmp_19_fu_245_p1;
end if;
end if;
end process;
left_7_V_fu_44(17 downto 13) <= "00000";
left_7_V_1_fu_48(17 downto 13) <= "00000";
left_7_V_2_fu_52(17 downto 13) <= "00000";
left_7_V_3_fu_56(17 downto 13) <= "00000";
left_7_V_4_fu_60(17 downto 13) <= "00000";
left_7_V_5_fu_64(17 downto 13) <= "00000";
left_7_V_6_fu_68(17 downto 13) <= "00000";
left_7_V_7_fu_72(17 downto 13) <= "00000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, exitcond3_fu_155_p2, ap_CS_fsm_state5, exitcond_fu_220_p2, ap_CS_fsm_state7, grp_reduce_fu_143_ap_done)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((exitcond3_fu_155_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when ap_ST_fsm_state5 =>
if (((exitcond_fu_220_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state5))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (grp_reduce_fu_143_ap_done = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state8;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state8)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state8) or ((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state8)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= std_logic_vector(unsigned(tmp1_fu_299_p2) + unsigned(p_Val2_7_reg_108));
exitcond3_fu_155_p2 <= "1" when (i_reg_97 = ap_const_lv4_8) else "0";
exitcond_fu_220_p2 <= "1" when (i2_reg_132 = ap_const_lv2_2) else "0";
grp_reduce_fu_143_ap_start <= grp_reduce_fu_143_ap_start_reg;
i_3_fu_226_p2 <= std_logic_vector(unsigned(i2_reg_132) + unsigned(ap_const_lv2_1));
i_4_fu_161_p2 <= std_logic_vector(unsigned(i_reg_97) + unsigned(ap_const_lv4_1));
left_0_V_fu_176_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x_V_q0),18));
right_0_V_fu_281_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x_V_q0),18));
right_1_V_1_fu_285_p3 <=
right_0_V_fu_281_p1 when (tmp_19_reg_388(0) = '1') else
p_Val2_7_reg_108;
right_1_V_2_fu_292_p3 <=
p_Val2_s_reg_120 when (tmp_19_reg_388(0) = '1') else
right_0_V_fu_281_p1;
tmp1_fu_299_p2 <= std_logic_vector(unsigned(p_Val2_s_reg_120) + unsigned(p_Val2_8_reg_444));
tmp_18_fu_172_p1 <= i_reg_97(3 - 1 downto 0);
tmp_19_fu_245_p1 <= i2_reg_132(1 - 1 downto 0);
tmp_1_fu_232_p3 <= (ap_const_lv2_2 & i2_reg_132);
tmp_fu_167_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_97),64));
tmp_s_fu_240_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_fu_232_p3),64));
x_V_address0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state5, tmp_fu_167_p1, tmp_s_fu_240_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
x_V_address0 <= tmp_s_fu_240_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
x_V_address0 <= tmp_fu_167_p1(4 - 1 downto 0);
else
x_V_address0 <= "XXXX";
end if;
end process;
x_V_ce0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state5)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state2))) then
x_V_ce0 <= ap_const_logic_1;
else
x_V_ce0 <= ap_const_logic_0;
end if;
end process;
end behav;
|
<reponame>kazooiebombchu/audio-synthesizer
-------------------------------------------------------------------------------
-- File : piano.vhd
-- Created : 23.2.2018
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Simple piano block which produces n_keys_g output.
-- Can be used to play melody instead of key presses.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity piano is
generic (
clk_freq_g : positive := 18_432_000; -- 18.432 MHz
tone_change_freq_g : real := 0.5; -- 2 seconds/tone.
n_keys_g : positive := 4
);
port (
clk : in std_logic;
rst_n : in std_logic;
enable_in : in std_logic;
keys_out : out std_logic_vector(n_keys_g - 1 downto 0)
);
end piano;
architecture rtl of piano is
constant logic_array_size : integer := 2**n_keys_g;
type logic_array is array (integer range <>)
of std_logic_vector(n_keys_g - 1 downto 0);
-- Emulated key presses.
constant keys_c : logic_array(0 to logic_array_size - 1) := (
"0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111"
);
-- Counter maximum for keeping the tone.
constant counter_max_c : integer :=
integer(real(clk_freq_g) / tone_change_freq_g);
-- Counter registers.
signal keys_index_r : integer range 0 to logic_array_size - 1;
signal counter_r : integer range 0 to counter_max_c;
begin
-- Process to increase counter and then when it is reached. Assign new tone
-- index.
counter : process(clk, rst_n)
begin
if rst_n = '0' then
keys_index_r <= 0;
counter_r <= 0;
elsif clk'event and clk = '1' then
if enable_in = '0' then
keys_index_r <= 0;
counter_r <= 0;
elsif counter_r /= counter_max_c then
counter_r <= counter_r + 1;
else
counter_r <= 0;
if keys_index_r /= logic_array_size - 1 then
keys_index_r <= keys_index_r + 1;
else
keys_index_r <= 0;
end if;
end if;
end if;
end process counter;
-- Combinational process to assign new tone to the output.
keys : process(keys_index_r)
begin
keys_out <= keys_c(keys_index_r);
end process keys;
end rtl;
|
<reponame>LenaicElsig/sem_labs
library Common;
use Common.CommonLib.all;
ARCHITECTURE studentVersion OF envelopeRetreiver IS
BEGIN
morseEnvelope <= '0';
END ARCHITECTURE studentVersion;
|
<reponame>rqou/yavhdl<gh_stars>10-100
entity test is
package a is new b generic map(c => baz foo'bar);
end;
|
<filename>examples/goFB_only/vhdl/pc2_conveyor/vhdl/Conveyor_SIFB.vhd
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by <NAME> and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Basic Function Block for Conveyor_SIFB
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Conveyor_SIFB is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--input events
conveyor_run_changed_eI : in std_logic := '0';
--output events
conveyor_moving_changed_eO : out std_logic;
conveyor_jammed_changed_eO : out std_logic;
--input variables
conveyor_run_I : in std_logic := '0'; --type was BOOL
--output variables
conveyor_moving_O : out std_logic; --type was BOOL
conveyor_jammed_O : out std_logic; --type was BOOL
--special emitted internal vars for I/O
rx_conveyor_moving : in std_logic; --type was BOOL
rx_conveyor_jammed : in std_logic; --type was BOOL
tx_conveyor_run : out std_logic; --type was BOOL
--for done signal
done : out std_logic
);
end entity;
architecture rtl of Conveyor_SIFB is
-- Build an enumerated type for the state machine
type state_type is (STATE_Start);
-- Register to hold the current state
signal state : state_type := STATE_Start;
-- signals to store variable sampled on enable
signal conveyor_run : std_logic := '0'; --register for input
-- signals to rename outputs
signal conveyor_moving : std_logic := '0';
signal conveyor_jammed : std_logic := '0';
--signals to rename output events
signal conveyor_moving_changed_eO_ecc_out : std_logic := '0'; --used when event driven from ECC (normal FB behaviour)
signal conveyor_moving_changed_eO_alg_out : std_logic := '0'; --used when event driven from algorithm (normal SIFB behaviour)
signal conveyor_jammed_changed_eO_ecc_out : std_logic := '0'; --used when event driven from ECC (normal FB behaviour)
signal conveyor_jammed_changed_eO_alg_out : std_logic := '0'; --used when event driven from algorithm (normal SIFB behaviour)
-- signals for enabling algorithms
signal conveyor_sifb_alg_alg_en : std_logic := '0';
signal conveyor_sifb_alg_alg_done : std_logic := '1';
-- signal for algorithm completion
signal AlgorithmsStart : std_logic := '0';
signal AlgorithmsDone : std_logic;
--internal variables
signal rx_conveyor_moving_prev : std_logic; --type was BOOL
signal rx_conveyor_jammed_prev : std_logic; --type was BOOL
begin
-- Registers for data variables (only updated on relevant events)
process (clk)
begin
if rising_edge(clk) then
if sync = '1' then
if conveyor_run_changed_eI = '1' then
conveyor_run <= conveyor_run_I;
end if;
end if;
end if;
end process;
--output var renaming, no output registers as inputs are stored where they are processed
conveyor_moving_O <= conveyor_moving;
conveyor_jammed_O <= conveyor_jammed;
-- Logic to advance to the next state
process (clk, reset)
begin
if reset = '1' then
state <= STATE_Start;
AlgorithmsStart <= '1';
elsif (rising_edge(clk)) then
if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal
AlgorithmsStart <= '0';
elsif enable = '1' then
--default values
state <= state;
AlgorithmsStart <= '0';
--next state logic
case state is
when STATE_Start =>
if true then
state <= STATE_Start;
AlgorithmsStart <= '1';
end if;
end case;
end if;
end if;
end process;
-- Event outputs and internal algorithm triggers depend solely on the current state
process (state)
begin
--default values
--events
conveyor_moving_changed_eO_ecc_out <= '0';
conveyor_jammed_changed_eO_ecc_out <= '0';
--algorithms
conveyor_sifb_alg_alg_en <= '0';
case state is
when STATE_Start =>
conveyor_sifb_alg_alg_en <= '1';
end case;
end process;
-- Algorithms process
process(clk)
begin
if rising_edge(clk) then
if AlgorithmsStart = '1' then
if conveyor_sifb_alg_alg_en = '1' then -- Algorithm conveyor_sifb_alg
conveyor_sifb_alg_alg_done <= '0';
--logic for resetting algorithm-driven output events
conveyor_moving_changed_eO_alg_out <= '0';
conveyor_jammed_changed_eO_alg_out <= '0';
end if;
end if;
if conveyor_sifb_alg_alg_done = '0' then -- Algorithm conveyor_sifb_alg
--begin algorithm raw text
--update previous values
rx_conveyor_moving_prev <= rx_conveyor_moving;
rx_conveyor_jammed_prev <= rx_conveyor_jammed;
--these are what we use to drive events
--conveyor_moving_changed_eO_alg_out;
--conveyor_jammed_changed_eO_alg_out;
if rx_conveyor_moving_prev /= rx_conveyor_moving then
conveyor_moving_changed_eO_alg_out <= '1';
conveyor_moving <= rx_conveyor_moving;
end if;
if rx_conveyor_jammed_prev /= rx_conveyor_jammed then
conveyor_jammed_changed_eO_alg_out <= '1';
conveyor_jammed <= rx_conveyor_jammed;
end if;
--emit outputs (input is already registered to only update on tick boundary with correct input event)
tx_conveyor_run <= conveyor_run;
conveyor_sifb_alg_alg_done <= '1';
--end algorithm raw text
end if;
end if;
end process;
--Done signal
AlgorithmsDone <= (not AlgorithmsStart) and (not enable) and conveyor_sifb_alg_alg_done;
Done <= AlgorithmsDone;
--logic for renamed output events
conveyor_moving_changed_eO <= conveyor_moving_changed_eO_ecc_out or conveyor_moving_changed_eO_alg_out;
conveyor_jammed_changed_eO <= conveyor_jammed_changed_eO_ecc_out or conveyor_jammed_changed_eO_alg_out;
end rtl;
|
<gh_stars>0
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
-- declaring entity
entity inverter is
port (
A: in std_logic_vector(3 downto 0); -- vector input
S: out std_logic_vector(3 downto 0) -- vector output
);
end inverter;
-- declaring architecture
architecture Behavior of inverter is --bitwise inverter
begin
S(0) <= not (A(0)); -- inversing A(0)
S(1) <= not (A(1)); -- inversing A(1)
S(2) <= not (A(2)); -- inversing A(2)
S(3) <= not (A(3)); -- inversing A(3)
end Behavior ;
|
<filename>SIMON/2-SIMON64-128_red1,2,3/RTL/Red_RoundFunction3.vhd
----------------------------------------------------------------------------------
-- COMPANY: Ruhr University Bochum, Embedded Security
-- AUTHOR: https://eprint.iacr.org/2018/203
----------------------------------------------------------------------------------
-- Copyright (c) 2019, <NAME>, <NAME>
-- All rights reserved.
-- BSD-3-Clause License
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the copyright holder, their organization nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTERS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.functions.all;
entity Red_RoundFunction3 is
Generic (
BitNumber : NATURAL;
LFTable : STD_LOGIC_VECTOR(63 downto 0));
port(
data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic);
end entity Red_RoundFunction3;
architecture behavioral of Red_RoundFunction3 is
constant LFTable0 : STD_LOGIC_VECTOR (15 DOWNTO 0) :=
LFTable(60) & LFTable(56) & LFTable(52) & LFTable(48) & LFTable(44) & LFTable(40) & LFTable(36) & LFTable(32) &
LFTable(28) & LFTable(24) & LFTable(20) & LFTable(16) & LFTable(12) & LFTable(8) & LFTable(4) & LFTable(0);
constant LFTable1 : STD_LOGIC_VECTOR (15 DOWNTO 0) :=
LFTable(61) & LFTable(57) & LFTable(53) & LFTable(49) & LFTable(45) & LFTable(41) & LFTable(37) & LFTable(33) &
LFTable(29) & LFTable(25) & LFTable(21) & LFTable(17) & LFTable(13) & LFTable(9) & LFTable(5) & LFTable(1);
constant LFTable2 : STD_LOGIC_VECTOR (15 DOWNTO 0) :=
LFTable(62) & LFTable(58) & LFTable(54) & LFTable(50) & LFTable(46) & LFTable(42) & LFTable(38) & LFTable(34) &
LFTable(30) & LFTable(26) & LFTable(22) & LFTable(18) & LFTable(14) & LFTable(10) & LFTable(6) & LFTable(2);
constant LFTable3 : STD_LOGIC_VECTOR (15 DOWNTO 0) :=
LFTable(63) & LFTable(59) & LFTable(55) & LFTable(51) & LFTable(47) & LFTable(43) & LFTable(39) & LFTable(35) &
LFTable(31) & LFTable(27) & LFTable(23) & LFTable(19) & LFTable(15) & LFTable(11) & LFTable(7) & LFTable(3);
----
signal input0 : STD_LOGIC_VECTOR(3 downto 0);
signal input1 : STD_LOGIC_VECTOR(3 downto 0);
signal input2 : STD_LOGIC_VECTOR(3 downto 0);
signal output : STD_LOGIC_VECTOR(3 downto 0);
begin
input0 <= data_in(3 downto 0);
input1 <= data_in(10 downto 7);
input2 <= data_in(9 downto 6);
------
output <= (input0 AND input1) XOR input2;
------
GEN0: IF BitNumber=0 GENERATE
LF_Process0: Process (output)
begin
data_out <= LFTable0(15-to_integer(unsigned(output)));
end process;
END GENERATE;
GEN1: IF BitNumber=1 GENERATE
LF_Process1: Process (output)
begin
data_out <= LFTable1(15-to_integer(unsigned(output)));
end process;
END GENERATE;
GEN2: IF BitNumber=2 GENERATE
LF_Process2: Process (output)
begin
data_out <= LFTable2(15-to_integer(unsigned(output)));
end process;
END GENERATE;
GEN3: IF BitNumber=3 GENERATE
LF_Process3: Process (output)
begin
data_out <= LFTable3(15-to_integer(unsigned(output)));
end process;
END GENERATE;
end architecture behavioral;
|
<reponame>Kur1su0/Computer-Arch-and-Design
--
-- VHDL Test Bench CAD_lib.lab8_mem_stage_struc_tb.lab8_mem_stage_struc_tester
--
-- Created:
-- by - W.UNKNOWN (DESKTOP-86TQKQ1)
-- at - 02:22:24 04/ 4/2021
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.2 (Build 19)
--
LIBRARY CAD_lib;
USE CAD_lib.RV32I.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.RV32I.ALL;
USE std.textio.all;
ENTITY lab8_mem_stage_struc_tb IS
GENERIC (
width : NATURAL RANGE 1 TO 64 := 32
);
END lab8_mem_stage_struc_tb;
LIBRARY CAD_lib;
USE CAD_lib.ALL;
ARCHITECTURE rtl OF lab8_mem_stage_struc_tb IS
-- Architecture declarations
FILE test_vectors : text OPEN read_mode IS "lab8_mem_stg_vec.txt";
-- Internal signal declarations
SIGNAL Data : std_ulogic_vector(31 DOWNTO 0);
SIGNAL Din : std_ulogic_vector(31 DOWNTO 0);
SIGNAL Address : std_ulogic_vector(31 DOWNTO 0);
SIGNAL Rd_in : std_ulogic_vector(4 DOWNTO 0);
SIGNAL FunC_in : RV32I_Op;
SIGNAL mDelay : std_ulogic;
SIGNAL clk : std_ulogic;
SIGNAL r,r_valid : std_ulogic;
SIGNAL w,w_valid : std_ulogic;
SIGNAL stall,stall_valid : std_ulogic;
SIGNAL Dout,Dout_valid : std_ulogic_vector(31 DOWNTO 0);
SIGNAL Data_out_wback,Data_out_wback_valid : std_ulogic_vector(31 DOWNTO 0);
SIGNAL Address_out_arb,Address_out_arb_valid : std_ulogic_vector(31 DOWNTO 0);
SIGNAL Rd_out,Rd_out_valid : std_ulogic_vector(4 DOWNTO 0);
SIGNAL FunC_out,FunC_out_valid : RV32I_Op;
SIGNAL vecno : NATURAL := 0;
-- Component declarations
COMPONENT lab8_mem_stage_struc
GENERIC (
width : NATURAL RANGE 1 TO 64 := 32
);
PORT (
Data : IN std_ulogic_vector(31 DOWNTO 0);
Din : IN std_ulogic_vector(31 DOWNTO 0);
Address : IN std_ulogic_vector(31 DOWNTO 0);
Rd_in : IN std_ulogic_vector(4 DOWNTO 0);
FunC_in : IN RV32I_Op;
mDelay : IN std_ulogic;
clk : IN std_ulogic;
r : OUT std_ulogic;
w : OUT std_ulogic;
stall : OUT std_ulogic;
Dout : OUT std_ulogic_vector(31 DOWNTO 0);
Data_out_wback : OUT std_ulogic_vector(31 DOWNTO 0);
Address_out_arb : OUT std_ulogic_vector(31 DOWNTO 0);
Rd_out : OUT std_ulogic_vector(4 DOWNTO 0);
FunC_out : OUT RV32I_Op
);
END COMPONENT;
-- embedded configurations
-- pragma synthesis_off
FOR U_0 : lab8_mem_stage_struc USE ENTITY CAD_lib.lab8_mem_stage_struc;
-- pragma synthesis_on
BEGIN
U_0 : lab8_mem_stage_struc
GENERIC MAP (
width => width
)
PORT MAP (
Data => Data,
Din => Din,
Address => Address,
Rd_in => Rd_in,
FunC_in => FunC_in,
mDelay => mDelay,
clk => clk,
r => r,
w => w,
stall => stall,
Dout => Dout,
Data_out_wback => Data_out_wback,
Address_out_arb => Address_out_arb,
Rd_out => Rd_out,
FunC_out => FunC_out
);
stimu : process
VARIABLE L : LINE;
VARIABLE v_Data,v_Din,v_Address : std_ulogic_vector(31 DOWNTO 0);
VARIABLE v_Rd_in,v_Rd_out_valid : std_ulogic_vector(4 DOWNTO 0);
VARIABLE v_FunC_in,v_FunC_out_valid : Func_Name;
VARIABLE v_mDelay,v_r_valid,v_w_valid,v_stall_valid :std_ulogic;
VARIABLE v_Dout_valid,v_Data_out_wback_valid,v_Address_out_arb_valid : std_ulogic_vector(31 DOWNTO 0);
VARIABLE space:string(1 DOWNTO 1);
begin
readline(test_vectors,L);
WHILE NOT endfile(test_vectors) LOOP
readline(test_vectors,L);
hread(L,v_Data); Data<=v_Data;
hread(L,v_Din); Din<=v_Din;
hread(L,v_Address); Address<=v_Address;
read(L,v_Rd_in); Rd_in<=v_Rd_in;
read(L,space);
read(L,v_FunC_in); FunC_in<=Ftype(v_FunC_in);
read(L,v_mDelay); mDelay<=v_mDelay;
clk<='0'; wait for 100ns;
read(L,v_r_valid); r_valid<=v_r_valid;
read(L,v_w_valid); w_valid<=v_w_valid;
read(L,v_stall_valid); stall_valid<=v_stall_valid;
hread(L,v_Dout_valid); Dout_valid<=v_Dout_valid;
hread(L,v_Data_out_wback_valid); Data_out_wback_valid<=v_Data_out_wback_valid;
hread(L,v_Address_out_arb_valid); Address_out_arb_valid<=v_Address_out_arb_valid;
read(L,v_Rd_out_valid); Rd_out_valid<=v_Rd_out_valid;
read(L,space);
read(L,v_Func_out_valid); Func_out_valid<=Ftype(v_Func_out_valid);
clk<='1'; wait for 100ns;
End Loop;
report "END of TB";
wait;
end process;
check: process(clk)
begin
if falling_edge(clk) then
vecno <= vecno + 1;
ASSERT r=r_valid
REPORT "ERROR: r " & to_string(vecno)
SEVERITY WARNING;
ASSERT w=w_valid
REPORT "ERROR: w " & to_string(vecno)
SEVERITY WARNING;
ASSERT stall=stall_valid
REPORT "ERROR: stall " & to_string(vecno)
SEVERITY WARNING;
ASSERT Dout=Dout_valid
REPORT "ERROR: Dout " & to_string(vecno)
SEVERITY WARNING;
ASSERT Data_out_wback=Data_out_wback_valid
REPORT "ERROR: Data_out_wback " & to_string(vecno)
SEVERITY WARNING;
ASSERT Address_out_arb=Address_out_arb_valid
REPORT "ERROR: Address_out_arb " & to_string(vecno)
SEVERITY WARNING;
ASSERT Rd_out=Rd_out_valid
REPORT "ERROR: Rd_out " & to_string(vecno)
SEVERITY WARNING;
ASSERT Func_out=Func_out_valid
REPORT "ERROR: Func_out " & to_string(vecno)
SEVERITY WARNING;
end if;
end process;
-- process
-- begin
-- Data <=x"00000003";
-- Din <=x"80000001";
-- Address <=x"00000001" ;
-- Rd_in <="00010";
-- FunC_in <=LB;
-- mDelay <='1';
-- clk <='0'; wait for 100ns;
-- clk <='1'; wait for 100ns;
-- Din <=x"8000008f";
-- Address <=x"0000000f" ;
-- mDelay <='0';
-- clk <='0'; wait for 100ns;
-- clk <='1'; wait for 100ns;
-- clk <='0'; wait for 100ns;
-- clk <='1'; wait for 100ns;
-- clk <='0'; wait for 100ns;
-- clk <='1'; wait for 100ns;
-- wait;
-- end process;
END rtl;
|
<gh_stars>0
--
-----------------------------------------------------------------
-- COMPANY : Ruhr University Bochum
-- AUTHOR : <NAME> (<EMAIL>) <NAME> (<EMAIL>)
-- DOCUMENT: https://doi.org/10.46586/tches.v2021.i1.305-342
-- -----------------------------------------------------------------
--
-- Copyright (c) 2020, <NAME>, <NAME>
--
-- All rights reserved.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTERS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Please see LICENSE and README for license and further instructions.
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Midori64_RoundBased IS
PORT ( input1: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
input2: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
wk : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
k_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
k_1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
output1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
output2 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
round : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
enc_dec : IN STD_LOGIC;
roundStart_Select : IN STD_LOGIC;
clk : IN STD_LOGIC);
END Midori64_RoundBased;
ARCHITECTURE behavioral OF Midori64_RoundBased IS
SIGNAL add_Result_Start1,
add_Result_Start2: STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL rounds_Output1,
rounds_Output2 : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- PORT MAPPING
add_Result_Start1 <= input1 XOR wk;
add_Result_Start2 <= input2;
rounds : Entity work.Midori64_Round
PORT MAP ( input1 => add_Result_Start1,
input2 => add_Result_Start2,
k_0 => k_0,
k_1 => k_1,
result1 => rounds_Output1,
result2 => rounds_Output2,
-- CONTROLLER SIGNALS
enc_dec => enc_dec,
clk => clk,
round_number => round,
roundStart_Select => roundStart_Select);
output1 <= rounds_Output1;
output2 <= rounds_Output2 XOR wk;
END behavioral;
|
<filename>Semester 3/Computer Organization (VHDL) [EN]/9999_Theory/Lab7/mealy.vhd<gh_stars>1-10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mealy IS
PORT(
clk, areset, inp : IN STD_LOGIC;
outpt : OUT STD_LOGIC
);
END mealy;
ARCHITECTURE fsm OF mealy IS
TYPE state_type IS (S0, S1, S2);
SIGNAL state : state_type;
BEGIN
PROCESS(clk, areset)
BEGIN
IF(areset = '1') THEN state <= S0;
ELSIF(RISING_EDGE(clk)) THEN
CASE state IS
WHEN S0 =>
IF(inp = '1') THEN state <= S1;
ELSE state <= S2; END IF;
WHEN S1 =>
IF(inp = '1') THEN state <= S1;
ELSE state <= S2; END IF;
WHEN S2 =>
IF(inp = '1') THEN state <= S0;
ELSE state <= S1; END IF;
END CASE;
END IF;
END PROCESS;
PROCESS(state, inp)
BEGIN
CASE state IS
WHEN S0 =>
outpt <= '1';
WHEN S1 =>
IF(inp = '1') THEN outpt <= '0';
ELSE outpt <= '1'; END IF;
WHEN S2 =>
IF(inp = '1') THEN outpt <= '1';
ELSE outpt <= '0'; END IF;
END CASE;
END PROCESS;
END fsm;
|
-- Copyright 2018 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.Utils.all;
use work.Arrow.all;
entity BufferReaderCmdGenBusReq is
generic (
---------------------------------------------------------------------------
-- Bus metrics and configuration
---------------------------------------------------------------------------
-- Bus address width.
BUS_ADDR_WIDTH : natural;
-- Bus burst length width.
BUS_LEN_WIDTH : natural;
-- Bus data width.
BUS_DATA_WIDTH : natural;
-- Number of beats in a burst step.
BUS_BURST_STEP_LEN : natural;
-- Maximum number of beats in a burst.
BUS_BURST_MAX_LEN : natural;
---------------------------------------------------------------------------
-- Arrow metrics and configuration
---------------------------------------------------------------------------
-- Index field width.
INDEX_WIDTH : natural;
---------------------------------------------------------------------------
-- Buffer metrics and configuration
---------------------------------------------------------------------------
-- Buffer element width in bits.
ELEMENT_WIDTH : natural;
-- Whether this is a normal buffer or an index buffer.
IS_INDEX_BUFFER : boolean;
-- Wether or not this component should check if the first and last index
-- are not equal
CHECK_INDEX : boolean
);
port (
---------------------------------------------------------------------------
-- Clock domains
---------------------------------------------------------------------------
-- Rising-edge sensitive clock and active-high synchronous reset.
clk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
-- Command stream input
---------------------------------------------------------------------------
-- Command stream input. firstIdx and lastIdx represent a range of elements
-- to be fetched from memory. firstIdx is inclusive, lastIdx is exclusive
-- for normal buffers and inclusive for index buffers, in all cases
-- resulting in lastIdx - firstIdx elements. baseAddr is the pointer to the
-- first element in the buffer. implicit may be set for null bitmap readers
-- if null count is zero; if it is set, no bus requests will be made, and
-- the unit will behave as if it receives all-one bus responses.
cmdIn_valid : in std_logic;
cmdIn_ready : out std_logic;
cmdIn_firstIdx : in std_logic_vector(INDEX_WIDTH-1 downto 0);
cmdIn_lastIdx : in std_logic_vector(INDEX_WIDTH-1 downto 0);
cmdIn_baseAddr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
cmdIn_implicit : in std_logic;
---------------------------------------------------------------------------
-- Output streams
---------------------------------------------------------------------------
-- Bus read request (bus clock domain). addr represents the start address
-- for the transfer, len is the amount of requested words requested in the
-- burst. The maximum for len is set by BUS_BURST_STEP_LEN. Bursts never cross
-- BUS_BURST_STEP_LEN-sized alignment boundaries.
busReq_valid : out std_logic;
busReq_ready : in std_logic;
busReq_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
busReq_len : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0)
);
end BufferReaderCmdGenBusReq;
architecture rtl of BufferReaderCmdGenBusReq is
type state_type is (IDLE, INDEX, PRE_STEP, MAX, POST_STEP);
type input_record is record
ready : std_logic;
end record;
constant input_reset : input_record := (ready => '0');
type master_record is record
addr : unsigned(BUS_ADDR_WIDTH-1 downto 0);
len : unsigned(BUS_LEN_WIDTH-1 downto 0);
valid : std_logic;
end record;
type index_record is record
first : unsigned(INDEX_WIDTH-1 downto 0);
last : unsigned(INDEX_WIDTH-1 downto 0);
current : unsigned(INDEX_WIDTH-1 downto 0);
end record;
type regs_record is record
state : state_type;
input : input_record;
index : index_record;
master : master_record;
base_address : unsigned(BUS_ADDR_WIDTH-1 downto 0);
end record;
signal r : regs_record;
signal d : regs_record;
-- Helper functions and constants
-- The pre-alignment state will end when we've reached either the global
-- maximum for the bus_burst_boundary or a maximum burst boundary.
-- However, this operates on the byte level.
constant BYTE_ALIGN : natural := work.Utils.min(BUS_BURST_BOUNDARY, BUS_BURST_MAX_LEN * BUS_DATA_WIDTH / 8);
constant ELEMS_PER_STEP : natural := BUS_DATA_WIDTH * BUS_BURST_STEP_LEN / ELEMENT_WIDTH;
constant ELEMS_PER_MAX : natural := BUS_DATA_WIDTH * BUS_BURST_MAX_LEN / ELEMENT_WIDTH;
-- Index shift required to calculate the byte offset of an element,
-- It depends on the number of bits of the element type as follows:
-- Elem bits| log2(bits) | shift left amount
-- 1 | 0 | -3
-- 2 | 1 | -2
-- 4 | 2 | -1
-- 8 | 3 | 0
-- 16 | 4 | 1
-- 32 | 5 | 2
-- 64 | 6 | 3
-- 128 | 7 | 4
-- ... | ... | ...
-- Thus, we must shift left with -3 + log2(ELEMENT_WIDTH)
-- Index to Byte Address Left Shift Amount
constant ITOBA_LSHIFT : integer := -3 + log2ceil(ELEMENT_WIDTH);
constant STEP_LEN : unsigned(BUS_LEN_WIDTH-1 downto 0) := u(BUS_BURST_STEP_LEN, BUS_LEN_WIDTH);
constant MAX_LEN : unsigned(BUS_LEN_WIDTH-1 downto 0) := u(BUS_BURST_MAX_LEN, BUS_LEN_WIDTH);
constant BYTES_PER_STEP : natural := BUS_DATA_WIDTH * BUS_BURST_STEP_LEN / 8;
constant BYTES_PER_MAX : natural := BUS_DATA_WIDTH * BUS_BURST_MAX_LEN / 8;
signal first_index : unsigned(INDEX_WIDTH-1 downto 0);
signal last_index : unsigned(INDEX_WIDTH-1 downto 0);
signal byte_address : unsigned(BUS_ADDR_WIDTH-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Burst step / index / address calculation
-----------------------------------------------------------------------------
-- Floor align the first index to the no. elements per step.
first_index <= align_beq(r.index.first, log2floor(ELEMS_PER_STEP));
-- Ceil align the last index to the no. elements per step.
last_index <= align_aeq(r.index.last, log2floor(ELEMS_PER_STEP));
-- Get the byte address of this index
byte_address <= r.base_address + shift_left_with_neg(r.index.current, ITOBA_LSHIFT);
-----------------------------------------------------------------------------
-- State machine sequential part
-----------------------------------------------------------------------------
sm_seq: process (clk) is
begin
if rising_edge(clk) then
r <= d;
if reset = '1' then
r.state <= IDLE;
r.master.valid <= '0';
r.input.ready <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- State machine combinatorial part
-----------------------------------------------------------------------------
sm_comb : process (
r,
cmdIn_valid, cmdIn_firstIdx, cmdIn_lastIdx, cmdIn_baseAddr, cmdIn_implicit,
busReq_ready,
byte_address, first_index, last_index
) is
variable v : regs_record;
begin
v := r;
-- Default values:
v.input.ready := '0';
v.master.addr := byte_address;
v.master.len := STEP_LEN;
v.master.valid := '0';
case v.state is
-------------------------------------------------------------------------
when IDLE =>
-------------------------------------------------------------------------
-- We are ready to receive some new input
v.input.ready := '1';
if cmdIn_valid = '1' then
-- Accept command & clock in data, if the first and last index are not the same
if cmdIn_firstIdx /= cmdIn_lastIdx or not CHECK_INDEX then
v.index.first := unsigned(cmdIn_firstIdx);
v.index.last := unsigned(cmdIn_lastIdx);
v.base_address := unsigned(cmdIn_baseAddr);
-- Determine what is to be loaded first
if (IS_INDEX_BUFFER) then
v.index.current := align_beq(unsigned(cmdIn_lastIdx), log2floor(ELEMS_PER_STEP));
else
v.index.current := align_beq(unsigned(cmdIn_firstIdx), log2floor(ELEMS_PER_STEP));
end if;
end if;
end if;
-- Getting out of idle requires no backpressure
-- Ignore commands with the "implicit" flag set; in this case we don't
-- want to generate any bus requests
if cmdIn_valid = '1' then
if cmdIn_implicit = '0' then
if cmdIn_firstIdx /= cmdIn_lastIdx or not CHECK_INDEX then
if IS_INDEX_BUFFER then
v.state := INDEX;
else
v.state := PRE_STEP;
end if;
end if;
end if;
end if;
-------------------------------------------------------------------------
when INDEX =>
-------------------------------------------------------------------------
-- State to fetch the last index, this is used for variable length lists,
-- where the user core needs to know the length of the whole variable
-- length List<Type> element that it will receive
v.master.addr := byte_address;
-- Assuming an index element fits in a burst step, the burst length is
-- always one step for the index state
v.master.len := STEP_LEN;
v.master.valid := '1';
-- Back-pressure
if busReq_ready = '1' then
-- Increase last index by 1 for index buffers
v.index.last := v.index.last + 1;
v.index.current := first_index;
v.state := PRE_STEP;
end if;
-------------------------------------------------------------------------
when PRE_STEP =>
-------------------------------------------------------------------------
-- State to step to first max burst aligned index or last index
v.master.addr := byte_address;
v.master.len := STEP_LEN;
-- Make bus request valid
v.master.valid := '1';
-- Invalidate if we've reached the alignment boundary
if is_aligned(byte_address, log2floor(BYTE_ALIGN)) then
v.master.valid := '0';
v.state := MAX;
end if;
-- Invalidate if we've reached the last index
if (v.index.current = last_index) then
v.master.valid := '0';
v.state := IDLE;
end if;
-- Back-pressure
if busReq_ready = '1' and v.master.valid = '1' then
v.index.current := v.index.current + ELEMS_PER_STEP;
end if;
-------------------------------------------------------------------------
when MAX =>
-------------------------------------------------------------------------
-- State to burst maximum lengths
v.master.addr := byte_address;
v.master.len := MAX_LEN;
-- Make bus request valid
v.master.valid := '1';
-- Invalidate if this burst would go over the last index
if v.index.current + ELEMS_PER_MAX >= last_index then
v.master.valid := '0';
v.state := POST_STEP;
end if;
-- Invalidate if we've reached the last index
if (v.index.current = last_index) then
v.master.valid := '0';
v.state := IDLE;
end if;
-- Back-pressure
if busReq_ready = '1' and v.master.valid = '1' then
v.index.current := v.index.current + ELEMS_PER_MAX;
end if;
-------------------------------------------------------------------------
when POST_STEP =>
-------------------------------------------------------------------------
-- State to step to last index
v.master.addr := byte_address;
v.master.len := STEP_LEN;
-- Make bus request valid
v.master.valid := '1';
-- Invalidate if we've reached the last index
if (v.index.current = last_index) then
v.master.valid := '0';
v.state := IDLE;
end if;
-- Back-pressure
if busReq_ready = '1' and v.master.valid = '1' then
v.index.current := v.index.current + ELEMS_PER_STEP;
end if;
end case;
d <= v;
end process;
cmdIn_ready <= d.input.ready;
busReq_addr <= slv(d.master.addr);
busReq_len <= slv(d.master.len);
busReq_valid <= d.master.valid;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
package my_package is
type Matrix is array(0 to 7) of std_logic_vector(6 downto 0);
end package;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.my_package.all;
entity shifter is
port( CLK : in std_logic;
EN: in std_logic;
SEGMENT_DISPLAY_MAT: in Matrix;
SEGMENT_ENABLE: out std_logic_vector(7 downto 0);
SEGMENT_OUTPUT : out std_logic_vector(6 downto 0));
end shifter;
architecture beh of shifter is
begin
process(CLK)
variable SEG_EN: std_logic_vector(7 downto 0):="00000001";
variable I: integer:= 0;
begin
if(CLK = '1' and CLK'EVENT) then
SEG_EN := SEG_EN(6 downto 0)& SEG_EN(7);
case SEG_EN is
when "00000001" => I:=0;
when "00000010" => I:=1;
when "00000100" => I:=2;
when "00001000" => I:=3;
when "00010000" => I:=4;
when "00100000" => I:=5;
when "01000000" => I:=6;
when "10000000" => I:=7;
when others=> NULL;
end case;
end if;
SEGMENT_OUTPUT<= SEGMENT_DISPLAY_MAT(I);
SEGMENT_ENABLE<= SEG_EN;
end process;
end beh;
|
<reponame>bjacobs1/vunit
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2014-2018, <NAME> <EMAIL>
package body integer_vector_ptr_pkg is
type integer_vector is array (natural range <>) of integer;
type integer_vector_access_t is access integer_vector;
type integer_vector_access_vector_t is array (natural range <>) of integer_vector_access_t;
type integer_vector_access_vector_access_t is access integer_vector_access_vector_t;
type integer_vector_ptr_storage_t is protected
impure function new_integer_vector_ptr(length : natural := 0; value : integer := 0) return integer_vector_ptr_t;
procedure deallocate(ptr : integer_vector_ptr_t);
impure function length(ptr : integer_vector_ptr_t) return integer;
procedure set(ptr : integer_vector_ptr_t; index : integer; value : integer);
impure function get(ptr : integer_vector_ptr_t; index : integer) return integer;
procedure reallocate(ptr : integer_vector_ptr_t; length : natural; value : integer := 0);
procedure resize(ptr : integer_vector_ptr_t; length : natural; drop : natural := 0; value : integer := 0);
end protected;
type integer_vector_ptr_storage_t is protected body
variable current_index : integer := 0;
variable ptrs : integer_vector_access_vector_access_t := null;
impure function new_integer_vector_ptr(length : natural := 0; value : integer := 0) return integer_vector_ptr_t is
variable old_ptrs : integer_vector_access_vector_access_t;
variable retval : integer_vector_ptr_t := (index => current_index);
begin
if ptrs = null then
ptrs := new integer_vector_access_vector_t'(0 => null);
elsif ptrs'length <= current_index then
-- Reallocate ptr pointers to larger ptr
-- Use more size to trade size for speed
old_ptrs := ptrs;
ptrs := new integer_vector_access_vector_t'(0 to ptrs'length + 2**16 => null);
for i in old_ptrs'range loop
ptrs(i) := old_ptrs(i);
end loop;
deallocate(old_ptrs);
end if;
ptrs(current_index) := new integer_vector'(0 to length-1 => value);
current_index := current_index + 1;
return retval;
end function;
procedure deallocate(ptr : integer_vector_ptr_t) is
begin
deallocate(ptrs(ptr.index));
ptrs(ptr.index) := null;
end procedure;
impure function length(ptr : integer_vector_ptr_t) return integer is
begin
return ptrs(ptr.index)'length;
end function;
procedure set(ptr : integer_vector_ptr_t; index : integer; value : integer) is
begin
ptrs(ptr.index)(index) := value;
end procedure;
impure function get(ptr : integer_vector_ptr_t; index : integer) return integer is
begin
return ptrs(ptr.index)(index);
end function;
procedure reallocate(ptr : integer_vector_ptr_t; length : natural; value : integer := 0) is
variable old_ptr, new_ptr : integer_vector_access_t;
begin
deallocate(ptrs(ptr.index));
ptrs(ptr.index) := new integer_vector'(0 to length - 1 => value);
end procedure;
procedure resize(ptr : integer_vector_ptr_t; length : natural; drop : natural := 0; value : integer := 0) is
variable old_ptr, new_ptr : integer_vector_access_t;
variable min_length : natural := length;
begin
new_ptr := new integer_vector'(0 to length - 1 => value);
old_ptr := ptrs(ptr.index);
if min_length > old_ptr'length - drop then
min_length := old_ptr'length - drop;
end if;
for i in 0 to min_length-1 loop
new_ptr(i) := old_ptr(drop + i);
end loop;
ptrs(ptr.index) := new_ptr;
deallocate(old_ptr);
end procedure;
end protected body;
shared variable integer_vector_ptr_storage : integer_vector_ptr_storage_t;
function to_integer(value : integer_vector_ptr_t) return integer is
begin
return value.index;
end function;
impure function to_integer_vector_ptr(value : integer) return integer_vector_ptr_t is
begin
-- @TODO maybe assert that the index is valid
return (index => value);
end function;
impure function new_integer_vector_ptr(length : natural := 0; value : integer := 0) return integer_vector_ptr_t is
begin
return integer_vector_ptr_storage.new_integer_vector_ptr(length, value);
end function;
procedure deallocate(ptr : integer_vector_ptr_t) is
begin
integer_vector_ptr_storage.deallocate(ptr);
end procedure;
impure function length(ptr : integer_vector_ptr_t) return integer is
begin
return integer_vector_ptr_storage.length(ptr);
end function;
procedure set(ptr : integer_vector_ptr_t; index : integer; value : integer) is
begin
integer_vector_ptr_storage.set(ptr, index, value);
end procedure;
impure function get(ptr : integer_vector_ptr_t; index : integer) return integer is
begin
return integer_vector_ptr_storage.get(ptr, index);
end function;
procedure reallocate(ptr : integer_vector_ptr_t; length : natural; value : integer := 0) is
begin
integer_vector_ptr_storage.reallocate(ptr, length, value);
end procedure;
procedure resize(ptr : integer_vector_ptr_t; length : natural; drop : natural := 0; value : integer := 0) is
begin
integer_vector_ptr_storage.resize(ptr, length, drop, value);
end procedure;
function encode(data : integer_vector_ptr_t) return string is
begin
return encode(data.index);
end;
function decode(code : string) return integer_vector_ptr_t is
variable ret_val : integer_vector_ptr_t;
variable index : positive := code'left;
begin
decode(code, index, ret_val);
return ret_val;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out integer_vector_ptr_t) is
begin
decode(code, index, result.index);
end;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port(
opcode: in std_logic_vector(2 downto 0);
operand1: in std_logic_vector(3 downto 0);
operand2: in std_logic_vector(3 downto 0); -- bitove operace - adresa bitu operand2(1 downto 0)
result: buffer std_logic_vector(3 downto 0);
status: out std_logic_vector(2 downto 0)); -- CF - status(2), ZF - status(1), SKIP - status(0)
end alu;
architecture behavioral of alu is
signal cf_auxiliary: std_logic_vector(4 downto 0);
begin
result <=
operand1(3 downto 1) & '1' when opcode = "010" and operand2(1 downto 0) = "00" else
operand1(3 downto 2) & '1' & operand1(0) when opcode = "010" and operand2(1 downto 0) = "01" else
operand1(3) & '1' & operand1(1 downto 0) when opcode = "010" and operand2(1 downto 0) = "10" else
'1' & operand1(2 downto 0) when opcode = "010" and operand2(1 downto 0) = "11" else
operand1(3 downto 1) & '0' when opcode = "011" and operand2(1 downto 0) = "00" else
operand1(3 downto 2) & '0' & operand1(0) when opcode = "011" and operand2(1 downto 0) = "01" else
operand1(3) & '0' & operand1(1 downto 0) when opcode = "011" and operand2(1 downto 0) = "10" else
'0' & operand1(2 downto 0) when opcode = "011" and operand2(1 downto 0) = "11" else
cf_auxiliary(3 downto 0) when opcode = "100" else
cf_auxiliary(3 downto 0) when opcode = "101" else
operand1 xor operand2 when opcode = "110"
else operand1 nand operand2;
cf_auxiliary <=
('0' & operand1) + ('0' & operand2) when opcode = "100"
else ('0' & operand1) - ('0' & operand2);
status(2) <= cf_auxiliary(4);
status(1) <= not (result(0) or result(1) or result(2) or result(3));
status(0) <=
operand1(conv_integer(operand2(1 downto 0))) when opcode = "000" else
not operand1(conv_integer(operand2(1 downto 0))) when opcode = "001" else '0';
end behavioral;
|
<gh_stars>0
library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;
entity opamp is
generic(
vdd : voltage := 15.0;
vss : voltage := -15.0;
gain : real := real'high);
port(
terminal in_p, in_n: electrical;
terminal output: electrical);
end entity;
architecture default of opamp is
quantity vin across in_p to in_n;
quantity vout across iout through output;
begin
if vin'above(vdd/gain) use
vout == vdd;
elsif not vin'above(vss/gain) use
vout == vss;
else
vout == vin*gain;
end use;
break on vin'above(vdd/gain), vin'above(vss/gain);
end architecture;
|
<reponame>bopopescu/lz-test-stand
-------------------------------------------------------------------------------
-- File : FastAdcPhy.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2017-02-04
-- Last update: 2017-10-13
-------------------------------------------------------------------------------
-- Description: LZ FastAdcPhy Top Level
-------------------------------------------------------------------------------
-- This file is part of 'LZ Test Stand Firmware'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'LZ Test Stand Firmware', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.StdRtlPkg.all;
use work.AxiLitePkg.all;
use work.AxiStreamPkg.all;
use work.jesd204bpkg.all;
use work.AppPkg.all;
library unisim;
use unisim.vcomponents.all;
entity FastAdcPhy is
generic (
TPD_G : time := 1 ns;
AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0'));
port (
-- JESD ADC Ports
jesdClkP : in sl;
jesdClkN : in sl;
jesdSysRefP : in sl;
jesdSysRefN : in sl;
jesdRxP : in slv(15 downto 0);
jesdRxN : in slv(15 downto 0);
jesdTxP : out slv(15 downto 0);
jesdTxN : out slv(15 downto 0);
jesdSync : out slv(3 downto 0);
-- Fast ADC SPI Ports
fadcSclk : out sl;
fadcSdin : out sl;
fadcSdout : in sl;
fadcSen : out slv(3 downto 0);
fadcReset : out slv(3 downto 0);
fadcPdn : out slv(3 downto 0);
-- LMK Ports
lmkRefClk : in sl;
lmkRefClkP : out sl;
lmkRefClkN : out sl;
lmkCsL : out sl;
lmkSck : out sl;
lmkSdio : inout sl;
lmkRst : out sl;
lmkSync : out sl;
-- JESD ADC Interface
adcClk : in sl;
adcRst : in sl;
adcValid : out slv(7 downto 0);
adcData : out Slv64Array(7 downto 0);
swTrigger : in sl;
swArmTrig : in sl;
-- AXI-Lite Interface (axilClk domain)
axilClk : in sl;
axilRst : in sl;
axilReadMaster : in AxiLiteReadMasterType;
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType);
end FastAdcPhy;
architecture rtl of FastAdcPhy is
constant NUM_AXI_MASTERS_C : natural := 8;
constant JESD_INDEX_C : natural := 0;
constant LMK_INDEX_C : natural := 1;
constant SPI0_INDEX_C : natural := 2;
constant SPI1_INDEX_C : natural := 3;
constant SPI2_INDEX_C : natural := 4;
constant SPI3_INDEX_C : natural := 5;
constant GTH_INDEX_C : natural := 6;
constant GTH_BASE_ADDR_C : slv(31 downto 0) := (AXI_BASE_ADDR_G+x"0060_0000");
constant DBG_INDEX_C : natural := 7;
constant DBG_BASE_ADDR_C : slv(31 downto 0) := (AXI_BASE_ADDR_G+x"0070_0000");
constant AXI_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXI_MASTERS_C-1 downto 0) := genAxiLiteConfig(NUM_AXI_MASTERS_C, AXI_BASE_ADDR_G, 24, 20);
signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXI_MASTERS_C-1 downto 0);
signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXI_MASTERS_C-1 downto 0);
signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXI_MASTERS_C-1 downto 0);
signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXI_MASTERS_C-1 downto 0);
constant GTH_CONFIG_C : AxiLiteCrossbarMasterConfigArray(JESD_LANE_C-1 downto 0) := genAxiLiteConfig(JESD_LANE_C, GTH_BASE_ADDR_C, 20, 16);
signal gthWriteMasters : AxiLiteWriteMasterArray(JESD_LANE_C-1 downto 0);
signal gthWriteSlaves : AxiLiteWriteSlaveArray(JESD_LANE_C-1 downto 0);
signal gthReadMasters : AxiLiteReadMasterArray(JESD_LANE_C-1 downto 0);
signal gthReadSlaves : AxiLiteReadSlaveArray(JESD_LANE_C-1 downto 0);
constant DBG_CONFIG_C : AxiLiteCrossbarMasterConfigArray(JESD_LANE_C-1 downto 0) := genAxiLiteConfig(JESD_LANE_C, DBG_BASE_ADDR_C, 20, 16);
signal dbgWriteMasters : AxiLiteWriteMasterArray(JESD_LANE_C-1 downto 0);
signal dbgWriteSlaves : AxiLiteWriteSlaveArray(JESD_LANE_C-1 downto 0);
signal dbgReadMasters : AxiLiteReadMasterArray(JESD_LANE_C-1 downto 0);
signal dbgReadSlaves : AxiLiteReadSlaveArray(JESD_LANE_C-1 downto 0);
signal drpClk : slv(JESD_LANE_C-1 downto 0) := (others => '0');
signal drpRdy : slv(JESD_LANE_C-1 downto 0) := (others => '0');
signal drpEn : slv(JESD_LANE_C-1 downto 0) := (others => '0');
signal drpWe : slv(JESD_LANE_C-1 downto 0) := (others => '0');
signal drpAddr : slv(JESD_LANE_C*9-1 downto 0) := (others => '0');
signal drpDi : slv(JESD_LANE_C*16-1 downto 0) := (others => '0');
signal drpDo : slv(JESD_LANE_C*16-1 downto 0) := (others => '0');
signal rawAdcValids : slv(JESD_LANE_C-1 downto 0) := (others => '0');
signal rawAdcValues : sampleDataArray(JESD_LANE_C-1 downto 0) := (others => (others => '0'));
signal refClk : sl;
signal jesdSysRef : sl;
signal jesdRxSync : sl;
signal rxSyncReg : slv(3 downto 0);
signal adcRstL : sl;
signal lmkDataIn : sl;
signal lmkDataOut : sl;
signal spiCsL : slv(3 downto 0);
signal spiSck : slv(3 downto 0);
signal spiMosi : slv(3 downto 0);
signal spiBusy : sl;
signal spiBusyVec : slv(3 downto 0);
signal bufferEnable : sl := '0';
begin
adcRstL <= not(adcRst);
----------------------------------------------------------
-- Combine the JESD lanes together for LMFS = 4244
-- Note: Refer to Table 11 in datasheet
----------------------------------------------------------
-- CH[2*i+0] = DA1/DB1 (A2[15:8] A2[7:0] A3[15:8] A3[7:0])
-- CH[2*i+1] = DA2/DB2 (A0[15:8] A0[7:0] A1[15:8] A1[7:0])
----------------------------------------------------------
process(adcClk)
variable i : natural;
begin
if rising_edge(adcClk) then
for i in 7 downto 0 loop
adcValid(i) <= rawAdcValids(2*i+0) and rawAdcValids(2*i+1) after TPD_G;
adcData(i) <= rawAdcValues(2*i+0) & rawAdcValues(2*i+1) after TPD_G;
end loop;
if (swArmTrig = '1') then
bufferEnable <= '1' after TPD_G;
elsif (swTrigger = '1') then
bufferEnable <= '0' after TPD_G;
end if;
end if;
end process;
-----------
-- Clocking
-----------
U_lmkRefClk : entity work.ClkOutBufDiff
generic map (
TPD_G => TPD_G,
XIL_DEVICE_G => "ULTRASCALE")
port map (
clkIn => lmkRefClk,
clkOutP => lmkRefClkP,
clkOutN => lmkRefClkN);
U_IBUFDS_GTE3 : IBUFDS_GTE3
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O
REFCLK_ICNTL_RX => "00")
port map (
I => jesdClkP,
IB => jesdClkN,
CEB => '0',
ODIV2 => open,
O => refClk);
IBUFDS_SysRef : IBUFDS
port map (
I => jesdSysRefP,
IB => jesdSysRefN,
O => jesdSysRef);
GEN_SYNC : for i in 3 downto 0 generate
U_ODDR : ODDRE1
port map (
C => adcClk,
Q => rxSyncReg(i),
D1 => jesdRxSync,
D2 => jesdRxSync,
SR => '0');
U_OBUF : OBUF
port map (
I => rxSyncReg(i),
O => jesdSync(i));
end generate GEN_SYNC;
---------------------
-- AXI-Lite Crossbar
---------------------
U_XBAR : entity work.AxiLiteCrossbar
generic map (
TPD_G => TPD_G,
NUM_SLAVE_SLOTS_G => 1,
NUM_MASTER_SLOTS_G => NUM_AXI_MASTERS_C,
MASTERS_CONFIG_G => AXI_CONFIG_C)
port map (
axiClk => axilClk,
axiClkRst => axilRst,
sAxiWriteMasters(0) => axilWriteMaster,
sAxiWriteSlaves(0) => axilWriteSlave,
sAxiReadMasters(0) => axilReadMaster,
sAxiReadSlaves(0) => axilReadSlave,
mAxiWriteMasters => axilWriteMasters,
mAxiWriteSlaves => axilWriteSlaves,
mAxiReadMasters => axilReadMasters,
mAxiReadSlaves => axilReadSlaves);
-------------
-- JESD block
-------------
U_Jesd : entity work.FastAdcJesd204b
generic map (
TPD_G => TPD_G)
port map (
-- DRP Interface
drpClk => drpClk,
drpRdy => drpRdy,
drpEn => drpEn,
drpWe => drpWe,
drpAddr => drpAddr,
drpDi => drpDi,
drpDo => drpDo,
-- AXI interface
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => axilReadMasters(JESD_INDEX_C),
axilReadSlave => axilReadSlaves(JESD_INDEX_C),
axilWriteMaster => axilWriteMasters(JESD_INDEX_C),
axilWriteSlave => axilWriteSlaves(JESD_INDEX_C),
-- Sample data output (Use if external data acquisition core is attached)
dataValidVec_o => rawAdcValids,
sampleDataArr_o => rawAdcValues,
-------
-- JESD
-------
-- Clocks
stableClk => axilClk,
refClk => refClk,
devClk_i => adcClk,
devClk2_i => adcClk,
devRst_i => adcRst,
devClkActive_i => adcRstL,
-- GTH Ports
gtTxP => jesdTxP,
gtTxN => jesdTxN,
gtRxP => jesdRxP,
gtRxN => jesdRxN,
-- SYSREF for subclass 1 fixed latency
sysRef_i => jesdSysRef,
-- Synchronization output combined from all receivers to be connected to ADC chips
nSync_o => jesdRxSync);
-----------------
-- LMK SPI Module
-----------------
SPI_LMK : entity work.AxiSpiMaster
generic map (
TPD_G => TPD_G,
ADDRESS_SIZE_G => 15,
DATA_SIZE_G => 8,
CLK_PERIOD_G => (1.0/156.25E+6),
SPI_SCLK_PERIOD_G => 10.0E-6)
port map (
axiClk => axilClk,
axiRst => axilRst,
axiReadMaster => axilReadMasters(LMK_INDEX_C),
axiReadSlave => axilReadSlaves(LMK_INDEX_C),
axiWriteMaster => axilWriteMasters(LMK_INDEX_C),
axiWriteSlave => axilWriteSlaves(LMK_INDEX_C),
coreSclk => lmkSck,
coreSDin => lmkDataIn,
coreSDout => lmkDataOut,
coreCsb => lmkCsL);
IOBUF_Lmk : IOBUF
port map (
I => '0',
O => lmkDataIn,
IO => lmkSdio,
T => lmkDataOut);
lmkSync <= '0';
lmkRst <= axilRst;
----------------------
-- Fast ADC SPI Module
----------------------
GEN_ADC_SPI : for i in 3 downto 0 generate
U_SPI : entity work.ads54j60
generic map (
TPD_G => TPD_G,
CLK_PERIOD_G => (1.0/156.25E+6),
SPI_SCLK_PERIOD_G => 10.0E-6)
port map (
-- Clock and Reset
axiClk => axilClk,
axiRst => axilRst,
-- AXI-Lite Interface
axiReadMaster => axilReadMasters(SPI0_INDEX_C+i),
axiReadSlave => axilReadSlaves(SPI0_INDEX_C+i),
axiWriteMaster => axilWriteMasters(SPI0_INDEX_C+i),
axiWriteSlave => axilWriteSlaves(SPI0_INDEX_C+i),
-- SPI Interface
coreBusyIn => spiBusy,
coreBusyOut => spiBusyVec(i),
coreRst => fadcReset(i),
coreSclk => spiSck(i),
coreSDin => fadcSdout,
coreSDout => spiMosi(i),
coreCsb => spiCsL(i));
end generate GEN_ADC_SPI;
spiBusy <= uOr(spiBusyVec);
fadcPdn <= (others => '0');
fadcSen <= spiCsL;
process(spiCsL, spiMosi, spiSck)
begin
if spiCsL(0) = '0' then
fadcSclk <= spiSck(0);
fadcSdin <= spiMosi(0);
elsif spiCsL(1) = '0' then
fadcSclk <= spiSck(1);
fadcSdin <= spiMosi(1);
elsif spiCsL(2) = '0' then
fadcSclk <= spiSck(2);
fadcSdin <= spiMosi(2);
elsif spiCsL(3) = '0' then
fadcSclk <= spiSck(3);
fadcSdin <= spiMosi(3);
else
fadcSclk <= '0';
fadcSdin <= '0';
end if;
end process;
-----------------------
-- GTH's DRP Interfaces
-----------------------
U_GT_XBAR : entity work.AxiLiteCrossbar
generic map (
TPD_G => TPD_G,
NUM_SLAVE_SLOTS_G => 1,
NUM_MASTER_SLOTS_G => JESD_LANE_C,
MASTERS_CONFIG_G => GTH_CONFIG_C)
port map (
axiClk => axilClk,
axiClkRst => axilRst,
sAxiWriteMasters(0) => axilWriteMasters(GTH_INDEX_C),
sAxiWriteSlaves(0) => axilWriteSlaves(GTH_INDEX_C),
sAxiReadMasters(0) => axilReadMasters(GTH_INDEX_C),
sAxiReadSlaves(0) => axilReadSlaves(GTH_INDEX_C),
mAxiWriteMasters => gthWriteMasters,
mAxiWriteSlaves => gthWriteSlaves,
mAxiReadMasters => gthReadMasters,
mAxiReadSlaves => gthReadSlaves);
drpClk <= (others => axilClk);
GEN_GTH_DRP : for i in (JESD_LANE_C-1) downto 0 generate
U_AxiLiteToDrp : entity work.AxiLiteToDrp
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => true,
EN_ARBITRATION_G => false,
TIMEOUT_G => 4096,
ADDR_WIDTH_G => 9,
DATA_WIDTH_G => 16)
port map (
-- AXI-Lite Port
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => gthReadMasters(i),
axilReadSlave => gthReadSlaves(i),
axilWriteMaster => gthWriteMasters(i),
axilWriteSlave => gthWriteSlaves(i),
-- DRP Interface
drpClk => axilClk,
drpRst => axilRst,
drpRdy => drpRdy(i),
drpEn => drpEn(i),
drpWe => drpWe(i),
drpAddr => drpAddr((i*9)+8 downto (i*9)),
drpDi => drpDi((i*16)+15 downto (i*16)),
drpDo => drpDo((i*16)+15 downto (i*16)));
end generate GEN_GTH_DRP;
--------------------
-- Debug ADC Modules
--------------------
U_DBG_XBAR : entity work.AxiLiteCrossbar
generic map (
TPD_G => TPD_G,
NUM_SLAVE_SLOTS_G => 1,
NUM_MASTER_SLOTS_G => JESD_LANE_C,
MASTERS_CONFIG_G => DBG_CONFIG_C)
port map (
axiClk => axilClk,
axiClkRst => axilRst,
sAxiWriteMasters(0) => axilWriteMasters(DBG_INDEX_C),
sAxiWriteSlaves(0) => axilWriteSlaves(DBG_INDEX_C),
sAxiReadMasters(0) => axilReadMasters(DBG_INDEX_C),
sAxiReadSlaves(0) => axilReadSlaves(DBG_INDEX_C),
mAxiWriteMasters => dbgWriteMasters,
mAxiWriteSlaves => dbgWriteSlaves,
mAxiReadMasters => dbgReadMasters,
mAxiReadSlaves => dbgReadSlaves);
GEN_ADC_DEBUG :
for i in (JESD_LANE_C-1) downto 0 generate
RING_BUFFER : entity work.AxiLiteRingBuffer
generic map (
TPD_G => TPD_G,
BRAM_EN_G => true,
REG_EN_G => true,
DATA_WIDTH_G => 32,
RAM_ADDR_WIDTH_G => 10)
port map (
-- Data to store in ring buffer
dataClk => adcClk,
dataRst => adcRst,
dataValid => rawAdcValids(i),
dataValue => rawAdcValues(i),
bufferEnable => bufferEnable,
bufferClear => swArmTrig,
-- AXI-Lite interface for readout
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => dbgReadMasters(i),
axilReadSlave => dbgReadSlaves(i),
axilWriteMaster => dbgWriteMasters(i),
axilWriteSlave => dbgWriteSlaves(i));
end generate GEN_ADC_DEBUG;
end rtl;
|
<reponame>essess/legendary-octo-barnacle
---
-- Copyright (c) 2020 <NAME>. All rights reserved.
-- Developed by: <NAME> <<EMAIL>>
-- Refer to license terms in LICENSE; In the absence of such a file,
-- contact me at the above email address and I can provide you with one.
---
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
-- work.phy_pkg.all;
library osvvm;
context osvvm.osvvmcontext;
entity sym_to_chip_tb is
generic( tclk : time := 10 ns;
TPD : time := 0 ns );
end entity;
architecture dfault of sym_to_chip_tb is
signal clk, srst, sink_ready, source_ready, give, take, valid_in, valid_out : std_logic;
signal symbol : std_logic_vector(0 to 3);
signal chip_chunk : std_logic_vector(0 to 7);
signal dbgsig : std_logic := '0';
signal tstcnt : integer := 0;
begin
CreateReset( Reset => srst,
ResetActive => '1',
Clk => clk,
Period => 1*tclk,
tpd => tclk/2 );
CreateClock( Clk => clk,
Period => tclk );
dut : entity work.sym_to_chip
generic map( TPD => TPD )
port map( clk_in => clk,
srst_in => srst,
sink_valid_in => valid_in,
sink_ready_in => sink_ready,
sink_take_out => take,
symbol_in => symbol,
source_valid_out => valid_out,
source_ready_in => source_ready,
source_give_out => give,
chip_chunk_out => chip_chunk );
test : process
begin
WaitForLevel( srst, '0' );
wait until falling_edge( clk );
--<< drive
-- initial conditions
symbol <= b"0000";
valid_in <= '0';
sink_ready <= '0';
source_ready <= '0';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"11011001"; --< 0 to 7
assert valid_out = valid_in;
assert give = '0';
assert take = '0';
tstcnt <= tstcnt +1;
--<< drive
-- advance by one chunk
symbol <= b"0000";
valid_in <= '1';
sink_ready <= '1';
source_ready <= '1';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"11000011"; --< 8 to 15
assert valid_out = valid_in;
assert give = '1';
assert take = '0';
tstcnt <= tstcnt +1;
--<< drive
-- drive valid_in inactive and verify hold
symbol <= b"0000";
valid_in <= '0';
sink_ready <= '1';
source_ready <= '1';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"11000011"; --< 8 to 15 (held, but invalid)
assert valid_out = valid_in;
assert give = '0';
assert take = '0';
tstcnt <= tstcnt +1;
--<< drive
-- drive sink_ready inactive and verify hold
symbol <= b"0000";
valid_in <= '1';
sink_ready <= '1';
source_ready <= '0';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"11000011"; --< 8 to 15 (held and valid)
assert valid_out = valid_in;
assert give = '1';
assert take = '0';
tstcnt <= tstcnt +1;
--<< drive
-- advance by one chunk
symbol <= b"0000";
valid_in <= '1';
sink_ready <= '1';
source_ready <= '1';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"01010010"; --< 16 to 23
assert valid_out = valid_in;
assert give = '1';
assert take = '0';
tstcnt <= tstcnt +1;
--<< drive
-- advance to last chunk
symbol <= b"0000";
valid_in <= '1';
sink_ready <= '1';
source_ready <= '1';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"00101110"; --< 24 to 31
assert valid_out = valid_in;
assert give = '1';
assert take = '1';
tstcnt <= tstcnt +1;
-- repeat hold tests above
--<< drive
-- drive valid_in inactive and verify hold
symbol <= b"0000";
valid_in <= '0';
sink_ready <= '1';
source_ready <= '1';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"00101110"; --< 24 to 31 (held, but invalid)
assert valid_out = valid_in;
assert give = '0';
assert take = '0';
tstcnt <= tstcnt +1;
--<< drive
-- drive sink_ready inactive and verify hold
symbol <= b"0000";
valid_in <= '1';
sink_ready <= '1';
source_ready <= '0';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"00101110"; --< 24 to 31 (held and valid)
assert valid_out = valid_in;
assert give = '1';
assert take = '0';
tstcnt <= tstcnt +1;
--<< drive
-- one more, but the source isn't ready
symbol <= b"0000";
valid_in <= '1';
sink_ready <= '0';
source_ready <= '1';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"00101110"; --< 24 to 31 (held and valid)
assert valid_out = valid_in;
assert give = '0';
assert take = '1';
tstcnt <= tstcnt +1;
--<< drive
-- advance to first chunk of next symbol
symbol <= b"0001";
valid_in <= '1';
sink_ready <= '1';
source_ready <= '1';
wait until rising_edge( clk );
-->> verify
wait until falling_edge( clk );
assert chip_chunk = b"10001100"; --< 0 to 7
assert valid_out = valid_in;
assert give = '1';
assert take = '0';
tstcnt <= tstcnt +1;
-- verify rest of chips if desired ...
wait for 1*tclk;
report "DONE"; std.env.stop;
end process;
end architecture;
|
<gh_stars>1-10
-- Import libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Defining the entity ports
entity ULA is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Operation : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end ULA;
-- Começo da arquitetura
architecture Behavioral of ULA is
-- Componente AND de 4 bits
component AND_4BIT
port (
x: in STD_LOGIC_VECTOR (3 downto 0);
y: in STD_LOGIC_VECTOR (3 downto 0);
z: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- Componente comparador de 4 bits
component COMPARADOR_4BITS
port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Gout : out STD_LOGIC;
Eout : out STD_LOGIC;
Sout : out STD_LOGIC
);
end component;
-- Componente complementador de 4 bits
component COMPLEMENTADOR_4BITS
port (
I : in STD_LOGIC_VECTOR (3 downto 0);
K : in STD_LOGIC;
Z : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- Componente somador de 4 bits
component FULL_ADDER_4BITS
port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC
);
end component;
-- Componente multiplicador de 4 bits
component MULTIPLICADOR_4BITS
port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- Componente OR de 4 bits
component OR_4BITS
port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- Componente XOR de 4 bits
component XOR_4BITS
port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
-- Signals
signal Not_A, Compl_A, A_plus_B, A_times_B, Not_B, A_minus_B, A_and_B, A_xor_B, A_or_B, A_compare_B : STD_LOGIC_VECTOR (3 downto 0);
-- Comportamento da ULA
begin
-- Declarando os componentes
U1: COMPLEMENTADOR_4BITS port map (A, '1', Not_A); -- Para operação 1
U2: FULL_ADDER_4BITS port map (Not_A, "0000", '1', Compl_A); -- Para operação 1
U3: FULL_ADDER_4BITS port map (A, B, '0', A_plus_B); -- Para operação 2
U4: MULTIPLICADOR_4BITS port map (A, B, A_times_B); -- Para operação 3
U5: COMPLEMENTADOR_4BITS port map (B, '1', Not_B); -- Para operação 4
U6: FULL_ADDER_4BITS port map (A, Not_B, '1', A_minus_B); -- Para operação 4
U7: AND_4BIT port map (A, B, A_and_B); -- Para operação 5
U8: XOR_4BITS port map (A, B, A_xor_B); -- Para operação 6
U9: OR_4BITS port map (A, B, A_or_B); -- Para operação 7
U10: COMPARADOR_4BITS port map (A, B, A_compare_B(2), A_compare_B(1), A_compare_B(0)); -- Para operação 8
A_compare_B(3) <= '0'; -- Para operação 8
-- Dando as saídas baseadas na escolha da operação
process (Operation, Compl_A, A_plus_B, A_times_B, A_minus_B, A_and_B, A_xor_B, A_or_B, A_compare_B)
begin
case Operation is
when "0000" =>
Z <= Compl_A;
when "1000" =>
Z <= Compl_A;
when "0001" =>
Z <= A_plus_B;
when "1001" =>
Z <= A_plus_B;
when "0010" =>
Z <= A_times_B;
when "1010" =>
Z <= A_times_B;
when "0011" =>
Z <= A_minus_B;
when "1011" =>
Z <= A_minus_B;
when "0100" =>
Z <= A_and_B;
when "1100" =>
Z <= A_and_B;
when "0101" =>
Z <= A_xor_B;
when "1101" =>
Z <= A_xor_B;
when "0110" =>
Z <= A_or_B;
when "1110" =>
Z <= A_or_B;
when "0111" =>
Z <= A_compare_B;
when "1111" =>
Z <= A_compare_B;
when others =>
Z <= "0000";
end case;
end process;
end Behavioral;
|
--
-- Copyright 2019 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- The patent license granted to you in Section 3 of the License, as applied
-- to the "Work," hereby includes implementations of the Work in physical form.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- The background Specification upon which this is based is managed by and available from
-- the OpenCAPI Consortium. More information can be found at https://opencapi.org.
--
library ieee, support, ibm, work;
use ieee.std_logic_1164.all;
use ibm.std_ulogic_unsigned.all;
use ibm.std_ulogic_function_support.all;
use ibm.std_ulogic_support.all;
use work.axi_pkg.all;
entity ocx_dlx_tlx_stage is
port (
---------------------------------------------------------------------------
-- Clocking
---------------------------------------------------------------------------
opt_gckn : in std_ulogic;
tlx_dlx_flit : IN std_ulogic_vector(511 downto 0);
tlx_dlx_flit_valid : IN std_ulogic;
---------------------------------------------------------------------------
-- RX Interface
---------------------------------------------------------------------------
i_dlx_tlx_flit_valid : in std_ulogic;
i_dlx_tlx_flit : in std_ulogic_vector(511 downto 0);
i_dlx_tlx_flit_crc_err : in std_ulogic;
i_dlx_tlx_link_up : in std_ulogic;
-- Interface to TLx
dlx_tlx_flit_valid : out std_ulogic;
dlx_tlx_flit : out std_ulogic_vector(511 downto 0);
dlx_tlx_flit_crc_err : out std_ulogic;
dlx_tlx_link_up : out std_ulogic
);
end ocx_dlx_tlx_stage;
architecture ocx_dlx_tlx_stage of ocx_dlx_tlx_stage is
signal tlx_dlx_flit_q : std_ulogic_vector(511 downto 0);
signal tlx_dlx_flit_valid_q : std_ulogic;
signal dlx_tlx_flit_valid_q : std_ulogic;
signal dlx_tlx_flit_q : std_ulogic_vector(511 downto 0);
signal dlx_tlx_flit_crc_err_q : std_ulogic;
signal dlx_tlx_link_up_q : std_ulogic;
signal dlx_tlx_flit_valid_qq : std_ulogic;
signal dlx_tlx_flit_qq : std_ulogic_vector(511 downto 0);
signal dlx_tlx_flit_crc_err_qq : std_ulogic;
signal dlx_tlx_link_up_qq : std_ulogic;
attribute keep : string;
attribute mark_debug : string;
attribute mark_debug of tlx_dlx_flit_q : signal is "true";
attribute mark_debug of tlx_dlx_flit_valid_q : signal is "true";
attribute keep of tlx_dlx_flit_q : signal is "true";
attribute keep of tlx_dlx_flit_valid_q : signal is "true";
begin
dlx_tlx_flit_valid <= dlx_tlx_flit_valid_qq;
dlx_tlx_flit <= dlx_tlx_flit_qq;
dlx_tlx_flit_crc_err <= dlx_tlx_flit_crc_err_qq;
dlx_tlx_link_up <= dlx_tlx_link_up_qq;
process (opt_gckn)
begin
if opt_gckn'event and opt_gckn = '1' then
dlx_tlx_flit_valid_q <= i_dlx_tlx_flit_valid;
dlx_tlx_flit_q <= i_dlx_tlx_flit;
dlx_tlx_flit_crc_err_q <= i_dlx_tlx_flit_crc_err;
dlx_tlx_link_up_q <= i_dlx_tlx_link_up;
dlx_tlx_flit_valid_qq <= dlx_tlx_flit_valid_q;
dlx_tlx_flit_qq <= dlx_tlx_flit_q;
dlx_tlx_flit_crc_err_qq <= dlx_tlx_flit_crc_err_q;
dlx_tlx_link_up_qq <= dlx_tlx_link_up_q;
tlx_dlx_flit_q <= tlx_dlx_flit;
tlx_dlx_flit_valid_q <= tlx_dlx_flit_valid;
end if;
end process;
end ocx_dlx_tlx_stage;
|
<reponame>dat4087/System-Designers-Guide-to-VHDL-AMS
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Constant Voltage Source (Includes Frequency Domain settings)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_constant IS
-- Initialize parameters
GENERIC (
level : VOLTAGE; -- Constant voltage value (V)
ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
ac_phase : real := 0.0); -- AC phase (degrees)
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_constant;
-- Ideal Architecture (I = constant)
ARCHITECTURE ideal OF v_constant IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
v == level;
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- C:\Rehan\Cs5\design_definition\hdl\vhdl\switch_dig_log.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity switch_dig_log is
generic
(
trans_time : real := 1.0e-9;
r_closed : resistance := 1.0e-3;
r_open : resistance := 1.0e6
);
port
(
terminal p1 : electrical ;
sw_state : in std_logic ;
terminal p2 : electrical
);
begin
end switch_dig_log ;
-----------------------------------------------------------------------------------------
architecture linear of switch_dig_log is
signal r_sig : resistance := r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
r_sig <= r_open;
elsif (sw_state'event and sw_state = '1') then
r_sig <= r_closed;
end if;
end process DetectState;
-- Characteristic equations
r == r_sig'ramp(trans_time, trans_time);
v == r*i;
end architecture linear;
-------------------------------------------------------------------------------------------
architecture log of switch_dig_log is
constant log10_r_open : real := log10(r_open);
constant log10_r_closed : real := log10(r_closed);
signal log10_r_sig : resistance := log10_r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
quantity log10_r : real;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
log10_r_sig <= log10_r_open;
elsif (sw_state'event and sw_state = '1') then
log10_r_sig <= log10_r_closed;
end if;
end process DetectState;
-- Characteristic equations
log10_r == log10_r_sig'ramp(trans_time, trans_time);
r == 10**log10_r;
v == r*i;
end architecture log;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : opamp.vhd
-- Author : <NAME>
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: 3-pin OpAmp model with behavioral architecture
-- Uses Q'LTF function to define open-loop response
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity opamp is
-- Initialize parameters
generic (rin : resistance := 1.0e6; -- Input resistance [Ohms]
rout : resistance := 100.0; -- Output resistance (Ohms]
avol : real := 100.0e3; -- Open loop gain
f_0dB : real := 1.0e6 -- Unity Gain Frequency [Hz]
);
-- Define ports as electrical terminals
port (
terminal in_pos, in_neg, output : electrical);
end entity opamp;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Characteristics modeled:
-- 1. Open loop gain
-- 2. Frequency characteristics (single pole response)
-- 3. Input and output resistance
-- Uses Q'Ltf function to create open loop gain and roll off
-------------------------------------------------------------------------------
architecture basic of opamp is
-- Declare constants
constant f_3db : real := f_0db / avol; -- -3dB frequency
constant w_3dB : real := math_2_pi*f_3dB; -- -3dB freq in radians
-- Numerator and denominator for Q'LTF function
constant num : real_vector := (0 => avol);
constant den : real_vector := (1.0, 1.0/w_3dB);
-- Declare input and output quantities
quantity v_in across i_in through in_pos to in_neg;
quantity v_out across i_out through output;
begin -- ARCHITECTURE basic
i_in == v_in / rin; -- input current
v_out == v_in'ltf(num, den) + i_out*rout; -- output voltage
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : comparator_d.vhd
-- Author : Mentor Graphics
-- Created : 2001/08/03
-- Last update: 2001/08/03
-------------------------------------------------------------------------------
-- Description: Voltage comparator with digital output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/08/03 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use IEEE natures and packages
library IEEE;
use ieee.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
use IEEE_proposed.ENERGY_SYSTEMS.all;
entity comparator_d is
port (
terminal in_pos : electrical;
terminal in_neg : electrical;
signal output : out std_logic := '1' -- Digital output
);
end comparator_d;
-------------------------------------------------------------------------------
-- Behavioral architecture
-------------------------------------------------------------------------------
architecture behavioral of comparator_d is
quantity Vin across in_pos;
quantity Vref across in_neg;
begin -- behavioral
-- purpose: Detect threshold crossing and assign event on output
-- type : combinational
-- inputs : vin'above(thres)
-- outputs: pulse_signal
process (Vin'above(Vref)) is
begin -- PROCESS
if Vin'above(Vref) then
output <= '1' after 1us;
else
output <= '0' after 1us;
end if;
end process;
end behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : <NAME>
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pwm_mac is
port(
terminal inp : electrical;
terminal inm : electrical;
dig_out : out std_logic
);
end pwm_mac;
architecture pwm_mac of pwm_mac is
-- Component declarations
-- Signal declarations
terminal cmp_in : electrical;
terminal plse_in : electrical;
terminal XSIG010002 : electrical;
terminal XSIG010003 : electrical;
begin
-- Signal assignments
-- Component instances
U1 : entity work.opamp(basic)
port map(
in_neg => XSIG010002,
in_pos => inm,
output => cmp_in
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => XSIG010002,
p2 => cmp_in
);
v2 : entity work.v_constant(ideal)
generic map(
level => 0.0
)
port map(
pos => XSIG010003,
neg => ELECTRICAL_REF
);
R2 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => plse_in,
p2 => XSIG010002
);
R3 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => inp,
p2 => XSIG010002
);
XCMP4 : entity work.comparator_d(behavioral)
port map(
output => dig_out,
in_pos => XSIG010003,
in_neg => cmp_in
);
v9 : entity work.v_pulse(ideal)
generic map(
initial => -4.7,
pulse => 4.7,
ti2p => 200 us,
tp2i => 200 us,
delay => 1 us,
width => 1 us,
period => 405 us
)
port map(
pos => plse_in,
neg => ELECTRICAL_REF
);
end pwm_mac;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : prop_pwl.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Propeller Load (Rotational_V domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
package pwl_functions is
function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real;
end package pwl_functions;
package body pwl_functions is
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "extrapolate: x1 cannot be equal to x2"
severity error;
assert (x <= x1) or (x >= x2)
report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
severity warning;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function extrapolate;
-- Created a new pwl_dim1_extrap function that returns extrapolated yvalue for "out-of-range" x value.
function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x <= xdata(0) then
yvalue := extrapolate(x,ydata(1),ydata(0),xdata(1),xdata(0));
return yvalue;
end if;
if x >= xdata(xdata'right) then
yvalue := extrapolate(x,ydata(ydata'right),ydata(ydata'right-1),xdata(xdata'right),xdata(xdata'right-1));
return yvalue;
end if;
start:=0;
fin:=xdata'right;
-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
-- so fin==n-1 in C terms (where n is the size of the array).
while start <=fin loop
mid:=(start+fin)/2;
if xdata(mid) < x
then start:=mid+1;
else fin:=mid-1;
end if;
end loop;
if xdata(mid) > x
then mid:=mid-1;
end if;
yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
return yvalue;
end function pwl_dim1_extrap;
end package body pwl_functions;
library IEEE_proposed; use IEEE_proposed.mechanical_systems.all;
library ieee; use ieee.math_real.all;
use work.pwl_functions.all;
entity prop_pwl is
generic (
ydata : real_vector; -- torque data
xdata : real_vector -- velocity data
);
port (terminal shaft1 : rotational_v);
end entity prop_pwl;
architecture ideal of prop_pwl is
quantity w across torq through shaft1 to rotational_v_ref;
begin
torq == pwl_dim1_extrap(w, xdata, ydata);
end architecture ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : diode_pwl.vhd
-- Author : <NAME>
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Diode model with ideal architecture
-- Currently no Generics due to bug in DV
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
use IEEE_proposed.energy_systems.all;
ENTITY diode_pwl IS
GENERIC (
ron : real; -- equivalent series resistance
roff : real); -- leakage resistance
PORT (
TERMINAL p, -- positive pin
m : electrical); -- minus pin
END ENTITY diode_pwl;
ARCHITECTURE simple OF diode_pwl IS
QUANTITY v across i through p TO m;
BEGIN -- simple ARCHITECTURE
if v'Above(0.0) use
i == v/ron;
elsif not v'Above(0.0) use
i == v/roff;
else
i == 0.0;
end use;
break on v'Above(0.0);
END ARCHITECTURE simple;
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical sinusoidal voltage source (v_sine.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_sine IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_sine;
-- Ideal Architecture
ARCHITECTURE ideal OF v_sine IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS5_Prop is
end tb_CS5_Prop;
architecture TB_CS5_Prop of tb_CS5_Prop is
-- Component declarations
-- Signal declarations
terminal prop : rotational_v;
terminal prop_amp_in : electrical;
terminal prop_mtr_in : electrical;
terminal prop_pwr : electrical;
signal pwm_out : std_logic;
begin
-- Signal assignments
-- Component instances
motor2 : entity work.DC_Motor(basic)
generic map(
kt => 30.1e-3,
l => 40.0e-6,
d => 5.63e-12,
j => 315.0e-6,
r_wind => 0.16
)
port map(
p1 => prop_mtr_in,
p2 => ELECTRICAL_REF,
shaft_rotv => prop
);
v4 : entity work.v_constant(ideal)
generic map(
level => 42.0
)
port map(
pos => prop_pwr,
neg => ELECTRICAL_REF
);
sw2 : entity work.switch_dig_log
port map(
sw_state => pwm_out,
p2 => prop_mtr_in,
p1 => prop_pwr
);
pwm1 : entity work.pwm_mac
port map(
inp => prop_amp_in,
dig_out => pwm_out,
inm => ELECTRICAL_REF
);
XCMP37 : entity work.prop_pwl(ideal)
generic map(
ydata => (0.233, 0.2865, 0.347, 0.4138, 0.485, 0.563, 0.645, 0.735, 0.830, 0.93, 1.08),
xdata => (471.2, 523.6, 576.0, 628.3, 680.7, 733.0, 785.4, 837.7, 890.0, 942.5, 994.8)
)
port map(
shaft1 => prop
);
D4 : entity work.diode_pwl(simple)
generic map(
ron => 0.001,
roff => 100.0e3
)
port map(
p => ELECTRICAL_REF,
m => prop_mtr_in
);
v8 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 2.3,
phase => 0.0,
offset => 2.3
)
port map(
pos => prop_amp_in,
neg => ELECTRICAL_REF
);
end TB_CS5_Prop;
--
|
<filename>cnn/utils/conv_image.vhd
LIBRARY IEEE;
LIBRARY work;
USE IEEE.fixed_float_types.ALL;
USE IEEE.fixed_pkg.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY convolut_image IS
GENERIC (FILTER_SIZE : INTEGER := 3;IMG_SIZE : INTEGER := 5);
PORT(
IMG : IN STD_LOGIC_VECTOR(IMG_SIZE*IMG_SIZE*16-1 DOWNTO 0);
FILTER1 : IN STD_LOGIC_VECTOR(FILTER_SIZE*FILTER_SIZE*16-1 DOWNTO 0);
convoluted_img : OUT STD_LOGIC_VECTOR((IMG_SIZE-FILTER_SIZE+1)*(IMG_SIZE-FILTER_SIZE+1)*16-1 DOWNTO 0);
end_conv :OUT STD_LOGIC;
clk,strat_signal,rst:IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE conv_image_arch OF convolut_image IS
COMPONENT conv_wimdow_1 IS
GENERIC (FILTER_SIZE : INTEGER);
PORT(
WINDOW : IN STD_LOGIC_VECTOR(FILTER_SIZE*FILTER_SIZE*16-1 DOWNTO 0);
FILTER : IN STD_LOGIC_VECTOR(FILTER_SIZE*FILTER_SIZE*16-1 DOWNTO 0);
PIXEL_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
end_conv :OUT STD_LOGIC;
clk,strat_signal,rst:IN STD_LOGIC
);
END COMPONENT;
COMPONENT extract_window IS
GENERIC(FILTER_SIZE : INTEGER ;IMG_SIZE : INTEGER);
PORT(
IMG : IN STD_LOGIC_VECTOR(IMG_SIZE*IMG_SIZE*16-1 DOWNTO 0);
IMG_SIZE_in:IN INTEGER;
FILTER_SIZE_in:IN INTEGER;
rst:IN STD_LOGIC;
OFFSET:IN INTEGER;
LAYER : OUT STD_LOGIC_VECTOR(FILTER_SIZE*FILTER_SIZE*16-1 DOWNTO 0)
);
END COMPONENT;
TYPE conv_type IS ARRAY(0 TO (IMG_SIZE-FILTER_SIZE+1)*(IMG_SIZE-FILTER_SIZE+1)-1)OF STD_LOGIC_VECTOR(FILTER_SIZE*FILTER_SIZE*16-1 DOWNTO 0);
SIGNAL WINDOW : conv_type;
SIGNAL y: STD_LOGIC_VECTOR((IMG_SIZE-FILTER_SIZE+1)*(IMG_SIZE-FILTER_SIZE+1)*16-1 DOWNTO 0);
TYPE OFFSSET_type IS ARRAY(0 TO (IMG_SIZE-FILTER_SIZE+1)*(IMG_SIZE-FILTER_SIZE+1)-1) OF unsigned(9 DOWNTO 0);
SIGNAL OFFSSET : OFFSSET_type ;
BEGIN
OFFSSET(0)<=(OTHERS =>'0');
loop0: FOR i IN 1 TO (IMG_SIZE-FILTER_SIZE+1)*(IMG_SIZE-FILTER_SIZE+1)-1 GENERATE
OFFSSET(i) <= OFFSSET(i-1)+to_unsigned(FILTER_SIZE,10) when ( (to_integer(OFFSSET(i-1))+FILTER_SIZE )mod IMG_SIZE)=0 ELSE
OFFSSET(i-1)+"0000000001" ;
END GENERATE;
loop1: FOR i IN 0 TO (IMG_SIZE-FILTER_SIZE+1)*(IMG_SIZE-FILTER_SIZE+1)-1 GENERATE
fx0:extract_window GENERIC MAP (FILTER_SIZE,IMG_SIZE)PORT MAP(IMG,IMG_SIZE,FILTER_SIZE,rst,to_integer(OFFSSET(i)),WINDOW(i));
fx1:conv_wimdow_1 GENERIC MAP (FILTER_SIZE) PORT MAP(WINDOW(i),
FILTER1,convoluted_img(i*16+15 DOWNTO i*16),end_conv,clk,strat_signal,rst);
END GENERATE;
END conv_image_arch;
|
<filename>src/Memory.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Common.all;
entity Memory is
port (
-- Interface --
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
rw: in RwType;
length: in LenType;
addr: in Int32;
data_in: in Int32;
data_out: out Int32;
completed: out std_logic;
int_com: out std_logic;
-- Import --
ram1_en: out std_logic;
ram1_oe: out std_logic;
ram1_rw: out std_logic;
ram1_data: inout Int16;
ram1_addr: out Int18;
ram2_en: out std_logic;
ram2_oe: out std_logic;
ram2_rw: out std_logic;
ram2_data: inout Int16;
ram2_addr: out Int18;
com_ready: in std_logic;
com_rdn: out std_logic;
com_wrn: out std_logic;
com_tbre: in std_logic;
com_tsre: in std_logic;
flash_byte: out std_logic;
flash_vpen: out std_logic;
flash_ce: out std_logic;
flash_oe: out std_logic;
flash_we: out std_logic;
flash_rp: out std_logic;
flash_data: inout Int16;
flash_addr: out Int23;
-- Debug --
seg7_r_num: out Int4
);
end Memory;
architecture Behavioral of Memory is
component Rom
port (
addr: in Int10;
data: out Int32
);
end component;
type StateType is (
INITIAL,
STOPPED,
RAM_READ,
RAM_WRITE,
RAM_WRITE_BYTE_1,
RAM_WRITE_BYTE_2,
COM_READ,
COM_WRITE,
COM_WRITE_1,
FLASH_READ,
FLASH_READ_1,
FLASH_WRITE
);
procedure print_state(
signal state: in StateType;
signal seg7_r_num: out Int4) is
begin
case state is
when INITIAL =>
seg7_r_num <= std_logic_vector(to_signed(0, 4));
when STOPPED =>
seg7_r_num <= std_logic_vector(to_signed(1, 4));
when RAM_READ =>
seg7_r_num <= std_logic_vector(to_signed(2, 4));
when RAM_WRITE =>
seg7_r_num <= std_logic_vector(to_signed(3, 4));
when RAM_WRITE_BYTE_1 =>
seg7_r_num <= std_logic_vector(to_signed(4, 4));
when RAM_WRITE_BYTE_2 =>
seg7_r_num <= std_logic_vector(to_signed(5, 4));
when COM_READ =>
seg7_r_num <= std_logic_vector(to_signed(6, 4));
when COM_WRITE =>
seg7_r_num <= std_logic_vector(to_signed(7, 4));
when FLASH_READ =>
seg7_r_num <= std_logic_vector(to_signed(8, 4));
when FLASH_WRITE =>
seg7_r_num <= std_logic_vector(to_signed(9, 4));
when others =>
seg7_r_num <= std_logic_vector(to_signed(15, 4));
end case;
end;
procedure rom_read(
signal data_out: out Int32;
signal rom_data: in Int32;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
data_out <= rom_data;
completed <= '1';
state <= STOPPED;
when others =>
end case;
end;
procedure ram_read(
signal length: in LenType;
signal addr: in Int32;
signal data_out: out Int32;
signal ram1_en: out std_logic;
signal ram1_oe: out std_logic;
signal ram1_rw: out std_logic;
signal ram1_data: inout Int16;
signal ram2_en: out std_logic;
signal ram2_oe: out std_logic;
signal ram2_rw: out std_logic;
signal ram2_data: inout Int16;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
ram1_en <= '0';
ram2_en <= '0';
ram1_oe <= '0';
ram2_oe <= '0';
ram1_rw <= '1';
ram2_rw <= '1';
ram1_data <= Int16_Z;
ram2_data <= Int16_Z;
state <= RAM_READ;
when RAM_READ =>
if length = Lword then
data_out(15 downto 0) <= ram1_data;
data_out(31 downto 16) <= ram2_data;
elsif length = Lhalf then
data_out(31 downto 16) <= Int16_Zero;
if addr(1) = '0' then
data_out(15 downto 0) <= ram1_data;
else
data_out(15 downto 0) <= ram2_data;
end if;
elsif length = Lbyte then
data_out(31 downto 8) <= Int16_Zero & Int8_Zero;
if addr(1) = '0' then
if addr(0) = '0' then
data_out(7 downto 0) <= ram1_data(7 downto 0);
else
data_out(7 downto 0) <= ram1_data(15 downto 8);
end if;
else
if addr(0) = '0' then
data_out(7 downto 0) <= ram2_data(7 downto 0);
else
data_out(7 downto 0) <= ram2_data(15 downto 8);
end if;
end if;
end if;
completed <= '1';
state <= STOPPED;
when others =>
end case;
end;
procedure ram_write(
signal length: in LenType;
signal addr: in Int32;
signal data_in: in Int32;
signal ram1_en: out std_logic;
signal ram1_oe: out std_logic;
signal ram1_rw: out std_logic;
signal ram1_data: inout Int16;
signal ram2_en: out std_logic;
signal ram2_oe: out std_logic;
signal ram2_rw: out std_logic;
signal ram2_data: inout Int16;
signal data_byte_temp: inout Int16;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
ram1_en <= '0';
ram2_en <= '0';
-- Write ram
if length = Lword then
ram1_oe <= '1';
ram2_oe <= '1';
ram1_rw <= '0';
ram2_rw <= '0';
ram1_data <= data_in(15 downto 0);
ram2_data <= data_in(31 downto 16);
state <= RAM_WRITE;
elsif length = Lhalf then
if addr(1) = '0' then
ram1_oe <= '1';
ram1_rw <= '0';
ram1_data <= data_in(15 downto 0);
else
ram2_oe <= '1';
ram2_rw <= '0';
ram2_data <= data_in(15 downto 0);
end if;
state <= RAM_WRITE;
elsif length = Lbyte then
ram1_oe <= '0';
ram2_oe <= '0';
ram1_rw <= '1';
ram2_rw <= '1';
ram1_data <= Int16_Z;
ram2_data <= Int16_Z;
state <= RAM_WRITE_BYTE_1;
end if;
when RAM_WRITE =>
ram1_rw <= '1';
ram2_rw <= '1';
completed <= '1';
state <= STOPPED;
when RAM_WRITE_BYTE_1 =>
if addr(1) = '0' then
data_byte_temp <= ram1_data;
else
data_byte_temp <= ram2_data;
end if;
state <= RAM_WRITE_BYTE_2;
when RAM_WRITE_BYTE_2 =>
if addr(1) = '0' then
ram1_oe <= '1';
ram1_rw <= '0';
if addr(0) = '0' then
ram1_data(7 downto 0) <= data_in(7 downto 0);
ram1_data(15 downto 8) <= data_byte_temp(15 downto 8);
else
ram1_data(7 downto 0) <= data_byte_temp(7 downto 0);
ram1_data(15 downto 8) <= data_in(7 downto 0);
end if;
else
ram2_oe <= '1';
ram2_rw <= '0';
if addr(0) = '0' then
ram2_data(7 downto 0) <= data_in(7 downto 0);
ram2_data(15 downto 8) <= data_byte_temp(15 downto 8);
else
ram2_data(7 downto 0) <= data_byte_temp(7 downto 0);
ram2_data(15 downto 8) <= data_in(7 downto 0);
end if;
end if;
state <= RAM_WRITE;
when others =>
end case;
end;
procedure com_status(
signal com_ready: in std_logic;
signal com_tbre: in std_logic;
signal com_tsre: in std_logic;
signal data_out: out Int32;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
data_out(0) <= com_tbre and com_tsre;
data_out(1) <= com_ready;
data_out(31 downto 2) <= Int30_Zero;
completed <= '1';
state <= STOPPED;
when others =>
end case;
end;
procedure com_read(
signal com_ready: in std_logic;
signal com_rdn: out std_logic;
signal ram1_en: out std_logic;
signal ram1_oe: out std_logic;
signal com_data: inout Int8;
signal data_out: out Int32;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
ram1_en <= '1';
ram1_oe <= '1';
com_rdn <= '0';
com_data <= Int8_Z;
state <= COM_READ;
when COM_READ =>
com_rdn <= '1';
data_out(7 downto 0) <= com_data;
data_out(31 downto 8) <= Int24_Zero;
completed <= '1';
state <= STOPPED;
when others =>
end case;
end;
procedure com_write(
signal com_tbre: in std_logic;
signal com_tsre: in std_logic;
signal data_in: in Int32;
signal com_wrn: out std_logic;
signal ram1_en: out std_logic;
signal ram1_oe: out std_logic;
signal com_data: inout Int8;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
ram1_en <= '1';
ram1_oe <= '1';
com_data <= data_in(7 downto 0);
state <= COM_WRITE;
when COM_WRITE =>
com_wrn <= '0';
state <= COM_WRITE_1;
when COM_WRITE_1 =>
com_wrn <= '1';
completed <= '1';
state <= STOPPED;
when others =>
end case;
end;
procedure flash_read(
signal addr: in Int32;
signal data_out: out Int32;
signal flash_oe: out std_logic;
signal flash_we: out std_logic;
signal flash_data: inout Int16;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
flash_oe <= '0';
flash_we <= '1';
flash_data <= Int16_Z;
state <= FLASH_READ;
when FLASH_READ =>
state <= FLASH_READ_1;
when FLASH_READ_1 =>
data_out(15 downto 0) <= flash_data;
data_out(31 downto 16) <= Int16_Zero;
completed <= '1';
state <= STOPPED;
when others =>
end case;
end;
procedure flash_write(
signal addr: in Int32;
signal data_in: in Int32;
signal flash_oe: out std_logic;
signal flash_we: out std_logic;
signal flash_data: inout Int16;
signal state: inout StateType;
signal completed: out std_logic) is
begin
case state is
when INITIAL =>
flash_oe <= '1';
flash_we <= '0';
flash_data <= data_in(15 downto 0);
state <= FLASH_WRITE;
when FLASH_WRITE =>
flash_we <= '1';
completed <= '1';
state <= STOPPED;
when others =>
end case;
end;
signal state: StateType;
signal data_byte_temp: Int16;
signal rom_addr: Int10;
signal rom_data: Int32;
begin
flash_byte <= '1';
flash_vpen <= '1';
flash_ce <= '0';
flash_rp <= '1';
flash_addr <= addr(23 downto 1);
rom_addr <= addr(11 downto 2);
ram1_addr <= addr(19 downto 2);
ram2_addr <= addr(19 downto 2);
int_com <= com_ready;
rom_instance: Rom port map (
addr => rom_addr,
data => rom_data
);
process(clk, rst)
begin
if rst = '0' then
-- Reset
ram1_en <= '1';
ram2_en <= '1';
ram1_oe <= '1';
ram2_oe <= '1';
ram1_rw <= '1';
ram2_rw <= '1';
com_rdn <= '1';
com_wrn <= '1';
completed <= '0';
state <= STOPPED;
elsif rising_edge(clk) then
print_state(state, seg7_r_num); -- Debug --
if en = '1' then
state <= INITIAL;
completed <= '0';
else
if addr(31 downto 20) = x"000" then
--- SRAM ---
if rw = R then
ram_read(length, addr, data_out, ram1_en, ram1_oe, ram1_rw, ram1_data,
ram2_en, ram2_oe, ram2_rw, ram2_data, state, completed);
else
ram_write(length, addr, data_in, ram1_en, ram1_oe, ram1_rw, ram1_data,
ram2_en, ram2_oe, ram2_rw, ram2_data, data_byte_temp, state, completed);
end if;
elsif addr(31 downto 12) = x"1FC00" then
-- ROM --
if rw = R then
rom_read(data_out, rom_data, state, completed);
end if;
elsif addr = COM_Data_Addr then
-- COM --
if rw = R then
com_read(com_ready, com_rdn, ram1_en, ram1_oe, ram1_data(7 downto 0), data_out, state, completed);
else
com_write(com_tbre, com_tsre, data_in, com_wrn, ram1_en, ram1_oe, ram1_data(7 downto 0), state, completed);
end if;
elsif addr = COM_Stat_Addr then
-- COM Status --
if rw = R then
com_status(com_ready, com_tbre, com_tsre, data_out, state, completed);
end if;
elsif addr(31 downto 24) = x"1E" then
--- Flash ---
if rw = R then
flash_read(addr, data_out, flash_oe, flash_we, flash_data, state, completed);
else
flash_write(addr, data_in, flash_oe, flash_we, flash_data, state, completed);
end if;
end if;
end if; -- en
end if; -- clk
end process;
end Behavioral;
|
<reponame>kmalhan/floating_cordic_power<filename>Hardware/FloP_Multiplier.vhd
-- <NAME>, <NAME>, <NAME>, IREECE 2015
-- Basic Description:
-- Behavioral floating point multiplier that multiplies arbitrary floating point numbers.
-- Parameters:
-- Generics:
-- expWidth: the width of the exponent field
-- fracWidth: the width of the fractional field
-- Ports:
-- num1, num2: the two numbers being multiplied
-- clk: the clock signal required by nature of this behavioral implementation
-- product: num1 * num2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity FloP_Multiplier is
Generic ( expWidth : integer := 11; fracWidth : integer := 52 );
Port ( num1, num2 : in std_logic_vector(expWidth+fracWidth downto 0);
clk : in std_logic;
product : out std_logic_vector(expWidth+fracWidth downto 0));
end FloP_Multiplier;
architecture Behavioral of FloP_Multiplier is
constant expBias : integer := (2**(expWidth-1)-1);
signal signifProd : std_logic_vector(2*fracWidth+1 downto 0);
signal signifMSB : std_logic_vector(expWidth downto 0);
signal expSum : std_logic_vector(expWidth downto 0);
signal prodSign : std_logic;
begin
-- pos*pos => pos, etc.
prodSign <= num1(expWidth+fracWidth) xor num2(expWidth+fracWidth);
-- ((exp1 - bias) + (exp2 - bias)) + bias = (exp1 + exp2 - bias). signifMSB is for if 1.num1*1.num2 >= 2 => requires shifting.
signifMSB <= (0 => signifProd(2*fracWidth+1), others => '0');
expSum <= std_logic_vector(unsigned(num1(expWidth+fracWidth-1 downto fracWidth)) + unsigned(num2(expWidth+fracWidth-1 downto fracWidth)) - to_unsigned(expBias, expWidth+1) + unsigned(signifMSB));
-- (fracWidth downto 0) * (fracWidth downto 0) size multiplication produces a (2*fracWidth+1 downto 0) size vector
signifProd <= std_logic_vector(unsigned('1' & num1(fracWidth-1 downto 0)) * unsigned('1' & num2(fracWidth-1 downto 0)));
p1 : process(clk) begin
if rising_edge(clk) then
-- If num1 = 0 or num2 = 0...
if num1 = std_logic_vector(to_unsigned(0, expWidth+fracWidth+1)) or num2 = std_logic_vector(to_unsigned(0, expWidth+fracWidth+1)) then
-- Their product is 0
product <= (others => '0');
-- Otherwise...
else
-- If MSB(signifProd) = 1, then
case signifProd(2*fracWidth+1) is
-- There needs to be a bit of shifting because the exponent increased by one
when '1' => product <= (prodSign & expSum(expWidth-1 downto 0) & signifProd(2*fracWidth downto fracWidth+1));
-- Otherwise, no normalization/shifting is required
when others => product <= (prodSign & expSum(expWidth-1 downto 0) & signifProd(2*fracWidth-1 downto fracWidth));
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- icap_statemachine.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: icap_statemachine.vhd
-- Version : v7.01a
-- Description: This module genrates the ce, we signals to ICAP
-- based on busy signal,control register & FIFO flags
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- -- Generics
-- ICAP_DWIDTH -- Icap Data Width;
-- C_FAMILY -- Family of FPGA
-- -- Inputs
-- Clk -- Clock
-- Rst -- Reset
-- Wrfifo_dataout -- Write fifo data read
-- Icap_dataout -- ICAP data out
-- Wrfifo_empty -- Write fifo empty
-- Wrfifo_full -- Write fifo full
-- Rdfifo_empty -- Read fifo empty
-- Rdfifo_full -- Read fifo full
-- Icap_busy -- ICAP busy
-- Rnc -- Read not configuration
-- Size -- Size of data transfer in words
-- -- Outputs
-- Wrfifo_rden -- Write fifo read enable
-- Rdfifo_wren -- Read fifo write enable
-- Icap_ce -- ICAP chip enable
-- Icap_we -- ICAP write eneble
-- Send_done -- Read done
-- Reset_cr -- Reset the control register
-- Icap_datain -- ICAP data in
-- Rdfifo_datain -- Read fifo data in
-------------------------------------------------------------------------------
entity icap_statemachine is
generic (
ICAP_DWIDTH : integer := 16;
C_MODE : integer := 0;
C_FAMILY : string := "virtex7");
port (
Clk : in std_logic;
Rst : in std_logic;
Wrfifo_dataout : in std_logic_vector(0 to ICAP_DWIDTH-1);
Icap_dataout : in std_logic_vector(0 to ICAP_DWIDTH-1);
Wrfifo_full : in std_logic;
Wrfifo_empty : in std_logic;
Rdfifo_empty : in std_logic;
Rdfifo_full : in std_logic;
Icap_busy : in std_logic;
Rnc : in std_logic_vector(0 to 1);
Abort : in std_logic;
Size : in std_logic_vector(0 to 11);
Status_read : in std_logic;
Size_counter : out std_logic_vector(0 to 11);
Wrfifo_rden : out std_logic;
Rdfifo_wren : out std_logic;
Icap_ce : out std_logic;
Icap_we : out std_logic;
Send_done : out std_logic;
Reset_cr : out std_logic;
Abort_in_progress : out std_logic;
Hang_status : out std_logic;
Icap_status : out std_logic_vector(0 to 31);
Icap_datain : out std_logic_vector(0 to ICAP_DWIDTH-1);
Rdfifo_datain : out std_logic_vector(0 to ICAP_DWIDTH-1)
);
attribute KEEP : string;
attribute KEEP of Icap_ce : signal is "TRUE";
attribute KEEP of Icap_we : signal is "TRUE";
attribute KEEP of Icap_datain : signal is "TRUE";
attribute KEEP of Icap_dataout : signal is "TRUE";
attribute KEEP of Icap_busy : signal is "TRUE";
end entity icap_statemachine;
architecture imp of icap_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute mark_debug : string;
-- icap state machine
type SM_TYPE is (ICAP_IDLE,ICAP_WRITE1,ICAP_WRITE2,ICAP_WRITE3,ICAP_WRITE4,
ICAP_WRITE5,ICAP_READ1,ICAP_ABORT0,ICAP_ABORT_HANG,ICAP_ABORT1,ICAP_ABORT2,
ICAP_ABORT3,ICAP_ABORT4,DONE);
signal icap_nstate_ns, icap_nstate_cs : SM_TYPE;
signal icap_ce_ns,icap_ce_cs,icap_ce_cs1 : std_logic;
signal icap_we_ns,icap_we_cs,icap_we_cs1 : std_logic;
signal rdfifo_wren_ns,rdfifo_wren_cs : std_logic;
signal wrfifo_rden_ns : std_logic;
signal Send_done_ns,Send_done_cs : std_logic;
signal size_ns,size_cs : std_logic_vector(0 to 11);
signal reset_cr_cs,reset_cr_ns: std_logic;
signal abort_ns,abort_cs,abort_cs2 : std_logic;
signal icap_status_i : std_logic_vector(0 to 31);
signal abort_i_ns,abort_i_cs,abort_i_cs2: std_logic;
signal icap_dataout_i : std_logic_vector(0 to ICAP_DWIDTH-1);
signal Wrfifo_empty_r,Wrfifo_empty_r1 : std_logic;
signal tmp_datain_ns,tmp_datain_cs : std_logic_vector(0 to ICAP_DWIDTH-1);
signal icap_datain_ns,icap_datain_cs, int1, int2 : std_logic_vector(0 to ICAP_DWIDTH-1);
signal stm_skip : std_logic;
signal count : std_logic_vector (2 downto 0);
signal count_enable_ns, count_enable_cs : std_logic;
signal count_reset_ns, count_reset_cs : std_logic;
signal hang_status_ns, hang_status_cs : std_logic := '0';
attribute mark_debug of icap_ce_cs : signal is "true";
attribute mark_debug of icap_we_cs: signal is "true";
attribute mark_debug of icap_datain_cs : signal is "true";
attribute mark_debug of icap_dataout_i : signal is "true";
begin
GEN_SKIP : if (C_MODE = 1) generate
begin
stm_skip <= '1';
end generate GEN_SKIP;
GEN_NOSKIP : if (C_MODE = 0) generate
begin
stm_skip <= '0';
end generate GEN_NOSKIP;
-------------------------------------------------------------------------------
-- ICAP FSM
-------------------------------------------------------------------------------
ICAP_FSM_NS : process (icap_nstate_cs,Rnc,Abort,Rdfifo_full,
Size,size_cs,Wrfifo_empty,Wrfifo_empty_r,Wrfifo_empty_r1,
Send_done_cs,Status_read,
icap_ce_cs,icap_we_cs,Icap_busy,stm_skip,
count_enable_cs, count_reset_cs, hang_status_cs, count)
begin
-- default
rdfifo_wren_ns <= '0';
wrfifo_rden_ns <= '0';
Send_done_ns <= Send_done_cs;
reset_cr_ns <= '0';
icap_ce_ns <= icap_ce_cs;
icap_we_ns <= icap_we_cs;
icap_nstate_ns <= icap_nstate_cs;
size_ns <= size_cs;
abort_ns <= '0';
abort_i_ns <= '0';
count_enable_ns <= count_enable_cs;
count_reset_ns <= count_reset_cs;
hang_status_ns <= hang_status_cs;
-- tmp_datain_ns <= tmp_datain_cs;
-- icap_datain_ns <= icap_datain_cs;
case icap_nstate_cs is
when ICAP_IDLE =>
if Status_read = '1' then
abort_ns <= '0';
count_enable_ns <= '0';
end if;
if Abort = '1' then
reset_cr_ns <= '0';
icap_ce_ns <= '0';
abort_i_ns <= '1';
icap_nstate_ns <= ICAP_ABORT0;
elsif Rnc = "01" then
if Wrfifo_empty = '0'then
icap_nstate_ns <= ICAP_WRITE1;
wrfifo_rden_ns <= '1';
Send_done_ns <= '0';
reset_cr_ns <= '0';
else
icap_nstate_ns <= ICAP_IDLE;
end if;
elsif Rnc = "10" then
if Rdfifo_full = '0'then
icap_nstate_ns <= ICAP_READ1;
Send_done_ns <= '0';
reset_cr_ns <= '0';
size_ns <= Size;
else
icap_nstate_ns <= ICAP_IDLE;
end if;
else
Send_done_ns <= '1';
reset_cr_ns <= '0';
icap_nstate_ns <= ICAP_IDLE;
end if;
count_reset_ns <= '1';
count_enable_ns <= '0';
when ICAP_WRITE1 =>
-- tmp_datain_ns <= Wrfifo_dataout;
icap_we_ns <= '0';
if Wrfifo_empty = '1' then
icap_nstate_ns <= ICAP_WRITE3;
wrfifo_rden_ns <= '0';
else
icap_nstate_ns <= ICAP_WRITE5;
wrfifo_rden_ns <= '1';
end if;
when ICAP_WRITE5 =>
icap_ce_ns <= '0';
icap_we_ns <= '0';
-- tmp_datain_ns <= Wrfifo_dataout;
-- icap_datain_ns <= tmp_datain_cs;
icap_nstate_ns <= ICAP_WRITE2;
if Wrfifo_empty = '1' then
wrfifo_rden_ns <= '0';
else
wrfifo_rden_ns <= '1';
end if;
when ICAP_WRITE2 =>
if Status_read = '1' then
abort_ns <= '0';
end if;
if Wrfifo_empty_r1 = '0' then
icap_ce_ns <= '0';
icap_we_ns <= '0';
-- tmp_datain_ns <= Wrfifo_dataout;
-- icap_datain_ns <= tmp_datain_cs;
if Abort = '1' and icap_ce_cs = '0'then
icap_nstate_ns <= ICAP_ABORT1;
icap_we_ns <= '1';
abort_i_ns <= '1';
-- elsif (Icap_busy = '0' and Wrfifo_empty_r = '0') then
elsif (Wrfifo_empty_r = '0') then
icap_nstate_ns <= ICAP_WRITE2;
wrfifo_rden_ns <= '1';
else
icap_nstate_ns <= ICAP_WRITE2;
wrfifo_rden_ns <= '0';
end if;
else
icap_nstate_ns <= DONE;
Send_done_ns <= '1';
reset_cr_ns <= '1';
wrfifo_rden_ns <= '0';
-- tmp_datain_ns <= (others => '0');
-- icap_datain_ns <= (others => '0');
icap_ce_ns <= '1';
icap_we_ns <= '0';
end if;
when ICAP_WRITE3 =>
icap_ce_ns <= '0';
icap_we_ns <= '0';
-- icap_datain_ns <= tmp_datain_cs;
if (stm_skip = '1') then -- Skipping to maintain single write on ICAP
icap_nstate_ns <= DONE; -- This is not required in actual h/w, and is more of simulation fix
elsif (Icap_busy = '0') then
icap_nstate_ns <= ICAP_WRITE4;
else
icap_nstate_ns <= ICAP_WRITE3;
end if;
when ICAP_WRITE4 =>
icap_nstate_ns <= DONE;
Send_done_ns <= '1';
reset_cr_ns <= '1';
-- tmp_datain_ns <= (others => '0');
-- icap_datain_ns <= (others => '0');
icap_ce_ns <= '1';
icap_we_ns <= '0';
when ICAP_READ1 =>
if Status_read = '1' then
abort_ns <= '0';
end if;
if Rdfifo_full = '0' then
if (size_cs > 0) then
if Abort = '1' and icap_ce_cs = '0'then
icap_ce_ns <= '0';
icap_we_ns <= '1';
icap_we_ns <= '0';
abort_i_ns <= '1';
icap_nstate_ns <= ICAP_ABORT1;
count_enable_ns <= '0';
hang_status_ns <= '0';
elsif Icap_busy = '0' then
if (size_cs = 1) then
icap_nstate_ns <= DONE;
icap_ce_ns <= '1';
else
icap_ce_ns <= '0';
icap_nstate_ns <= ICAP_READ1;
end if;
size_ns <= size_cs - 1;
icap_we_ns <= '1';
rdfifo_wren_ns <= '1';
count_enable_ns <= '0';
hang_status_ns <= '0';
else
icap_ce_ns <= '0';
icap_we_ns <= '1';
if (count = "111") then
hang_status_ns <= '1';
icap_nstate_ns <= ICAP_ABORT_HANG;
else
icap_nstate_ns <= ICAP_READ1;
hang_status_ns <= '0';
end if;
size_ns <= size_cs;
rdfifo_wren_ns <= '0';
count_enable_ns <= '1'; -- This is used to increment timeout counter
count_reset_ns <= '0';
end if;
else
icap_ce_ns <= '1';
icap_we_ns <= '1';
rdfifo_wren_ns <= '0';
Send_done_ns <= '1';
reset_cr_ns <= '1';
count_enable_ns <= '0';
icap_nstate_ns <= DONE;
end if;
else
rdfifo_wren_ns <= '0';
icap_ce_ns <= '0'; -- Not aborting, only gating
icap_we_ns <= '1';
count_enable_ns <= '0';
icap_nstate_ns <= ICAP_READ1;
end if;
when ICAP_ABORT0 =>
abort_i_ns <= '1';
icap_we_ns <= '0';
if Icap_busy = '1' and icap_ce_cs = '0' then
icap_nstate_ns <= ICAP_ABORT2;
else
icap_nstate_ns <= ICAP_ABORT0;
end if;
when ICAP_ABORT_HANG => -- Internally de-locking the ICAP
abort_i_ns <= '0';
abort_ns <= '0';
icap_ce_ns <= '1';
icap_we_ns <= '1';
count_reset_ns <= '1';
count_enable_ns <= '0';
hang_status_ns <= '1';
icap_nstate_ns <= DONE;
when ICAP_ABORT1 =>
abort_i_ns <= '1';
-- if Icap_busy = '1' and icap_ce_cs = '0' then
icap_nstate_ns <= ICAP_ABORT2;
-- else
-- icap_nstate_ns <= ICAP_ABORT1;
-- end if;
when ICAP_ABORT2 =>
abort_i_ns <= '1';
abort_ns <= '1';
icap_nstate_ns <= ICAP_ABORT3;
when ICAP_ABORT3 =>
abort_i_ns <= '1';
abort_ns <= '1';
icap_nstate_ns <= ICAP_ABORT4;
when ICAP_ABORT4 =>
abort_i_ns <= '0'; -- Asserted for 4 clocks
abort_ns <= '1';
icap_nstate_ns <= DONE;
when DONE =>
if Status_read = '1' then
abort_ns <= '0';
end if;
abort_i_ns <= '0'; -- Asserted for 4 clocks
icap_ce_ns <= '1';
icap_we_ns <= '1';
-- tmp_datain_ns <= (others => '0');
-- icap_datain_ns <= (others => '0');
Send_done_ns <= '1';
reset_cr_ns <= '1';
count_reset_ns <= '0';
count_enable_ns <= '0';
if Rnc = "00" and Abort = '0' then
icap_nstate_ns <= ICAP_IDLE;
else
icap_nstate_ns <= DONE;
end if;
-- This part of the code never executes, because all of the
-- combinations are used above. "When others =>" added to
-- allow the synthesis tool to optimize the design well
-- coverage off
when others =>
icap_nstate_ns <= ICAP_IDLE;
-- coverage on
end case;
end process ICAP_FSM_NS;
-------------------------------------------------------------------------------
-- ICAP Timeout reg process
-------------------------------------------------------------------------------
ICAP_TIMEOUT_REG: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
count <= (others => '0');
elsif (count_reset_cs = '1') then
count <= (others => '0');
elsif (count_enable_cs = '1' and count < "111" ) then
count <= count + '1';
end if;
end if;
end process ICAP_TIMEOUT_REG;
-------------------------------------------------------------------------------
-- ICAP FSM reg process
-------------------------------------------------------------------------------
ICAP_FSM_REG: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
icap_nstate_cs <= ICAP_IDLE;
Send_done_cs <= '1';
icap_ce_cs <= '1';
icap_we_cs <= '1';
icap_ce_cs1 <= '1';
icap_we_cs1 <= '1';
size_cs <= (others =>'0');
-- tmp_datain_cs <= (others => '0');
icap_datain_cs <= (others =>'0');
count_enable_cs <= '0';
count_reset_cs <= '0';
hang_status_cs <= '0';
int1 <= (others => '0');
int2 <= (others => '0');
else
icap_nstate_cs <= icap_nstate_ns;
Send_done_cs <= Send_done_ns;
icap_ce_cs <= icap_ce_ns;
icap_ce_cs1 <= icap_ce_cs;
icap_we_cs <= icap_we_ns;
icap_we_cs1 <= icap_we_cs;
size_cs <= size_ns;
-- tmp_datain_cs <= tmp_datain_ns;
int1 <= Wrfifo_dataout;
icap_datain_cs <= int1; --icap_datain_ns;
count_enable_cs <= count_enable_ns;
count_reset_cs <= count_reset_ns;
hang_status_cs <= hang_status_ns;
end if;
end if;
end process ICAP_FSM_REG;
Hang_status <= hang_status_cs;
ICAP_SIG_REG: process (Clk) is
begin
if (Clk'event and Clk = '1') then
abort_cs <= abort_ns;
abort_cs2 <= abort_cs;
reset_cr_cs <= reset_cr_ns;
abort_i_cs <= abort_i_ns;
abort_i_cs2 <= abort_i_cs;
Wrfifo_empty_r <= Wrfifo_empty;
Wrfifo_empty_r1 <= Wrfifo_empty_r;
rdfifo_wren_cs <= rdfifo_wren_ns;
end if;
end process ICAP_SIG_REG;
S1: Rdfifo_wren <= rdfifo_wren_cs;
S2: Wrfifo_rden <= wrfifo_rden_ns;
S3: Send_done <= Send_done_cs;
S4: Icap_ce <= icap_ce_cs;
S5: Icap_we <= icap_we_cs;
S6: Reset_cr <= reset_cr_cs;
S7: Size_counter <= size_cs;
S8: Abort_in_progress <= abort_cs2;
S9: Icap_status <= icap_status_i;
-----------------------------------------------------------------------------
-- Need to do bit swapping within each byte but not for Virtex4 in 32-bit mode
-------------------------------------------------------------------------------
SWAP_BITS: process (icap_datain_cs) is
begin -- process Swap_bit_Order
for byte in 0 to (ICAP_DWIDTH/8-1) loop
for bit in 0 to 7 loop
Icap_datain(byte*8 + (7-bit)) <= icap_datain_cs(byte*8 + bit);
-- Rdfifo_datain (byte*8 + (7-bit)) <= icap_dataout_i(byte*8 + bit);
end loop; -- Bit
end loop; -- Byte
end process SWAP_BITS;
SWAP_BITS_IN: process (icap_dataout_i) is
begin -- process Swap_bit_Order
for byte in 0 to (ICAP_DWIDTH/8-1) loop
for bit in 0 to 7 loop
-- Icap_datain(byte*8 + (7-bit)) <= icap_datain_cs(byte*8 + bit);
Rdfifo_datain (byte*8 + (7-bit)) <= icap_dataout_i(byte*8 + bit);
end loop; -- Bit
end loop; -- Byte
end process SWAP_BITS_IN;
-------------------------------------------------------------------------------
-- UPDATE_STATUS_PROCESS
-------------------------------------------------------------------------------
-- This process loads data from Icap_dataout when abort_i_cs enabled
-------------------------------------------------------------------------------
UPDATE_STATUS_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
icap_status_i <= (others => '0');
elsif abort_i_cs2 = '1' then
icap_status_i (0 to 7) <= Icap_dataout(ICAP_DWIDTH-8 to ICAP_DWIDTH-1);
icap_status_i (8 to 15) <= icap_status_i (0 to 7);
icap_status_i (16 to 23) <= icap_status_i (8 to 15);
icap_status_i (24 to 31) <= icap_status_i (16 to 23);
else
icap_status_i <= icap_status_i;
end if;
end if;
end process UPDATE_STATUS_PROCESS;
-------------------------------------------------------------------------------
-- This process registers ICAP data out
-------------------------------------------------------------------------------
ICAPDOUT_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
icap_dataout_i <= Icap_dataout;
end if;
end process ICAPDOUT_PROCESS;
end architecture imp;
|
<filename>g05_mastermind_datapath.vhd
-- Descp. mastermind datapath
--
-- entity name: g05_mastermind_datapath
--
-- Version 1.0
-- Author: <NAME>; <EMAIL> & <NAME>; <EMAIL>
-- Date: November 23, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_mastermind_datapath is
port (
P_SEL, GR_SEL, SR_SEL : in std_logic;
GR_LD, SR_LD : in std_logic;
TM_IN, TM_EN, TC_RST, TC_EN : in std_logic;
EXT_PATTERN : in std_logic_vector(11 downto 0);
EXT_SCORE : in std_logic_vector(3 downto 0);
MODE : in std_logic;
START_MODE : in std_logic;
CLK : in std_logic;
TM_OUT : out std_logic;
TC_LAST : out std_logic;
SC_CMP : out std_logic;
DIS_P1, DIS_P2, DIS_P3, DIS_P4, DIS_P5, DIS_P6 : out std_logic_vector(3 downto 0)
);
end g05_mastermind_datapath;
architecture behavior of g05_mastermind_datapath is
component g05_mastermind_score is
port (
P1, P2, P3, P4 : in std_logic_vector(2 downto 0);
G1, G2, G3, G4 : in std_logic_vector(2 downto 0);
exact_match_score : out std_logic_vector(2 downto 0);
color_match_score : out std_logic_vector(2 downto 0);
score_code : out std_logic_vector(3 downto 0)
);
end component;
component g05_possibility_table is
port (
TC_EN : in std_logic;
TC_RST : in std_logic;
TM_IN : in std_logic;
TM_EN : in std_logic;
CLK : in std_logic;
TC_LAST : out std_logic;
TM_ADDR : out std_logic_vector(11 downto 0);
TM_OUT : out std_logic
);
end component;
component g05_comp6 is
port (
A : in std_logic_vector(5 downto 0);
B : in std_logic_vector(5 downto 0);
AeqB : out std_logic
);
end component;
component g05_color_decoder is
port (
color : in std_logic_vector(2 downto 0);
color_code : out std_logic_vector(3 downto 0)
);
end component;
component g05_score_decoder is
port (
score_code : in std_logic_vector(3 downto 0);
num_exact_matches, num_color_matches : out std_logic_vector(3 downto 0)
);
end component;
signal P1, P2, P3, P4 : std_logic_vector(2 downto 0);
signal G1, G2, G3, G4 : std_logic_vector(2 downto 0);
signal TM_ADDR : std_logic_vector(11 downto 0);
signal score, score_reg, SR : std_logic_vector(3 downto 0);
signal G1_code, G2_code, G3_code, G4_code, P1_code, P2_code, P3_code, P4_code : std_logic_vector(3 downto 0);
signal num_exact_matches, num_color_matches : std_logic_vector(3 downto 0);
begin
P4 <= EXT_PATTERN(2 downto 0) when P_SEL = '0' else TM_ADDR(2 downto 0);
P3 <= EXT_PATTERN(5 downto 3) when P_SEL = '0' else TM_ADDR(5 downto 3);
P2 <= EXT_PATTERN(8 downto 6) when P_SEL = '0' else TM_ADDR(8 downto 6);
P1 <= EXT_PATTERN(11 downto 9) when P_SEL = '0' else TM_ADDR(11 downto 9);
process(CLK)
begin
if (rising_edge(CLK)) then
if (GR_LD = '1') then
if (GR_SEL = '0') then
G1 <= TM_ADDR(2 downto 0);
G2 <= TM_ADDR(5 downto 3);
G3 <= TM_ADDR(8 downto 6);
G4 <= TM_ADDR(11 downto 9);
else
G1 <= "001";
G2 <= "001";
G3 <= "000";
G4 <= "000";
end if;
end if;
end if;
end process;
G1_decode : g05_color_decoder
port map (color => G1, color_code => G1_code);
G2_decode : g05_color_decoder
port map (color => G2, color_code => G2_code);
G3_decode : g05_color_decoder
port map (color => G3, color_code => G3_code);
G4_decode : g05_color_decoder
port map (color => G4, color_code => G4_code);
P1_decode : g05_color_decoder
port map (color => P1, color_code => P1_code);
P2_decode : g05_color_decoder
port map (color => P2, color_code => P2_code);
P3_decode : g05_color_decoder
port map (color => P3, color_code => P3_code);
P4_decode : g05_color_decoder
port map (color => P4, color_code => P4_code);
process(CLK, START_MODE, MODE)
begin
if (rising_edge(CLK)) then
if START_MODE = '0' then
if MODE = '0' then
DIS_P1 <= G1_code;
DIS_P2 <= G2_code;
DIS_P3 <= G3_code;
DIS_P4 <= G4_code;
DIS_P5 <= num_color_matches;
DIS_P6 <= num_exact_matches;
else
DIS_P1 <= P1_code;
DIS_P2 <= P2_code;
DIS_P3 <= P3_code;
DIS_P4 <= P4_code;
DIS_P5 <= num_color_matches;
DIS_P6 <= num_exact_matches;
end if;
else
DIS_P1 <= "0111"; -- T
DIS_P2 <= "1011"; -- R
DIS_P3 <= "1000"; -- A
DIS_P4 <= "0111"; -- T
DIS_P5 <= "0101"; -- S
DIS_P6 <= "0000"; --
end if;
end if;
end process;
mastermind_score : g05_mastermind_score
port map (P1 => P1, P2 => P2, P3 => P3, P4 => P4,
G1 => G1, G2 => G2, G3 => G3, G4 => G4,
score_code => score);
process(CLK)
begin
if rising_edge(CLK) then
if SR_LD = '1' then
if MODE = '0' then
score_reg <= EXT_SCORE;
else
score_reg <= score;
end if;
end if;
end if;
end process;
decode : g05_score_decoder
port map (score_code => score_reg, num_exact_matches => num_exact_matches, num_color_matches => num_color_matches);
SR <= score when SR_SEL = '0' else "0000";
score_comp : g05_comp6
port map (A(5 downto 4) => "00", A(3 downto 0) => score_reg,
B(5 downto 4) => "00", B(3 downto 0) => SR, AeqB => SC_CMP);
possibility_table : g05_possibility_table
port map (TC_EN => TC_EN, TC_RST => TC_RST, TM_IN => TM_IN,
TM_EN => TM_EN, CLK => CLK, TC_LAST => TC_LAST,
TM_ADDR => TM_ADDR, TM_OUT => TM_OUT);
end behavior;
|
-- file Mcvevp.vhd
-- Aries Cyclone V evaluation platform global constants and types
-- copyright: (C) 2017-2020 MPSI Technologies GmbH
-- author: <NAME> (auto-generation)
-- date created: 21 Oct 2021
-- IP header --- ABOVE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Dbecore is
constant fls8: std_logic_vector(7 downto 0) := x"AA";
constant fls16: std_logic_vector(15 downto 0) := x"AAAA";
constant fls32: std_logic_vector(31 downto 0) := x"AAAAAAAA";
constant tru8: std_logic_vector(7 downto 0) := x"55";
constant tru16: std_logic_vector(15 downto 0) := x"5555";
constant tru32: std_logic_vector(31 downto 0) := x"55555555";
constant ixOpbufBuffer: natural := 0;
constant ixOpbufController: natural := 1;
constant ixOpbufCommand: natural := 2;
constant ixOpbufLength: natural := 3;
constant ixOpbufCrc: natural := 5;
end Dbecore;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Mcvevp is
end Mcvevp;
|
<reponame>lsylvestre/dsml
-- AVALON MM-slave wrapper around the core fact IP
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.misc_fact.all;
entity avs_fact is
port (avs_s0_address : in std_logic_vector(3 downto 0) := (others => '0');
-- 0000 : control/status register (b1=start, b0=rdy)
-- 0001 : n register
-- 0010 : result register
avs_s0_read : in std_logic := '0';
avs_s0_readdata : out std_logic_vector(31 downto 0);
avs_s0_write : in std_logic := '0';
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0');
clock_clk : in std_logic := '0';
reset_reset : in std_logic := '0');
end entity;
architecture rtl of avs_fact is
component fact is
port (signal clk : in std_logic;
signal reset : in std_logic;
signal start : in std_logic;
signal rdy : out std_logic;
signal n: in caml_int;
signal result: out caml_int);
end component;
signal n: caml_int;
signal result: caml_int;
signal start: std_logic;
signal rdy: std_logic;type write_state_t is (Idle, StartAsserted);
signal write_state: write_state_t;
begin
fact_CC : component fact
port map (clk => clock_clk,
reset => reset_reset,
start => start,
rdy => rdy,
n => n,
result => result);
WRITE: process (clock_clk, reset_reset)
begin
if reset_reset = '1' then
write_state <= Idle;
elsif rising_edge(clock_clk) then
case write_state is
when StartAsserted =>
start <= '0';
write_state <= Idle;
when Idle =>
if avs_s0_write = '1' then
case avs_s0_address is
when "0000" => -- writing CSR asserts start for one clock period
start <= '1';
write_state <= StartAsserted;
when "0001" => n <= signed(avs_s0_writedata(30 downto 0));
when others => NULL;
end case;
end if;
end case;
end if;
end process;
READ: process (clock_clk)
begin
if rising_edge(clock_clk) then
if avs_s0_read = '1' then
case avs_s0_address is
when "0000" => avs_s0_readdata <= X"0000000" & "000" & rdy;
-- when reading CSR, bit 0 is rdy
when "0001" => avs_s0_readdata <= "0" & std_logic_vector(n);
when "0010" => avs_s0_readdata <= "0" & std_logic_vector(result);
when others => null;
end case;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_calc_bin_to_6x7seg is
end entity test_calc_bin_to_6x7seg;
architecture test of test_calc_bin_to_6x7seg is
component calc_bin_to_6x7seg port(
binaryNumber : in std_logic_vector(19 downto 0); -- 2^20 > 999.999 (max on 6 segments)
HEX0: out std_logic_vector(6 downto 0);
HEX1: out std_logic_vector(6 downto 0);
HEX2: out std_logic_vector(6 downto 0);
HEX3: out std_logic_vector(6 downto 0);
HEX4: out std_logic_vector(6 downto 0);
HEX5: out std_logic_vector(6 downto 0)
-- TODO: add enumeration for display mode
-- type display_6x7seg_mode_type is {FULL, ACTUAL_VOLTAGE, ...};
-- put this in a separate package to make it available to other modules
);
end component calc_bin_to_6x7seg;
signal HEX0: std_logic_vector(6 downto 0);
signal HEX1: std_logic_vector(6 downto 0);
signal HEX2: std_logic_vector(6 downto 0);
signal HEX3: std_logic_vector(6 downto 0);
signal HEX4: std_logic_vector(6 downto 0);
signal HEX5: std_logic_vector(6 downto 0);
signal binaryNumber : std_logic_vector(19 downto 0);
begin
sut : calc_bin_to_6x7seg port map( binaryNumber, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 );
simulate: process
begin
binaryNumber <= std_logic_vector(to_unsigned(999999, binaryNumber'length));
wait for 100 ns;
assert HEX0=not "1101111" report "HEX0 nok for 999999" severity error;
assert HEX1=not "1101111" report "HEX1 nok for 999999" severity error;
assert HEX2=not "1101111" report "HEX2 nok for 999999" severity error;
assert HEX3=not "1101111" report "HEX3 nok for 999999" severity error;
assert HEX4=not "1101111" report "HEX4 nok for 999999" severity error;
assert HEX5=not "1101111" report "HEX5 nok for 999999" severity error;
binaryNumber <= std_logic_vector(to_unsigned(0, binaryNumber'length));
wait for 100 ns;
assert HEX0=not "0111111" report "HEX0 nok for 0" severity error;
assert HEX1=not "0111111" report "HEX1 nok for 0" severity error;
assert HEX2=not "0111111" report "HEX2 nok for 0" severity error;
assert HEX3=not "0111111" report "HEX3 nok for 0" severity error;
assert HEX4=not "0111111" report "HEX4 nok for 0" severity error;
assert HEX5=not "0111111" report "HEX5 nok for 0" severity error;
end process simulate;
end architecture test;
|
<gh_stars>1-10
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
-- Date : Thu Feb 20 21:08:33 2020
-- Host : ssg0 running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /ectf/pl/proj/test/bd/system/ip/system_splitchannel_0_0/system_splitchannel_0_0_sim_netlist.vhdl
-- Design : system_splitchannel_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z007sclg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_splitchannel_0_0 is
port (
i_stereo : in STD_LOGIC_VECTOR ( 31 downto 0 );
o_left : out STD_LOGIC_VECTOR ( 15 downto 0 );
o_right : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_splitchannel_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_splitchannel_0_0 : entity is "system_splitchannel_0_0,splitchannel,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_splitchannel_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_splitchannel_0_0 : entity is "splitchannel,Vivado 2017.4";
end system_splitchannel_0_0;
architecture STRUCTURE of system_splitchannel_0_0 is
signal \^i_stereo\ : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
\^i_stereo\(31 downto 0) <= i_stereo(31 downto 0);
o_left(15 downto 0) <= \^i_stereo\(15 downto 0);
o_right(15 downto 0) <= \^i_stereo\(31 downto 16);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.RV32I_pkg.all;
entity alu_tb is
end alu_tb;
architecture driver of alu_tb is
component alu
port ( inputA : in std_logic_vector (XLEN-1 downto 0);
inputB : in std_logic_vector (XLEN-1 downto 0);
ALUop : in std_logic_vector (3 downto 0);
result : out std_logic_vector (XLEN-1 downto 0));
end component;
-- inputs
signal tb_inputA : std_logic_vector (XLEN-1 downto 0):= (others => '0');
signal tb_inputB : std_logic_vector (XLEN-1 downto 0):= (others => '0');
signal tb_ALUop : std_logic_vector (3 downto 0):= (others => '0');
-- outputs
signal tb_result : std_logic_vector (XLEN-1 downto 0);
begin
-- Instantiate the Unit Under Test (UUT)
UUT: alu port map ( inputA => tb_inputA,
inputB => tb_inputB,
ALUop => tb_ALUop,
result => tb_result);
tb_ALUop <= ALU_OP_ADD after 10ns,
ALU_OP_SUB after 20ns,
ALU_OP_AND after 40ns,
ALU_OP_OR after 50ns,
ALU_OP_XOR after 60ns,
ALU_OP_SLL after 70ns,
ALU_OP_SRL after 80ns,
ALU_OP_SRA after 90ns,
ALU_OP_SLT after 100ns,
ALU_OP_SLTU after 110ns;
tb_inputA <= "00000000000000001110010010110101" after 10ns,
"11111100000000001111000000000100" after 20ns,
"00000000001110001111000000000100" after 30ns,
"11111111100000001111000000000100" after 40ns;
tb_inputB <= "00000000000000000010110101001010" after 10ns,
"11111111111100001111000000000100" after 20ns,
"00000000000000000000000000000110" after 40ns;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:46:14 12/28/2015
-- Design Name:
-- Module Name: C:/Users/lcastedo/Documents/pruebas/tema5_4/e02_bufferz_tb.vhd
-- Project Name: tema5_4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: e02_bufferz
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
use work.e04_mux_pkg.all;
entity e04_mux_tb is
end e04_mux_tb;
architecture behavior of e04_mux_tb is
-- Component Declaration for the Unit Under Test (UUT)
component e04_mux is
generic (
FANIN: positive
);
port (
A: in mux_bus_vector(0 to FANIN - 1);
S: in std_logic_vector(integer(ceil(log2(real(FANIN)))) - 1 downto 0);
Y: out mux_bus
);
end component;
--Inputs
signal a: mux_bus_vector(0 to 3) := (X"33", X"55", X"AA", X"FF");
signal s: std_logic_vector(1 downto 0);
--Output
signal y: mux_bus;
-- Clocks period
constant CLK_PERIOD: time := 10 ns;
constant DELAY : time := 0.1 * CLK_PERIOD;
begin
-- Instantiate the Unit Under Test (UUT)
uut: e04_mux
generic map (
FANIN => 4
)
port map (
A => a,
S => s,
Y => y
);
-- Stimulus process
stim_proc: process
begin
for i in 0 to 3 loop
s <= std_logic_vector(to_signed(i, s'length));
wait for DELAY;
assert y = a(i)
report "[FAILED]: mux malfunction."
severity failure;
wait for CLK_PERIOD - DELAY;
end loop;
assert false
report "[PASSED]: Simulation finished."
severity failure;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.util.all;
entity testbench_dadda_final_approx_fully_parallel is
generic (max_limit_ambe : integer := 5;
max_limit_dadda : integer := 6);
end testbench_dadda_final_approx_fully_parallel;
architecture behav of testbench_dadda_final_approx_fully_parallel is
component mul_ambe_mbe_dadda_four_to_two
generic (limit_ambe : integer := 0;
limit_dadda : integer := 0);
port (a, b : in signed(Nbit -1 downto 0);
product : out signed(2 * Nbit - 1 downto 0));
end component;
signal a, b : signed(9 downto 0) := "0000000000";
signal a_int, b_int, correct_int : integer;
signal correct_bin : signed(19 downto 0);
--type subfile_array is array(max_limit_dadda downto 0) of file;
--type file_array is array(max_limit_ambe downto 0) of subfile_array;
type subproduct_array is
array(max_limit_dadda downto 0) of signed(2 * Nbit - 1 downto 0);
type product_array is
array(max_limit_ambe downto 0) of subproduct_array;
type subproduct_int_array is array(max_limit_dadda downto 0) of integer;
type product_int_array is
array(max_limit_ambe downto 0) of subproduct_int_array;
type substring_array is array(max_limit_dadda downto 0) of string(40 downto 1);
type string_array is array(max_limit_ambe downto 0) of substring_array;
type correct_array is array(max_limit_ambe downto 0) of
std_logic_vector(max_limit_dadda downto 0);
signal product : product_array;
signal product_int, dist : product_int_array;
--signal files : file_array;
signal filenames : string_array;
signal basedir : string(24 downto 1) := "Comparisons_final_approx";
signal correct : correct_array;
begin
if_gen : if max_limit_ambe >= 0 and max_limit_ambe <= 5 and
max_limit_dadda >= 0 and max_limit_dadda <= 6 generate
ambe_gen : for i in 0 to max_limit_ambe generate
dadda_gen : for j in 0 to max_limit_dadda generate
test : mul_ambe_mbe_dadda_four_to_two
generic map (limit_ambe => i, limit_dadda => j)
port map (a => a, b => b, product => product(i)(j));
product_int(i)(j) <= to_integer(product(i)(j));
dist(i)(j) <= correct_int - product_int(i)(j);
filenames(i)(j) <= basedir & "/ambe" & integer'image(i) &
"dadda" & integer'image(j) & ".txt";
end generate;
end generate;
end generate;
a <= to_signed(a_int, 10);
b <= to_signed(b_int, 10);
correct_bin <= to_signed(correct_int, 20);
process
variable line_out : line;
file output : text;
begin
a_int <= 0;
b_int <= 0;
wait for 10 ns;
for i in -2 ** 9 to 2 ** 9 - 1 loop
for j in -2**9 to 2 ** 9 - 1 loop
a_int <= i;
b_int <= j;
wait for 1 ps;
correct_int <= i * j;
if max_limit_ambe >= 0 and max_limit_ambe <= 5 and
max_limit_dadda >= 0 and max_limit_dadda <= 6 then
for k in 0 to max_limit_ambe loop
for l in 0 to max_limit_dadda loop
if (i * j - product_int(k)(l)) = 0 then
correct(k)(l) <= '1';
else
correct(k)(l) <= '0';
end if;
end loop;
end loop;
end if;
wait for 2500 ps;
if max_limit_ambe >= 0 and max_limit_ambe <= 5 and
max_limit_dadda >= 0 and max_limit_dadda <= 6 then
for k in 0 to max_limit_ambe loop
for l in 0 to max_limit_dadda loop
--write(line_out, string'("a bin: "));
--write(line_out, a, right, 10);
--write(line_out, string'(" ; a int: "));
--write(line_out, string'("a int: "));
write(line_out, a_int);
--write(line_out, string'(" ; b bin: "));
--write(line_out, b, right, 10);
--write(line_out, string'(" ; b int: "));
write(line_out, string'(";"));
write(line_out, b_int);
--write(line_out, string'(" ; product bin: "));
--write(line_out, product, right, 20);
--write(line_out, string'(" ; product int: "));
write(line_out, string'(";"));
write(line_out, product_int(k)(l));
--write(line_out, string'(" ; correct bin: "));
--write(line_out, correct_bin, right, 20);
--write(line_out, string'(" ; correct int: "));
write(line_out, string'(";"));
write(line_out, correct_int);
--write(line_out, string'(" ; correct bool: "));
write(line_out, string'(";"));
write(line_out, correct(k)(l));
--write(line_out, string'(" ; distance: "));
write(line_out, string'(";"));
write(line_out, dist(k)(l));
file_open(output, filenames(k)(l), append_mode);
writeline(output, line_out);
file_close(output);
deallocate(line_out);
end loop;
end loop;
end if;
wait for 2499 ps;
end loop;
end loop;
-- a <= "0000000001";
-- b <= "0000000001";
-- wait for 10 ns;
-- a <= "1111111111";
-- b <= "1111111111";
-- wait for 10 ns;
-- a <= "1111111110";
-- b <= "0000000001";
-- wait for 10 ns;
-- a <= "1010010100";
-- b <= "1010111001";
-- wait for 10 ns;
wait;
end process;
end behav;
|
<reponame>xfrolk03/Digital-electronics-1-2021<filename>Labs/project/hall_sensor/hall_sensor.srcs/sources_1/new/hall.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.04.2021 18:07:26
-- Design Name:
-- Module Name: hall - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hall is
port(
clk : in std_logic; -- main clock
hall_sensor : in std_logic; -- hall_sensor input
wheel_circuit : in integer; -- integer input of wheel circuit
mode_BTN : in std_logic; -- button input for setting display mode
reset_BTN : in std_logic; -- button input for resetting distance
number : out integer -- integer output of speed/distance
);
end hall;
architecture Behavioral of hall is
signal s_reset : std_logic; -- internal reset for time stop
signal s_run : std_logic; -- internal variable for running timer for wheel rotation
signal s_mode : std_logic:='0'; -- internal variable for display mode
signal s_runtime : integer; -- variable for wheel rotation time
signal speed : integer:=0; -- variable for calculated speed
signal distance : integer:=0; -- variable for calculated distance
constant speed_calculation : integer:=1000;
begin
-- instance copy of time_enable entity
time_stop : entity work.time_enable
port map(
runtime => s_runtime,
clk => clk,
reset => s_reset,
run => s_run
);
------------------------------------------------------------------------
-- Process speed_calc:
-- every time when hall_sensor is enabled, process calculates speed
--
-- using speed_calculation constant for correct simulation, when used in
-- real time, constants must be changed
------------------------------------------------------------------------
speed_calc : process(clk)
begin
if (s_reset = '1') then
s_reset <= '0';
end if;
if (rising_edge(hall_sensor)) then
speed <= (wheel_circuit * speed_calculation) / (s_runtime + 1);
s_reset <= '1';
end if;
end process;
------------------------------------------------------------------------
-- Process dist_calc:
-- every time when hall_sensor is enabled, process calculates distance
------------------------------------------------------------------------
dist_calc : process(clk, hall_sensor)
begin
if (rising_edge(hall_sensor)) then
distance <= distance + (wheel_circuit / 100); -- wheel circuit int mm must be calculated to m, used 100 for displaying decimal point
end if;
if (rising_edge(reset_BTN)) then
distance <= 0;
end if;
end process;
------------------------------------------------------------------------
-- Process view:
-- changing displayed values (speed / distance)
------------------------------------------------------------------------
view : process(clk)
begin
if (rising_edge(mode_BTN)) then
s_mode <= not(s_mode);
end if;
case s_mode is
when '0' =>
number <= speed;
when '1' =>
-- if distance is greater or equals 1 km, the distance is divided by 1000
if(distance >= 10000) then
number <= distance / 1000;
else number <= distance;
end if;
when others =>
number <= speed;
end case;
end process;
end Behavioral;
|
-- ALU CONTROL
library ieee;
use ieee.std_logic_1164.all;
entity control_alu is
port (ALUOp: in std_logic_vector (3 downto 0); -- first 4 bit of OPCode
funct: in std_logic_vector (5 downto 0); -- field in R-instructions
ALUCtrl: out std_logic_vector (3 downto 0);
ShiftCtrl: out std_logic_vector (1 downto 0);
ResSrc: out std_logic );
end control_alu;
architecture behav of control_alu is
begin
process (ALUOp, funct)
begin
case ALUOp is
when "0001" =>
case funct is
-- shift ll
when "000000" =>
ALUCtrl <= "0000";
ShiftCtrl <= "01";
ResSrc <= '1';
-- shift rl
when "000001" =>
ALUCtrl <= "0000";
ShiftCtrl <= "10";
ResSrc <= '1';
-- sum, sub, and, or, nand, nor, slt
when "000010" | "000011" | "000100" | "000101" | "000110" | "000111" | "001000" =>
ALUCtrl <= funct(3 downto 0);
ShiftCtrl <= "00";
ResSrc <= '0';
when others =>
ALUCtrl <= "0000"; -- NOP
ShiftCtrl <= "00";
ResSrc <= '0';
end case;
-- sum imm, sub imm, and imm, or imm, nand imm, nor imm, slt imm
when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" =>
ALUCtrl <= ALUOp;
ShiftCtrl <= "00";
ResSrc <= '0';
-- load, store (ALU sum)
when "1001" | "1010" =>
ALUCtrl <= "0010";
ShiftCtrl <= "00";
ResSrc <= '0';
-- beq, bne (ALU sub)
when "1011" | "1100" =>
ALUCtrl <= "0011";
ShiftCtrl <= "00";
ResSrc <= '0';
when others =>
ALUCtrl <= "0000"; -- NOP
ShiftCtrl <= "00";
ResSrc <= '0';
end case;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: <NAME>
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_5
-- Module Name: Solving_Key_Equation_5
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified binary extended euclidean algorithm.
-- The modification is made to stop the algorithm in 2*final degree steps.
-- The syndrome is the input and expected to be of degree 2*final_degree-1, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is pipeline circuit version that is slower than solving_key_equation_4.
-- However this version is constant time, therefore is more side channel resistant.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_5 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_load_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_5 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 27;
-- size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 66;
-- size_final_degree : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
gf_2_m : integer range 1 to 20 := 13;
final_degree : integer := 128;
size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_r : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_u : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_s : out STD_LOGIC;
write_enable_r : out STD_LOGIC;
write_enable_v : out STD_LOGIC;
write_enable_u : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_r : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_u : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_5;
architecture Behavioral of solving_key_equation_5 is
component controller_solving_key_equation_5
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_number_of_iterations : in STD_LOGIC;
last_polynomial_coefficient : in STD_LOGIC;
is_inv_zero : in STD_LOGIC;
is_r0_zero : in STD_LOGIC;
is_delta_less_than_0 : in STD_LOGIC;
is_rho_zero : in STD_LOGIC;
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_s : out STD_LOGIC;
write_enable_r : out STD_LOGIC;
write_enable_v : out STD_LOGIC;
write_enable_u : out STD_LOGIC;
sel_mult_r_inv : out STD_LOGIC;
last_u_value : out STD_LOGIC;
change_s_v : out STD_LOGIC;
change_r_u : out STD_LOGIC;
shift_r_u : out STD_LOGIC;
reg_value_s_rst : out STD_LOGIC;
reg_value_s_ce : out STD_LOGIC;
reg_value_r_rst : out STD_LOGIC;
reg_value_r_ce : out STD_LOGIC;
reg_value_v_rst : out STD_LOGIC;
reg_value_v_ce : out STD_LOGIC;
reg_value_u_rst : out STD_LOGIC;
reg_value_u_ce : out STD_LOGIC;
sel_reg_rho_rst_value : out STD_LOGIC;
reg_rho_rst : out STD_LOGIC;
reg_rho_ce : out STD_LOGIC;
ctr_delta_ce : out STD_LOGIC;
ctr_delta_load : out STD_LOGIC;
ctr_delta_rst : out STD_LOGIC;
reg_new_value_s_rst : out STD_LOGIC;
reg_new_value_s_ce : out STD_LOGIC;
reg_new_value_r_rst : out STD_LOGIC;
reg_new_value_r_ce : out STD_LOGIC;
reg_new_value_v_ce : out STD_LOGIC;
reg_new_value_u_rst : out STD_LOGIC;
reg_new_value_u_ce : out STD_LOGIC;
reg_new_value_u0_ce : out STD_LOGIC;
ctr_load_value_ce : out STD_LOGIC;
ctr_load_value_rst : out STD_LOGIC;
ctr_store_value_ce : out STD_LOGIC;
ctr_store_value_rst : out STD_LOGIC;
ctr_number_of_iterations_ce : out STD_LOGIC;
ctr_number_of_iterations_rst : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_load_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_value_s_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_s_rst : STD_LOGIC;
constant reg_value_s_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_s_ce : STD_LOGIC;
signal reg_value_s_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_r_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_r_rst : STD_LOGIC;
constant reg_value_r_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_r_ce : STD_LOGIC;
signal reg_value_r_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_v_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_v_rst : STD_LOGIC;
constant reg_value_v_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_v_ce : STD_LOGIC;
signal reg_value_v_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_u_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_u_rst : STD_LOGIC;
constant reg_value_u_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_u_ce : STD_LOGIC;
signal reg_value_u_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_rho_rst_value : STD_LOGIC;
signal reg_rho_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_rho_rst : STD_LOGIC;
constant reg_rho_rst_value_0 : STD_LOGIC_VECTOR((gf_2_m - 2) downto 0) := (others => '0');
signal reg_rho_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_rho_ce : STD_LOGIC;
signal reg_rho_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_delta_d : STD_LOGIC_VECTOR((size_final_degree) downto 0);
signal ctr_delta_ce : STD_LOGIC;
signal ctr_delta_load : STD_LOGIC;
signal ctr_delta_rst : STD_LOGIC;
constant ctr_delta_rst_value : STD_LOGIC_VECTOR((size_final_degree) downto 0) := std_logic_vector(to_signed(-1, size_final_degree+1));
signal ctr_delta_q : STD_LOGIC_VECTOR((size_final_degree) downto 0);
signal mult_s_rho_r_inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_s_rho_r_inv_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_s_rho_r_inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_v_rho_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_v_rho_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_v_rho_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal add_s_rho_r : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal add_v_rho_u : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_s_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_s_rst : STD_LOGIC;
constant reg_new_value_s_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_new_value_s_ce : STD_LOGIC;
signal reg_new_value_s_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_r_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_r_rst : STD_LOGIC;
constant reg_new_value_r_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_new_value_r_ce : STD_LOGIC;
signal reg_new_value_r_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_v_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_v_ce : STD_LOGIC;
signal reg_new_value_v_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u_rst : STD_LOGIC;
constant reg_new_value_u_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_new_value_u_ce : STD_LOGIC;
signal reg_new_value_u_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u0_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u0_ce : STD_LOGIC;
signal reg_new_value_u0_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_load_value_ce : STD_LOGIC;
signal ctr_load_value_rst : STD_LOGIC;
constant ctr_load_value_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0, size_final_degree+2));
signal ctr_load_value_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_delay_store_value_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_delay_store_value_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal shift_r_u : STD_LOGIC;
signal ctr_store_value_ce : STD_LOGIC;
signal ctr_store_value_rst : STD_LOGIC;
constant ctr_store_value_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0, size_final_degree+2));
signal ctr_store_value_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_number_of_iterations_ce : STD_LOGIC;
signal ctr_number_of_iterations_rst : STD_LOGIC;
constant ctr_number_of_iterations_rst_value : STD_LOGIC_VECTOR(size_final_degree downto 0) := std_logic_vector(to_unsigned(0, size_final_degree+1));
signal ctr_number_of_iterations_q : STD_LOGIC_VECTOR(size_final_degree downto 0);
signal sel_mult_r_inv : STD_LOGIC;
signal last_u_value : STD_LOGIC;
signal change_s_v : STD_LOGIC;
signal change_r_u : STD_LOGIC;
signal limit_number_of_iterations : STD_LOGIC;
signal last_polynomial_coefficient : STD_LOGIC;
signal is_rho_zero : STD_LOGIC;
signal is_inv_zero : STD_LOGIC;
signal is_r0_zero : STD_LOGIC;
signal is_delta_less_than_0 : STD_LOGIC;
begin
controller : controller_solving_key_equation_5
Port Map(
clk => clk,
rst => rst,
limit_number_of_iterations => limit_number_of_iterations,
last_polynomial_coefficient => last_polynomial_coefficient,
is_inv_zero => is_inv_zero,
is_r0_zero => is_r0_zero,
is_delta_less_than_0 => is_delta_less_than_0,
is_rho_zero => is_rho_zero,
signal_inv => signal_inv,
key_equation_found => key_equation_found,
write_enable_s => write_enable_s,
write_enable_r => write_enable_r,
write_enable_v => write_enable_v,
write_enable_u => write_enable_u,
sel_mult_r_inv => sel_mult_r_inv,
last_u_value => last_u_value,
change_s_v => change_s_v,
change_r_u => change_r_u,
shift_r_u => shift_r_u,
reg_value_s_rst => reg_value_s_rst,
reg_value_s_ce => reg_value_s_ce,
reg_value_r_rst => reg_value_r_rst,
reg_value_r_ce => reg_value_r_ce,
reg_value_v_rst => reg_value_v_rst,
reg_value_v_ce => reg_value_v_ce,
reg_value_u_rst => reg_value_u_rst,
reg_value_u_ce => reg_value_u_ce,
sel_reg_rho_rst_value => sel_reg_rho_rst_value,
reg_rho_rst => reg_rho_rst,
reg_rho_ce => reg_rho_ce,
ctr_delta_ce => ctr_delta_ce,
ctr_delta_load => ctr_delta_load,
ctr_delta_rst => ctr_delta_rst,
reg_new_value_s_rst => reg_new_value_s_rst,
reg_new_value_s_ce => reg_new_value_s_ce,
reg_new_value_r_rst => reg_new_value_r_rst,
reg_new_value_r_ce => reg_new_value_r_ce,
reg_new_value_v_ce => reg_new_value_v_ce,
reg_new_value_u_rst => reg_new_value_u_rst,
reg_new_value_u_ce => reg_new_value_u_ce,
reg_new_value_u0_ce => reg_new_value_u0_ce,
ctr_load_value_ce => ctr_load_value_ce,
ctr_load_value_rst => ctr_load_value_rst,
ctr_store_value_ce => ctr_store_value_ce,
ctr_store_value_rst => ctr_store_value_rst,
ctr_number_of_iterations_ce => ctr_number_of_iterations_ce,
ctr_number_of_iterations_rst => ctr_number_of_iterations_rst
);
reg_value_s : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_s_d,
clk => clk,
rst => reg_value_s_rst,
rst_value => reg_value_s_rst_value,
ce => reg_value_s_ce,
q => reg_value_s_q
);
reg_value_r : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_r_d,
clk => clk,
rst => reg_value_r_rst,
rst_value => reg_value_r_rst_value,
ce => reg_value_r_ce,
q => reg_value_r_q
);
reg_value_v : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_v_d,
clk => clk,
rst => reg_value_v_rst,
rst_value => reg_value_v_rst_value,
ce => reg_value_v_ce,
q => reg_value_v_q
);
reg_value_u : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_u_d,
clk => clk,
rst => reg_value_u_rst,
rst_value => reg_value_u_rst_value,
ce => reg_value_u_ce,
q => reg_value_u_q
);
reg_rho : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_rho_d,
clk => clk,
rst => reg_rho_rst,
rst_value => reg_rho_rst_value,
ce => reg_rho_ce,
q => reg_rho_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_delta : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+1,
decrement_value => 1
)
Port Map(
d => ctr_delta_d,
clk => clk,
ce => ctr_delta_ce,
load => ctr_delta_load,
rst => ctr_delta_rst,
rst_value => ctr_delta_rst_value,
q => ctr_delta_q
);
mult_s_rho_r_inv: mult_gf_2_m
Generic Map (
gf_2_m => gf_2_m
)
Port Map (
a => mult_s_rho_r_inv_a,
b => mult_s_rho_r_inv_b,
o => mult_s_rho_r_inv_o
);
mult_v_rho: mult_gf_2_m
Generic Map (
gf_2_m => gf_2_m
)
Port Map (
a => mult_v_rho_a,
b => mult_v_rho_b,
o => mult_v_rho_o
);
reg_new_value_s : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_s_d,
clk => clk,
rst => reg_new_value_s_rst,
rst_value => reg_new_value_s_rst_value,
ce => reg_new_value_s_ce,
q => reg_new_value_s_q
);
reg_new_value_r : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_r_d,
clk => clk,
rst => reg_new_value_r_rst,
rst_value => reg_new_value_r_rst_value,
ce => reg_new_value_r_ce,
q => reg_new_value_r_q
);
reg_new_value_v : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_v_d,
clk => clk,
ce => reg_new_value_v_ce,
q => reg_new_value_v_q
);
reg_new_value_u : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_u_d,
clk => clk,
rst => reg_new_value_u_rst,
rst_value => reg_new_value_u_rst_value,
ce => reg_new_value_u_ce,
q => reg_new_value_u_q
);
reg_new_value_u0 : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_u0_d,
clk => clk,
ce => reg_new_value_u0_ce,
q => reg_new_value_u0_q
);
ctr_number_of_iterations : counter_rst_nbits
Generic Map(
size => size_final_degree+1,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_number_of_iterations_ce,
rst => ctr_number_of_iterations_rst,
rst_value => ctr_number_of_iterations_rst_value,
q => ctr_number_of_iterations_q
);
ctr_load_value : counter_rst_nbits
Generic Map(
size => size_final_degree+2,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_load_value_ce,
rst => ctr_load_value_rst,
rst_value => ctr_load_value_rst_value,
q => ctr_load_value_q
);
ctr_store_value : counter_rst_nbits
Generic Map(
size => size_final_degree+2,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_store_value_ce,
rst => ctr_store_value_rst,
rst_value => ctr_store_value_rst_value,
q => ctr_store_value_q
);
reg_delay_store_value : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_delay_store_value_d,
clk => clk,
ce => '1',
q => reg_delay_store_value_q
);
reg_value_s_d <= value_s;
reg_value_r_d <= value_r;
reg_value_v_d <= value_v;
reg_value_u_d <= value_u;
reg_rho_d <= mult_s_rho_r_inv_o;
reg_rho_rst_value <= reg_rho_rst_value_0 & sel_reg_rho_rst_value;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_delta_d <= std_logic_vector(to_signed(-1, size_final_degree+1) - signed(ctr_delta_q));
mult_s_rho_r_inv_a <= reg_inv_q when sel_mult_r_inv = '1' else
reg_rho_q;
mult_s_rho_r_inv_b <= reg_value_r_q when sel_mult_r_inv = '1' else
reg_value_s_q;
mult_v_rho_a <= reg_rho_q;
mult_v_rho_b <= reg_value_v_q;
add_s_rho_r <= mult_s_rho_r_inv_o xor reg_value_r_q;
add_v_rho_u <= mult_v_rho_o xor reg_value_u_q;
reg_new_value_s_d <= reg_value_r_q when change_s_v = '1' else
reg_value_s_q;
reg_new_value_r_d <= reg_value_s_q when change_r_u = '1' else
add_s_rho_r;
reg_new_value_v_d <= reg_value_u_q when change_s_v = '1' else
reg_value_v_q;
reg_new_value_u_d <= reg_value_v_q when change_r_u = '1' else
add_v_rho_u;
reg_new_value_u0_d <= add_v_rho_u;
new_value_inv <= reg_new_value_s_q;
new_value_s <= reg_new_value_s_q;
new_value_v <= reg_new_value_v_q;
new_value_r <= reg_new_value_r_q;
new_value_u <= reg_new_value_u0_q when last_u_value = '1' else
reg_new_value_u_q;
address_value_s <= ctr_load_value_q;
address_value_r <= ctr_load_value_q;
address_value_v <= ctr_load_value_q;
address_value_u <= ctr_load_value_q;
reg_delay_store_value_d <= ctr_store_value_q;
address_new_value_s <= ctr_store_value_q;
address_new_value_r <= reg_delay_store_value_q when shift_r_u = '1' else
ctr_store_value_q;
address_new_value_v <= ctr_store_value_q;
address_new_value_u <= reg_delay_store_value_q when shift_r_u = '1' else
ctr_store_value_q;
limit_number_of_iterations <= '1' when (ctr_number_of_iterations_q = std_logic_vector(to_unsigned(2*final_degree - 1, size_final_degree+1))) else '0';
last_polynomial_coefficient <= '1' when (ctr_store_value_q = std_logic_vector(to_unsigned(2*final_degree - 1, size_final_degree+2))) else '0';
is_inv_zero <= '1' when (reg_inv_q = std_logic_vector(to_unsigned(0, gf_2_m))) else '0';
is_rho_zero <= '1' when (reg_rho_q = std_logic_vector(to_unsigned(0, gf_2_m))) else '0';
is_r0_zero <= '1' when (reg_value_r_q = std_logic_vector(to_unsigned(0, gf_2_m))) else '0';
is_delta_less_than_0 <= '1' when (signed(ctr_delta_q) < to_signed(0, size_final_degree+1)) else '0';
end Behavioral;
|
<reponame>umarcor/neorv32<filename>setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd<gh_stars>100-1000
-- #################################################################################################
-- # << NEORV32 - Processor Top Qsys component with AvalonMM Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # (c) "NIOS-2", "Qsys", "Platform Designer" and "AvalonMM" are trademarks of Intel. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, <NAME>. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) <NAME> #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_qsys is
generic (
GUI_CLOCK_FREQUENCY : integer := 100000000;
GUI_EMABLE_INTERNAL_IMEM : integer := 1;
GUI_IMEM_SIZE : integer := 16;
GUI_EMABLE_INTERNAL_DMEM : integer := 1;
GUI_DMEM_SIZE : integer := 8;
GUI_ENABLE_BOOTLOADER : integer := 0;
GUI_ENABLE_AVALONMM : integer := 1;
GUI_ENABLE_UART0 : integer := 1;
GUI_ENABLE_UART1 : integer := 0;
GUI_ENABLE_GPIO : integer := 0
);
port (
-- Global control --
clk_i : in std_logic := '0'; -- global clock, rising edge
rstn_i : in std_logic := '0'; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_logic_vector(63 downto 0); -- parallel output
gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel output
-- UART0 --
uart0_txd_o : out std_logic; -- UART0 send data
uart0_rxd_i : in std_logic := '0'; -- UART0 receive data
-- UART1 --
uart1_txd_o : out std_logic; -- UART0 send data
uart1_rxd_i : in std_logic := '0'; -- UART0 receive data
-- AvalonMM interface
read : out std_logic;
write : out std_logic;
waitrequest : in std_logic := '0';
byteenable : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 0);
writedata : out std_logic_vector(31 downto 0);
readdata : in std_logic_vector(31 downto 0) := (others => '0')
);
end entity;
architecture neorv32_qsys_rtl of neorv32_qsys is
signal gpio_i_ulogic : std_ulogic_vector(63 downto 0);
signal gpio_o_ulogic : std_ulogic_vector(63 downto 0);
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag
signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address
signal wb_dat_i : std_ulogic_vector(31 downto 0); -- read data
signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data
signal wb_we_o : std_ulogic; -- read/write
signal wb_sel_o : std_ulogic_vector(03 downto 0); -- byte enable
signal wb_stb_o : std_ulogic; -- strobe
signal wb_cyc_o : std_ulogic; -- valid cycle
signal wb_lock_o : std_ulogic; -- exclusive access request
signal wb_ack_i : std_ulogic; -- transfer acknowledge
signal wb_err_i : std_ulogic; -- transfer error
signal reset : std_logic;
function integer2bool(integer_value : integer := 0) return boolean is
begin
if integer_value = 0 then
return false;
else
return true;
end if;
end function;
begin
-- The Core Of The Problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_top_inst: neorv32_top
generic map (
-- General --
CLOCK_FREQUENCY => GUI_CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN => integer2bool(GUI_ENABLE_BOOTLOADER), -- implement processor-internal bootloader?
HW_THREAD_ID => 0, -- hardware thread id (hartid)
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => false, -- implement atomic extension?
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension?
-- Extension Options --
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
CPU_IPB_ENTRIES => 2, -- entries is instruction prefetch buffer, has to be a power of 2
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS => 0, -- number of regions (0..64)
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => 4, -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_IMEM), -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => GUI_IMEM_SIZE*1024, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_DMEM), -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => GUI_DMEM_SIZE*1024, -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_EN => false, -- implement instruction cache
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- External memory interface --
MEM_EXT_EN => integer2bool(GUI_ENABLE_AVALONMM), -- implement external memory bus interface?
MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled)
MEM_EXT_PIPE_MODE => false, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false
-- Stream link interface (SLINK) --
SLINK_NUM_TX => 0, -- number of TX links (0..8)
SLINK_NUM_RX => 0, -- number of TX links (0..8)
SLINK_TX_FIFO => 1, -- TX fifo depth, has to be a power of two
SLINK_RX_FIFO => 1, -- RX fifo depth, has to be a power of two
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH => 0, -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE => (x"FFFFFFFF"), -- trigger type: 0=level, 1=edge
XIRQ_TRIGGER_POLARITY => (x"FFFFFFFF"), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
-- Processor peripherals --
IO_GPIO_EN => integer2bool(GUI_ENABLE_GPIO), -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART0_EN => integer2bool(GUI_ENABLE_UART0), -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => integer2bool(GUI_ENABLE_UART1), -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => false, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => false, -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN => true, -- implement watch dog timer (WDT)?
IO_TRNG_EN => false, -- implement true random number generator (TRNG)?
IO_CFS_EN => false, -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic
IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits
IO_NEOLED_EN => false, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO => 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
)
port map (
-- Global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
jtag_trst_i => '0', -- low-active TAP reset (optional)
jtag_tck_i => '0', -- serial clock
jtag_tdi_i => '0', -- serial data input
jtag_tdo_o => open, -- serial data output
jtag_tms_i => '0', -- mode select
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
wb_tag_o => wb_tag_o, -- tag
wb_adr_o => wb_adr_o, -- address
wb_dat_i => wb_dat_i, -- read data
wb_dat_o => wb_dat_o, -- write data
wb_we_o => wb_we_o, -- read/write
wb_sel_o => wb_sel_o, -- byte enable
wb_stb_o => wb_stb_o, -- strobe
wb_cyc_o => wb_cyc_o, -- valid cycle
wb_lock_o => wb_lock_o, -- exclusive access request
wb_ack_i => wb_ack_i, -- transfer acknowledge
wb_err_i => wb_err_i, -- transfer error
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o => open, -- indicates an executed FENCE operation
fencei_o => open, -- indicates an executed FENCEI operation
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
slink_tx_dat_o => open, -- output data
slink_tx_val_o => open, -- valid output
slink_tx_rdy_i => (others => 'L'), -- ready to send
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
slink_rx_dat_i => (others => (others => 'U')), -- input data
slink_rx_val_i => (others => 'L'), -- valid input
slink_rx_rdy_o => open, -- ready to receive
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => gpio_o_ulogic, -- parallel output
gpio_i => gpio_i_ulogic, -- parallel input
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd_o, -- UART0 send data
uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o => uart1_txd_o, -- UART1 send data
uart1_rxd_i => uart1_rxd_i, -- UART1 receive data
uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o => open, -- SPI serial clock
spi_sdo_o => open, -- controller data out, peripheral data in
spi_sdi_i => '0', -- controller data in, peripheral data out
spi_csn_o => open, -- SPI CS
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io => open, -- twi serial data line
twi_scl_io => open, -- twi serial clock line
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o => open, -- pwm channels
-- Custom Functions Subsystem IO --
cfs_in_i => (others => '0'), -- custom inputs
cfs_out_o => open, -- custom outputs
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o => open, -- async serial data line
-- System time --
mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true)
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
xirq_i => (others => '0'), -- IRQ channels
-- Interrupts --
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i => '0', -- machine software interrupt
mext_irq_i => '0' -- machine external interrupt
);
-- Convert between std_logic / std_ulogic
gpio_o <= std_logic_vector(gpio_o_ulogic);
gpio_i_ulogic <= std_ulogic_vector(gpio_i);
reset <= not(rstn_i);
-- Wishbone to AvalonMM brdige
read <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0';
write <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0';
address <= std_logic_vector(wb_adr_o);
writedata <= std_logic_vector(wb_dat_o);
byteenable <= std_logic_vector(wb_sel_o);
wb_dat_i <= std_ulogic_vector(readdata);
wb_ack_i <= not(waitrequest);
wb_err_i <= '0';
end architecture;
|
--
-- File Name: TbUtilPkg.vhd
-- Design Unit Name: TbUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: <NAME> email: <EMAIL>
-- Contributor(s):
-- <NAME> email: <EMAIL>
--
-- Package Defines
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 11/1999: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 10/2013 2013.10 Split out Text Utilities
-- 11/2016 2016.11 First Public Release Version
-- Updated naming for consistency.
-- 04/2018 2018.04 Added RequestTransaction, WaitForTransaction, Toggle, WaitForToggle for bit.
-- Added Increment and WaitForToggle for integer.
--
--
-- Copyright (c) 1999 - 2018 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
library ieee ;
use ieee.std_logic_1164.all ;
library osvvm ;
use osvvm.AlertLogPkg.all ;
use osvvm.TranscriptPkg.all ;
package TbUtilPkg is
constant CLK_ACTIVE : std_logic := '1' ;
constant t_sim_resolution : time := std.env.resolution_limit ; -- VHDL-2008
-- constant t_sim_resolution : time := 1 ns ; -- for non VHDL-2008 simulators
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean ;
------------------------------------------------------------
-- RequestTransaction
-- Transaction initiation side of handshaking
-- Pairs with WaitForTransaction or one of its variations
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) ;
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) ;
------------------------------------------------------------
-- WaitForTransaction
-- Model side of handshaking
-- Pairs with RequestTransaction
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) ;
-- Variation for model that stops waiting when TimeOut is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) ;
-- Set Ack to Model starting value
procedure StartTransaction ( signal Ack : Out std_logic ) ;
-- Set Ack to Model finishing value
procedure FinishTransaction ( signal Ack : Out std_logic ) ;
-- If a transaction is pending, return true
function TransactionPending ( signal Rdy : In std_logic ) return boolean ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) ;
procedure Toggle ( signal Sig : InOut std_logic ) ;
procedure ToggleHS ( signal Sig : InOut std_logic ) ;
function IsToggle ( signal Sig : In std_logic ) return boolean ;
procedure WaitForToggle ( signal Sig : In std_logic ) ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) ;
procedure Toggle ( signal Sig : InOut bit ) ;
procedure ToggleHS ( signal Sig : InOut bit ) ;
function IsToggle ( signal Sig : In bit ) return boolean ;
procedure WaitForToggle ( signal Sig : In bit ) ;
-- Integer type versions
procedure Increment ( signal Sig : InOut integer ; constant RollOverValue : in integer := 0) ;
procedure WaitForToggle ( signal Sig : In integer ) ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) ;
-- resolved_barrier : summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer ;
subtype integer_barrier is resolved_barrier integer ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
------------------------------------------------------------
-- Deprecated subprogram names
-- Maintaining backward compatibility using aliases
------------------------------------------------------------
-- History of RequestTransaction / WaitForTransaction
alias RequestAction is RequestTransaction [std_logic, std_logic] ;
alias WaitForRequest is WaitForTransaction [std_logic, std_logic, std_logic] ;
-- History of WaitForToggle
alias WaitOnToggle is WaitForToggle [std_logic] ;
-- History of WaitForBarrier
alias WayPointBlock is WaitForBarrier [std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic_vector] ;
-- Backward compatible name
alias SyncToClk is WaitForClock [std_logic, time] ;
------------------------------------------------------------
-- Deprecated
-- subsumed by WaitForTransaction with Ack and TimeOut.
-- TimeOut works exactly like IntReq
------------------------------------------------------------
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) ;
procedure StrobeAck ( signal Ack : Out std_logic ) ;
end TbUtilPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body TbUtilPkg is
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return found_one ; -- found a one
end function OneHot ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return TRUE ; -- all zero or found a one
end function ZeroOneHot ;
------------------------------------------------------------
-- RequestTransaction
-- Transaction initiation side of handshaking
-- Pairs with WaitForTransaction or one of its variations
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
------------------------------------------------------------
-- WaitForTransaction
-- Model side of handshaking
-- Pairs with RequestTransaction
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
end procedure WaitForTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
end procedure WaitForTransaction ;
-- Variation for model that stops waiting when TimeOut is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) is
variable AckTime : time ;
variable FoundRdy : boolean ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Ready or Time out
if (Rdy /= '1' and TimeOut /= Polarity) then
wait until Rdy = '1' or TimeOut = Polarity ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
FoundRdy := Rdy = '1' ;
-- align to clock if Rdy or TimeOut does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
if FoundRdy then
-- Model active and owns the record
Ack <= '0' ; -- #3
end if ;
end procedure WaitForTransaction ;
-- Set Ack to Model starting value
-- Pairs with WaitForTransactionOrIrq above
procedure StartTransaction ( signal Ack : Out std_logic ) is
begin
Ack <= '0' ;
end procedure StartTransaction ;
-- Set Ack to Model finishing value
-- Pairs with WaitForTransactionOrIrq above
procedure FinishTransaction ( signal Ack : Out std_logic ) is
begin
-- End of Cycle
Ack <= '1' ;
end procedure FinishTransaction ;
-- If a transaction is pending, return true
-- Used to detect presence of transaction stream,
-- such as an interrupt handler
function TransactionPending (
signal Rdy : In std_logic
) return boolean is
begin
return Rdy = '1' ;
end function TransactionPending ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
-- Find Start of Transaction
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
end procedure WaitForTransaction ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
type stdulogic_indexby_stdulogic is array (std_ulogic) of std_ulogic;
constant toggle_sl_table : stdulogic_indexby_stdulogic := (
'0' => '1',
'L' => '1',
others => '0'
);
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec, "osvvm.TbUtilPkg.Toggle: Delay value < 0 ns") ;
end if ;
Sig <= toggle_sl_table(Sig) after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In std_logic ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In std_logic ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec,
"osvvm.TbUtilPkg.Toggle: Delay value < 0 ns", WARNING) ;
end if ;
Sig <= not Sig after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In bit ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In bit ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Integer type versions
procedure Increment ( signal Sig : InOut integer ; constant RollOverValue : in integer := 0) is
begin
if Sig = integer'high then
Sig <= RollOverValue ;
else
Sig <= Sig + 1 ;
end if ;
end procedure Increment ;
procedure WaitForToggle ( signal Sig : In integer ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
------------------------------------------------------------
-- resolved_barrier
-- summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer is
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
else
result := s(i) + 1; -- removes the initialization requirement
end if ;
end loop ;
return result ;
end function resolved_barrier ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) is
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until other process' Rdy is at level 1
if SyncIn /= '1' then
wait until SyncIn = '1' ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) is
constant ALL_ONE : std_logic_vector(SyncInV'Range) := (others => '1');
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until all other process' Rdy is at level 1
if SyncInV /= ALL_ONE then
wait until SyncInV = ALL_ONE ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) is
begin
if delay > t_sim_resolution then
wait for delay - t_sim_resolution ;
end if ;
wait until Clk = CLK_ACTIVE ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) is
begin
for i in 1 to NumberOfClocks loop
wait until Clk = CLK_ACTIVE ;
end loop ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable = Polarity ;
end procedure WaitForClock ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) is
begin
if not A then
wait until A ;
end if ;
end procedure WaitForLevel ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) is
begin
if A /= Polarity then
-- wait on A until A = Polarity ;
if Polarity = '1' then
wait until A = '1' ;
else
wait until A = '0' ;
end if ;
end if ;
end procedure WaitForLevel ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) is
constant HIGH_TIME : time := Period * DutyCycle ;
constant LOW_TIME : time := Period - HIGH_TIME ;
begin
if HIGH_TIME = LOW_TIME then
loop
Clk <= toggle_sl_table(Clk) after HIGH_TIME ;
wait on Clk ;
end loop ;
else
-- Schedule s.t. all assignments after the first occur on delta cycle 0
Clk <= '0', '1' after LOW_TIME ;
wait for period - 1 ns ; -- allows after on future Clk <= '0'
loop
Clk <= '0' after 1 ns, '1' after LOW_TIME + 1 ns ;
wait for period ;
end loop ;
end if ;
end procedure CreateClock ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
variable LastLogTime, ObservedPeriod : time ;
begin
wait until Clk = CLK_ACTIVE ;
LastLogTime := now ;
-- Check First HowMany clocks
for i in 1 to HowMany loop
wait until Clk = CLK_ACTIVE ;
ObservedPeriod := now - LastLogTime ;
AffirmIf(AlertLogID, ObservedPeriod = Period,
"CheckClockPeriod: " & ClkName & " Period: " & to_string(ObservedPeriod) &
" = Expected " & to_string(Period)) ;
LastLogTime := now ;
end loop ;
wait ;
end procedure CheckClockPeriod ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
begin
CheckClockPeriod (
AlertLogID => ALERTLOG_DEFAULT_ID,
Clk => Clk,
Period => Period,
ClkName => ClkName,
HowMany => HowMany
) ;
end procedure CheckClockPeriod ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) is
begin
wait until Clk = CLK_ACTIVE ;
Reset <= ResetActive after tpd ;
wait for Period - t_sim_resolution ;
wait until Clk = CLK_ACTIVE ;
Reset <= not ResetActive after tpd ;
wait ;
end procedure CreateReset ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
-- Does not log the value of Reset at time 0.
for_ever : loop
wait on Reset ;
if Reset = ResetActive then
LOG(AlertLogID, ResetName & " now active", INFO) ;
print("") ;
elsif Reset = not ResetActive then
LOG(AlertLogID, ResetName & " now inactive", INFO) ;
print("") ;
else
LOG(AlertLogID, ResetName & " = " & to_string(Reset), INFO) ;
print("") ;
end if ;
end loop for_ever ;
end procedure LogReset ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
LogReset (
AlertLogID => ALERTLOG_DEFAULT_ID,
Reset => Reset,
ResetActive => ResetActive,
ResetName => ResetName,
LogLevel => LogLevel
) ;
end procedure LogReset ;
------------------------------------------------------------
-- Deprecated
-- subsumed by WaitForTransaction with Ack and TimeOut.
-- TimeOut works exactly like IntReq
------------------------------------------------------------
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) is
variable AckTime : time ;
constant POLARITY : std_logic := '1' ;
begin
AckTime := NOW ;
-- Find Ready or Time out
if (Rdy /= '1' and IntReq /= POLARITY) then
wait until Rdy = '1' or IntReq = POLARITY ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if Rdy or IntReq does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) is
begin
-- Wait for Model to be done
wait until Ack = '1' ;
end procedure ;
procedure StrobeAck ( signal Ack : Out std_logic ) is
begin
-- Model done, drive rising edge on Ack
Ack <= '0' ;
wait for 0 ns ;
Ack <= '1' ;
end procedure ;
end TbUtilPkg ;
|
-- ----------------------------------------------------------------------------
-- FILE: ba16x16x26.vhd
-- DESCRIPTION: This file implements only array of adders required for
-- Booth multiplier design. Booth array is truncated to
-- 26 bits in order to save some hardware.
-- DATE: Aug 24, 2001
-- AUTHOR(s): Microelectronic Centre Design Team
-- MUMEC
-- Bounds Green Road
-- N11 2NQ London
-- REVISIONS:
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity ba16x16x26mac is
port (
x: in std_logic_vector (15 downto 0);
y: in std_logic_vector (15 downto 0);
c: out std_logic_vector (25 downto 0);
s: out std_logic_vector (25 downto 0);
clk: in std_logic;
en: in std_logic;
reset: in std_logic
);
end ba16x16x26mac;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture ba16x16x26mac_arch of ba16x16x26mac is
-- Latched x and y
signal xl1, xl2, xl3, xl4: std_logic_vector(15 downto 0);
signal yl1, yl2, yl3, yl4: std_logic_vector(15 downto 0);
-- Partial sums, carries and latces
signal a1, b1: std_logic_vector(14 downto 0);
signal a2, b2: std_logic_vector(16 downto 0);
signal a2l, b2l: std_logic_vector(16 downto 0); -- Latch B
signal a3, b3: std_logic_vector(18 downto 0);
signal a4, b4: std_logic_vector(18 downto 0);
signal a4l, b4l: std_logic_vector(18 downto 0); -- Latch C
signal a5, b5: std_logic_vector(18 downto 0);
signal a6, b6: std_logic_vector(18 downto 0);
signal a6l, b6l: std_logic_vector(18 downto 0); -- Latch D
signal a7, b7: std_logic_vector(18 downto 0);
signal al1, bl1: std_logic_vector(3 downto 0);
signal al2, bl2: std_logic_vector(7 downto 0);
-- Logic connstants
signal zero: std_logic;
-- Component declarations
use work.components.rowfirstt12;
use work.components.row14;
use work.components.row16;
for all:rowfirstt12 use entity work.rowfirstt12(rowfirstt12_arch);
for all:row14 use entity work.row14(row14_arch);
for all:row16 use entity work.row16(row16_arch);
begin
zero <= '0';
-- Latches
latch: process(clk, reset)
begin
if reset = '0' then
xl1 <= (others => '0');
yl1 <= (others => '0');
xl2 <= (others => '0');
yl2 <= (others => '0');
xl3 <= (others => '0');
yl3 <= (others => '0');
xl4 <= (others => '0');
yl4 <= (others => '0');
a2l <= (others => '0');
b2l <= (others => '0');
a4l <= (others => '0');
b4l <= (others => '0');
a6l <= (others => '0');
b6l <= (others => '0');
al1 <= (others => '0');
bl1 <= (others => '0');
al2 <= (others => '0');
bl2 <= (others => '0');
elsif clk'event and clk = '1' then
if en = '1' then
xl1 <= x;
yl1 <= y;
xl2 <= xl1;
yl2 <= yl1;
xl3 <= xl2;
yl3 <= yl2;
xl4 <= xl3;
yl4 <= yl3;
a2l <= a2;
b2l <= b2;
a4l <= a4;
b4l <= b4;
a6l <= a6;
b6l <= b6;
al1 <= a4(1 downto 0) & a3(1 downto 0);
bl1 <= b4(1 downto 0) & b3(1 downto 0);
al2 <= a6(1 downto 0) & a5(1 downto 0) & al1;
bl2 <= b6(1 downto 0) & b5(1 downto 0) & bl1;
end if;
end if;
end process latch;
-- Rows of adders
-- Latch A
row1: rowfirstt12
port map(x => xl1(15 downto 4), y => yl1(3 downto 0),
sbit => zero, s => a1, c => b1);
row2: row14
port map(x => xl1(15 downto 2), y => yl1(5 downto 3),
a => a1, b => b1, s => a2, c => b2);
-- Latch B
row3: row16
port map(x => xl2, y => yl2(7 downto 5),
a => a2l, b => b2l, s => a3, c => b3);
row4: row16
port map(x => xl2, y => yl2(9 downto 7),
a => a3(18 downto 2), b => b3(18 downto 2), s => a4, c => b4);
-- Latch C
row5: row16
port map(x => xl3, y => yl3(11 downto 9),
a => a4l(18 downto 2), b => b4l(18 downto 2), s => a5, c => b5);
row6: row16
port map(x => xl3, y => yl3(13 downto 11),
a => a5(18 downto 2), b => b5(18 downto 2), s => a6, c => b6);
-- Latch D
row7: row16
port map(x => xl4, y => yl4(15 downto 13),
a => a6l(18 downto 2), b => b6l(18 downto 2), s => a7, c => b7);
c <= a7(17 downto 0) & al2;
s <= b7(17 downto 0) & bl2;
end ba16x16x26mac_arch;
|
<filename>2019-eln-inverter-linejessye/Inverter_test/hdl/risingDetector_tester_test.vhd
ARCHITECTURE test OF risingDetector_tester IS
constant clockFrequency: real := 100.0E6;
constant clockPeriod: time := 1.0/clockFrequency * 1 sec;
signal sClock: std_uLogic := '1';
constant inputFrequency: real := clockFrequency / 5.0;
constant inputPeriod: time := 1.0/inputFrequency * 1 sec;
signal sInput: std_uLogic := '0';
BEGIN
------------------------------------------------------------------------------
-- clock and reset
reset <= '1', '0' after 4*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after 9.0/10.0 * clockPeriod;
------------------------------------------------------------------------------
-- mains
sInput <= not sInput after inputPeriod/2;
sigIn <= sInput;
END ARCHITECTURE test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_nt is
port(
clk : in std_logic;
SI : in BIT;
SO : out BIT
);
end nt_nt;
architecture nt_nt of nt_nt is
signal tmp: bit_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
tmp <= tmp(6 downto 0)& SI;
end if;
end process;
SO <= tmp(7);
end nt_nt;
--clk=20Mhz; SI= random 10ns;
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Fri Mar 18 09:01:57 2022
-- Host : labx running 64-bit Ubuntu 20.04.1 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ eth_xcvr_gt_channel_sim_netlist.vhdl
-- Design : eth_xcvr_gt_channel
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcvu9p-flga2104-2L-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer is
port (
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC;
rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer is
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rxresetdone_out(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_0 is
port (
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC;
txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_0 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_0 is
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => txresetdone_out(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_1 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
gtpowergood_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_sequential_sm_reset_all_reg[0]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\FSM_sequential_sm_reset_all_reg[0]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_1 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_1 is
signal gtpowergood_sync : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
\FSM_sequential_sm_reset_all[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF0FAF00CFFFCFFF"
)
port map (
I0 => gtpowergood_sync,
I1 => \FSM_sequential_sm_reset_all_reg[0]\,
I2 => Q(2),
I3 => Q(0),
I4 => \FSM_sequential_sm_reset_all_reg[0]_0\,
I5 => Q(1),
O => E(0)
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtpowergood_out(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => gtpowergood_sync,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_10 is
port (
gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC;
sm_reset_rx_cdr_to_sat_reg : out STD_LOGIC;
rxcdrlock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
sm_reset_rx_cdr_to_clr_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
plllock_rx_sync : in STD_LOGIC;
sm_reset_rx_cdr_to_clr : in STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC;
sm_reset_rx_cdr_to_sat : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_10 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_10;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_10 is
signal \^gtwiz_reset_rx_cdr_stable_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
signal sm_reset_rx_cdr_to_clr_i_2_n_0 : STD_LOGIC;
signal \^sm_reset_rx_cdr_to_sat_reg\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of rxprogdivreset_out_i_2 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_2 : label is "soft_lutpair2";
begin
gtwiz_reset_rx_cdr_stable_out(0) <= \^gtwiz_reset_rx_cdr_stable_out\(0);
sm_reset_rx_cdr_to_sat_reg <= \^sm_reset_rx_cdr_to_sat_reg\;
\FSM_sequential_sm_reset_rx[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A000AC0C000C0"
)
port map (
I0 => \^sm_reset_rx_cdr_to_sat_reg\,
I1 => \FSM_sequential_sm_reset_rx_reg[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => plllock_rx_sync,
I5 => Q(2),
O => \FSM_sequential_sm_reset_rx_reg[1]\
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rxcdrlock_out(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => \^gtwiz_reset_rx_cdr_stable_out\(0),
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
rxprogdivreset_out_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sm_reset_rx_cdr_to_sat,
I1 => \^gtwiz_reset_rx_cdr_stable_out\(0),
O => \^sm_reset_rx_cdr_to_sat_reg\
);
sm_reset_rx_cdr_to_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF0800AAAA"
)
port map (
I0 => sm_reset_rx_cdr_to_clr_i_2_n_0,
I1 => sm_reset_rx_cdr_to_clr_reg,
I2 => Q(2),
I3 => plllock_rx_sync,
I4 => Q(0),
I5 => sm_reset_rx_cdr_to_clr,
O => \FSM_sequential_sm_reset_rx_reg[2]\
);
sm_reset_rx_cdr_to_clr_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"00EF"
)
port map (
I0 => sm_reset_rx_cdr_to_sat,
I1 => \^gtwiz_reset_rx_cdr_stable_out\(0),
I2 => Q(2),
I3 => Q(1),
O => sm_reset_rx_cdr_to_clr_i_2_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_2 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
in0 : in STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[0]_1\ : in STD_LOGIC;
gtwiz_reset_rx_pll_and_datapath_dly : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_2 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_2 is
signal \FSM_sequential_sm_reset_rx[2]_i_3_n_0\ : STD_LOGIC;
signal gtwiz_reset_rx_datapath_dly : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
\FSM_sequential_sm_reset_rx[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFAAEA"
)
port map (
I0 => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\,
I1 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
I2 => \FSM_sequential_sm_reset_rx_reg[0]\,
I3 => Q(0),
I4 => \FSM_sequential_sm_reset_rx_reg[0]_0\,
I5 => \FSM_sequential_sm_reset_rx_reg[0]_1\,
O => E(0)
);
\FSM_sequential_sm_reset_rx[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"01010100"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(2),
I3 => gtwiz_reset_rx_datapath_dly,
I4 => gtwiz_reset_rx_pll_and_datapath_dly,
O => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => in0,
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => gtwiz_reset_rx_datapath_dly,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_3 is
port (
gtwiz_reset_rx_pll_and_datapath_dly : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
in0 : in STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC;
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_3 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_3 is
signal \^gtwiz_reset_rx_pll_and_datapath_dly\ : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
gtwiz_reset_rx_pll_and_datapath_dly <= \^gtwiz_reset_rx_pll_and_datapath_dly\;
\FSM_sequential_sm_reset_rx[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F55EA55EA55EA55E"
)
port map (
I0 => Q(0),
I1 => \^gtwiz_reset_rx_pll_and_datapath_dly\,
I2 => Q(2),
I3 => Q(1),
I4 => \FSM_sequential_sm_reset_rx_reg[0]\,
I5 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
O => D(0)
);
\FSM_sequential_sm_reset_rx[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F800FF00F800FFF"
)
port map (
I0 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
I1 => \FSM_sequential_sm_reset_rx_reg[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => Q(2),
I5 => \^gtwiz_reset_rx_pll_and_datapath_dly\,
O => D(1)
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => in0,
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => \^gtwiz_reset_rx_pll_and_datapath_dly\,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_4 is
port (
gtwiz_reset_tx_datapath_dly : out STD_LOGIC;
in0 : in STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_4 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_4 is
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => in0,
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => gtwiz_reset_tx_datapath_dly,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_5 is
port (
gtwiz_reset_tx_pll_and_datapath_dly : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
in0 : in STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_5 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_5 is
signal \^gtwiz_reset_tx_pll_and_datapath_dly\ : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[1]_i_1\ : label is "soft_lutpair0";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
gtwiz_reset_tx_pll_and_datapath_dly <= \^gtwiz_reset_tx_pll_and_datapath_dly\;
\FSM_sequential_sm_reset_tx[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F3E"
)
port map (
I0 => \^gtwiz_reset_tx_pll_and_datapath_dly\,
I1 => Q(1),
I2 => Q(0),
I3 => Q(2),
O => D(0)
);
\FSM_sequential_sm_reset_tx[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FF1"
)
port map (
I0 => \^gtwiz_reset_tx_pll_and_datapath_dly\,
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
O => D(1)
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => in0,
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => \^gtwiz_reset_tx_pll_and_datapath_dly\,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_6 is
port (
\FSM_sequential_sm_reset_rx_reg[0]\ : out STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC;
gtwiz_userclk_rx_active_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
sm_reset_rx_timer_clr_reg : in STD_LOGIC;
gtwiz_reset_rx_any_sync : in STD_LOGIC;
\gen_gtwizard_gtye4.rxuserrdy_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC;
sm_reset_rx_timer_clr_reg_0 : in STD_LOGIC;
sm_reset_rx_timer_clr_reg_1 : in STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC;
sm_reset_rx_pll_timer_sat : in STD_LOGIC;
sm_reset_rx_timer_sat : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_6 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_6 is
signal gtwiz_reset_userclk_rx_active_sync : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
signal rxuserrdy_out_i_2_n_0 : STD_LOGIC;
signal sm_reset_rx_timer_clr_i_2_n_0 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
\FSM_sequential_sm_reset_rx[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2023202000000000"
)
port map (
I0 => rxuserrdy_out_i_2_n_0,
I1 => Q(1),
I2 => Q(2),
I3 => \FSM_sequential_sm_reset_rx_reg[0]_0\,
I4 => sm_reset_rx_pll_timer_sat,
I5 => Q(0),
O => \FSM_sequential_sm_reset_rx_reg[1]\
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtwiz_userclk_rx_active_out(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => gtwiz_reset_userclk_rx_active_sync,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
rxuserrdy_out_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFAAF00000800"
)
port map (
I0 => Q(2),
I1 => rxuserrdy_out_i_2_n_0,
I2 => Q(1),
I3 => Q(0),
I4 => gtwiz_reset_rx_any_sync,
I5 => \gen_gtwizard_gtye4.rxuserrdy_int\,
O => \FSM_sequential_sm_reset_rx_reg[2]\
);
rxuserrdy_out_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sm_reset_rx_timer_clr_reg,
I1 => sm_reset_rx_timer_sat,
I2 => gtwiz_reset_userclk_rx_active_sync,
O => rxuserrdy_out_i_2_n_0
);
sm_reset_rx_timer_clr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EBAE28A2"
)
port map (
I0 => sm_reset_rx_timer_clr_i_2_n_0,
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => sm_reset_rx_timer_clr_reg,
O => \FSM_sequential_sm_reset_rx_reg[0]\
);
sm_reset_rx_timer_clr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8888CC00C0C0FFFF"
)
port map (
I0 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
I1 => sm_reset_rx_timer_clr_reg_0,
I2 => gtwiz_reset_userclk_rx_active_sync,
I3 => sm_reset_rx_timer_clr_reg_1,
I4 => Q(2),
I5 => Q(1),
O => sm_reset_rx_timer_clr_i_2_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_7 is
port (
\FSM_sequential_sm_reset_tx_reg[2]\ : out STD_LOGIC;
\FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_active_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
sm_reset_tx_timer_clr_reg : in STD_LOGIC;
gtwiz_reset_tx_any_sync : in STD_LOGIC;
\gen_gtwizard_gtye4.txuserrdy_int\ : in STD_LOGIC;
\FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC;
gtwiz_reset_tx_pll_and_datapath_dly : in STD_LOGIC;
gtwiz_reset_tx_datapath_dly : in STD_LOGIC;
sm_reset_tx_pll_timer_clr : in STD_LOGIC;
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC;
sm_reset_tx_timer_clr_reg_0 : in STD_LOGIC;
plllock_tx_sync : in STD_LOGIC;
\FSM_sequential_sm_reset_tx_reg[0]_0\ : in STD_LOGIC;
\FSM_sequential_sm_reset_tx_reg[0]_1\ : in STD_LOGIC;
sm_reset_tx_pll_timer_sat : in STD_LOGIC;
sm_reset_tx_timer_sat : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_7 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_7 is
signal \FSM_sequential_sm_reset_tx[2]_i_3_n_0\ : STD_LOGIC;
signal gtwiz_reset_userclk_tx_active_sync : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
signal sm_reset_tx_timer_clr_i_2_n_0 : STD_LOGIC;
signal txuserrdy_out_i_2_n_0 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
\FSM_sequential_sm_reset_tx[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEFFFEEEEE"
)
port map (
I0 => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\,
I1 => \FSM_sequential_sm_reset_tx_reg[0]\,
I2 => gtwiz_reset_tx_pll_and_datapath_dly,
I3 => gtwiz_reset_tx_datapath_dly,
I4 => sm_reset_tx_pll_timer_clr,
I5 => Q(0),
O => E(0)
);
\FSM_sequential_sm_reset_tx[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F0000088888888"
)
port map (
I0 => \FSM_sequential_sm_reset_tx_reg[0]_0\,
I1 => gtwiz_reset_userclk_tx_active_sync,
I2 => sm_reset_tx_pll_timer_clr,
I3 => \FSM_sequential_sm_reset_tx_reg[0]_1\,
I4 => sm_reset_tx_pll_timer_sat,
I5 => Q(0),
O => \FSM_sequential_sm_reset_tx[2]_i_3_n_0\
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtwiz_userclk_tx_active_out(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => gtwiz_reset_userclk_tx_active_sync,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
sm_reset_tx_timer_clr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EBEB282B"
)
port map (
I0 => sm_reset_tx_timer_clr_i_2_n_0,
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => sm_reset_tx_timer_clr_reg,
O => \FSM_sequential_sm_reset_tx_reg[2]\
);
sm_reset_tx_timer_clr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A0C0A0C0F0F000F0"
)
port map (
I0 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
I1 => gtwiz_reset_userclk_tx_active_sync,
I2 => sm_reset_tx_timer_clr_reg_0,
I3 => Q(0),
I4 => plllock_tx_sync,
I5 => Q(2),
O => sm_reset_tx_timer_clr_i_2_n_0
);
txuserrdy_out_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEFB000002AA"
)
port map (
I0 => txuserrdy_out_i_2_n_0,
I1 => Q(1),
I2 => Q(2),
I3 => Q(0),
I4 => gtwiz_reset_tx_any_sync,
I5 => \gen_gtwizard_gtye4.txuserrdy_int\,
O => \FSM_sequential_sm_reset_tx_reg[1]\
);
txuserrdy_out_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => sm_reset_tx_timer_sat,
I1 => sm_reset_tx_timer_clr_reg,
I2 => Q(2),
I3 => Q(1),
I4 => gtwiz_reset_userclk_tx_active_sync,
O => txuserrdy_out_i_2_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_8 is
port (
plllock_rx_sync : out STD_LOGIC;
i_in_out_reg_0 : out STD_LOGIC;
i_in_out_reg_1 : out STD_LOGIC;
i_in_out_reg_2 : out STD_LOGIC;
gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_done_int_reg : in STD_LOGIC;
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
gtwiz_reset_rx_done_int_reg_0 : in STD_LOGIC;
gtrxreset_out_reg : in STD_LOGIC;
sm_reset_rx_timer_sat : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_8 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_8;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_8 is
signal gtwiz_reset_rx_done_int : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
signal \^plllock_rx_sync\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of gtrxreset_out_i_2 : label is "soft_lutpair1";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
attribute SOFT_HLUTNM of sm_reset_rx_timer_clr_i_3 : label is "soft_lutpair1";
begin
plllock_rx_sync <= \^plllock_rx_sync\;
gtrxreset_out_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"20FFFF00"
)
port map (
I0 => \^plllock_rx_sync\,
I1 => gtrxreset_out_reg,
I2 => sm_reset_rx_timer_sat,
I3 => Q(1),
I4 => Q(0),
O => i_in_out_reg_1
);
gtwiz_reset_rx_done_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAC0FFFFAAC00000"
)
port map (
I0 => \^plllock_rx_sync\,
I1 => gtwiz_reset_rx_done_int_reg,
I2 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
I3 => Q(0),
I4 => gtwiz_reset_rx_done_int,
I5 => gtwiz_reset_rx_done_int_reg_0,
O => i_in_out_reg_0
);
gtwiz_reset_rx_done_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"44440000C0000000"
)
port map (
I0 => \^plllock_rx_sync\,
I1 => Q(1),
I2 => gtwiz_reset_rx_done_int_reg,
I3 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
I4 => Q(2),
I5 => Q(0),
O => gtwiz_reset_rx_done_int
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtwiz_reset_qpll0lock_in(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => \^plllock_rx_sync\,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
sm_reset_rx_timer_clr_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^plllock_rx_sync\,
I1 => Q(0),
O => i_in_out_reg_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_9 is
port (
plllock_tx_sync : out STD_LOGIC;
gtwiz_reset_tx_done_int_reg : out STD_LOGIC;
i_in_out_reg_0 : out STD_LOGIC;
sm_reset_tx_timer_sat_reg : out STD_LOGIC;
gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_done_int_reg_0 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC;
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC;
sm_reset_tx_timer_sat : in STD_LOGIC;
gttxreset_out_reg : in STD_LOGIC;
gtwiz_reset_tx_any_sync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_9 : entity is "gtwizard_ultrascale_v1_7_12_bit_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_9;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_9 is
signal gtwiz_reset_tx_done_int : STD_LOGIC;
signal gtwiz_reset_tx_done_int_i_2_n_0 : STD_LOGIC;
signal i_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of i_in_meta : signal is "true";
signal i_in_sync1 : STD_LOGIC;
attribute async_reg of i_in_sync1 : signal is "true";
signal i_in_sync2 : STD_LOGIC;
attribute async_reg of i_in_sync2 : signal is "true";
signal i_in_sync3 : STD_LOGIC;
attribute async_reg of i_in_sync3 : signal is "true";
signal \^plllock_tx_sync\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of i_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
attribute KEEP of i_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
attribute KEEP of i_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
attribute KEEP of i_in_sync3_reg : label is "yes";
begin
plllock_tx_sync <= \^plllock_tx_sync\;
\FSM_sequential_sm_reset_tx[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"38000C0008000C00"
)
port map (
I0 => \^plllock_tx_sync\,
I1 => Q(1),
I2 => Q(2),
I3 => \FSM_sequential_sm_reset_tx_reg[0]\,
I4 => Q(0),
I5 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
O => i_in_out_reg_0
);
gttxreset_out_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => sm_reset_tx_timer_sat,
I1 => gttxreset_out_reg,
I2 => \^plllock_tx_sync\,
I3 => gtwiz_reset_tx_any_sync,
I4 => Q(2),
I5 => Q(1),
O => sm_reset_tx_timer_sat_reg
);
gtwiz_reset_tx_done_int_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => gtwiz_reset_tx_done_int_i_2_n_0,
I1 => gtwiz_reset_tx_done_int,
I2 => gtwiz_reset_tx_done_int_reg_0,
O => gtwiz_reset_tx_done_int_reg
);
gtwiz_reset_tx_done_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444F44444"
)
port map (
I0 => Q(0),
I1 => \^plllock_tx_sync\,
I2 => sm_reset_tx_timer_sat,
I3 => gttxreset_out_reg,
I4 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
I5 => Q(1),
O => gtwiz_reset_tx_done_int_i_2_n_0
);
gtwiz_reset_tx_done_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"3000404000004040"
)
port map (
I0 => \^plllock_tx_sync\,
I1 => Q(1),
I2 => Q(2),
I3 => \FSM_sequential_sm_reset_tx_reg[0]\,
I4 => Q(0),
I5 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
O => gtwiz_reset_tx_done_int
);
i_in_meta_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtwiz_reset_qpll0lock_in(0),
Q => i_in_meta,
R => '0'
);
i_in_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync3,
Q => \^plllock_tx_sync\,
R => '0'
);
i_in_sync1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_meta,
Q => i_in_sync1,
R => '0'
);
i_in_sync2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync1,
Q => i_in_sync2,
R => '0'
);
i_in_sync3_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => i_in_sync2,
Q => i_in_sync3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_rx is
port (
gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_srcclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
lopt : out STD_LOGIC;
lopt_1 : in STD_LOGIC;
lopt_2 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_rx;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_rx is
signal \<const1>\ : STD_LOGIC;
signal \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta\ : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta\ : signal is "true";
signal \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync\ : STD_LOGIC;
attribute async_reg of \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync\ : signal is "true";
signal \^gtwiz_userclk_rx_usrclk2_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^lopt\ : STD_LOGIC;
signal \^lopt_1\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst\ : label is "PRIMITIVE";
attribute OPT_MODIFIED : string;
attribute OPT_MODIFIED of \gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst\ : label is "MLO";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta_reg\ : label is "yes";
attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg\ : label is std.standard.true;
attribute KEEP of \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg\ : label is "yes";
begin
\^lopt\ <= lopt_1;
\^lopt_1\ <= lopt_2;
gtwiz_userclk_rx_active_out(0) <= \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync\;
gtwiz_userclk_rx_usrclk2_out(0) <= \^gtwiz_userclk_rx_usrclk2_out\(0);
lopt <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst\: unisim.vcomponents.BUFG_GT
generic map(
SIM_DEVICE => "ULTRASCALE",
STARTUP_SYNC => "FALSE"
)
port map (
CE => \^lopt\,
CEMASK => '0',
CLR => \^lopt_1\,
CLRMASK => '0',
DIV(2 downto 0) => B"000",
I => gtwiz_userclk_rx_srcclk_out(0),
O => \^gtwiz_userclk_rx_usrclk2_out\(0)
);
\gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \^gtwiz_userclk_rx_usrclk2_out\(0),
CE => '1',
CLR => gtwiz_userclk_rx_reset_in(0),
D => '1',
Q => \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta\
);
\gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \^gtwiz_userclk_rx_usrclk2_out\(0),
CE => '1',
CLR => gtwiz_userclk_rx_reset_in(0),
D => \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta\,
Q => \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_tx is
port (
gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_srcclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
lopt : out STD_LOGIC;
lopt_1 : in STD_LOGIC;
lopt_2 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_tx;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_tx is
signal \<const1>\ : STD_LOGIC;
signal \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta\ : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta\ : signal is "true";
signal \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync\ : STD_LOGIC;
attribute async_reg of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync\ : signal is "true";
signal \^gtwiz_userclk_tx_usrclk2_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^lopt\ : STD_LOGIC;
signal \^lopt_1\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst\ : label is "PRIMITIVE";
attribute OPT_MODIFIED : string;
attribute OPT_MODIFIED of \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst\ : label is "MLO";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta_reg\ : label is "yes";
attribute ASYNC_REG_boolean of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync_reg\ : label is std.standard.true;
attribute KEEP of \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync_reg\ : label is "yes";
begin
\^lopt\ <= lopt_1;
\^lopt_1\ <= lopt_2;
gtwiz_userclk_tx_active_out(0) <= \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync\;
gtwiz_userclk_tx_usrclk2_out(0) <= \^gtwiz_userclk_tx_usrclk2_out\(0);
lopt <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst\: unisim.vcomponents.BUFG_GT
generic map(
SIM_DEVICE => "ULTRASCALE",
STARTUP_SYNC => "FALSE"
)
port map (
CE => \^lopt\,
CEMASK => '0',
CLR => \^lopt_1\,
CLRMASK => '0',
DIV(2 downto 0) => B"000",
I => gtwiz_userclk_tx_srcclk_out(0),
O => \^gtwiz_userclk_tx_usrclk2_out\(0)
);
\gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \^gtwiz_userclk_tx_usrclk2_out\(0),
CE => '1',
CLR => gtwiz_userclk_tx_reset_in(0),
D => '1',
Q => \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta\
);
\gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \^gtwiz_userclk_tx_usrclk2_out\(0),
CE => '1',
CLR => gtwiz_userclk_tx_reset_in(0),
D => \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta\,
Q => \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_channel is
port (
\gen_gtwizard_gtye4.gtpowergood_int\ : out STD_LOGIC;
gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_0\ : out STD_LOGIC;
\gen_gtwizard_gtye4.gtrxreset_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.gttxreset_ch_int\ : in STD_LOGIC;
gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.rxprogdivreset_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.rxuserrdy_int\ : in STD_LOGIC;
gtwiz_userclk_rx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
TXRATE : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.txprogdivreset_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.txuserrdy_int\ : in STD_LOGIC;
gtwiz_userclk_tx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
lopt : in STD_LOGIC;
lopt_1 : in STD_LOGIC;
lopt_2 : out STD_LOGIC;
lopt_3 : out STD_LOGIC;
lopt_4 : in STD_LOGIC;
lopt_5 : in STD_LOGIC;
lopt_6 : out STD_LOGIC;
lopt_7 : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_channel is
signal \^gen_gtwizard_gtye4.gtpowergood_int\ : STD_LOGIC;
signal \^gtwiz_userclk_rx_srcclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_tx_srcclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_1\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_19\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_203\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_204\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_205\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_206\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_207\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_208\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_209\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_240\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_241\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_256\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_257\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_34\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_366\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_367\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_368\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_369\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_370\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_371\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_372\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_373\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_374\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_375\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_376\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_39\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_45\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_5\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_57\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_6\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_60\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_62\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_63\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_67\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_7\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
signal \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
signal \^lopt_2\ : STD_LOGIC;
signal \^lopt_3\ : STD_LOGIC;
signal \xlnx_opt_\ : STD_LOGIC;
signal \xlnx_opt__1\ : STD_LOGIC;
signal \xlnx_opt__2\ : STD_LOGIC;
signal \xlnx_opt__3\ : STD_LOGIC;
attribute OPT_MODIFIED : string;
attribute OPT_MODIFIED of BUFG_GT_SYNC : label is "MLO";
attribute OPT_MODIFIED of BUFG_GT_SYNC_1 : label is "MLO";
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
begin
\^lopt_2\ <= lopt_4;
\^lopt_3\ <= lopt_5;
\gen_gtwizard_gtye4.gtpowergood_int\ <= \^gen_gtwizard_gtye4.gtpowergood_int\;
gtwiz_userclk_rx_srcclk_out(0) <= \^gtwiz_userclk_rx_srcclk_out\(0);
gtwiz_userclk_tx_srcclk_out(0) <= \^gtwiz_userclk_tx_srcclk_out\(0);
lopt_2 <= \xlnx_opt_\;
lopt_3 <= \xlnx_opt__1\;
lopt_6 <= \xlnx_opt__2\;
lopt_7 <= \xlnx_opt__3\;
BUFG_GT_SYNC: unisim.vcomponents.BUFG_GT_SYNC
port map (
CE => lopt,
CESYNC => \xlnx_opt_\,
CLK => \^gtwiz_userclk_rx_srcclk_out\(0),
CLR => lopt_1,
CLRSYNC => \xlnx_opt__1\
);
BUFG_GT_SYNC_1: unisim.vcomponents.BUFG_GT_SYNC
port map (
CE => \^lopt_2\,
CESYNC => \xlnx_opt__2\,
CLK => \^gtwiz_userclk_tx_srcclk_out\(0),
CLR => \^lopt_3\,
CLRSYNC => \xlnx_opt__3\
);
\gen_powergood_delay.intclk_rrst_n_r[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_gtwizard_gtye4.gtpowergood_int\,
O => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_0\
);
\gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST\: unisim.vcomponents.GTYE4_CHANNEL
generic map(
ACJTAG_DEBUG_MODE => '0',
ACJTAG_MODE => '0',
ACJTAG_RESET => '0',
ADAPT_CFG0 => X"0000",
ADAPT_CFG1 => X"FB1C",
ADAPT_CFG2 => X"0000",
ALIGN_COMMA_DOUBLE => "FALSE",
ALIGN_COMMA_ENABLE => B"0000000000",
ALIGN_COMMA_WORD => 1,
ALIGN_MCOMMA_DET => "FALSE",
ALIGN_MCOMMA_VALUE => B"1010000011",
ALIGN_PCOMMA_DET => "FALSE",
ALIGN_PCOMMA_VALUE => B"0101111100",
A_RXOSCALRESET => '0',
A_RXPROGDIVRESET => '0',
A_RXTERMINATION => '1',
A_TXDIFFCTRL => B"01100",
A_TXPROGDIVRESET => '0',
CBCC_DATA_SOURCE_SEL => "ENCODED",
CDR_SWAP_MODE_EN => '0',
CFOK_PWRSVE_EN => '1',
CHAN_BOND_KEEP_ALIGN => "FALSE",
CHAN_BOND_MAX_SKEW => 1,
CHAN_BOND_SEQ_1_1 => B"0000000000",
CHAN_BOND_SEQ_1_2 => B"0000000000",
CHAN_BOND_SEQ_1_3 => B"0000000000",
CHAN_BOND_SEQ_1_4 => B"0000000000",
CHAN_BOND_SEQ_1_ENABLE => B"1111",
CHAN_BOND_SEQ_2_1 => B"0000000000",
CHAN_BOND_SEQ_2_2 => B"0000000000",
CHAN_BOND_SEQ_2_3 => B"0000000000",
CHAN_BOND_SEQ_2_4 => B"0000000000",
CHAN_BOND_SEQ_2_ENABLE => B"1111",
CHAN_BOND_SEQ_2_USE => "FALSE",
CHAN_BOND_SEQ_LEN => 1,
CH_HSPMUX => X"9090",
CKCAL1_CFG_0 => B"0100000001000000",
CKCAL1_CFG_1 => B"0001000001000000",
CKCAL1_CFG_2 => B"0010000000001000",
CKCAL1_CFG_3 => B"0000000000000000",
CKCAL2_CFG_0 => B"0100000001000000",
CKCAL2_CFG_1 => B"0000000001000000",
CKCAL2_CFG_2 => B"0001000000000000",
CKCAL2_CFG_3 => B"0000000000000000",
CKCAL2_CFG_4 => B"0000000000000000",
CLK_CORRECT_USE => "FALSE",
CLK_COR_KEEP_IDLE => "FALSE",
CLK_COR_MAX_LAT => 20,
CLK_COR_MIN_LAT => 18,
CLK_COR_PRECEDENCE => "TRUE",
CLK_COR_REPEAT_WAIT => 0,
CLK_COR_SEQ_1_1 => B"0000000000",
CLK_COR_SEQ_1_2 => B"0000000000",
CLK_COR_SEQ_1_3 => B"0000000000",
CLK_COR_SEQ_1_4 => B"0000000000",
CLK_COR_SEQ_1_ENABLE => B"1111",
CLK_COR_SEQ_2_1 => B"0000000000",
CLK_COR_SEQ_2_2 => B"0000000000",
CLK_COR_SEQ_2_3 => B"0000000000",
CLK_COR_SEQ_2_4 => B"0000000000",
CLK_COR_SEQ_2_ENABLE => B"1111",
CLK_COR_SEQ_2_USE => "FALSE",
CLK_COR_SEQ_LEN => 1,
CPLL_CFG0 => X"01FA",
CPLL_CFG1 => X"002B",
CPLL_CFG2 => X"0002",
CPLL_CFG3 => X"0000",
CPLL_FBDIV => 2,
CPLL_FBDIV_45 => 5,
CPLL_INIT_CFG0 => X"02B2",
CPLL_LOCK_CFG => X"01E8",
CPLL_REFCLK_DIV => 1,
CTLE3_OCAP_EXT_CTRL => B"000",
CTLE3_OCAP_EXT_EN => '0',
DDI_CTRL => B"00",
DDI_REALIGN_WAIT => 15,
DEC_MCOMMA_DETECT => "FALSE",
DEC_PCOMMA_DETECT => "FALSE",
DEC_VALID_COMMA_ONLY => "FALSE",
DELAY_ELEC => '0',
DMONITOR_CFG0 => B"00" & X"00",
DMONITOR_CFG1 => X"00",
ES_CLK_PHASE_SEL => '0',
ES_CONTROL => B"000000",
ES_ERRDET_EN => "FALSE",
ES_EYE_SCAN_EN => "FALSE",
ES_HORZ_OFFSET => X"000",
ES_PRESCALE => B"00000",
ES_QUALIFIER0 => X"0000",
ES_QUALIFIER1 => X"0000",
ES_QUALIFIER2 => X"0000",
ES_QUALIFIER3 => X"0000",
ES_QUALIFIER4 => X"0000",
ES_QUALIFIER5 => X"0000",
ES_QUALIFIER6 => X"0000",
ES_QUALIFIER7 => X"0000",
ES_QUALIFIER8 => X"0000",
ES_QUALIFIER9 => X"0000",
ES_QUAL_MASK0 => X"0000",
ES_QUAL_MASK1 => X"0000",
ES_QUAL_MASK2 => X"0000",
ES_QUAL_MASK3 => X"0000",
ES_QUAL_MASK4 => X"0000",
ES_QUAL_MASK5 => X"0000",
ES_QUAL_MASK6 => X"0000",
ES_QUAL_MASK7 => X"0000",
ES_QUAL_MASK8 => X"0000",
ES_QUAL_MASK9 => X"0000",
ES_SDATA_MASK0 => X"0000",
ES_SDATA_MASK1 => X"0000",
ES_SDATA_MASK2 => X"0000",
ES_SDATA_MASK3 => X"0000",
ES_SDATA_MASK4 => X"0000",
ES_SDATA_MASK5 => X"0000",
ES_SDATA_MASK6 => X"0000",
ES_SDATA_MASK7 => X"0000",
ES_SDATA_MASK8 => X"0000",
ES_SDATA_MASK9 => X"0000",
EYESCAN_VP_RANGE => 0,
EYE_SCAN_SWAP_EN => '0',
FTS_DESKEW_SEQ_ENABLE => B"1111",
FTS_LANE_DESKEW_CFG => B"1111",
FTS_LANE_DESKEW_EN => "FALSE",
GEARBOX_MODE => B"10001",
ISCAN_CK_PH_SEL2 => '0',
LOCAL_MASTER => '1',
LPBK_BIAS_CTRL => 4,
LPBK_EN_RCAL_B => '0',
LPBK_EXT_RCAL => B"1000",
LPBK_IND_CTRL0 => 5,
LPBK_IND_CTRL1 => 5,
LPBK_IND_CTRL2 => 5,
LPBK_RG_CTRL => 2,
OOBDIVCTL => B"00",
OOB_PWRUP => '0',
PCI3_AUTO_REALIGN => "OVR_1K_BLK",
PCI3_PIPE_RX_ELECIDLE => '0',
PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
PCI3_RX_FIFO_DISABLE => '0',
PCIE3_CLK_COR_EMPTY_THRSH => B"00000",
PCIE3_CLK_COR_FULL_THRSH => B"010000",
PCIE3_CLK_COR_MAX_LAT => B"00100",
PCIE3_CLK_COR_MIN_LAT => B"00000",
PCIE3_CLK_COR_THRSH_TIMER => B"001000",
PCIE_64B_DYN_CLKSW_DIS => "FALSE",
PCIE_BUFG_DIV_CTRL => X"3500",
PCIE_GEN4_64BIT_INT_EN => "FALSE",
PCIE_PLL_SEL_MODE_GEN12 => B"10",
PCIE_PLL_SEL_MODE_GEN3 => B"10",
PCIE_PLL_SEL_MODE_GEN4 => B"10",
PCIE_RXPCS_CFG_GEN3 => X"0AA5",
PCIE_RXPMA_CFG => X"280A",
PCIE_TXPCS_CFG_GEN3 => X"2CA4",
PCIE_TXPMA_CFG => X"280A",
PCS_PCIE_EN => "FALSE",
PCS_RSVD0 => X"0000",
PD_TRANS_TIME_FROM_P2 => X"03C",
PD_TRANS_TIME_NONE_P2 => X"19",
PD_TRANS_TIME_TO_P2 => X"64",
PREIQ_FREQ_BST => 3,
RATE_SW_USE_DRP => '1',
RCLK_SIPO_DLY_ENB => '0',
RCLK_SIPO_INV_EN => '0',
RTX_BUF_CML_CTRL => B"111",
RTX_BUF_TERM_CTRL => B"11",
RXBUFRESET_TIME => B"00011",
RXBUF_ADDR_MODE => "FAST",
RXBUF_EIDLE_HI_CNT => B"1000",
RXBUF_EIDLE_LO_CNT => B"0000",
RXBUF_EN => "FALSE",
RXBUF_RESET_ON_CB_CHANGE => "TRUE",
RXBUF_RESET_ON_COMMAALIGN => "FALSE",
RXBUF_RESET_ON_EIDLE => "FALSE",
RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
RXBUF_THRESH_OVFLW => 0,
RXBUF_THRESH_OVRD => "FALSE",
RXBUF_THRESH_UNDFLW => 4,
RXCDRFREQRESET_TIME => B"00001",
RXCDRPHRESET_TIME => B"00001",
RXCDR_CFG0 => X"0003",
RXCDR_CFG0_GEN3 => X"0003",
RXCDR_CFG1 => X"0000",
RXCDR_CFG1_GEN3 => X"0000",
RXCDR_CFG2 => X"01E9",
RXCDR_CFG2_GEN2 => B"10" & X"69",
RXCDR_CFG2_GEN3 => X"0269",
RXCDR_CFG2_GEN4 => X"0164",
RXCDR_CFG3 => X"0010",
RXCDR_CFG3_GEN2 => B"01" & X"0",
RXCDR_CFG3_GEN3 => X"0010",
RXCDR_CFG3_GEN4 => X"0010",
RXCDR_CFG4 => X"5CF6",
RXCDR_CFG4_GEN3 => X"5CF6",
RXCDR_CFG5 => X"B46B",
RXCDR_CFG5_GEN3 => X"146B",
RXCDR_FR_RESET_ON_EIDLE => '0',
RXCDR_HOLD_DURING_EIDLE => '0',
RXCDR_LOCK_CFG0 => X"2201",
RXCDR_LOCK_CFG1 => X"9FFF",
RXCDR_LOCK_CFG2 => X"0000",
RXCDR_LOCK_CFG3 => X"0000",
RXCDR_LOCK_CFG4 => X"0000",
RXCDR_PH_RESET_ON_EIDLE => '0',
RXCFOK_CFG0 => X"0000",
RXCFOK_CFG1 => X"8015",
RXCFOK_CFG2 => X"02AE",
RXCKCAL1_IQ_LOOP_RST_CFG => X"0004",
RXCKCAL1_I_LOOP_RST_CFG => X"0004",
RXCKCAL1_Q_LOOP_RST_CFG => X"0004",
RXCKCAL2_DX_LOOP_RST_CFG => X"0004",
RXCKCAL2_D_LOOP_RST_CFG => X"0004",
RXCKCAL2_S_LOOP_RST_CFG => X"0004",
RXCKCAL2_X_LOOP_RST_CFG => X"0004",
RXDFELPMRESET_TIME => B"0001111",
RXDFELPM_KL_CFG0 => X"0000",
RXDFELPM_KL_CFG1 => X"A082",
RXDFELPM_KL_CFG2 => X"0100",
RXDFE_CFG0 => X"0A00",
RXDFE_CFG1 => X"0000",
RXDFE_GC_CFG0 => X"0000",
RXDFE_GC_CFG1 => X"8000",
RXDFE_GC_CFG2 => X"FFE0",
RXDFE_H2_CFG0 => X"0000",
RXDFE_H2_CFG1 => X"0002",
RXDFE_H3_CFG0 => X"0000",
RXDFE_H3_CFG1 => X"8002",
RXDFE_H4_CFG0 => X"0000",
RXDFE_H4_CFG1 => X"8002",
RXDFE_H5_CFG0 => X"0000",
RXDFE_H5_CFG1 => X"8002",
RXDFE_H6_CFG0 => X"0000",
RXDFE_H6_CFG1 => X"8002",
RXDFE_H7_CFG0 => X"0000",
RXDFE_H7_CFG1 => X"8002",
RXDFE_H8_CFG0 => X"0000",
RXDFE_H8_CFG1 => X"8002",
RXDFE_H9_CFG0 => X"0000",
RXDFE_H9_CFG1 => X"8002",
RXDFE_HA_CFG0 => X"0000",
RXDFE_HA_CFG1 => X"8002",
RXDFE_HB_CFG0 => X"0000",
RXDFE_HB_CFG1 => X"8002",
RXDFE_HC_CFG0 => X"0000",
RXDFE_HC_CFG1 => X"8002",
RXDFE_HD_CFG0 => X"0000",
RXDFE_HD_CFG1 => X"8002",
RXDFE_HE_CFG0 => X"0000",
RXDFE_HE_CFG1 => X"8002",
RXDFE_HF_CFG0 => X"0000",
RXDFE_HF_CFG1 => X"8002",
RXDFE_KH_CFG0 => X"8000",
RXDFE_KH_CFG1 => X"FE00",
RXDFE_KH_CFG2 => X"281C",
RXDFE_KH_CFG3 => X"4120",
RXDFE_OS_CFG0 => X"2000",
RXDFE_OS_CFG1 => X"8000",
RXDFE_UT_CFG0 => X"0000",
RXDFE_UT_CFG1 => X"0003",
RXDFE_UT_CFG2 => X"0000",
RXDFE_VP_CFG0 => X"0000",
RXDFE_VP_CFG1 => X"0033",
RXDLY_CFG => X"0010",
RXDLY_LCFG => X"0030",
RXELECIDLE_CFG => "SIGCFG_4",
RXGBOX_FIFO_INIT_RD_ADDR => 3,
RXGEARBOX_EN => "TRUE",
RXISCANRESET_TIME => B"00001",
RXLPM_CFG => X"0000",
RXLPM_GC_CFG => X"F800",
RXLPM_KH_CFG0 => X"0000",
RXLPM_KH_CFG1 => X"A002",
RXLPM_OS_CFG0 => X"0000",
RXLPM_OS_CFG1 => X"8002",
RXOOB_CFG => B"000000110",
RXOOB_CLK_CFG => "PMA",
RXOSCALRESET_TIME => B"00011",
RXOUT_DIV => 1,
RXPCSRESET_TIME => B"00011",
RXPHBEACON_CFG => X"0000",
RXPHDLY_CFG => X"2070",
RXPHSAMP_CFG => X"2100",
RXPHSLIP_CFG => X"9933",
RXPH_MONITOR_SEL => B"00000",
RXPI_CFG0 => X"3006",
RXPI_CFG1 => B"0000000000000000",
RXPMACLK_SEL => "DATA",
RXPMARESET_TIME => B"00011",
RXPRBS_ERR_LOOPBACK => '0',
RXPRBS_LINKACQ_CNT => 15,
RXREFCLKDIV2_SEL => '0',
RXSLIDE_AUTO_WAIT => 7,
RXSLIDE_MODE => "OFF",
RXSYNC_MULTILANE => '0',
RXSYNC_OVRD => '0',
RXSYNC_SKIP_DA => '0',
RX_AFE_CM_EN => '0',
RX_BIAS_CFG0 => X"12B0",
RX_BUFFER_CFG => B"000000",
RX_CAPFF_SARC_ENB => '0',
RX_CLK25_DIV => 7,
RX_CLKMUX_EN => '1',
RX_CLK_SLIP_OVRD => B"00000",
RX_CM_BUF_CFG => B"1010",
RX_CM_BUF_PD => '0',
RX_CM_SEL => 3,
RX_CM_TRIM => 10,
RX_CTLE_PWR_SAVING => '0',
RX_CTLE_RES_CTRL => B"0000",
RX_DATA_WIDTH => 64,
RX_DDI_SEL => B"000000",
RX_DEFER_RESET_BUF_EN => "TRUE",
RX_DEGEN_CTRL => B"111",
RX_DFELPM_CFG0 => 10,
RX_DFELPM_CFG1 => '1',
RX_DFELPM_KLKH_AGC_STUP_EN => '1',
RX_DFE_AGC_CFG1 => 4,
RX_DFE_KL_LPM_KH_CFG0 => 3,
RX_DFE_KL_LPM_KH_CFG1 => 2,
RX_DFE_KL_LPM_KL_CFG0 => B"11",
RX_DFE_KL_LPM_KL_CFG1 => 2,
RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
RX_DISPERR_SEQ_MATCH => "TRUE",
RX_DIVRESET_TIME => B"00001",
RX_EN_CTLE_RCAL_B => '0',
RX_EN_SUM_RCAL_B => 0,
RX_EYESCAN_VS_CODE => B"0000000",
RX_EYESCAN_VS_NEG_DIR => '0',
RX_EYESCAN_VS_RANGE => B"10",
RX_EYESCAN_VS_UT_SIGN => '0',
RX_FABINT_USRCLK_FLOP => '0',
RX_I2V_FILTER_EN => '1',
RX_INT_DATAWIDTH => 2,
RX_PMA_POWER_SAVE => '0',
RX_PMA_RSV0 => X"002F",
RX_PROGDIV_CFG => 16.500000,
RX_PROGDIV_RATE => X"0000",
RX_RESLOAD_CTRL => B"0000",
RX_RESLOAD_OVRD => '0',
RX_SAMPLE_PERIOD => B"111",
RX_SIG_VALID_DLY => 11,
RX_SUM_DEGEN_AVTT_OVERITE => 1,
RX_SUM_DFETAPREP_EN => '0',
RX_SUM_IREF_TUNE => B"0000",
RX_SUM_PWR_SAVING => 0,
RX_SUM_RES_CTRL => B"0000",
RX_SUM_VCMTUNE => B"1001",
RX_SUM_VCM_BIAS_TUNE_EN => '1',
RX_SUM_VCM_OVWR => '0',
RX_SUM_VREF_TUNE => B"100",
RX_TUNE_AFE_OS => B"10",
RX_VREG_CTRL => B"010",
RX_VREG_PDB => '1',
RX_WIDEMODE_CDR => B"10",
RX_WIDEMODE_CDR_GEN3 => B"00",
RX_WIDEMODE_CDR_GEN4 => B"01",
RX_XCLK_SEL => "RXDES",
RX_XMODE_SEL => '0',
SAMPLE_CLK_PHASE => '0',
SAS_12G_MODE => '0',
SATA_BURST_SEQ_LEN => B"1111",
SATA_BURST_VAL => B"100",
SATA_CPLL_CFG => "VCO_3000MHZ",
SATA_EIDLE_VAL => B"100",
SHOW_REALIGN_COMMA => "TRUE",
SIM_DEVICE => "ULTRASCALE_PLUS",
SIM_MODE => "FAST",
SIM_RECEIVER_DETECT_PASS => "TRUE",
SIM_RESET_SPEEDUP => "TRUE",
SIM_TX_EIDLE_DRIVE_LEVEL => "Z",
SRSTMODE => '0',
TAPDLY_SET_TX => B"00",
TERM_RCAL_CFG => B"100001000000010",
TERM_RCAL_OVRD => B"001",
TRANS_TIME_RATE => X"0E",
TST_RSV0 => X"00",
TST_RSV1 => X"00",
TXBUF_EN => "FALSE",
TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
TXDLY_CFG => X"8010",
TXDLY_LCFG => X"0030",
TXDRV_FREQBAND => 3,
TXFE_CFG0 => B"0000001111000110",
TXFE_CFG1 => B"1111100000000000",
TXFE_CFG2 => B"1111100000000000",
TXFE_CFG3 => B"1111100000000000",
TXFIFO_ADDR_CFG => "LOW",
TXGBOX_FIFO_INIT_RD_ADDR => 4,
TXGEARBOX_EN => "TRUE",
TXOUT_DIV => 1,
TXPCSRESET_TIME => B"00011",
TXPHDLY_CFG0 => X"6070",
TXPHDLY_CFG1 => X"000E",
TXPH_CFG => X"0723",
TXPH_CFG2 => X"0000",
TXPH_MONITOR_SEL => B"00000",
TXPI_CFG0 => B"0011000000000000",
TXPI_CFG1 => B"0000000000000000",
TXPI_GRAY_SEL => '0',
TXPI_INVSTROBE_SEL => '0',
TXPI_PPM => '0',
TXPI_PPM_CFG => B"00000000",
TXPI_SYNFREQ_PPM => B"001",
TXPMARESET_TIME => B"00011",
TXREFCLKDIV2_SEL => '0',
TXSWBST_BST => 1,
TXSWBST_EN => 1,
TXSWBST_MAG => 4,
TXSYNC_MULTILANE => '0',
TXSYNC_OVRD => '0',
TXSYNC_SKIP_DA => '0',
TX_CLK25_DIV => 7,
TX_CLKMUX_EN => '1',
TX_DATA_WIDTH => 64,
TX_DCC_LOOP_RST_CFG => X"0004",
TX_DEEMPH0 => B"000000",
TX_DEEMPH1 => B"000000",
TX_DEEMPH2 => B"000000",
TX_DEEMPH3 => B"000000",
TX_DIVRESET_TIME => B"00001",
TX_DRIVE_MODE => "DIRECT",
TX_EIDLE_ASSERT_DELAY => B"100",
TX_EIDLE_DEASSERT_DELAY => B"011",
TX_FABINT_USRCLK_FLOP => '0',
TX_FIFO_BYP_EN => '0',
TX_IDLE_DATA_ZERO => '0',
TX_INT_DATAWIDTH => 2,
TX_LOOPBACK_DRIVE_HIZ => "FALSE",
TX_MAINCURSOR_SEL => '0',
TX_MARGIN_FULL_0 => B"1011000",
TX_MARGIN_FULL_1 => B"1010111",
TX_MARGIN_FULL_2 => B"1010101",
TX_MARGIN_FULL_3 => B"1010011",
TX_MARGIN_FULL_4 => B"1010001",
TX_MARGIN_LOW_0 => B"1001100",
TX_MARGIN_LOW_1 => B"1001011",
TX_MARGIN_LOW_2 => B"1001000",
TX_MARGIN_LOW_3 => B"1000010",
TX_MARGIN_LOW_4 => B"1000000",
TX_PHICAL_CFG0 => X"0020",
TX_PHICAL_CFG1 => X"0040",
TX_PI_BIASSET => 3,
TX_PMADATA_OPT => '0',
TX_PMA_POWER_SAVE => '0',
TX_PMA_RSV0 => X"0000",
TX_PMA_RSV1 => X"0000",
TX_PROGCLK_SEL => "PREPI",
TX_PROGDIV_CFG => 16.500000,
TX_PROGDIV_RATE => X"0000",
TX_RXDETECT_CFG => B"00" & X"032",
TX_RXDETECT_REF => 5,
TX_SAMPLE_PERIOD => B"111",
TX_SW_MEAS => B"00",
TX_VREG_CTRL => B"011",
TX_VREG_PDB => '1',
TX_VREG_VREFSEL => B"10",
TX_XCLK_SEL => "TXOUT",
USB_BOTH_BURST_IDLE => '0',
USB_BURSTMAX_U3WAKE => B"1111111",
USB_BURSTMIN_U3WAKE => B"1100011",
USB_CLK_COR_EQ_EN => '0',
USB_EXT_CNTL => '1',
USB_IDLEMAX_POLLING => B"1010111011",
USB_IDLEMIN_POLLING => B"0100101011",
USB_LFPSPING_BURST => B"000000101",
USB_LFPSPOLLING_BURST => B"000110001",
USB_LFPSPOLLING_IDLE_MS => B"000000100",
USB_LFPSU1EXIT_BURST => B"000011101",
USB_LFPSU2LPEXIT_BURST_MS => B"001100011",
USB_LFPSU3WAKE_BURST_MS => B"111110011",
USB_LFPS_TPERIOD => B"0011",
USB_LFPS_TPERIOD_ACCURATE => '1',
USB_MODE => '0',
USB_PCIE_ERR_REP_DIS => '0',
USB_PING_SATA_MAX_INIT => 21,
USB_PING_SATA_MIN_INIT => 12,
USB_POLL_SATA_MAX_BURST => 8,
USB_POLL_SATA_MIN_BURST => 4,
USB_RAW_ELEC => '0',
USB_RXIDLE_P0_CTRL => '1',
USB_TXIDLE_TUNE_ENABLE => '1',
USB_U1_SATA_MAX_WAKE => 7,
USB_U1_SATA_MIN_WAKE => 4,
USB_U2_SAS_MAX_COM => 64,
USB_U2_SAS_MIN_COM => 36,
USE_PCS_CLK_PHASE_SEL => '0',
Y_ALL_MODE => '0'
)
port map (
BUFGTCE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_0\,
BUFGTCEMASK(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_313\,
BUFGTCEMASK(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_314\,
BUFGTCEMASK(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_315\,
BUFGTDIV(8) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_368\,
BUFGTDIV(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_369\,
BUFGTDIV(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_370\,
BUFGTDIV(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_371\,
BUFGTDIV(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_372\,
BUFGTDIV(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_373\,
BUFGTDIV(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_374\,
BUFGTDIV(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_375\,
BUFGTDIV(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_376\,
BUFGTRESET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_1\,
BUFGTRSTMASK(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_316\,
BUFGTRSTMASK(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_317\,
BUFGTRSTMASK(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_318\,
CDRSTEPDIR => '0',
CDRSTEPSQ => '0',
CDRSTEPSX => '0',
CFGRESET => '0',
CLKRSVD0 => '0',
CLKRSVD1 => '0',
CPLLFBCLKLOST => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_2\,
CPLLFREQLOCK => '0',
CPLLLOCK => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_3\,
CPLLLOCKDETCLK => '0',
CPLLLOCKEN => '0',
CPLLPD => '1',
CPLLREFCLKLOST => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_4\,
CPLLREFCLKSEL(2 downto 0) => B"001",
CPLLRESET => '1',
DMONFIFORESET => '0',
DMONITORCLK => '0',
DMONITOROUT(15) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_203\,
DMONITOROUT(14) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_204\,
DMONITOROUT(13) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_205\,
DMONITOROUT(12) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_206\,
DMONITOROUT(11) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_207\,
DMONITOROUT(10) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_208\,
DMONITOROUT(9) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_209\,
DMONITOROUT(8) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_210\,
DMONITOROUT(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_211\,
DMONITOROUT(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_212\,
DMONITOROUT(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_213\,
DMONITOROUT(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_214\,
DMONITOROUT(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_215\,
DMONITOROUT(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_216\,
DMONITOROUT(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_217\,
DMONITOROUT(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_218\,
DMONITOROUTCLK => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_5\,
DRPADDR(9 downto 0) => B"0000000000",
DRPCLK => '0',
DRPDI(15 downto 0) => B"0000000000000000",
DRPDO(15) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_219\,
DRPDO(14) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_220\,
DRPDO(13) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_221\,
DRPDO(12) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_222\,
DRPDO(11) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_223\,
DRPDO(10) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_224\,
DRPDO(9) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_225\,
DRPDO(8) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_226\,
DRPDO(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_227\,
DRPDO(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_228\,
DRPDO(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_229\,
DRPDO(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_230\,
DRPDO(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_231\,
DRPDO(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_232\,
DRPDO(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_233\,
DRPDO(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_234\,
DRPEN => '0',
DRPRDY => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_6\,
DRPRST => '0',
DRPWE => '0',
EYESCANDATAERROR => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_7\,
EYESCANRESET => '0',
EYESCANTRIGGER => '0',
FREQOS => '0',
GTGREFCLK => '0',
GTNORTHREFCLK0 => '0',
GTNORTHREFCLK1 => '0',
GTPOWERGOOD => \^gen_gtwizard_gtye4.gtpowergood_int\,
GTREFCLK0 => '0',
GTREFCLK1 => '0',
GTREFCLKMONITOR => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_9\,
GTRSVD(15 downto 0) => B"0000000000000000",
GTRXRESET => \gen_gtwizard_gtye4.gtrxreset_int\,
GTRXRESETSEL => '0',
GTSOUTHREFCLK0 => '0',
GTSOUTHREFCLK1 => '0',
GTTXRESET => \gen_gtwizard_gtye4.gttxreset_ch_int\,
GTTXRESETSEL => '0',
GTYRXN => gtyrxn_in(0),
GTYRXP => gtyrxp_in(0),
GTYTXN => gtytxn_out(0),
GTYTXP => gtytxp_out(0),
INCPCTRL => '0',
LOOPBACK(2 downto 0) => B"000",
PCIEEQRXEQADAPTDONE => '0',
PCIERATEGEN3 => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_12\,
PCIERATEIDLE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_13\,
PCIERATEQPLLPD(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_299\,
PCIERATEQPLLPD(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_300\,
PCIERATEQPLLRESET(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_301\,
PCIERATEQPLLRESET(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_302\,
PCIERSTIDLE => '0',
PCIERSTTXSYNCSTART => '0',
PCIESYNCTXSYNCDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_14\,
PCIEUSERGEN3RDY => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_15\,
PCIEUSERPHYSTATUSRST => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_16\,
PCIEUSERRATEDONE => '0',
PCIEUSERRATESTART => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_17\,
PCSRSVDIN(15 downto 0) => B"0000000000000000",
PCSRSVDOUT(15) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_235\,
PCSRSVDOUT(14) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_236\,
PCSRSVDOUT(13) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_237\,
PCSRSVDOUT(12) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_238\,
PCSRSVDOUT(11) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_239\,
PCSRSVDOUT(10) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_240\,
PCSRSVDOUT(9) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_241\,
PCSRSVDOUT(8) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_242\,
PCSRSVDOUT(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_243\,
PCSRSVDOUT(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_244\,
PCSRSVDOUT(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_245\,
PCSRSVDOUT(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_246\,
PCSRSVDOUT(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_247\,
PCSRSVDOUT(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_248\,
PCSRSVDOUT(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_249\,
PCSRSVDOUT(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_250\,
PHYSTATUS => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_18\,
PINRSRVDAS(15) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_251\,
PINRSRVDAS(14) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_252\,
PINRSRVDAS(13) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_253\,
PINRSRVDAS(12) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_254\,
PINRSRVDAS(11) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_255\,
PINRSRVDAS(10) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_256\,
PINRSRVDAS(9) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_257\,
PINRSRVDAS(8) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_258\,
PINRSRVDAS(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_259\,
PINRSRVDAS(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_260\,
PINRSRVDAS(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_261\,
PINRSRVDAS(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_262\,
PINRSRVDAS(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_263\,
PINRSRVDAS(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_264\,
PINRSRVDAS(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_265\,
PINRSRVDAS(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_266\,
POWERPRESENT => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_19\,
QPLL0CLK => qpll0clk_in(0),
QPLL0FREQLOCK => '0',
QPLL0REFCLK => qpll0refclk_in(0),
QPLL1CLK => qpll1clk_in(0),
QPLL1FREQLOCK => '0',
QPLL1REFCLK => qpll1refclk_in(0),
RESETEXCEPTION => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_20\,
RESETOVRD => '0',
RX8B10BEN => '0',
RXAFECFOKEN => '1',
RXBUFRESET => '0',
RXBUFSTATUS(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_319\,
RXBUFSTATUS(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_320\,
RXBUFSTATUS(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_321\,
RXBYTEISALIGNED => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_21\,
RXBYTEREALIGN => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_22\,
RXCDRFREQRESET => '0',
RXCDRHOLD => '0',
RXCDRLOCK => rxcdrlock_out(0),
RXCDROVRDEN => '0',
RXCDRPHDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_24\,
RXCDRRESET => '0',
RXCHANBONDSEQ => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_25\,
RXCHANISALIGNED => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_26\,
RXCHANREALIGN => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_27\,
RXCHBONDEN => '0',
RXCHBONDI(4 downto 0) => B"00000",
RXCHBONDLEVEL(2 downto 0) => B"000",
RXCHBONDMASTER => '0',
RXCHBONDO(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_325\,
RXCHBONDO(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_326\,
RXCHBONDO(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_327\,
RXCHBONDO(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_328\,
RXCHBONDO(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_329\,
RXCHBONDSLAVE => '0',
RXCKCALDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_28\,
RXCKCALRESET => '0',
RXCKCALSTART(6 downto 0) => B"0000000",
RXCLKCORCNT(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_303\,
RXCLKCORCNT(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_304\,
RXCOMINITDET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_29\,
RXCOMMADET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_30\,
RXCOMMADETEN => '0',
RXCOMSASDET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_31\,
RXCOMWAKEDET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_32\,
RXCTRL0(15) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_267\,
RXCTRL0(14) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_268\,
RXCTRL0(13) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_269\,
RXCTRL0(12) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_270\,
RXCTRL0(11) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_271\,
RXCTRL0(10) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_272\,
RXCTRL0(9) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_273\,
RXCTRL0(8) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_274\,
RXCTRL0(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_275\,
RXCTRL0(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_276\,
RXCTRL0(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_277\,
RXCTRL0(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_278\,
RXCTRL0(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_279\,
RXCTRL0(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_280\,
RXCTRL0(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_281\,
RXCTRL0(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_282\,
RXCTRL1(15) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_283\,
RXCTRL1(14) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_284\,
RXCTRL1(13) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_285\,
RXCTRL1(12) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_286\,
RXCTRL1(11) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_287\,
RXCTRL1(10) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_288\,
RXCTRL1(9) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_289\,
RXCTRL1(8) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_290\,
RXCTRL1(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_291\,
RXCTRL1(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_292\,
RXCTRL1(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_293\,
RXCTRL1(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_294\,
RXCTRL1(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_295\,
RXCTRL1(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_296\,
RXCTRL1(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_297\,
RXCTRL1(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_298\,
RXCTRL2(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_336\,
RXCTRL2(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_337\,
RXCTRL2(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_338\,
RXCTRL2(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_339\,
RXCTRL2(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_340\,
RXCTRL2(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_341\,
RXCTRL2(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_342\,
RXCTRL2(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_343\,
RXCTRL3(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_344\,
RXCTRL3(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_345\,
RXCTRL3(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_346\,
RXCTRL3(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_347\,
RXCTRL3(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_348\,
RXCTRL3(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_349\,
RXCTRL3(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_350\,
RXCTRL3(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_351\,
RXDATA(127) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_75\,
RXDATA(126) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_76\,
RXDATA(125) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_77\,
RXDATA(124) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_78\,
RXDATA(123) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_79\,
RXDATA(122) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_80\,
RXDATA(121) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_81\,
RXDATA(120) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_82\,
RXDATA(119) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_83\,
RXDATA(118) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_84\,
RXDATA(117) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_85\,
RXDATA(116) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_86\,
RXDATA(115) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_87\,
RXDATA(114) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_88\,
RXDATA(113) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_89\,
RXDATA(112) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_90\,
RXDATA(111) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_91\,
RXDATA(110) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_92\,
RXDATA(109) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_93\,
RXDATA(108) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_94\,
RXDATA(107) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_95\,
RXDATA(106) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_96\,
RXDATA(105) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_97\,
RXDATA(104) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_98\,
RXDATA(103) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_99\,
RXDATA(102) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_100\,
RXDATA(101) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_101\,
RXDATA(100) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_102\,
RXDATA(99) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_103\,
RXDATA(98) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_104\,
RXDATA(97) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_105\,
RXDATA(96) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_106\,
RXDATA(95) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_107\,
RXDATA(94) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_108\,
RXDATA(93) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_109\,
RXDATA(92) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_110\,
RXDATA(91) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_111\,
RXDATA(90) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_112\,
RXDATA(89) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_113\,
RXDATA(88) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_114\,
RXDATA(87) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_115\,
RXDATA(86) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_116\,
RXDATA(85) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_117\,
RXDATA(84) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_118\,
RXDATA(83) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_119\,
RXDATA(82) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_120\,
RXDATA(81) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_121\,
RXDATA(80) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_122\,
RXDATA(79) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_123\,
RXDATA(78) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_124\,
RXDATA(77) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_125\,
RXDATA(76) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_126\,
RXDATA(75) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_127\,
RXDATA(74) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_128\,
RXDATA(73) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_129\,
RXDATA(72) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_130\,
RXDATA(71) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_131\,
RXDATA(70) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_132\,
RXDATA(69) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_133\,
RXDATA(68) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_134\,
RXDATA(67) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_135\,
RXDATA(66) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_136\,
RXDATA(65) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_137\,
RXDATA(64) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_138\,
RXDATA(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
RXDATAEXTENDRSVD(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_352\,
RXDATAEXTENDRSVD(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_353\,
RXDATAEXTENDRSVD(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_354\,
RXDATAEXTENDRSVD(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_355\,
RXDATAEXTENDRSVD(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_356\,
RXDATAEXTENDRSVD(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_357\,
RXDATAEXTENDRSVD(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_358\,
RXDATAEXTENDRSVD(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_359\,
RXDATAVALID(1 downto 0) => rxdatavalid_out(1 downto 0),
RXDFEAGCHOLD => '0',
RXDFEAGCOVRDEN => '0',
RXDFECFOKFCNUM(3 downto 0) => B"1101",
RXDFECFOKFEN => '0',
RXDFECFOKFPULSE => '0',
RXDFECFOKHOLD => '0',
RXDFECFOKOVREN => '0',
RXDFEKHHOLD => '0',
RXDFEKHOVRDEN => '0',
RXDFELFHOLD => '0',
RXDFELFOVRDEN => '0',
RXDFELPMRESET => '0',
RXDFETAP10HOLD => '0',
RXDFETAP10OVRDEN => '0',
RXDFETAP11HOLD => '0',
RXDFETAP11OVRDEN => '0',
RXDFETAP12HOLD => '0',
RXDFETAP12OVRDEN => '0',
RXDFETAP13HOLD => '0',
RXDFETAP13OVRDEN => '0',
RXDFETAP14HOLD => '0',
RXDFETAP14OVRDEN => '0',
RXDFETAP15HOLD => '0',
RXDFETAP15OVRDEN => '0',
RXDFETAP2HOLD => '0',
RXDFETAP2OVRDEN => '0',
RXDFETAP3HOLD => '0',
RXDFETAP3OVRDEN => '0',
RXDFETAP4HOLD => '0',
RXDFETAP4OVRDEN => '0',
RXDFETAP5HOLD => '0',
RXDFETAP5OVRDEN => '0',
RXDFETAP6HOLD => '0',
RXDFETAP6OVRDEN => '0',
RXDFETAP7HOLD => '0',
RXDFETAP7OVRDEN => '0',
RXDFETAP8HOLD => '0',
RXDFETAP8OVRDEN => '0',
RXDFETAP9HOLD => '0',
RXDFETAP9OVRDEN => '0',
RXDFEUTHOLD => '0',
RXDFEUTOVRDEN => '0',
RXDFEVPHOLD => '0',
RXDFEVPOVRDEN => '0',
RXDFEXYDEN => '1',
RXDLYBYPASS => '1',
RXDLYEN => '0',
RXDLYOVRDEN => '0',
RXDLYSRESET => '0',
RXDLYSRESETDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_33\,
RXELECIDLE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_34\,
RXELECIDLEMODE(1 downto 0) => B"11",
RXEQTRAINING => '0',
RXGEARBOXSLIP => rxgearboxslip_in(0),
RXHEADER(5 downto 0) => rxheader_out(5 downto 0),
RXHEADERVALID(1 downto 0) => rxheadervalid_out(1 downto 0),
RXLATCLK => '0',
RXLFPSTRESETDET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_35\,
RXLFPSU2LPEXITDET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_36\,
RXLFPSU3WAKEDET => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_37\,
RXLPMEN => '0',
RXLPMGCHOLD => '0',
RXLPMGCOVRDEN => '0',
RXLPMHFHOLD => '0',
RXLPMHFOVRDEN => '0',
RXLPMLFHOLD => '0',
RXLPMLFKLOVRDEN => '0',
RXLPMOSHOLD => '0',
RXLPMOSOVRDEN => '0',
RXMCOMMAALIGNEN => '0',
RXMONITOROUT(7) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_360\,
RXMONITOROUT(6) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_361\,
RXMONITOROUT(5) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_362\,
RXMONITOROUT(4) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_363\,
RXMONITOROUT(3) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_364\,
RXMONITOROUT(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_365\,
RXMONITOROUT(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_366\,
RXMONITOROUT(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_367\,
RXMONITORSEL(1 downto 0) => B"00",
RXOOBRESET => '0',
RXOSCALRESET => '0',
RXOSHOLD => '0',
RXOSINTDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_38\,
RXOSINTSTARTED => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_39\,
RXOSINTSTROBEDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_40\,
RXOSINTSTROBESTARTED => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_41\,
RXOSOVRDEN => '0',
RXOUTCLK => \^gtwiz_userclk_rx_srcclk_out\(0),
RXOUTCLKFABRIC => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_43\,
RXOUTCLKPCS => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_44\,
RXOUTCLKSEL(2 downto 0) => B"101",
RXPCOMMAALIGNEN => '0',
RXPCSRESET => '0',
RXPD(1 downto 0) => B"00",
RXPHALIGN => '0',
RXPHALIGNDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_45\,
RXPHALIGNEN => '0',
RXPHALIGNERR => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_46\,
RXPHDLYPD => '1',
RXPHDLYRESET => '0',
RXPLLCLKSEL(1 downto 0) => B"11",
RXPMARESET => '0',
RXPMARESETDONE => rxpmaresetdone_out(0),
RXPOLARITY => '0',
RXPRBSCNTRESET => '0',
RXPRBSERR => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_48\,
RXPRBSLOCKED => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_49\,
RXPRBSSEL(3 downto 0) => B"0000",
RXPRGDIVRESETDONE => rxprgdivresetdone_out(0),
RXPROGDIVRESET => \gen_gtwizard_gtye4.rxprogdivreset_int\,
RXRATE(2 downto 0) => B"000",
RXRATEDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_51\,
RXRATEMODE => '0',
RXRECCLKOUT => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_52\,
RXRESETDONE => rxresetdone_out(0),
RXSLIDE => '0',
RXSLIDERDY => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_54\,
RXSLIPDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_55\,
RXSLIPOUTCLK => '0',
RXSLIPOUTCLKRDY => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_56\,
RXSLIPPMA => '0',
RXSLIPPMARDY => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_57\,
RXSTARTOFSEQ(1 downto 0) => rxstartofseq_out(1 downto 0),
RXSTATUS(2) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_322\,
RXSTATUS(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_323\,
RXSTATUS(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_324\,
RXSYNCALLIN => '0',
RXSYNCDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_58\,
RXSYNCIN => '0',
RXSYNCMODE => '0',
RXSYNCOUT => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_59\,
RXSYSCLKSEL(1 downto 0) => B"10",
RXTERMINATION => '0',
RXUSERRDY => \gen_gtwizard_gtye4.rxuserrdy_int\,
RXUSRCLK => gtwiz_userclk_rx_usrclk2_out(0),
RXUSRCLK2 => gtwiz_userclk_rx_usrclk2_out(0),
RXVALID => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_60\,
SIGVALIDCLK => '0',
TSTIN(19 downto 0) => B"00000000000000000000",
TX8B10BBYPASS(7 downto 0) => B"00000000",
TX8B10BEN => '0',
TXBUFSTATUS(1) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_311\,
TXBUFSTATUS(0) => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_312\,
TXCOMFINISH => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_61\,
TXCOMINIT => '0',
TXCOMSAS => '0',
TXCOMWAKE => '0',
TXCTRL0(15 downto 0) => B"0000000000000000",
TXCTRL1(15 downto 0) => B"0000000000000000",
TXCTRL2(7 downto 0) => B"00000000",
TXDATA(127 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000",
TXDATA(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0),
TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
TXDCCDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_62\,
TXDCCFORCESTART => '0',
TXDCCRESET => '0',
TXDEEMPH(1 downto 0) => B"00",
TXDETECTRX => '0',
TXDIFFCTRL(4 downto 0) => B"11000",
TXDLYBYPASS => '1',
TXDLYEN => '0',
TXDLYHOLD => '0',
TXDLYOVRDEN => '0',
TXDLYSRESET => '0',
TXDLYSRESETDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_63\,
TXDLYUPDOWN => '0',
TXELECIDLE => '0',
TXHEADER(5 downto 0) => txheader_in(5 downto 0),
TXINHIBIT => '0',
TXLATCLK => '0',
TXLFPSTRESET => '0',
TXLFPSU2LPEXIT => '0',
TXLFPSU3WAKE => '0',
TXMAINCURSOR(6 downto 0) => B"1010000",
TXMARGIN(2 downto 0) => B"000",
TXMUXDCDEXHOLD => '0',
TXMUXDCDORWREN => '0',
TXONESZEROS => '0',
TXOUTCLK => \^gtwiz_userclk_tx_srcclk_out\(0),
TXOUTCLKFABRIC => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_65\,
TXOUTCLKPCS => txoutclkpcs_out(0),
TXOUTCLKSEL(2 downto 0) => B"101",
TXPCSRESET => '0',
TXPD(1 downto 0) => B"00",
TXPDELECIDLEMODE => '0',
TXPHALIGN => '0',
TXPHALIGNDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_67\,
TXPHALIGNEN => '0',
TXPHDLYPD => '1',
TXPHDLYRESET => '0',
TXPHDLYTSTCLK => '0',
TXPHINIT => '0',
TXPHINITDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_68\,
TXPHOVRDEN => '0',
TXPIPPMEN => '0',
TXPIPPMOVRDEN => '0',
TXPIPPMPD => '0',
TXPIPPMSEL => '1',
TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
TXPISOPD => TXRATE(0),
TXPLLCLKSEL(1 downto 0) => B"11",
TXPMARESET => '0',
TXPMARESETDONE => txpmaresetdone_out(0),
TXPOLARITY => '0',
TXPOSTCURSOR(4 downto 0) => B"00000",
TXPRBSFORCEERR => '0',
TXPRBSSEL(3 downto 0) => B"0000",
TXPRECURSOR(4 downto 0) => B"00000",
TXPRGDIVRESETDONE => txprgdivresetdone_out(0),
TXPROGDIVRESET => \gen_gtwizard_gtye4.txprogdivreset_int\,
TXRATE(2 downto 1) => B"00",
TXRATE(0) => TXRATE(0),
TXRATEDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_71\,
TXRATEMODE => TXRATE(0),
TXRESETDONE => txresetdone_out(0),
TXSEQUENCE(6 downto 0) => txsequence_in(6 downto 0),
TXSWING => '0',
TXSYNCALLIN => '0',
TXSYNCDONE => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_73\,
TXSYNCIN => '0',
TXSYNCMODE => '0',
TXSYNCOUT => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_n_74\,
TXSYSCLKSEL(1 downto 0) => B"10",
TXUSERRDY => \gen_gtwizard_gtye4.txuserrdy_int\,
TXUSRCLK => gtwiz_userclk_tx_usrclk2_out(0),
TXUSRCLK2 => gtwiz_userclk_tx_usrclk2_out(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_delay_powergood is
port (
\out\ : out STD_LOGIC;
TXRATE : out STD_LOGIC_VECTOR ( 0 to 0 );
txoutclkpcs_out : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_delay_powergood;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_delay_powergood is
signal \gen_powergood_delay.int_pwr_on_fsm\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \gen_powergood_delay.int_pwr_on_fsm\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \gen_powergood_delay.int_pwr_on_fsm\ : signal is "true";
attribute shreg_extract : string;
attribute shreg_extract of \gen_powergood_delay.int_pwr_on_fsm\ : signal is "no";
signal \gen_powergood_delay.int_pwr_on_fsm_i_1_n_0\ : STD_LOGIC;
signal \gen_powergood_delay.intclk_rrst_n_r\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute async_reg of \gen_powergood_delay.intclk_rrst_n_r\ : signal is "true";
attribute shreg_extract of \gen_powergood_delay.intclk_rrst_n_r\ : signal is "no";
signal \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\ : STD_LOGIC;
signal \gen_powergood_delay.pwr_on_fsm\ : STD_LOGIC;
attribute RTL_KEEP of \gen_powergood_delay.pwr_on_fsm\ : signal is "true";
attribute async_reg of \gen_powergood_delay.pwr_on_fsm\ : signal is "true";
attribute shreg_extract of \gen_powergood_delay.pwr_on_fsm\ : signal is "no";
signal \gen_powergood_delay.wait_cnt\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg of \gen_powergood_delay.wait_cnt\ : signal is "true";
attribute shreg_extract of \gen_powergood_delay.wait_cnt\ : signal is "no";
signal \gen_powergood_delay.wait_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_powergood_delay.wait_cnt[8]_i_1_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \gen_powergood_delay.int_pwr_on_fsm_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \gen_powergood_delay.int_pwr_on_fsm_reg\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.int_pwr_on_fsm_reg\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.intclk_rrst_n_r_reg[0]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.intclk_rrst_n_r_reg[0]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.intclk_rrst_n_r_reg[0]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.intclk_rrst_n_r_reg[1]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.intclk_rrst_n_r_reg[1]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.intclk_rrst_n_r_reg[1]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.intclk_rrst_n_r_reg[2]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.intclk_rrst_n_r_reg[2]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.intclk_rrst_n_r_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.intclk_rrst_n_r_reg[3]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.intclk_rrst_n_r_reg[3]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.intclk_rrst_n_r_reg[3]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.intclk_rrst_n_r_reg[4]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.intclk_rrst_n_r_reg[4]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.intclk_rrst_n_r_reg[4]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.pwr_on_fsm_reg\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.pwr_on_fsm_reg\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.pwr_on_fsm_reg\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[0]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[0]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[0]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[1]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[1]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[1]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[2]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[2]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[3]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[3]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[3]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[4]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[4]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[4]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[5]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[5]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[5]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[6]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[6]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[6]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[7]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[7]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[7]\ : label is "no";
attribute ASYNC_REG_boolean of \gen_powergood_delay.wait_cnt_reg[8]\ : label is std.standard.true;
attribute KEEP of \gen_powergood_delay.wait_cnt_reg[8]\ : label is "yes";
attribute SHREG_EXTRACT of \gen_powergood_delay.wait_cnt_reg[8]\ : label is "no";
begin
\out\ <= \gen_powergood_delay.pwr_on_fsm\;
\gen_powergood_delay.int_pwr_on_fsm_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_powergood_delay.int_pwr_on_fsm\,
I1 => \gen_powergood_delay.wait_cnt\(7),
O => \gen_powergood_delay.int_pwr_on_fsm_i_1_n_0\
);
\gen_powergood_delay.int_pwr_on_fsm_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => txoutclkpcs_out(0),
CE => '1',
CLR => \gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\,
D => \gen_powergood_delay.int_pwr_on_fsm_i_1_n_0\,
Q => \gen_powergood_delay.int_pwr_on_fsm\
);
\gen_powergood_delay.intclk_rrst_n_r[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_powergood_delay.int_pwr_on_fsm\,
O => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\
);
\gen_powergood_delay.intclk_rrst_n_r_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
CLR => \gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\,
D => '1',
Q => \gen_powergood_delay.intclk_rrst_n_r\(0)
);
\gen_powergood_delay.intclk_rrst_n_r_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
CLR => \gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\,
D => \gen_powergood_delay.intclk_rrst_n_r\(0),
Q => \gen_powergood_delay.intclk_rrst_n_r\(1)
);
\gen_powergood_delay.intclk_rrst_n_r_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
CLR => \gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\,
D => \gen_powergood_delay.intclk_rrst_n_r\(1),
Q => \gen_powergood_delay.intclk_rrst_n_r\(2)
);
\gen_powergood_delay.intclk_rrst_n_r_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
CLR => \gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\,
D => \gen_powergood_delay.intclk_rrst_n_r\(2),
Q => \gen_powergood_delay.intclk_rrst_n_r\(3)
);
\gen_powergood_delay.intclk_rrst_n_r_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
CLR => \gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\,
D => \gen_powergood_delay.intclk_rrst_n_r\(3),
Q => \gen_powergood_delay.intclk_rrst_n_r\(4)
);
\gen_powergood_delay.pwr_on_fsm_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => txoutclkpcs_out(0),
CE => '1',
D => \gen_powergood_delay.int_pwr_on_fsm\,
Q => \gen_powergood_delay.pwr_on_fsm\,
R => '0'
);
\gen_powergood_delay.wait_cnt[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \gen_powergood_delay.intclk_rrst_n_r\(4),
I1 => \gen_powergood_delay.int_pwr_on_fsm\,
O => \gen_powergood_delay.wait_cnt[0]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_powergood_delay.intclk_rrst_n_r\(4),
O => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.wait_cnt[0]_i_1_n_0\,
D => \gen_powergood_delay.intclk_rrst_n_r\(4),
Q => \gen_powergood_delay.wait_cnt\(0),
R => '0'
);
\gen_powergood_delay.wait_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(0),
Q => \gen_powergood_delay.wait_cnt\(1),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(1),
Q => \gen_powergood_delay.wait_cnt\(2),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(2),
Q => \gen_powergood_delay.wait_cnt\(3),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(3),
Q => \gen_powergood_delay.wait_cnt\(4),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(4),
Q => \gen_powergood_delay.wait_cnt\(5),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(5),
Q => \gen_powergood_delay.wait_cnt\(6),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(6),
Q => \gen_powergood_delay.wait_cnt\(7),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gen_powergood_delay.wait_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => txoutclkpcs_out(0),
CE => \gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0\,
D => \gen_powergood_delay.wait_cnt\(7),
Q => \gen_powergood_delay.wait_cnt\(8),
R => \gen_powergood_delay.wait_cnt[8]_i_1_n_0\
);
\gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_powergood_delay.pwr_on_fsm\,
O => TXRATE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer is
port (
gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_in_sync2_reg_0 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer is
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal \rst_in_out_i_1__0_n_0\ : STD_LOGIC;
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
rst_in_meta_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_rx_usrclk2_out(0),
CE => '1',
CLR => \rst_in_out_i_1__0_n_0\,
D => '1',
Q => rst_in_meta
);
\rst_in_out_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst_in_sync2_reg_0,
O => \rst_in_out_i_1__0_n_0\
);
rst_in_out_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_rx_usrclk2_out(0),
CE => '1',
CLR => \rst_in_out_i_1__0_n_0\,
D => rst_in_sync3,
Q => gtwiz_reset_rx_done_out(0)
);
rst_in_sync1_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_rx_usrclk2_out(0),
CE => '1',
CLR => \rst_in_out_i_1__0_n_0\,
D => rst_in_meta,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_rx_usrclk2_out(0),
CE => '1',
CLR => \rst_in_out_i_1__0_n_0\,
D => rst_in_sync1,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_rx_usrclk2_out(0),
CE => '1',
CLR => \rst_in_out_i_1__0_n_0\,
D => rst_in_sync2,
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer_17 is
port (
gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_in_sync2_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer_17 : entity is "gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer_17;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer_17 is
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_out_i_1_n_0 : STD_LOGIC;
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
rst_in_meta_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_tx_usrclk2_out(0),
CE => '1',
CLR => rst_in_out_i_1_n_0,
D => '1',
Q => rst_in_meta
);
rst_in_out_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst_in_sync2_reg_0,
O => rst_in_out_i_1_n_0
);
rst_in_out_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_tx_usrclk2_out(0),
CE => '1',
CLR => rst_in_out_i_1_n_0,
D => rst_in_sync3,
Q => gtwiz_reset_tx_done_out(0)
);
rst_in_sync1_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_tx_usrclk2_out(0),
CE => '1',
CLR => rst_in_out_i_1_n_0,
D => rst_in_meta,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_tx_usrclk2_out(0),
CE => '1',
CLR => rst_in_out_i_1_n_0,
D => rst_in_sync1,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => gtwiz_userclk_tx_usrclk2_out(0),
CE => '1',
CLR => rst_in_out_i_1_n_0,
D => rst_in_sync2,
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer is
port (
gtwiz_reset_all_sync : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer is
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => gtwiz_reset_all_in(0),
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => gtwiz_reset_all_in(0),
Q => gtwiz_reset_all_sync
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => gtwiz_reset_all_in(0),
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => gtwiz_reset_all_in(0),
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => gtwiz_reset_all_in(0),
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_11 is
port (
gtwiz_reset_rx_any_sync : out STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[1]_0\ : out STD_LOGIC;
\FSM_sequential_sm_reset_rx_reg[1]_1\ : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : in STD_LOGIC;
rxprogdivreset_out_reg : in STD_LOGIC;
\gen_gtwizard_gtye4.rxprogdivreset_int\ : in STD_LOGIC;
gtrxreset_out_reg : in STD_LOGIC;
\gen_gtwizard_gtye4.gtrxreset_int\ : in STD_LOGIC;
rst_in_out_reg_0 : in STD_LOGIC;
gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_in_out_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_11 : entity is "gtwizard_ultrascale_v1_7_12_reset_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_11;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_11 is
signal gtwiz_reset_rx_any : STD_LOGIC;
signal \^gtwiz_reset_rx_any_sync\ : STD_LOGIC;
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
gtwiz_reset_rx_any_sync <= \^gtwiz_reset_rx_any_sync\;
gtrxreset_out_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF7FFFF00070000"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => Q(2),
I3 => \^gtwiz_reset_rx_any_sync\,
I4 => gtrxreset_out_reg,
I5 => \gen_gtwizard_gtye4.gtrxreset_int\,
O => \FSM_sequential_sm_reset_rx_reg[1]_1\
);
pllreset_rx_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFDF0010"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => \^gtwiz_reset_rx_any_sync\,
I4 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
O => \FSM_sequential_sm_reset_rx_reg[1]\
);
\rst_in_meta_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rst_in_out_reg_0,
I1 => gtwiz_reset_rx_datapath_in(0),
I2 => gtwiz_reset_rx_pll_and_datapath_in(0),
I3 => rst_in_out_reg_1,
O => gtwiz_reset_rx_any
);
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => gtwiz_reset_rx_any,
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => gtwiz_reset_rx_any,
Q => \^gtwiz_reset_rx_any_sync\
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => gtwiz_reset_rx_any,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => gtwiz_reset_rx_any,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => gtwiz_reset_rx_any,
Q => rst_in_sync3
);
rxprogdivreset_out_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFBFFFF00120012"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => \^gtwiz_reset_rx_any_sync\,
I4 => rxprogdivreset_out_reg,
I5 => \gen_gtwizard_gtye4.rxprogdivreset_int\,
O => \FSM_sequential_sm_reset_rx_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_12 is
port (
in0 : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_in_out_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_12 : entity is "gtwizard_ultrascale_v1_7_12_reset_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_12;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_12 is
signal rst_in0_1 : STD_LOGIC;
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
\rst_in_meta_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => gtwiz_reset_rx_datapath_in(0),
I1 => rst_in_out_reg_0,
O => rst_in0_1
);
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => rst_in0_1,
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => rst_in0_1,
Q => in0
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => rst_in0_1,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => rst_in0_1,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => rst_in0_1,
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_13 is
port (
in0 : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_in_out_reg_0 : in STD_LOGIC;
gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_13 : entity is "gtwizard_ultrascale_v1_7_12_reset_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_13;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_13 is
signal p_0_in_0 : STD_LOGIC;
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
\rst_in_meta_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_out_reg_0,
I1 => gtwiz_reset_rx_pll_and_datapath_in(0),
O => p_0_in_0
);
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => p_0_in_0,
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => p_0_in_0,
Q => in0
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => p_0_in_0,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => p_0_in_0,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => p_0_in_0,
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_14 is
port (
gtwiz_reset_tx_any_sync : out STD_LOGIC;
\FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC;
rst_in_out_reg_0 : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ : in STD_LOGIC;
gttxreset_out_reg : in STD_LOGIC;
\gen_gtwizard_gtye4.gttxreset_int\ : in STD_LOGIC;
gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_in_out_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_14 : entity is "gtwizard_ultrascale_v1_7_12_reset_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_14;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_14 is
signal gtwiz_reset_tx_any : STD_LOGIC;
signal \^gtwiz_reset_tx_any_sync\ : STD_LOGIC;
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
gtwiz_reset_tx_any_sync <= \^gtwiz_reset_tx_any_sync\;
gttxreset_out_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"3F3FFFFF3F3F0014"
)
port map (
I0 => \^gtwiz_reset_tx_any_sync\,
I1 => Q(1),
I2 => Q(0),
I3 => Q(2),
I4 => gttxreset_out_reg,
I5 => \gen_gtwizard_gtye4.gttxreset_int\,
O => rst_in_out_reg_0
);
pllreset_tx_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFDF0010"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => \^gtwiz_reset_tx_any_sync\,
I4 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\,
O => \FSM_sequential_sm_reset_tx_reg[1]\
);
rst_in_meta_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => gtwiz_reset_tx_datapath_in(0),
I1 => gtwiz_reset_tx_pll_and_datapath_in(0),
I2 => rst_in_out_reg_1,
O => gtwiz_reset_tx_any
);
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => gtwiz_reset_tx_any,
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => gtwiz_reset_tx_any,
Q => \^gtwiz_reset_tx_any_sync\
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => gtwiz_reset_tx_any,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => gtwiz_reset_tx_any,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => gtwiz_reset_tx_any,
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_15 is
port (
in0 : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_15 : entity is "gtwizard_ultrascale_v1_7_12_reset_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_15;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_15 is
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => gtwiz_reset_tx_datapath_in(0),
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => gtwiz_reset_tx_datapath_in(0),
Q => in0
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => gtwiz_reset_tx_datapath_in(0),
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => gtwiz_reset_tx_datapath_in(0),
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => gtwiz_reset_tx_datapath_in(0),
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_16 is
port (
in0 : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_in_out_reg_0 : in STD_LOGIC;
gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_16 : entity is "gtwizard_ultrascale_v1_7_12_reset_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_16;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_16 is
signal p_1_in : STD_LOGIC;
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
\rst_in_meta_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_out_reg_0,
I1 => gtwiz_reset_tx_pll_and_datapath_in(0),
O => p_1_in
);
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => p_1_in,
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => p_1_in,
Q => in0
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => p_1_in,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => p_1_in,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => p_1_in,
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_18 is
port (
\gen_gtwizard_gtye4.txprogdivreset_int\ : out STD_LOGIC;
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_18 : entity is "gtwizard_ultrascale_v1_7_12_reset_synchronizer";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_18;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_18 is
signal rst_in0 : STD_LOGIC;
signal rst_in_meta : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_in_meta : signal is "true";
signal rst_in_sync1 : STD_LOGIC;
attribute async_reg of rst_in_sync1 : signal is "true";
signal rst_in_sync2 : STD_LOGIC;
attribute async_reg of rst_in_sync2 : signal is "true";
signal rst_in_sync3 : STD_LOGIC;
attribute async_reg of rst_in_sync3 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of rst_in_meta_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
attribute KEEP of rst_in_sync1_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
attribute KEEP of rst_in_sync2_reg : label is "yes";
attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
attribute KEEP of rst_in_sync3_reg : label is "yes";
begin
\rst_in_meta_i_1__4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gtwiz_reset_qpll0lock_in(0),
O => rst_in0
);
rst_in_meta_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => '0',
PRE => rst_in0,
Q => rst_in_meta
);
rst_in_out_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync3,
PRE => rst_in0,
Q => \gen_gtwizard_gtye4.txprogdivreset_int\
);
rst_in_sync1_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_meta,
PRE => rst_in0,
Q => rst_in_sync1
);
rst_in_sync2_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync1,
PRE => rst_in0,
Q => rst_in_sync2
);
rst_in_sync3_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => rst_in_sync2,
PRE => rst_in0,
Q => rst_in_sync3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtye4_channel_wrapper is
port (
\gen_gtwizard_gtye4.gtpowergood_int\ : out STD_LOGIC;
gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST\ : out STD_LOGIC;
\gen_gtwizard_gtye4.gtrxreset_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.gttxreset_ch_int\ : in STD_LOGIC;
gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.rxprogdivreset_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.rxuserrdy_int\ : in STD_LOGIC;
gtwiz_userclk_rx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
TXRATE : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.txprogdivreset_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.txuserrdy_int\ : in STD_LOGIC;
gtwiz_userclk_tx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
lopt : in STD_LOGIC;
lopt_1 : in STD_LOGIC;
lopt_2 : out STD_LOGIC;
lopt_3 : out STD_LOGIC;
lopt_4 : in STD_LOGIC;
lopt_5 : in STD_LOGIC;
lopt_6 : out STD_LOGIC;
lopt_7 : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtye4_channel_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtye4_channel_wrapper is
begin
channel_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_channel
port map (
TXRATE(0) => TXRATE(0),
\gen_gtwizard_gtye4.gtpowergood_int\ => \gen_gtwizard_gtye4.gtpowergood_int\,
\gen_gtwizard_gtye4.gtrxreset_int\ => \gen_gtwizard_gtye4.gtrxreset_int\,
\gen_gtwizard_gtye4.gttxreset_ch_int\ => \gen_gtwizard_gtye4.gttxreset_ch_int\,
\gen_gtwizard_gtye4.rxprogdivreset_int\ => \gen_gtwizard_gtye4.rxprogdivreset_int\,
\gen_gtwizard_gtye4.rxuserrdy_int\ => \gen_gtwizard_gtye4.rxuserrdy_int\,
\gen_gtwizard_gtye4.txprogdivreset_int\ => \gen_gtwizard_gtye4.txprogdivreset_int\,
\gen_gtwizard_gtye4.txuserrdy_int\ => \gen_gtwizard_gtye4.txuserrdy_int\,
gtwiz_userclk_rx_srcclk_out(0) => gtwiz_userclk_rx_srcclk_out(0),
gtwiz_userclk_rx_usrclk2_out(0) => gtwiz_userclk_rx_usrclk2_out(0),
gtwiz_userclk_tx_srcclk_out(0) => gtwiz_userclk_tx_srcclk_out(0),
gtwiz_userclk_tx_usrclk2_out(0) => gtwiz_userclk_tx_usrclk2_out(0),
gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0),
\gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_0\ => \gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST\,
gtyrxn_in(0) => gtyrxn_in(0),
gtyrxp_in(0) => gtyrxp_in(0),
gtytxn_out(0) => gtytxn_out(0),
gtytxp_out(0) => gtytxp_out(0),
lopt => lopt,
lopt_1 => lopt_1,
lopt_2 => lopt_2,
lopt_3 => lopt_3,
lopt_4 => lopt_4,
lopt_5 => lopt_5,
lopt_6 => lopt_6,
lopt_7 => lopt_7,
qpll0clk_in(0) => qpll0clk_in(0),
qpll0refclk_in(0) => qpll0refclk_in(0),
qpll1clk_in(0) => qpll1clk_in(0),
qpll1refclk_in(0) => qpll1refclk_in(0),
rxcdrlock_out(0) => rxcdrlock_out(0),
rxdatavalid_out(1 downto 0) => rxdatavalid_out(1 downto 0),
rxgearboxslip_in(0) => rxgearboxslip_in(0),
rxheader_out(5 downto 0) => rxheader_out(5 downto 0),
rxheadervalid_out(1 downto 0) => rxheadervalid_out(1 downto 0),
rxpmaresetdone_out(0) => rxpmaresetdone_out(0),
rxprgdivresetdone_out(0) => rxprgdivresetdone_out(0),
rxresetdone_out(0) => rxresetdone_out(0),
rxstartofseq_out(1 downto 0) => rxstartofseq_out(1 downto 0),
txheader_in(5 downto 0) => txheader_in(5 downto 0),
txoutclkpcs_out(0) => txoutclkpcs_out(0),
txpmaresetdone_out(0) => txpmaresetdone_out(0),
txprgdivresetdone_out(0) => txprgdivresetdone_out(0),
txresetdone_out(0) => txresetdone_out(0),
txsequence_in(6 downto 0) => txsequence_in(6 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_reset is
port (
\gen_gtwizard_gtye4.txprogdivreset_int\ : out STD_LOGIC;
gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.txuserrdy_int\ : out STD_LOGIC;
\gen_gtwizard_gtye4.rxprogdivreset_int\ : out STD_LOGIC;
\gen_gtwizard_gtye4.gtrxreset_int\ : out STD_LOGIC;
\gen_gtwizard_gtye4.rxuserrdy_int\ : out STD_LOGIC;
\gen_gtwizard_gtye4.gttxreset_ch_int\ : out STD_LOGIC;
gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtpowergood_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_active_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_active_out : in STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrlock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_usrclk2_out : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.gtpowergood_int\ : in STD_LOGIC;
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC;
gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_reset is
signal \FSM_sequential_sm_reset_all[2]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_sm_reset_all[2]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_sm_reset_rx[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_sm_reset_rx[2]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_sm_reset_tx[2]_i_6_n_0\ : STD_LOGIC;
signal \FSM_sequential_sm_reset_tx[2]_i_7_n_0\ : STD_LOGIC;
signal bit_synchronizer_gtpowergood_inst_n_0 : STD_LOGIC;
signal bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0 : STD_LOGIC;
signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0 : STD_LOGIC;
signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1 : STD_LOGIC;
signal bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2 : STD_LOGIC;
signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0 : STD_LOGIC;
signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1 : STD_LOGIC;
signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2 : STD_LOGIC;
signal bit_synchronizer_plllock_rx_inst_n_1 : STD_LOGIC;
signal bit_synchronizer_plllock_rx_inst_n_2 : STD_LOGIC;
signal bit_synchronizer_plllock_rx_inst_n_3 : STD_LOGIC;
signal bit_synchronizer_plllock_tx_inst_n_1 : STD_LOGIC;
signal bit_synchronizer_plllock_tx_inst_n_2 : STD_LOGIC;
signal bit_synchronizer_plllock_tx_inst_n_3 : STD_LOGIC;
signal bit_synchronizer_rxcdrlock_inst_n_1 : STD_LOGIC;
signal bit_synchronizer_rxcdrlock_inst_n_2 : STD_LOGIC;
signal bit_synchronizer_rxcdrlock_inst_n_3 : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ : STD_LOGIC;
signal \^gen_gtwizard_gtye4.gtrxreset_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gttxreset_int\ : STD_LOGIC;
signal \^gen_gtwizard_gtye4.rxprogdivreset_int\ : STD_LOGIC;
signal \^gen_gtwizard_gtye4.rxuserrdy_int\ : STD_LOGIC;
signal \^gen_gtwizard_gtye4.txuserrdy_int\ : STD_LOGIC;
signal gtwiz_reset_all_sync : STD_LOGIC;
signal gtwiz_reset_rx_any_sync : STD_LOGIC;
signal gtwiz_reset_rx_datapath_int_i_1_n_0 : STD_LOGIC;
signal gtwiz_reset_rx_datapath_int_reg_n_0 : STD_LOGIC;
signal gtwiz_reset_rx_datapath_sync : STD_LOGIC;
signal gtwiz_reset_rx_done_int_reg_n_0 : STD_LOGIC;
signal gtwiz_reset_rx_pll_and_datapath_dly : STD_LOGIC;
signal gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC;
signal gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 : STD_LOGIC;
signal gtwiz_reset_rx_pll_and_datapath_sync : STD_LOGIC;
signal gtwiz_reset_tx_any_sync : STD_LOGIC;
signal gtwiz_reset_tx_datapath_dly : STD_LOGIC;
signal gtwiz_reset_tx_datapath_sync : STD_LOGIC;
signal gtwiz_reset_tx_done_int_reg_n_0 : STD_LOGIC;
signal gtwiz_reset_tx_pll_and_datapath_dly : STD_LOGIC;
signal gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC;
signal gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 : STD_LOGIC;
signal gtwiz_reset_tx_pll_and_datapath_sync : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal plllock_rx_sync : STD_LOGIC;
signal plllock_tx_sync : STD_LOGIC;
signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_1 : STD_LOGIC;
signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_2 : STD_LOGIC;
signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_3 : STD_LOGIC;
signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_1 : STD_LOGIC;
signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_2 : STD_LOGIC;
signal sm_reset_all : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \sm_reset_all__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sm_reset_all_timer_clr_i_1_n_0 : STD_LOGIC;
signal sm_reset_all_timer_clr_i_2_n_0 : STD_LOGIC;
signal sm_reset_all_timer_clr_reg_n_0 : STD_LOGIC;
signal sm_reset_all_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \sm_reset_all_timer_ctr0_inferred__0/i__n_0\ : STD_LOGIC;
signal \sm_reset_all_timer_ctr[0]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_all_timer_ctr[1]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_all_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
signal sm_reset_all_timer_sat : STD_LOGIC;
signal sm_reset_all_timer_sat_i_1_n_0 : STD_LOGIC;
signal sm_reset_rx : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \sm_reset_rx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sm_reset_rx_cdr_to_clr : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\ : STD_LOGIC;
signal sm_reset_rx_cdr_to_ctr_reg : STD_LOGIC_VECTOR ( 25 downto 0 );
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\ : STD_LOGIC;
signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\ : STD_LOGIC;
signal sm_reset_rx_cdr_to_sat : STD_LOGIC;
signal sm_reset_rx_cdr_to_sat_i_1_n_0 : STD_LOGIC;
signal sm_reset_rx_cdr_to_sat_i_2_n_0 : STD_LOGIC;
signal sm_reset_rx_cdr_to_sat_i_3_n_0 : STD_LOGIC;
signal sm_reset_rx_cdr_to_sat_i_4_n_0 : STD_LOGIC;
signal sm_reset_rx_cdr_to_sat_i_5_n_0 : STD_LOGIC;
signal sm_reset_rx_cdr_to_sat_i_6_n_0 : STD_LOGIC;
signal sm_reset_rx_pll_timer_clr_i_1_n_0 : STD_LOGIC;
signal sm_reset_rx_pll_timer_clr_reg_n_0 : STD_LOGIC;
signal \sm_reset_rx_pll_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_pll_timer_ctr[3]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC;
signal \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC;
signal sm_reset_rx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sm_reset_rx_pll_timer_sat : STD_LOGIC;
signal sm_reset_rx_pll_timer_sat_i_1_n_0 : STD_LOGIC;
signal sm_reset_rx_pll_timer_sat_i_2_n_0 : STD_LOGIC;
signal sm_reset_rx_pll_timer_sat_i_3_n_0 : STD_LOGIC;
signal sm_reset_rx_timer_clr_reg_n_0 : STD_LOGIC;
signal sm_reset_rx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\ : STD_LOGIC;
signal \sm_reset_rx_timer_ctr[0]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_timer_ctr[1]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_rx_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
signal sm_reset_rx_timer_sat : STD_LOGIC;
signal sm_reset_rx_timer_sat_i_1_n_0 : STD_LOGIC;
signal sm_reset_tx : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \sm_reset_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sm_reset_tx_pll_timer_clr : STD_LOGIC;
signal sm_reset_tx_pll_timer_clr_i_1_n_0 : STD_LOGIC;
signal sm_reset_tx_pll_timer_clr_reg_n_0 : STD_LOGIC;
signal \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_tx_pll_timer_ctr[3]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC;
signal \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC;
signal sm_reset_tx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sm_reset_tx_pll_timer_sat : STD_LOGIC;
signal sm_reset_tx_pll_timer_sat_i_1_n_0 : STD_LOGIC;
signal sm_reset_tx_pll_timer_sat_i_2_n_0 : STD_LOGIC;
signal sm_reset_tx_pll_timer_sat_i_3_n_0 : STD_LOGIC;
signal sm_reset_tx_timer_clr_reg_n_0 : STD_LOGIC;
signal sm_reset_tx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \sm_reset_tx_timer_ctr[0]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_tx_timer_ctr[1]_i_1_n_0\ : STD_LOGIC;
signal \sm_reset_tx_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
signal sm_reset_tx_timer_sat : STD_LOGIC;
signal sm_reset_tx_timer_sat_i_1_n_0 : STD_LOGIC;
signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_4\ : label is "soft_lutpair12";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[0]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[1]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[2]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[1]_i_2\ : label is "soft_lutpair9";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[0]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[1]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[2]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_6\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[2]_i_7\ : label is "soft_lutpair8";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[0]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[1]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[2]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
attribute SOFT_HLUTNM of gtwiz_reset_rx_datapath_int_i_1 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of gtwiz_reset_tx_pll_and_datapath_int_i_1 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[1]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[2]_i_1\ : label is "soft_lutpair20";
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[0]_i_2\ : label is 16;
attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[16]_i_1\ : label is 16;
attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[24]_i_1\ : label is 16;
attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[8]_i_1\ : label is 16;
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sm_reset_rx_pll_timer_sat_i_2 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[2]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of sm_reset_rx_timer_sat_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of sm_reset_tx_pll_timer_clr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of sm_reset_tx_pll_timer_sat_i_2 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[1]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[2]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of sm_reset_tx_timer_sat_i_1 : label is "soft_lutpair8";
begin
\gen_gtwizard_gtye4.gtrxreset_int\ <= \^gen_gtwizard_gtye4.gtrxreset_int\;
\gen_gtwizard_gtye4.rxprogdivreset_int\ <= \^gen_gtwizard_gtye4.rxprogdivreset_int\;
\gen_gtwizard_gtye4.rxuserrdy_int\ <= \^gen_gtwizard_gtye4.rxuserrdy_int\;
\gen_gtwizard_gtye4.txuserrdy_int\ <= \^gen_gtwizard_gtye4.txuserrdy_int\;
\FSM_sequential_sm_reset_all[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFF70000FFFFFF"
)
port map (
I0 => gtwiz_reset_rx_done_int_reg_n_0,
I1 => sm_reset_all_timer_sat,
I2 => sm_reset_all_timer_clr_reg_n_0,
I3 => sm_reset_all(2),
I4 => sm_reset_all(1),
I5 => sm_reset_all(0),
O => \sm_reset_all__0\(0)
);
\FSM_sequential_sm_reset_all[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"34"
)
port map (
I0 => sm_reset_all(2),
I1 => sm_reset_all(1),
I2 => sm_reset_all(0),
O => \sm_reset_all__0\(1)
);
\FSM_sequential_sm_reset_all[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"4A"
)
port map (
I0 => sm_reset_all(2),
I1 => sm_reset_all(0),
I2 => sm_reset_all(1),
O => \sm_reset_all__0\(2)
);
\FSM_sequential_sm_reset_all[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => sm_reset_all_timer_sat,
I1 => gtwiz_reset_rx_done_int_reg_n_0,
I2 => sm_reset_all_timer_clr_reg_n_0,
O => \FSM_sequential_sm_reset_all[2]_i_3_n_0\
);
\FSM_sequential_sm_reset_all[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sm_reset_all_timer_clr_reg_n_0,
I1 => sm_reset_all_timer_sat,
I2 => gtwiz_reset_tx_done_int_reg_n_0,
O => \FSM_sequential_sm_reset_all[2]_i_4_n_0\
);
\FSM_sequential_sm_reset_all_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtpowergood_inst_n_0,
D => \sm_reset_all__0\(0),
Q => sm_reset_all(0),
R => gtwiz_reset_all_sync
);
\FSM_sequential_sm_reset_all_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtpowergood_inst_n_0,
D => \sm_reset_all__0\(1),
Q => sm_reset_all(1),
R => gtwiz_reset_all_sync
);
\FSM_sequential_sm_reset_all_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtpowergood_inst_n_0,
D => \sm_reset_all__0\(2),
Q => sm_reset_all(2),
R => gtwiz_reset_all_sync
);
\FSM_sequential_sm_reset_rx[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sm_reset_rx_timer_sat,
I1 => sm_reset_rx_timer_clr_reg_n_0,
O => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\
);
\FSM_sequential_sm_reset_rx[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDFD8888DDDD8888"
)
port map (
I0 => sm_reset_rx(1),
I1 => sm_reset_rx(0),
I2 => sm_reset_rx_timer_sat,
I3 => sm_reset_rx_timer_clr_reg_n_0,
I4 => sm_reset_rx(2),
I5 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
O => \sm_reset_rx__0\(2)
);
\FSM_sequential_sm_reset_rx[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sm_reset_rx_timer_clr_reg_n_0,
I1 => sm_reset_rx_timer_sat,
I2 => sm_reset_rx(1),
O => \FSM_sequential_sm_reset_rx[2]_i_4_n_0\
);
\FSM_sequential_sm_reset_rx_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
D => \sm_reset_rx__0\(0),
Q => sm_reset_rx(0),
R => gtwiz_reset_rx_any_sync
);
\FSM_sequential_sm_reset_rx_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
D => \sm_reset_rx__0\(1),
Q => sm_reset_rx(1),
R => gtwiz_reset_rx_any_sync
);
\FSM_sequential_sm_reset_rx_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
D => \sm_reset_rx__0\(2),
Q => sm_reset_rx(2),
R => gtwiz_reset_rx_any_sync
);
\FSM_sequential_sm_reset_tx[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"38"
)
port map (
I0 => sm_reset_tx(0),
I1 => sm_reset_tx(1),
I2 => sm_reset_tx(2),
O => \sm_reset_tx__0\(2)
);
\FSM_sequential_sm_reset_tx[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sm_reset_tx(1),
I1 => sm_reset_tx(2),
O => sm_reset_tx_pll_timer_clr
);
\FSM_sequential_sm_reset_tx[2]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => sm_reset_tx(1),
I1 => sm_reset_tx(2),
I2 => sm_reset_tx_timer_clr_reg_n_0,
I3 => sm_reset_tx_timer_sat,
O => \FSM_sequential_sm_reset_tx[2]_i_6_n_0\
);
\FSM_sequential_sm_reset_tx[2]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sm_reset_tx_timer_sat,
I1 => sm_reset_tx_timer_clr_reg_n_0,
O => \FSM_sequential_sm_reset_tx[2]_i_7_n_0\
);
\FSM_sequential_sm_reset_tx_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
D => \sm_reset_tx__0\(0),
Q => sm_reset_tx(0),
R => gtwiz_reset_tx_any_sync
);
\FSM_sequential_sm_reset_tx_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
D => \sm_reset_tx__0\(1),
Q => sm_reset_tx(1),
R => gtwiz_reset_tx_any_sync
);
\FSM_sequential_sm_reset_tx_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
D => \sm_reset_tx__0\(2),
Q => sm_reset_tx(2),
R => gtwiz_reset_tx_any_sync
);
bit_synchronizer_gtpowergood_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_1
port map (
E(0) => bit_synchronizer_gtpowergood_inst_n_0,
\FSM_sequential_sm_reset_all_reg[0]\ => \FSM_sequential_sm_reset_all[2]_i_3_n_0\,
\FSM_sequential_sm_reset_all_reg[0]_0\ => \FSM_sequential_sm_reset_all[2]_i_4_n_0\,
Q(2 downto 0) => sm_reset_all(2 downto 0),
gtpowergood_out(0) => gtpowergood_out(0),
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0)
);
bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_2
port map (
E(0) => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
\FSM_sequential_sm_reset_rx_reg[0]\ => \FSM_sequential_sm_reset_rx[2]_i_4_n_0\,
\FSM_sequential_sm_reset_rx_reg[0]_0\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2,
\FSM_sequential_sm_reset_rx_reg[0]_1\ => bit_synchronizer_rxcdrlock_inst_n_2,
Q(2 downto 0) => sm_reset_rx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_rx_pll_and_datapath_dly => gtwiz_reset_rx_pll_and_datapath_dly,
in0 => gtwiz_reset_rx_datapath_sync
);
bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_3
port map (
D(1 downto 0) => \sm_reset_rx__0\(1 downto 0),
\FSM_sequential_sm_reset_rx_reg[0]\ => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\,
Q(2 downto 0) => sm_reset_rx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_rx_pll_and_datapath_dly => gtwiz_reset_rx_pll_and_datapath_dly,
in0 => gtwiz_reset_rx_pll_and_datapath_sync
);
bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_4
port map (
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_tx_datapath_dly => gtwiz_reset_tx_datapath_dly,
in0 => gtwiz_reset_tx_datapath_sync
);
bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_5
port map (
D(1 downto 0) => \sm_reset_tx__0\(1 downto 0),
Q(2 downto 0) => sm_reset_tx(2 downto 0),
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly,
in0 => gtwiz_reset_tx_pll_and_datapath_sync
);
bit_synchronizer_gtwiz_reset_userclk_rx_active_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_6
port map (
\FSM_sequential_sm_reset_rx_reg[0]\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0,
\FSM_sequential_sm_reset_rx_reg[0]_0\ => sm_reset_rx_pll_timer_clr_reg_n_0,
\FSM_sequential_sm_reset_rx_reg[1]\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2,
\FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1,
Q(2 downto 0) => sm_reset_rx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
\gen_gtwizard_gtye4.rxuserrdy_int\ => \^gen_gtwizard_gtye4.rxuserrdy_int\,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
gtwiz_userclk_rx_active_out(0) => gtwiz_userclk_rx_active_out(0),
sm_reset_rx_pll_timer_sat => sm_reset_rx_pll_timer_sat,
sm_reset_rx_timer_clr_reg => sm_reset_rx_timer_clr_reg_n_0,
sm_reset_rx_timer_clr_reg_0 => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\,
sm_reset_rx_timer_clr_reg_1 => bit_synchronizer_plllock_rx_inst_n_3,
sm_reset_rx_timer_sat => sm_reset_rx_timer_sat
);
bit_synchronizer_gtwiz_reset_userclk_tx_active_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_7
port map (
E(0) => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
\FSM_sequential_sm_reset_tx_reg[0]\ => bit_synchronizer_plllock_tx_inst_n_2,
\FSM_sequential_sm_reset_tx_reg[0]_0\ => \FSM_sequential_sm_reset_tx[2]_i_6_n_0\,
\FSM_sequential_sm_reset_tx_reg[0]_1\ => sm_reset_tx_pll_timer_clr_reg_n_0,
\FSM_sequential_sm_reset_tx_reg[1]\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1,
\FSM_sequential_sm_reset_tx_reg[2]\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0,
Q(2 downto 0) => sm_reset_tx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
\gen_gtwizard_gtye4.txuserrdy_int\ => \^gen_gtwizard_gtye4.txuserrdy_int\,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
gtwiz_reset_tx_datapath_dly => gtwiz_reset_tx_datapath_dly,
gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly,
gtwiz_userclk_tx_active_out(0) => gtwiz_userclk_tx_active_out(0),
plllock_tx_sync => plllock_tx_sync,
sm_reset_tx_pll_timer_clr => sm_reset_tx_pll_timer_clr,
sm_reset_tx_pll_timer_sat => sm_reset_tx_pll_timer_sat,
sm_reset_tx_timer_clr_reg => sm_reset_tx_timer_clr_reg_n_0,
sm_reset_tx_timer_clr_reg_0 => \FSM_sequential_sm_reset_tx[2]_i_7_n_0\,
sm_reset_tx_timer_sat => sm_reset_tx_timer_sat
);
bit_synchronizer_plllock_rx_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_8
port map (
Q(2 downto 0) => sm_reset_rx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
gtrxreset_out_reg => sm_reset_rx_timer_clr_reg_n_0,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_qpll0lock_in(0) => gtwiz_reset_qpll0lock_in(0),
gtwiz_reset_rx_done_int_reg => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\,
gtwiz_reset_rx_done_int_reg_0 => gtwiz_reset_rx_done_int_reg_n_0,
i_in_out_reg_0 => bit_synchronizer_plllock_rx_inst_n_1,
i_in_out_reg_1 => bit_synchronizer_plllock_rx_inst_n_2,
i_in_out_reg_2 => bit_synchronizer_plllock_rx_inst_n_3,
plllock_rx_sync => plllock_rx_sync,
sm_reset_rx_timer_sat => sm_reset_rx_timer_sat
);
bit_synchronizer_plllock_tx_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_9
port map (
\FSM_sequential_sm_reset_tx_reg[0]\ => \FSM_sequential_sm_reset_tx[2]_i_7_n_0\,
Q(2 downto 0) => sm_reset_tx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
gttxreset_out_reg => sm_reset_tx_timer_clr_reg_n_0,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_qpll0lock_in(0) => gtwiz_reset_qpll0lock_in(0),
gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
gtwiz_reset_tx_done_int_reg => bit_synchronizer_plllock_tx_inst_n_1,
gtwiz_reset_tx_done_int_reg_0 => gtwiz_reset_tx_done_int_reg_n_0,
i_in_out_reg_0 => bit_synchronizer_plllock_tx_inst_n_2,
plllock_tx_sync => plllock_tx_sync,
sm_reset_tx_timer_sat => sm_reset_tx_timer_sat,
sm_reset_tx_timer_sat_reg => bit_synchronizer_plllock_tx_inst_n_3
);
bit_synchronizer_rxcdrlock_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_10
port map (
\FSM_sequential_sm_reset_rx_reg[0]\ => \FSM_sequential_sm_reset_rx[1]_i_2_n_0\,
\FSM_sequential_sm_reset_rx_reg[1]\ => bit_synchronizer_rxcdrlock_inst_n_2,
\FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_rxcdrlock_inst_n_1,
Q(2 downto 0) => sm_reset_rx(2 downto 0),
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
plllock_rx_sync => plllock_rx_sync,
rxcdrlock_out(0) => rxcdrlock_out(0),
sm_reset_rx_cdr_to_clr => sm_reset_rx_cdr_to_clr,
sm_reset_rx_cdr_to_clr_reg => \FSM_sequential_sm_reset_rx[2]_i_4_n_0\,
sm_reset_rx_cdr_to_sat => sm_reset_rx_cdr_to_sat,
sm_reset_rx_cdr_to_sat_reg => bit_synchronizer_rxcdrlock_inst_n_3
);
gtrxreset_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_3,
Q => \^gen_gtwizard_gtye4.gtrxreset_int\,
R => '0'
);
gttxreset_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_2,
Q => \gen_gtwizard_gtye4.gttxreset_int\,
R => '0'
);
\gtwiz_reset_qpll0reset_out[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\,
I1 => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
O => gtwiz_reset_qpll0reset_out(0)
);
gtwiz_reset_rx_datapath_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F740"
)
port map (
I0 => sm_reset_all(2),
I1 => sm_reset_all(0),
I2 => sm_reset_all(1),
I3 => gtwiz_reset_rx_datapath_int_reg_n_0,
O => gtwiz_reset_rx_datapath_int_i_1_n_0
);
gtwiz_reset_rx_datapath_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtwiz_reset_rx_datapath_int_i_1_n_0,
Q => gtwiz_reset_rx_datapath_int_reg_n_0,
R => gtwiz_reset_all_sync
);
gtwiz_reset_rx_done_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => bit_synchronizer_plllock_rx_inst_n_1,
Q => gtwiz_reset_rx_done_int_reg_n_0,
R => gtwiz_reset_rx_any_sync
);
gtwiz_reset_rx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F704"
)
port map (
I0 => sm_reset_all(0),
I1 => sm_reset_all(2),
I2 => sm_reset_all(1),
I3 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
O => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0
);
gtwiz_reset_rx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0,
Q => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
R => gtwiz_reset_all_sync
);
gtwiz_reset_tx_done_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => bit_synchronizer_plllock_tx_inst_n_1,
Q => gtwiz_reset_tx_done_int_reg_n_0,
R => gtwiz_reset_tx_any_sync
);
gtwiz_reset_tx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB02"
)
port map (
I0 => sm_reset_all(0),
I1 => sm_reset_all(1),
I2 => sm_reset_all(2),
I3 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0,
O => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0
);
gtwiz_reset_tx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0,
Q => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0,
R => gtwiz_reset_all_sync
);
\gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \gen_gtwizard_gtye4.gttxreset_int\,
I1 => gtpowergood_out(0),
I2 => \gen_gtwizard_gtye4.gtpowergood_int\,
O => \gen_gtwizard_gtye4.gttxreset_ch_int\
);
pllreset_rx_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1,
Q => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
R => '0'
);
pllreset_tx_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1,
Q => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\,
R => '0'
);
reset_synchronizer_gtwiz_reset_all_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer
port map (
gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
gtwiz_reset_all_sync => gtwiz_reset_all_sync,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0)
);
reset_synchronizer_gtwiz_reset_rx_any_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_11
port map (
\FSM_sequential_sm_reset_rx_reg[1]\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1,
\FSM_sequential_sm_reset_rx_reg[1]_0\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2,
\FSM_sequential_sm_reset_rx_reg[1]_1\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_3,
Q(2 downto 0) => sm_reset_rx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
\gen_gtwizard_gtye4.gtrxreset_int\ => \^gen_gtwizard_gtye4.gtrxreset_int\,
\gen_gtwizard_gtye4.rxprogdivreset_int\ => \^gen_gtwizard_gtye4.rxprogdivreset_int\,
gtrxreset_out_reg => bit_synchronizer_plllock_rx_inst_n_2,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0,
rst_in_out_reg_1 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
rxprogdivreset_out_reg => bit_synchronizer_rxcdrlock_inst_n_3
);
reset_synchronizer_gtwiz_reset_rx_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_12
port map (
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
in0 => gtwiz_reset_rx_datapath_sync,
rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0
);
reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_13
port map (
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
in0 => gtwiz_reset_rx_pll_and_datapath_sync,
rst_in_out_reg_0 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0
);
reset_synchronizer_gtwiz_reset_tx_any_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_14
port map (
\FSM_sequential_sm_reset_tx_reg[1]\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1,
Q(2 downto 0) => sm_reset_tx(2 downto 0),
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int\,
\gen_gtwizard_gtye4.gttxreset_int\ => \gen_gtwizard_gtye4.gttxreset_int\,
gttxreset_out_reg => bit_synchronizer_plllock_tx_inst_n_3,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
rst_in_out_reg_0 => reset_synchronizer_gtwiz_reset_tx_any_inst_n_2,
rst_in_out_reg_1 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0
);
reset_synchronizer_gtwiz_reset_tx_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_15
port map (
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
in0 => gtwiz_reset_tx_datapath_sync
);
reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_16
port map (
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
in0 => gtwiz_reset_tx_pll_and_datapath_sync,
rst_in_out_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0
);
reset_synchronizer_rx_done_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer
port map (
gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
gtwiz_userclk_rx_usrclk2_out(0) => gtwiz_userclk_rx_usrclk2_out(0),
rst_in_sync2_reg_0 => gtwiz_reset_rx_done_int_reg_n_0
);
reset_synchronizer_tx_done_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_inv_synchronizer_17
port map (
gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
gtwiz_userclk_tx_usrclk2_out(0) => gtwiz_userclk_tx_usrclk2_out(0),
rst_in_sync2_reg_0 => gtwiz_reset_tx_done_int_reg_n_0
);
reset_synchronizer_txprogdivreset_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_reset_synchronizer_18
port map (
\gen_gtwizard_gtye4.txprogdivreset_int\ => \gen_gtwizard_gtye4.txprogdivreset_int\,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_qpll0lock_in(0) => gtwiz_reset_qpll0lock_in(0)
);
rxprogdivreset_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2,
Q => \^gen_gtwizard_gtye4.rxprogdivreset_int\,
R => '0'
);
rxuserrdy_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1,
Q => \^gen_gtwizard_gtye4.rxuserrdy_int\,
R => '0'
);
sm_reset_all_timer_clr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFA200A"
)
port map (
I0 => sm_reset_all_timer_clr_i_2_n_0,
I1 => sm_reset_all(1),
I2 => sm_reset_all(2),
I3 => sm_reset_all(0),
I4 => sm_reset_all_timer_clr_reg_n_0,
O => sm_reset_all_timer_clr_i_1_n_0
);
sm_reset_all_timer_clr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B0003333BB33"
)
port map (
I0 => gtwiz_reset_rx_done_int_reg_n_0,
I1 => sm_reset_all(2),
I2 => gtwiz_reset_tx_done_int_reg_n_0,
I3 => sm_reset_all_timer_sat,
I4 => sm_reset_all_timer_clr_reg_n_0,
I5 => sm_reset_all(1),
O => sm_reset_all_timer_clr_i_2_n_0
);
sm_reset_all_timer_clr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_all_timer_clr_i_1_n_0,
Q => sm_reset_all_timer_clr_reg_n_0,
S => gtwiz_reset_all_sync
);
\sm_reset_all_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => sm_reset_all_timer_ctr(2),
I1 => sm_reset_all_timer_ctr(0),
I2 => sm_reset_all_timer_ctr(1),
O => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\
);
\sm_reset_all_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sm_reset_all_timer_ctr(0),
O => \sm_reset_all_timer_ctr[0]_i_1_n_0\
);
\sm_reset_all_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => sm_reset_all_timer_ctr(0),
I1 => sm_reset_all_timer_ctr(1),
O => \sm_reset_all_timer_ctr[1]_i_1_n_0\
);
\sm_reset_all_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => sm_reset_all_timer_ctr(0),
I1 => sm_reset_all_timer_ctr(1),
I2 => sm_reset_all_timer_ctr(2),
O => \sm_reset_all_timer_ctr[2]_i_1_n_0\
);
\sm_reset_all_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
D => \sm_reset_all_timer_ctr[0]_i_1_n_0\,
Q => sm_reset_all_timer_ctr(0),
R => sm_reset_all_timer_clr_reg_n_0
);
\sm_reset_all_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
D => \sm_reset_all_timer_ctr[1]_i_1_n_0\,
Q => sm_reset_all_timer_ctr(1),
R => sm_reset_all_timer_clr_reg_n_0
);
\sm_reset_all_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
D => \sm_reset_all_timer_ctr[2]_i_1_n_0\,
Q => sm_reset_all_timer_ctr(2),
R => sm_reset_all_timer_clr_reg_n_0
);
sm_reset_all_timer_sat_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF80"
)
port map (
I0 => sm_reset_all_timer_ctr(2),
I1 => sm_reset_all_timer_ctr(0),
I2 => sm_reset_all_timer_ctr(1),
I3 => sm_reset_all_timer_sat,
I4 => sm_reset_all_timer_clr_reg_n_0,
O => sm_reset_all_timer_sat_i_1_n_0
);
sm_reset_all_timer_sat_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_all_timer_sat_i_1_n_0,
Q => sm_reset_all_timer_sat,
R => '0'
);
sm_reset_rx_cdr_to_clr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => bit_synchronizer_rxcdrlock_inst_n_1,
Q => sm_reset_rx_cdr_to_clr,
S => gtwiz_reset_rx_any_sync
);
\sm_reset_rx_cdr_to_ctr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(1),
I1 => sm_reset_rx_cdr_to_ctr_reg(0),
I2 => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\,
I3 => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\,
I4 => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\,
I5 => \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\,
O => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\
);
\sm_reset_rx_cdr_to_ctr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFFFFFFFF"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(18),
I1 => sm_reset_rx_cdr_to_ctr_reg(19),
I2 => sm_reset_rx_cdr_to_ctr_reg(17),
I3 => sm_reset_rx_cdr_to_ctr_reg(16),
I4 => sm_reset_rx_cdr_to_ctr_reg(14),
I5 => sm_reset_rx_cdr_to_ctr_reg(15),
O => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\
);
\sm_reset_rx_cdr_to_ctr[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(24),
I1 => sm_reset_rx_cdr_to_ctr_reg(25),
I2 => sm_reset_rx_cdr_to_ctr_reg(22),
I3 => sm_reset_rx_cdr_to_ctr_reg(23),
I4 => sm_reset_rx_cdr_to_ctr_reg(21),
I5 => sm_reset_rx_cdr_to_ctr_reg(20),
O => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\
);
\sm_reset_rx_cdr_to_ctr[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF7FFF"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(12),
I1 => sm_reset_rx_cdr_to_ctr_reg(13),
I2 => sm_reset_rx_cdr_to_ctr_reg(10),
I3 => sm_reset_rx_cdr_to_ctr_reg(11),
I4 => sm_reset_rx_cdr_to_ctr_reg(9),
I5 => sm_reset_rx_cdr_to_ctr_reg(8),
O => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\
);
\sm_reset_rx_cdr_to_ctr[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(6),
I1 => sm_reset_rx_cdr_to_ctr_reg(7),
I2 => sm_reset_rx_cdr_to_ctr_reg(4),
I3 => sm_reset_rx_cdr_to_ctr_reg(5),
I4 => sm_reset_rx_cdr_to_ctr_reg(3),
I5 => sm_reset_rx_cdr_to_ctr_reg(2),
O => \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0\
);
\sm_reset_rx_cdr_to_ctr[0]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(0),
O => \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\
);
\sm_reset_rx_cdr_to_ctr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\,
Q => sm_reset_rx_cdr_to_ctr_reg(0),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[0]_i_2\: unisim.vcomponents.CARRY8
port map (
CI => '0',
CI_TOP => '0',
CO(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\,
CO(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\,
CO(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\,
CO(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\,
CO(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\,
CO(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\,
CO(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\,
CO(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\,
DI(7 downto 0) => B"00000001",
O(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\,
O(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\,
O(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\,
O(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\,
O(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\,
O(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\,
O(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\,
O(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\,
S(7 downto 1) => sm_reset_rx_cdr_to_ctr_reg(7 downto 1),
S(0) => \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0\
);
\sm_reset_rx_cdr_to_ctr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\,
Q => sm_reset_rx_cdr_to_ctr_reg(10),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\,
Q => sm_reset_rx_cdr_to_ctr_reg(11),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\,
Q => sm_reset_rx_cdr_to_ctr_reg(12),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\,
Q => sm_reset_rx_cdr_to_ctr_reg(13),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\,
Q => sm_reset_rx_cdr_to_ctr_reg(14),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\,
Q => sm_reset_rx_cdr_to_ctr_reg(15),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\,
Q => sm_reset_rx_cdr_to_ctr_reg(16),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[16]_i_1\: unisim.vcomponents.CARRY8
port map (
CI => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\,
CI_TOP => '0',
CO(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\,
CO(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\,
CO(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\,
CO(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\,
CO(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\,
CO(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\,
CO(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\,
CO(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\,
DI(7 downto 0) => B"00000000",
O(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\,
O(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\,
O(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\,
O(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\,
O(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\,
O(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\,
O(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\,
O(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\,
S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(23 downto 16)
);
\sm_reset_rx_cdr_to_ctr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\,
Q => sm_reset_rx_cdr_to_ctr_reg(17),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\,
Q => sm_reset_rx_cdr_to_ctr_reg(18),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\,
Q => sm_reset_rx_cdr_to_ctr_reg(19),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\,
Q => sm_reset_rx_cdr_to_ctr_reg(1),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\,
Q => sm_reset_rx_cdr_to_ctr_reg(20),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\,
Q => sm_reset_rx_cdr_to_ctr_reg(21),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\,
Q => sm_reset_rx_cdr_to_ctr_reg(22),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\,
Q => sm_reset_rx_cdr_to_ctr_reg(23),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\,
Q => sm_reset_rx_cdr_to_ctr_reg(24),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[24]_i_1\: unisim.vcomponents.CARRY8
port map (
CI => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\,
CI_TOP => '0',
CO(7 downto 1) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\(7 downto 1),
CO(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\,
DI(7 downto 0) => B"00000000",
O(7 downto 2) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\(7 downto 2),
O(1) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\,
O(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\,
S(7 downto 2) => B"000000",
S(1 downto 0) => sm_reset_rx_cdr_to_ctr_reg(25 downto 24)
);
\sm_reset_rx_cdr_to_ctr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\,
Q => sm_reset_rx_cdr_to_ctr_reg(25),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\,
Q => sm_reset_rx_cdr_to_ctr_reg(2),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\,
Q => sm_reset_rx_cdr_to_ctr_reg(3),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\,
Q => sm_reset_rx_cdr_to_ctr_reg(4),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\,
Q => sm_reset_rx_cdr_to_ctr_reg(5),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\,
Q => sm_reset_rx_cdr_to_ctr_reg(6),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\,
Q => sm_reset_rx_cdr_to_ctr_reg(7),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\,
Q => sm_reset_rx_cdr_to_ctr_reg(8),
R => sm_reset_rx_cdr_to_clr
);
\sm_reset_rx_cdr_to_ctr_reg[8]_i_1\: unisim.vcomponents.CARRY8
port map (
CI => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\,
CI_TOP => '0',
CO(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\,
CO(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\,
CO(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\,
CO(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\,
CO(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\,
CO(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\,
CO(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\,
CO(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\,
DI(7 downto 0) => B"00000000",
O(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\,
O(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\,
O(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\,
O(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\,
O(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\,
O(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\,
O(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\,
O(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\,
S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(15 downto 8)
);
\sm_reset_rx_cdr_to_ctr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\,
Q => sm_reset_rx_cdr_to_ctr_reg(9),
R => sm_reset_rx_cdr_to_clr
);
sm_reset_rx_cdr_to_sat_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => sm_reset_rx_cdr_to_sat,
I1 => sm_reset_rx_cdr_to_sat_i_2_n_0,
I2 => sm_reset_rx_cdr_to_clr,
O => sm_reset_rx_cdr_to_sat_i_1_n_0
);
sm_reset_rx_cdr_to_sat_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => sm_reset_rx_cdr_to_sat_i_3_n_0,
I1 => sm_reset_rx_cdr_to_sat_i_4_n_0,
I2 => sm_reset_rx_cdr_to_sat_i_5_n_0,
I3 => sm_reset_rx_cdr_to_sat_i_6_n_0,
I4 => sm_reset_rx_cdr_to_ctr_reg(1),
I5 => sm_reset_rx_cdr_to_ctr_reg(0),
O => sm_reset_rx_cdr_to_sat_i_2_n_0
);
sm_reset_rx_cdr_to_sat_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(4),
I1 => sm_reset_rx_cdr_to_ctr_reg(5),
I2 => sm_reset_rx_cdr_to_ctr_reg(2),
I3 => sm_reset_rx_cdr_to_ctr_reg(3),
I4 => sm_reset_rx_cdr_to_ctr_reg(7),
I5 => sm_reset_rx_cdr_to_ctr_reg(6),
O => sm_reset_rx_cdr_to_sat_i_3_n_0
);
sm_reset_rx_cdr_to_sat_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(22),
I1 => sm_reset_rx_cdr_to_ctr_reg(23),
I2 => sm_reset_rx_cdr_to_ctr_reg(20),
I3 => sm_reset_rx_cdr_to_ctr_reg(21),
I4 => sm_reset_rx_cdr_to_ctr_reg(25),
I5 => sm_reset_rx_cdr_to_ctr_reg(24),
O => sm_reset_rx_cdr_to_sat_i_4_n_0
);
sm_reset_rx_cdr_to_sat_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(17),
I1 => sm_reset_rx_cdr_to_ctr_reg(16),
I2 => sm_reset_rx_cdr_to_ctr_reg(15),
I3 => sm_reset_rx_cdr_to_ctr_reg(14),
I4 => sm_reset_rx_cdr_to_ctr_reg(19),
I5 => sm_reset_rx_cdr_to_ctr_reg(18),
O => sm_reset_rx_cdr_to_sat_i_5_n_0
);
sm_reset_rx_cdr_to_sat_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => sm_reset_rx_cdr_to_ctr_reg(10),
I1 => sm_reset_rx_cdr_to_ctr_reg(11),
I2 => sm_reset_rx_cdr_to_ctr_reg(8),
I3 => sm_reset_rx_cdr_to_ctr_reg(9),
I4 => sm_reset_rx_cdr_to_ctr_reg(13),
I5 => sm_reset_rx_cdr_to_ctr_reg(12),
O => sm_reset_rx_cdr_to_sat_i_6_n_0
);
sm_reset_rx_cdr_to_sat_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_rx_cdr_to_sat_i_1_n_0,
Q => sm_reset_rx_cdr_to_sat,
R => '0'
);
sm_reset_rx_pll_timer_clr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF3000B"
)
port map (
I0 => sm_reset_rx_pll_timer_sat,
I1 => sm_reset_rx(0),
I2 => sm_reset_rx(1),
I3 => sm_reset_rx(2),
I4 => sm_reset_rx_pll_timer_clr_reg_n_0,
O => sm_reset_rx_pll_timer_clr_i_1_n_0
);
sm_reset_rx_pll_timer_clr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_rx_pll_timer_clr_i_1_n_0,
Q => sm_reset_rx_pll_timer_clr_reg_n_0,
S => gtwiz_reset_rx_any_sync
);
\sm_reset_rx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(0),
O => \p_0_in__1\(0)
);
\sm_reset_rx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(0),
I1 => sm_reset_rx_pll_timer_ctr_reg(1),
O => \p_0_in__1\(1)
);
\sm_reset_rx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(1),
I1 => sm_reset_rx_pll_timer_ctr_reg(0),
I2 => sm_reset_rx_pll_timer_ctr_reg(2),
O => \sm_reset_rx_pll_timer_ctr[2]_i_1_n_0\
);
\sm_reset_rx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(2),
I1 => sm_reset_rx_pll_timer_ctr_reg(0),
I2 => sm_reset_rx_pll_timer_ctr_reg(1),
I3 => sm_reset_rx_pll_timer_ctr_reg(3),
O => \sm_reset_rx_pll_timer_ctr[3]_i_1_n_0\
);
\sm_reset_rx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(1),
I1 => sm_reset_rx_pll_timer_ctr_reg(0),
I2 => sm_reset_rx_pll_timer_ctr_reg(2),
I3 => sm_reset_rx_pll_timer_ctr_reg(3),
I4 => sm_reset_rx_pll_timer_ctr_reg(4),
O => \p_0_in__1\(4)
);
\sm_reset_rx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(4),
I1 => sm_reset_rx_pll_timer_ctr_reg(3),
I2 => sm_reset_rx_pll_timer_ctr_reg(2),
I3 => sm_reset_rx_pll_timer_ctr_reg(0),
I4 => sm_reset_rx_pll_timer_ctr_reg(1),
I5 => sm_reset_rx_pll_timer_ctr_reg(5),
O => \p_0_in__1\(5)
);
\sm_reset_rx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
I1 => sm_reset_rx_pll_timer_ctr_reg(6),
O => \p_0_in__1\(6)
);
\sm_reset_rx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(6),
I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
I2 => sm_reset_rx_pll_timer_ctr_reg(7),
O => \p_0_in__1\(7)
);
\sm_reset_rx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
I1 => sm_reset_rx_pll_timer_ctr_reg(6),
I2 => sm_reset_rx_pll_timer_ctr_reg(7),
I3 => sm_reset_rx_pll_timer_ctr_reg(8),
O => \p_0_in__1\(8)
);
\sm_reset_rx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFFFFF"
)
port map (
I0 => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\,
I1 => sm_reset_rx_pll_timer_ctr_reg(3),
I2 => sm_reset_rx_pll_timer_ctr_reg(1),
I3 => sm_reset_rx_pll_timer_ctr_reg(0),
I4 => sm_reset_rx_pll_timer_ctr_reg(2),
O => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\
);
\sm_reset_rx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
I1 => sm_reset_rx_pll_timer_ctr_reg(8),
I2 => sm_reset_rx_pll_timer_ctr_reg(7),
I3 => sm_reset_rx_pll_timer_ctr_reg(6),
I4 => sm_reset_rx_pll_timer_ctr_reg(9),
O => \p_0_in__1\(9)
);
\sm_reset_rx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(8),
I1 => sm_reset_rx_pll_timer_ctr_reg(9),
I2 => sm_reset_rx_pll_timer_ctr_reg(6),
I3 => sm_reset_rx_pll_timer_ctr_reg(7),
I4 => sm_reset_rx_pll_timer_ctr_reg(5),
I5 => sm_reset_rx_pll_timer_ctr_reg(4),
O => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\
);
\sm_reset_rx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(4),
I1 => sm_reset_rx_pll_timer_ctr_reg(3),
I2 => sm_reset_rx_pll_timer_ctr_reg(2),
I3 => sm_reset_rx_pll_timer_ctr_reg(0),
I4 => sm_reset_rx_pll_timer_ctr_reg(1),
I5 => sm_reset_rx_pll_timer_ctr_reg(5),
O => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\
);
\sm_reset_rx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(0),
Q => sm_reset_rx_pll_timer_ctr_reg(0),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(1),
Q => sm_reset_rx_pll_timer_ctr_reg(1),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \sm_reset_rx_pll_timer_ctr[2]_i_1_n_0\,
Q => sm_reset_rx_pll_timer_ctr_reg(2),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \sm_reset_rx_pll_timer_ctr[3]_i_1_n_0\,
Q => sm_reset_rx_pll_timer_ctr_reg(3),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(4),
Q => sm_reset_rx_pll_timer_ctr_reg(4),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(5),
Q => sm_reset_rx_pll_timer_ctr_reg(5),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(6),
Q => sm_reset_rx_pll_timer_ctr_reg(6),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(7),
Q => sm_reset_rx_pll_timer_ctr_reg(7),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(8),
Q => sm_reset_rx_pll_timer_ctr_reg(8),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
\sm_reset_rx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__1\(9),
Q => sm_reset_rx_pll_timer_ctr_reg(9),
R => sm_reset_rx_pll_timer_clr_reg_n_0
);
sm_reset_rx_pll_timer_sat_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000ABAA"
)
port map (
I0 => sm_reset_rx_pll_timer_sat,
I1 => sm_reset_rx_pll_timer_ctr_reg(3),
I2 => sm_reset_rx_pll_timer_sat_i_2_n_0,
I3 => sm_reset_rx_pll_timer_sat_i_3_n_0,
I4 => sm_reset_rx_pll_timer_clr_reg_n_0,
O => sm_reset_rx_pll_timer_sat_i_1_n_0
);
sm_reset_rx_pll_timer_sat_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(1),
I1 => sm_reset_rx_pll_timer_ctr_reg(0),
I2 => sm_reset_rx_pll_timer_ctr_reg(2),
O => sm_reset_rx_pll_timer_sat_i_2_n_0
);
sm_reset_rx_pll_timer_sat_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => sm_reset_rx_pll_timer_ctr_reg(6),
I1 => sm_reset_rx_pll_timer_ctr_reg(7),
I2 => sm_reset_rx_pll_timer_ctr_reg(4),
I3 => sm_reset_rx_pll_timer_ctr_reg(5),
I4 => sm_reset_rx_pll_timer_ctr_reg(9),
I5 => sm_reset_rx_pll_timer_ctr_reg(8),
O => sm_reset_rx_pll_timer_sat_i_3_n_0
);
sm_reset_rx_pll_timer_sat_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_rx_pll_timer_sat_i_1_n_0,
Q => sm_reset_rx_pll_timer_sat,
R => '0'
);
sm_reset_rx_timer_clr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0,
Q => sm_reset_rx_timer_clr_reg_n_0,
S => gtwiz_reset_rx_any_sync
);
\sm_reset_rx_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => sm_reset_rx_timer_ctr(2),
I1 => sm_reset_rx_timer_ctr(0),
I2 => sm_reset_rx_timer_ctr(1),
O => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\
);
\sm_reset_rx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sm_reset_rx_timer_ctr(0),
O => \sm_reset_rx_timer_ctr[0]_i_1_n_0\
);
\sm_reset_rx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => sm_reset_rx_timer_ctr(0),
I1 => sm_reset_rx_timer_ctr(1),
O => \sm_reset_rx_timer_ctr[1]_i_1_n_0\
);
\sm_reset_rx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => sm_reset_rx_timer_ctr(0),
I1 => sm_reset_rx_timer_ctr(1),
I2 => sm_reset_rx_timer_ctr(2),
O => \sm_reset_rx_timer_ctr[2]_i_1_n_0\
);
\sm_reset_rx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
D => \sm_reset_rx_timer_ctr[0]_i_1_n_0\,
Q => sm_reset_rx_timer_ctr(0),
R => sm_reset_rx_timer_clr_reg_n_0
);
\sm_reset_rx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
D => \sm_reset_rx_timer_ctr[1]_i_1_n_0\,
Q => sm_reset_rx_timer_ctr(1),
R => sm_reset_rx_timer_clr_reg_n_0
);
\sm_reset_rx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
D => \sm_reset_rx_timer_ctr[2]_i_1_n_0\,
Q => sm_reset_rx_timer_ctr(2),
R => sm_reset_rx_timer_clr_reg_n_0
);
sm_reset_rx_timer_sat_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF80"
)
port map (
I0 => sm_reset_rx_timer_ctr(2),
I1 => sm_reset_rx_timer_ctr(0),
I2 => sm_reset_rx_timer_ctr(1),
I3 => sm_reset_rx_timer_sat,
I4 => sm_reset_rx_timer_clr_reg_n_0,
O => sm_reset_rx_timer_sat_i_1_n_0
);
sm_reset_rx_timer_sat_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_rx_timer_sat_i_1_n_0,
Q => sm_reset_rx_timer_sat,
R => '0'
);
sm_reset_tx_pll_timer_clr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF5000D"
)
port map (
I0 => sm_reset_tx(0),
I1 => sm_reset_tx_pll_timer_sat,
I2 => sm_reset_tx(1),
I3 => sm_reset_tx(2),
I4 => sm_reset_tx_pll_timer_clr_reg_n_0,
O => sm_reset_tx_pll_timer_clr_i_1_n_0
);
sm_reset_tx_pll_timer_clr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_tx_pll_timer_clr_i_1_n_0,
Q => sm_reset_tx_pll_timer_clr_reg_n_0,
S => gtwiz_reset_tx_any_sync
);
\sm_reset_tx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(0),
O => \p_0_in__0\(0)
);
\sm_reset_tx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(0),
I1 => sm_reset_tx_pll_timer_ctr_reg(1),
O => \p_0_in__0\(1)
);
\sm_reset_tx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(1),
I1 => sm_reset_tx_pll_timer_ctr_reg(0),
I2 => sm_reset_tx_pll_timer_ctr_reg(2),
O => \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\
);
\sm_reset_tx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(2),
I1 => sm_reset_tx_pll_timer_ctr_reg(0),
I2 => sm_reset_tx_pll_timer_ctr_reg(1),
I3 => sm_reset_tx_pll_timer_ctr_reg(3),
O => \sm_reset_tx_pll_timer_ctr[3]_i_1_n_0\
);
\sm_reset_tx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(1),
I1 => sm_reset_tx_pll_timer_ctr_reg(0),
I2 => sm_reset_tx_pll_timer_ctr_reg(2),
I3 => sm_reset_tx_pll_timer_ctr_reg(3),
I4 => sm_reset_tx_pll_timer_ctr_reg(4),
O => \p_0_in__0\(4)
);
\sm_reset_tx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(4),
I1 => sm_reset_tx_pll_timer_ctr_reg(3),
I2 => sm_reset_tx_pll_timer_ctr_reg(2),
I3 => sm_reset_tx_pll_timer_ctr_reg(0),
I4 => sm_reset_tx_pll_timer_ctr_reg(1),
I5 => sm_reset_tx_pll_timer_ctr_reg(5),
O => \p_0_in__0\(5)
);
\sm_reset_tx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
I1 => sm_reset_tx_pll_timer_ctr_reg(6),
O => \p_0_in__0\(6)
);
\sm_reset_tx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(6),
I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
I2 => sm_reset_tx_pll_timer_ctr_reg(7),
O => \p_0_in__0\(7)
);
\sm_reset_tx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
I1 => sm_reset_tx_pll_timer_ctr_reg(6),
I2 => sm_reset_tx_pll_timer_ctr_reg(7),
I3 => sm_reset_tx_pll_timer_ctr_reg(8),
O => \p_0_in__0\(8)
);
\sm_reset_tx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFFFFF"
)
port map (
I0 => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\,
I1 => sm_reset_tx_pll_timer_ctr_reg(3),
I2 => sm_reset_tx_pll_timer_ctr_reg(1),
I3 => sm_reset_tx_pll_timer_ctr_reg(0),
I4 => sm_reset_tx_pll_timer_ctr_reg(2),
O => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\
);
\sm_reset_tx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
I1 => sm_reset_tx_pll_timer_ctr_reg(8),
I2 => sm_reset_tx_pll_timer_ctr_reg(7),
I3 => sm_reset_tx_pll_timer_ctr_reg(6),
I4 => sm_reset_tx_pll_timer_ctr_reg(9),
O => \p_0_in__0\(9)
);
\sm_reset_tx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(8),
I1 => sm_reset_tx_pll_timer_ctr_reg(9),
I2 => sm_reset_tx_pll_timer_ctr_reg(6),
I3 => sm_reset_tx_pll_timer_ctr_reg(7),
I4 => sm_reset_tx_pll_timer_ctr_reg(5),
I5 => sm_reset_tx_pll_timer_ctr_reg(4),
O => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\
);
\sm_reset_tx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(4),
I1 => sm_reset_tx_pll_timer_ctr_reg(3),
I2 => sm_reset_tx_pll_timer_ctr_reg(2),
I3 => sm_reset_tx_pll_timer_ctr_reg(0),
I4 => sm_reset_tx_pll_timer_ctr_reg(1),
I5 => sm_reset_tx_pll_timer_ctr_reg(5),
O => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\
);
\sm_reset_tx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(0),
Q => sm_reset_tx_pll_timer_ctr_reg(0),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(1),
Q => sm_reset_tx_pll_timer_ctr_reg(1),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\,
Q => sm_reset_tx_pll_timer_ctr_reg(2),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \sm_reset_tx_pll_timer_ctr[3]_i_1_n_0\,
Q => sm_reset_tx_pll_timer_ctr_reg(3),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(4),
Q => sm_reset_tx_pll_timer_ctr_reg(4),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(5),
Q => sm_reset_tx_pll_timer_ctr_reg(5),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(6),
Q => sm_reset_tx_pll_timer_ctr_reg(6),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(7),
Q => sm_reset_tx_pll_timer_ctr_reg(7),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(8),
Q => sm_reset_tx_pll_timer_ctr_reg(8),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
\sm_reset_tx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => \sm_reset_tx_pll_timer_ctr[9]_i_1_n_0\,
D => \p_0_in__0\(9),
Q => sm_reset_tx_pll_timer_ctr_reg(9),
R => sm_reset_tx_pll_timer_clr_reg_n_0
);
sm_reset_tx_pll_timer_sat_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000ABAA"
)
port map (
I0 => sm_reset_tx_pll_timer_sat,
I1 => sm_reset_tx_pll_timer_ctr_reg(3),
I2 => sm_reset_tx_pll_timer_sat_i_2_n_0,
I3 => sm_reset_tx_pll_timer_sat_i_3_n_0,
I4 => sm_reset_tx_pll_timer_clr_reg_n_0,
O => sm_reset_tx_pll_timer_sat_i_1_n_0
);
sm_reset_tx_pll_timer_sat_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(1),
I1 => sm_reset_tx_pll_timer_ctr_reg(0),
I2 => sm_reset_tx_pll_timer_ctr_reg(2),
O => sm_reset_tx_pll_timer_sat_i_2_n_0
);
sm_reset_tx_pll_timer_sat_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => sm_reset_tx_pll_timer_ctr_reg(6),
I1 => sm_reset_tx_pll_timer_ctr_reg(7),
I2 => sm_reset_tx_pll_timer_ctr_reg(4),
I3 => sm_reset_tx_pll_timer_ctr_reg(5),
I4 => sm_reset_tx_pll_timer_ctr_reg(9),
I5 => sm_reset_tx_pll_timer_ctr_reg(8),
O => sm_reset_tx_pll_timer_sat_i_3_n_0
);
sm_reset_tx_pll_timer_sat_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_tx_pll_timer_sat_i_1_n_0,
Q => sm_reset_tx_pll_timer_sat,
R => '0'
);
sm_reset_tx_timer_clr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0,
Q => sm_reset_tx_timer_clr_reg_n_0,
S => gtwiz_reset_tx_any_sync
);
\sm_reset_tx_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => sm_reset_tx_timer_ctr(2),
I1 => sm_reset_tx_timer_ctr(0),
I2 => sm_reset_tx_timer_ctr(1),
O => p_0_in
);
\sm_reset_tx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sm_reset_tx_timer_ctr(0),
O => \sm_reset_tx_timer_ctr[0]_i_1_n_0\
);
\sm_reset_tx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => sm_reset_tx_timer_ctr(0),
I1 => sm_reset_tx_timer_ctr(1),
O => \sm_reset_tx_timer_ctr[1]_i_1_n_0\
);
\sm_reset_tx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => sm_reset_tx_timer_ctr(0),
I1 => sm_reset_tx_timer_ctr(1),
I2 => sm_reset_tx_timer_ctr(2),
O => \sm_reset_tx_timer_ctr[2]_i_1_n_0\
);
\sm_reset_tx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => p_0_in,
D => \sm_reset_tx_timer_ctr[0]_i_1_n_0\,
Q => sm_reset_tx_timer_ctr(0),
R => sm_reset_tx_timer_clr_reg_n_0
);
\sm_reset_tx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => p_0_in,
D => \sm_reset_tx_timer_ctr[1]_i_1_n_0\,
Q => sm_reset_tx_timer_ctr(1),
R => sm_reset_tx_timer_clr_reg_n_0
);
\sm_reset_tx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => p_0_in,
D => \sm_reset_tx_timer_ctr[2]_i_1_n_0\,
Q => sm_reset_tx_timer_ctr(2),
R => sm_reset_tx_timer_clr_reg_n_0
);
sm_reset_tx_timer_sat_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF80"
)
port map (
I0 => sm_reset_tx_timer_ctr(2),
I1 => sm_reset_tx_timer_ctr(0),
I2 => sm_reset_tx_timer_ctr(1),
I3 => sm_reset_tx_timer_sat,
I4 => sm_reset_tx_timer_clr_reg_n_0,
O => sm_reset_tx_timer_sat_i_1_n_0
);
sm_reset_tx_timer_sat_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => sm_reset_tx_timer_sat_i_1_n_0,
Q => sm_reset_tx_timer_sat,
R => '0'
);
txuserrdy_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => gtwiz_reset_clk_freerun_in(0),
CE => '1',
D => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1,
Q => \^gen_gtwizard_gtye4.txuserrdy_int\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_gtye4 is
port (
gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_gtye4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_gtye4 is
signal \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_12\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_3\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_7\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_89\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_9\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gtpowergood_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gtrxreset_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.gttxreset_ch_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.rxprogdivreset_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.rxuserrdy_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.txpisopd_ch_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.txprogdivreset_int\ : STD_LOGIC;
signal \gen_gtwizard_gtye4.txuserrdy_int\ : STD_LOGIC;
signal \^gtpowergood_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_rx_active_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_rx_srcclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_rx_usrclk2_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_tx_active_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_tx_srcclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_tx_usrclk2_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal lopt : STD_LOGIC;
signal lopt_1 : STD_LOGIC;
signal lopt_2 : STD_LOGIC;
signal lopt_3 : STD_LOGIC;
signal lopt_4 : STD_LOGIC;
signal lopt_5 : STD_LOGIC;
begin
gtpowergood_out(0) <= \^gtpowergood_out\(0);
gtwiz_userclk_rx_active_out(0) <= \^gtwiz_userclk_rx_active_out\(0);
gtwiz_userclk_rx_srcclk_out(0) <= \^gtwiz_userclk_rx_srcclk_out\(0);
gtwiz_userclk_rx_usrclk2_out(0) <= \^gtwiz_userclk_rx_usrclk2_out\(0);
gtwiz_userclk_tx_active_out(0) <= \^gtwiz_userclk_tx_active_out\(0);
gtwiz_userclk_tx_srcclk_out(0) <= \^gtwiz_userclk_tx_srcclk_out\(0);
gtwiz_userclk_tx_usrclk2_out(0) <= \^gtwiz_userclk_tx_usrclk2_out\(0);
\gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtye4_channel_wrapper
port map (
TXRATE(0) => \gen_gtwizard_gtye4.txpisopd_ch_int\,
\gen_gtwizard_gtye4.gtpowergood_int\ => \gen_gtwizard_gtye4.gtpowergood_int\,
\gen_gtwizard_gtye4.gtrxreset_int\ => \gen_gtwizard_gtye4.gtrxreset_int\,
\gen_gtwizard_gtye4.gttxreset_ch_int\ => \gen_gtwizard_gtye4.gttxreset_ch_int\,
\gen_gtwizard_gtye4.rxprogdivreset_int\ => \gen_gtwizard_gtye4.rxprogdivreset_int\,
\gen_gtwizard_gtye4.rxuserrdy_int\ => \gen_gtwizard_gtye4.rxuserrdy_int\,
\gen_gtwizard_gtye4.txprogdivreset_int\ => \gen_gtwizard_gtye4.txprogdivreset_int\,
\gen_gtwizard_gtye4.txuserrdy_int\ => \gen_gtwizard_gtye4.txuserrdy_int\,
gtwiz_userclk_rx_srcclk_out(0) => \^gtwiz_userclk_rx_srcclk_out\(0),
gtwiz_userclk_rx_usrclk2_out(0) => \^gtwiz_userclk_rx_usrclk2_out\(0),
gtwiz_userclk_tx_srcclk_out(0) => \^gtwiz_userclk_tx_srcclk_out\(0),
gtwiz_userclk_tx_usrclk2_out(0) => \^gtwiz_userclk_tx_usrclk2_out\(0),
gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0),
\gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST\ => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_89\,
gtyrxn_in(0) => gtyrxn_in(0),
gtyrxp_in(0) => gtyrxp_in(0),
gtytxn_out(0) => gtytxn_out(0),
gtytxp_out(0) => gtytxp_out(0),
lopt => lopt,
lopt_1 => gtwiz_userclk_rx_reset_in(0),
lopt_2 => lopt_1,
lopt_3 => lopt_2,
lopt_4 => lopt_3,
lopt_5 => gtwiz_userclk_tx_reset_in(0),
lopt_6 => lopt_4,
lopt_7 => lopt_5,
qpll0clk_in(0) => qpll0clk_in(0),
qpll0refclk_in(0) => qpll0refclk_in(0),
qpll1clk_in(0) => qpll1clk_in(0),
qpll1refclk_in(0) => qpll1refclk_in(0),
rxcdrlock_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_3\,
rxdatavalid_out(1 downto 0) => rxdatavalid_out(1 downto 0),
rxgearboxslip_in(0) => rxgearboxslip_in(0),
rxheader_out(5 downto 0) => rxheader_out(5 downto 0),
rxheadervalid_out(1 downto 0) => rxheadervalid_out(1 downto 0),
rxpmaresetdone_out(0) => rxpmaresetdone_out(0),
rxprgdivresetdone_out(0) => rxprgdivresetdone_out(0),
rxresetdone_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_7\,
rxstartofseq_out(1 downto 0) => rxstartofseq_out(1 downto 0),
txheader_in(5 downto 0) => txheader_in(5 downto 0),
txoutclkpcs_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_9\,
txpmaresetdone_out(0) => txpmaresetdone_out(0),
txprgdivresetdone_out(0) => txprgdivresetdone_out(0),
txresetdone_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_12\,
txsequence_in(6 downto 0) => txsequence_in(6 downto 0)
);
\gen_gtwizard_gtye4.gen_pwrgood_delay_inst[0].delay_powergood_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtye4_delay_powergood
port map (
TXRATE(0) => \gen_gtwizard_gtye4.txpisopd_ch_int\,
\gen_powergood_delay.intclk_rrst_n_r_reg[4]_0\ => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_89\,
\out\ => \^gtpowergood_out\(0),
txoutclkpcs_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_9\
);
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer
port map (
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
rxresetdone_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_7\
);
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_bit_synchronizer_0
port map (
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
txresetdone_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_12\
);
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_reset
port map (
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\,
\gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ => \gen_gtwizard_gtye4.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\,
\gen_gtwizard_gtye4.gtpowergood_int\ => \gen_gtwizard_gtye4.gtpowergood_int\,
\gen_gtwizard_gtye4.gtrxreset_int\ => \gen_gtwizard_gtye4.gtrxreset_int\,
\gen_gtwizard_gtye4.gttxreset_ch_int\ => \gen_gtwizard_gtye4.gttxreset_ch_int\,
\gen_gtwizard_gtye4.rxprogdivreset_int\ => \gen_gtwizard_gtye4.rxprogdivreset_int\,
\gen_gtwizard_gtye4.rxuserrdy_int\ => \gen_gtwizard_gtye4.rxuserrdy_int\,
\gen_gtwizard_gtye4.txprogdivreset_int\ => \gen_gtwizard_gtye4.txprogdivreset_int\,
\gen_gtwizard_gtye4.txuserrdy_int\ => \gen_gtwizard_gtye4.txuserrdy_int\,
gtpowergood_out(0) => \^gtpowergood_out\(0),
gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_qpll0lock_in(0) => gtwiz_reset_qpll0lock_in(0),
gtwiz_reset_qpll0reset_out(0) => gtwiz_reset_qpll0reset_out(0),
gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
gtwiz_userclk_rx_active_out(0) => \^gtwiz_userclk_rx_active_out\(0),
gtwiz_userclk_rx_usrclk2_out(0) => \^gtwiz_userclk_rx_usrclk2_out\(0),
gtwiz_userclk_tx_active_out(0) => \^gtwiz_userclk_tx_active_out\(0),
gtwiz_userclk_tx_usrclk2_out(0) => \^gtwiz_userclk_tx_usrclk2_out\(0),
rxcdrlock_out(0) => \gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst_n_3\
);
\gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_rx
port map (
gtwiz_userclk_rx_active_out(0) => \^gtwiz_userclk_rx_active_out\(0),
gtwiz_userclk_rx_reset_in(0) => gtwiz_userclk_rx_reset_in(0),
gtwiz_userclk_rx_srcclk_out(0) => \^gtwiz_userclk_rx_srcclk_out\(0),
gtwiz_userclk_rx_usrclk2_out(0) => \^gtwiz_userclk_rx_usrclk2_out\(0),
lopt => lopt,
lopt_1 => lopt_1,
lopt_2 => lopt_2
);
\gen_gtwizard_gtye4.gen_tx_user_clocking_internal.gen_single_instance.gtwiz_userclk_tx_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_12_gtwiz_userclk_tx
port map (
gtwiz_userclk_tx_active_out(0) => \^gtwiz_userclk_tx_active_out\(0),
gtwiz_userclk_tx_reset_in(0) => gtwiz_userclk_tx_reset_in(0),
gtwiz_userclk_tx_srcclk_out(0) => \^gtwiz_userclk_tx_srcclk_out\(0),
gtwiz_userclk_tx_usrclk2_out(0) => \^gtwiz_userclk_tx_usrclk2_out\(0),
lopt => lopt_3,
lopt_1 => lopt_4,
lopt_2 => lopt_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top is
port (
gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_rx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_buffbypass_rx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll1lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll1reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_gthe3_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 );
gtwiz_gthe3_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 );
gtwiz_gthe3_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_gthe4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 );
gtwiz_gthe4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 );
gtwiz_gthe4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_gtye4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 17 downto 0 );
gtwiz_gtye4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 17 downto 0 );
gtwiz_gtye4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
bgbypassb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
bgmonitorenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
bgpdb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
bgrcalovrd_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
bgrcalovrdenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drpaddr_common_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
drpclk_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drpdi_common_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
drpen_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drpwe_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtgrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtgrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtnorthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtnorthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtnorthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtnorthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtsouthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtsouthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtsouthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtsouthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
pcierateqpll0_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
pcierateqpll1_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
pmarsvd0_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
pmarsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
qpll0clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0fbdiv_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
qpll0lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0locken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0pd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
qpll0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1fbdiv_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
qpll1lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1locken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1pd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
qpll1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpllrsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
qpllrsvd2_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
qpllrsvd3_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
qpllrsvd4_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
rcalenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
sdm0data_in : in STD_LOGIC_VECTOR ( 24 downto 0 );
sdm0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
sdm0toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
sdm0width_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
sdm1data_in : in STD_LOGIC_VECTOR ( 24 downto 0 );
sdm1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
sdm1toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
sdm1width_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
tcongpi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
tconpowerup_in : in STD_LOGIC_VECTOR ( 0 to 0 );
tconreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
tconrsvdin1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubcfgstreamen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubdo_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
ubdrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubenable_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubgpi_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
ubintr_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
ubiolmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmcapture_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmdbgrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmdbgupdate_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmregen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
ubmdmshift_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmsysrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmtck_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmtdi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drpdo_common_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
drprdy_common_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pmarsvdout0_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
pmarsvdout1_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll0refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qpll1refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
qplldmonitor0_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
qplldmonitor1_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
refclkoutmonitor0_out : out STD_LOGIC_VECTOR ( 0 to 0 );
refclkoutmonitor1_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxrecclk0_sel_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxrecclk1_sel_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxrecclk0sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxrecclk1sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
sdm0finalout_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
sdm0testdata_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
sdm1finalout_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
sdm1testdata_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
tcongpo_out : out STD_LOGIC_VECTOR ( 0 to 0 );
tconrsvdout0_out : out STD_LOGIC_VECTOR ( 0 to 0 );
ubdaddr_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
ubden_out : out STD_LOGIC_VECTOR ( 0 to 0 );
ubdi_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
ubdwe_out : out STD_LOGIC_VECTOR ( 0 to 0 );
ubmdmtdo_out : out STD_LOGIC_VECTOR ( 0 to 0 );
ubrsvdout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
ubtxuart_out : out STD_LOGIC_VECTOR ( 0 to 0 );
cdrstepdir_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cdrstepsq_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cdrstepsx_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cfgreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cpllfreqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cplllockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cplllocken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cpllpd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
cpllrefclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
cpllreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
dmonfiforeset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
dmonitorclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drpaddr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
drpen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drprst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
drpwe_in : in STD_LOGIC_VECTOR ( 0 to 0 );
elpcaldvorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
elpcalpaorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
evoddphicaldone_in : in STD_LOGIC_VECTOR ( 0 to 0 );
evoddphicalstart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
evoddphidrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
evoddphidwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
evoddphixrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
evoddphixwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
eyescanmode_in : in STD_LOGIC_VECTOR ( 0 to 0 );
eyescanreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
eyescantrigger_in : in STD_LOGIC_VECTOR ( 0 to 0 );
freqos_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtgrefclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtnorthrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtnorthrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrsvd_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
gtrxreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtrxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtsouthrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtsouthrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gttxreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gttxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
incpctrl_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
looprsvd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
lpbkrxtxseren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
lpbktxrxseren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
pcieeqrxeqadaptdone_in : in STD_LOGIC_VECTOR ( 0 to 0 );
pcierstidle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
pciersttxsyncstart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
pcieuserratedone_in : in STD_LOGIC_VECTOR ( 0 to 0 );
pcsrsvdin_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
pcsrsvdin2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
pmarsvdin_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
resetovrd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rstclkentx_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxafecfoken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxbufreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrfreqreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrresetrsv_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxchbonden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxchbondi_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
rxchbondlevel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
rxchbondmaster_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxchbondslave_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxckcalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxckcalstart_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
rxcommadeten_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfeagcctrl_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfeagchold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfeagcovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfecfokfcnum_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
rxdfecfokfen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfecfokfpulse_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfecfokhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfecfokovren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfekhhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfekhovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfelfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfelfovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfelpmreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap10hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap10ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap11hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap11ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap12hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap12ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap13hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap13ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap14hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap14ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap15hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap15ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap2hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap2ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap3hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap3ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap4hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap4ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap5hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap5ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap6hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap6ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap7hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap7ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap8hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap8ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap9hold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfetap9ovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfeuthold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfeutovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfevphold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfevpovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfevsen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdfexyden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdlybypass_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdlyen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdlyovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxdlysreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxelecidlemode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
rxeqtraining_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlatclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmgchold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmgcovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmhfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmhfovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmlfhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmlfklovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmoshold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxlpmosovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
rxoobreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxoscalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxoshold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxosintcfg_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxosinten_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxosinthold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxosintovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxosintstrobe_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxosinttestovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxosovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxoutclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
rxphalign_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxphalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxphdlypd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxphdlyreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxphovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxpllclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
rxpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxprbscntreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
rxprogdivreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxqpien_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxrate_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
rxratemode_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxslide_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxslipoutclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxslippma_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxsyncallin_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxsyncin_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxsyncmode_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxsysclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
rxtermination_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxuserrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
sigvalidclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
tstin_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
tx8b10bbypass_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
tx8b10ben_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txbufdiffctrl_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txcominit_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txcomsas_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txcomwake_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txctrl0_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
txctrl1_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
txctrl2_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
txdata_in : in STD_LOGIC_VECTOR ( 127 downto 0 );
txdataextendrsvd_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
txdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdccreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdeemph_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
txdetectrx_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdiffctrl_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
txdiffpd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdlybypass_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdlyen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdlyhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdlyovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdlysreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txdlyupdown_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txelecidle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txelforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
txinhibit_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txlatclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txlfpstreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txlfpsu2lpexit_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txlfpsu3wake_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
txmargin_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
txmuxdcdexhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txmuxdcdorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txoneszeros_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txoutclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
txpcsreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
txpdelecidlemode_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txphalign_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txphalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txphdlypd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txphdlyreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txphdlytstclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txphinit_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txphovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpippmen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpippmovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpippmpd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpippmsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpippmstepsize_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
txpisopd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpllclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
txpmareset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
txpostcursorinv_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txprbsforceerr_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txprbssel_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
txprecursorinv_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txprogdivreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txqpibiasen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txqpistrongpdown_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txqpiweakpup_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txrate_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
txratemode_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
txswing_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txsyncallin_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txsyncin_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txsyncmode_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txsysclksel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
txuserrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
bufgtce_out : out STD_LOGIC_VECTOR ( 0 to 0 );
bufgtcemask_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
bufgtdiv_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
bufgtreset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
bufgtrstmask_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
cpllfbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
cpllrefclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
dmonitorout_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
dmonitoroutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
drprdy_out : out STD_LOGIC_VECTOR ( 0 to 0 );
eyescandataerror_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtrefclkmonitor_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pcierategen3_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pcierateidle_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pcierateqpllpd_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
pcierateqpllreset_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
pciesynctxsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pcieusergen3rdy_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pcieuserphystatusrst_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pcieuserratestart_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pcsrsvdout_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
phystatus_out : out STD_LOGIC_VECTOR ( 0 to 0 );
pinrsrvdas_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
powerpresent_out : out STD_LOGIC_VECTOR ( 0 to 0 );
resetexception_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxbyterealign_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxcdrphdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxchanbondseq_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxchanisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxchanrealign_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxchbondo_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
rxckcaldone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxcominitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxcommadet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxcomsasdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxcomwakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxctrl0_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
rxctrl1_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
rxctrl2_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
rxctrl3_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
rxdata_out : out STD_LOGIC_VECTOR ( 127 downto 0 );
rxdataextendrsvd_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxdlysresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxelecidle_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxlfpstresetdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxlfpsu2lpexitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxlfpsu3wakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxmonitorout_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
rxosintdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxosintstarted_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxosintstrobedone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxosintstrobestarted_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxoutclkfabric_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxphaligndone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxphalignerr_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxprbserr_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxprbslocked_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxqpisenn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxqpisenp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxratedone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxrecclkout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxsliderdy_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxslipdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxslipoutclkrdy_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxslippmardy_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
rxsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxsyncout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxvalid_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
txcomfinish_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txdccdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txdlysresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txoutclkfabric_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txoutclkpcs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txphaligndone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txphinitdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txqpisenn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txqpisenp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txratedone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txsyncdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txsyncout_out : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_CHANNEL_ENABLE : string;
attribute C_CHANNEL_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
attribute C_COMMON_SCALING_FACTOR : integer;
attribute C_COMMON_SCALING_FACTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_CPLL_VCO_FREQUENCY : string;
attribute C_CPLL_VCO_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "2578.125000";
attribute C_ENABLE_COMMON_USRCLK : integer;
attribute C_ENABLE_COMMON_USRCLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_FORCE_COMMONS : integer;
attribute C_FORCE_COMMONS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_FREERUN_FREQUENCY : string;
attribute C_FREERUN_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "125.000000";
attribute C_GT_REV : integer;
attribute C_GT_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 67;
attribute C_GT_TYPE : integer;
attribute C_GT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 3;
attribute C_INCLUDE_CPLL_CAL : integer;
attribute C_INCLUDE_CPLL_CAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 2;
attribute C_LOCATE_COMMON : integer;
attribute C_LOCATE_COMMON of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer;
attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 2;
attribute C_LOCATE_RESET_CONTROLLER : integer;
attribute C_LOCATE_RESET_CONTROLLER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer;
attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_LOCATE_RX_USER_CLOCKING : integer;
attribute C_LOCATE_RX_USER_CLOCKING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer;
attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_LOCATE_TX_USER_CLOCKING : integer;
attribute C_LOCATE_TX_USER_CLOCKING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer;
attribute C_LOCATE_USER_DATA_WIDTH_SIZING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_PCIE_CORECLK_FREQ : integer;
attribute C_PCIE_CORECLK_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 250;
attribute C_PCIE_ENABLE : integer;
attribute C_PCIE_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer;
attribute C_RESET_CONTROLLER_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RESET_SEQUENCE_INTERVAL : integer;
attribute C_RESET_SEQUENCE_INTERVAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_BUFFBYPASS_MODE : integer;
attribute C_RX_BUFFBYPASS_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_BUFFER_MODE : integer;
attribute C_RX_BUFFER_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_CB_DISP : string;
attribute C_RX_CB_DISP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "8'b00000000";
attribute C_RX_CB_K : string;
attribute C_RX_CB_K of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "8'b00000000";
attribute C_RX_CB_LEN_SEQ : integer;
attribute C_RX_CB_LEN_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_CB_MAX_LEVEL : integer;
attribute C_RX_CB_MAX_LEVEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_CB_NUM_SEQ : integer;
attribute C_RX_CB_NUM_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_CB_VAL : string;
attribute C_RX_CB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_RX_CC_DISP : string;
attribute C_RX_CC_DISP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "8'b00000000";
attribute C_RX_CC_ENABLE : integer;
attribute C_RX_CC_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_CC_K : string;
attribute C_RX_CC_K of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "8'b00000000";
attribute C_RX_CC_LEN_SEQ : integer;
attribute C_RX_CC_LEN_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_CC_NUM_SEQ : integer;
attribute C_RX_CC_NUM_SEQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_CC_PERIODICITY : integer;
attribute C_RX_CC_PERIODICITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 5000;
attribute C_RX_CC_VAL : string;
attribute C_RX_CC_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_RX_COMMA_M_ENABLE : integer;
attribute C_RX_COMMA_M_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_COMMA_M_VAL : string;
attribute C_RX_COMMA_M_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "10'b1010000011";
attribute C_RX_COMMA_P_ENABLE : integer;
attribute C_RX_COMMA_P_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_COMMA_P_VAL : string;
attribute C_RX_COMMA_P_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "10'b0101111100";
attribute C_RX_DATA_DECODING : integer;
attribute C_RX_DATA_DECODING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 4;
attribute C_RX_ENABLE : integer;
attribute C_RX_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_INT_DATA_WIDTH : integer;
attribute C_RX_INT_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 64;
attribute C_RX_LINE_RATE : string;
attribute C_RX_LINE_RATE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "25.781250";
attribute C_RX_MASTER_CHANNEL_IDX : integer;
attribute C_RX_MASTER_CHANNEL_IDX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 4;
attribute C_RX_OUTCLK_BUFG_GT_DIV : integer;
attribute C_RX_OUTCLK_BUFG_GT_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_OUTCLK_FREQUENCY : string;
attribute C_RX_OUTCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "390.625000";
attribute C_RX_OUTCLK_SOURCE : integer;
attribute C_RX_OUTCLK_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 4;
attribute C_RX_PLL_TYPE : integer;
attribute C_RX_PLL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_RECCLK_OUTPUT : string;
attribute C_RX_RECCLK_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_RX_REFCLK_FREQUENCY : string;
attribute C_RX_REFCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "156.250000";
attribute C_RX_SLIDE_MODE : integer;
attribute C_RX_SLIDE_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_USER_CLOCKING_CONTENTS : integer;
attribute C_RX_USER_CLOCKING_CONTENTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer;
attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_RX_USER_CLOCKING_SOURCE : integer;
attribute C_RX_USER_CLOCKING_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_RX_USER_DATA_WIDTH : integer;
attribute C_RX_USER_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 64;
attribute C_RX_USRCLK2_FREQUENCY : string;
attribute C_RX_USRCLK2_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "390.625000";
attribute C_RX_USRCLK_FREQUENCY : string;
attribute C_RX_USRCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "390.625000";
attribute C_SECONDARY_QPLL_ENABLE : integer;
attribute C_SECONDARY_QPLL_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string;
attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "257.812500";
attribute C_SIM_CPLL_CAL_BYPASS : integer;
attribute C_SIM_CPLL_CAL_BYPASS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TOTAL_NUM_CHANNELS : integer;
attribute C_TOTAL_NUM_CHANNELS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TOTAL_NUM_COMMONS : integer;
attribute C_TOTAL_NUM_COMMONS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer;
attribute C_TOTAL_NUM_COMMONS_EXAMPLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TXPROGDIV_FREQ_ENABLE : integer;
attribute C_TXPROGDIV_FREQ_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TXPROGDIV_FREQ_SOURCE : integer;
attribute C_TXPROGDIV_FREQ_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TXPROGDIV_FREQ_VAL : string;
attribute C_TXPROGDIV_FREQ_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "390.625000";
attribute C_TX_BUFFBYPASS_MODE : integer;
attribute C_TX_BUFFBYPASS_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TX_BUFFER_MODE : integer;
attribute C_TX_BUFFER_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TX_DATA_ENCODING : integer;
attribute C_TX_DATA_ENCODING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 4;
attribute C_TX_ENABLE : integer;
attribute C_TX_ENABLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TX_INT_DATA_WIDTH : integer;
attribute C_TX_INT_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 64;
attribute C_TX_LINE_RATE : string;
attribute C_TX_LINE_RATE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "25.781250";
attribute C_TX_MASTER_CHANNEL_IDX : integer;
attribute C_TX_MASTER_CHANNEL_IDX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 4;
attribute C_TX_OUTCLK_BUFG_GT_DIV : integer;
attribute C_TX_OUTCLK_BUFG_GT_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TX_OUTCLK_FREQUENCY : string;
attribute C_TX_OUTCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "390.625000";
attribute C_TX_OUTCLK_SOURCE : integer;
attribute C_TX_OUTCLK_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 4;
attribute C_TX_PLL_TYPE : integer;
attribute C_TX_PLL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TX_REFCLK_FREQUENCY : string;
attribute C_TX_REFCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "156.250000";
attribute C_TX_USER_CLOCKING_CONTENTS : integer;
attribute C_TX_USER_CLOCKING_CONTENTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer;
attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
attribute C_TX_USER_CLOCKING_SOURCE : integer;
attribute C_TX_USER_CLOCKING_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 0;
attribute C_TX_USER_DATA_WIDTH : integer;
attribute C_TX_USER_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 64;
attribute C_TX_USRCLK2_FREQUENCY : string;
attribute C_TX_USRCLK2_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "390.625000";
attribute C_TX_USRCLK_FREQUENCY : string;
attribute C_TX_USRCLK_FREQUENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is "390.625000";
attribute C_USER_GTPOWERGOOD_DELAY_EN : integer;
attribute C_USER_GTPOWERGOOD_DELAY_EN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top is
signal \<const0>\ : STD_LOGIC;
signal \^gtwiz_userclk_rx_usrclk2_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^gtwiz_userclk_tx_usrclk2_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
bufgtce_out(0) <= \<const0>\;
bufgtcemask_out(2) <= \<const0>\;
bufgtcemask_out(1) <= \<const0>\;
bufgtcemask_out(0) <= \<const0>\;
bufgtdiv_out(8) <= \<const0>\;
bufgtdiv_out(7) <= \<const0>\;
bufgtdiv_out(6) <= \<const0>\;
bufgtdiv_out(5) <= \<const0>\;
bufgtdiv_out(4) <= \<const0>\;
bufgtdiv_out(3) <= \<const0>\;
bufgtdiv_out(2) <= \<const0>\;
bufgtdiv_out(1) <= \<const0>\;
bufgtdiv_out(0) <= \<const0>\;
bufgtreset_out(0) <= \<const0>\;
bufgtrstmask_out(2) <= \<const0>\;
bufgtrstmask_out(1) <= \<const0>\;
bufgtrstmask_out(0) <= \<const0>\;
cpllfbclklost_out(0) <= \<const0>\;
cplllock_out(0) <= \<const0>\;
cpllrefclklost_out(0) <= \<const0>\;
dmonitorout_out(15) <= \<const0>\;
dmonitorout_out(14) <= \<const0>\;
dmonitorout_out(13) <= \<const0>\;
dmonitorout_out(12) <= \<const0>\;
dmonitorout_out(11) <= \<const0>\;
dmonitorout_out(10) <= \<const0>\;
dmonitorout_out(9) <= \<const0>\;
dmonitorout_out(8) <= \<const0>\;
dmonitorout_out(7) <= \<const0>\;
dmonitorout_out(6) <= \<const0>\;
dmonitorout_out(5) <= \<const0>\;
dmonitorout_out(4) <= \<const0>\;
dmonitorout_out(3) <= \<const0>\;
dmonitorout_out(2) <= \<const0>\;
dmonitorout_out(1) <= \<const0>\;
dmonitorout_out(0) <= \<const0>\;
dmonitoroutclk_out(0) <= \<const0>\;
drpdo_common_out(15) <= \<const0>\;
drpdo_common_out(14) <= \<const0>\;
drpdo_common_out(13) <= \<const0>\;
drpdo_common_out(12) <= \<const0>\;
drpdo_common_out(11) <= \<const0>\;
drpdo_common_out(10) <= \<const0>\;
drpdo_common_out(9) <= \<const0>\;
drpdo_common_out(8) <= \<const0>\;
drpdo_common_out(7) <= \<const0>\;
drpdo_common_out(6) <= \<const0>\;
drpdo_common_out(5) <= \<const0>\;
drpdo_common_out(4) <= \<const0>\;
drpdo_common_out(3) <= \<const0>\;
drpdo_common_out(2) <= \<const0>\;
drpdo_common_out(1) <= \<const0>\;
drpdo_common_out(0) <= \<const0>\;
drpdo_out(15) <= \<const0>\;
drpdo_out(14) <= \<const0>\;
drpdo_out(13) <= \<const0>\;
drpdo_out(12) <= \<const0>\;
drpdo_out(11) <= \<const0>\;
drpdo_out(10) <= \<const0>\;
drpdo_out(9) <= \<const0>\;
drpdo_out(8) <= \<const0>\;
drpdo_out(7) <= \<const0>\;
drpdo_out(6) <= \<const0>\;
drpdo_out(5) <= \<const0>\;
drpdo_out(4) <= \<const0>\;
drpdo_out(3) <= \<const0>\;
drpdo_out(2) <= \<const0>\;
drpdo_out(1) <= \<const0>\;
drpdo_out(0) <= \<const0>\;
drprdy_common_out(0) <= \<const0>\;
drprdy_out(0) <= \<const0>\;
eyescandataerror_out(0) <= \<const0>\;
gthtxn_out(0) <= \<const0>\;
gthtxp_out(0) <= \<const0>\;
gtrefclkmonitor_out(0) <= \<const0>\;
gtwiz_buffbypass_rx_done_out(0) <= \<const0>\;
gtwiz_buffbypass_rx_error_out(0) <= \<const0>\;
gtwiz_buffbypass_tx_done_out(0) <= \<const0>\;
gtwiz_buffbypass_tx_error_out(0) <= \<const0>\;
gtwiz_reset_qpll1reset_out(0) <= \<const0>\;
gtwiz_userclk_rx_usrclk2_out(0) <= \^gtwiz_userclk_rx_usrclk2_out\(0);
gtwiz_userclk_rx_usrclk_out(0) <= \^gtwiz_userclk_rx_usrclk2_out\(0);
gtwiz_userclk_tx_usrclk2_out(0) <= \^gtwiz_userclk_tx_usrclk2_out\(0);
gtwiz_userclk_tx_usrclk_out(0) <= \^gtwiz_userclk_tx_usrclk2_out\(0);
pcierategen3_out(0) <= \<const0>\;
pcierateidle_out(0) <= \<const0>\;
pcierateqpllpd_out(1) <= \<const0>\;
pcierateqpllpd_out(0) <= \<const0>\;
pcierateqpllreset_out(1) <= \<const0>\;
pcierateqpllreset_out(0) <= \<const0>\;
pciesynctxsyncdone_out(0) <= \<const0>\;
pcieusergen3rdy_out(0) <= \<const0>\;
pcieuserphystatusrst_out(0) <= \<const0>\;
pcieuserratestart_out(0) <= \<const0>\;
pcsrsvdout_out(15) <= \<const0>\;
pcsrsvdout_out(14) <= \<const0>\;
pcsrsvdout_out(13) <= \<const0>\;
pcsrsvdout_out(12) <= \<const0>\;
pcsrsvdout_out(11) <= \<const0>\;
pcsrsvdout_out(10) <= \<const0>\;
pcsrsvdout_out(9) <= \<const0>\;
pcsrsvdout_out(8) <= \<const0>\;
pcsrsvdout_out(7) <= \<const0>\;
pcsrsvdout_out(6) <= \<const0>\;
pcsrsvdout_out(5) <= \<const0>\;
pcsrsvdout_out(4) <= \<const0>\;
pcsrsvdout_out(3) <= \<const0>\;
pcsrsvdout_out(2) <= \<const0>\;
pcsrsvdout_out(1) <= \<const0>\;
pcsrsvdout_out(0) <= \<const0>\;
phystatus_out(0) <= \<const0>\;
pinrsrvdas_out(15) <= \<const0>\;
pinrsrvdas_out(14) <= \<const0>\;
pinrsrvdas_out(13) <= \<const0>\;
pinrsrvdas_out(12) <= \<const0>\;
pinrsrvdas_out(11) <= \<const0>\;
pinrsrvdas_out(10) <= \<const0>\;
pinrsrvdas_out(9) <= \<const0>\;
pinrsrvdas_out(8) <= \<const0>\;
pinrsrvdas_out(7) <= \<const0>\;
pinrsrvdas_out(6) <= \<const0>\;
pinrsrvdas_out(5) <= \<const0>\;
pinrsrvdas_out(4) <= \<const0>\;
pinrsrvdas_out(3) <= \<const0>\;
pinrsrvdas_out(2) <= \<const0>\;
pinrsrvdas_out(1) <= \<const0>\;
pinrsrvdas_out(0) <= \<const0>\;
pmarsvdout0_out(7) <= \<const0>\;
pmarsvdout0_out(6) <= \<const0>\;
pmarsvdout0_out(5) <= \<const0>\;
pmarsvdout0_out(4) <= \<const0>\;
pmarsvdout0_out(3) <= \<const0>\;
pmarsvdout0_out(2) <= \<const0>\;
pmarsvdout0_out(1) <= \<const0>\;
pmarsvdout0_out(0) <= \<const0>\;
pmarsvdout1_out(7) <= \<const0>\;
pmarsvdout1_out(6) <= \<const0>\;
pmarsvdout1_out(5) <= \<const0>\;
pmarsvdout1_out(4) <= \<const0>\;
pmarsvdout1_out(3) <= \<const0>\;
pmarsvdout1_out(2) <= \<const0>\;
pmarsvdout1_out(1) <= \<const0>\;
pmarsvdout1_out(0) <= \<const0>\;
powerpresent_out(0) <= \<const0>\;
qpll0fbclklost_out(0) <= \<const0>\;
qpll0lock_out(0) <= \<const0>\;
qpll0outclk_out(0) <= \<const0>\;
qpll0outrefclk_out(0) <= \<const0>\;
qpll0refclklost_out(0) <= \<const0>\;
qpll1fbclklost_out(0) <= \<const0>\;
qpll1lock_out(0) <= \<const0>\;
qpll1outclk_out(0) <= \<const0>\;
qpll1outrefclk_out(0) <= \<const0>\;
qpll1refclklost_out(0) <= \<const0>\;
qplldmonitor0_out(7) <= \<const0>\;
qplldmonitor0_out(6) <= \<const0>\;
qplldmonitor0_out(5) <= \<const0>\;
qplldmonitor0_out(4) <= \<const0>\;
qplldmonitor0_out(3) <= \<const0>\;
qplldmonitor0_out(2) <= \<const0>\;
qplldmonitor0_out(1) <= \<const0>\;
qplldmonitor0_out(0) <= \<const0>\;
qplldmonitor1_out(7) <= \<const0>\;
qplldmonitor1_out(6) <= \<const0>\;
qplldmonitor1_out(5) <= \<const0>\;
qplldmonitor1_out(4) <= \<const0>\;
qplldmonitor1_out(3) <= \<const0>\;
qplldmonitor1_out(2) <= \<const0>\;
qplldmonitor1_out(1) <= \<const0>\;
qplldmonitor1_out(0) <= \<const0>\;
refclkoutmonitor0_out(0) <= \<const0>\;
refclkoutmonitor1_out(0) <= \<const0>\;
resetexception_out(0) <= \<const0>\;
rxbufstatus_out(2) <= \<const0>\;
rxbufstatus_out(1) <= \<const0>\;
rxbufstatus_out(0) <= \<const0>\;
rxbyteisaligned_out(0) <= \<const0>\;
rxbyterealign_out(0) <= \<const0>\;
rxcdrlock_out(0) <= \<const0>\;
rxcdrphdone_out(0) <= \<const0>\;
rxchanbondseq_out(0) <= \<const0>\;
rxchanisaligned_out(0) <= \<const0>\;
rxchanrealign_out(0) <= \<const0>\;
rxchbondo_out(4) <= \<const0>\;
rxchbondo_out(3) <= \<const0>\;
rxchbondo_out(2) <= \<const0>\;
rxchbondo_out(1) <= \<const0>\;
rxchbondo_out(0) <= \<const0>\;
rxckcaldone_out(0) <= \<const0>\;
rxclkcorcnt_out(1) <= \<const0>\;
rxclkcorcnt_out(0) <= \<const0>\;
rxcominitdet_out(0) <= \<const0>\;
rxcommadet_out(0) <= \<const0>\;
rxcomsasdet_out(0) <= \<const0>\;
rxcomwakedet_out(0) <= \<const0>\;
rxctrl0_out(15) <= \<const0>\;
rxctrl0_out(14) <= \<const0>\;
rxctrl0_out(13) <= \<const0>\;
rxctrl0_out(12) <= \<const0>\;
rxctrl0_out(11) <= \<const0>\;
rxctrl0_out(10) <= \<const0>\;
rxctrl0_out(9) <= \<const0>\;
rxctrl0_out(8) <= \<const0>\;
rxctrl0_out(7) <= \<const0>\;
rxctrl0_out(6) <= \<const0>\;
rxctrl0_out(5) <= \<const0>\;
rxctrl0_out(4) <= \<const0>\;
rxctrl0_out(3) <= \<const0>\;
rxctrl0_out(2) <= \<const0>\;
rxctrl0_out(1) <= \<const0>\;
rxctrl0_out(0) <= \<const0>\;
rxctrl1_out(15) <= \<const0>\;
rxctrl1_out(14) <= \<const0>\;
rxctrl1_out(13) <= \<const0>\;
rxctrl1_out(12) <= \<const0>\;
rxctrl1_out(11) <= \<const0>\;
rxctrl1_out(10) <= \<const0>\;
rxctrl1_out(9) <= \<const0>\;
rxctrl1_out(8) <= \<const0>\;
rxctrl1_out(7) <= \<const0>\;
rxctrl1_out(6) <= \<const0>\;
rxctrl1_out(5) <= \<const0>\;
rxctrl1_out(4) <= \<const0>\;
rxctrl1_out(3) <= \<const0>\;
rxctrl1_out(2) <= \<const0>\;
rxctrl1_out(1) <= \<const0>\;
rxctrl1_out(0) <= \<const0>\;
rxctrl2_out(7) <= \<const0>\;
rxctrl2_out(6) <= \<const0>\;
rxctrl2_out(5) <= \<const0>\;
rxctrl2_out(4) <= \<const0>\;
rxctrl2_out(3) <= \<const0>\;
rxctrl2_out(2) <= \<const0>\;
rxctrl2_out(1) <= \<const0>\;
rxctrl2_out(0) <= \<const0>\;
rxctrl3_out(7) <= \<const0>\;
rxctrl3_out(6) <= \<const0>\;
rxctrl3_out(5) <= \<const0>\;
rxctrl3_out(4) <= \<const0>\;
rxctrl3_out(3) <= \<const0>\;
rxctrl3_out(2) <= \<const0>\;
rxctrl3_out(1) <= \<const0>\;
rxctrl3_out(0) <= \<const0>\;
rxdata_out(127) <= \<const0>\;
rxdata_out(126) <= \<const0>\;
rxdata_out(125) <= \<const0>\;
rxdata_out(124) <= \<const0>\;
rxdata_out(123) <= \<const0>\;
rxdata_out(122) <= \<const0>\;
rxdata_out(121) <= \<const0>\;
rxdata_out(120) <= \<const0>\;
rxdata_out(119) <= \<const0>\;
rxdata_out(118) <= \<const0>\;
rxdata_out(117) <= \<const0>\;
rxdata_out(116) <= \<const0>\;
rxdata_out(115) <= \<const0>\;
rxdata_out(114) <= \<const0>\;
rxdata_out(113) <= \<const0>\;
rxdata_out(112) <= \<const0>\;
rxdata_out(111) <= \<const0>\;
rxdata_out(110) <= \<const0>\;
rxdata_out(109) <= \<const0>\;
rxdata_out(108) <= \<const0>\;
rxdata_out(107) <= \<const0>\;
rxdata_out(106) <= \<const0>\;
rxdata_out(105) <= \<const0>\;
rxdata_out(104) <= \<const0>\;
rxdata_out(103) <= \<const0>\;
rxdata_out(102) <= \<const0>\;
rxdata_out(101) <= \<const0>\;
rxdata_out(100) <= \<const0>\;
rxdata_out(99) <= \<const0>\;
rxdata_out(98) <= \<const0>\;
rxdata_out(97) <= \<const0>\;
rxdata_out(96) <= \<const0>\;
rxdata_out(95) <= \<const0>\;
rxdata_out(94) <= \<const0>\;
rxdata_out(93) <= \<const0>\;
rxdata_out(92) <= \<const0>\;
rxdata_out(91) <= \<const0>\;
rxdata_out(90) <= \<const0>\;
rxdata_out(89) <= \<const0>\;
rxdata_out(88) <= \<const0>\;
rxdata_out(87) <= \<const0>\;
rxdata_out(86) <= \<const0>\;
rxdata_out(85) <= \<const0>\;
rxdata_out(84) <= \<const0>\;
rxdata_out(83) <= \<const0>\;
rxdata_out(82) <= \<const0>\;
rxdata_out(81) <= \<const0>\;
rxdata_out(80) <= \<const0>\;
rxdata_out(79) <= \<const0>\;
rxdata_out(78) <= \<const0>\;
rxdata_out(77) <= \<const0>\;
rxdata_out(76) <= \<const0>\;
rxdata_out(75) <= \<const0>\;
rxdata_out(74) <= \<const0>\;
rxdata_out(73) <= \<const0>\;
rxdata_out(72) <= \<const0>\;
rxdata_out(71) <= \<const0>\;
rxdata_out(70) <= \<const0>\;
rxdata_out(69) <= \<const0>\;
rxdata_out(68) <= \<const0>\;
rxdata_out(67) <= \<const0>\;
rxdata_out(66) <= \<const0>\;
rxdata_out(65) <= \<const0>\;
rxdata_out(64) <= \<const0>\;
rxdata_out(63) <= \<const0>\;
rxdata_out(62) <= \<const0>\;
rxdata_out(61) <= \<const0>\;
rxdata_out(60) <= \<const0>\;
rxdata_out(59) <= \<const0>\;
rxdata_out(58) <= \<const0>\;
rxdata_out(57) <= \<const0>\;
rxdata_out(56) <= \<const0>\;
rxdata_out(55) <= \<const0>\;
rxdata_out(54) <= \<const0>\;
rxdata_out(53) <= \<const0>\;
rxdata_out(52) <= \<const0>\;
rxdata_out(51) <= \<const0>\;
rxdata_out(50) <= \<const0>\;
rxdata_out(49) <= \<const0>\;
rxdata_out(48) <= \<const0>\;
rxdata_out(47) <= \<const0>\;
rxdata_out(46) <= \<const0>\;
rxdata_out(45) <= \<const0>\;
rxdata_out(44) <= \<const0>\;
rxdata_out(43) <= \<const0>\;
rxdata_out(42) <= \<const0>\;
rxdata_out(41) <= \<const0>\;
rxdata_out(40) <= \<const0>\;
rxdata_out(39) <= \<const0>\;
rxdata_out(38) <= \<const0>\;
rxdata_out(37) <= \<const0>\;
rxdata_out(36) <= \<const0>\;
rxdata_out(35) <= \<const0>\;
rxdata_out(34) <= \<const0>\;
rxdata_out(33) <= \<const0>\;
rxdata_out(32) <= \<const0>\;
rxdata_out(31) <= \<const0>\;
rxdata_out(30) <= \<const0>\;
rxdata_out(29) <= \<const0>\;
rxdata_out(28) <= \<const0>\;
rxdata_out(27) <= \<const0>\;
rxdata_out(26) <= \<const0>\;
rxdata_out(25) <= \<const0>\;
rxdata_out(24) <= \<const0>\;
rxdata_out(23) <= \<const0>\;
rxdata_out(22) <= \<const0>\;
rxdata_out(21) <= \<const0>\;
rxdata_out(20) <= \<const0>\;
rxdata_out(19) <= \<const0>\;
rxdata_out(18) <= \<const0>\;
rxdata_out(17) <= \<const0>\;
rxdata_out(16) <= \<const0>\;
rxdata_out(15) <= \<const0>\;
rxdata_out(14) <= \<const0>\;
rxdata_out(13) <= \<const0>\;
rxdata_out(12) <= \<const0>\;
rxdata_out(11) <= \<const0>\;
rxdata_out(10) <= \<const0>\;
rxdata_out(9) <= \<const0>\;
rxdata_out(8) <= \<const0>\;
rxdata_out(7) <= \<const0>\;
rxdata_out(6) <= \<const0>\;
rxdata_out(5) <= \<const0>\;
rxdata_out(4) <= \<const0>\;
rxdata_out(3) <= \<const0>\;
rxdata_out(2) <= \<const0>\;
rxdata_out(1) <= \<const0>\;
rxdata_out(0) <= \<const0>\;
rxdataextendrsvd_out(7) <= \<const0>\;
rxdataextendrsvd_out(6) <= \<const0>\;
rxdataextendrsvd_out(5) <= \<const0>\;
rxdataextendrsvd_out(4) <= \<const0>\;
rxdataextendrsvd_out(3) <= \<const0>\;
rxdataextendrsvd_out(2) <= \<const0>\;
rxdataextendrsvd_out(1) <= \<const0>\;
rxdataextendrsvd_out(0) <= \<const0>\;
rxdlysresetdone_out(0) <= \<const0>\;
rxelecidle_out(0) <= \<const0>\;
rxlfpstresetdet_out(0) <= \<const0>\;
rxlfpsu2lpexitdet_out(0) <= \<const0>\;
rxlfpsu3wakedet_out(0) <= \<const0>\;
rxmonitorout_out(7) <= \<const0>\;
rxmonitorout_out(6) <= \<const0>\;
rxmonitorout_out(5) <= \<const0>\;
rxmonitorout_out(4) <= \<const0>\;
rxmonitorout_out(3) <= \<const0>\;
rxmonitorout_out(2) <= \<const0>\;
rxmonitorout_out(1) <= \<const0>\;
rxmonitorout_out(0) <= \<const0>\;
rxosintdone_out(0) <= \<const0>\;
rxosintstarted_out(0) <= \<const0>\;
rxosintstrobedone_out(0) <= \<const0>\;
rxosintstrobestarted_out(0) <= \<const0>\;
rxoutclk_out(0) <= \<const0>\;
rxoutclkfabric_out(0) <= \<const0>\;
rxoutclkpcs_out(0) <= \<const0>\;
rxphaligndone_out(0) <= \<const0>\;
rxphalignerr_out(0) <= \<const0>\;
rxprbserr_out(0) <= \<const0>\;
rxprbslocked_out(0) <= \<const0>\;
rxqpisenn_out(0) <= \<const0>\;
rxqpisenp_out(0) <= \<const0>\;
rxratedone_out(0) <= \<const0>\;
rxrecclk0_sel_out(0) <= \<const0>\;
rxrecclk0sel_out(1) <= \<const0>\;
rxrecclk0sel_out(0) <= \<const0>\;
rxrecclk1_sel_out(0) <= \<const0>\;
rxrecclk1sel_out(1) <= \<const0>\;
rxrecclk1sel_out(0) <= \<const0>\;
rxrecclkout_out(0) <= \<const0>\;
rxresetdone_out(0) <= \<const0>\;
rxsliderdy_out(0) <= \<const0>\;
rxslipdone_out(0) <= \<const0>\;
rxslipoutclkrdy_out(0) <= \<const0>\;
rxslippmardy_out(0) <= \<const0>\;
rxstatus_out(2) <= \<const0>\;
rxstatus_out(1) <= \<const0>\;
rxstatus_out(0) <= \<const0>\;
rxsyncdone_out(0) <= \<const0>\;
rxsyncout_out(0) <= \<const0>\;
rxvalid_out(0) <= \<const0>\;
sdm0finalout_out(3) <= \<const0>\;
sdm0finalout_out(2) <= \<const0>\;
sdm0finalout_out(1) <= \<const0>\;
sdm0finalout_out(0) <= \<const0>\;
sdm0testdata_out(14) <= \<const0>\;
sdm0testdata_out(13) <= \<const0>\;
sdm0testdata_out(12) <= \<const0>\;
sdm0testdata_out(11) <= \<const0>\;
sdm0testdata_out(10) <= \<const0>\;
sdm0testdata_out(9) <= \<const0>\;
sdm0testdata_out(8) <= \<const0>\;
sdm0testdata_out(7) <= \<const0>\;
sdm0testdata_out(6) <= \<const0>\;
sdm0testdata_out(5) <= \<const0>\;
sdm0testdata_out(4) <= \<const0>\;
sdm0testdata_out(3) <= \<const0>\;
sdm0testdata_out(2) <= \<const0>\;
sdm0testdata_out(1) <= \<const0>\;
sdm0testdata_out(0) <= \<const0>\;
sdm1finalout_out(3) <= \<const0>\;
sdm1finalout_out(2) <= \<const0>\;
sdm1finalout_out(1) <= \<const0>\;
sdm1finalout_out(0) <= \<const0>\;
sdm1testdata_out(14) <= \<const0>\;
sdm1testdata_out(13) <= \<const0>\;
sdm1testdata_out(12) <= \<const0>\;
sdm1testdata_out(11) <= \<const0>\;
sdm1testdata_out(10) <= \<const0>\;
sdm1testdata_out(9) <= \<const0>\;
sdm1testdata_out(8) <= \<const0>\;
sdm1testdata_out(7) <= \<const0>\;
sdm1testdata_out(6) <= \<const0>\;
sdm1testdata_out(5) <= \<const0>\;
sdm1testdata_out(4) <= \<const0>\;
sdm1testdata_out(3) <= \<const0>\;
sdm1testdata_out(2) <= \<const0>\;
sdm1testdata_out(1) <= \<const0>\;
sdm1testdata_out(0) <= \<const0>\;
tcongpo_out(0) <= \<const0>\;
tconrsvdout0_out(0) <= \<const0>\;
txbufstatus_out(1) <= \<const0>\;
txbufstatus_out(0) <= \<const0>\;
txcomfinish_out(0) <= \<const0>\;
txdccdone_out(0) <= \<const0>\;
txdlysresetdone_out(0) <= \<const0>\;
txoutclk_out(0) <= \<const0>\;
txoutclkfabric_out(0) <= \<const0>\;
txoutclkpcs_out(0) <= \<const0>\;
txphaligndone_out(0) <= \<const0>\;
txphinitdone_out(0) <= \<const0>\;
txqpisenn_out(0) <= \<const0>\;
txqpisenp_out(0) <= \<const0>\;
txratedone_out(0) <= \<const0>\;
txresetdone_out(0) <= \<const0>\;
txsyncdone_out(0) <= \<const0>\;
txsyncout_out(0) <= \<const0>\;
ubdaddr_out(15) <= \<const0>\;
ubdaddr_out(14) <= \<const0>\;
ubdaddr_out(13) <= \<const0>\;
ubdaddr_out(12) <= \<const0>\;
ubdaddr_out(11) <= \<const0>\;
ubdaddr_out(10) <= \<const0>\;
ubdaddr_out(9) <= \<const0>\;
ubdaddr_out(8) <= \<const0>\;
ubdaddr_out(7) <= \<const0>\;
ubdaddr_out(6) <= \<const0>\;
ubdaddr_out(5) <= \<const0>\;
ubdaddr_out(4) <= \<const0>\;
ubdaddr_out(3) <= \<const0>\;
ubdaddr_out(2) <= \<const0>\;
ubdaddr_out(1) <= \<const0>\;
ubdaddr_out(0) <= \<const0>\;
ubden_out(0) <= \<const0>\;
ubdi_out(15) <= \<const0>\;
ubdi_out(14) <= \<const0>\;
ubdi_out(13) <= \<const0>\;
ubdi_out(12) <= \<const0>\;
ubdi_out(11) <= \<const0>\;
ubdi_out(10) <= \<const0>\;
ubdi_out(9) <= \<const0>\;
ubdi_out(8) <= \<const0>\;
ubdi_out(7) <= \<const0>\;
ubdi_out(6) <= \<const0>\;
ubdi_out(5) <= \<const0>\;
ubdi_out(4) <= \<const0>\;
ubdi_out(3) <= \<const0>\;
ubdi_out(2) <= \<const0>\;
ubdi_out(1) <= \<const0>\;
ubdi_out(0) <= \<const0>\;
ubdwe_out(0) <= \<const0>\;
ubmdmtdo_out(0) <= \<const0>\;
ubrsvdout_out(0) <= \<const0>\;
ubtxuart_out(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_gtwizard_gtye4_top.eth_xcvr_gt_channel_gtwizard_gtye4_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_gtye4
port map (
gtpowergood_out(0) => gtpowergood_out(0),
gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_qpll0lock_in(0) => gtwiz_reset_qpll0lock_in(0),
gtwiz_reset_qpll0reset_out(0) => gtwiz_reset_qpll0reset_out(0),
gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
gtwiz_userclk_rx_active_out(0) => gtwiz_userclk_rx_active_out(0),
gtwiz_userclk_rx_reset_in(0) => gtwiz_userclk_rx_reset_in(0),
gtwiz_userclk_rx_srcclk_out(0) => gtwiz_userclk_rx_srcclk_out(0),
gtwiz_userclk_rx_usrclk2_out(0) => \^gtwiz_userclk_rx_usrclk2_out\(0),
gtwiz_userclk_tx_active_out(0) => gtwiz_userclk_tx_active_out(0),
gtwiz_userclk_tx_reset_in(0) => gtwiz_userclk_tx_reset_in(0),
gtwiz_userclk_tx_srcclk_out(0) => gtwiz_userclk_tx_srcclk_out(0),
gtwiz_userclk_tx_usrclk2_out(0) => \^gtwiz_userclk_tx_usrclk2_out\(0),
gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0),
gtyrxn_in(0) => gtyrxn_in(0),
gtyrxp_in(0) => gtyrxp_in(0),
gtytxn_out(0) => gtytxn_out(0),
gtytxp_out(0) => gtytxp_out(0),
qpll0clk_in(0) => qpll0clk_in(0),
qpll0refclk_in(0) => qpll0refclk_in(0),
qpll1clk_in(0) => qpll1clk_in(0),
qpll1refclk_in(0) => qpll1refclk_in(0),
rxdatavalid_out(1 downto 0) => rxdatavalid_out(1 downto 0),
rxgearboxslip_in(0) => rxgearboxslip_in(0),
rxheader_out(5 downto 0) => rxheader_out(5 downto 0),
rxheadervalid_out(1 downto 0) => rxheadervalid_out(1 downto 0),
rxpmaresetdone_out(0) => rxpmaresetdone_out(0),
rxprgdivresetdone_out(0) => rxprgdivresetdone_out(0),
rxstartofseq_out(1 downto 0) => rxstartofseq_out(1 downto 0),
txheader_in(5 downto 0) => txheader_in(5 downto 0),
txpmaresetdone_out(0) => txpmaresetdone_out(0),
txprgdivresetdone_out(0) => txprgdivresetdone_out(0),
txsequence_in(6 downto 0) => txsequence_in(6 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll0refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1clk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
qpll1refclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rxgearboxslip_in : in STD_LOGIC_VECTOR ( 0 to 0 );
txheader_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
txsequence_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxdatavalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxheader_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
rxheadervalid_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
rxstartofseq_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "eth_xcvr_gt_channel,eth_xcvr_gt_channel_gtwizard_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "eth_xcvr_gt_channel_gtwizard_top,Vivado 2021.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_bufgtce_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_bufgtcemask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_bufgtdiv_out_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_inst_bufgtreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_bufgtrstmask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_cpllfbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_cplllock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_cpllrefclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_dmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_dmonitoroutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_drpdo_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_drpdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_drprdy_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_drprdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_eyescandataerror_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gthtxn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gthtxp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gtrefclkmonitor_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pcierategen3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pcierateidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pcierateqpllpd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_pcierateqpllreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_pciesynctxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pcieusergen3rdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pcieuserphystatusrst_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pcieuserratestart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pcsrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_phystatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_pinrsrvdas_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_pmarsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_pmarsvdout1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_powerpresent_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll0fbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll0lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll0outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll0outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll0refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll1fbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll1lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll1outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll1outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qpll1refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_qplldmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_qplldmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_refclkoutmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_refclkoutmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_resetexception_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_rxbyteisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxbyterealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxcdrlock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxcdrphdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxchanbondseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxchanisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxchanrealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxchbondo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_inst_rxckcaldone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxclkcorcnt_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_rxcominitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxcommadet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxcomsasdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxcomwakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxctrl0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_rxctrl1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_rxctrl2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_rxctrl3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_rxdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
signal NLW_inst_rxdataextendrsvd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_rxdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxelecidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxlfpstresetdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_rxosintdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxosintstarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxosintstrobedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxosintstrobestarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxphalignerr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxprbserr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxprbslocked_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxrecclk0_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxrecclk0sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_rxrecclk1_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxrecclk1sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_rxrecclkout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxsliderdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxslipdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxslipoutclkrdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxslippmardy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_rxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_rxvalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sdm0finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_sdm0testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_inst_sdm1finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_sdm1testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_inst_tcongpo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_tconrsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_txcomfinish_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txdccdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txphinitdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_txsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_ubdaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_ubden_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_ubdi_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_ubdwe_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_ubmdmtdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_ubrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_ubtxuart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_CHANNEL_ENABLE : string;
attribute C_CHANNEL_ENABLE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
attribute C_COMMON_SCALING_FACTOR : integer;
attribute C_COMMON_SCALING_FACTOR of inst : label is 1;
attribute C_CPLL_VCO_FREQUENCY : string;
attribute C_CPLL_VCO_FREQUENCY of inst : label is "2578.125000";
attribute C_ENABLE_COMMON_USRCLK : integer;
attribute C_ENABLE_COMMON_USRCLK of inst : label is 0;
attribute C_FORCE_COMMONS : integer;
attribute C_FORCE_COMMONS of inst : label is 0;
attribute C_FREERUN_FREQUENCY : string;
attribute C_FREERUN_FREQUENCY of inst : label is "125.000000";
attribute C_GT_REV : integer;
attribute C_GT_REV of inst : label is 67;
attribute C_GT_TYPE : integer;
attribute C_GT_TYPE of inst : label is 3;
attribute C_INCLUDE_CPLL_CAL : integer;
attribute C_INCLUDE_CPLL_CAL of inst : label is 2;
attribute C_LOCATE_COMMON : integer;
attribute C_LOCATE_COMMON of inst : label is 1;
attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer;
attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of inst : label is 2;
attribute C_LOCATE_RESET_CONTROLLER : integer;
attribute C_LOCATE_RESET_CONTROLLER of inst : label is 0;
attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer;
attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of inst : label is 0;
attribute C_LOCATE_RX_USER_CLOCKING : integer;
attribute C_LOCATE_RX_USER_CLOCKING of inst : label is 0;
attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer;
attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of inst : label is 0;
attribute C_LOCATE_TX_USER_CLOCKING : integer;
attribute C_LOCATE_TX_USER_CLOCKING of inst : label is 0;
attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer;
attribute C_LOCATE_USER_DATA_WIDTH_SIZING of inst : label is 0;
attribute C_PCIE_CORECLK_FREQ : integer;
attribute C_PCIE_CORECLK_FREQ of inst : label is 250;
attribute C_PCIE_ENABLE : integer;
attribute C_PCIE_ENABLE of inst : label is 0;
attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer;
attribute C_RESET_CONTROLLER_INSTANCE_CTRL of inst : label is 0;
attribute C_RESET_SEQUENCE_INTERVAL : integer;
attribute C_RESET_SEQUENCE_INTERVAL of inst : label is 0;
attribute C_RX_BUFFBYPASS_MODE : integer;
attribute C_RX_BUFFBYPASS_MODE of inst : label is 0;
attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0;
attribute C_RX_BUFFER_MODE : integer;
attribute C_RX_BUFFER_MODE of inst : label is 1;
attribute C_RX_CB_DISP : string;
attribute C_RX_CB_DISP of inst : label is "8'b00000000";
attribute C_RX_CB_K : string;
attribute C_RX_CB_K of inst : label is "8'b00000000";
attribute C_RX_CB_LEN_SEQ : integer;
attribute C_RX_CB_LEN_SEQ of inst : label is 1;
attribute C_RX_CB_MAX_LEVEL : integer;
attribute C_RX_CB_MAX_LEVEL of inst : label is 1;
attribute C_RX_CB_NUM_SEQ : integer;
attribute C_RX_CB_NUM_SEQ of inst : label is 0;
attribute C_RX_CB_VAL : string;
attribute C_RX_CB_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_RX_CC_DISP : string;
attribute C_RX_CC_DISP of inst : label is "8'b00000000";
attribute C_RX_CC_ENABLE : integer;
attribute C_RX_CC_ENABLE of inst : label is 0;
attribute C_RX_CC_K : string;
attribute C_RX_CC_K of inst : label is "8'b00000000";
attribute C_RX_CC_LEN_SEQ : integer;
attribute C_RX_CC_LEN_SEQ of inst : label is 1;
attribute C_RX_CC_NUM_SEQ : integer;
attribute C_RX_CC_NUM_SEQ of inst : label is 0;
attribute C_RX_CC_PERIODICITY : integer;
attribute C_RX_CC_PERIODICITY of inst : label is 5000;
attribute C_RX_CC_VAL : string;
attribute C_RX_CC_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_RX_COMMA_M_ENABLE : integer;
attribute C_RX_COMMA_M_ENABLE of inst : label is 0;
attribute C_RX_COMMA_M_VAL : string;
attribute C_RX_COMMA_M_VAL of inst : label is "10'b1010000011";
attribute C_RX_COMMA_P_ENABLE : integer;
attribute C_RX_COMMA_P_ENABLE of inst : label is 0;
attribute C_RX_COMMA_P_VAL : string;
attribute C_RX_COMMA_P_VAL of inst : label is "10'b0101111100";
attribute C_RX_DATA_DECODING : integer;
attribute C_RX_DATA_DECODING of inst : label is 4;
attribute C_RX_ENABLE : integer;
attribute C_RX_ENABLE of inst : label is 1;
attribute C_RX_INT_DATA_WIDTH : integer;
attribute C_RX_INT_DATA_WIDTH of inst : label is 64;
attribute C_RX_LINE_RATE : string;
attribute C_RX_LINE_RATE of inst : label is "25.781250";
attribute C_RX_MASTER_CHANNEL_IDX : integer;
attribute C_RX_MASTER_CHANNEL_IDX of inst : label is 4;
attribute C_RX_OUTCLK_BUFG_GT_DIV : integer;
attribute C_RX_OUTCLK_BUFG_GT_DIV of inst : label is 1;
attribute C_RX_OUTCLK_FREQUENCY : string;
attribute C_RX_OUTCLK_FREQUENCY of inst : label is "390.625000";
attribute C_RX_OUTCLK_SOURCE : integer;
attribute C_RX_OUTCLK_SOURCE of inst : label is 4;
attribute C_RX_PLL_TYPE : integer;
attribute C_RX_PLL_TYPE of inst : label is 0;
attribute C_RX_RECCLK_OUTPUT : string;
attribute C_RX_RECCLK_OUTPUT of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_RX_REFCLK_FREQUENCY : string;
attribute C_RX_REFCLK_FREQUENCY of inst : label is "156.250000";
attribute C_RX_SLIDE_MODE : integer;
attribute C_RX_SLIDE_MODE of inst : label is 0;
attribute C_RX_USER_CLOCKING_CONTENTS : integer;
attribute C_RX_USER_CLOCKING_CONTENTS of inst : label is 0;
attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer;
attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0;
attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1;
attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1;
attribute C_RX_USER_CLOCKING_SOURCE : integer;
attribute C_RX_USER_CLOCKING_SOURCE of inst : label is 0;
attribute C_RX_USER_DATA_WIDTH : integer;
attribute C_RX_USER_DATA_WIDTH of inst : label is 64;
attribute C_RX_USRCLK2_FREQUENCY : string;
attribute C_RX_USRCLK2_FREQUENCY of inst : label is "390.625000";
attribute C_RX_USRCLK_FREQUENCY : string;
attribute C_RX_USRCLK_FREQUENCY of inst : label is "390.625000";
attribute C_SECONDARY_QPLL_ENABLE : integer;
attribute C_SECONDARY_QPLL_ENABLE of inst : label is 0;
attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string;
attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of inst : label is "257.812500";
attribute C_SIM_CPLL_CAL_BYPASS : integer;
attribute C_SIM_CPLL_CAL_BYPASS of inst : label is 1;
attribute C_TOTAL_NUM_CHANNELS : integer;
attribute C_TOTAL_NUM_CHANNELS of inst : label is 1;
attribute C_TOTAL_NUM_COMMONS : integer;
attribute C_TOTAL_NUM_COMMONS of inst : label is 0;
attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer;
attribute C_TOTAL_NUM_COMMONS_EXAMPLE of inst : label is 1;
attribute C_TXPROGDIV_FREQ_ENABLE : integer;
attribute C_TXPROGDIV_FREQ_ENABLE of inst : label is 0;
attribute C_TXPROGDIV_FREQ_SOURCE : integer;
attribute C_TXPROGDIV_FREQ_SOURCE of inst : label is 0;
attribute C_TXPROGDIV_FREQ_VAL : string;
attribute C_TXPROGDIV_FREQ_VAL of inst : label is "390.625000";
attribute C_TX_BUFFBYPASS_MODE : integer;
attribute C_TX_BUFFBYPASS_MODE of inst : label is 0;
attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0;
attribute C_TX_BUFFER_MODE : integer;
attribute C_TX_BUFFER_MODE of inst : label is 1;
attribute C_TX_DATA_ENCODING : integer;
attribute C_TX_DATA_ENCODING of inst : label is 4;
attribute C_TX_ENABLE : integer;
attribute C_TX_ENABLE of inst : label is 1;
attribute C_TX_INT_DATA_WIDTH : integer;
attribute C_TX_INT_DATA_WIDTH of inst : label is 64;
attribute C_TX_LINE_RATE : string;
attribute C_TX_LINE_RATE of inst : label is "25.781250";
attribute C_TX_MASTER_CHANNEL_IDX : integer;
attribute C_TX_MASTER_CHANNEL_IDX of inst : label is 4;
attribute C_TX_OUTCLK_BUFG_GT_DIV : integer;
attribute C_TX_OUTCLK_BUFG_GT_DIV of inst : label is 1;
attribute C_TX_OUTCLK_FREQUENCY : string;
attribute C_TX_OUTCLK_FREQUENCY of inst : label is "390.625000";
attribute C_TX_OUTCLK_SOURCE : integer;
attribute C_TX_OUTCLK_SOURCE of inst : label is 4;
attribute C_TX_PLL_TYPE : integer;
attribute C_TX_PLL_TYPE of inst : label is 0;
attribute C_TX_REFCLK_FREQUENCY : string;
attribute C_TX_REFCLK_FREQUENCY of inst : label is "156.250000";
attribute C_TX_USER_CLOCKING_CONTENTS : integer;
attribute C_TX_USER_CLOCKING_CONTENTS of inst : label is 0;
attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer;
attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0;
attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1;
attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1;
attribute C_TX_USER_CLOCKING_SOURCE : integer;
attribute C_TX_USER_CLOCKING_SOURCE of inst : label is 0;
attribute C_TX_USER_DATA_WIDTH : integer;
attribute C_TX_USER_DATA_WIDTH of inst : label is 64;
attribute C_TX_USRCLK2_FREQUENCY : string;
attribute C_TX_USRCLK2_FREQUENCY of inst : label is "390.625000";
attribute C_TX_USRCLK_FREQUENCY : string;
attribute C_TX_USRCLK_FREQUENCY of inst : label is "390.625000";
attribute C_USER_GTPOWERGOOD_DELAY_EN : integer;
attribute C_USER_GTPOWERGOOD_DELAY_EN of inst : label is 1;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_eth_xcvr_gt_channel_gtwizard_top
port map (
bgbypassb_in(0) => '1',
bgmonitorenb_in(0) => '1',
bgpdb_in(0) => '1',
bgrcalovrd_in(4 downto 0) => B"10000",
bgrcalovrdenb_in(0) => '1',
bufgtce_out(0) => NLW_inst_bufgtce_out_UNCONNECTED(0),
bufgtcemask_out(2 downto 0) => NLW_inst_bufgtcemask_out_UNCONNECTED(2 downto 0),
bufgtdiv_out(8 downto 0) => NLW_inst_bufgtdiv_out_UNCONNECTED(8 downto 0),
bufgtreset_out(0) => NLW_inst_bufgtreset_out_UNCONNECTED(0),
bufgtrstmask_out(2 downto 0) => NLW_inst_bufgtrstmask_out_UNCONNECTED(2 downto 0),
cdrstepdir_in(0) => '0',
cdrstepsq_in(0) => '0',
cdrstepsx_in(0) => '0',
cfgreset_in(0) => '0',
clkrsvd0_in(0) => '0',
clkrsvd1_in(0) => '0',
cpllfbclklost_out(0) => NLW_inst_cpllfbclklost_out_UNCONNECTED(0),
cpllfreqlock_in(0) => '0',
cplllock_out(0) => NLW_inst_cplllock_out_UNCONNECTED(0),
cplllockdetclk_in(0) => '0',
cplllocken_in(0) => '0',
cpllpd_in(0) => '1',
cpllrefclklost_out(0) => NLW_inst_cpllrefclklost_out_UNCONNECTED(0),
cpllrefclksel_in(2 downto 0) => B"001",
cpllreset_in(0) => '1',
dmonfiforeset_in(0) => '0',
dmonitorclk_in(0) => '0',
dmonitorout_out(15 downto 0) => NLW_inst_dmonitorout_out_UNCONNECTED(15 downto 0),
dmonitoroutclk_out(0) => NLW_inst_dmonitoroutclk_out_UNCONNECTED(0),
drpaddr_common_in(15 downto 0) => B"0000000000000000",
drpaddr_in(9 downto 0) => B"0000000000",
drpclk_common_in(0) => '0',
drpclk_in(0) => '0',
drpdi_common_in(15 downto 0) => B"0000000000000000",
drpdi_in(15 downto 0) => B"0000000000000000",
drpdo_common_out(15 downto 0) => NLW_inst_drpdo_common_out_UNCONNECTED(15 downto 0),
drpdo_out(15 downto 0) => NLW_inst_drpdo_out_UNCONNECTED(15 downto 0),
drpen_common_in(0) => '0',
drpen_in(0) => '0',
drprdy_common_out(0) => NLW_inst_drprdy_common_out_UNCONNECTED(0),
drprdy_out(0) => NLW_inst_drprdy_out_UNCONNECTED(0),
drprst_in(0) => '0',
drpwe_common_in(0) => '0',
drpwe_in(0) => '0',
elpcaldvorwren_in(0) => '0',
elpcalpaorwren_in(0) => '0',
evoddphicaldone_in(0) => '0',
evoddphicalstart_in(0) => '0',
evoddphidrden_in(0) => '0',
evoddphidwren_in(0) => '0',
evoddphixrden_in(0) => '0',
evoddphixwren_in(0) => '0',
eyescandataerror_out(0) => NLW_inst_eyescandataerror_out_UNCONNECTED(0),
eyescanmode_in(0) => '0',
eyescanreset_in(0) => '0',
eyescantrigger_in(0) => '0',
freqos_in(0) => '0',
gtgrefclk0_in(0) => '0',
gtgrefclk1_in(0) => '0',
gtgrefclk_in(0) => '0',
gthrxn_in(0) => '0',
gthrxp_in(0) => '0',
gthtxn_out(0) => NLW_inst_gthtxn_out_UNCONNECTED(0),
gthtxp_out(0) => NLW_inst_gthtxp_out_UNCONNECTED(0),
gtnorthrefclk00_in(0) => '0',
gtnorthrefclk01_in(0) => '0',
gtnorthrefclk0_in(0) => '0',
gtnorthrefclk10_in(0) => '0',
gtnorthrefclk11_in(0) => '0',
gtnorthrefclk1_in(0) => '0',
gtpowergood_out(0) => gtpowergood_out(0),
gtrefclk00_in(0) => '0',
gtrefclk01_in(0) => '0',
gtrefclk0_in(0) => '0',
gtrefclk10_in(0) => '0',
gtrefclk11_in(0) => '0',
gtrefclk1_in(0) => '0',
gtrefclkmonitor_out(0) => NLW_inst_gtrefclkmonitor_out_UNCONNECTED(0),
gtresetsel_in(0) => '0',
gtrsvd_in(15 downto 0) => B"0000000000000000",
gtrxreset_in(0) => '0',
gtrxresetsel_in(0) => '0',
gtsouthrefclk00_in(0) => '0',
gtsouthrefclk01_in(0) => '0',
gtsouthrefclk0_in(0) => '0',
gtsouthrefclk10_in(0) => '0',
gtsouthrefclk11_in(0) => '0',
gtsouthrefclk1_in(0) => '0',
gttxreset_in(0) => '0',
gttxresetsel_in(0) => '0',
gtwiz_buffbypass_rx_done_out(0) => NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED(0),
gtwiz_buffbypass_rx_error_out(0) => NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED(0),
gtwiz_buffbypass_rx_reset_in(0) => '0',
gtwiz_buffbypass_rx_start_user_in(0) => '0',
gtwiz_buffbypass_tx_done_out(0) => NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED(0),
gtwiz_buffbypass_tx_error_out(0) => NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED(0),
gtwiz_buffbypass_tx_reset_in(0) => '0',
gtwiz_buffbypass_tx_start_user_in(0) => '0',
gtwiz_gthe3_cpll_cal_bufg_ce_in(0) => '0',
gtwiz_gthe3_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000",
gtwiz_gthe3_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000",
gtwiz_gthe4_cpll_cal_bufg_ce_in(0) => '0',
gtwiz_gthe4_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000",
gtwiz_gthe4_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000",
gtwiz_gtye4_cpll_cal_bufg_ce_in(0) => '0',
gtwiz_gtye4_cpll_cal_cnt_tol_in(17 downto 0) => B"000000000000000000",
gtwiz_gtye4_cpll_cal_txoutclk_period_in(17 downto 0) => B"000000000000000000",
gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
gtwiz_reset_qpll0lock_in(0) => gtwiz_reset_qpll0lock_in(0),
gtwiz_reset_qpll0reset_out(0) => gtwiz_reset_qpll0reset_out(0),
gtwiz_reset_qpll1lock_in(0) => '0',
gtwiz_reset_qpll1reset_out(0) => NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED(0),
gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
gtwiz_reset_rx_done_in(0) => '0',
gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
gtwiz_reset_tx_done_in(0) => '0',
gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
gtwiz_userclk_rx_active_in(0) => '0',
gtwiz_userclk_rx_active_out(0) => gtwiz_userclk_rx_active_out(0),
gtwiz_userclk_rx_reset_in(0) => gtwiz_userclk_rx_reset_in(0),
gtwiz_userclk_rx_srcclk_out(0) => gtwiz_userclk_rx_srcclk_out(0),
gtwiz_userclk_rx_usrclk2_out(0) => gtwiz_userclk_rx_usrclk2_out(0),
gtwiz_userclk_rx_usrclk_out(0) => gtwiz_userclk_rx_usrclk_out(0),
gtwiz_userclk_tx_active_in(0) => '0',
gtwiz_userclk_tx_active_out(0) => gtwiz_userclk_tx_active_out(0),
gtwiz_userclk_tx_reset_in(0) => gtwiz_userclk_tx_reset_in(0),
gtwiz_userclk_tx_srcclk_out(0) => gtwiz_userclk_tx_srcclk_out(0),
gtwiz_userclk_tx_usrclk2_out(0) => gtwiz_userclk_tx_usrclk2_out(0),
gtwiz_userclk_tx_usrclk_out(0) => gtwiz_userclk_tx_usrclk_out(0),
gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
gtwiz_userdata_tx_in(63 downto 0) => gtwiz_userdata_tx_in(63 downto 0),
gtyrxn_in(0) => gtyrxn_in(0),
gtyrxp_in(0) => gtyrxp_in(0),
gtytxn_out(0) => gtytxn_out(0),
gtytxp_out(0) => gtytxp_out(0),
incpctrl_in(0) => '0',
loopback_in(2 downto 0) => B"000",
looprsvd_in(0) => '0',
lpbkrxtxseren_in(0) => '0',
lpbktxrxseren_in(0) => '0',
pcieeqrxeqadaptdone_in(0) => '0',
pcierategen3_out(0) => NLW_inst_pcierategen3_out_UNCONNECTED(0),
pcierateidle_out(0) => NLW_inst_pcierateidle_out_UNCONNECTED(0),
pcierateqpll0_in(2 downto 0) => B"000",
pcierateqpll1_in(2 downto 0) => B"000",
pcierateqpllpd_out(1 downto 0) => NLW_inst_pcierateqpllpd_out_UNCONNECTED(1 downto 0),
pcierateqpllreset_out(1 downto 0) => NLW_inst_pcierateqpllreset_out_UNCONNECTED(1 downto 0),
pcierstidle_in(0) => '0',
pciersttxsyncstart_in(0) => '0',
pciesynctxsyncdone_out(0) => NLW_inst_pciesynctxsyncdone_out_UNCONNECTED(0),
pcieusergen3rdy_out(0) => NLW_inst_pcieusergen3rdy_out_UNCONNECTED(0),
pcieuserphystatusrst_out(0) => NLW_inst_pcieuserphystatusrst_out_UNCONNECTED(0),
pcieuserratedone_in(0) => '0',
pcieuserratestart_out(0) => NLW_inst_pcieuserratestart_out_UNCONNECTED(0),
pcsrsvdin2_in(0) => '0',
pcsrsvdin_in(15 downto 0) => B"0000000000000000",
pcsrsvdout_out(15 downto 0) => NLW_inst_pcsrsvdout_out_UNCONNECTED(15 downto 0),
phystatus_out(0) => NLW_inst_phystatus_out_UNCONNECTED(0),
pinrsrvdas_out(15 downto 0) => NLW_inst_pinrsrvdas_out_UNCONNECTED(15 downto 0),
pmarsvd0_in(7 downto 0) => B"00000000",
pmarsvd1_in(7 downto 0) => B"00000000",
pmarsvdin_in(0) => '0',
pmarsvdout0_out(7 downto 0) => NLW_inst_pmarsvdout0_out_UNCONNECTED(7 downto 0),
pmarsvdout1_out(7 downto 0) => NLW_inst_pmarsvdout1_out_UNCONNECTED(7 downto 0),
powerpresent_out(0) => NLW_inst_powerpresent_out_UNCONNECTED(0),
qpll0clk_in(0) => qpll0clk_in(0),
qpll0clkrsvd0_in(0) => '0',
qpll0clkrsvd1_in(0) => '0',
qpll0fbclklost_out(0) => NLW_inst_qpll0fbclklost_out_UNCONNECTED(0),
qpll0fbdiv_in(7 downto 0) => B"00000000",
qpll0freqlock_in(0) => '0',
qpll0lock_out(0) => NLW_inst_qpll0lock_out_UNCONNECTED(0),
qpll0lockdetclk_in(0) => '0',
qpll0locken_in(0) => '1',
qpll0outclk_out(0) => NLW_inst_qpll0outclk_out_UNCONNECTED(0),
qpll0outrefclk_out(0) => NLW_inst_qpll0outrefclk_out_UNCONNECTED(0),
qpll0pd_in(0) => '0',
qpll0refclk_in(0) => qpll0refclk_in(0),
qpll0refclklost_out(0) => NLW_inst_qpll0refclklost_out_UNCONNECTED(0),
qpll0refclksel_in(2 downto 0) => B"001",
qpll0reset_in(0) => '0',
qpll1clk_in(0) => qpll1clk_in(0),
qpll1clkrsvd0_in(0) => '0',
qpll1clkrsvd1_in(0) => '0',
qpll1fbclklost_out(0) => NLW_inst_qpll1fbclklost_out_UNCONNECTED(0),
qpll1fbdiv_in(7 downto 0) => B"00000000",
qpll1freqlock_in(0) => '0',
qpll1lock_out(0) => NLW_inst_qpll1lock_out_UNCONNECTED(0),
qpll1lockdetclk_in(0) => '0',
qpll1locken_in(0) => '0',
qpll1outclk_out(0) => NLW_inst_qpll1outclk_out_UNCONNECTED(0),
qpll1outrefclk_out(0) => NLW_inst_qpll1outrefclk_out_UNCONNECTED(0),
qpll1pd_in(0) => '1',
qpll1refclk_in(0) => qpll1refclk_in(0),
qpll1refclklost_out(0) => NLW_inst_qpll1refclklost_out_UNCONNECTED(0),
qpll1refclksel_in(2 downto 0) => B"001",
qpll1reset_in(0) => '1',
qplldmonitor0_out(7 downto 0) => NLW_inst_qplldmonitor0_out_UNCONNECTED(7 downto 0),
qplldmonitor1_out(7 downto 0) => NLW_inst_qplldmonitor1_out_UNCONNECTED(7 downto 0),
qpllrsvd1_in(7 downto 0) => B"00000000",
qpllrsvd2_in(4 downto 0) => B"00000",
qpllrsvd3_in(4 downto 0) => B"00000",
qpllrsvd4_in(7 downto 0) => B"00000000",
rcalenb_in(0) => '1',
refclkoutmonitor0_out(0) => NLW_inst_refclkoutmonitor0_out_UNCONNECTED(0),
refclkoutmonitor1_out(0) => NLW_inst_refclkoutmonitor1_out_UNCONNECTED(0),
resetexception_out(0) => NLW_inst_resetexception_out_UNCONNECTED(0),
resetovrd_in(0) => '0',
rstclkentx_in(0) => '0',
rx8b10ben_in(0) => '0',
rxafecfoken_in(0) => '1',
rxbufreset_in(0) => '0',
rxbufstatus_out(2 downto 0) => NLW_inst_rxbufstatus_out_UNCONNECTED(2 downto 0),
rxbyteisaligned_out(0) => NLW_inst_rxbyteisaligned_out_UNCONNECTED(0),
rxbyterealign_out(0) => NLW_inst_rxbyterealign_out_UNCONNECTED(0),
rxcdrfreqreset_in(0) => '0',
rxcdrhold_in(0) => '0',
rxcdrlock_out(0) => NLW_inst_rxcdrlock_out_UNCONNECTED(0),
rxcdrovrden_in(0) => '0',
rxcdrphdone_out(0) => NLW_inst_rxcdrphdone_out_UNCONNECTED(0),
rxcdrreset_in(0) => '0',
rxcdrresetrsv_in(0) => '0',
rxchanbondseq_out(0) => NLW_inst_rxchanbondseq_out_UNCONNECTED(0),
rxchanisaligned_out(0) => NLW_inst_rxchanisaligned_out_UNCONNECTED(0),
rxchanrealign_out(0) => NLW_inst_rxchanrealign_out_UNCONNECTED(0),
rxchbonden_in(0) => '0',
rxchbondi_in(4 downto 0) => B"00000",
rxchbondlevel_in(2 downto 0) => B"000",
rxchbondmaster_in(0) => '0',
rxchbondo_out(4 downto 0) => NLW_inst_rxchbondo_out_UNCONNECTED(4 downto 0),
rxchbondslave_in(0) => '0',
rxckcaldone_out(0) => NLW_inst_rxckcaldone_out_UNCONNECTED(0),
rxckcalreset_in(0) => '0',
rxckcalstart_in(6 downto 0) => B"0000000",
rxclkcorcnt_out(1 downto 0) => NLW_inst_rxclkcorcnt_out_UNCONNECTED(1 downto 0),
rxcominitdet_out(0) => NLW_inst_rxcominitdet_out_UNCONNECTED(0),
rxcommadet_out(0) => NLW_inst_rxcommadet_out_UNCONNECTED(0),
rxcommadeten_in(0) => '0',
rxcomsasdet_out(0) => NLW_inst_rxcomsasdet_out_UNCONNECTED(0),
rxcomwakedet_out(0) => NLW_inst_rxcomwakedet_out_UNCONNECTED(0),
rxctrl0_out(15 downto 0) => NLW_inst_rxctrl0_out_UNCONNECTED(15 downto 0),
rxctrl1_out(15 downto 0) => NLW_inst_rxctrl1_out_UNCONNECTED(15 downto 0),
rxctrl2_out(7 downto 0) => NLW_inst_rxctrl2_out_UNCONNECTED(7 downto 0),
rxctrl3_out(7 downto 0) => NLW_inst_rxctrl3_out_UNCONNECTED(7 downto 0),
rxdata_out(127 downto 0) => NLW_inst_rxdata_out_UNCONNECTED(127 downto 0),
rxdataextendrsvd_out(7 downto 0) => NLW_inst_rxdataextendrsvd_out_UNCONNECTED(7 downto 0),
rxdatavalid_out(1 downto 0) => rxdatavalid_out(1 downto 0),
rxdccforcestart_in(0) => '0',
rxdfeagcctrl_in(0) => '0',
rxdfeagchold_in(0) => '0',
rxdfeagcovrden_in(0) => '0',
rxdfecfokfcnum_in(3 downto 0) => B"1101",
rxdfecfokfen_in(0) => '0',
rxdfecfokfpulse_in(0) => '0',
rxdfecfokhold_in(0) => '0',
rxdfecfokovren_in(0) => '0',
rxdfekhhold_in(0) => '0',
rxdfekhovrden_in(0) => '0',
rxdfelfhold_in(0) => '0',
rxdfelfovrden_in(0) => '0',
rxdfelpmreset_in(0) => '0',
rxdfetap10hold_in(0) => '0',
rxdfetap10ovrden_in(0) => '0',
rxdfetap11hold_in(0) => '0',
rxdfetap11ovrden_in(0) => '0',
rxdfetap12hold_in(0) => '0',
rxdfetap12ovrden_in(0) => '0',
rxdfetap13hold_in(0) => '0',
rxdfetap13ovrden_in(0) => '0',
rxdfetap14hold_in(0) => '0',
rxdfetap14ovrden_in(0) => '0',
rxdfetap15hold_in(0) => '0',
rxdfetap15ovrden_in(0) => '0',
rxdfetap2hold_in(0) => '0',
rxdfetap2ovrden_in(0) => '0',
rxdfetap3hold_in(0) => '0',
rxdfetap3ovrden_in(0) => '0',
rxdfetap4hold_in(0) => '0',
rxdfetap4ovrden_in(0) => '0',
rxdfetap5hold_in(0) => '0',
rxdfetap5ovrden_in(0) => '0',
rxdfetap6hold_in(0) => '0',
rxdfetap6ovrden_in(0) => '0',
rxdfetap7hold_in(0) => '0',
rxdfetap7ovrden_in(0) => '0',
rxdfetap8hold_in(0) => '0',
rxdfetap8ovrden_in(0) => '0',
rxdfetap9hold_in(0) => '0',
rxdfetap9ovrden_in(0) => '0',
rxdfeuthold_in(0) => '0',
rxdfeutovrden_in(0) => '0',
rxdfevphold_in(0) => '0',
rxdfevpovrden_in(0) => '0',
rxdfevsen_in(0) => '0',
rxdfexyden_in(0) => '1',
rxdlybypass_in(0) => '1',
rxdlyen_in(0) => '0',
rxdlyovrden_in(0) => '0',
rxdlysreset_in(0) => '0',
rxdlysresetdone_out(0) => NLW_inst_rxdlysresetdone_out_UNCONNECTED(0),
rxelecidle_out(0) => NLW_inst_rxelecidle_out_UNCONNECTED(0),
rxelecidlemode_in(1 downto 0) => B"11",
rxeqtraining_in(0) => '0',
rxgearboxslip_in(0) => rxgearboxslip_in(0),
rxheader_out(5 downto 0) => rxheader_out(5 downto 0),
rxheadervalid_out(1 downto 0) => rxheadervalid_out(1 downto 0),
rxlatclk_in(0) => '0',
rxlfpstresetdet_out(0) => NLW_inst_rxlfpstresetdet_out_UNCONNECTED(0),
rxlfpsu2lpexitdet_out(0) => NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED(0),
rxlfpsu3wakedet_out(0) => NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED(0),
rxlpmen_in(0) => '0',
rxlpmgchold_in(0) => '0',
rxlpmgcovrden_in(0) => '0',
rxlpmhfhold_in(0) => '0',
rxlpmhfovrden_in(0) => '0',
rxlpmlfhold_in(0) => '0',
rxlpmlfklovrden_in(0) => '0',
rxlpmoshold_in(0) => '0',
rxlpmosovrden_in(0) => '0',
rxmcommaalignen_in(0) => '0',
rxmonitorout_out(7 downto 0) => NLW_inst_rxmonitorout_out_UNCONNECTED(7 downto 0),
rxmonitorsel_in(1 downto 0) => B"00",
rxoobreset_in(0) => '0',
rxoscalreset_in(0) => '0',
rxoshold_in(0) => '0',
rxosintcfg_in(0) => '0',
rxosintdone_out(0) => NLW_inst_rxosintdone_out_UNCONNECTED(0),
rxosinten_in(0) => '0',
rxosinthold_in(0) => '0',
rxosintovrden_in(0) => '0',
rxosintstarted_out(0) => NLW_inst_rxosintstarted_out_UNCONNECTED(0),
rxosintstrobe_in(0) => '0',
rxosintstrobedone_out(0) => NLW_inst_rxosintstrobedone_out_UNCONNECTED(0),
rxosintstrobestarted_out(0) => NLW_inst_rxosintstrobestarted_out_UNCONNECTED(0),
rxosinttestovrden_in(0) => '0',
rxosovrden_in(0) => '0',
rxoutclk_out(0) => NLW_inst_rxoutclk_out_UNCONNECTED(0),
rxoutclkfabric_out(0) => NLW_inst_rxoutclkfabric_out_UNCONNECTED(0),
rxoutclkpcs_out(0) => NLW_inst_rxoutclkpcs_out_UNCONNECTED(0),
rxoutclksel_in(2 downto 0) => B"101",
rxpcommaalignen_in(0) => '0',
rxpcsreset_in(0) => '0',
rxpd_in(1 downto 0) => B"00",
rxphalign_in(0) => '0',
rxphaligndone_out(0) => NLW_inst_rxphaligndone_out_UNCONNECTED(0),
rxphalignen_in(0) => '0',
rxphalignerr_out(0) => NLW_inst_rxphalignerr_out_UNCONNECTED(0),
rxphdlypd_in(0) => '1',
rxphdlyreset_in(0) => '0',
rxphovrden_in(0) => '0',
rxpllclksel_in(1 downto 0) => B"11",
rxpmareset_in(0) => '0',
rxpmaresetdone_out(0) => rxpmaresetdone_out(0),
rxpolarity_in(0) => '0',
rxprbscntreset_in(0) => '0',
rxprbserr_out(0) => NLW_inst_rxprbserr_out_UNCONNECTED(0),
rxprbslocked_out(0) => NLW_inst_rxprbslocked_out_UNCONNECTED(0),
rxprbssel_in(3 downto 0) => B"0000",
rxprgdivresetdone_out(0) => rxprgdivresetdone_out(0),
rxprogdivreset_in(0) => '0',
rxqpien_in(0) => '0',
rxqpisenn_out(0) => NLW_inst_rxqpisenn_out_UNCONNECTED(0),
rxqpisenp_out(0) => NLW_inst_rxqpisenp_out_UNCONNECTED(0),
rxrate_in(2 downto 0) => B"000",
rxratedone_out(0) => NLW_inst_rxratedone_out_UNCONNECTED(0),
rxratemode_in(0) => '0',
rxrecclk0_sel_out(0) => NLW_inst_rxrecclk0_sel_out_UNCONNECTED(0),
rxrecclk0sel_out(1 downto 0) => NLW_inst_rxrecclk0sel_out_UNCONNECTED(1 downto 0),
rxrecclk1_sel_out(0) => NLW_inst_rxrecclk1_sel_out_UNCONNECTED(0),
rxrecclk1sel_out(1 downto 0) => NLW_inst_rxrecclk1sel_out_UNCONNECTED(1 downto 0),
rxrecclkout_out(0) => NLW_inst_rxrecclkout_out_UNCONNECTED(0),
rxresetdone_out(0) => NLW_inst_rxresetdone_out_UNCONNECTED(0),
rxslide_in(0) => '0',
rxsliderdy_out(0) => NLW_inst_rxsliderdy_out_UNCONNECTED(0),
rxslipdone_out(0) => NLW_inst_rxslipdone_out_UNCONNECTED(0),
rxslipoutclk_in(0) => '0',
rxslipoutclkrdy_out(0) => NLW_inst_rxslipoutclkrdy_out_UNCONNECTED(0),
rxslippma_in(0) => '0',
rxslippmardy_out(0) => NLW_inst_rxslippmardy_out_UNCONNECTED(0),
rxstartofseq_out(1 downto 0) => rxstartofseq_out(1 downto 0),
rxstatus_out(2 downto 0) => NLW_inst_rxstatus_out_UNCONNECTED(2 downto 0),
rxsyncallin_in(0) => '0',
rxsyncdone_out(0) => NLW_inst_rxsyncdone_out_UNCONNECTED(0),
rxsyncin_in(0) => '0',
rxsyncmode_in(0) => '0',
rxsyncout_out(0) => NLW_inst_rxsyncout_out_UNCONNECTED(0),
rxsysclksel_in(1 downto 0) => B"10",
rxtermination_in(0) => '0',
rxuserrdy_in(0) => '1',
rxusrclk2_in(0) => '0',
rxusrclk_in(0) => '0',
rxvalid_out(0) => NLW_inst_rxvalid_out_UNCONNECTED(0),
sdm0data_in(24 downto 0) => B"0100000000000000000000000",
sdm0finalout_out(3 downto 0) => NLW_inst_sdm0finalout_out_UNCONNECTED(3 downto 0),
sdm0reset_in(0) => '0',
sdm0testdata_out(14 downto 0) => NLW_inst_sdm0testdata_out_UNCONNECTED(14 downto 0),
sdm0toggle_in(0) => '0',
sdm0width_in(1 downto 0) => B"00",
sdm1data_in(24 downto 0) => B"0000000000000000000000000",
sdm1finalout_out(3 downto 0) => NLW_inst_sdm1finalout_out_UNCONNECTED(3 downto 0),
sdm1reset_in(0) => '0',
sdm1testdata_out(14 downto 0) => NLW_inst_sdm1testdata_out_UNCONNECTED(14 downto 0),
sdm1toggle_in(0) => '0',
sdm1width_in(1 downto 0) => B"00",
sigvalidclk_in(0) => '0',
tcongpi_in(0) => '0',
tcongpo_out(0) => NLW_inst_tcongpo_out_UNCONNECTED(0),
tconpowerup_in(0) => '0',
tconreset_in(0) => '0',
tconrsvdin1_in(0) => '0',
tconrsvdout0_out(0) => NLW_inst_tconrsvdout0_out_UNCONNECTED(0),
tstin_in(19 downto 0) => B"00000000000000000000",
tx8b10bbypass_in(7 downto 0) => B"00000000",
tx8b10ben_in(0) => '0',
txbufdiffctrl_in(0) => '0',
txbufstatus_out(1 downto 0) => NLW_inst_txbufstatus_out_UNCONNECTED(1 downto 0),
txcomfinish_out(0) => NLW_inst_txcomfinish_out_UNCONNECTED(0),
txcominit_in(0) => '0',
txcomsas_in(0) => '0',
txcomwake_in(0) => '0',
txctrl0_in(15 downto 0) => B"0000000000000000",
txctrl1_in(15 downto 0) => B"0000000000000000",
txctrl2_in(7 downto 0) => B"00000000",
txdata_in(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
txdataextendrsvd_in(7 downto 0) => B"00000000",
txdccdone_out(0) => NLW_inst_txdccdone_out_UNCONNECTED(0),
txdccforcestart_in(0) => '0',
txdccreset_in(0) => '0',
txdeemph_in(1 downto 0) => B"00",
txdetectrx_in(0) => '0',
txdiffctrl_in(4 downto 0) => B"11000",
txdiffpd_in(0) => '0',
txdlybypass_in(0) => '1',
txdlyen_in(0) => '0',
txdlyhold_in(0) => '0',
txdlyovrden_in(0) => '0',
txdlysreset_in(0) => '0',
txdlysresetdone_out(0) => NLW_inst_txdlysresetdone_out_UNCONNECTED(0),
txdlyupdown_in(0) => '0',
txelecidle_in(0) => '0',
txelforcestart_in(0) => '0',
txheader_in(5 downto 0) => txheader_in(5 downto 0),
txinhibit_in(0) => '0',
txlatclk_in(0) => '0',
txlfpstreset_in(0) => '0',
txlfpsu2lpexit_in(0) => '0',
txlfpsu3wake_in(0) => '0',
txmaincursor_in(6 downto 0) => B"1010000",
txmargin_in(2 downto 0) => B"000",
txmuxdcdexhold_in(0) => '0',
txmuxdcdorwren_in(0) => '0',
txoneszeros_in(0) => '0',
txoutclk_out(0) => NLW_inst_txoutclk_out_UNCONNECTED(0),
txoutclkfabric_out(0) => NLW_inst_txoutclkfabric_out_UNCONNECTED(0),
txoutclkpcs_out(0) => NLW_inst_txoutclkpcs_out_UNCONNECTED(0),
txoutclksel_in(2 downto 0) => B"101",
txpcsreset_in(0) => '0',
txpd_in(1 downto 0) => B"00",
txpdelecidlemode_in(0) => '0',
txphalign_in(0) => '0',
txphaligndone_out(0) => NLW_inst_txphaligndone_out_UNCONNECTED(0),
txphalignen_in(0) => '0',
txphdlypd_in(0) => '1',
txphdlyreset_in(0) => '0',
txphdlytstclk_in(0) => '0',
txphinit_in(0) => '0',
txphinitdone_out(0) => NLW_inst_txphinitdone_out_UNCONNECTED(0),
txphovrden_in(0) => '0',
txpippmen_in(0) => '0',
txpippmovrden_in(0) => '0',
txpippmpd_in(0) => '0',
txpippmsel_in(0) => '1',
txpippmstepsize_in(4 downto 0) => B"00000",
txpisopd_in(0) => '0',
txpllclksel_in(1 downto 0) => B"11",
txpmareset_in(0) => '0',
txpmaresetdone_out(0) => txpmaresetdone_out(0),
txpolarity_in(0) => '0',
txpostcursor_in(4 downto 0) => B"00000",
txpostcursorinv_in(0) => '0',
txprbsforceerr_in(0) => '0',
txprbssel_in(3 downto 0) => B"0000",
txprecursor_in(4 downto 0) => B"00000",
txprecursorinv_in(0) => '0',
txprgdivresetdone_out(0) => txprgdivresetdone_out(0),
txprogdivreset_in(0) => '0',
txqpibiasen_in(0) => '0',
txqpisenn_out(0) => NLW_inst_txqpisenn_out_UNCONNECTED(0),
txqpisenp_out(0) => NLW_inst_txqpisenp_out_UNCONNECTED(0),
txqpistrongpdown_in(0) => '0',
txqpiweakpup_in(0) => '0',
txrate_in(2 downto 0) => B"000",
txratedone_out(0) => NLW_inst_txratedone_out_UNCONNECTED(0),
txratemode_in(0) => '0',
txresetdone_out(0) => NLW_inst_txresetdone_out_UNCONNECTED(0),
txsequence_in(6 downto 0) => txsequence_in(6 downto 0),
txswing_in(0) => '0',
txsyncallin_in(0) => '0',
txsyncdone_out(0) => NLW_inst_txsyncdone_out_UNCONNECTED(0),
txsyncin_in(0) => '0',
txsyncmode_in(0) => '0',
txsyncout_out(0) => NLW_inst_txsyncout_out_UNCONNECTED(0),
txsysclksel_in(1 downto 0) => B"10",
txuserrdy_in(0) => '1',
txusrclk2_in(0) => '0',
txusrclk_in(0) => '0',
ubcfgstreamen_in(0) => '0',
ubdaddr_out(15 downto 0) => NLW_inst_ubdaddr_out_UNCONNECTED(15 downto 0),
ubden_out(0) => NLW_inst_ubden_out_UNCONNECTED(0),
ubdi_out(15 downto 0) => NLW_inst_ubdi_out_UNCONNECTED(15 downto 0),
ubdo_in(15 downto 0) => B"0000000000000000",
ubdrdy_in(0) => '0',
ubdwe_out(0) => NLW_inst_ubdwe_out_UNCONNECTED(0),
ubenable_in(0) => '0',
ubgpi_in(1 downto 0) => B"00",
ubintr_in(1 downto 0) => B"00",
ubiolmbrst_in(0) => '0',
ubmbrst_in(0) => '0',
ubmdmcapture_in(0) => '0',
ubmdmdbgrst_in(0) => '0',
ubmdmdbgupdate_in(0) => '0',
ubmdmregen_in(3 downto 0) => B"0000",
ubmdmshift_in(0) => '0',
ubmdmsysrst_in(0) => '0',
ubmdmtck_in(0) => '0',
ubmdmtdi_in(0) => '0',
ubmdmtdo_out(0) => NLW_inst_ubmdmtdo_out_UNCONNECTED(0),
ubrsvdout_out(0) => NLW_inst_ubrsvdout_out_UNCONNECTED(0),
ubtxuart_out(0) => NLW_inst_ubtxuart_out_UNCONNECTED(0)
);
end STRUCTURE;
|
---------------------------------------------------------------------------------
--
-- Copyright 2017 - <NAME> Laboratory and University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ipbus.web.cern.ch/ipbus
--
---------------------------------------------------------------------------------
-- Simple interface to tx side of transactor...
-- Even simpler, but now multi-buffer RAM!
--
-- <NAME>, September 2012
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity udp_txtransactor_if is
generic(
BUFWIDTH: natural := 0
);
port (
mac_clk: in std_logic;
rst_macclk: in std_logic;
--
pkt_resend: in std_logic;
resend_pkt_id: in std_logic_vector(15 downto 0);
--
ipbus_out_hdr: in std_logic_vector(31 downto 0);
ipbus_out_valid: in std_logic;
tx_read_buffer: in std_logic_vector(BUFWIDTH - 1 downto 0);
--
udpram_busy: in std_logic;
clean_buf: in std_logic_vector(2**BUFWIDTH - 1 downto 0);
--
req_not_found: out std_logic;
req_resend: out std_logic;
resend_buf: out std_logic_vector(BUFWIDTH - 1 downto 0);
udpram_sent: out std_logic
);
end udp_txtransactor_if;
architecture simple of udp_txtransactor_if is
type pktid_buf is array (2**BUFWIDTH - 1 downto 0) of std_logic_vector(15 downto 0);
signal pkt_id_buf: pktid_buf;
begin
pkt_id_block: process (mac_clk)
begin
if rising_edge(mac_clk) then
if rst_macclk = '1' then
pkt_id_buf <= (Others => (Others => '0'));
elsif ipbus_out_valid = '1' then
-- Take byte ordering into account and make packet ID big endian...
if ipbus_out_hdr(31 downto 24) = x"20" then
pkt_id_buf(to_integer(unsigned(tx_read_buffer))) <= ipbus_out_hdr(23 downto 8);
else
pkt_id_buf(to_integer(unsigned(tx_read_buffer))) <=
ipbus_out_hdr(15 downto 8) & ipbus_out_hdr(23 downto 16);
end if;
end if;
end if;
end process;
resend_block: process (mac_clk)
variable req_resend_i, req_not_found_i: std_logic;
variable resend_buf_i: std_logic_vector(BUFWIDTH - 1 downto 0);
begin
if rising_edge(mac_clk) then
req_resend_i := '0';
req_not_found_i := '0';
resend_buf_i := (Others => '0');
if pkt_resend = '1' then
for i in 0 to 2**BUFWIDTH - 1 loop
if pkt_id_buf(i) = resend_pkt_id and clean_buf(i) = '1' then
req_resend_i := '1';
resend_buf_i := std_logic_vector(to_unsigned(i, BUFWIDTH));
end if;
end loop;
req_not_found_i := not req_resend_i;
end if;
req_not_found <= req_not_found_i
-- pragma translate_off
after 4 ns
-- pragma translate_on
;
req_resend <= req_resend_i
-- pragma translate_off
after 4 ns
-- pragma translate_on
;
resend_buf <= resend_buf_i
-- pragma translate_off
after 4 ns
-- pragma translate_on
;
end if;
end process;
sent_block: process (mac_clk)
variable last_busy: std_logic;
begin
if rising_edge(mac_clk) then
udpram_sent <= last_busy and not udpram_busy
-- pragma translate_off
after 4 ns
-- pragma translate_on
;
last_busy := udpram_busy;
end if;
end process;
end simple;
|
<filename>hdl/generic_spi_master.vhd
--************************************************************************
-- @author: <NAME>
-- @copyright: Copyright 2021
-- @credits: AKAE
--
-- @license: BSDv3
-- @maintainer: <NAME>
-- @email: <EMAIL>
--
-- @note: VHDL'93
-- @file: generic_spi_master.vhd
-- @date: 2021-01-23
--
-- @see: https://github.com/akaeba/generic_spi_master
-- @brief: SPI Master
--
-- Generic SPI master with multiple chip select lines
-- and a at compile time adjustable transfer rate.
-- The chip select lines use a round robin arbitration
-- starting with lowest CSN index.
--************************************************************************
--
-- Important Hints:
-- ================
--
-- Key Features
-- ------------
-- * SPI Mode 0-3
-- * Arbitrary number of chip-selects (CSN)
-- * Adjustable shift register width
-- * FSCK,max = FCLK/2
-- * FSCK settable at compile
-- * MISO input filter
-- * round-robin CSN arbitration, starting at low index
-- * no parallel buffer registers for minimal resource footprint
--
-- SPI Mode
-- --------
-- +----------+------+------+
-- | SPI Mode | CPOL | CPHA |
-- +----------+------+------+
-- | 0 | 0 | 0 |
-- | 1 | 0 | 1 |
-- | 2 | 1 | 0 |
-- | 3 | 1 | 1 |
-- +----------+------+------+
--
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.log2;
use IEEE.math_real.ceil;
use IEEE.math_real.floor;
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Generic SPI Master
entity generic_spi_master is
generic (
SPI_MODE : integer range 0 to 3 := 0; --! used transfer mode
NUM_CS : positive := 1; --! Number of Channels (chip-selects)
DW_SFR : integer := 8; --! data width serial in/out shift register
CLK_HZ : positive := 50_000_000; --! clock frequency
SCK_HZ : positive := 1_000_000; --! Bit clock rate; minimal frequency - can be higher due numeric rounding effects
RST_ACTIVE : bit := '1'; --! Reset active level
MISO_SYNC_STG : natural range 0 to 3 := 0; --! number of MISO sync stages, 0: not implemented
MISO_FILT_STG : natural := 0 --! number of evaluated sample bits for hysteresis, 0/1: not implemented
);
port (
-- Clock/Reset
RST : in std_logic; --! asynchronous reset
CLK : in std_logic; --! clock, rising edge
-- SPI
CSN : out std_logic_vector(NUM_CS-1 downto 0); --! chip select
SCK : out std_logic; --! Shift forward clock
MOSI : out std_logic; --! serial data out; master-out / slave-in
MISO : in std_logic; --! serial data in; master-in / slave-out
-- Parallel
DI : in std_logic_vector(DW_SFR-1 downto 0); --! Parallel data-in, transmitted via MOSI
DO : out std_logic_vector(DW_SFR-1 downto 0); --! Parallel data-out, received via MISO
-- Management
EN : in std_logic; --! if in idle master starts receive and transmission
BSY : out std_logic; --! transmission is active
DI_RD : out std_logic_vector(NUM_CS-1 downto 0); --! DI segment transfered into MOSI shift forward register
DO_WR : out std_logic_vector(NUM_CS-1 downto 0) --! DO segment contents new data
);
end entity generic_spi_master;
--------------------------------------------------------------------------
--------------------------------------------------------------------------
architecture rtl of generic_spi_master is
----------------------------------------------
-- Constants
----------------------------------------------
-- SPI Mode
constant c_spi_mode_slv : std_logic_vector(1 downto 0) := std_logic_vector(to_unsigned(SPI_MODE, 2)); --! spi mode as slv
alias c_cpol : std_logic is c_spi_mode_slv(1); --! clock polarity; 0: clock idle low, 1: clock idle high
alias c_cpha : std_logic is c_spi_mode_slv(0); --! clock phase; 0: latch on first edge 1: latch on second edge
-- SCK Clock Divider
constant c_sck_div_2 : integer := integer(floor(real(CLK_HZ)/(2.0*real(SCK_HZ)))); --! 2.0 cause SCK needs half clocks
constant c_sck_div_width : integer := integer(ceil(log2(real(c_sck_div_2+1)))); --! half lock counter width
constant c_sck_cntr_init : unsigned(c_sck_div_width-1 downto 0) := to_unsigned(c_sck_div_2-1, c_sck_div_width); --! init value of SCK counter
-- Counter
constant c_bit_cntr_width : integer := integer(ceil(log2(real(DW_SFR+1)))); --! bit counter for SFR
constant c_cs_cntr_width : integer := integer(ceil(log2(real(NUM_CS+1)))); --! chip select channel counter
----------------------------------------------
----------------------------------------------
-- SPI state machine
----------------------------------------------
type t_spi_master is
(
IDLE, --! Wait for transfer start
CSN_START, --! CSN at transmission start
SCK_CHG, --! SFR output (MOSI) is changed
SCK_CAP, --! SFR captures input (MISO)
CSN_END, --! CSN at transmission start
CSN_FRC --! ensures wait of half SCK period
);
----------------------------------------------
----------------------------------------------
-- Signals
----------------------------------------------
-- FSM
signal current_state : t_spi_master; --! FSM state
signal next_state : t_spi_master; --! next state
-- Counter
signal sck_cntr_cnt : unsigned(c_sck_div_width-1 downto 0); --! SCK clock generator counter value
signal sck_cntr_ld : std_logic; --! load SCK clock generator
signal sck_cntr_en : std_logic; --! counter decrements
signal sck_cntr_is_zero : std_logic; --! actual count value is zero
signal sck_cntr_is_init : std_logic; --! counter was initialized
signal bit_cntr_cnt : unsigned(c_bit_cntr_width-1 downto 0); --! bit counter, needed for FSMs end of shift
signal bit_cntr_ld : std_logic; --! preload bit counter
signal bit_cntr_is_zero : std_logic; --! has zero count
signal bit_cntr_is_init : std_logic; --! has load count
signal bit_cntr_en : std_logic; --! enable counters decrement
signal cs_cntr_cnt : unsigned(c_cs_cntr_width-1 downto 0); --! CS channel selection counter
signal cs_cntr_zero : std_logic; --! make counter to zero
signal cs_cntr_en : std_logic; --! enable increment
signal cs_cntr_is_zero : std_logic; --! has minimal value, zero
-- SFR
signal sck_tff : std_logic; --! toggle flip-flop for SCK clock generation
signal sck_tff_ld : std_logic; --! preload register
signal sck_tff_en : std_logic; --! enable toggle
signal mosi_sfr : std_logic_vector(DW_SFR-1 downto 0); --! MOSI shift register
signal mosi_load : std_logic; --! load parallel data
signal mosi_shift : std_logic; --! shift on next clock rise edge
signal miso_filt : std_logic; --! filtered MISO data input
signal miso_sfr : std_logic_vector(DW_SFR-1 downto 0); --! MISO shift register
signal miso_shift : std_logic; --! shift on next clock rise edge
signal miso_shift_in : std_logic; --! shift delayed with filter delay
signal miso_shift_dly1 : std_logic; --! one clock cycle delayed mosi shift
-- Miscellaneous
signal csn_ff : std_logic_vector(CSN'range); --! CSN registered out
signal csn_ff_ld : std_logic;
signal csn_ff_en : std_logic;
----------------------------------------------
begin
----------------------------------------------
-- Synthesis/Simulator Messages
-- general
assert not true
report character(LF) &
"generic_spi_master" & character(LF) &
" SPI Mode : " & integer'image(SPI_MODE) & character(LF) &
" Chip select : " & integer'image(NUM_CS) & character(LF) &
" SFR width : " & integer'image(DW_SFR) & character(LF) &
" FCLK : " & integer'image(CLK_HZ) & "Hz" & character(LF) &
" FSCK : " & integer'image(CLK_HZ/(2*c_sck_div_2)) & "Hz"
severity note;
-- filter not implemented, but requested
assert not ( (c_sck_div_2 <= (MISO_SYNC_STG + MISO_FILT_STG)) and ((0 /= MISO_SYNC_STG) or (0 /= MISO_FILT_STG)) )
report character(LF) &
"MISO Filter" & character(LF) &
" SYNC : " & integer'image(MISO_SYNC_STG) & character(LF) &
" FILTER : " & integer'image(MISO_FILT_STG) & character(LF) &
" CLKDIV2 : " & integer'image(c_sck_div_2) & character(LF) &
"NOT IMPLEMENTED, OVERSAMPLING FACTOR OF SCK TWO LOW; SYNC + FILTER < CLKDIV2"
severity warning;
----------------------------------------------
----------------------------------------------
-- SPI Clock generator & control
----------------------------------------------
--***************************
p_sck : process( RST, CLK )
begin
if ( RST = to_stdulogic(RST_ACTIVE) ) then
sck_tff <= c_cpol;
elsif ( rising_edge(CLK) ) then
if ( '1' = sck_tff_ld ) then
sck_tff <= c_cpol;
elsif ( '1' = sck_tff_en ) then
sck_tff <= not sck_tff;
end if;
end if;
end process p_sck;
--***************************
--***************************
-- toggle control
with current_state select --! preload
sck_tff_ld <= '1' when IDLE, --! init
'1' when CSN_END, --! SPI Mode 0/2 last toggle skipped, bring to idle
'0' when others; --! counter not needed, reload
with current_state select --! enable
sck_tff_en <= ((c_cpha or (not bit_cntr_is_init)) and sck_cntr_is_init) when SCK_CHG, --! SPI Mode 0/2 TFF toggels not on falling edge of CSN
sck_cntr_is_init when SCK_CAP, --! toggle
'0' when others; --! hold
--***************************
--***************************
-- port assignment
SCK <= sck_tff;
--***************************
----------------------------------------------
----------------------------------------------
-- CSN Register & Control
----------------------------------------------
--***************************
p_csn_reg : process( RST, CLK )
begin
if ( RST = to_stdulogic(RST_ACTIVE) ) then
csn_ff <= (others => '1');
elsif ( rising_edge(CLK) ) then
if ( '1' = csn_ff_ld ) then
csn_ff <= (others => '1');
elsif ( '1' = csn_ff_en ) then
csn_ff <= (others => '1'); --! disable all
csn_ff(to_integer(to_01(cs_cntr_cnt))) <= '0'; --! enable selected channel
end if;
end if;
end process p_csn_reg;
--***************************
--***************************
-- Control
with current_state select --! select channel
csn_ff_en <= '1' when CSN_START, --! SPI Mode 1/3,
(((not c_cpha) and bit_cntr_is_init) and sck_cntr_is_init) when SCK_CHG, --! SPI Mode 0/2, CSN is enabled at SCK change
'0' when others; --! hold last value
with current_state select --! deselect all
csn_ff_ld <= '1' when IDLE, --! all slaves disabled
'1' when CSN_FRC, --! deselect all slaves
'0' when others; --! hold last value
--***************************
--***************************
-- port assignment
CSN <= csn_ff;
--***************************
----------------------------------------------
----------------------------------------------
-- MOSI Shift Register & Control
----------------------------------------------
--***************************
-- SFR
p_mosi_sfr : process( RST, CLK )
begin
if ( to_stdulogic(RST_ACTIVE) = RST ) then
mosi_sfr <= (others => '0');
elsif ( rising_edge(CLK) ) then
if ( '1' = mosi_load ) then
mosi_sfr <= DI; --! load SFR
elsif ( '1' = mosi_shift ) then
mosi_sfr <= mosi_sfr(mosi_sfr'left-1 downto mosi_sfr'right) & '0'; --! shift one bit to left
end if;
end if;
end process p_mosi_sfr;
--***************************
--***************************
-- SFR Control
with current_state select --! MOSI load, dominant
mosi_load <= bit_cntr_is_init and sck_cntr_is_init when SCK_CHG, --! new value
'0' when others; --!
with current_state select --! MOSI shift
mosi_shift <= sck_cntr_is_init when SCK_CHG, --! shift
sck_cntr_is_init when CSN_END, --! sets line to zero
'0' when others; --! no shift
--***************************
--***************************
-- Input selection
p_di_sel : process( mosi_load, cs_cntr_cnt )
begin
DI_RD <= (others => '0');
DI_RD(to_integer(to_01(cs_cntr_cnt))) <= mosi_load;
end process p_di_sel;
--***************************
--***************************
-- Output
MOSI <= mosi_sfr(mosi_sfr'left); --! MSB is shifted out first
--***************************
----------------------------------------------
----------------------------------------------
-- MISO Shift Register
----------------------------------------------
--***************************
-- MISO input filtering
-- sample point = sync stages + floor(filter stages/2)
-- for relaxed internal FSM handling some additional clock cycles
g_filter : if c_sck_div_2 > (MISO_SYNC_STG + MISO_FILT_STG) generate
i_generic_spi_master_inp_filter : entity work.generic_spi_master_inp_filter
generic map (
SYNC_STAGES => MISO_SYNC_STG, --! synchronizer stages; 0: not implemented
VOTER_STAGES => MISO_FILT_STG, --! number of ff stages for voter; if all '1' out is '1', if all '0' out '0', otherwise hold; 0: not implemented
RST_STRBO => '0', --! STRBO output in reset
RST_ACTIVE => RST_ACTIVE --! Reset active level
)
port map (
RST => RST, --! asynchronous reset
CLK => CLK, --! clock, rising edge
FILTI => MISO, --! filter input
FILTO => miso_filt, --! filter output
STRBI => miso_shift_in, --! data strobe input
STRBO => miso_shift --! data strobe output, not filtered only delayed like filter delay, strobe is center aligned to filter chain
);
end generate g_filter;
--***************************
--***************************
-- No input filtering
-- filter delay is longer then capturing state of FSM, avoids complex FSM
g_skip_filter : if c_sck_div_2 <= (MISO_SYNC_STG + MISO_FILT_STG) generate
miso_filt <= MISO;
miso_shift <= miso_shift_in;
end generate g_skip_filter;
--***************************
--***************************
-- SFR
p_miso_sfr : process( RST, CLK )
begin
if ( to_stdulogic(RST_ACTIVE) = RST ) then
miso_sfr <= (others => '0');
miso_shift_dly1 <= '0';
elsif ( rising_edge(CLK) ) then
-- SFR
if ( '1' = miso_shift ) then
miso_sfr <= miso_sfr(miso_sfr'left-1 downto miso_sfr'right) & miso_filt; --! shift one bit to left
end if;
-- DFF
miso_shift_dly1 <= miso_shift;
end if;
end process p_MISO_sfr;
--***************************
--***************************
-- SFR Control
with current_state select --! MOSI shift
miso_shift_in <= sck_cntr_is_init when SCK_CAP, --! when SCK_CAP, --! shift
'0' when others; --! no shift
--***************************
--***************************
-- Output Capturing
p_do_sel : process( miso_shift_dly1, cs_cntr_cnt, bit_cntr_is_zero )
begin
DO_WR <= (others => '0');
DO_WR(to_integer(to_01(cs_cntr_cnt))) <= miso_shift_dly1 and bit_cntr_is_zero; --! SFR data complete received
end process p_do_sel;
--***************************
--***************************
-- Output
DO <= miso_sfr; --! Captured Serial data is released
--***************************
----------------------------------------------
----------------------------------------------
-- SCK counter & control
----------------------------------------------
--***************************
-- c_sck_div_2 > 1 -> go in wait state, and count divider down
--
g_sck_cntr : if c_sck_div_2 > 1 generate
-- registered counter
p_sck_cntr : process( RST, CLK )
begin
if ( to_stdulogic(RST_ACTIVE) = RST ) then
-- Reset
sck_cntr_cnt <= (others => '0');
elsif ( rising_edge(CLK) ) then
-- SCK Clock generator
if ( '1' = sck_cntr_ld ) then
-- counter clock divider required?
if ( 1 < c_sck_div_2 ) then --! SCK < CLK/2
sck_cntr_cnt <= c_sck_cntr_init;
else --! SCK = CLK/2
sck_cntr_cnt <= (others => '0');
end if;
elsif ( '1' = sck_cntr_en ) then
sck_cntr_cnt <= sck_cntr_cnt-1;
end if;
end if;
end process p_sck_cntr;
-- control
with current_state select --! reload
sck_cntr_ld <= sck_cntr_is_zero when CSN_START, --! wait for target shift clock generation, and overflow
sck_cntr_is_zero when SCK_CHG, --!
sck_cntr_is_zero when SCK_CAP, --!
sck_cntr_is_zero when CSN_END, --!
sck_cntr_is_zero when CSN_FRC, --!
'1' when others; --! counter not needed, reload
with current_state select --! enable
sck_cntr_en <= '1' when CSN_START, --! count to achieve target clock
'1' when SCK_CHG, --!
'1' when SCK_CAP, --!
'1' when CSN_END, --!
'1' when CSN_FRC, --!
'0' when others; --! no count
end generate g_sck_cntr;
--***************************
--***************************
-- c_sck_div_2 = 1 -> SCK toggles at every CLK rising edge, no wait state required
--
g_skip_sck_cntr : if c_sck_div_2 <= 1 generate
sck_cntr_cnt <= (others => '0');
end generate g_skip_sck_cntr;
--***************************
--***************************
-- Flags
sck_cntr_is_zero <= '1' when ( 0 = to_01(sck_cntr_cnt) ) else '0';
sck_cntr_is_init <= '1' when ( c_sck_cntr_init = to_01(sck_cntr_cnt) ) else '0';
--***************************
----------------------------------------------
----------------------------------------------
-- CSN counter & control
----------------------------------------------
--***************************
-- NUM_CS > 1 -> serve multiple CS in round robin method, starting at low index
--
g_csn_cntr : if NUM_CS > 1 generate
-- registered counter
p_csn_cntr : process( RST, CLK )
begin
if ( to_stdulogic(RST_ACTIVE) = RST ) then
-- Reset
cs_cntr_cnt <= (others => '0');
elsif ( rising_edge(CLK) ) then
-- CS counter
if ( '1' = cs_cntr_zero ) then
cs_cntr_cnt <= (others => '0');
elsif ( '1' = cs_cntr_en ) then
if ( cs_cntr_cnt = NUM_CS-1 ) then --! overflow, always inside CSN vector
cs_cntr_cnt <= (others => '0');
else
cs_cntr_cnt <= cs_cntr_cnt + 1; --! increment
end if;
end if;
end if;
end process p_csn_cntr;
-- control
with current_state select --! clears counter
cs_cntr_zero <= '1' when IDLE, --! clear
'0' when others; --! hold
with current_state select --! enable
cs_cntr_en <= sck_cntr_is_init when CSN_FRC, --! ready to release
'0' when others; --! hold
end generate g_csn_cntr;
--***************************
--***************************
-- NUM_CS = 1 -> no counter necessary
--
g_skip_csn_cntr : if NUM_CS <= 1 generate
cs_cntr_cnt <= (others => '0');
end generate g_skip_csn_cntr;
--***************************
--***************************
-- flags
cs_cntr_is_zero <= '1' when ( 0 = to_01(cs_cntr_cnt) ) else '0';
--***************************
----------------------------------------------
----------------------------------------------
-- Counter registers & Control
----------------------------------------------
--***************************
p_bit_cntr : process( RST, CLK )
begin
if ( to_stdulogic(RST_ACTIVE) = RST ) then
-- Reset
bit_cntr_cnt <= (others => '0');
elsif ( rising_edge(CLK) ) then
-- Bit counter
if ( '1' = bit_cntr_ld ) then
bit_cntr_cnt <= to_unsigned(DW_SFR, bit_cntr_cnt'length);
elsif ( '1' = bit_cntr_en ) then
bit_cntr_cnt <= bit_cntr_cnt-1;
end if;
end if;
end process p_bit_cntr;
--***************************
--***************************
-- Bit counter
with current_state select --! reload
bit_cntr_ld <= '1' when IDLE, --! preload
'1' when CSN_FRC, --! reload counter in SPI Mode 0/2, cause CSN_START is bypassed
'1' when CSN_START, --! preload counter
'0' when others; --! counter not needed, reload
with current_state select --! enable
bit_cntr_en <= sck_cntr_is_init when SCK_CHG, --! decrement counter
'0' when others; --! hold
-- Flags
bit_cntr_is_zero <= '1' when ( 0 = to_01(bit_cntr_cnt) ) else '0';
bit_cntr_is_init <= '1' when ( to_unsigned(DW_SFR, bit_cntr_cnt'length) = to_01(bit_cntr_cnt) ) else '0';
--***************************
----------------------------------------------
----------------------------------------------
-- Miscellaneous
----------------------------------------------
--***************************
-- SPI activity
with current_state select --! SPI active
BSY <= '0' when IDLE, --! idle
'1' when others; --! busy
--***************************
----------------------------------------------
----------------------------------------------
-- FSM state registers
p_fsm_reg : process( RST, CLK )
begin
if ( to_stdulogic(RST_ACTIVE) = RST ) then
current_state <= IDLE;
elsif ( rising_edge(CLK) ) then
current_state <= next_state;
end if;
end process p_fsm_reg;
----------------------------------------------
----------------------------------------------
-- next state calculation
p_next_state : process (
current_state, --! current FSM state
EN, --! module inputs, enables transceiver
sck_cntr_is_zero, --! sck counter expired
bit_cntr_is_zero, --! count shifted times
cs_cntr_is_zero --! cs counter expired
)
begin
-- default assignment
next_state <= current_state; --! default assignment
-- state transitions
case current_state is
--***************************
-- wait for start
when IDLE =>
if ( '1' = EN ) then
if ( '0' = c_cpha ) then --! SPI mode 0/2
next_state <= SCK_CHG;
else
next_state <= CSN_START;
end if;
else
next_state <= IDLE;
end if;
--***************************
--***************************
-- Chip select is asserted
when CSN_START =>
if ( '1' = sck_cntr_is_zero ) then --! wait done
next_state <= SCK_CHG;
else --! clock division
next_state <= CSN_START;
end if;
--***************************
--***************************
-- MOSI changes
when SCK_CHG =>
if ( '1' = sck_cntr_is_zero ) then --! wait done
next_state <= SCK_CAP;
else --! SCK clock division
next_state <= SCK_CHG;
end if;
--***************************
--***************************
-- MISO captured
when SCK_CAP =>
if ( '1' = sck_cntr_is_zero ) then
if ( '1' = bit_cntr_is_zero ) then
if ( '0' = c_cpha ) then --! SPI mode 0/2
next_state <= CSN_END; --! waits half clock SCK cycle before CS disabling
else --! SPI mode 1/3
next_state <= CSN_FRC; --! de-select SPI slave
end if;
else
next_state <= SCK_CHG;
end if;
else --! clock division
next_state <= SCK_CAP;
end if;
--***************************
--***************************
-- Wait for CSN half SCK cycle before deassert
when CSN_END =>
if ( '1' = sck_cntr_is_zero ) then
next_state <= CSN_FRC;
else
next_state <= CSN_END;
end if;
--***************************
--***************************
-- Limits CSN disable/enable to half SCK
when CSN_FRC =>
if ( '1' = sck_cntr_is_zero ) then --! go on
if ( '1' = cs_cntr_is_zero ) then --! all CSN channels served
if ( '1' = EN ) then --! continuous run
if ( '0' = c_cpha ) then
next_state <= SCK_CHG; --! next CS, SPI 0/2
else
next_state <= CSN_START; --! next CS, SPI 1/3
end if;
else
next_state <= IDLE; --! all channels served
end if;
else
if ( '0' = c_cpha ) then
next_state <= SCK_CHG; --! next CS, SPI 0/2
else
next_state <= CSN_START; --! next CS, SPI 1/3
end if;
end if;
else --! clock division
next_state <= CSN_FRC;
end if;
--***************************
--***************************
-- Recovering from illegal state transitions
when others =>
next_state <= IDLE;
--***************************
end case;
end process p_next_state;
----------------------------------------------
end architecture rtl;
--------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity slr is
generic (
m : integer := 6);
port (
din : in std_logic_vector(m-1 downto 0); -- input
clk : in std_logic; -- input
en : in std_logic; -- input
load : in std_logic; -- input
Q : out std_logic); -- output
end entity slr;
architecture slr_arc of slr is
signal temp : std_logic_vector(m-1 downto 0);
begin -- architecture srl_arc
process(clk)
begin
if (clk'event and clk='1') then
if (en='1') then
if (load='1') then
temp<=din;
else
temp<=temp(m-2 downto 0) & temp(m-1);
end if;
end if;
Q<=temp(m-1);
end if;
end process;
end architecture slr_arc;
|
----------------------------------------------------------------------------------------------------
-- Block name: DISCRETE_COMM_SHIELD --
----------------------------------------------------------------------------------------------------
-- Author name: <NAME> --
----------------------------------------------------------------------------------------------------
-- Dependencies: None. --
----------------------------------------------------------------------------------------------------
-- Initial version 1 - 09/08/2017 --
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DISCRETE_COMM_SHIELD is
port (
-- Clock and Reset signals
CLK_50MHZ : in std_logic; -- 50 MHz clock.
nRESET : in std_logic; -- Asynchronous reset (Active LOW).
-- FPGA_MAIN_MODULE ports interface
DISC_IN_1_SH_D2 : in std_logic; -- Arduino Shield digital port D2. Discrete Input 1.
DISC_IN_2_SH_D4 : in std_logic; -- Arduino Shield digital port D4. Discrete Input 2.
DISC_IN_3_SH_D7 : in std_logic; -- Arduino Shield digital port D7. Discrete Input 3.
PWM_1_SH_D3 : out std_logic; -- Arduino Shield digital port D3. PWM port 1.
PWM_2_SH_D5 : out std_logic; -- Arduino Shield digital port D5. PWM port 2.
PWM_3_SH_D6 : out std_logic; -- Arduino Shield digital port D6. PWM port 3.
DISC_OUT_1_SH_D8 : out std_logic; -- Arduino Shield digital port D8. Discrete Ouput 1.
DISC_OUT_2_SH_D12 : out std_logic; -- Arduino Shield digital port D8. Discrete Ouput 1.
DISC_OUT_3_SH_D13 : out std_logic; -- Arduino Shield digital port D8. Discrete Ouput 1.
PWM_4_SH_D9 : out std_logic; -- Arduino Shield digital port D9. PWM port 4.
PWM_5_SH_D10 : out std_logic; -- Arduino Shield digital port D10. PWM port 5.
PWM_6_SH_D11 : out std_logic; -- Arduino Shield digital port D11. PWM port 6.
-- MAIN_PROCESSOR ports interface
DISC_OUT_SH_LEVEL : in std_logic_vector(8 downto 0); -- Commanded level for discrete outputs.
DISC_IN_SH_EDGE : out std_logic_vector(2 downto 0)); -- Edge detected in discrete inputs.
end DISCRETE_COMM_SHIELD;
architecture RTL of DISCRETE_COMM_SHIELD is
----------------------------------------------------------------------------------------------------
-- COMPONENT DECLARATIONS --
----------------------------------------------------------------------------------------------------
-- None.
----------------------------------------------------------------------------------------------------
-- SIGNAL DECLARATIONS --
----------------------------------------------------------------------------------------------------
-- Edge detector
signal DISC_IN_1_SH_D2_FF : std_logic; -- Discrete Input 1 register
signal DISC_IN_2_SH_D4_FF : std_logic; -- Discrete Input 2 register
signal DISC_IN_3_SH_D7_FF : std_logic; -- Discrete Input 3 register
begin
----------------------------------------------------------------------------------------------------
-- COMPONENT INSTANTIATIONS --
----------------------------------------------------------------------------------------------------
-- None.
-- Discrete Input edge detector
DISCRETE_INPUT_EDGE_DET: process(CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if nRESET = '0' then
DISC_IN_1_SH_D2_FF <= '0';
DISC_IN_2_SH_D4_FF <= '0';
DISC_IN_3_SH_D7_FF <= '0';
DISC_IN_SH_EDGE <= (others => '0');
else
DISC_IN_1_SH_D2_FF <= DISC_IN_1_SH_D2;
DISC_IN_2_SH_D4_FF <= DISC_IN_2_SH_D4;
DISC_IN_3_SH_D7_FF <= DISC_IN_3_SH_D7;
DISC_IN_SH_EDGE(0) <= DISC_IN_1_SH_D2 xor DISC_IN_1_SH_D2_FF;
DISC_IN_SH_EDGE(1) <= DISC_IN_2_SH_D4 xor DISC_IN_2_SH_D4_FF;
DISC_IN_SH_EDGE(2) <= DISC_IN_3_SH_D7 xor DISC_IN_3_SH_D7_FF;
end if;
end if;
end process DISCRETE_INPUT_EDGE_DET;
-- Discrete Output register
DISCRETE_OUTPUT_REG: process(CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if nRESET = '0' then
PWM_1_SH_D3 <= '0';
PWM_2_SH_D5 <= '0';
PWM_3_SH_D6 <= '0';
DISC_OUT_1_SH_D8 <= '0';
DISC_OUT_2_SH_D12 <= '0';
DISC_OUT_3_SH_D13 <= '0';
PWM_4_SH_D9 <= '0';
PWM_5_SH_D10 <= '0';
PWM_6_SH_D11 <= '0';
else
PWM_1_SH_D3 <= DISC_OUT_SH_LEVEL(0);
PWM_2_SH_D5 <= DISC_OUT_SH_LEVEL(1);
PWM_3_SH_D6 <= DISC_OUT_SH_LEVEL(2);
DISC_OUT_1_SH_D8 <= DISC_OUT_SH_LEVEL(3);
DISC_OUT_2_SH_D12 <= DISC_OUT_SH_LEVEL(4);
DISC_OUT_3_SH_D13 <= DISC_OUT_SH_LEVEL(5);
PWM_4_SH_D9 <= DISC_OUT_SH_LEVEL(6);
PWM_5_SH_D10 <= DISC_OUT_SH_LEVEL(7);
PWM_6_SH_D11 <= DISC_OUT_SH_LEVEL(8);
end if;
end if;
end process DISCRETE_OUTPUT_REG;
end RTL;
|
<reponame>slaclab/smurf-pcie
-------------------------------------------------------------------------------
-- File : EthPhyWrapper.vhd
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiStreamPkg.all;
use surf.AxiLitePkg.all;
use surf.EthMacPkg.all;
use surf.TenGigEthPkg.all;
use work.AppPkg.all;
library unisim;
use unisim.vcomponents.all;
entity EthPhyWrapper is
generic (
TPD_G : time := 1 ns;
AXI_BASE_ADDR_G : slv(31 downto 0));
port (
-- Local Configurations
localMac : out Slv48Array(NUM_RSSI_C-1 downto 0);
localIp : out Slv32Array(NUM_RSSI_C-1 downto 0);
udpToPhyRoute : in Slv8Array(NUM_RSSI_C-1 downto 0);
-- Streaming DMA Interface
udpIbMasters : out AxiStreamMasterArray(NUM_RSSI_C-1 downto 0);
udpIbSlaves : in AxiStreamSlaveArray(NUM_RSSI_C-1 downto 0);
udpObMasters : in AxiStreamMasterArray(NUM_RSSI_C-1 downto 0);
udpObSlaves : out AxiStreamSlaveArray(NUM_RSSI_C-1 downto 0);
-- Slave AXI-Lite Interface
axilClk : in sl;
axilRst : in sl;
axilReadMaster : in AxiLiteReadMasterType;
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;
---------------------
-- Hardware Ports
---------------------
-- QSFP[0] Ports
qsfp0RefClkP : in slv(1 downto 0);
qsfp0RefClkN : in slv(1 downto 0);
qsfp0RxP : in slv(3 downto 0);
qsfp0RxN : in slv(3 downto 0);
qsfp0TxP : out slv(3 downto 0);
qsfp0TxN : out slv(3 downto 0);
-- QSFP[1] Ports
qsfp1RefClkP : in slv(1 downto 0);
qsfp1RefClkN : in slv(1 downto 0);
qsfp1RxP : in slv(3 downto 0);
qsfp1RxN : in slv(3 downto 0);
qsfp1TxP : out slv(3 downto 0);
qsfp1TxN : out slv(3 downto 0));
end EthPhyWrapper;
architecture mapping of EthPhyWrapper is
constant NUM_AXI_MASTERS_C : natural := 16;
constant AXI_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXI_MASTERS_C-1 downto 0) := genAxiLiteConfig(NUM_AXI_MASTERS_C, AXI_BASE_ADDR_G, 16, 12);
signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXI_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C);
signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXI_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C);
signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXI_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C);
signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXI_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C);
signal phyIbMasters : AxiStreamMasterArray(7 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
signal phyIbSlaves : AxiStreamSlaveArray(7 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C);
signal phyObMasters : AxiStreamMasterArray(7 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
signal phyObSlaves : AxiStreamSlaveArray(7 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C);
signal mac : Slv48Array(7 downto 0) := (others => (others => '0'));
signal ip : Slv32Array(7 downto 0) := (others => (others => '0'));
signal axilReset : sl;
signal gtTxPreCursor : Slv5Array(7 downto 0);
signal gtTxPostCursor : Slv5Array(7 downto 0);
signal gtTxDiffCtrl : Slv4Array(7 downto 0);
signal phyToUdpRoute : Slv8Array(7 downto 0);
signal dmaClk : slv(7 downto 0);
signal dmaRst : slv(7 downto 0);
signal axiLiteClk : slv(7 downto 0);
signal axiLiteRst : slv(7 downto 0);
signal refClk : slv(1 downto 0);
attribute dont_touch : string;
attribute dont_touch of refClk : signal is "TRUE";
begin
dmaClk <= (others => axilClk);
dmaRst <= (others => axilReset);
axiLiteClk <= (others => axilClk);
axiLiteRst <= (others => axilReset);
-------------------------------
-- TODO: Add routing logic here
-------------------------------
localMac <= mac(NUM_RSSI_C-1 downto 0);
localIp <= ip(NUM_RSSI_C-1 downto 0);
udpIbMasters <= phyObMasters(NUM_RSSI_C-1 downto 0);
phyObSlaves(NUM_RSSI_C-1 downto 0) <= udpIbSlaves;
phyIbMasters(NUM_RSSI_C-1 downto 0) <= udpObMasters;
udpObSlaves <= phyIbSlaves(NUM_RSSI_C-1 downto 0);
-- ROUTE_TABLE : process (udpToPhyRoute) is
-- variable route : Slv8Array(7 downto 0);
-- begin
-- -- Init
-- route := (others => x"FF");
-- -- Create the PHY-to-UDP route table
-- for i in NUM_RSSI_C-1 downto 0 loop
-- route(conv_integer(udpToPhyRoute(i))) := toSlv(i, 8);
-- end loop;
-- -- Outputs
-- phyToUdpRoute <= route;
-- end process;
-- process(axilClk)
-- begin
-- if rising_edge(axilClk) then
-- for i in 7 downto 0 loop
-- if phyToUdpRoute(i) /= x"FF" then
-- localMac(conv_integer(phyToUdpRoute(i))) <= mac(i) after TPD_G;
-- localIp(conv_integer(phyToUdpRoute(i))) <= ip(i) after TPD_G;
-- end if;
-- end loop;
-- end if;
-- end process;
-- U_IbRouter : entity work.AxiStreamRouter
-- generic map (
-- TPD_G => TPD_G,
-- NUM_SLAVES_G => 8,
-- NUM_MASTERS_G => NUM_RSSI_C,
-- SLAVES_PIPE_STAGES_G => 1,
-- MASTERS_PIPE_STAGES_G => 1)
-- port map (
-- -- Clock and reset
-- axisClk => axilClk,
-- axisRst => axilReset,
-- -- Routing Configuration
-- routeConfig => phyToUdpRoute,
-- -- Slave Interfaces
-- sAxisMasters => phyObMasters,
-- sAxisSlaves => phyObSlaves,
-- -- Master Interfaces
-- mAxisMasters => udpIbMasters,
-- mAxisSlaves => udpIbSlaves);
-- U_ObRouter : entity work.AxiStreamRouter
-- generic map (
-- TPD_G => TPD_G,
-- NUM_SLAVES_G => NUM_RSSI_C,
-- NUM_MASTERS_G => 8,
-- SLAVES_PIPE_STAGES_G => 1,
-- MASTERS_PIPE_STAGES_G => 1)
-- port map (
-- -- Clock and reset
-- axisClk => axilClk,
-- axisRst => axilReset,
-- -- Routing Configuration
-- routeConfig => udpToPhyRoute,
-- -- Slave Interfaces
-- sAxisMasters => udpObMasters,
-- sAxisSlaves => udpObSlaves,
-- -- Master Interfaces
-- mAxisMasters => phyIbMasters,
-- mAxisSlaves => phyIbSlaves);
-----------------
-- Reset Pipeline
-----------------
U_axilRst : entity surf.RstPipeline
generic map (
TPD_G => TPD_G)
port map (
clk => axilClk,
rstIn => axilRst,
rstOut => axilReset);
---------------------
-- AXI-Lite Crossbar
---------------------
U_XBAR : entity surf.AxiLiteCrossbar
generic map (
TPD_G => TPD_G,
NUM_SLAVE_SLOTS_G => 1,
NUM_MASTER_SLOTS_G => NUM_AXI_MASTERS_C,
MASTERS_CONFIG_G => AXI_CONFIG_C)
port map (
axiClk => axilClk,
axiClkRst => axilReset,
sAxiWriteMasters(0) => axilWriteMaster,
sAxiWriteSlaves(0) => axilWriteSlave,
sAxiReadMasters(0) => axilReadMaster,
sAxiReadSlaves(0) => axilReadSlave,
mAxiWriteMasters => axilWriteMasters,
mAxiWriteSlaves => axilWriteSlaves,
mAxiReadMasters => axilReadMasters,
mAxiReadSlaves => axilReadSlaves);
----------------
-- 10GigE Module
----------------
U_QSFP0 : entity surf.TenGigEthGthUltraScaleWrapper
generic map (
TPD_G => TPD_G,
NUM_LANE_G => 4,
EN_AXI_REG_G => true,
-- AXI Streaming Configurations
AXIS_CONFIG_G => (others => EMAC_AXIS_CONFIG_C))
port map (
-- Local Configurations
localMac => mac(3 downto 0),
-- Streaming DMA Interface
dmaClk => dmaClk(3 downto 0),
dmaRst => dmaRst(3 downto 0),
dmaIbMasters => phyObMasters(3 downto 0),
dmaIbSlaves => phyObSlaves(3 downto 0),
dmaObMasters => phyIbMasters(3 downto 0),
dmaObSlaves => phyIbSlaves(3 downto 0),
-- Slave AXI-Lite Interface
axiLiteClk => axiLiteClk(3 downto 0),
axiLiteRst => axiLiteRst(3 downto 0),
axiLiteReadMasters => axilReadMasters(3 downto 0),
axiLiteReadSlaves => axilReadSlaves(3 downto 0),
axiLiteWriteMasters => axilWriteMasters(3 downto 0),
axiLiteWriteSlaves => axilWriteSlaves(3 downto 0),
-- Misc. Signals
extRst => axilReset,
-- Transceiver Debug Interface
-- gtTxPreCursor => gtTxPreCursor(3 downto 0),
-- gtTxPostCursor => gtTxPostCursor(3 downto 0),
-- gtTxDiffCtrl => gtTxDiffCtrl(3 downto 0),
-- MGT Clock Port
gtClkP => qsfp0RefClkP(0),
gtClkN => qsfp0RefClkN(0),
-- MGT Ports
gtTxP => qsfp0TxP,
gtTxN => qsfp0TxN,
gtRxP => qsfp0RxP,
gtRxN => qsfp0RxN);
U_QSFP1 : entity surf.TenGigEthGthUltraScaleWrapper
generic map (
TPD_G => TPD_G,
NUM_LANE_G => 4,
EN_AXI_REG_G => true,
-- AXI Streaming Configurations
AXIS_CONFIG_G => (others => EMAC_AXIS_CONFIG_C))
port map (
-- Local Configurations
localMac => mac(7 downto 4),
-- Streaming DMA Interface
dmaClk => dmaClk(7 downto 4),
dmaRst => dmaRst(7 downto 4),
dmaIbMasters => phyObMasters(7 downto 4),
dmaIbSlaves => phyObSlaves(7 downto 4),
dmaObMasters => phyIbMasters(7 downto 4),
dmaObSlaves => phyIbSlaves(7 downto 4),
-- Slave AXI-Lite Interface
axiLiteClk => axiLiteClk(7 downto 4),
axiLiteRst => axiLiteRst(7 downto 4),
axiLiteReadMasters => axilReadMasters(7 downto 4),
axiLiteReadSlaves => axilReadSlaves(7 downto 4),
axiLiteWriteMasters => axilWriteMasters(7 downto 4),
axiLiteWriteSlaves => axilWriteSlaves(7 downto 4),
-- Misc. Signals
extRst => axilReset,
-- Transceiver Debug Interface
-- gtTxPreCursor => gtTxPreCursor(7 downto 4),
-- gtTxPostCursor => gtTxPostCursor(7 downto 4),
-- gtTxDiffCtrl => gtTxDiffCtrl(7 downto 4),
-- MGT Clock Port
gtClkP => qsfp1RefClkP(0),
gtClkN => qsfp1RefClkN(0),
-- MGT Ports
gtTxP => qsfp1TxP,
gtTxN => qsfp1TxN,
gtRxP => qsfp1RxP,
gtRxN => qsfp1RxN);
-- U_QSFP1 : entity surf.TenGigEthGthUltraScaleWrapper
-- generic map (
-- TPD_G => TPD_G,
-- NUM_LANE_G => 2,
-- EN_AXI_REG_G => true,
-- -- AXI Streaming Configurations
-- AXIS_CONFIG_G => (others => EMAC_AXIS_CONFIG_C))
-- port map (
-- -- Local Configurations
-- localMac => mac(5 downto 4),
-- -- Streaming DMA Interface
-- dmaClk => dmaClk(5 downto 4),
-- dmaRst => dmaRst(5 downto 4),
-- dmaIbMasters => phyObMasters(5 downto 4),
-- dmaIbSlaves => phyObSlaves(5 downto 4),
-- dmaObMasters => phyIbMasters(5 downto 4),
-- dmaObSlaves => phyIbSlaves(5 downto 4),
-- -- Slave AXI-Lite Interface
-- axiLiteClk => axiLiteClk(5 downto 4),
-- axiLiteRst => axiLiteRst(5 downto 4),
-- axiLiteReadMasters => axilReadMasters(5 downto 4),
-- axiLiteReadSlaves => axilReadSlaves(5 downto 4),
-- axiLiteWriteMasters => axilWriteMasters(5 downto 4),
-- axiLiteWriteSlaves => axilWriteSlaves(5 downto 4),
-- -- Misc. Signals
-- extRst => axilReset,
-- -- MGT Clock Port
-- gtClkP => qsfp1RefClkP(0),
-- gtClkN => qsfp1RefClkN(0),
-- -- MGT Ports
-- gtTxP => qsfp1TxP(1 downto 0),
-- gtTxN => qsfp1TxN(1 downto 0),
-- gtRxP => qsfp1RxP(1 downto 0),
-- gtRxN => qsfp1RxN(1 downto 0));
-- U_GTH_TERM : entity surf.Gthe3ChannelDummy
-- generic map (
-- TPD_G => TPD_G,
-- WIDTH_G => 2)
-- port map (
-- refClk => axilRst,
-- gtTxP => qsfp1TxP(3 downto 2),
-- gtTxN => qsfp1TxN(3 downto 2),
-- gtRxP => qsfp1RxP(3 downto 2),
-- gtRxN => qsfp1RxN(3 downto 2));
--------------------
-- Unused GTH Clocks
--------------------
U_QsfpRef0 : IBUFDS_GTE3
port map (
I => qsfp0RefClkP(1),
IB => qsfp0RefClkN(1),
CEB => '0',
O => refClk(0));
U_QsfpRef1 : IBUFDS_GTE3
port map (
I => qsfp1RefClkP(1),
IB => qsfp1RefClkN(1),
CEB => '0',
O => refClk(1));
GEN_VEC : for i in 7 downto 0 generate
U_EthConfig : entity work.EthConfig
generic map (
TPD_G => TPD_G)
port map (
localIp => ip(i),
localMac => mac(i),
gtTxPreCursor => gtTxPreCursor(i),
gtTxPostCursor => gtTxPostCursor(i),
gtTxDiffCtrl => gtTxDiffCtrl(i),
-- AXI-Lite Register Interface (axilClk domain)
axilClk => axilClk,
axilRst => axilReset,
axilReadMaster => axilReadMasters(i+8),
axilReadSlave => axilReadSlaves(i+8),
axilWriteMaster => axilWriteMasters(i+8),
axilWriteSlave => axilWriteSlaves(i+8));
end generate GEN_VEC;
end mapping;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Data memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "data.mem"
entity DRAM is
generic (
RAM_DEPTH : natural := 4096;
I_SIZE : integer := 32);
port (
Clk : in std_logic;
Rst : in std_logic;
Enable : in std_logic;
WR : in std_logic;
Din : in std_logic_vector(I_SIZE - 1 downto 0);
Addr : in std_logic_vector(I_SIZE - 1 downto 0);
Dout : out std_logic_vector(I_SIZE - 1 downto 0)
);
end DRAM;
architecture DRam_Bhe of DRAM is
type RAMtype is array (0 to RAM_DEPTH - 1) of std_logic_vector(I_SIZE - 1 downto 0);-- std_logic_vector(I_SIZE - 1 downto 0);
signal DRAM_mem : RAMtype;
begin -- DRam_Bhe
-- Dout <= DRAM_mem(to_integer(unsigned(Addr))/4) when WR = '0' and Enable = '1' else (others => 'Z');
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
-- type : combinational
-- inputs : Rst
-- outputs: DRAM_mem
FILL_MEM_P: process (Rst,Clk)
file mem_fp2: text;
variable file_line2 : line;
variable index2 : integer := 0;
variable tmp_data_u2 : std_logic_vector(I_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (Rst = '1') then
file_open(mem_fp2,"DLX_vhd/test_bench/data.mem",READ_MODE);
report "RESETTT:";
while (not endfile(mem_fp2)) loop
readline(mem_fp2,file_line2);
hread(file_line2,tmp_data_u2);
DRAM_mem(index2) <= tmp_data_u2;
index2 := index2 + 1;
end loop;
else
if(clk'event and clk = '0') then
if(Enable = '1' and Wr = '1') then
DRAM_mem(to_integer(unsigned(Addr))/4) <= Din;
report "i = " & integer'image(to_integer(unsigned(Addr)));
elsif ( Enable = '1' and WR='0' ) then
Dout <= DRAM_mem(to_integer(unsigned(Addr))/4);
end if;
end if;
end if;
end process FILL_MEM_P;
end DRam_Bhe;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "ipbus_ctrl"
-- Project :
-------------------------------------------------------------------------------
-- File : ipbus_ctrl_tb.vhd
-- Author : <NAME> <<EMAIL>>
-- Company :
-- Created : 2016-06-07
-- Last update: 2016-06-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-06-07 1.0 wzab Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.ipbus.all;
library work;
-------------------------------------------------------------------------------
entity ipbus_ctrl_tb is
end entity ipbus_ctrl_tb;
-------------------------------------------------------------------------------
architecture rtl of ipbus_ctrl_tb is
-- component generics
constant rdpipename : string := "/tmp/rdpipe";
constant wrpipename : string := "/tmp/wrpipe";
-- component ports
signal ipb_out : ipb_wbus;
signal ipb_in : ipb_rbus;
signal ipb_clk : std_logic;
signal ipb_rst : std_logic := '1';
signal ipb_addr : std_logic_vector (31 downto 0);
signal ipb_wdata : std_logic_vector (31 downto 0);
signal ipb_strobe : std_logic;
signal ipb_write : std_logic;
signal ipb_rdata : std_logic_vector (31 downto 0);
signal ipb_ack : std_logic;
signal ipb_err : std_logic;
signal leds : std_logic_vector(2 downto 0);
-- clock
signal Clk : std_logic := '1';
begin -- architecture rtl
-- component instantiation
DUT: entity work.ipbus_ctrl
generic map (
rdpipename => rdpipename,
wrpipename => wrpipename)
port map (
ipb_out => ipb_out,
ipb_in => ipb_in,
ipb_clk => ipb_clk);
slaves_1: entity work.slaves
port map (
ipb_clk => ipb_clk,
ipb_rst => ipb_rst,
ipb_addr => ipb_addr,
ipb_wdata => ipb_wdata,
ipb_strobe => ipb_strobe,
ipb_write => ipb_write,
ipb_rdata => ipb_rdata,
ipb_ack => ipb_ack,
ipb_err => ipb_err,
leds => leds);
ipb_clk <= Clk;
-- Mapping of signals from the "flattened" IP-bus implementation
ipb_addr <= ipb_out.ipb_addr;
ipb_wdata <= ipb_out.ipb_wdata;
ipb_strobe <= ipb_out.ipb_strobe;
ipb_write <= ipb_out.ipb_write;
ipb_in.ipb_rdata <= ipb_rdata;
ipb_in.ipb_ack <= ipb_ack;
ipb_in.ipb_err <= ipb_err;
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
wait until Clk = '1';
wait for 15 ns;
ipb_rst <= '0';
end process WaveGen_Proc;
end architecture rtl;
-------------------------------------------------------------------------------
|
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