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<filename>rtl/periph/ps2kc.vhd
-- Copyright (c) 2015, $ME
-- All rights reserved.
--
-- Redistribution and use in source and synthezised forms, with or without modification, are permitted
-- provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions
-- and the following disclaimer.
--
-- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions
-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-- WARRANTIES, INCLUDING, BUT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT LIMITED
-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-- MiSTer PS/2 inputs -> KC87 Keymatrix
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ps2kc is
port (
clk : in std_logic;
res_n : in std_logic;
scancode : in std_logic_vector(7 downto 0);
scanstate : in std_logic;
rcvd : in std_logic;
matrixXin : in std_logic_vector(7 downto 0);
matrixXout : out std_logic_vector(7 downto 0);
matrixYin : in std_logic_vector(7 downto 0);
matrixYout : out std_logic_vector(7 downto 0);
joystick_0 : in std_logic_vector(31 downto 0);
joystick_1 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of ps2kc is
type keyMatrixType is array(8 downto 1) of std_logic_vector(8 downto 1);
-- init mit 1 funktioniert in ise nicht, Quartus kanns :P
signal keyMatrix : keyMatrixType := (others => (others => '1'));
signal joystick_0_old : std_logic_vector(31 downto 0) := (others => '0');
signal joystick_1_old : std_logic_vector(31 downto 0) := (others => '0');
begin
-- ps/2-codes in eine 8x8 matrix umkopieren die weitgehend der des kc entspricht
process(clk, scancode, rcvd, matrixXin, matrixYin, keyMatrix)
begin
if rising_edge(clk) then
if (rcvd='1') then
case scancode is
--- Zeile 1
when x"45" => keyMatrix(1)(1) <= scanstate; -- 0 (_) => (0 =)
when x"16" => keyMatrix(1)(2) <= scanstate; -- 1 !
when x"1e" => keyMatrix(1)(3) <= scanstate; -- 2 "
when x"26" => keyMatrix(1)(4) <= scanstate; -- 3 (#) => (3 §)
when x"25" => keyMatrix(1)(5) <= scanstate; -- 4 $
when x"2e" => keyMatrix(1)(6) <= scanstate; -- 5 %
when x"36" => keyMatrix(1)(7) <= scanstate; -- 6 &
when x"3d" => keyMatrix(1)(8) <= scanstate; -- 7 (') => (7 /)
--- Zeile 2
when x"3e" => keyMatrix(2)(1) <= scanstate; -- 8 (
when x"46" => keyMatrix(2)(2) <= scanstate; -- 9 )
when x"61" => keyMatrix(2)(3) <= scanstate; -- : * => (< >)
when x"5b" => keyMatrix(2)(4) <= scanstate; -- ; + => (+ *)
when x"41" => keyMatrix(2)(5) <= scanstate; -- , < => (, ;)
when x"4a" => keyMatrix(2)(6) <= scanstate; -- = - => (- _)
when x"49" => keyMatrix(2)(7) <= scanstate; -- . > => (. :)
when x"4e" => keyMatrix(2)(8) <= scanstate; -- ? / => (ß ?)
--- Zeile 3
-- @
when x"1c" => keyMatrix(3)(2) <= scanstate; -- A
when x"32" => keyMatrix(3)(3) <= scanstate; -- B
when x"21" => keyMatrix(3)(4) <= scanstate; -- C
when x"23" => keyMatrix(3)(5) <= scanstate; -- D
when x"24" => keyMatrix(3)(6) <= scanstate; -- E
when x"2b" => keyMatrix(3)(7) <= scanstate; -- F
when x"34" => keyMatrix(3)(8) <= scanstate; -- G
--- Zeile 4
when x"33" => keyMatrix(4)(1) <= scanstate; -- H
when x"43" => keyMatrix(4)(2) <= scanstate; -- I
when x"3b" => keyMatrix(4)(3) <= scanstate; -- J
when x"42" => keyMatrix(4)(4) <= scanstate; -- K
when x"4b" => keyMatrix(4)(5) <= scanstate; -- L
when x"3a" => keyMatrix(4)(6) <= scanstate; -- M
when x"31" => keyMatrix(4)(7) <= scanstate; -- N
when x"44" => keyMatrix(4)(8) <= scanstate; -- O
--- Zeile 5
when x"4d" => keyMatrix(5)(1) <= scanstate; -- P
when x"15" => keyMatrix(5)(2) <= scanstate; -- Q
when x"2d" => keyMatrix(5)(3) <= scanstate; -- R
when x"1b" => keyMatrix(5)(4) <= scanstate; -- S
when x"2c" => keyMatrix(5)(5) <= scanstate; -- T
when x"3c" => keyMatrix(5)(6) <= scanstate; -- U
when x"2a" => keyMatrix(5)(7) <= scanstate; -- V
when x"1d" => keyMatrix(5)(8) <= scanstate; -- W
--- Zeile 6
when x"22" => keyMatrix(6)(1) <= scanstate; -- X
when x"1a" => keyMatrix(6)(2) <= scanstate; -- Y
when x"35" => keyMatrix(6)(3) <= scanstate; -- Z
when x"0d" => keyMatrix(6)(4) <= scanstate; -- Tab
when x"05" => keyMatrix(6)(5) <= scanstate; -- Pause Cont => (F1)
when x"70" => keyMatrix(6)(6) <= scanstate; -- INS DEL => (Einfg)
when x"0e" => keyMatrix(6)(7) <= scanstate; -- ^
when x"71" => keyMatrix(6)(8) <= scanstate; -- (Entf) => DEL
when x"66" => keyMatrix(6)(8) <= scanstate; -- (Backspace) => DEL
--- Zeile 7
when x"6b" => keyMatrix(7)(1) <= scanstate; -- Cursor <-
when x"74" => keyMatrix(7)(2) <= scanstate; -- Cursor ->
when x"72" => keyMatrix(7)(3) <= scanstate; -- Cursor down
when x"75" => keyMatrix(7)(4) <= scanstate; -- Cursor up
when x"76" => keyMatrix(7)(5) <= scanstate; -- ESC
when x"5a" => keyMatrix(7)(6) <= scanstate; -- Enter
when x"0c" => keyMatrix(7)(7) <= scanstate; -- Stop => F4
when x"29" => keyMatrix(7)(8) <= scanstate; -- Space
--- Zeile 8
-- (8)(1) Shift
when x"59" => keyMatrix(8)(1) <= scanstate; -- rshift
when x"12" => keyMatrix(8)(1) <= scanstate; -- lshift
when x"03" => keyMatrix(8)(2) <= scanstate; -- Color => (F5)
when x"14" => keyMatrix(8)(3) <= scanstate; -- Contr
when x"0b" => keyMatrix(8)(4) <= scanstate; -- Graphic => (F6)
when x"06" => keyMatrix(8)(5) <= scanstate; -- List => (F2)
when x"04" => keyMatrix(8)(6) <= scanstate; -- Run => (F3)
when x"58" => keyMatrix(8)(7) <= scanstate; -- Shift Lock
when x"5d" => keyMatrix(8)(8) <= scanstate; -- => (# ')
when others =>null;
end case;
else
-- joystick
if joystick_0_old /= joystick_0 then
keyMatrix(7)(1) <= not joystick_0(1); -- joystick 1 left
keyMatrix(7)(2) <= not joystick_0(0); -- joystick 1 right
keyMatrix(7)(3) <= not joystick_0(2); -- joystick 1 down
keyMatrix(7)(4) <= not joystick_0(3); -- joystick 1 up
keyMatrix(7)(5) <= not joystick_0(4); -- joystick 1 fire
end if;
joystick_0_old <= joystick_0;
if joystick_1_old /= joystick_1 then
keyMatrix(8)(1) <= not joystick_1(1); -- joystick 2 left
keyMatrix(8)(2) <= not joystick_1(0); -- joystick 2 right
keyMatrix(8)(3) <= not joystick_1(2); -- joystick 2 down
keyMatrix(8)(4) <= not joystick_1(3); -- joystick 2 up
keyMatrix(8)(5) <= not joystick_1(4); -- joystick 2 fire
end if;
joystick_1_old <= joystick_1;
end if;
end if;
-- matrix zeilen und spalten fuer pio kombinieren
for i in 0 to 7 loop
matrixXout(i) <= (keyMatrix(1)(i+1) or matrixYin(0))
and (keyMatrix(2)(i+1) or matrixYin(1))
and (keyMatrix(3)(i+1) or matrixYin(2))
and (keyMatrix(4)(i+1) or matrixYin(3))
and (keyMatrix(5)(i+1) or matrixYin(4))
and (keyMatrix(6)(i+1) or matrixYin(5))
and (keyMatrix(7)(i+1) or matrixYin(6))
and (keyMatrix(8)(i+1) or matrixYin(7));
if ((keyMatrix(i+1) or matrixXin)="11111111") then
matrixYout(i) <= '1';
else
matrixYout(i) <= '0';
end if;
end loop;
end process;
end;
|
<reponame>MaxIV-KitsControls/PandABlocks-FPGA<filename>targets/PandABox/SlowFPGA/src/hdl/temp_sensors.vhd<gh_stars>0
--------------------------------------------------------------------------------
-- PandA Motion Project - 2016
-- Diamond Light Source, Oxford, UK
-- SOLEIL Synchrotron, GIF-sur-YVETTE, France
--
-- Author : Dr. <NAME> (<EMAIL>)
--------------------------------------------------------------------------------
--
-- Description : Read I2C temperature sensors in loop.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.top_defines.all;
use work.support.all;
use work.addr_defines.all;
entity temp_sensors is
port (
-- 50MHz system clock
clk_i : in std_logic;
reset_i : in std_logic;
-- I2C Interface
sda : inout std_logic;
scl : inout std_logic;
-- Status registers
TEMP_MON : out std32_array(4 downto 0)
);
end temp_sensors;
architecture rtl of temp_sensors is
type i2c_fsm_t is (INIT, READ_DATA, NEXT_SLAVE);
-- Array of Slave addresses
constant SLAVE_ARRAY : std8_array(4 downto 0) := (
"01001100",
"01001011",
"01001010",
"01001001",
"01001000");
signal i2c_fsm : i2c_fsm_t;
signal busy_prev : std_logic;
signal i2c_ena : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_rw : std_logic;
signal i2c_data_wr : std_logic_vector(7 downto 0);
signal i2c_busy : std_logic;
signal i2c_data_rd : std_logic_vector(7 downto 0);
signal i2c_ack_error : std_logic;
signal i2c_rise : std_logic;
signal data_rd : std_logic_vector(15 downto 0);
signal i2c_start : std_logic;
signal sda_din : std_logic;
signal scl_din : std_logic;
signal sda_t : std_logic;
signal scl_t : std_logic;
component icon
port (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)
);
end component;
component ila
port (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal DATA : STD_LOGIC_VECTOR(63 DOWNTO 0);
signal TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal slave_index : natural range 0 to 4;
begin
--------------------------------------------------------------------
-- 3-state I2C I/O Buffers
--------------------------------------------------------------------
iobuf_scl : iobuf
port map (
I => '0',
O => scl_din,
IO => scl,
T => scl_t
);
iobuf_sda : iobuf
port map (
I => '0',
O => sda_din,
IO => sda,
T => sda_t
);
-- Generate Internal from system clock
start_presc : entity work.prescaler
port map (
clk_i => clk_i,
reset_i => reset_i,
PERIOD => TO_SVECTOR(50_000_000,32), -- 1sec
pulse_o => i2c_start
);
i2c_master_inst : entity work.i2c_master
generic map (
input_clk => 50_000_000,
bus_clk => 10_000
)
port map (
clk => clk_i,
reset => reset_i,
ena => i2c_ena,
addr => i2c_addr,
rw => i2c_rw,
data_wr => i2c_data_wr,
busy => i2c_busy,
data_rd => i2c_data_rd,
ack_error => i2c_ack_error,
sda => sda_din,
scl => scl_din,
sda_t => sda_t,
scl_t => scl_t
);
--------------------------------------------------------------------
-- Main read state machine loops through all SLAVES
--------------------------------------------------------------------
i2c_rise <= i2c_busy and not busy_prev;
process(clk_i)
variable busy_cnt : natural range 0 to 3;
begin
if rising_edge(clk_i) then
if (reset_i = '1') then
i2c_fsm <= INIT;
slave_index <= 0;
busy_cnt := 0;
busy_prev <= '1';
i2c_rw <= '1';
i2c_ena <= '0';
i2c_addr <= (others => '0');
i2c_data_wr <= X"00";
data_rd <= (others => '0');
TEMP_MON <= (others => (others => '0'));
else
busy_prev <= i2c_busy;
case (i2c_fsm) is
-- Wait for 1 sec to start
when INIT =>
if (i2c_busy = '0' and i2c_start = '1') then
i2c_fsm <= READ_DATA;
end if;
-- Pointer register defaults to temperature reg. So,
-- directly Read i2 bytes from the current slave
when READ_DATA =>
if (i2c_rise = '1') then
busy_cnt := busy_cnt + 1;
end if;
case busy_cnt is
-- Initiate the transaction by writing to
-- pointer register.
-- '0' is write, '1' is read
when 0 =>
i2c_ena <= '1';
i2c_addr <= SLAVE_ARRAY(slave_index)(6 downto 0);
i2c_rw <= '1'; -- read
when 1 =>
if (i2c_busy = '0') then
data_rd(15 downto 8) <= i2c_data_rd;
end if;
when 2 =>
i2c_ena <= '0';
if (i2c_busy = '0') then
data_rd(7 downto 0) <= i2c_data_rd;
busy_cnt := 0;
i2c_fsm <= NEXT_SLAVE;
end if;
when others => NULL;
end case;
-- Latch read data and move to next slave
when NEXT_SLAVE =>
if (i2c_start = '1') then
if (slave_index = 4) then
slave_index <= 0;
else
slave_index <= slave_index + 1;
end if;
i2c_fsm <= READ_DATA;
end if;
-- Latch and sign convert sensor data. It has 0.5C
-- resolution
TEMP_MON(slave_index) <=
std_logic_vector(resize(signed(data_rd(15 downto 8)), 32));
when others => NULL;
end case;
end if;
end if;
end process;
end rtl;
|
<reponame>lefmylonas/auto_power_systems_simulator<filename>hardware-oriented section/top_level.vhd<gh_stars>1-10
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.PS_SIM_PACKAGE.ALL;
USE WORK.PS_SIM_SUPPORT_PACKAGE.ALL;
ENTITY TOP_LEVEL is
port(rst,clk: in std_logic;
V_s: in matrix(1 to No_Vk, 1 to 1) := (others=>(others=>(others=>'0')));
I_s: in matrix(1 to No_Src-No_Vk, 1 to 1);
Vnodal: out matrix(1 to No_Nodes, 1 to 1);
Ibranch: out matrix(1 to No_Brn, 1 to 1));
END TOP_LEVEL;
ARCHITECTURE arch of TOP_LEVEL is
COMPONENT PS_SIM
port(rst,clk: in std_logic;
V_s: in matrix(1 to No_Vk, 1 to 1) := (others=>(others=>(others=>'0')));
I_s: in matrix(1 to No_Src-No_Vk, 1 to 1);
Vnodal: out matrix(1 to No_Nodes, 1 to 1);
Ibranch: out matrix(1 to No_Brn, 1 to 1));
END COMPONENT;
begin
T1: if (No_Vk /= 0) generate -- Voltage sources are found
U1: entity work.PS_SIM(arch1) port map(rst=>rst,clk=>clk,V_s=>V_s,I_s=>I_s,Vnodal=>Vnodal,Ibranch=>Ibranch);
end generate;
T2: if (No_Vk = 0) generate -- Only current sources are found
U2: entity work.PS_SIM(arch2) port map(rst=>rst,clk=>clk,V_s=>open,I_s=>I_s,Vnodal=>Vnodal,Ibranch=>Ibranch);
end generate;
end arch;
|
<reponame>miguelviladev/laboratorio-de-sistemas-digitais
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY contadorincdecnbitstb IS
END contadorincdecnbitstb;
ARCHITECTURE stimulus OF contadorincdecnbitstb IS
SIGNAL s_resetar, s_incdec, s_entradaclock : STD_LOGIC;
SIGNAL s_contagem : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
uut : ENTITY work.contadorincdecnbits(behavioral)
PORT MAP(
resetar => s_resetar,
incdec => s_incdec,
entradaclock => s_entradaclock,
contagem => s_contagem);
contagem => s_contagem);
PROCESS IS
BEGIN
s_entradaclock <= '0';
WAIT FOR 100 ns;
s_entradaclock <= '1';
WAIT FOR 100 ns;
END PROCESS;
PROCESS IS
BEGIN
s_incdec <= '1';
WAIT FOR 1000 ns;
s_incdec <= '0';
WAIT FOR 1000 ns;
s_incdec <= '1';
WAIT FOR 2000 ns;
s_resetar <= '1';
WAIT FOR 200 ns;
s_resetar <= '0';
WAIT FOR 300 ns;
END PROCESS;
|
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:hls:compute_weight_2:1.0
-- IP Revision: 1904051711
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY compute_weight_compute_weight_2_0_0 IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
input_r_TVALID : IN STD_LOGIC;
input_r_TREADY : OUT STD_LOGIC;
input_r_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
input_r_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
output_r_TVALID : OUT STD_LOGIC;
output_r_TREADY : IN STD_LOGIC;
output_r_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
output_r_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END compute_weight_compute_weight_2_0_0;
ARCHITECTURE compute_weight_compute_weight_2_0_0_arch OF compute_weight_compute_weight_2_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF compute_weight_compute_weight_2_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT compute_weight_2 IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
input_r_TVALID : IN STD_LOGIC;
input_r_TREADY : OUT STD_LOGIC;
input_r_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
input_r_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
output_r_TVALID : OUT STD_LOGIC;
output_r_TREADY : IN STD_LOGIC;
output_r_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
output_r_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT compute_weight_2;
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF compute_weight_compute_weight_2_0_0_arch: ARCHITECTURE IS "HLS";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF output_r_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 output_r TLAST";
ATTRIBUTE X_INTERFACE_INFO OF output_r_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 output_r TDATA";
ATTRIBUTE X_INTERFACE_INFO OF output_r_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 output_r TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF output_r_TVALID: SIGNAL IS "XIL_INTERFACENAME output_r, TDATA_NUM_BYTES 4, TUSER_WIDTH 0, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} TDATA {datatype {name {attribs {resolve_type immediate dependency {}" &
" format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {float {sigwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 24}}}}} TDATA_WIDTH 32}, TDEST_WIDTH 0, TID_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CL" &
"K_DOMAIN compute_weight_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF output_r_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 output_r TVALID";
ATTRIBUTE X_INTERFACE_INFO OF input_r_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 input_r TLAST";
ATTRIBUTE X_INTERFACE_INFO OF input_r_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 input_r TDATA";
ATTRIBUTE X_INTERFACE_INFO OF input_r_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 input_r TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF input_r_TVALID: SIGNAL IS "XIL_INTERFACENAME input_r, TDATA_NUM_BYTES 4, TUSER_WIDTH 0, LAYERED_METADATA undef, TDEST_WIDTH 0, TID_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN compute_weight_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF input_r_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 input_r TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF ap_rst_n: SIGNAL IS "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ap_clk: SIGNAL IS "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF input_r:output_r, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMA" &
"IN compute_weight_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
BEGIN
U0 : compute_weight_2
PORT MAP (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
input_r_TVALID => input_r_TVALID,
input_r_TREADY => input_r_TREADY,
input_r_TDATA => input_r_TDATA,
input_r_TLAST => input_r_TLAST,
output_r_TVALID => output_r_TVALID,
output_r_TREADY => output_r_TREADY,
output_r_TDATA => output_r_TDATA,
output_r_TLAST => output_r_TLAST
);
END compute_weight_compute_weight_2_0_0_arch;
|
<filename>simulation/modelsim/finalproject/finalproject_cpu_jtag_debug_module_wrapper/_primary.vhd
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_jtag_debug_module_wrapper is
port(
MonDReg : in vl_logic_vector(31 downto 0);
break_readreg : in vl_logic_vector(31 downto 0);
clk : in vl_logic;
dbrk_hit0_latch : in vl_logic;
dbrk_hit1_latch : in vl_logic;
dbrk_hit2_latch : in vl_logic;
dbrk_hit3_latch : in vl_logic;
debugack : in vl_logic;
monitor_error : in vl_logic;
monitor_ready : in vl_logic;
reset_n : in vl_logic;
resetlatch : in vl_logic;
tracemem_on : in vl_logic;
tracemem_trcdata: in vl_logic_vector(35 downto 0);
tracemem_tw : in vl_logic;
trc_im_addr : in vl_logic_vector(6 downto 0);
trc_on : in vl_logic;
trc_wrap : in vl_logic;
trigbrktype : in vl_logic;
trigger_state_1 : in vl_logic;
jdo : out vl_logic_vector(37 downto 0);
jrst_n : out vl_logic;
st_ready_test_idle: out vl_logic;
take_action_break_a: out vl_logic;
take_action_break_b: out vl_logic;
take_action_break_c: out vl_logic;
take_action_ocimem_a: out vl_logic;
take_action_ocimem_b: out vl_logic;
take_action_tracectrl: out vl_logic;
take_action_tracemem_a: out vl_logic;
take_action_tracemem_b: out vl_logic;
take_no_action_break_a: out vl_logic;
take_no_action_break_b: out vl_logic;
take_no_action_break_c: out vl_logic;
take_no_action_ocimem_a: out vl_logic;
take_no_action_tracemem_a: out vl_logic
);
end finalproject_cpu_jtag_debug_module_wrapper;
|
---------------------------------------------------------------------------------
-- This is free and unencumbered software released into the public domain.
--
-- Anyone is free to copy, modify, publish, use, compile, sell, or
-- distribute this software, either in source code form or as a compiled
-- binary, for any purpose, commercial or non-commercial, and by any
-- means.
--
-- In jurisdictions that recognize copyright laws, the author or authors
-- of this software dedicate any and all copyright interest in the
-- software to the public domain. We make this dedication for the benefit
-- of the public at large and to the detriment of our heirs and
-- successors. We intend this dedication to be an overt act of
-- relinquishment in perpetuity of all present and future rights to this
-- software under copyright law.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- OTHER DEALINGS IN THE SOFTWARE.
--
-- For more information, please refer to <http://unlicense.org/>
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package can_aximm_pkg is
--generic (
--Package Generics go here.
--);
constant golden_c : std_logic_vector(31 downto 0) := x"A1A2A3A4";
constant C_S_AXI_ADDR_WIDTH : integer := 7;
constant C_S_AXI_DATA_WIDTH : integer := 32;
constant package_version_c : String := "20210528_1505";
component can_aximm_top is
generic (
system_freq : real := 96.0000e+6;
internal_phy : boolean := false
);
port (
mclk_i : in std_logic;
rst_i : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8) - 1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
--Simple IRQs
tx_irq_o : out std_logic;
rx_irq_o : out std_logic;
--external PHY signals
txo_o : out std_logic;
txo_t : out std_logic;
rxi : in std_logic;
--internal phy
can_l : inout std_logic;
can_h : inout std_logic
);
end component;
component can_clk is
generic (
system_freq : real := 96.0000e+6 -- the system frequency
);
port (
mclk_i : in std_logic;
rst_i : in std_logic;
baud_rate_i : in std_logic_vector(11 downto 0); -- baudrate in N x kbps, n = 0...2**12
clk_sync_i : in std_logic;
tx_clken_o : out std_logic;
rx_clken_o : out std_logic;
fb_clken_o : out std_logic
);
end component;
component can_rx is
port (
rst_i : in std_logic;
mclk_i : in std_logic;
rx_clken_i : in std_logic;
fb_clken_i : in std_logic;
--can signals can be bundled in TUSER
usr_eff_o : out std_logic; -- 32 bit can_id + eff/rtr/err flags can_id : in std_logic_vector (31 downto 0);-- 32 bit can_id + eff/rtr/err flags
usr_id_o : out std_logic_vector(28 downto 0); -- 32 bit can_id + eff/rtr/err flags can_id : in std_logic_vector (31 downto 0);-- 32 bit can_id + eff/rtr/err flags
usr_rtr_o : out std_logic; -- 32 bit can_id + eff/rtr/err flags can_id : in std_logic_vector (31 downto 0);-- 32 bit can_id + eff/rtr/err flags
usr_dlc_o : out std_logic_vector(3 downto 0);
usr_rsvd_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(63 downto 0);
data_ready_i : in std_logic;
data_valid_o : out std_logic;
data_last_o : out std_logic;
--status
reg_id_i : in std_logic_vector(28 downto 0);
reg_id_mask_i : in std_logic_vector(28 downto 0);
promiscuous_i : in std_logic;
busy_o : out std_logic;
rx_crc_error_o : out std_logic;
send_ack_o : out std_logic;
--Signals to PHY
ch_ready_i : in std_logic;
collision_i : in std_logic;
rxdata_i : in std_logic
);
end component;
component can_tx is
port (
rst_i : in std_logic;
mclk_i : in std_logic;
tx_clken_i : in std_logic;
--can signals can be bundled in TUSER
usr_eff_i : in std_logic; -- 32 bit can_id + eff/rtr/err flags can_id : in std_logic_vector (31 downto 0);-- 32 bit can_id + eff/rtr/err flags
usr_id_i : in std_logic_vector(28 downto 0); -- 32 bit can_id + eff/rtr/err flags can_id : in std_logic_vector (31 downto 0);-- 32 bit can_id + eff/rtr/err flags
usr_rtr_i : in std_logic; -- 32 bit can_id + eff/rtr/err flags can_id : in std_logic_vector (31 downto 0);-- 32 bit can_id + eff/rtr/err flags
usr_dlc_i : in std_logic_vector(3 downto 0);
usr_rsvd_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(63 downto 0);
data_ready_o : out std_logic;
data_valid_i : in std_logic;
data_last_i : in std_logic;
--status
rtry_error_o : out std_logic;
ack_error_o : out std_logic;
arb_lost_o : out std_logic;
busy_o : out std_logic;
--Signals to PHY
ch_ready_i : in std_logic;
collision_i : in std_logic;
read_ack_i : in std_logic;
txdata_o : out std_logic;
txen_o : out std_logic
);
end component;
component can_phy is
generic (
internal_phy : boolean := false
);
port (
rst_i : in std_logic;
mclk_i : in std_logic;
--configs
force_error_i : in std_logic;
lock_dominant_i : in std_logic;
loopback_i : in std_logic;
--stats
stuff_violation_o : out std_logic;
collision_o : out std_logic;
channel_ready_o : out std_logic;
--commands
read_ack_o : out std_logic;
send_ack_i : in std_logic;
-- data channel;
tx_clken_i : in std_logic;
rx_clken_i : in std_logic;
fb_clken_i : in std_logic;
tx_i : in std_logic;
tx_en_i : in std_logic;
rx_o : out std_logic;
rx_sync_o : out std_logic;
--external PHY
txo_o : out std_logic;
txo_t : out std_logic;
rxi : in std_logic;
--internal phy
can_l : inout std_logic;
can_h : inout std_logic
);
end component;
component can_aximm is
generic (
C_S_AXI_ADDR_WIDTH : integer := 7;
C_S_AXI_DATA_WIDTH : integer := 32
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8) - 1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
g1_i : in std_logic_vector(31 downto 0);
iso_mode_o : out std_logic;
fd_enable_o : out std_logic;
promiscuous_o : out std_logic;
sample_rate_o : out std_logic_vector(15 downto 0);
rx_data_irq_i : in std_logic;
rx_error_irq_i : in std_logic;
tx_data_irq_i : in std_logic;
tx_error_irq_i : in std_logic;
rx_data_mask_o : out std_logic;
rx_error_mask_o : out std_logic;
tx_data_mask_o : out std_logic;
tx_error_mask_o : out std_logic;
stuff_violation_i : in std_logic;
collision_i : in std_logic;
channel_ready_i : in std_logic;
loop_enable_o : out std_logic;
insert_error_o : out std_logic;
force_dominant_o : out std_logic;
rx_data_valid_i : in std_logic;
rx_read_done_o : out std_logic;
rx_busy_i : in std_logic;
rx_crc_error_i : in std_logic;
rx_rtr_i : in std_logic;
rx_ide_i : in std_logic;
rx_reserved_i : in std_logic_vector(1 downto 0);
id1_o : out std_logic_vector(28 downto 0);
id1_mask_o : out std_logic_vector(28 downto 0);
rx_size_i : in std_logic_vector(3 downto 0);
rx_id_i : in std_logic_vector(28 downto 0);
rx_data0_i : in std_logic_vector(31 downto 0);
rx_data1_i : in std_logic_vector(31 downto 0);
tx_ready_i : in std_logic;
tx_valid_o : out std_logic;
tx_busy_i : in std_logic;
tx_arb_lost_i : in std_logic;
tx_retry_error_i : in std_logic;
tx_rtr_o : out std_logic;
tx_eff_o : out std_logic;
tx_reserved_o : out std_logic_vector(1 downto 0);
tx_dlc_o : out std_logic_vector(3 downto 0);
tx_id_o : out std_logic_vector(28 downto 0);
tx_data0_o : out std_logic_vector(31 downto 0);
tx_data1_o : out std_logic_vector(31 downto 0)
);
end component;
procedure crc15(vector : inout std_logic_vector(14 downto 0); input : in std_logic);
--procedure crc15( signal vector : inout std_logic_vector(14 downto 0); input : in std_logic);
end can_aximm_pkg;
package body can_aximm_pkg is
procedure crc15(vector : inout std_logic_vector(14 downto 0); input : in std_logic) is
variable crc_v : std_logic_vector(15 downto 0);
begin
--input and shift
crc_v(15 downto 1) := vector;
--xor
crc_v(0) := crc_v(15) xor crc_v(14) xor crc_v(10) xor crc_v(8) xor crc_v(7) xor crc_v(4) xor crc_v(3) xor input;
--output
vector := crc_v(14 downto 0);
end procedure;
-- procedure crc15( signal vector : inout std_logic_vector(14 downto 0); input : in std_logic) is
-- variable crc_v : std_logic_vector(14 downto 0);
-- begin
-- crc_v := vector;
-- crc15(crc_v,input);
-- vector <= crc_v;
-- end procedure;
end package body;
|
--------------------------------------------------------------------------------
-- This file is part of the ParaNut project.
--
-- Copyright (C) 2013-2019 <NAME> <<EMAIL>>
-- <NAME>, <<EMAIL>>
-- Hochschule Augsburg, University of Applied Sciences
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation and/or
-- other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Description:
-- ParaNut top level module. Contains EXU, LSU, IFU, MEMU.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library paranut;
use paranut.paranut_pkg.all;
use paranut.paranut_config.all;
use paranut.types.all;
use paranut.memu.all;
use paranut.memu_lib.all;
use paranut.ifu.all;
use paranut.lsu.all;
use paranut.exu.all;
use paranut.dbg.all;
use paranut.intc.all;
-- pragma translate_off
use paranut.text_io.all;
use paranut.txt_util.all;
use paranut.tb_monitor.all;
-- pragma translate_on
entity mparanut is
generic (
-- CFG_NUT_CPU_CORES : integer := 1;
-- CFG_MEMU_CACHE_BANKS : integer := 1
CLK_FREQ_HZ : integer := 100_000_000
);
port (
-- Ports (WISHBONE master)
clk_i : in std_logic;
rst_i : in std_logic;
ack_i : in std_logic; -- normal termination
err_i : in std_logic; -- termination w/ error
rty_i : in std_logic; -- termination w/ retry
dat_i : in std_logic_vector(CFG_MEMU_BUSIF_WIDTH-1 downto 0); -- input data bus
cyc_o : out std_logic; -- cycle valid output
stb_o : out std_logic; -- strobe output
we_o : out std_logic; -- indicates write transfer
sel_o : out std_logic_vector((CFG_MEMU_BUSIF_WIDTH/8)-1 downto 0); -- byte select outputs
adr_o : out TWord; -- address bus outputs
dat_o : out std_logic_vector(CFG_MEMU_BUSIF_WIDTH-1 downto 0); -- output data bus
cti_o : out std_logic_vector(2 downto 0); -- cycle type identifier
bte_o : out std_logic_vector(1 downto 0); -- burst type extension
-- Other
du_stall : in std_logic;
ex_int : in std_logic_vector(CFG_NUT_EX_INT-1 downto 0);
-- JTAG
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic
);
end mparanut;
architecture RTL of mparanut is
-- MEMU: busif, read ports (rp), write ports (wp)
signal mi : memu_in_type;
signal mo : memu_out_type;
-- IFU
signal ifui : ifu_in_vector(0 to CFG_NUT_CPU_CORES-1);
signal ifuo : ifu_out_vector(0 to CFG_NUT_CPU_CORES-1);
-- LSU
signal lsui : lsu_in_vector(0 to CFG_NUT_CPU_CORES-1);
signal lsuo : lsu_out_vector(0 to CFG_NUT_CPU_CORES-1);
-- others
--signal icache_enable, dcache_enable: std_logic;
-- EXU signals
signal exui : exu_in_vector(0 to CFG_NUT_CPU_CORES-1);
signal exuo : exu_out_vector(0 to CFG_NUT_CPU_CORES-1);
signal cepui : cepu_in_vector(0 to CFG_NUT_CPU_CORES-1);
signal cepuo : cepu_out_type;
-- INTC signals
signal intci : intc_in_type;
signal intco : intc_out_type;
-- DBG signals
signal bifwbi : busif_wishbone_out_type;
signal bifwbo : busif_wishbone_in_type;
signal jtagi : jtag_in_type;
signal jtago : jtag_out_type;
signal dmo : dm_out_type;
signal reset_or : STD_LOGIC;
signal ifu_reset : STD_LOGIC_VECTOR(0 to CFG_NUT_CPU_CORES-1);
signal dbg_addressed : STD_LOGIC;
-- Histogram
-- signal emhci : exu_memu_hist_ctrl_in_vector(0 to CFG_NUT_CPU_CORES-1);
-- pragma translate_off
-- signal lsui_reg : lsu_in_vector(0 to CFG_signal rp_rd_i : STD_LOGIC;NUT_CPU_CORES-1);
-- signal lsuo_reg : lsu_out_vector(0 to CFG_NUT_CPU_CORES-1);
-- pragma translate_on
function OR_reduce(d: std_logic_vector) return std_logic is
constant all_zeros: std_logic_vector(d'range) := (others => '0');
begin
if d = all_zeros then
return '0';
else
return '1';
end if;
end OR_reduce;
begin
-- MemU
dbg_addressed <= '1' when mo.bifwbo.adr_o(31 downto 16) = "0000000000000000" else '0';
mi.bifwbi.ack_i <= bifwbo.ack_i when dbg_addressed = '1' else ack_i;
mi.bifwbi.err_i <= bifwbo.err_i when dbg_addressed = '1' else err_i;
mi.bifwbi.rty_i <= bifwbo.rty_i when dbg_addressed = '1' else rty_i;
mi.bifwbi.dat_i <= bifwbo.dat_i when dbg_addressed = '1' else dat_i;
cyc_o <= '0' when dbg_addressed = '1' else mo.bifwbo.cyc_o;
stb_o <= '0' when dbg_addressed = '1' else mo.bifwbo.stb_o;
we_o <= '0' when dbg_addressed = '1' else mo.bifwbo.we_o;
bsel_le : if (CFG_NUT_LITTLE_ENDIAN) generate
sel_o <= mo.bifwbo.sel_o;
end generate;
bsel_be : if (not CFG_NUT_LITTLE_ENDIAN) generate
-- TODO: Add reverse order based on CFG_MEMU_BUSIF_WIDTH
sel_o(3) <= mo.bifwbo.sel_o(0);
sel_o(2) <= mo.bifwbo.sel_o(1);
sel_o(1) <= mo.bifwbo.sel_o(2);
sel_o(0) <= mo.bifwbo.sel_o(3);
end generate;
adr_o <= mo.bifwbo.adr_o;
dat_o <= mo.bifwbo.dat_o;
cti_o <= mo.bifwbo.cti_o;
bte_o <= mo.bifwbo.bte_o;
MemU : mmemu
port map (
clk => clk_i,
reset => reset_or,
mi => mi,
mo => mo
);
-- DBGU
bifwbi <= mo.bifwbo;
--~ bifwbi.cyc_o <= mo.bifwbo.cyc_o;
--~ bifwbi.stb_o <= mo.bifwbo.stb_o;
--~ bifwbi.we_o <= mo.bifwbo.we_o;
--~ bifwbi.adr_o <= mo.bifwbo.adr_o;
--~ bifwbi.dat_o <= mo.bifwbo.dat_o;
jtagi.tck <= tck;
jtagi.tms <= tms;
jtagi.tdi <= tdi;
tdo <= jtago.tdo;
slv_bsel_le : if (CFG_NUT_LITTLE_ENDIAN) generate
bifwbi.sel_o <= mo.bifwbo.sel_o;
end generate;
slv_bsel_be : if (not CFG_NUT_LITTLE_ENDIAN) generate
-- TODO: Add reverse order based on CFG_MEMU_BUSIF_WIDTH
bifwbi.sel_o(3) <= mo.bifwbo.sel_o(0);
bifwbi.sel_o(2) <= mo.bifwbo.sel_o(1);
bifwbi.sel_o(1) <= mo.bifwbo.sel_o(2);
bifwbi.sel_o(0) <= mo.bifwbo.sel_o(3);
end generate;
DBG : dbg_wrapper
port map (
clk => clk_i,
reset => rst_i,
bifwbi => bifwbi,
bifwbo => bifwbo,
jtagi => jtagi,
jtago => jtago,
dmo => dmo
);
-- reset_or used in all other modules so DBGU can reset them
reset_or <= dmo.dbg_reset or rst_i;
-- IntC
IntC : mintc_wrapper
port map (
clk => clk_i,
reset => reset_or,
intci => intci,
intco => intco,
ex_int => ex_int
);
-- IFUs
IFUs : for n in 0 to CFG_NUT_CPU_MODE2_CORES-1 generate
IFU : mifu_wrapper
port map (
clk => clk_i,
reset => ifu_reset(n),
ifui => ifui(n),
ifuo => ifuo(n),
rpi => mi.rpi(CFG_NUT_CPU_CORES+n),
rpo => mo.rpo(CFG_NUT_CPU_CORES+n),
icache_enable => cepuo.icache_enable
);
end generate IFUs;
IFU_RESET_SIG : for n in 0 to CFG_NUT_CPU_CORES-1 generate
ifu_reset(n) <= reset_or or exuo(n).ifu_reset;
end generate IFU_RESET_SIG;
MODE1_RP : for n in CFG_NUT_CPU_MODE2_CORES to CFG_NUT_CPU_CORES-1 generate
-- unuse read ports
mi.rpi(CFG_NUT_CPU_CORES+n).port_rd <= '0';
mi.rpi(CFG_NUT_CPU_CORES+n).port_bsel <= (others => '-');
mi.rpi(CFG_NUT_CPU_CORES+n).port_direct <= '-';
mi.rpi(CFG_NUT_CPU_CORES+n).port_adr <= (others => '-');
--mo.rpo(CFG_NUT_CPU_CORES+n).port_ack
end generate MODE1_RP;
-- LSUs
LSUs : for n in 0 to CFG_NUT_CPU_CORES-1 generate
LSUs_SIMPLE : if (CFG_LSU_SIMPLE) generate
LSU : mlsu_simple
port map (
clk => clk_i,
reset => rst_i,
lsui => lsui(n),
lsuo => lsuo(n),
rpi => mi.rpi(n),
rpo => mo.rpo(n),
wpi => mi.wpi(n),
wpo => mo.wpo(n),
dcache_enable => cepuo.dcache_enable
);
end generate;
LSUs_COMPLEX : if (not CFG_LSU_SIMPLE) generate
LSU : mlsu_wrapper
port map (
clk => clk_i,
reset => reset_or,
lsui => lsui(n),
lsuo => lsuo(n),
rpi => mi.rpi(n),
rpo => mo.rpo(n),
wpi => mi.wpi(n),
wpo => mo.wpo(n),
dcache_enable => cepuo.dcache_enable
);
end generate;
end generate LSUs;
-- hist_ctrl_gen : if (CFG_NUT_HISTOGRAM) generate
-- hist_ctrl_in_gen : for n in 0 to CFG_NUT_CPU_CORES-1 generate
-- hist_ctrl_in_gen_cepu : if (n = 0) generate
-- emhci(n).cache_line_fill <= mo.mhco.cache_line_fill;
-- emhci(n).cache_line_wb <= mo.mhco.cache_line_wb;
-- end generate;
-- emhci(n).cache_read_hit_ifu <= mo.mhco.cache_read_hit(CFG_NUT_CPU_CORES+n);
-- emhci(n).cache_read_miss_ifu <= mo.mhco.cache_read_miss(CFG_NUT_CPU_CORES+n);
-- emhci(n).cache_read_hit_lsu <= mo.mhco.cache_read_hit(n);
-- emhci(n).cache_read_miss_lsu <= mo.mhco.cache_read_miss(n);
-- emhci(n).cache_write_hit_lsu <= mo.mhco.cache_write_hit(n);
-- emhci(n).cache_write_miss_lsu <= mo.mhco.cache_write_miss(n);
-- end generate;
-- end generate;
-- EXUs
EXUs : for n in 0 to CFG_NUT_CPU_CORES-1 generate
EXUCePUs : if (n = 0) generate -- CePU
EXUCePU : mexu_wrapper
generic map (
CEPU_FLAG => true,
CAPABILITY_FLAG => true,
CPU_ID => n,
CLK_FREQ_HZ => CLK_FREQ_HZ
)
port map (
clk => clk_i,
reset => reset_or,
-- to IFU
ifui => ifui(n),
ifuo => ifuo(n),
-- to Load/Store Unit (LSU)
lsui => lsui(n),
lsuo => lsuo(n),
-- to/from CePU
exui => exui(n),
exuo => exuo(n),
-- to/from CoPUs
cepui => cepui(n),
cepuo => cepuo,
-- from Debug Module
dbg_req => dmo.dbg_request(n),
-- to/from IntC
intco => intci,
intci => intco
);
-- route signals for CePU
exui(n).ex_i <= OR_reduce(cepui(0).pnx);
exui(n).m2_ir_valid <= '-';
exui(n).m2_ir <= (others => '-');
exui(n).m2_pc <= (others => '-');
end generate EXUCePUs;
EXUMode2CoPUs: if (n > 0 and n < CFG_NUT_CPU_MODE2_CORES) generate -- CoPUs
EXUMode2CoPU: mexu_wrapper
generic map (
CEPU_FLAG => false,
CAPABILITY_FLAG => true,
CPU_ID => n,
CLK_FREQ_HZ => CLK_FREQ_HZ
)
port map (
clk => clk_i,
reset => reset_or,
-- to IFU
ifui => ifui(n),
ifuo => ifuo(n),
-- to Load/Store Unit (LSU)
lsui => lsui(n),
lsuo => lsuo(n),
-- to/from CePU/CoPU
exui => exui(n),
exuo => exuo(n),
-- to/from CoPUs
cepui => cepui(n),
cepuo => open,
-- from Debug Module
dbg_req => dmo.dbg_request(n),
-- to/from IntC
intco => open,
intci.ir_request => '-',
intci.ir_id => (others => '-')
);
-- don't care about cepui on CoPUs
cepui(n).pnhaltreq <= (others => '-');
cepui(n).pnx <= (others => '-');
-- route signals for CoPUs
exui(n).ex_i <= exuo(0).ex_o;
exui(n).m2_ir_valid <= ifuo(0).ir_valid;
exui(n).m2_ir <= ifuo(0).ir;
exui(n).m2_pc <= ifuo(0).pc;
end generate EXUMode2CoPUs;
EXUMode1CoPUs: if (n >= CFG_NUT_CPU_MODE2_CORES) generate -- CoPUs
EXUMode1CoPU: mexu_wrapper
generic map (
CEPU_FLAG => false,
CAPABILITY_FLAG => false,
CPU_ID => n,
CLK_FREQ_HZ => CLK_FREQ_HZ
)
port map (
clk => clk_i,
reset => reset_or,
-- to IFU
ifui => open, -- open
ifuo => ifuo(0), -- CePU IFU signals
-- to Load/Store Unit (LSU)
lsui => lsui(n),
lsuo => lsuo(n),
-- to/from CePU/CoPU
exui => exui(n),
exuo => exuo(n),
-- to/from CoPUs
cepui => cepui(n),
cepuo => open,
-- from Debug Module
dbg_req => dmo.dbg_request(n),
-- to/from IntC
intco => open,
intci.ir_request => '-',
intci.ir_id => (others => '-')
);
-- don't care about cepui on CoPUs
cepui(n).pnhaltreq <= (others => '-');
cepui(n).pnx <= (others => '-');
-- route signals for CoPUs
exui(n).ex_i <= exuo(0).ex_o;
exui(n).m2_ir_valid <= '-';
exui(n).m2_ir <= (others => '-');
exui(n).m2_pc <= (others => '-');
end generate EXUMode1CoPUs;
-- route signals for every CPU
exui(n).enable <= cepuo.pnce(n);
exui(n).linked <= cepuo.pnlm(n);
exui(n).sync_next <= exuo(0).sync_o;
exui(n).xsel <= cepuo.pnxsel(n);
cepui(0).pnhaltreq(n) <= exuo(n).haltreq;
cepui(0).pnx(n) <= exuo(n).ex_o;
end generate EXUs;
-- route exception & sync daisy chain...
MoreThanOne: if (CFG_NUT_CPU_CORES_LD > 0) generate
-- All other CPUs
CoPUs : for n in 0 to CFG_NUT_CPU_CORES-2 generate
exui(n).cause_i <= exuo(n+1).cause_o;
exui(n).epc_i <= exuo(n+1).epc_o;
exui(n).sync_i <= exuo(n+1).sync_o;
end generate CoPUs;
-- Last CoPU
exui(CFG_NUT_CPU_CORES-1).cause_i <= (others => '-');
exui(CFG_NUT_CPU_CORES-1).epc_i <= (others => '-');
exui(CFG_NUT_CPU_CORES-1).sync_i <= '1';
end generate MoreThanOne;
CePUOnly: if (CFG_NUT_CPU_CORES_LD = 0) generate
-- CePU only:
exui(0).cause_i <= (others => '-');
exui(0).epc_i <= (others => '-');
exui(0).sync_i <= '1';
end generate CePUOnly;
-- pragma translate_off
process (clk_i)
begin
if (clk_i'event and clk_i='1') then
for n in 0 to CFG_NUT_CPU_CORES-1 loop
if (cepuo.pnce(n) = '0') then
monitor(n).halted <= true;
else
monitor(n).halted <= false;
end if;
end loop;
end if;
-- if (CFG_DBG_LSU_TRACE) then
-- for n in 0 to CFG_NUT_CPU_CORES-1 loop
-- if (lsui_reg(n).rd = '1' and lsuo_reg(n).ack = '1') then
-- INFO("EXU(" & str(n) & ") LSU read: " & hstr(lsui_reg(n).adr) &
-- " DATA: " & hstr(lsuo(n).rdata) &
-- " WIDTH: " & hstr(lsui_reg(n).width));
-- end if;
-- if (lsui(n).wr = '1' and lsui_reg(n).wr = '0') then
-- INFO("EXU(" & str(n) & ") LSU write: " & hstr(lsui(n).adr) &
-- " DATA: " & hstr(lsui(n).wdata) &
-- " WIDTH: " & hstr(lsui(n).width));
-- end if;
-- end loop;
-- lsui_reg <= lsui;
-- lsuo_reg <= lsuo;
-- end if;
-- if (CFG_DBG_BUS_TRACE) then
-- if (mi.bifwbi.ack_i = '1') then
-- if (mo.bifwbo.we_o = '0') then
-- INFO ("MEM read: " & hstr(mo.bifwbo.adr_o) &
-- " DATA: " & hstr(mi.bifwbi.dat_i) &
-- " BSEL: " & hstr(mo.bifwbo.sel_o));
-- else
-- INFO ("MEM write: " & hstr(mo.bifwbo.adr_o) &
-- " DATA: " & hstr(mo.bifwbo.dat_o) &
-- " BSEL: " & hstr(mo.bifwbo.sel_o));
-- end if;
-- end if;
-- end if;
-- end if;
end process;
-- pragma translate_on
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
Entity mux is
Generic(W : integer);
Port (D0, D1 : in std_logic_vector(W-1 downto 0);
S : in std_logic;
Y : out std_logic_vector(W-1 downto 0));
End;
Architecture behave of mux is
begin
y <= D0 when S = '0' else D1;
end;
|
<gh_stars>0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_asm is
-- Port ( );
end test_asm;
architecture Behavioral of test_asm is
component cartaASM is
Port(
clk, clr, ini, z, a0: in STD_LOGIC;
la, lb, ea, eb, ec: out STD_LOGIC
);
end component;
signal ini, clr, clk, z, a0 : std_logic := '0';
signal la, lb, ea, eb, ec : std_logic := '0';
begin
uu : cartaASM Port Map(
ini => ini,
clr => clr,
clk => clk,
z => z,
a0 => a0,
la => la,
lb => lb,
ea => ea,
eb => eb,
ec => ec
);
clock : process
begin
clk <= '0';
wait for 5ns;
clk <= '1';
wait for 5 ns;
end process;
test : process
begin
clr <= '1';
wait for 30 ns;
clr <= '0';
wait for 60 ns;
ini <= '1';
wait for 10 ns;
ini <= '0';
wait for 50 ns;
a0 <= '1';
wait for 10 ns;
a0 <= '0';
wait for 20 ns;
a0 <= '1';
wait for 10 ns;
a0 <= '0';
wait for 120 ns;
z <= '1';
wait;
end process;
end Behavioral;
|
<reponame>hossameldin1995/riscv_vhdl<filename>rtl/riverlib/core/fpu_d/fadd_d.vhd
--!
--! Copyright 2019 <NAME>, <EMAIL>
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity DoubleAdd is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_add : in std_logic;
i_sub : in std_logic;
i_eq : in std_logic;
i_lt : in std_logic;
i_le : in std_logic;
i_max : in std_logic;
i_min : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_DoubleAdd of DoubleAdd is
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(7 downto 0);
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
illegal_op : std_logic;
overflow : std_logic;
add : std_logic;
sub : std_logic;
eq : std_logic;
lt : std_logic;
le : std_logic;
max : std_logic;
min : std_logic;
flMore : std_logic;
flEqual : std_logic;
flLess : std_logic;
preShift : integer range 0 to 4095;
signOpMore : std_logic;
expMore : std_logic_vector(10 downto 0);
mantMore : std_logic_vector(52 downto 0);
mantLess : std_logic_vector(52 downto 0);
mantLessScale : std_logic_vector(104 downto 0);
mantSum : std_logic_vector(105 downto 0);
lshift : integer range 0 to 127;
mantAlign : std_logic_vector(104 downto 0);
expPostScale : std_logic_vector(11 downto 0);
expPostScaleInv : integer range 0 to 4095;
mantPostScale : std_logic_vector(104 downto 0);
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), (others => '0'), -- a, b, result
'0', '0', '0', '0', -- illegal_op, overflow, add, sub
'0', '0', '0', '0', '0', -- eq, lt, le, max, min
'0', '0', '0', -- flMore, flEqual, flLess
0, '0', (others => '0'), -- preShift, signOpMore, expMore
(others => '0'), (others => '0'), (others => '0'), -- mantMore, mantLess, mantLessScale
(others => '0'), 0, (others => '0'), -- mantSum, lshift, mantAlign
(others => '0'), 0, (others => '0') -- expPostScale, expPostScaleInv, mantPostScale
);
constant zero105 : std_logic_vector(104 downto 0) := (others => '0');
signal r, rin : RegistersType;
begin
-- registers:
comb : process(i_nrst, i_ena, i_add, i_sub, i_eq, i_lt, i_le, i_max, i_min,
i_a, i_b, r)
variable v : RegistersType;
variable signOp : std_logic;
variable signA : std_logic;
variable signB : std_logic;
variable signOpB : std_logic;
variable mantA : std_logic_vector(52 downto 0);
variable mantB : std_logic_vector(52 downto 0);
variable mantDif : std_logic_vector(53 downto 0);
variable expDif : std_logic_vector(11 downto 0);
variable v_flMore : std_logic;
variable v_flEqual : std_logic;
variable v_flLess : std_logic;
variable vb_preShift : std_logic_vector(11 downto 0);
variable v_signOpMore : std_logic;
variable vb_expMore : std_logic_vector(10 downto 0);
variable vb_mantMore : std_logic_vector(52 downto 0);
variable vb_mantLess : std_logic_vector(52 downto 0);
variable mantMoreScale : std_logic_vector(104 downto 0);
variable mantLessScale : std_logic_vector(104 downto 0);
variable vb_mantSum : std_logic_vector(105 downto 0);
variable vb_mantSumInv : std_logic_vector(104 downto 0);
variable vb_lshift : integer range 0 to 127;
variable vb_lshift_p1 : integer range 0 to 127;
variable vb_lshift_p2 : integer range 0 to 127;
variable vb_mantAlign : std_logic_vector(104 downto 0);
variable vb_expPostScale : std_logic_vector(11 downto 0);
variable vb_mantPostScale : std_logic_vector(104 downto 0);
variable mantShort : std_logic_vector(52 downto 0);
variable tmpMant05 : std_logic_vector(51 downto 0);
variable mantOnes : std_logic;
variable mantEven : std_logic;
variable mant05 : std_logic;
variable rndBit : std_logic;
variable mantZeroA : std_logic;
variable mantZeroB : std_logic;
variable allZero : std_logic;
variable sumZero : std_logic;
variable nanA : std_logic;
variable nanB : std_logic;
variable nanAB : std_logic;
variable overflow : std_logic;
variable resAdd : std_logic_vector(63 downto 0);
variable resEQ : std_logic_vector(63 downto 0);
variable resLT : std_logic_vector(63 downto 0);
variable resLE : std_logic_vector(63 downto 0);
variable resMax : std_logic_vector(63 downto 0);
variable resMin : std_logic_vector(63 downto 0);
begin
v := r;
v.ena := r.ena(6 downto 0) & (i_ena and not r.busy);
if i_ena = '1' then
v.busy := '1';
v.add := i_add;
v.sub := i_sub;
v.eq := i_eq;
v.lt := i_lt;
v.le := i_le;
v.max := i_max;
v.min := i_min;
v.a := i_a;
v.b := i_b;
v.illegal_op := '0';
v.overflow := '0';
end if;
signOp := r.sub or r.le or r.lt;
signA := r.a(63);
signB := r.b(63);
signOpB := signB xor signOp;
mantA(51 downto 0) := r.a(51 downto 0);
mantA(52) := '0';
if r.a(62 downto 52) /= zero105(10 downto 0) then
mantA(52) := '1';
end if;
mantB(51 downto 0) := r.b(51 downto 0);
mantB(52) := '0';
if r.b(62 downto 52) /= zero105(10 downto 0) then
mantB(52) := '1';
end if;
if r.a(62 downto 52) /= "00000000000" and r.b(62 downto 52) = "00000000000" then
expDif := ('0' & r.a(62 downto 52)) - "000000000001";
elsif r.a(62 downto 52) = "00000000000" and r.b(62 downto 52) /= "00000000000" then
expDif := "000000000001" - ('0' & r.b(62 downto 52));
else
expDif := ('0' & r.a(62 downto 52)) - ('0' & r.b(62 downto 52));
end if;
mantDif := ('0' & mantA) - ('0' & mantB);
if expDif = X"000" then
vb_preShift := expDif;
if mantDif = zero105(53 downto 0) then
v_flMore := not signA and (signA xor signB);
v_flEqual := not (signA xor signB);
v_flLess := signA and (signA xor signB);
v_signOpMore := signA;
vb_expMore := r.a(62 downto 52);
vb_mantMore := mantA;
vb_mantLess := mantB;
elsif mantDif(53) = '0' then -- A > B
v_flMore := not signA;
v_flEqual := '0';
v_flLess := signA;
v_signOpMore := signA;
vb_expMore := r.a(62 downto 52);
vb_mantMore := mantA;
vb_mantLess := mantB;
else
v_flMore := signB;
v_flEqual := '0';
v_flLess := not signB;
v_signOpMore := signOpB;
vb_expMore := r.b(62 downto 52);
vb_mantMore := mantB;
vb_mantLess := mantA;
end if;
elsif expDif(11) = '0' then
v_flMore := not signA;
v_flEqual := '0';
v_flLess := signA;
vb_preShift := expDif;
v_signOpMore := signA;
vb_expMore := r.a(62 downto 52);
vb_mantMore := mantA;
vb_mantLess := mantB;
else
v_flMore := signB;
v_flEqual := '0';
v_flLess := not signB;
vb_preShift := not expDif + 1;
v_signOpMore := signOpB;
vb_expMore := r.b(62 downto 52);
vb_mantMore := mantB;
vb_mantLess := mantA;
end if;
if r.ena(0) = '1' then
v.flMore := v_flMore;
v.flEqual := v_flEqual;
v.flLess := v_flLess;
v.preShift := conv_integer(vb_preShift);
v.signOpMore := v_signOpMore;
v.expMore := vb_expMore;
v.mantMore := vb_mantMore;
v.mantLess := vb_mantLess;
end if;
-- Pre-scale 105-bits mantissa if preShift < 105:
-- M = {mantM, 52'd0}
mantLessScale := r.mantLess & zero105(51 downto 0);
if r.ena(1) = '1' then
if r.preShift = 0 then
v.mantLessScale := mantLessScale;
else
v.mantLessScale := (others => '0');
for i in 1 to 104 loop
if i = r.preShift then
v.mantLessScale := zero105(i-1 downto 0) & mantLessScale(104 downto i);
end if;
end loop;
end if;
end if;
mantMoreScale := r.mantMore & zero105(51 downto 0);
-- 106-bits adder/subtractor
if (signA xor signOpB) = '1' then
vb_mantSum := ('0' & mantMoreScale) - ('0' & r.mantLessScale);
else
vb_mantSum := ('0' & mantMoreScale) + ('0' & r.mantLessScale);
end if;
if r.ena(2) = '1' then
v.mantSum := vb_mantSum;
end if;
-- To avoid timing constrains violation occured in Vivado Studio
-- try to implement parallel demuxultiplexer splitted on 2 parts
vb_mantSumInv(0) := '0';
for i in 0 to 103 loop
vb_mantSumInv(i + 1) := r.mantSum(103 - i);
end loop;
vb_lshift_p1 := 0;
for i in 0 to 63 loop
if vb_lshift_p1 = 0 and vb_mantSumInv(i) = '1' then
vb_lshift_p1 := i;
end if;
end loop;
vb_lshift_p2 := 0;
for i in 0 to 40 loop
if vb_lshift_p2 = 0 and vb_mantSumInv(64 + i) = '1' then
vb_lshift_p2 := 64 + i;
end if;
end loop;
-- multiplexer
if r.mantSum(105) = '1' then
-- shift right
vb_lshift := 127;
elsif r.mantSum(104) = '1' then
vb_lshift := 0;
elsif vb_lshift_p1 /= 0 then
vb_lshift := vb_lshift_p1;
else
vb_lshift := vb_lshift_p2;
end if;
if r.ena(3) = '1' then
v.lshift := vb_lshift;
end if;
-- Prepare to mantissa post-scale
vb_mantAlign := (others => '0');
if r.lshift = 127 then
vb_mantAlign := r.mantSum(105 downto 1);
elsif r.lshift = 0 then
vb_mantAlign := r.mantSum(104 downto 0);
else
for i in 1 to 104 loop
if i = r.lshift then
vb_mantAlign := r.mantSum(104-i downto 0) & zero105(i-1 downto 0);
end if;
end loop;
end if;
if r.lshift = 127 then
if r.expMore = "11111111111" then
vb_expPostScale := ('0' & r.expMore);
else
vb_expPostScale := ('0' & r.expMore) + 1;
end if;
else
if r.expMore = "00000000000" and r.lshift = 0 then
vb_expPostScale := X"001";
else
vb_expPostScale := ('0' & r.expMore) - conv_std_logic_vector(r.lshift, 12);
end if;
end if;
if (signA xor signOpB) = '1' then
-- subtractor only: result value becomes with exp=0
if r.expMore /= "00000000000" and
(vb_expPostScale(11) = '1' or vb_expPostScale = X"000") then
vb_expPostScale := vb_expPostScale - 1;
end if;
end if;
if r.ena(4) = '1' then
v.mantAlign := vb_mantAlign;
v.expPostScale := vb_expPostScale;
v.expPostScaleInv := conv_integer((not vb_expPostScale) + 1);
end if;
-- Mantissa post-scale:
-- Scaled = SumScale>>(-ExpSum) only if ExpSum < 0;
vb_mantPostScale := r.mantAlign;
if r.expPostScale(11) = '1' then
for i in 1 to 104 loop
if i = r.expPostScaleInv then
vb_mantPostScale := zero105(i-1 downto 0) & r.mantAlign(104 downto i);
end if;
end loop;
end if;
if r.ena(5) = '1' then
v.mantPostScale := vb_mantPostScale;
end if;
-- Rounding bit
mantShort := r.mantPostScale(104 downto 52);
tmpMant05 := r.mantPostScale(51 downto 0);
mantOnes := '0';
if mantShort(52) = '1' and mantShort(51 downto 0) = X"fffffffffffff" then
mantOnes := '1';
end if;
mantEven := r.mantPostScale(52);
mant05 := '0';
if tmpMant05 = X"8000000000000" then
mant05 := '1';
end if;
rndBit := r.mantPostScale(51) and not(mant05 and not mantEven);
-- Check Borders
mantZeroA := '0';
if r.a(51 downto 0) = zero105(51 downto 0) then
mantZeroA := '1';
end if;
mantZeroB := '0';
if r.b(51 downto 0) = zero105(51 downto 0) then
mantZeroB := '1';
end if;
-- Exceptions
allZero := '0';
if r.a(62 downto 0) = zero105(62 downto 0) and
r.b(62 downto 0) = zero105(62 downto 0) then
allZero := '1';
end if;
sumZero := '0';
if r.mantPostScale = zero105 then
sumZero := '1';
end if;
nanA := '0';
if r.a(62 downto 52) = "11111111111" then
nanA := '1';
end if;
nanB := '0';
if r.b(62 downto 52) = "11111111111" then
nanB := '1';
end if;
nanAB := nanA and mantZeroA and nanB and mantZeroB;
overflow := '0';
if r.expPostScale = X"7FF" then -- positive
overflow := '1';
end if;
-- Result multiplexers:
if (nanAB and signOp) = '1' then
resAdd(63) := signA xor signOpB;
elsif nanA = '1' then
-- when both values are NaN, value B has higher priority if sign=1
resAdd(63) := signA or (nanB and signOpB);
elsif nanB = '1' then
resAdd(63) := signOpB xor (signOp and not mantZeroB);
elsif allZero = '1' then
resAdd(63) := signA and signOpB;
elsif sumZero = '1' then
resAdd(63) := '0';
else
resAdd(63) := r.signOpMore;
end if;
if (nanA or nanB) = '1' then
resAdd(62 downto 52) := (others => '1');
elsif r.expPostScale(11) = '1' or sumZero = '1' then
resAdd(62 downto 52) := (others => '0');
else
resAdd(62 downto 52) := r.expPostScale(10 downto 0)
+ (mantOnes and rndBit and not r.overflow);
end if;
if (nanA and mantZeroA and nanB and mantZeroB) = '1' then
resAdd(51) := '1';
resAdd(50 downto 0) := (others => '0');
elsif nanA = '1' and (nanB and signOpB) = '0' then
-- when both values are NaN, value B has higher priority if sign=1
resAdd(51) := '1';
resAdd(50 downto 0) := r.a(50 downto 0);
elsif nanB = '1' then
resAdd(51) := '1';
resAdd(50 downto 0) := r.b(50 downto 0);
elsif r.overflow = '1' then
resAdd(51 downto 0) := (others => '0');
else
resAdd(51 downto 0) := mantShort(51 downto 0) + rndBit;
end if;
resEQ(63 downto 1) := (others => '0');
resEQ(0) := r.flEqual;
resLT(63 downto 1) := (others => '0');
resLT(0) := r.flLess;
resLE(63 downto 1) := (others => '0');
resLE(0) := r.flLess or r.flEqual;
if (nanA or nanB) = '1' then
resMax := r.b;
elsif r.flMore = '1' then
resMax := r.a;
else
resMax := r.b;
end if;
if (nanA or nanB) = '1' then
resMin := r.b;
elsif r.flLess = '1' then
resMin := r.a;
else
resMin := r.b;
end if;
if r.ena(6) = '1' then
if r.eq = '1' then
v.result := resEQ;
elsif r.lt = '1' then
v.result := resLT;
elsif r.le = '1' then
v.result := resLE;
elsif r.max = '1' then
v.result := resMax;
elsif r.min = '1' then
v.result := resMin;
else
v.result := resAdd;
end if;
v.illegal_op := nanA or nanB;
v.overflow := overflow;
v.busy := '0';
v.add := '0';
v.sub := '0';
v.eq := '0';
v.lt := '0';
v.le := '0';
v.max := '0';
v.min := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_illegal_op <= r.illegal_op;
o_overflow <= r.overflow;
o_valid <= r.ena(7);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fir_c_rom is
generic(
dwidth : integer := 16;
awidth : integer := 6;
mem_size : integer := 59
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of fir_c_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "1111111010000110", 1 => "1111111110110111", 2 => "0000000000011011",
3 => "0000000010101010", 4 => "0000000100101010", 5 => "0000000101100000",
6 => "0000000100101110", 7 => "0000000010101000", 8 => "0000000000001110",
9 => "1111111110110000", 10 => "1111111111000000", 11 => "0000000000110101",
12 => "0000000010111010", 13 => "0000000011011000", 14 => "0000000000101000",
15 => "1111111010011100", 16 => "1111110010011101", 17 => "1111101011111101",
18 => "1111101010101010", 19 => "1111110001000110", 20 => "1111111111001101",
21 => "0000010001101100", 22 => "0000100010110011", 23 => "0000101100001101",
24 => "0000101001010111", 25 => "0000011001100001", 26 => "0000000000011001",
27 => "1111100101010000", 28 => "1111010000011110", 29 => "0111001000101101",
30 => "1111010000011110", 31 => "1111100101010000", 32 => "0000000000011001",
33 => "0000011001100001", 34 => "0000101001010111", 35 => "0000101100001101",
36 => "0000100010110011", 37 => "0000010001101100", 38 => "1111111111001101",
39 => "1111110001000110", 40 => "1111101010101010", 41 => "1111101011111101",
42 => "1111110010011101", 43 => "1111111010011100", 44 => "0000000000101000",
45 => "0000000011011000", 46 => "0000000010111010", 47 => "0000000000110101",
48 => "1111111111000000", 49 => "1111111110110000", 50 => "0000000000001110",
51 => "0000000010101000", 52 => "0000000100101110", 53 => "0000000101100000",
54 => "0000000100101010", 55 => "0000000010101010", 56 => "0000000000011011",
57 => "1111111110110111", 58 => "1111111010000110" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem : signal is "select_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem : signal is "distributed";
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_c is
generic (
DataWidth : INTEGER := 16;
AddressRange : INTEGER := 59;
AddressWidth : INTEGER := 6);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of fir_c is
component fir_c_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_c_rom_U : component fir_c_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity test_FFA is
generic (N : natural := 8);
end entity;
architecture bhv of test_FFA is
component FFA
--generic (N : natural := 8; P : integer := 3; period : time := 1000 ns);
generic (N : natural := 8; P : integer := 3);
port (FW : in std_logic_vector (N-1 downto 0);
en : in std_logic;
ffa : inout std_logic);
end component;
signal FWt : std_logic_vector (N-1 downto 0) := std_logic_vector(to_unsigned(2,N));
signal FWt1 : std_logic_vector (N-1 downto 0) := std_logic_vector(to_unsigned(3,N));
signal FWt2 : std_logic_vector (N-1 downto 0) := std_logic_vector(to_unsigned(4,N));
signal FWt3 : std_logic_vector (N-1 downto 0) := std_logic_vector(to_unsigned(5,N));
signal ent, ffat, ffat1, ffat2, ffat3 : std_logic;
begin
uut : FFA generic map (N => N, P => 3) port map (FW => FWt, en => ent, ffa => ffat);
uut1: FFA generic map (N => N, P => 3) port map (FW => FWt1, en => ent, ffa => ffat1);
uut2: FFA generic map (N => N, P => 3) port map (FW => FWt2, en => ent, ffa => ffat2);
uut3: FFA generic map (N => N, P => 3) port map (FW => FWt3, en => ent, ffa => ffat3);
ent <= '0', '1' after 300 ns;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity alu is
port(
alu_a : in vl_logic_vector(31 downto 0);
alu_b : in vl_logic_vector(31 downto 0);
alu_ctrl : in vl_logic_vector(3 downto 0);
alu_y : out vl_logic_vector(31 downto 0);
alu_comp : out vl_logic_vector(1 downto 0)
);
end alu;
|
-- © IBM Corp. 2020
-- This softcore is licensed under and subject to the terms of the CC-BY 4.0
-- license (https://creativecommons.org/licenses/by/4.0/legalcode).
-- Additional rights, including the right to physically implement a softcore
-- that is compliant with the required sections of the Power ISA
-- Specification, will be available at no cost via the OpenPOWER Foundation.
-- This README will be updated with additional information when OpenPOWER's
-- license is available.
LIBRARY ieee; USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY ibm;
USE ibm.std_ulogic_support.all;
USE ibm.std_ulogic_unsigned.all;
USE ibm.std_ulogic_function_support.all;
LIBRARY support;
USE support.power_logic_pkg.all;
LIBRARY tri; USE tri.tri_latches_pkg.all;
LIBRARY clib ;
entity xuq_lsu_cmp_cmp31 is
generic( expand_type: integer := 2 );
port(
d0 :in std_ulogic_vector(0 to 30);
d1 :in std_ulogic_vector(0 to 30);
eq :out std_ulogic
);
end xuq_lsu_cmp_cmp31;
architecture xuq_lsu_cmp_cmp31 of xuq_lsu_cmp_cmp31 is
constant tiup : std_ulogic := '1';
constant tidn : std_ulogic := '0';
signal eq01 :std_ulogic_vector(0 to 30) ;
signal eq03_b : std_ulogic_vector(0 to 11);
signal eq06 : std_ulogic_vector(0 to 5);
signal eq18_b : std_ulogic_vector(0 to 1);
begin
u_eq01: eq01(0 to 30) <= not( d0(0 to 30) xor d1(0 to 30) );
u_eq03_00: eq03_b( 0) <= not( eq01( 0) and eq01( 1) and eq01( 2) );
u_eq03_01: eq03_b( 1) <= not( eq01( 3) and eq01( 4) and eq01( 5) );
u_eq03_02: eq03_b( 2) <= not( eq01( 6) and eq01( 7) and eq01( 8) );
u_eq03_03: eq03_b( 3) <= not( eq01( 9) and eq01(10) and eq01(11) );
u_eq03_04: eq03_b( 4) <= not( eq01(12) and eq01(13) and eq01(14) );
u_eq03_05: eq03_b( 5) <= not( eq01(15) and eq01(16) and eq01(17) );
u_eq03_06: eq03_b( 6) <= not( eq01(18) and eq01(19) and eq01(20) );
u_eq03_07: eq03_b( 7) <= not( eq01(21) and eq01(22) );
u_eq03_08: eq03_b( 8) <= not( eq01(23) and eq01(24) );
u_eq03_09: eq03_b( 9) <= not( eq01(25) and eq01(26) );
u_eq03_10: eq03_b(10) <= not( eq01(27) and eq01(28) );
u_eq03_11: eq03_b(11) <= not( eq01(29) and eq01(30) );
u_eq06_00: eq06( 0) <= not( eq03_b( 0) or eq03_b( 1) );
u_eq06_01: eq06( 1) <= not( eq03_b( 2) or eq03_b( 3) );
u_eq06_02: eq06( 2) <= not( eq03_b( 4) or eq03_b( 5) );
u_eq06_03: eq06( 3) <= not( eq03_b( 6) or eq03_b( 7) );
u_eq06_04: eq06( 4) <= not( eq03_b( 8) or eq03_b( 9) );
u_eq06_05: eq06( 5) <= not( eq03_b(10) or eq03_b(11) );
u_eq18_00: eq18_b( 0) <= not( eq06(0) and eq06(1) and eq06(2) );
u_eq18_01: eq18_b( 1) <= not( eq06(3) and eq06(4) and eq06(5) );
u_eq36_00: eq <= not( eq18_b( 0) or eq18_b( 1) );
end;
|
<filename>rtl/riscv_local_memmap.vhd<gh_stars>10-100
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:13:30 03/09/2017
-- Design Name:
-- Module Name: riscv_local_memmap - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Bonfire CPU
-- (c) 2016,2017 <NAME>
-- See license.md for License
-- Bonfire CPU local memory mapped devices
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity riscv_local_memmap is
generic (
TIMER_XLEN : natural := 32
);
port (
-- bus interface
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(15 downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
timer_irq_o : out std_logic
);
end riscv_local_memmap;
architecture rtl of riscv_local_memmap is
signal mtime : unsigned(TIMER_XLEN-1 downto 0) := (others=>'0');
signal mtimecmp : unsigned(TIMER_XLEN-1 downto 0) := (others=>'0');
signal cs : std_logic;
signal timer_irq : std_logic :='0';
begin
timer_irq_o<=timer_irq;
cs <= '1' when wbs_adr_i(15 downto 4) = "000000000000" and wbs_cyc_i='1' and wbs_stb_i='1' else
'0';
wbs_ack_o <= cs;
--TODO: Add Support for mtime and mtimecmp > 32 Bit
with wbs_adr_i(3 downto 2) select
wbs_dat_o <= std_logic_vector(mtime(31 downto 0)) when "00",
std_logic_vector(mtimecmp(31 downto 0)) when "10",
(others=>'X') when others;
process(clk_i) begin
if rising_edge(clk_i) then
if rst_i='1' then
mtime <= (others=>'0');
mtimecmp <= (others=>'0');
timer_irq<='0';
else
mtime <= mtime + 1;
if mtimecmp /= 0 and mtime=mtimecmp then
timer_irq <= '1';
end if;
if cs='1' and wbs_we_i='1' then
case wbs_adr_i(3 downto 2) is
when "10" =>
mtimecmp(31 downto 0) <= unsigned(wbs_dat_i);
timer_irq <= '0';
when "11" =>
if mtimecmp'high > 31 then
mtimecmp(mtimecmp'high downto 32) <= unsigned(wbs_dat_i(mtimecmp'high-32 downto 0));
timer_irq <= '0';
end if;
when others =>
end case;
end if;
end if;
end if;
end process;
end rtl;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
PACKAGE ula_package IS
COMPONENT ula_struct IS
PORT
(
operacao : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
operA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
operB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Result : buffer STD_LOGIC_VECTOR(7 DOWNTO 0);
Cin : IN STD_LOGIC;
N,Z,C,B,V : buffer STD_LOGIC
);
END COMPONENT;
END ula_package;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:24:15 04/11/2018
-- Design Name:
-- Module Name: dzielnik - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider is
port(
signal clock_in: in std_logic;
signal clock_out: out std_logic
);
end divider;
architecture Behavioral of dzielnik is
signal y:std_logic_vector(25 downto 0):="00000000000000000000000000";
constant n:integer :=50000;
constant m:integer :=n/2;
begin
div:process(clock_in) is
begin
if rising_edge(clock_in) then
if
y=n-1 then y<="00000000000000000000000000";
elsif (true) then y<=y+1;
end if;
if y = m then clock_out<='0';
elsif y ="00000000000000000000000000" then clock_out<='1';
end if;
end if;
end process div;
end Behavioral;
|
<reponame>ankurshaswat/COL216
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity reverse_8 is
port (
inp : in std_logic_vector(31 downto 0);
slct : in std_logic;
oup : out std_logic_vector(31 downto 0));
end entity reverse_8;
architecture arch_1 of reverse_8 is
begin
with slct select oup(15 downto 0) <=
inp(7 downto 0)&inp(15 downto 8) when '1',
inp(15 downto 0) when others;
with slct select oup(31 downto 16) <=
inp(23 downto 16)&inp(31 downto 24) when '1',
inp(31 downto 16) when others;
end architecture arch_1;
|
<gh_stars>1-10
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-- Date : Tue Oct 5 21:04:10 2021
-- Host : Duller running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_s00_data_fifo_0 -prefix
-- system_s00_data_fifo_0_ system_s00_data_fifo_0_sim_netlist.vhdl
-- Design : system_s00_data_fifo_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_s00_data_fifo_0_xpm_cdc_async_rst is
port (
src_arst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_arst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is 0;
attribute INV_DEF_VAL : string;
attribute INV_DEF_VAL of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is "1'b1";
attribute RST_ACTIVE_HIGH : integer;
attribute RST_ACTIVE_HIGH of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is 1;
attribute VERSION : integer;
attribute VERSION of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is "TRUE";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of system_s00_data_fifo_0_xpm_cdc_async_rst : entity is "ASYNC_RST";
end system_s00_data_fifo_0_xpm_cdc_async_rst;
architecture STRUCTURE of system_s00_data_fifo_0_xpm_cdc_async_rst is
signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of arststages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of arststages_ff : signal is "true";
attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
begin
dest_arst <= arststages_ff(1);
\arststages_ff_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => '0',
PRE => src_arst,
Q => arststages_ff(0)
);
\arststages_ff_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => arststages_ff(0),
PRE => src_arst,
Q => arststages_ff(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ is
port (
src_arst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_arst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is 0;
attribute INV_DEF_VAL : string;
attribute INV_DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is "xpm_cdc_async_rst";
attribute RST_ACTIVE_HIGH : integer;
attribute RST_ACTIVE_HIGH of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is "TRUE";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ : entity is "ASYNC_RST";
end \system_s00_data_fifo_0_xpm_cdc_async_rst__3\;
architecture STRUCTURE of \system_s00_data_fifo_0_xpm_cdc_async_rst__3\ is
signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of arststages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of arststages_ff : signal is "true";
attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
begin
dest_arst <= arststages_ff(1);
\arststages_ff_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => '0',
PRE => src_arst,
Q => arststages_ff(0)
);
\arststages_ff_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => arststages_ff(0),
PRE => src_arst,
Q => arststages_ff(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ is
port (
src_arst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_arst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is 0;
attribute INV_DEF_VAL : string;
attribute INV_DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is "xpm_cdc_async_rst";
attribute RST_ACTIVE_HIGH : integer;
attribute RST_ACTIVE_HIGH of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is "TRUE";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ : entity is "ASYNC_RST";
end \system_s00_data_fifo_0_xpm_cdc_async_rst__4\;
architecture STRUCTURE of \system_s00_data_fifo_0_xpm_cdc_async_rst__4\ is
signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of arststages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of arststages_ff : signal is "true";
attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
begin
dest_arst <= arststages_ff(1);
\arststages_ff_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => '0',
PRE => src_arst,
Q => arststages_ff(0)
);
\arststages_ff_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => arststages_ff(0),
PRE => src_arst,
Q => arststages_ff(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ is
port (
src_arst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_arst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is 0;
attribute INV_DEF_VAL : string;
attribute INV_DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is "xpm_cdc_async_rst";
attribute RST_ACTIVE_HIGH : integer;
attribute RST_ACTIVE_HIGH of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is "TRUE";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ : entity is "ASYNC_RST";
end \system_s00_data_fifo_0_xpm_cdc_async_rst__5\;
architecture STRUCTURE of \system_s00_data_fifo_0_xpm_cdc_async_rst__5\ is
signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of arststages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of arststages_ff : signal is "true";
attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
begin
dest_arst <= arststages_ff(1);
\arststages_ff_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => '0',
PRE => src_arst,
Q => arststages_ff(0)
);
\arststages_ff_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => arststages_ff(0),
PRE => src_arst,
Q => arststages_ff(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ is
port (
src_arst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_arst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is 0;
attribute INV_DEF_VAL : string;
attribute INV_DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is "xpm_cdc_async_rst";
attribute RST_ACTIVE_HIGH : integer;
attribute RST_ACTIVE_HIGH of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is "TRUE";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ : entity is "ASYNC_RST";
end \system_s00_data_fifo_0_xpm_cdc_async_rst__6\;
architecture STRUCTURE of \system_s00_data_fifo_0_xpm_cdc_async_rst__6\ is
signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of arststages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of arststages_ff : signal is "true";
attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
begin
dest_arst <= arststages_ff(1);
\arststages_ff_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => '0',
PRE => src_arst,
Q => arststages_ff(0)
);
\arststages_ff_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => arststages_ff(0),
PRE => src_arst,
Q => arststages_ff(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_s00_data_fifo_0_xpm_cdc_sync_rst is
port (
src_rst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_rst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is "1'b1";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is 5;
attribute INIT : string;
attribute INIT of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is "1";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is 0;
attribute VERSION : integer;
attribute VERSION of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is "TRUE";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of system_s00_data_fifo_0_xpm_cdc_sync_rst : entity is "SYNC_RST";
end system_s00_data_fifo_0_xpm_cdc_sync_rst;
architecture STRUCTURE of system_s00_data_fifo_0_xpm_cdc_sync_rst is
signal syncstages_ff : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[4]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[4]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[4]\ : label is "SYNC_RST";
begin
dest_rst <= syncstages_ff(4);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => src_rst,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(1),
Q => syncstages_ff(2),
R => '0'
);
\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(2),
Q => syncstages_ff(3),
R => '0'
);
\syncstages_ff_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(3),
Q => syncstages_ff(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ is
port (
src_rst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_rst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is "1'b1";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is 5;
attribute INIT : string;
attribute INIT of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is "1";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is "xpm_cdc_sync_rst";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is "TRUE";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ : entity is "SYNC_RST";
end \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\;
architecture STRUCTURE of \system_s00_data_fifo_0_xpm_cdc_sync_rst__2\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[4]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[4]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[4]\ : label is "SYNC_RST";
begin
dest_rst <= syncstages_ff(4);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => src_rst,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(1),
Q => syncstages_ff(2),
R => '0'
);
\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(2),
Q => syncstages_ff(3),
R => '0'
);
\syncstages_ff_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(3),
Q => syncstages_ff(4),
R => '0'
);
end STRUCTURE;
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<KEY>
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_READ_FIFO_DELAY : integer;
attribute C_AXI_READ_FIFO_DELAY of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_READ_FIFO_DEPTH : integer;
attribute C_AXI_READ_FIFO_DEPTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 512;
attribute C_AXI_READ_FIFO_TYPE : string;
attribute C_AXI_READ_FIFO_TYPE of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is "bram";
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 0;
attribute C_AXI_WRITE_FIFO_DELAY : integer;
attribute C_AXI_WRITE_FIFO_DELAY of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_AXI_WRITE_FIFO_DEPTH : integer;
attribute C_AXI_WRITE_FIFO_DEPTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 512;
attribute C_AXI_WRITE_FIFO_TYPE : string;
attribute C_AXI_WRITE_FIFO_TYPE of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is "bram";
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is "zynq";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 2;
attribute P_PRIM_FIFO_TYPE : string;
attribute P_PRIM_FIFO_TYPE of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is "512x72";
attribute P_READ_FIFO_DEPTH_LOG : integer;
attribute P_READ_FIFO_DEPTH_LOG of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 9;
attribute P_WIDTH_RACH : integer;
attribute P_WIDTH_RACH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 60;
attribute P_WIDTH_RDCH : integer;
attribute P_WIDTH_RDCH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 69;
attribute P_WIDTH_WACH : integer;
attribute P_WIDTH_WACH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 60;
attribute P_WIDTH_WDCH : integer;
attribute P_WIDTH_WDCH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 75;
attribute P_WIDTH_WRCH : integer;
attribute P_WIDTH_WRCH of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 4;
attribute P_WRITE_FIFO_DEPTH_LOG : integer;
attribute P_WRITE_FIFO_DEPTH_LOG of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo : entity is 9;
end system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo;
architecture STRUCTURE of system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo is
signal \<const0>\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_almost_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_almost_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axis_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axis_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axis_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axis_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axis_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axis_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tlast_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tvalid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_s_axis_tready_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_valid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_wr_ack_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_wr_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axis_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axis_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_axis_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_arid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_arregion_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_aruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awregion_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_wid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axi_wuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tdata_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tdest_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tstrb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_m_axis_tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_fifo.fifo_gen_inst_s_axi_bid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_s_axi_buser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_s_axi_rid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_s_axi_ruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.fifo_gen_inst_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_AXI_ADDR_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 32;
attribute C_AXI_ARUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_AXI_AWUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_AXI_BUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_AXI_DATA_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 64;
attribute C_AXI_ID_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 4;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_AXI_RUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \gen_fifo.fifo_gen_inst\ : label is 3;
attribute C_AXI_WUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \gen_fifo.fifo_gen_inst\ : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \gen_fifo.fifo_gen_inst\ : label is 60;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \gen_fifo.fifo_gen_inst\ : label is 69;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \gen_fifo.fifo_gen_inst\ : label is 60;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \gen_fifo.fifo_gen_inst\ : label is 75;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \gen_fifo.fifo_gen_inst\ : label is 75;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \gen_fifo.fifo_gen_inst\ : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_FAMILY of \gen_fifo.fifo_gen_inst\ : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \gen_fifo.fifo_gen_inst\ : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \gen_fifo.fifo_gen_inst\ : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \gen_fifo.fifo_gen_inst\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \gen_fifo.fifo_gen_inst\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \gen_fifo.fifo_gen_inst\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \gen_fifo.fifo_gen_inst\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \gen_fifo.fifo_gen_inst\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \gen_fifo.fifo_gen_inst\ : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \gen_fifo.fifo_gen_inst\ : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \gen_fifo.fifo_gen_inst\ : label is 30;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \gen_fifo.fifo_gen_inst\ : label is 510;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \gen_fifo.fifo_gen_inst\ : label is 30;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \gen_fifo.fifo_gen_inst\ : label is 510;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \gen_fifo.fifo_gen_inst\ : label is 14;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \gen_fifo.fifo_gen_inst\ : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \gen_fifo.fifo_gen_inst\ : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \gen_fifo.fifo_gen_inst\ : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \gen_fifo.fifo_gen_inst\ : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \gen_fifo.fifo_gen_inst\ : label is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \gen_fifo.fifo_gen_inst\ : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \gen_fifo.fifo_gen_inst\ : label is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \gen_fifo.fifo_gen_inst\ : label is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \gen_fifo.fifo_gen_inst\ : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \gen_fifo.fifo_gen_inst\ : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \gen_fifo.fifo_gen_inst\ : label is 2;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \gen_fifo.fifo_gen_inst\ : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \gen_fifo.fifo_gen_inst\ : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \gen_fifo.fifo_gen_inst\ : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \gen_fifo.fifo_gen_inst\ : label is 32;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \gen_fifo.fifo_gen_inst\ : label is 512;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \gen_fifo.fifo_gen_inst\ : label is 32;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \gen_fifo.fifo_gen_inst\ : label is 512;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \gen_fifo.fifo_gen_inst\ : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \gen_fifo.fifo_gen_inst\ : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \gen_fifo.fifo_gen_inst\ : label is 9;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \gen_fifo.fifo_gen_inst\ : label is 5;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \gen_fifo.fifo_gen_inst\ : label is 9;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \gen_fifo.fifo_gen_inst\ : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \gen_fifo.fifo_gen_inst\ : label is 1;
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of \gen_fifo.fifo_gen_inst\ : label is "soft";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of \gen_fifo.fifo_gen_inst\ : label is "true";
begin
m_axi_arid(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_fifo.fifo_gen_inst\: entity work.system_s00_data_fifo_0_fifo_generator_v13_2_5
port map (
almost_empty => \NLW_gen_fifo.fifo_gen_inst_almost_empty_UNCONNECTED\,
almost_full => \NLW_gen_fifo.fifo_gen_inst_almost_full_UNCONNECTED\,
axi_ar_data_count(5 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_ar_data_count_UNCONNECTED\(5 downto 0),
axi_ar_dbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED\,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => \NLW_gen_fifo.fifo_gen_inst_axi_ar_overflow_UNCONNECTED\,
axi_ar_prog_empty => \NLW_gen_fifo.fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED\,
axi_ar_prog_empty_thresh(4 downto 0) => B"00000",
axi_ar_prog_full => \NLW_gen_fifo.fifo_gen_inst_axi_ar_prog_full_UNCONNECTED\,
axi_ar_prog_full_thresh(4 downto 0) => B"00000",
axi_ar_rd_data_count(5 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED\(5 downto 0),
axi_ar_sbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED\,
axi_ar_underflow => \NLW_gen_fifo.fifo_gen_inst_axi_ar_underflow_UNCONNECTED\,
axi_ar_wr_data_count(5 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED\(5 downto 0),
axi_aw_data_count(5 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_aw_data_count_UNCONNECTED\(5 downto 0),
axi_aw_dbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED\,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => \NLW_gen_fifo.fifo_gen_inst_axi_aw_overflow_UNCONNECTED\,
axi_aw_prog_empty => \NLW_gen_fifo.fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED\,
axi_aw_prog_empty_thresh(4 downto 0) => B"00000",
axi_aw_prog_full => \NLW_gen_fifo.fifo_gen_inst_axi_aw_prog_full_UNCONNECTED\,
axi_aw_prog_full_thresh(4 downto 0) => B"00000",
axi_aw_rd_data_count(5 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED\(5 downto 0),
axi_aw_sbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED\,
axi_aw_underflow => \NLW_gen_fifo.fifo_gen_inst_axi_aw_underflow_UNCONNECTED\,
axi_aw_wr_data_count(5 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED\(5 downto 0),
axi_b_data_count(4 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_b_data_count_UNCONNECTED\(4 downto 0),
axi_b_dbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_b_dbiterr_UNCONNECTED\,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => \NLW_gen_fifo.fifo_gen_inst_axi_b_overflow_UNCONNECTED\,
axi_b_prog_empty => \NLW_gen_fifo.fifo_gen_inst_axi_b_prog_empty_UNCONNECTED\,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => \NLW_gen_fifo.fifo_gen_inst_axi_b_prog_full_UNCONNECTED\,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED\(4 downto 0),
axi_b_sbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_b_sbiterr_UNCONNECTED\,
axi_b_underflow => \NLW_gen_fifo.fifo_gen_inst_axi_b_underflow_UNCONNECTED\,
axi_b_wr_data_count(4 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED\(4 downto 0),
axi_r_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_r_data_count_UNCONNECTED\(9 downto 0),
axi_r_dbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_r_dbiterr_UNCONNECTED\,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => \NLW_gen_fifo.fifo_gen_inst_axi_r_overflow_UNCONNECTED\,
axi_r_prog_empty => \NLW_gen_fifo.fifo_gen_inst_axi_r_prog_empty_UNCONNECTED\,
axi_r_prog_empty_thresh(8 downto 0) => B"000000000",
axi_r_prog_full => \NLW_gen_fifo.fifo_gen_inst_axi_r_prog_full_UNCONNECTED\,
axi_r_prog_full_thresh(8 downto 0) => B"000000000",
axi_r_rd_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED\(9 downto 0),
axi_r_sbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_r_sbiterr_UNCONNECTED\,
axi_r_underflow => \NLW_gen_fifo.fifo_gen_inst_axi_r_underflow_UNCONNECTED\,
axi_r_wr_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED\(9 downto 0),
axi_w_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_w_data_count_UNCONNECTED\(9 downto 0),
axi_w_dbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_w_dbiterr_UNCONNECTED\,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => \NLW_gen_fifo.fifo_gen_inst_axi_w_overflow_UNCONNECTED\,
axi_w_prog_empty => \NLW_gen_fifo.fifo_gen_inst_axi_w_prog_empty_UNCONNECTED\,
axi_w_prog_empty_thresh(8 downto 0) => B"000000000",
axi_w_prog_full => \NLW_gen_fifo.fifo_gen_inst_axi_w_prog_full_UNCONNECTED\,
axi_w_prog_full_thresh(8 downto 0) => B"000000000",
axi_w_rd_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED\(9 downto 0),
axi_w_sbiterr => \NLW_gen_fifo.fifo_gen_inst_axi_w_sbiterr_UNCONNECTED\,
axi_w_underflow => \NLW_gen_fifo.fifo_gen_inst_axi_w_underflow_UNCONNECTED\,
axi_w_wr_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED\(9 downto 0),
axis_data_count(10 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axis_data_count_UNCONNECTED\(10 downto 0),
axis_dbiterr => \NLW_gen_fifo.fifo_gen_inst_axis_dbiterr_UNCONNECTED\,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => \NLW_gen_fifo.fifo_gen_inst_axis_overflow_UNCONNECTED\,
axis_prog_empty => \NLW_gen_fifo.fifo_gen_inst_axis_prog_empty_UNCONNECTED\,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => \NLW_gen_fifo.fifo_gen_inst_axis_prog_full_UNCONNECTED\,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axis_rd_data_count_UNCONNECTED\(10 downto 0),
axis_sbiterr => \NLW_gen_fifo.fifo_gen_inst_axis_sbiterr_UNCONNECTED\,
axis_underflow => \NLW_gen_fifo.fifo_gen_inst_axis_underflow_UNCONNECTED\,
axis_wr_data_count(10 downto 0) => \NLW_gen_fifo.fifo_gen_inst_axis_wr_data_count_UNCONNECTED\(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_data_count_UNCONNECTED\(9 downto 0),
dbiterr => \NLW_gen_fifo.fifo_gen_inst_dbiterr_UNCONNECTED\,
din(17 downto 0) => B"000000000000000000",
dout(17 downto 0) => \NLW_gen_fifo.fifo_gen_inst_dout_UNCONNECTED\(17 downto 0),
empty => \NLW_gen_fifo.fifo_gen_inst_empty_UNCONNECTED\,
full => \NLW_gen_fifo.fifo_gen_inst_full_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '1',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_arid_UNCONNECTED\(0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_arregion_UNCONNECTED\(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_aruser_UNCONNECTED\(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awid_UNCONNECTED\(0),
m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awregion_UNCONNECTED\(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awuser_UNCONNECTED\(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => '0',
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(0) => '0',
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_wid_UNCONNECTED\(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_wuser_UNCONNECTED\(0),
m_axi_wvalid => m_axi_wvalid,
m_axis_tdata(63 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axis_tdata_UNCONNECTED\(63 downto 0),
m_axis_tdest(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axis_tdest_UNCONNECTED\(3 downto 0),
m_axis_tid(7 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axis_tid_UNCONNECTED\(7 downto 0),
m_axis_tkeep(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axis_tkeep_UNCONNECTED\(3 downto 0),
m_axis_tlast => \NLW_gen_fifo.fifo_gen_inst_m_axis_tlast_UNCONNECTED\,
m_axis_tready => '0',
m_axis_tstrb(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axis_tstrb_UNCONNECTED\(3 downto 0),
m_axis_tuser(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axis_tuser_UNCONNECTED\(3 downto 0),
m_axis_tvalid => \NLW_gen_fifo.fifo_gen_inst_m_axis_tvalid_UNCONNECTED\,
overflow => \NLW_gen_fifo.fifo_gen_inst_overflow_UNCONNECTED\,
prog_empty => \NLW_gen_fifo.fifo_gen_inst_prog_empty_UNCONNECTED\,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => \NLW_gen_fifo.fifo_gen_inst_prog_full_UNCONNECTED\,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_rd_data_count_UNCONNECTED\(9 downto 0),
rd_en => '0',
rd_rst => '0',
rd_rst_busy => \NLW_gen_fifo.fifo_gen_inst_rd_rst_busy_UNCONNECTED\,
rst => '0',
s_aclk => aclk,
s_aclk_en => '1',
s_aresetn => aresetn,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(0) => '0',
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => \NLW_gen_fifo.fifo_gen_inst_s_axi_bid_UNCONNECTED\(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => \NLW_gen_fifo.fifo_gen_inst_s_axi_buser_UNCONNECTED\(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(63 downto 0) => s_axi_rdata(63 downto 0),
s_axi_rid(0) => \NLW_gen_fifo.fifo_gen_inst_s_axi_rid_UNCONNECTED\(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => \NLW_gen_fifo.fifo_gen_inst_s_axi_ruser_UNCONNECTED\(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid,
s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axis_tdest(3 downto 0) => B"0000",
s_axis_tid(7 downto 0) => B"00000000",
s_axis_tkeep(3 downto 0) => B"0000",
s_axis_tlast => '0',
s_axis_tready => \NLW_gen_fifo.fifo_gen_inst_s_axis_tready_UNCONNECTED\,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => \NLW_gen_fifo.fifo_gen_inst_sbiterr_UNCONNECTED\,
sleep => '0',
srst => '0',
underflow => \NLW_gen_fifo.fifo_gen_inst_underflow_UNCONNECTED\,
valid => \NLW_gen_fifo.fifo_gen_inst_valid_UNCONNECTED\,
wr_ack => \NLW_gen_fifo.fifo_gen_inst_wr_ack_UNCONNECTED\,
wr_clk => '0',
wr_data_count(9 downto 0) => \NLW_gen_fifo.fifo_gen_inst_wr_data_count_UNCONNECTED\(9 downto 0),
wr_en => '0',
wr_rst => '0',
wr_rst_busy => \NLW_gen_fifo.fifo_gen_inst_wr_rst_busy_UNCONNECTED\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_s00_data_fifo_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_s00_data_fifo_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_s00_data_fifo_0 : entity is "system_s00_data_fifo_0,axi_data_fifo_v2_1_21_axi_data_fifo,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_s00_data_fifo_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_s00_data_fifo_0 : entity is "axi_data_fifo_v2_1_21_axi_data_fifo,Vivado 2020.2";
end system_s00_data_fifo_0;
architecture STRUCTURE of system_s00_data_fifo_0 is
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 1;
attribute C_AXI_READ_FIFO_DELAY : integer;
attribute C_AXI_READ_FIFO_DELAY of inst : label is 1;
attribute C_AXI_READ_FIFO_DEPTH : integer;
attribute C_AXI_READ_FIFO_DEPTH of inst : label is 512;
attribute C_AXI_READ_FIFO_TYPE : string;
attribute C_AXI_READ_FIFO_TYPE of inst : label is "bram";
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WRITE_FIFO_DELAY : integer;
attribute C_AXI_WRITE_FIFO_DELAY of inst : label is 1;
attribute C_AXI_WRITE_FIFO_DEPTH : integer;
attribute C_AXI_WRITE_FIFO_DEPTH of inst : label is 512;
attribute C_AXI_WRITE_FIFO_TYPE : string;
attribute C_AXI_WRITE_FIFO_TYPE of inst : label is "bram";
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_PRIM_FIFO_TYPE : string;
attribute P_PRIM_FIFO_TYPE of inst : label is "512x72";
attribute P_READ_FIFO_DEPTH_LOG : integer;
attribute P_READ_FIFO_DEPTH_LOG of inst : label is 9;
attribute P_WIDTH_RACH : integer;
attribute P_WIDTH_RACH of inst : label is 60;
attribute P_WIDTH_RDCH : integer;
attribute P_WIDTH_RDCH of inst : label is 69;
attribute P_WIDTH_WACH : integer;
attribute P_WIDTH_WACH of inst : label is 60;
attribute P_WIDTH_WDCH : integer;
attribute P_WIDTH_WDCH of inst : label is 75;
attribute P_WIDTH_WRCH : integer;
attribute P_WIDTH_WRCH of inst : label is 4;
attribute P_WRITE_FIFO_DEPTH_LOG : integer;
attribute P_WRITE_FIFO_DEPTH_LOG of inst : label is 9;
attribute downgradeipidentifiedwarnings of inst : label is "yes";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of m_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of m_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_INFO of m_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
attribute X_INTERFACE_INFO of m_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
attribute X_INTERFACE_INFO of m_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
attribute X_INTERFACE_INFO of m_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of m_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARQOS";
attribute X_INTERFACE_INFO of m_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of m_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
attribute X_INTERFACE_INFO of m_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
attribute X_INTERFACE_INFO of m_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
attribute X_INTERFACE_INFO of m_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of m_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWQOS";
attribute X_INTERFACE_INFO of m_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS";
attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS";
attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
inst: entity work.system_s00_data_fifo_0_axi_data_fifo_v2_1_21_axi_data_fifo
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => '0',
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(0) => '0',
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(0) => '0',
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(63 downto 0) => s_axi_rdata(63 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_sin_taylor_ser is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Block_sin_taylor_ser is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal grp_fu_18_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_18_ce : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_return_preg : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component sin_taylor_seriesfYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesfYi_U12 : component sin_taylor_seriesfYi
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => p_read,
din1 => p_read1,
ce => grp_fu_18_ce,
dout => grp_fu_18_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv64_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return_preg <= grp_fu_18_p2;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(grp_fu_18_p2, ap_CS_fsm_state5, ap_return_preg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return <= grp_fu_18_p2;
else
ap_return <= ap_return_preg;
end if;
end process;
grp_fu_18_ce_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1)))) then
grp_fu_18_ce <= ap_const_logic_0;
else
grp_fu_18_ce <= ap_const_logic_1;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LZC_20_tb is
end LZC_20_tb;
architecture driver of LZC_20_tb is
component LZC_20 is
port(
in_20: in std_logic_vector(19 downto 0);
count: out std_logic_vector(4 downto 0)
);
end component;
signal tb_in_20: std_logic_vector(19 downto 0) := (others => '0') ;
signal tb_count: std_logic_vector(4 downto 0);
begin
UUT: LZC_20 port map ( in_20 => tb_in_20,
count => tb_count);
tb_in_20 <= "11101010101000010101" after 20ns,
"01101100100111101111" after 30ns,
"00100101001010001100" after 40ns,
"00011000100010101001" after 50ns,
"00001110010110001111" after 60ns,
"00000101010101100111" after 70ns,
"00000011010000001111" after 80ns,
"00000001000000010010" after 90ns,
"00000000101010001110" after 100ns,
"00000000010101000111" after 110ns,
"00000000001010001110" after 120ns,
"00000000000101000111" after 130ns,
"00000000000010001110" after 140ns,
"00000000000001001110" after 150ns,
"00000000000000101110" after 160ns,
"00000000000000011110" after 170ns,
"00000000000000001110" after 180ns,
"00000000000000000110" after 190ns,
"00000000000000000010" after 200ns,
"00000000000000000000" after 210ns;
end architecture;
|
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<KEY>
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<KEY>
`protect end_protected
|
------------------------------------------------------------------------------------------------
-- WWW.DEADLINE-DESIGN.COM --
------------------------------------------------------------------------------------------------
-- --
-- This software representation and its inclusive documentation are provided AS-IS and with --
-- all faults; is without warranty expressed or implied, including but not limited to, --
-- warranties of merchantability or fitness for a particular purpose. --
-- --
-- All trademarks are the property of their respective owners. --
-- --
-- DESIGN UNITS : gray_counter_TSTR(testbench1) --
-- --
-- FILE NAME : gray_counter_TSTR.vhd --
-- --
-- PURPOSE : The purpose of this design unit is to provide a very simplistic testbench --
-- for the pgray_counter_TSTR(dynamic) design unit. --
-- --
-- NOTE : This testbench does utilize certain elements contained within the --
-- D_D_pkg PACKAGE (D_D_pkg.vhd). Be sure to compile the package into the --
-- DEADLINE LIBRARY prior to compiling this testbench into the DEADLINE --
-- LIBRARY. --
-- --
-- This testbench does utilize the gray_count_bit(ver1) primitive --
-- (gray_count_bit.vhd). Be sure to compile the primitive into the --
-- DEADLINE LIBRARY prior to compiling this testbench into the --
-- DEADLINE LIBRARY. --
-- --
-- This testbench does utilize the gray_counter(ver1) counter --
-- (gray_counter.vhd). Be sure to compile the peripheral into the --
-- DEADLINE LIBRARY prior to compiling this testbench into the --
-- DEADLINE LIBRARY. --
-- --
-- LIMITATIONS : N/A. --
-- --
-- ERRORS : No known errors. --
-- --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- MODULE HISTORY --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- --
-- VERSION AUTHOR DATE COMMENTS --
-- 0.0 D-D 09 Feb 22 - Created. --
-- --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- LIBRARY UTILIZATION(S) --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY DEADLINE;
USE DEADLINE.ALL;
USE DEADLINE.D_D_pkg.ALL;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- ENTITY and ARCHITECTURE(S) --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
ENTITY gray_counter_TSTR IS
END gray_counter_TSTR;
ARCHITECTURE testbench1 OF gray_counter_TSTR IS
------------------------------
-- COMPONENT DECLARATION(S) --
------------------------------
COMPONENT gray_counter IS
GENERIC (
CLOCK_POL_RISING : BOOLEAN := TRUE;
WIDTH : INTEGER := 2
);
PORT (
i_reset : IN STD_LOGIC;
i_clock : IN STD_LOGIC;
i_count_enable : IN STD_LOGIC;
o_gray_count : OUT STD_LOGIC_VECTOR((WIDTH-1) DOWNTO 0)
);
END COMPONENT;
---------------
-- CONSTANTS --
---------------
CONSTANT tSYSCLKPER : TIME := 20 nS;
CONSTANT GRAY_COUNTER_WIDTH : INTEGER := 6;
-------------
-- SIGNALS --
-------------
SIGNAL sys_reset : STD_LOGIC := '1';
SIGNAL sys_enable : STD_LOGIC := '0';
SIGNAL sys_clock : STD_LOGIC := '0';
SIGNAL sys_gray_count : STD_LOGIC_VECTOR((GRAY_COUNTER_WIDTH-1) DOWNTO 0);
BEGIN
SYSCLKGEN: sys_clock <= NOT(sys_clock) AFTER tSYSCLKPER/2;
STIM: PROCESS
BEGIN
WAIT FOR tSYSCLKPER * GRAY_COUNTER_WIDTH; -- Wait
WAIT UNTIL FALLING_EDGE(sys_clock);
sys_reset <= '0'; -- De-assert reset
WAIT FOR tSYSCLKPER * GRAY_COUNTER_WIDTH; -- Wait
WAIT UNTIL FALLING_EDGE(sys_clock);
sys_enable <= '1'; -- Assert count enable
WAIT FOR tSYSCLKPER * 4 *(2**(GRAY_COUNTER_WIDTH+1)); -- Wait (cycle through 4X's)
WAIT FOR tSYSCLKPER * GRAY_COUNTER_WIDTH; -- Wait
WAIT UNTIL FALLING_EDGE(sys_clock);
sys_enable <= '0'; -- De-assert count enable
WAIT FOR tSYSCLKPER * GRAY_COUNTER_WIDTH; -- Wait
WAIT UNTIL FALLING_EDGE(sys_clock);
sys_reset <= '1'; -- Assert reset
WAIT FOR tSYSCLKPER * GRAY_COUNTER_WIDTH; -- Wait
--------------------
-- END SIMULATION --
--------------------
ASSERT (FALSE)
REPORT "END OF SIMULATION"
SEVERITY FAILURE;
END PROCESS;
------------------------------------------------------------------------------------------------
-- GRAY COUNTER MODULES UNDER TEST --
------------------------------------------------------------------------------------------------
GRAYCNTUT: gray_counter GENERIC MAP (
CLOCK_POL_RISING => TRUE,
WIDTH => GRAY_COUNTER_WIDTH
)
PORT MAP (
i_reset => sys_reset,
i_clock => sys_clock,
i_count_enable => sys_enable,
o_gray_count => sys_gray_count
);
END testbench1;
-------------------------------------------- END OF CODE ---------------------------------------
|
-- IVH - Seminar VHDL
-- Projekt 3
-- xtotha01
-- <NAME>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.maskpack.ALL; -- proj1
--===============================================================================================
entity cell is
GENERIC (
MASK : mask_t := (others => '1') -- mask_t from math_pack(proj1)
);
Port (
INVERT_REQ_IN : in STD_LOGIC_VECTOR (3 downto 0);
INVERT_REQ_OUT : out STD_LOGIC_VECTOR (3 downto 0);
KEYS : in STD_LOGIC_VECTOR (4 downto 0);
SELECT_REQ_IN : in STD_LOGIC_VECTOR (3 downto 0);
SELECT_REQ_OUT : out STD_LOGIC_VECTOR (3 downto 0);
INIT_ACTIVE : in STD_LOGIC;
ACTIVE : out STD_LOGIC;
INIT_SELECTED : in STD_LOGIC;
SELECTED : out STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end cell;
--===============================================================================================
architecture Behavioral of cell is
constant IDX_TOP : NATURAL := 0; -- index sousedni bunky nachazejici se nahore v signalech *_REQ_IN a *_REQ_OUT, index klavesy posun nahoru v KEYSS
constant IDX_LEFT : NATURAL := 1; -- ... totez ... vlevo
constant IDX_RIGHT : NATURAL := 2; -- ... totez ... vpravo
constant IDX_BOTTOM : NATURAL := 3; -- ... totez ... dole
constant IDX_ENTER : NATURAL := 4; -- index klavesy v KEYSS, zpusobujici inverzi bunky (enter, klavesa 5)
signal active_sig : STD_LOGIC;
signal selected_sig : STD_LOGIC;
begin
--OK Pozadavky na funkci (sekvencni chovani vazane na vzestupnou hranu CLK)
--OK pri resetu se nastavi ACTIVE a SELECTED na vychozi hodnotu danou signaly INIT_ACTIVE a INIT_SELECTED
--OK pokud je bunka aktivni a prijde signal z klavesnice, tak se bud presune aktivita pomoci SELECT_REQ na dalsi bunky nebo se invertuje stav bunky a jejiho okoli pomoci INVERT_REQ (klavesa ENTER)
--OK pokud bunka neni aktivni a prijde signal INVERT_REQ, invertuje svuj stav
--OK pozadavky do okolnich bunek se posilaji a z okolnich bunek prijimaji, jen pokud je maska na prislusne pozici v '1'
process (CLK, RESET)
begin
-- pri resetu se nastavi ACTIVE a SELECTED na vychozi hodnotu danou signaly INIT_ACTIVE a INIT_SELECTED
-- reseting cell
if ( RESET = '1' ) then
active_sig <= INIT_ACTIVE;
selected_sig <= INIT_SELECTED;
-- Pozadavky na funkci (sekvencni chovani vazane na vzestupnou hranu CLK)
-- Pozadavky do okolnich bunek se posilaji a z okolnich bunek prijimaji, jen pokud je maska na prislusne pozici v '1'
elsif rising_edge(CLK) then
-- erasing previous values for SELECT
SELECT_REQ_OUT(IDX_TOP) <= '0';
SELECT_REQ_OUT(IDX_LEFT) <= '0';
SELECT_REQ_OUT(IDX_RIGHT) <= '0';
SELECT_REQ_OUT(IDX_BOTTOM) <= '0';
-- erasing previous values for INVERT
INVERT_REQ_OUT(IDX_TOP) <= '0';
INVERT_REQ_OUT(IDX_LEFT) <= '0';
INVERT_REQ_OUT(IDX_RIGHT) <= '0';
INVERT_REQ_OUT(IDX_BOTTOM) <= '0';
-- pokud je bunka aktivni a prijde signal z klavesnice, tak se bud presune aktivita
-- pomoci SELECT_REQ na dalsi bunky nebo se invertuje stav bunky a jejiho okoli
-- pomoci INVERT_REQ (klavesa ENTER)
if ( selected_sig = '1' ) then
-- skip from selected cell to another direction (up-top,left,right,down-bottom)
-- if neighbor exits
if ( KEYS(IDX_TOP) = '1' and MASK.top = '1' ) then
SELECT_REQ_OUT(IDX_TOP) <= '1';
selected_sig <= '0';
end if;
if ( KEYS(IDX_LEFT) = '1' and MASK.left = '1' ) then
SELECT_REQ_OUT(IDX_LEFT) <= '1';
selected_sig <= '0';
end if;
if ( KEYS(IDX_RIGHT) = '1' and MASK.right = '1' ) then
SELECT_REQ_OUT(IDX_RIGHT) <= '1';
selected_sig <= '0';
end if;
if ( KEYS(IDX_BOTTOM) = '1' and MASK.bottom = '1' ) then
SELECT_REQ_OUT(IDX_BOTTOM) <= '1';
selected_sig <= '0';
end if;
-- cell is selected and inverted(ENTER was pressed)
-- invert myself
-- send invert request to neigbor cells (top,left,right,bottom)
if ( KEYS(IDX_ENTER) = '1' ) then
active_sig <= not active_sig;
if ( MASK.top = '1' ) then
INVERT_REQ_OUT(IDX_TOP) <= '1';
end if;
if ( MASK.left = '1' ) then
INVERT_REQ_OUT(IDX_LEFT) <= '1';
end if;
if ( MASK.right = '1' ) then
INVERT_REQ_OUT(IDX_RIGHT) <= '1';
end if;
if ( MASK.bottom = '1' ) then
INVERT_REQ_OUT(IDX_BOTTOM) <= '1';
end if;
end if;
end if;
-- pokud bunka neni aktivni a prijde signal INVERT_REQ, invertuje svuj stav
-- cell got request to invert from neighbor cell
if (selected_sig = '0') then
if ( INVERT_REQ_IN(IDX_TOP) = '1' and MASK.top = '1') then
active_sig <= not active_sig;
end if;
if ( INVERT_REQ_IN(IDX_LEFT) = '1' and MASK.left = '1') then
active_sig <= not active_sig;
end if;
if ( INVERT_REQ_IN(IDX_RIGHT) = '1' and MASK.right = '1') then
active_sig <= not active_sig;
end if;
if ( INVERT_REQ_IN(IDX_BOTTOM) = '1' and MASK.bottom = '1') then
active_sig <= not active_sig;
end if;
if ( SELECT_REQ_IN(IDX_TOP) = '1' and MASK.top = '1' ) then
selected_sig <= '1';
end if;
if ( SELECT_REQ_IN(IDX_LEFT) = '1' and MASK.left = '1' ) then
selected_sig <= '1';
end if;
if ( SELECT_REQ_IN(IDX_RIGHT) = '1' and MASK.right = '1' ) then
selected_sig <= '1';
end if;
if ( SELECT_REQ_IN(IDX_BOTTOM) = '1' and MASK.bottom = '1' ) then
selected_sig <= '1';
end if;
end if;
end if;
end process;
ACTIVE <= active_sig;
SELECTED <= selected_sig;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Common.all;
entity AluOpEncoder is
port (
-- Interface --
op : in std_logic_vector(5 downto 0);
func : in std_logic_vector(5 downto 0);
rt : in std_logic_vector(4 downto 0);
aluop : out AluOpType
);
end AluOpEncoder;
architecture Behavioral of AluOpEncoder is
signal special, regimm : AluOpType;
begin
with func select special <=
ALU_SLL when func_sll,
ALU_SRL when func_srl,
ALU_SRA when func_sra,
ALU_SLL when func_sllv,
ALU_SRL when func_srlv,
ALU_SRA when func_srav,
ALU_MUL when func_mult,
ALU_MULU when func_multu,
ALU_ADD when func_addu,
ALU_SUB when func_subu,
ALU_AND when func_and,
ALU_OR when func_or,
ALU_XOR when func_xor,
ALU_NOR when func_nor,
ALU_LT when func_slt,
ALU_LTU when func_sltu,
ALU_NOP when others;
with rt select regimm <=
ALU_LT when rt_bltz,
ALU_GEZ when rt_bgez,
ALU_NOP when others;
with op select aluop <=
special when op_special,
regimm when op_regimm,
ALU_EQ when op_beq,
ALU_NE when op_bne,
ALU_LEZ when op_blez,
ALU_GTZ when op_bgtz,
ALU_ADD when op_addiu,
ALU_LT when op_slti,
ALU_LTU when op_sltiu,
ALU_AND when op_andi,
ALU_OR when op_ori,
ALU_XOR when op_xori,
ALU_SLL when op_lui,
ALU_ADD when op_lb | op_lw | op_lbu | op_sb | op_sw,
ALU_NOP when others;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clear is
port (
start : in std_logic;
wren : out std_logic;
addr : out std_logic_vector(13 downto 0);
done : out std_logic
);
end clear;
architecture clear of clear is
signal addrR : std_logic_vector(13 downto 0);
signal addrN : std_logic_vector(13 downto 0);
begin
addr <= addrR;
process
begin
if clock'event and clock = '1' then
if start = '1' then
addrR <= 0;
else
addrR <= std_logic_vector( signed(addrR) + 1 );
end if;
----------------------------------------------
if addrR = "11111111111111" then
done <= '1';
else
done <= '0';
end if;
end if;
end process;
end clear;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
|
package CONSTANTS is
constant NumBit : integer := 16;
end package CONSTANTS;
|
--
-- vid_packer.vhd
--
-- Crops oa configurable window out of a video stream
--
--
-- Copyright (C) 2015 <NAME> <<EMAIL>>
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- vim: ts=4 sw=4
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.utils_pkg.all;
entity vid_crop is
generic (
DATA_WIDTH : integer := 32;
CNT_WIDTH : integer := 12
);
port (
-- Input
in_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
in_last : in std_logic;
in_sof : in std_logic;
in_valid : in std_logic;
-- Output
out_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
out_last : out std_logic;
out_sof : out std_logic;
out_valid : out std_logic;
-- Config
win_cs : in std_logic_vector(CNT_WIDTH-1 downto 0);
win_ce : in std_logic_vector(CNT_WIDTH-1 downto 0);
win_ls : in std_logic_vector(CNT_WIDTH-1 downto 0);
win_le : in std_logic_vector(CNT_WIDTH-1 downto 0);
-- Clock / Reset
clk : in std_logic;
rst : in std_logic
);
end vid_crop;
architecture rtl of vid_crop is
signal last_1 : std_logic;
signal last_2 : std_logic;
signal last_3 : std_logic;
signal sof_1 : std_logic;
signal sof_2 : std_logic;
signal sof_3 : std_logic;
signal valid_1 : std_logic;
signal valid_2 : std_logic;
signal valid_3 : std_logic;
signal data_3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal cnt_col_1 : std_logic_vector(CNT_WIDTH-1 downto 0);
signal cnt_line_1 : std_logic_vector(CNT_WIDTH-1 downto 0);
signal win_cs_ok_2 : std_logic;
signal win_ce_ok_2 : std_logic;
signal win_ls_ok_2 : std_logic;
signal win_le_ok_2 : std_logic;
signal win_ce_last_2 : std_logic;
signal win_ok_2 : std_logic;
begin
-- Position counters
----------------------
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
cnt_col_1 <= (others => '0');
cnt_line_1 <= (others => '0');
else
if in_sof = '1' and in_valid = '1' then
cnt_col_1 <= (others => '0');
cnt_line_1 <= (others => '0');
elsif valid_1 = '1' then
if last_1 = '1' then
cnt_col_1 <= (others => '0');
cnt_line_1 <= cnt_line_1 + 1;
else
cnt_col_1 <= cnt_col_1 + 1;
end if;
end if;
end if;
end if;
end process;
-- Comparators
----------------
process (clk)
begin
if rising_edge(clk) then
win_cs_ok_2 <= btsl(cnt_col_1 >= win_cs);
win_ce_ok_2 <= btsl(cnt_col_1 <= win_ce);
win_ls_ok_2 <= btsl(cnt_line_1 >= win_ls);
win_le_ok_2 <= btsl(cnt_line_1 <= win_le);
win_ce_last_2 <= btsl(cnt_col_1 = win_ce);
end if;
end process;
win_ok_2 <= win_cs_ok_2 and win_ce_ok_2 and win_ls_ok_2 and win_le_ok_2;
-- Flags
----------
process (clk)
begin
if rising_edge(clk) then
-- Last flag
last_1 <= in_last;
last_2 <= last_1;
last_3 <= valid_2 and win_ok_2 and (last_2 or win_ce_last_2);
-- SOF
sof_1 <= in_sof;
sof_2 <= sof_1;
if sof_2 = '1' and valid_2 = '1' then
sof_3 <= '1';
elsif valid_3 = '1' then
sof_3 <= '0';
end if;
-- Valid flag
valid_1 <= in_valid;
valid_2 <= valid_1;
valid_3 <= valid_2 and win_ok_2;
end if;
end process;
-- Data delay
---------------
data_dly_I: delay_bus
generic map (
DELAY => 3,
WIDTH => DATA_WIDTH
)
port map (
d => in_data,
q => data_3,
qp => open,
clk => clk
);
-- Output
-----------
out_data <= data_3;
out_last <= last_3;
out_sof <= sof_3;
out_valid <= valid_3;
end rtl;
|
<filename>D_7SEG/testbench.vhd
-- Insert library and use clauses
library ieee;
use IEEE.std_logic_textio.all;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
use IEEE.numeric_std.all;
ENTITY testbench IS
generic (
ASIZE : integer := 23;
DSIZE : integer := 32;
ROWSIZE : integer := 13;
COLSIZE : integer := 9;
BANKSIZE : integer := 2;
ROWSTART : integer := 9;
COLSTART : integer := 0;
BANKSTART : integer := 20;
DATA_ADDR_SIZE : integer := 32;
WORD_SIZE : integer := 32;
-- SDRAM latencies
DATA_AVAL : integer := 2; -- cycles
RESET_NOP : integer := 4; -- cycles
RAS_TO_CAS : integer := 2; -- cycles
PRE_TO_ACT : integer := 3 -- cycles
);
END ENTITY testbench;
ARCHITECTURE stimulus OF testbench IS
component tcs230
port (
clk : in std_logic;
rst : in std_logic;
freq_sel : in std_logic_vector(1 downto 0);
s_out : out std_logic_vector(3 downto 0); -- Filter selection
data_in : in std_logic -- sensor data input
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal s : std_logic_vector(3 downto 0);
signal data : std_logic;
signal data_0, data_1, sel : std_logic;
BEGIN -- beginning of architecture body
tcs230_0: tcs230 port map (
clk => clk,
rst => reset,
freq_sel => "11",
s_out => s,
data_in => data
);
-- Process to create clock signal -- 50Mhz
clk_proc : process
begin
clk <= '0';
wait for 500 ns;
clk <= '1';
wait for 500 ns;
end process;
reset_p : process
begin
reset <= '1';
WAIT FOR 1 us;
reset <= '0';
wait;
end process;
data_sim_f0: process
begin
data_0 <= '0';
wait for 2 us;
data_0 <= '1';
wait for 2 us;
end process;
data_sim_f1: process
begin
data_1 <= '0';
wait for 1 us;
data_1 <= '1';
wait for 1 us;
end process;
--LCD_EN <= '1' when (enable = '1') and count = 1 else '0';
sel <= '0', '1' AFTER 40 us;
data <= data_0 when (sel = '0') else data_1;
END ARCHITECTURE stimulus;
|
<reponame>mtrberzi/ym2608
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:09:21 08/02/2014
-- Design Name:
-- Module Name: signal_generator_sampled - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity signal_generator_sampled is
Port ( clk : in STD_LOGIC;
nxt : in STD_LOGIC;
sample: out signed(19 downto 0));
end signal_generator_sampled;
architecture Behavioral of signal_generator_sampled is
component sample_rom port (
clka: in std_logic;
addra: in std_logic_vector(17 downto 0);
douta: out std_logic_vector(15 downto 0)
); end component;
signal addr: std_logic_vector(17 downto 0) := (others=>'0');
constant addr_hi: unsigned(17 downto 0) := to_unsigned(233138-1, 18);
constant resample_scale: unsigned(1 downto 0) := "10"; -- resample by 3 (16000Hz samples)
signal resample: unsigned(1 downto 0) := resample_scale;
signal data: std_logic_vector(15 downto 0);
begin
process(clk, nxt, addr, resample)
variable addr_u: unsigned(17 downto 0);
variable next_addr: unsigned(17 downto 0);
variable resample_next: unsigned(1 downto 0);
begin
addr_u := unsigned(addr);
next_addr := addr_u;
resample_next := resample;
if(nxt = '1') then
if(resample = "00") then
resample_next := resample_scale;
if(addr_u = addr_hi) then
next_addr := to_unsigned(0, 18);
else
next_addr := addr_u + 1;
end if;
else
resample_next := resample - 1;
end if;
end if;
if(rising_edge(clk)) then
addr <= std_logic_vector(next_addr);
resample <= resample_next;
end if;
end process;
sample <= signed(data & "0000");
ROM: sample_rom port map (
clka => clk,
addra => addr,
douta => data
);
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.stdtap.all;
entity MachXO2_TAP is
generic (
-- The IDCODE is just kept here for interface compatibility
-- For MACHXO2 platforms, it is specified in the .lpf file
IDCODE : std_logic_vector(32-1 downto 0) := x"00000000"
);
port (
-- JTAG signals (dedicated pins on MACHXO2)
reset : in std_logic;
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
-- Core <-> TAP signals:
tin : in tap_in_rec;
tout : out tap_out_rec
);
end MachXO2_TAP;
architecture sim of MachXO2_TAP is
begin
process
begin
tout.emurequest <= '0';
tout.core_reset <= '0';
wait for 5 us;
tout.core_reset <= '1';
wait for 1 us;
tout.core_reset <= '0';
wait;
end process;
end sim;
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.stdtap.all;
entity ECP3_TAP is
generic (
-- The IDCODE is just kept here for interface compatibility
-- For ECP3 platforms, it is specified in the .lpf file
IDCODE : std_logic_vector(32-1 downto 0) := x"00000000"
);
port (
-- JTAG signals (dedicated pins on ECP3)
reset : in std_logic;
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
-- Core <-> TAP signals:
tin : in tap_in_rec;
tout : out tap_out_rec
);
end ECP3_TAP;
architecture sim of ECP3_TAP is
begin
process
begin
tout.emurequest <= '0';
tout.core_reset <= '0';
wait for 5 us;
tout.core_reset <= '1';
wait for 1 us;
tout.core_reset <= '0';
wait;
end process;
end sim;
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.stdtap.all;
entity ECP5_TAP is
generic (
-- The IDCODE is just kept here for interface compatibility
-- For ECP3 platforms, it is specified in the .lpf file
IDCODE : std_logic_vector(32-1 downto 0) := x"00000000"
);
port (
reset : in std_logic;
-- JTAG signals (dedicated pins on ECP3)
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
-- Core <-> TAP signals:
tin : in tap_in_rec;
tout : out tap_out_rec
);
end ECP5_TAP;
architecture sim of ECP5_TAP is
begin
process
begin
tout.emurequest <= '0';
tout.core_reset <= '0';
wait for 5 us;
tout.core_reset <= '1';
wait for 1 us;
tout.core_reset <= '0';
wait;
end process;
end sim;
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.stdtap.all;
entity Spartan3_TAP is
generic (
-- The IDCODE is just kept here for interface compatibility
-- For ECP3 platforms, it is specified in the .lpf file
IDCODE : std_logic_vector(32-1 downto 0) := x"00000000"
);
port (
-- JTAG signals (dedicated pins on ECP3)
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
-- Core <-> TAP signals:
tin : in tap_in_rec;
tout : out tap_out_rec
);
end Spartan3_TAP;
architecture sim of Spartan3_TAP is
begin
process
begin
tout.emurequest <= '0';
tout.core_reset <= '0';
wait for 5 us;
tout.core_reset <= '1';
wait for 1 us;
tout.core_reset <= '0';
wait;
end process;
end sim;
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.stdtap.all;
entity Spartan6_TAP is
generic (
-- The IDCODE is just kept here for interface compatibility
-- For ECP3 platforms, it is specified in the .lpf file
IDCODE : std_logic_vector(32-1 downto 0) := x"00000000"
);
port (
-- JTAG signals (dedicated pins on ECP3)
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
-- Core <-> TAP signals:
tin : in tap_in_rec;
tout : out tap_out_rec
);
end Spartan6_TAP;
architecture sim of Spartan6_TAP is
begin
process
begin
tout.emurequest <= '0';
tout.core_reset <= '0';
wait for 5 us;
tout.core_reset <= '1';
wait for 1 us;
tout.core_reset <= '0';
wait;
end process;
end sim;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SubRS is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_0_V_empty_n : IN STD_LOGIC;
src_data_stream_0_V_read : OUT STD_LOGIC;
src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_1_V_empty_n : IN STD_LOGIC;
src_data_stream_1_V_read : OUT STD_LOGIC;
src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_2_V_empty_n : IN STD_LOGIC;
src_data_stream_2_V_read : OUT STD_LOGIC;
dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst_data_stream_0_V_full_n : IN STD_LOGIC;
dst_data_stream_0_V_write : OUT STD_LOGIC;
dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst_data_stream_1_V_full_n : IN STD_LOGIC;
dst_data_stream_1_V_write : OUT STD_LOGIC;
dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst_data_stream_2_V_full_n : IN STD_LOGIC;
dst_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of SubRS is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv10_2D0 : STD_LOGIC_VECTOR (9 downto 0) := "1011010000";
constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_const_lv11_500 : STD_LOGIC_VECTOR (10 downto 0) := "10100000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv9_FA : STD_LOGIC_VECTOR (8 downto 0) := "011111010";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal src_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_reg_333 : STD_LOGIC_VECTOR (0 downto 0);
signal src_data_stream_1_V_blk_n : STD_LOGIC;
signal src_data_stream_2_V_blk_n : STD_LOGIC;
signal dst_data_stream_0_V_blk_n : STD_LOGIC;
signal dst_data_stream_1_V_blk_n : STD_LOGIC;
signal dst_data_stream_2_V_blk_n : STD_LOGIC;
signal t_V_1_reg_196 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond1_i_fu_207_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_V_fu_213_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal i_V_reg_328 : STD_LOGIC_VECTOR (9 downto 0);
signal exitcond_i_fu_219_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal j_V_fu_225_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal t_V_reg_185 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_state1 : BOOLEAN;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal rhs_V_i_fu_231_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_Val2_1_fu_235_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_fu_241_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_2_fu_249_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal rhs_V_1_i_fu_262_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_Val2_4_fu_266_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_fu_272_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_5_fu_280_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal rhs_V_2_i_fu_293_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_Val2_s_fu_297_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_4_fu_303_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_7_fu_311_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond1_i_fu_207_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((exitcond1_i_fu_207_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((exitcond1_i_fu_207_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
t_V_1_reg_196_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_219_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
t_V_1_reg_196 <= j_V_fu_225_p2;
elsif (((exitcond1_i_fu_207_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
t_V_1_reg_196 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_185_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
t_V_reg_185 <= i_V_reg_328;
elsif ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
t_V_reg_185 <= ap_const_lv10_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
exitcond_i_reg_333 <= exitcond_i_fu_219_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_V_reg_328 <= i_V_fu_213_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, exitcond1_i_fu_207_p2, ap_CS_fsm_state2, exitcond_i_fu_219_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((exitcond1_i_fu_207_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (not(((exitcond_i_fu_219_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((exitcond_i_fu_219_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state5 <= ap_CS_fsm(3);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(src_data_stream_0_V_empty_n, src_data_stream_1_V_empty_n, src_data_stream_2_V_empty_n, dst_data_stream_0_V_full_n, dst_data_stream_1_V_full_n, dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_333)
begin
ap_block_pp0_stage0_01001 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_0_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_0_V_empty_n = ap_const_logic_0))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(src_data_stream_0_V_empty_n, src_data_stream_1_V_empty_n, src_data_stream_2_V_empty_n, dst_data_stream_0_V_full_n, dst_data_stream_1_V_full_n, dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_333)
begin
ap_block_pp0_stage0_11001 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_0_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_0_V_empty_n = ap_const_logic_0))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(src_data_stream_0_V_empty_n, src_data_stream_1_V_empty_n, src_data_stream_2_V_empty_n, dst_data_stream_0_V_full_n, dst_data_stream_1_V_full_n, dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_333)
begin
ap_block_pp0_stage0_subdone <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_0_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_0_V_empty_n = ap_const_logic_0))));
end process;
ap_block_state1_assign_proc : process(real_start, ap_done_reg)
begin
ap_block_state1 <= ((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(src_data_stream_0_V_empty_n, src_data_stream_1_V_empty_n, src_data_stream_2_V_empty_n, dst_data_stream_0_V_full_n, dst_data_stream_1_V_full_n, dst_data_stream_2_V_full_n, exitcond_i_reg_333)
begin
ap_block_state4_pp0_stage0_iter1 <= (((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (dst_data_stream_0_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_333 = ap_const_lv1_0) and (src_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_i_fu_219_p2)
begin
if ((exitcond_i_fu_219_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond1_i_fu_207_p2, ap_CS_fsm_state2)
begin
if (((exitcond1_i_fu_207_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
dst_data_stream_0_V_blk_n_assign_proc : process(dst_data_stream_0_V_full_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_333)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
dst_data_stream_0_V_blk_n <= dst_data_stream_0_V_full_n;
else
dst_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
dst_data_stream_0_V_din <=
ap_const_lv8_0 when (tmp_fu_241_p3(0) = '1') else
p_Val2_2_fu_249_p1;
dst_data_stream_0_V_write_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_333, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
dst_data_stream_0_V_write <= ap_const_logic_1;
else
dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
dst_data_stream_1_V_blk_n_assign_proc : process(dst_data_stream_1_V_full_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_333)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
dst_data_stream_1_V_blk_n <= dst_data_stream_1_V_full_n;
else
dst_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
dst_data_stream_1_V_din <=
ap_const_lv8_0 when (tmp_2_fu_272_p3(0) = '1') else
p_Val2_5_fu_280_p1;
dst_data_stream_1_V_write_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_333, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
dst_data_stream_1_V_write <= ap_const_logic_1;
else
dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
dst_data_stream_2_V_blk_n_assign_proc : process(dst_data_stream_2_V_full_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_333)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
dst_data_stream_2_V_blk_n <= dst_data_stream_2_V_full_n;
else
dst_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
dst_data_stream_2_V_din <=
ap_const_lv8_0 when (tmp_4_fu_303_p3(0) = '1') else
p_Val2_7_fu_311_p1;
dst_data_stream_2_V_write_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_333, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
dst_data_stream_2_V_write <= ap_const_logic_1;
else
dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
exitcond1_i_fu_207_p2 <= "1" when (t_V_reg_185 = ap_const_lv10_2D0) else "0";
exitcond_i_fu_219_p2 <= "1" when (t_V_1_reg_196 = ap_const_lv11_500) else "0";
i_V_fu_213_p2 <= std_logic_vector(unsigned(t_V_reg_185) + unsigned(ap_const_lv10_1));
internal_ap_ready_assign_proc : process(exitcond1_i_fu_207_p2, ap_CS_fsm_state2)
begin
if (((exitcond1_i_fu_207_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
j_V_fu_225_p2 <= std_logic_vector(unsigned(t_V_1_reg_196) + unsigned(ap_const_lv11_1));
p_Val2_1_fu_235_p2 <= std_logic_vector(unsigned(ap_const_lv9_FA) - unsigned(rhs_V_i_fu_231_p1));
p_Val2_2_fu_249_p1 <= p_Val2_1_fu_235_p2(8 - 1 downto 0);
p_Val2_4_fu_266_p2 <= std_logic_vector(unsigned(ap_const_lv9_FA) - unsigned(rhs_V_1_i_fu_262_p1));
p_Val2_5_fu_280_p1 <= p_Val2_4_fu_266_p2(8 - 1 downto 0);
p_Val2_7_fu_311_p1 <= p_Val2_s_fu_297_p2(8 - 1 downto 0);
p_Val2_s_fu_297_p2 <= std_logic_vector(unsigned(ap_const_lv9_FA) - unsigned(rhs_V_2_i_fu_293_p1));
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (start_full_n = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
rhs_V_1_i_fu_262_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(src_data_stream_1_V_dout),9));
rhs_V_2_i_fu_293_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(src_data_stream_2_V_dout),9));
rhs_V_i_fu_231_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(src_data_stream_0_V_dout),9));
src_data_stream_0_V_blk_n_assign_proc : process(src_data_stream_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_333)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
src_data_stream_0_V_blk_n <= src_data_stream_0_V_empty_n;
else
src_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
src_data_stream_0_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_333, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
src_data_stream_0_V_read <= ap_const_logic_1;
else
src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
src_data_stream_1_V_blk_n_assign_proc : process(src_data_stream_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_333)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
src_data_stream_1_V_blk_n <= src_data_stream_1_V_empty_n;
else
src_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
src_data_stream_1_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_333, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
src_data_stream_1_V_read <= ap_const_logic_1;
else
src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
src_data_stream_2_V_blk_n_assign_proc : process(src_data_stream_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_333)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
src_data_stream_2_V_blk_n <= src_data_stream_2_V_empty_n;
else
src_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
src_data_stream_2_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_333, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_333 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
src_data_stream_2_V_read <= ap_const_logic_1;
else
src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
tmp_2_fu_272_p3 <= p_Val2_4_fu_266_p2(8 downto 8);
tmp_4_fu_303_p3 <= p_Val2_s_fu_297_p2(8 downto 8);
tmp_fu_241_p3 <= p_Val2_1_fu_235_p2(8 downto 8);
end behav;
|
<reponame>bravo95/SecondProcessor
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity regis is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC := '0' ;
datain : in STD_LOGIC_VECTOR (31 downto 0) := x"00000000" ;
dataout : out STD_LOGIC_VECTOR (31 downto 0) := x"00000000" );
end regis;
architecture Behavioral of regis is
signal res: std_logic_vector(31 downto 0):= x"00000000";
begin
res <= datain;
process (clk, rst)
begin
if (clk'event and clk = '1' and rst = '0') then
if datain = "00000000000000000000000001000000" then
dataout<= "00000000000000000000000000000000";
else
dataout <= res;
end if;
end if;
if (rst = '1') then
dataout <= "00000000000000000000000000000000";
end if;
end process;
--process (rst)
--begin
-- if (rst'event and rst = '1') then
-- res <= x"00000000";
-- dataout <= res;
-- end if;
--end process;
end Behavioral;
|
<gh_stars>10-100
--======================================================================
-- Wrapper for the Xilinx device DNA primitive. A 1->0 transition of
-- the reset triggers a read of the DNA value, which is then exposed
-- as a 96-bit parallel value.
--
-- Details about the DNA_PORTE2 primitive itself can be found in UG974
-- and UG570.
--======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity device_dna is
port (
clk : in std_logic;
rst : in std_logic;
dna : out std_logic_vector(95 downto 0)
);
end device_dna;
architecture rtl of device_dna is
constant C_DNA_LENGTH : natural := 96;
signal dna_dout : std_logic;
signal dna_read : std_logic;
signal dna_shift : std_logic;
signal dna_val : std_logic_vector(C_DNA_LENGTH - 1 downto 0);
signal dna_bits_left : std_logic_vector(7 downto 0);
type STATE is (STATE_IDLE, STATE_READ, STATE_SHIFT, STATE_DONE);
signal fsm_state : STATE;
begin
-- The actual Xilinx UltraScale(+) device DNA primitive.
dna_port : DNA_PORTE2
generic map (
SIM_DNA_VALUE => x"000000000000000000000000"
)
port map (
clk => clk,
din => '0',
dout => dna_dout,
read => dna_read,
shift => dna_shift
);
-- The process to trigger a DNA read and turn the serial result into
-- a bit vector.
read_dna : process (clk) is
begin
if rising_edge(clk) then
if rst = '1' then
fsm_state <= STATE_IDLE;
else
case fsm_state is
when STATE_IDLE =>
dna_read <= '0';
dna_shift <= '0';
dna_val <= (others => '0');
dna_bits_left <= (others => '0');
-- Move on.
fsm_state <= STATE_READ;
when STATE_READ =>
-- Trigger a DNA read.
dna_read <= '1';
dna_shift <= '0';
dna_val <= (others => '0');
dna_bits_left <= std_logic_vector(to_unsigned(C_DNA_LENGTH, dna_bits_left'length));
-- Move on.
fsm_state <= STATE_SHIFT;
when STATE_SHIFT =>
dna_read <= '0';
dna_shift <= '1';
-- Add the latest bit read to our running value.
-- NOTE: Shift direction is from LSB to MSB.
dna_val <= dna_dout & dna_val(dna_val'length - 1 downto 1);
dna_bits_left <= dna_bits_left - '1';
-- Once the whole DNA has been read, move on.
if dna_bits_left = (dna_bits_left'range => '0') then
fsm_state <= STATE_DONE;
else
fsm_state <= fsm_state;
end if;
when STATE_DONE =>
-- Nothing to do, really.
dna_read <= dna_read;
dna_shift <= '0';
dna_val <= dna_val;
dna_bits_left <= dna_bits_left;
fsm_state <= fsm_state;
end case;
end if;
end if;
end process read_dna;
dna <= dna_val;
end rtl;
--======================================================================
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
entity fourbitadderCount is
port (A,B: in STD_Logic_Vector(3 downto 0);
carry: out std_logic;
sum: out std_logic_vector(3 downto 0));
end fourbitadderCount;
-------------------------------------------------
architecture behavioral of fourbitadderCount is
signal result: std_logic_vector (4 downto 0);
begin
result <= ('0' & A) + ('0' & B);
sum <= result(3 downto 0);
carry <= result(4);
end behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dec_2to4_ne IS
PORT(
a: IN std_logic_vector(2 DOWNTO 1);
d: OUT std_logic_vector(4 DOWNTO 1));
END dec_2to4_ne;
ARCHITECTURE behav OF dec_2to4_ne IS
BEGIN
WITH a SELECT
d <= "0001" WHEN "00",
"0010" WHEN "01",
"0100" WHEN "10",
"1000" WHEN "11",
"0000" WHEN OTHERS;
END behav;
|
library ieee;
use ieee.std_logic_1164.all;
use work.core_pack.all;
use work.serial_port_pkg.all;
entity serial_port_wrapper is
generic (
clk_freq : integer;
baud_rate : integer;
sync_stages : integer;
tx_fifo_depth : integer;
rx_fifo_depth : integer);
port (
clk : in std_logic;
res_n : in std_logic;
address : in std_logic_vector(0 downto 0);
wr : in std_logic;
wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
rd : in std_logic;
rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
tx : out std_logic;
rx : in std_logic);
end serial_port_wrapper;
architecture behavior of serial_port_wrapper is
signal tx_data : std_logic_vector(7 downto 0);
signal tx_wr : std_logic;
signal tx_free : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_rd : std_logic;
signal rx_data_empty : std_logic;
signal rx_data_full : std_logic;
signal rd_address : std_logic_vector(0 downto 0);
begin -- behavior
sp : serial_port
generic map (
clk_freq => clk_freq,
baud_rate => baud_rate,
sync_stages => sync_stages,
tx_fifo_depth => tx_fifo_depth,
rx_fifo_depth => rx_fifo_depth)
port map (
clk => clk,
res_n => res_n,
tx_data => tx_data,
tx_wr => tx_wr,
tx_free => tx_free,
rx_data => rx_data,
rx_rd => rx_rd,
rx_data_empty => rx_data_empty,
rx_data_full => rx_data_full,
rx => rx,
tx => tx);
sync: process (clk, res_n)
begin -- process sync
if res_n = '0' then -- asynchronous reset (active low)
rd_address <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if rd = '1' then
rd_address <= address;
end if;
end if;
end process sync;
write: process (address, wr, wr_data)
begin -- process wrap
tx_data <= wr_data(31 downto 24);
if address(0) = '1' then
tx_wr <= wr;
else
tx_wr <= '0';
end if;
end process write;
read: process (address, rd, rd_address, rx_data, rx_data_empty, rx_data_full, tx_free)
begin -- process read
if address(0) = '1' then
rx_rd <= rd;
else
rx_rd <= '0';
end if;
rd_data <= (others => '0');
if rd_address(0) = '1' then
rd_data(31 downto 24) <= rx_data;
else
rd_data(31 downto 24) <= "00000" & rx_data_full & not rx_data_empty & tx_free;
end if;
end process read;
end behavior;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Sboxes IS
GENERIC ( count : POSITIVE);
PORT ( input: IN STD_LOGIC_VECTOR (4*count-1 DOWNTO 0);
output: OUT STD_LOGIC_VECTOR (4*count-1 DOWNTO 0));
END Sboxes;
ARCHITECTURE behavioral OF Sboxes IS
BEGIN
GEN :
FOR i IN 0 TO count-1 GENERATE
SboxInst: ENTITY work.sbox
Port Map (
X => input ((i+1)*4-1 downto i*4),
Y => output((i+1)*4-1 downto i*4));
END GENERATE;
END behavioral;
|
<filename>vhdl/customClock.vhd
-- uartRx.vhd
--
-- UART transmitter model for the camera link interface.
--
-- <NAME>
-- NASA MSFC EI31
-- 3/6/2006
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.meshPack.all;
entity customClock is
generic(
clockDivider : integer range 0 to 100000 := 2;
halfClk : integer range 0 to 100000 := 1
);
port (
clk : in std_logic;
rst : in std_logic;
clkOut : out std_logic
);
end customClock;
architecture behave of customClock is
type clockStates is (waitForClkHigh,waitForClkLow);
signal clockState : clockStates;
signal cnt : integer range 0 to clockDivider := 0;
begin
-- transmitter
process(rst, clk)
begin
if rst = '0' then
clockState <= waitForClkLow;
cnt <= 1;
clkOut <= '0';
elsif (clk'event and clk = '1') then
if (cnt = clockDivider) then
clkOut <= '1';
cnt <= 1;
-- elsif (cnt >= halfClk) then
-- clkOut <= '0';
-- cnt <= cnt + 1;
else
clkOut <= '0';
cnt <= cnt + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
end behave;
|
--------------------------------------------
-- 信号窄化器
-- 在sig_in的上升沿作为启动窄化的信号
-- 窄化的后的信号持续narr_prd个clk周期的高电平
-- 当narr_prd=0时, narr_sig_out就是0了
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity narr_sig is
port(
sig_in : in std_logic;
clk : in std_logic;
reset : in std_logic;
narr_prd : in std_logic_vector(7 downto 0); -- narr信号持续的周期数(以clk为周期)
narr_sig_out : out std_logic
);
end narr_sig;
architecture arch of narr_sig is
-- narr信号持续的周期计数器(1 -> narr_prd)
signal narr_prd_cnt : std_logic_vector(7 downto 0);
-- 停止窄化标志 0-窄化, 1-不窄化
signal stop_narr_flag : std_logic;
begin
process(sig_in, reset, clk, stop_narr_flag)
begin
if reset = '1' then
narr_prd_cnt <= X"00";
stop_narr_flag <= '1';
narr_sig_out <= '0';
else
if sig_in = '0' then
narr_prd_cnt <= X"00";
stop_narr_flag <= '0';
narr_sig_out <= '0';
else
if stop_narr_flag = '0' then
if rising_edge(clk) then
narr_prd_cnt <= narr_prd_cnt + '1';
narr_sig_out <= '1';
if narr_prd_cnt = narr_prd then
stop_narr_flag <= '1';
narr_prd_cnt <= X"00";
narr_sig_out <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end arch;
|
<filename>zed_system/zed3_axiethlite/zed3_axiethlite.ip_user_files/ipstatic/axi_ethernetlite_v3_0/hdl/src/vhdl/defer_state.vhd
-------------------------------------------------------------------------------
-- defer_state - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : defer_state.vhd
-- Version : v2.0
-- Description : This file contains the transmit deferral state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_4 library is used for axi_ethernetlite_v3_0_4
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_4;
use axi_ethernetlite_v3_0_4.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxEn -- Transmit enable
-- Txrst -- Transmit reset
-- Ifgp2Done -- Interframe gap2 done
-- Ifgp1Done -- Interframe gap1 done
-- BackingOff -- Backing off
-- Crs -- Carrier sense
-- Full_half_n -- Full/Half duplex indicator
-- Deferring -- Deffering for the tx data
-- CntrEnbl -- Counter enable
-- CntrLd -- Counter load
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity defer_state is
port (
Clk : in std_logic;
Rst : in std_logic;
TxEn : in std_logic;
Txrst : in std_logic;
Ifgp2Done : in std_logic;
Ifgp1Done : in std_logic;
BackingOff : in std_logic;
Crs : in std_logic;
Full_half_n : in std_logic;
Deferring : out std_logic;
CntrEnbl : out std_logic;
CntrLd : out std_logic
);
end defer_state;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of defer_state is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type StateName is (loadCntr,startIfgp1Cnt,startIfgp2Cnt,cntDone);
signal thisState : StateName;
signal nextState : StateName;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the tx state machine
begin
----------------------------------------------------------------------------
-- FSMR Process
----------------------------------------------------------------------------
-- An FSM that deals with transmitting data
----------------------------------------------------------------------------
FSMR : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1' or Txrst = '1') then
thisState <= loadCntr;
else
thisState <= nextState;
end if;
end if;
end process FSMR;
----------------------------------------------------------------------------
-- FSMC Process
----------------------------------------------------------------------------
FSMC : process (thisState,TxEn,Ifgp2Done,Ifgp1Done,BackingOff,Crs,
Full_half_n)
begin --
case thisState is
when loadCntr =>
if (((TxEn = '0') and (Full_half_n = '1')) or
((Crs = '0') and (Full_half_n = '0') and
(BackingOff = '0'))) and
Ifgp1Done = '0' and Ifgp2Done = '0' then
nextState <= startIfgp1Cnt;
else
nextState <= loadCntr; -- wait for end of transmission
end if;
when startIfgp1Cnt =>
if (((Crs = '1') and (Full_half_n = '0')) or
((BackingOff = '1') and (Full_half_n = '0'))) then
nextState <= loadCntr;
elsif (Ifgp1Done = '1') then -- gap done
nextState <= startIfgp2Cnt;
else
nextState <= startIfgp1Cnt; -- still counting
end if;
when startIfgp2Cnt =>
-- Added check for CRS to reset counter in when CRS goes low.
if (((Crs = '1') and (Full_half_n = '0')) or
((BackingOff = '1') and (Full_half_n = '0'))) then
nextState <= loadCntr;
elsif (Ifgp2Done = '1') then -- gap done
nextState <= cntDone;
else
nextState <= startIfgp2Cnt; -- still counting
end if;
when cntDone =>
if (TxEn = '1' or Crs = '1') then -- transmission started
nextState <= loadCntr;
else
nextState <= cntDone;
end if;
-- coverage off
when others => null;
nextState <= loadCntr;
-- coverage on
end case;
end process FSMC;
----------------------------------------------------------------------------
-- FSMD Process
----------------------------------------------------------------------------
FSMD : process(thisState)
begin --
if ((thisState = loadCntr) or (thisState = startIfgp1Cnt) or
(thisState = startIfgp2Cnt)) then
Deferring <= '1';
else
Deferring <= '0';
end if;
if ((thisState = startIfgp1Cnt) or (thisState = startIfgp2Cnt)) then
CntrEnbl <= '1';
else
CntrEnbl <= '0';
end if;
if (thisState = loadCntr) then
CntrLd <= '1';
else
CntrLd <= '0';
end if;
end process FSMD;
end implementation;
|
<filename>hardware/traffic_generator_receiver/VHDL/traffic_gen_with_noc/rtl/packages/NOC_3D_PACKAGE.vhd
-------------------------------------------------------------------------------
-- Title : Package for modular, heterogenous 3D NoC
-- Project : Modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : NOC_3D_PACKAGE.vhd
-- Author : <NAME> <<EMAIL>>
-- Company :
-- Created : 2018-10-24
-- Last update: 2018-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package including the constants, types, function and components
-- required for the modular, heterogenous 3D NoC.
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-10-24 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
package NOC_3D_PACKAGE is
--------------------------------------------------------------------------------
---------------------- CONSTANTS -----------------------------------------------
--------------------------------------------------------------------------------
---- The following lines can be edited to change the router architecture
---- With VHDL2008 these should be generic of the package
constant flit_size : positive := 32; -- Flit size in bits
constant max_vc_num : positive := 4; -- Max VCs of an input phy. channel
constant max_vc_num_out : positive := 4; -- Max VCs of an op. channel
constant max_x_dim : positive := 4; -- Max number of routers in X-dim
constant max_y_dim : positive := 4; -- Max number of routers in Y-dim
constant max_Z_dim : positive := 4; -- Max number of routers in Z-dim
constant max_packet_len : positive := 31; -- Max packet_length in flits
-- (ideal is 2^N-1)
constant max_port_num : positive := 7; -- Max number of router port
-- Which port-num belongs to witch port
constant int_local : natural := 0;
constant int_north : natural := 1;
constant int_east : natural := 2;
constant int_south : natural := 3;
constant int_west : natural := 4;
constant int_up : natural := 5;
constant int_down : natural := 6;
-- General contants for the used technology
constant RST_LVL : std_logic := '0'; -- Level to acticate reset ('1' =>
-- active high; '0' => active low)
-- Clock cycle in nano second
constant clk_period : time := 10 ns;
constant delay_constant : time := 300 ps;
-- Derived constants that cannot be edited (there values is calculated later
-- in the body)
constant packet_len_width : positive; -- Header Bits req. for packet-length
constant x_addr_width : positive; -- Header Bits req. for Dest. Addr X
constant y_addr_width : positive; -- Header Bits req. for Dest. Addr Y
constant z_addr_width : positive; -- Header Bits req. for Dest. Addr Z
--------------------------------------------------------------------------------
--------------------- (SUB)TYPES -----------------------------------------------
--------------------------------------------------------------------------------
-- General
type integer_vec is array (natural range <>) of integer;
type integer_array is array (natural range <>, natural range <>) of integer;
-- Flit related
subtype flit is std_logic_vector(flit_size-1 downto 0);
type flit_vector is array (natural range <>) of
std_logic_vector(flit_size-1 downto 0);
-- Virtual channel related
subtype vc_status_vec is std_logic_vector(max_vc_num-1 downto 0);
subtype vc_status_vec_enc is std_logic_vector(
positive(ceil(log2(real(max_vc_num))))-1 downto 0);
type vc_status_array is array (natural range <>) of vc_status_vec;
type vc_status_array_enc is array (natural range <>) of vc_status_vec_enc;
subtype vc_prop_int is integer_vec(0 to max_vc_num-1); -- integer vc
-- propoerties
-- (e.g. depth)
type vc_prop_int_array is array (natural range <>) of vc_prop_int;
-- Full NoC related
-- Head Flit related
type header_inf is record
packet_length : std_logic_vector(positive(ceil(log2(real(max_packet_len+1))))-1 downto 0);
------------------------------- (packet_len_width-1 downto 0)
x_dest : std_logic_vector(positive(ceil(log2(real(max_x_dim))))-1 downto 0);
------------------------------- (x_addr_width-1 downto 0)
y_dest : std_logic_vector(positive(ceil(log2(real(max_y_dim))))-1 downto 0);
------------------------------- (y_addr_width-1 downto 0)
z_dest : std_logic_vector(positive(ceil(log2(real(max_z_dim))))-1 downto 0);
--------------------------------- (z_addr_width-1 downto 0)
end record;
type header_inf_vector is array (natural range <>) of header_inf;
-- Head Flit related
type address_inf is record
x_dest : std_logic_vector(positive(ceil(log2(real(max_x_dim))))-1 downto 0);
------------------------------- (x_addr_width-1 downto 0)
y_dest : std_logic_vector(positive(ceil(log2(real(max_y_dim))))-1 downto 0);
------------------------------- (y_addr_width-1 downto 0)
z_dest : std_logic_vector(positive(ceil(log2(real(max_z_dim))))-1 downto 0);
--------------------------------- (z_addr_width-1 downto 0)
end record;
---------------------------------------------------------------------------------
------------------ FUNCTION-DEC. ------------------------------------------------
---------------------------------------------------------------------------------
-- Bits required to encode x different values
function bit_width(x : positive) return positive;
-- Transfer std_logic_vector (intp. unsigned) to natural integer
function slv2int(x : std_logic_vector) return natural;
-- Transfer "one_hot" to std_logic_vector
function one_hot2slv(x : std_logic_vector) return std_logic_vector;
-- Transfer "one_hot" to natural integer
function one_hot2int(x : std_logic_vector) return natural;
-- Get the req. information from the head_flit
function get_header_inf(x : std_logic_vector) return header_inf;
-- Get the dest. adress from the header information
function extract_address_inf(x : header_inf) return address_inf;
-- Sum all values of an integer array
function int_vec_sum(x : integer_vec) return integer;
-- Upper range
function upper_range(x : integer_vec; i : natural) return natural;
-- Lower range
function lower_range(x : integer_vec; i : natural) return natural;
-- Get the i^th slice of x (slice sized defined by vec)
function slice(x : std_logic_vector;
vec : integer_vec;
i : natural) return std_logic_vector;
-- Return the index of a value in an array
function ret_index(x : integer_vec; i : integer) return integer;
-- Return the maximum value of an array
function ret_max(x : integer_vec) return integer;
end package NOC_3D_PACKAGE;
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
--------------------- BODY -------------------------------------------------------
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
package body NOC_3D_PACKAGE is
-----------------------------------------------------------------------------------
------------------- FUNCTION-DEC. -------------------------------------------------
-----------------------------------------------------------------------------------
-- Bits required to encode x different values
function bit_width(x : positive) return positive is
begin
assert (x > 1) report "Encoding for less than two values is not possible"
severity failure;
return positive(ceil(log2(real(x))));
end function;
-- Derived constants using function bit_width
constant packet_len_width : positive := bit_width(max_packet_len+1);
constant x_addr_width : positive := bit_width(max_x_dim);
constant y_addr_width : positive := bit_width(max_y_dim);
constant z_addr_width : positive := bit_width(max_z_dim);
-- Transfer "std_logic_vector" (intp. unsigned) to "natural integer"
function slv2int(x : std_logic_vector) return natural is
begin
return to_integer(unsigned(x));
end function;
-- Transfer "one_hot" to "std_logic_vector"
function one_hot2slv(x : std_logic_vector) return std_logic_vector is
variable var : std_logic_vector(bit_width(x'length)-1 downto 0);
begin
var := (others => '0');
for i in x'range loop
if x(i) = '1' then
-- use "or" to avoid synthesizing a priority decoder
var := var or std_logic_vector(to_unsigned(i, var'length));
end if;
end loop;
return var;
end function;
-- Transfer "one_hot" to natural
function one_hot2int(x : std_logic_vector) return natural is
variable var : unsigned(bit_width(x'length)-1 downto 0);
begin
var := (others => '0');
for i in x'range loop
if x(i) = '1' then
-- use "or" to avoid synthesizing a priority decoder
var := var or to_unsigned(i, var'length);
end if;
end loop;
return to_integer(var);
end function;
-- The following unit has to be change if the header structure is changes.
-- Currently we assume that the LSBs are the packet-length: the next higher bits
-- are the X, Y and then Z address. All higher value bith are currently used by higher
-- layers. Important sofar is that is that the req. header informations
-- (addr, packet_length) are not allowed to take mor then "flit_size" bits.
function get_header_inf(x : std_logic_vector) return header_inf is
variable y : header_inf;
variable offset : integer;
begin
y.packet_length := x(packet_len_width-1 downto 0);
offset := packet_len_width;
y.x_dest := x(x_addr_width+offset-1 downto offset);
offset := offset + x_addr_width;
y.y_dest := x(y_addr_width+offset-1 downto offset);
offset := offset + y_addr_width;
y.z_dest := x(z_addr_width+offset-1 downto offset);
return y;
end function;
-- Get the address information from a header
function extract_address_inf(x : header_inf) return address_inf is
variable y : address_inf;
begin
y.x_dest := x.x_dest;
y.y_dest := x.y_dest;
y.z_dest := x.z_dest;
return y;
end function;
-- Sum of integer array
function int_vec_sum(x : integer_vec) return integer is
variable var : integer;
begin
var := 0;
for i in x'range loop
var := var + x(i);
end loop;
return var;
end function;
-- Uper range
function upper_range(x : integer_vec; i : natural) return natural is
variable var : natural;
begin
var := 0;
for it in 0 to i loop
var := var + x(it);
end loop;
return var-1;
end function;
-- Lower range
function lower_range(x : integer_vec; i : natural) return natural is
variable var : natural;
begin
var := 0;
for it in 0 to i loop
var := var + x(it);
end loop;
return var-x(i);
end function;
-- Slice of vector
function slice(x : std_logic_vector; vec : integer_vec;
i : natural) return std_logic_vector is
begin
return x(upper_range(vec, i) downto lower_range(vec, i));
end function;
-- Return the position in an array
function ret_index(x : integer_vec; i : integer) return integer is
variable result : integer:=-1;
begin
for index in 0 to x'length-1 loop
if x(x'left+index) = i then
result:= index;
end if;
end loop;
if result=-1 then
assert false report "INDEX IS NOT FOUND" severity error;
end if;
return result;
end function;
-- Return the maximum value of an array
function ret_max(x : integer_vec) return integer is
variable max_value : integer:=0;
begin
for index in 0 to x'length-1 loop
if x(x'left+index) > max_value then
max_value := x(x'left+index);
end if;
end loop;
return max_value;
end function;
end package body NOC_3D_PACKAGE;
|
--------------------------------------------------------------------------------
-- Brno University of Technology, Department of Radio Electronics
--------------------------------------------------------------------------------
-- Author: <NAME>
-- Design: substraction_with_carry
-- Description: Implementation of substraction_with_carry.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration for substraction_with_carry
--------------------------------------------------------------------------------
entity substraction_with_carry is
port(
-- Input
A_i : in std_logic_vector(4-1 downto 0);
B_i : in std_logic_vector(4-1 downto 0);
C_i : in std_logic;
-- Output
Y_o : out std_logic_vector(4-1 downto 0) ;
C_o : out std_logic
);
end substraction_with_carry;
--------------------------------------------------------------------------------
-- Architecture declaration for substraction_with_carry
--------------------------------------------------------------------------------
architecture Behavioral of substraction_with_carry is
signal sig_1 : std_logic_vector(4-1 downto 0);
signal sig_2 : std_logic_vector(2-1 downto 0);
signal carry_s : std_logic_vector(4-1 downto 0);
begin
NA0: entity work.substraction
port map (A_i,B_i,'0',sig_1,sig_2(0)); -- odecteni cisel A a B
NA1: entity work.substraction
port map (sig_1, carry_s,'0',Y_o,sig_2(1)); -- Odecteni cisla z prvni odcitacky s carry na nejnizsim bitu
c_o <= sig_2(0) or sig_2(1); -- vystupy z obou odcitaacek secteny a privedeny na vystup c_o
carry_s(3 downto 1) <= "000"; -- naplneni carry_s nulami krome nejnizsiho bitu
carry_s(0) <= C_i; -- na posledni bit carry_s je zapsan vstup carry
end Behavioral;
|
<reponame>richmr/CTF<filename>dcdarknet/2018/complex_v10-old.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity complex_v10 is
port (
Din : in std_logic_vector(31 downto 0);
Dout : out std_logic_vector(39 downto 0)
);
end complex_v10;
architecture imp of complex_v10 is
-- 10 bit constants
constant x000 : std_logic_vector(9 downto 0) := (others => '0');
constant x019 : std_logic_vector(9 downto 0) := "00" & X19;
constant x022 : std_logic_vector(9 downto 0) := "00" & X22;
constant x024 : std_logic_vector(9 downto 0) := "00" & X24;
constant x03A : std_logic_vector(9 downto 0) := "00" & X3A;
constant x066 : std_logic_vector(9 downto 0) := "00" & X66;
constant x067 : std_logic_vector(9 downto 0) := "00" & X67;
constant x0DE : std_logic_vector(9 downto 0) := "00" & XDE;
constant x0FF : std_logic_vector(9 downto 0) := "00" & XFF;
constant x111 : std_logic_vector(9 downto 0) := "01" & X11;
constant x155 : std_logic_vector(9 downto 0) := "01" & X55;
constant x2A5 : std_logic_vector(9 downto 0) := "10" & XA5;
constant x2AA : std_logic_vector(9 downto 0) := "10" & XAA;
-- break 32-bit input Din into bytes and store it in a 10-bit value
signal Dinb3 : std_logic_vector(9 downto 0);
signal Dinb2 : std_logic_vector(9 downto 0);
signal Dinb1 : std_logic_vector(9 downto 0);
signal Dinb0 : std_logic_vector(9 downto 0);
begin
-- break them into bytes and extend to 10 bits
proc0 : process(Din)
begin
Dinb3 <= "00" & Din(31 downto 24);
Dinb2 <= "00" & Din(23 downto 16);
Dinb1 <= "00" & Din(15 downto 8);
Dinb0 <= "00" & Din(7 downto 0);
end process proc0;
-- Din(31:24) drives Dout(19:10)
proc1 : process(Dinb3)
begin
case to_integer((Dinb3(7 downto 0))) is
when to_integer(00) to to_integer(31) => Dout(19 downto 10) <= Dinb3 + x03A;
when to_integer(unsigned(32)) to to_integer(unsigned(42)) => Dout(19 downto 10) <= Dinb3 - x0DE;
when to_integer(unsigned(43)) to to_integer(unsigned(55)) => Dout(19 downto 10) <= Dinb3 XOR x2A5;
when to_integer(unsigned(56)) to to_integer(unsigned(96)) => Dout(19 downto 10) <= std_logic_vector(shift_left(unsigned(Dinb3),3));
when to_integer(unsigned(97)) to to_integer(unsigned(170)) => Dout(19 downto 10) <= std_logic_vector(rotate_left(unsigned(Dinb3),5));
when to_integer(unsigned(171)) to to_integer(unsigned(255)) => Dout(19 downto 10) <= std_logic_vector(shift_right(unsigned(Dinb3),2));
when others => Dout(19 downto 10) <= x000;
end case;
end process proc1;
-- Din(23:16) drives Dout(9:0)
proc2 : process(Dinb2)
begin
case to_integer(unsigned(Dinb2(7 downto 0))) is
when to_integer(unsigned(00)) to to_integer(unsigned(16)) => Dout(9 downto 0) <= NOT Dinb2;
when to_integer(unsigned(17)) to to_integer(unsigned(44)) => Dout(9 downto 0) <= Dinb2 - x111;
when to_integer(unsigned(45)) to to_integer(unsigned(68)) => Dout(9 downto 0) <= Dinb2 + x066;
when to_integer(unsigned(69)) to to_integer(unsigned(187)) => Dout(9 downto 0) <= Dinb2 AND x2AA;
when to_integer(unsigned(188)) to to_integer(unsigned(222)) => Dout(9 downto 0) <= Dinb2(1) & Dinb2(3) & Dinb2(2) & Dinb2(6) & Dinb2(0) & Dinb2(8) & Dinb2(5) & Dinb2(7) & Dinb2(4) & Dinb2(9);
when to_integer(unsigned(223)) to to_integer(unsigned(255)) => Dout(9 downto 0) <= Dinb2 + x022;
when others => Dout(9 downto 0) <= x000;
end case;
end process proc2;
-- Din(15:8) drives Dout(39:30)
proc3 : process(Dinb1)
begin
case to_integer(unsigned(Dinb1(7 downto 0))) is
when to_integer(unsigned(X"00")) to to_integer(unsigned(44)) => Dout(39 downto 30) <= NOT(Dinb1(3 downto 0)) & Dinb1(7 downto 4) & Dinb1(9 downto 8);
when to_integer(unsigned(45)) to to_integer(unsigned(61)) => Dout(39 downto 30) <= Dinb1 + x024;
when to_integer(unsigned(62)) to to_integer(unsigned(82)) => Dout(39 downto 30) <= Dinb1 + x0ff;
when to_integer(unsigned(83)) to to_integer(unsigned(115)) => Dout(39 downto 30) <= Dinb1 - x024;
when to_integer(unsigned(116)) to to_integer(unsigned(204)) => Dout(39 downto 30) <= Dinb1 - x0ff;
when to_integer(unsigned(205)) to to_integer(unsigned(255)) => Dout(39 downto 30) <= "10" & (Dinb1(7 downto 4) OR X"1") & (Dinb1(3 downto 0) AND X"E");
when others => Dout(39 downto 30) <= x000;
end case;
end process proc3;
-- Din(7:0) drives Dout(29:20)
proc4 : process(Dinb0)
begin
case to_integer(unsigned(Dinb0(7 downto 0))) is
when to_integer(unsigned(X"00")) to to_integer(unsigned(65)) => Dout(29 downto 20) <= std_logic_vector(rotate_right(unsigned(Dinb0),3));
when to_integer(unsigned(X"42")) to to_integer(unsigned(90)) => Dout(29 downto 20) <= Dinb0(5) & Dinb0(3) & Dinb0(0) & Dinb0(2) & Dinb0(1) & Dinb0(7) & Dinb0(9) & Dinb0(6) & Dinb0(4) & Dinb0(8);
when to_integer(unsigned(X"5b")) to to_integer(unsigned(134)) => Dout(29 downto 20) <= Dinb0 + x019;
when to_integer(unsigned(X"87")) to to_integer(unsigned(175)) => Dout(29 downto 20) <= Dinb0 + x067;
when to_integer(unsigned(X"b0")) to to_integer(unsigned(223)) => Dout(29 downto 20) <= Dinb0 XOR x2AA;
when to_integer(unsigned(X"e0")) to to_integer(unsigned(255)) => Dout(29 downto 20) <= Dinb0 XOR x155;
when others => Dout(29 downto 20) <= x000;
end case;
end process proc4;
end imp;
|
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: Wrapper for Lmk048Base to handle 3-wire SPI and address mapping
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
library unisim;
use unisim.vcomponents.all;
entity Lmk048Base is
generic (
TPD_G : time := 1 ns;
CLK_PERIOD_G : real := 6.4E-9; -- units of seconds
SPI_SCLK_PERIOD_G : real := 100.0E-6); -- units of seconds
port (
-- 3-Wire SPI Ports
lmkCsL : out sl;
lmkSck : out sl;
lmkSdio : inout sl;
-- AXI-Lite Interface
axilClk : in sl;
axilRst : in sl;
axilReadMaster : in AxiLiteReadMasterType;
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType);
end Lmk048Base;
architecture mapping of Lmk048Base is
signal writeMaster : AxiLiteWriteMasterType;
signal readMaster : AxiLiteReadMasterType;
signal lmkSDin : sl;
signal lmkSDout : sl;
begin
process (axilReadMaster, axilWriteMaster) is
variable wrMst : AxiLiteWriteMasterType;
variable rdMst : AxiLiteReadMasterType;
begin
-- Init
wrMst := axilWriteMaster;
rdMst := axilReadMaster;
-- Force the Upper SPI address bits that should always be zero
wrMst.awaddr(31 downto 12) := (others => '0');
rdMst.araddr(31 downto 12) := (others => '0');
-- Outputs
writeMaster <= wrMst;
readMaster <= rdMst;
end process;
U_LMK : entity surf.AxiSpiMaster
generic map (
TPD_G => TPD_G,
ADDRESS_SIZE_G => 15,
DATA_SIZE_G => 8,
CLK_PERIOD_G => CLK_PERIOD_G,
SPI_SCLK_PERIOD_G => SPI_SCLK_PERIOD_G)
port map (
-- AXI-Lite Interface
axiClk => axilClk,
axiRst => axilRst,
axiReadMaster => readMaster,
axiReadSlave => axilReadSlave,
axiWriteMaster => writeMaster,
axiWriteSlave => axilWriteSlave,
-- SPI Ports
coreSclk => lmkSck,
coreSDin => lmkSDin,
coreSDout => lmkSDout,
coreCsb => lmkCsL);
U_lmkSdio : IOBUF
port map (
I => '0',
O => lmkSDin,
IO => lmkSdio,
T => lmkSDout);
end mapping;
|
<reponame>varunnagpaal/Digital-Hardware-Modelling<gh_stars>10-100
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
generic( W : natural := 4); -- Width of data
port (clk : in std_logic;
rst : in std_logic; -- active high sync to clock
i_data_a : in std_logic_vector(W-1 downto 0); -- input data A
i_data_b : in std_logic_vector(W-1 downto 0); -- input data B
i_data_carry : in std_logic; -- carry in or borrow in
i_ctrl : in std_logic_vector(3 downto 0); -- control signals
o_data_c : out std_logic_vector(W-1 downto 0); -- output data C
o_data_carry : out std_logic; -- carry out or borrow out
o_data_comp : out std_logic_vector(1 downto 0); -- output comparison
o_valid : out std_logic -- valid output
);
end top;
architecture rtl of top is
-- 1: FETCH
signal reg_i_instr_1 : std_logic_vector( i_ctrl'RANGE ) := ( others => '0' );
signal reg_i_data_a_1 : std_logic_vector( i_data_a'RANGE ) := ( others => '0' );
signal reg_i_data_b_1 : std_logic_vector( i_data_b'RANGE ) := ( others => '0' );
signal reg_i_data_carry_1 : std_logic := '0';
-- 2: DECODE
signal reg_i_instr_2 : std_logic_vector( i_ctrl'RANGE ) := ( others => '0' );
signal reg_i_data_a_2 : std_logic_vector( i_data_a'RANGE ) := ( others => '0' );
signal reg_i_data_b_2 : std_logic_vector( i_data_b'RANGE ) := ( others => '0' );
signal reg_i_data_carry_2 : std_logic := '0';
-- 3: Execute
signal reg_i_instr_3 : std_logic_vector( i_ctrl'RANGE ) := ( others => '0' );
signal reg_i_data_a_3 : std_logic_vector( i_data_a'RANGE ) := ( others => '0' );
signal reg_i_data_b_3 : std_logic_vector( i_data_b'RANGE ) := ( others => '0' );
signal reg_i_data_carry_3 : std_logic := '0';
-- Output signals of ALU
signal sig_data_c : std_logic_vector( o_data_c'RANGE ) := ( others=> '0' );
signal sig_data_carry : std_logic := '0';
signal sig_data_comp : std_logic_vector( o_data_comp'RANGE ) := ( others=> '0' );
signal sig_valid : std_logic := '0';
signal reg_valid : std_logic := '0';
-- Declare component ALU
component alu is
generic( W : natural := 4 );
port (i_data_a : in std_logic_vector(W-1 downto 0); -- input data A
i_data_b : in std_logic_vector(W-1 downto 0); -- input data B
i_data_carry : in std_logic; -- carry in or borrow in
i_ctrl : in std_logic_vector(3 downto 0); -- control signals
o_data_c : out std_logic_vector(W-1 downto 0); -- output data C
o_data_carry : out std_logic; -- carry out or borrow out
o_data_comp : out std_logic_vector(1 downto 0) -- output comparison
);
end component alu;
begin
-- Instruction pipeline (1: FETCH, 2: DECODE, 3: EXECUTE)
mem_instr: process(clk)
begin
if rising_edge(clk) then
if( rst = '1' ) then
-- 1: FETCH
reg_i_instr_1 <= ( others => '0' ); -- NOP
-- 2: DECODE
reg_i_instr_2 <= ( others => '0' ); -- NOP
-- 2: DECODE
reg_i_instr_3 <= ( others => '0' ); -- NOP
else
-- 1: FETCH
reg_i_instr_1 <= i_ctrl;
-- 2: DECODE
reg_i_instr_2 <= reg_i_instr_1;
-- 3: Execute
reg_i_instr_3 <= reg_i_instr_2;
end if;
end if;
end process mem_instr;
-- Operand pipeline (1: FETCH, 2: DECODE, 3: EXECUTE)
mem_operands: process(clk)
begin
if rising_edge(clk) then
if( rst = '1' ) then
-- 1: FETCH
reg_i_data_a_1 <= ( others => '0' );
reg_i_data_b_1 <= ( others => '0' );
reg_i_data_carry_1 <= '0';
-- 2: DECODE
reg_i_data_a_2 <= ( others => '0' );
reg_i_data_b_2 <= ( others => '0' );
reg_i_data_carry_2 <= '0';
-- 2: Execute
reg_i_data_a_3 <= ( others => '0' );
reg_i_data_b_3 <= ( others => '0' );
reg_i_data_carry_3 <= '0';
else
-- 1: FETCH
reg_i_data_a_1 <= i_data_a;
reg_i_data_b_1 <= i_data_b;
reg_i_data_carry_1 <= i_data_carry;
-- 2: DECODE
reg_i_data_a_2 <= reg_i_data_a_1;
reg_i_data_b_2 <= reg_i_data_b_1;
reg_i_data_carry_2 <= reg_i_data_carry_1;
-- 2: EXECUTE
reg_i_data_a_3 <= reg_i_data_a_2;
reg_i_data_b_3 <= reg_i_data_b_2;
reg_i_data_carry_3 <= reg_i_data_carry_2;
end if;
end if;
end process mem_operands;
-- 2: DECODE
-- Check if fetched instruction is a valid instruction
sig_valid <= '1' when reg_i_instr_2 = "0001" OR
reg_i_instr_2 = "0010" OR
reg_i_instr_2 = "0011" OR
reg_i_instr_2 = "0100" OR
reg_i_instr_2 = "0101" OR
reg_i_instr_2 = "0110" OR
reg_i_instr_2 = "0111" else '0';
-- 2: DECODE
mem_valid: process(clk)
begin
if rising_edge(clk) then
if( rst = '1') then
reg_valid <= '0';
else
reg_valid <= sig_valid;
end if;
end if;
end process mem_valid;
-- 2: DECODE
o_valid <= reg_valid;
-- 3: EXECUTE
alu_inst: alu
generic map( W => W )
port map( i_data_a => reg_i_data_a_3,
i_data_b => reg_i_data_b_3,
i_data_carry => reg_i_data_carry_3,
i_ctrl => reg_i_instr_3,
o_data_c => sig_data_c,
o_data_carry => sig_data_carry,
o_data_comp => sig_data_comp );
-- 3: EXECUTE
mem_outputs: process(clk)
begin
if rising_edge(clk) then
if( rst = '1') then
o_data_c <= ( others => '0' );
o_data_carry <= '0';
o_data_comp <= ( others => '0' );
else
if( reg_valid = '1' ) then
o_data_c <= sig_data_c;
o_data_carry <= sig_data_carry;
o_data_comp <= sig_data_comp;
else
o_data_c <= ( others => '0' );
o_data_carry <= '0';
o_data_comp <= ( others => '0' );
end if;
end if;
end if;
end process mem_outputs;
end rtl;
|
------------------------------------------------------------------------------
-- This file is part of 'RCE Development Firmware'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'RCE Development Firmware', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- SlaveRena.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library rce_gen3_fw_lib;
use rce_gen3_fw_lib.RceG3Pkg.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
use surf.AxiStreamPkg.all;
use surf.EthMacPkg.all;
library ucsc_hn;
entity SlaveRena is
generic (
BUILD_INFO_G : BuildInfoType);
port (
-- I2C
i2cSda : inout sl;
i2cScl : inout sl;
-- Ethernet
ethRxP : in sl;
ethRxN : in sl;
ethTxP : out sl;
ethTxN : out sl;
-- Hub clock and sync
clockHubP : in sl;
clockHubN : in sl;
syncHubP : inout sl;
syncHubN : inout sl;
-- Rena Clock And Sync
clockOutP : out sl;
clockOutN : out sl;
syncOutP : out sl;
syncOutN : out sl;
syncOutNew : out sl;
fpgaProgL : out sl;
-- Data inputs
rxDataP : in slv(30 downto 1);
rxDataN : in slv(30 downto 1);
-- Control outputs
txData : out slv(6 downto 1)
);
end SlaveRena;
architecture STRUCTURE of SlaveRena is
constant TPD_C : time := 1 ns;
constant SERVER_PORTS_C : PositiveArray(1 downto 0) := (
1 => 2542, -- Xilinx XVC
0 => 8192);
constant APP_AXIS_CONFIG_C : AxiStreamConfigType := (
TSTRB_EN_C => False,
TDATA_BYTES_C => 8,
TDEST_BITS_C => 0,
TID_BITS_C => 0,
TKEEP_MODE_C => TKEEP_COMP_C,
TUSER_BITS_C => 2,
TUSER_MODE_C => TUSER_FIRST_LAST_C);
-- AXI-Lite
constant AXIL_XBAR_MASTERS_C : integer := 3;
constant MAC_AXIL_INDEX_C : integer := 0;
constant UDP_AXIL_INDEX_C : integer := 1;
constant RSSI_AXIL_INDEX_C : integer := 2;
constant AXIL_XBAR_CFG_C : AxiLiteCrossbarMasterConfigArray(AXIL_XBAR_MASTERS_C-1 downto 0) := (
MAC_AXIL_INDEX_C => (
baseAddr => X"B0000000",
addrBits => 16,
connectivity => X"FFFF"),
UDP_AXIL_INDEX_C => (
baseAddr => X"B0010000",
addrBits => 16,
connectivity => X"FFFF"),
RSSI_AXIL_INDEX_C => (
baseAddr => X"B0020000",
addrBits => 10,
connectivity => X"FFFF"));
signal stableClk : sl;
signal stableRst : sl;
signal clk312 : sl;
signal rst312 : sl;
signal clk200 : sl;
signal rst200 : sl;
signal clk156 : sl;
signal rst156 : sl;
signal clk125 : sl;
signal rst125 : sl;
signal clk62 : sl;
signal rst62 : sl;
signal locked : sl;
signal axiDmaClk : sl;
signal axiDmaRst : sl;
signal axilClk : sl;
signal axilRst : sl;
-- External Axi Bus, 0xA0000000 - 0xAFFFFFFF (axilClk domain)
signal extAxilReadMaster : AxiLiteReadMasterType;
signal extAxilReadSlave : AxiLiteReadSlaveType;
signal extAxilWriteMaster : AxiLiteWriteMasterType;
signal extAxilWriteSlave : AxiLiteWriteSlaveType;
-- Core Axi Bus, 0xB0000000 - 0xBFFFFFFF (axilClk domain)
signal coreAxilReadMaster : AxiLiteReadMasterType;
signal coreAxilReadSlave : AxiLiteReadSlaveType;
signal coreAxilWriteMaster : AxiLiteWriteMasterType;
signal coreAxilWriteSlave : AxiLiteWriteSlaveType;
-- Core Axi Bus, 0xB0000000 - 0xBFFFFFFF (axilClk domain)
signal coreAxilReadMasters : AxiLiteReadMasterArray(AXIL_XBAR_MASTERS_C-1 downto 0);
signal coreAxilReadSlaves : AxiLiteReadSlaveArray(AXIL_XBAR_MASTERS_C-1 downto 0);
signal coreAxilWriteMasters : AxiLiteWriteMasterArray(AXIL_XBAR_MASTERS_C-1 downto 0);
signal coreAxilWriteSlaves : AxiLiteWriteSlaveArray(AXIL_XBAR_MASTERS_C-1 downto 0);
signal udpAxilReadMaster : AxiLiteReadMasterType;
signal udpAxilReadSlave : AxiLiteReadSlaveType;
signal udpAxilWriteMaster : AxiLiteWriteMasterType;
signal udpAxilWriteSlave : AxiLiteWriteSlaveType;
signal udpObServerMasters : AxiStreamMasterArray(1 downto 0);
signal udpObServerSlaves : AxiStreamSlaveArray(1 downto 0);
signal udpIbServerMasters : AxiStreamMasterArray(1 downto 0);
signal udpIbServerSlaves : AxiStreamSlaveArray(1 downto 0);
-- DMA Interfaces (dmaClk domain)
signal dmaClk : slv(3 downto 0);
signal dmaClkRst : slv(3 downto 0);
signal dmaState : RceDmaStateArray(3 downto 0);
signal dmaObMaster : AxiStreamMasterArray(3 downto 0);
signal dmaObSlave : AxiStreamSlaveArray(3 downto 0);
signal dmaIbMaster : AxiStreamMasterArray(3 downto 0);
signal dmaIbSlave : AxiStreamSlaveArray(3 downto 0);
-- User Ethernet
signal userEthClk : sl;
signal userEthClkRst : sl;
signal userEthUdpIbMaster : AxiStreamMasterType;
signal userEthUdpIbSlave : AxiStreamSlaveType;
signal userEthUdpObMaster : AxiStreamMasterType;
signal userEthUdpObSlave : AxiStreamSlaveType;
signal localIp : slv(31 downto 0);
signal localMac : slv(47 downto 0);
signal rssiObMaster : AxiStreamMasterType;
signal rssiObSlave : AxiStreamSlaveType;
signal rssiIbMaster : AxiStreamMasterType;
signal rssiIbSlave : AxiStreamSlaveType;
-- ZYNQ GEM Interface
signal armEthTx : ArmEthTxArray(1 downto 0);
signal armEthRx : ArmEthRxArray(1 downto 0);
signal armEthMode : slv(31 downto 0);
signal iethRxP : slv(3 downto 0);
signal iethRxN : slv(3 downto 0);
signal iethTxP : slv(3 downto 0);
signal iethTxN : slv(3 downto 0);
begin
--------------------------------------------------
-- RCE Core
--------------------------------------------------
U_RceG3Top : entity rce_gen3_fw_lib.RceG3Top
generic map (
TPD_G => TPD_C,
MEMORY_TYPE_G => "block",
SEL_REFCLK_G => false,
BUILD_INFO_G => BUILD_INFO_G,
SLOW_PLL_G => true,
PCIE_EN_G => false,
RCE_DMA_MODE_G => RCE_DMA_AXISV2_C)
port map (
-- I2C Ports
i2cSda => i2cSda,
i2cScl => i2cScl,
-- Reference Clock
ethRefClkP => '1',
ethRefClkN => '0',
ethRefClk => open,
stableClk => stableClk,
stableRst => stableRst,
-- Top-level clocks and resets
clk312 => clk312,
rst312 => rst312,
clk200 => clk200,
rst200 => rst200,
clk156 => clk156,
rst156 => rst156,
clk125 => clk125,
rst125 => rst125,
clk62 => clk62,
rst62 => rst62,
locked => locked,
userInterrupt => (others=>'0'),
-- DMA clock and reset
axiDmaClk => axiDmaClk,
axiDmaRst => axiDmaRst,
-- AXI-Lite clock and reset
axilClk => axilClk,
axilRst => axilRst,
-- External Axi Bus, (axilClk domain)
-- 0xA0000000 - 0xAFFFFFFF (COB_MIN_C10_G = False)
-- 0x90000000 - 0x97FFFFFF (COB_MIN_C10_G = True)
extAxilReadMaster => extAxilReadMaster,
extAxilReadSlave => extAxilReadSlave,
extAxilWriteMaster => extAxilWriteMaster,
extAxilWriteSlave => extAxilWriteSlave,
-- Core Axi Bus, 0xB0000000 - 0xBFFFFFFF (axilClk domain)
coreAxilReadMaster => coreAxilReadMaster,
coreAxilReadSlave => coreAxilReadSlave,
coreAxilWriteMaster => coreAxilWriteMaster,
coreAxilWriteSlave => coreAxilWriteSlave,
-- DMA Interfaces (dmaClk domain)
dmaClk => dmaClk,
dmaClkRst => dmaClkRst,
dmaState => dmaState,
dmaObMaster => dmaObMaster,
dmaObSlave => dmaObSlave,
dmaIbMaster => dmaIbMaster,
dmaIbSlave => dmaIbSlave,
-- ZYNQ GEM Interface
armEthTx => armEthTx,
armEthRx => armEthRx,
armEthMode => armEthMode);
----------------------------------------------------------------------------
-- Core AXI Crossbar --
----------------------------------------------------------------------------
U_AxiLiteCrossbar_1 : entity surf.AxiLiteCrossbar
generic map (
TPD_G => TPD_C,
NUM_SLAVE_SLOTS_G => 1,
NUM_MASTER_SLOTS_G => AXIL_XBAR_MASTERS_C,
MASTERS_CONFIG_G => AXIL_XBAR_CFG_C,
DEBUG_G => false)
port map (
axiClk => axilClk,
axiClkRst => axilRst,
sAxiWriteMasters(0) => coreAxilWriteMaster,
sAxiWriteSlaves(0) => coreAxilWriteSlave,
sAxiReadMasters(0) => coreAxilReadMaster,
sAxiReadSlaves(0) => coreAxilReadSlave,
mAxiWriteMasters => coreAxilWriteMasters,
mAxiWriteSlaves => coreAxilWriteSlavEs,
mAxiReadMasters => coreAxilReadMasters,
mAxiReadSlaves => coreAxilReadSlaves);
----------------------------------------------------------------------------
-- ETH GT Mapping --
----------------------------------------------------------------------------
-- This VHDL wrapper is determined by the ZYNQ family type
-- Zynq-7000: rce-gen3-fw-lib/RceG3/hdl/zynq/RceEthGtMapping.vhd
-- Zynq Ultrascale+: rce-gen3-fw-lib/RceG3/hdl/zynquplus/RceEthGtMapping.vhd
----------------------------------------------------------------------------
U_RceEthernet : entity rce_gen3_fw_lib.RceEthernet
generic map (
-- Generic Configurations
TPD_G => TPD_C,
RCE_DMA_MODE_G => RCE_DMA_AXIS_C,
ETH_TYPE_G => "1000BASE-KX",
MEMORY_TYPE_G => "block",
EN_JUMBO_G => false,
-- User ETH Configurations
UDP_SERVER_EN_G => true,
UDP_SERVER_SIZE_G => 2,
UDP_SERVER_PORTS_G => SERVER_PORTS_C,
BYP_EN_G => false,
VLAN_EN_G => false)
port map (
-- Clocks and resets
clk312 => clk312,
rst312 => rst312,
clk200 => clk200,
rst200 => rst200,
clk156 => clk156,
rst156 => rst156,
clk125 => clk125,
rst125 => rst125,
clk62 => clk62,
rst62 => rst62,
stableClk => stableClk,
stableRst => stableRst,
-- PPI Interface
dmaClk => dmaClk(3),
dmaRst => dmaClkRst(3),
dmaState => dmaState(3),
dmaIbMaster => dmaIbMaster(3),
dmaIbSlave => dmaIbSlave(3),
dmaObMaster => dmaObMaster(3),
dmaObSlave => dmaObSlave(3),
-- User ETH interface
userEthClk => userEthClk,
userEthRst => userEthClkRst,
userEthIpAddr => localIp,
userEthMacAddr => localMac,
userEthUdpIbMaster => userEthUdpIbMaster,
userEthUdpIbSlave => userEthUdpIbSlave,
userEthUdpObMaster => userEthUdpObMaster,
userEthUdpObSlave => userEthUdpObSlave,
userEthBypIbMaster => AXI_STREAM_MASTER_INIT_C,
userEthBypIbSlave => open,
userEthBypObMaster => open,
userEthBypObSlave => AXI_STREAM_SLAVE_FORCE_C,
userEthVlanIbMasters => (others=>AXI_STREAM_MASTER_INIT_C),
userEthVlanIbSlaves => open,
userEthVlanObMasters => open,
userEthVlanObSlaves => (others=>AXI_STREAM_SLAVE_FORCE_C),
-- AXI-Lite Buses
axilClk => axilClk,
axilRst => axilRst,
axilWriteMaster => coreAxilWriteMasters(MAC_AXIL_INDEX_C),
axilWriteSlave => coreAxilWriteSlaves(MAC_AXIL_INDEX_C),
axilReadMaster => coreAxilReadMasters(MAC_AXIL_INDEX_C),
axilReadSlave => coreAxilReadSlaves(MAC_AXIL_INDEX_C),
-- Ref Clock
ethRefClk => '0',
-- Ethernet Lines
ethRxP => iethRxP,
ethRxN => iethRxN,
ethTxP => iethTxP,
ethTxN => iethTxN);
armEthMode <= x"00000002";
-- Show connections
iethRxP(0) <= ethRxP;
iethRxN(0) <= ethRxN;
ethTxP <= iethTxP(0);
ethTxN <= iethTxN(0);
-------------------------------------------------------------------------------------------------
-- UDP Engine
-------------------------------------------------------------------------------------------------
U_AxiLiteAsync : entity surf.AxiLiteAsync
generic map (
TPD_G => TPD_C)
port map (
sAxiClk => axilClk,
sAxiClkRst => axilRst,
sAxiReadMaster => coreAxilReadMasters(UDP_AXIL_INDEX_C),
sAxiReadSlave => coreAxilReadSlaves(UDP_AXIL_INDEX_C),
sAxiWriteMaster => coreAxilWriteMasters(UDP_AXIL_INDEX_C),
sAxiWriteSlave => coreAxilWriteSlaves(UDP_AXIL_INDEX_C),
mAxiClk => userEthClk,
mAxiClkRst => userEthClkRst,
mAxiReadMaster => udpAxilReadMaster,
mAxiReadSlave => udpAxilReadSlave,
mAxiWriteMaster => udpAxilWriteMaster,
mAxiWriteSlave => udpAxilWriteSlave);
U_UdpEngineWrapper : entity surf.UdpEngineWrapper
generic map (
TPD_G => TPD_C,
SERVER_EN_G => true,
SERVER_SIZE_G => 2,
SERVER_PORTS_G => SERVER_PORTS_C,
CLIENT_EN_G => false,
DHCP_G => false,
CLK_FREQ_G => 125.0e6)
port map (
localMac => localMac,
localIp => localIp,
obMacMaster => userEthUdpObMaster,
obMacSlave => userEthUdpObSlave,
ibMacMaster => userEthUdpIbMaster,
ibMacSlave => userEthUdpIbSlave,
obServerMasters => udpObServerMasters,
obServerSlaves => udpObServerSlaves,
ibServerMasters => udpIbServerMasters,
ibServerSlaves => udpIbServerSlaves,
axilWriteMaster => udpAxilWriteMaster,
axilWriteSlave => udpAxilWriteSlave,
axilReadMaster => udpAxilReadMaster,
axilReadSlave => udpAxilReadSlave,
clk => userEthClk,
rst => userEthClkRst);
U_Debug : entity surf.UdpDebugBridgeWrapper
generic map (
TPD_G => TPD_C)
port map (
-- Clock and Reset
clk => userEthClk,
rst => userEthClkRst,
-- UDP XVC Interface
obServerMaster => udpObServerMasters(1),
obServerSlave => udpObServerSlaves(1),
ibServerMaster => udpIbServerMasters(1),
ibServerSlave => udpIbServerSlaves(1));
-------------------------------------------------------------------------------------------------
-- RSSI Engines
-------------------------------------------------------------------------------------------------
U_RssiCoreWrapper : entity surf.RssiCoreWrapper
generic map (
TPD_G => TPD_C,
CLK_FREQUENCY_G => 125.0e6,
WINDOW_ADDR_SIZE_G => 4,
SEGMENT_ADDR_SIZE_G => 7,
BYPASS_CHUNKER_G => false,
PIPE_STAGES_G => 1,
APP_STREAMS_G => 1,
TIMEOUT_UNIT_G => 1.0e-3,
SERVER_G => true,
RETRANSMIT_ENABLE_G => true,
MAX_NUM_OUTS_SEG_G => 16,
INIT_SEQ_N_G => 16#80#,
APP_ILEAVE_EN_G => true,
BYP_TX_BUFFER_G => false,
BYP_RX_BUFFER_G => false,
ILEAVE_ON_NOTVALID_G => true,
APP_AXIS_CONFIG_G => (0 => APP_AXIS_CONFIG_C),
TSP_AXIS_CONFIG_G => EMAC_AXIS_CONFIG_C,
MAX_SEG_SIZE_G => 1024)
port map (
clk_i => userEthClk,
rst_i => userEthClkRst,
sAppAxisMasters_i(0) => rssiIbMaster,
sAppAxisSlaves_o(0) => rssiIbSlave,
mAppAxisMasters_o(0) => rssiObMaster,
mAppAxisSlaves_i(0) => rssiObSlave,
sTspAxisMaster_i => udpObServerMasters(0),
sTspAxisSlave_o => udpObServerSlaves(0),
mTspAxisMaster_o => udpIbServerMasters(0),
mTspAxisSlave_i => udpIbServerSlaves(0),
openRq_i => '1',
axiClk_i => axilClk,
axiRst_i => axilRst,
axilReadMaster => coreAxilReadMasters(RSSI_AXIL_INDEX_C),
axilReadSlave => coreAxilReadSlaves(RSSI_AXIL_INDEX_C),
axilWriteMaster => coreAxilWriteMasters(RSSI_AXIL_INDEX_C),
axilWriteSlave => coreAxilWriteSlaves(RSSI_AXIL_INDEX_C),
statusReg_o => open);
----------------------------------------------------
-- Fan In Board Core
----------------------------------------------------
U_FanInBoard: entity ucsc_hn.FanInBoard
generic map (
TPD_G => TPD_C,
MASTER_G => false,
AXIS_CONFIG_G => APP_AXIS_CONFIG_C
) port map (
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => extAxilReadMaster,
axilReadSlave => extAxilReadSlave,
axilWriteMaster => extAxilWriteMaster,
axilWriteSlave => extAxilWriteSlave,
dataClk => userEthClk,
dataClkRst => userEthClkRst,
dataObMaster => rssiIbMaster,
dataObSlave => rssiIbSlave,
dataIbMaster => rssiObMaster,
dataIbSlave => rssiObSlave,
clockHubInP => clockHubP,
clockHubInN => clockHubN,
syncHubP => syncHubP,
syncHubN => syncHubN,
clockOutP => clockOutP,
clockOutN => clockOutN,
syncOutP => syncOutP,
syncOutN => syncOutN,
syncOutNew => syncOutNew,
fpgaProgL => fpgaProgL,
rxDataP => rxDataP,
rxDataN => rxDataN,
txData => txData
);
-- DMA Interfaces are not used
dmaClk(2 downto 0) <= (others=>axiDmaClk);
dmaClkRst(2 downto 0) <= (others=>axiDmaRst);
--dmaObMaster(2 downto 0)
dmaObSlave(2 downto 0) <= dmaIbSlave(2 downto 0);
dmaIbMaster(2 downto 0) <= dmaObMaster(2 downto 0);
--dmaIbSlave(2 downto 0)
end architecture STRUCTURE;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LogicTest IS
END LogicTest;
ARCHITECTURE behavior OF LogicTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Logic
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
Issue : IN std_logic;
Op : IN std_logic_vector(1 downto 0);
Vj : IN std_logic_vector(31 downto 0);
Qj : IN std_logic_vector(4 downto 0);
Vk : IN std_logic_vector(31 downto 0);
Qk : IN std_logic_vector(4 downto 0);
CDBV : IN std_logic_vector(31 downto 0);
CDBQ : IN std_logic_vector(4 downto 0);
Grant : IN std_logic;
Available : OUT std_logic_vector(2 downto 0);
VOut : OUT std_logic_vector(31 downto 0);
QOut : OUT std_logic_vector(4 downto 0);
Request : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal Issue : std_logic := '0';
signal Op : std_logic_vector(1 downto 0) := (others => '0');
signal Vj : std_logic_vector(31 downto 0) := (others => '0');
signal Qj : std_logic_vector(4 downto 0) := (others => '0');
signal Vk : std_logic_vector(31 downto 0) := (others => '0');
signal Qk : std_logic_vector(4 downto 0) := (others => '0');
signal CDBV : std_logic_vector(31 downto 0) := (others => '0');
signal CDBQ : std_logic_vector(4 downto 0) := (others => '0');
signal Grant : std_logic := '0';
--Outputs
signal Available : std_logic_vector(2 downto 0);
signal VOut : std_logic_vector(31 downto 0);
signal QOut : std_logic_vector(4 downto 0);
signal Request : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Logic PORT MAP (
Clk => Clk,
Rst => Rst,
Issue => Issue,
Op => Op,
Vj => Vj,
Qj => Qj,
Vk => Vk,
Qk => Qk,
CDBV => CDBV,
CDBQ => CDBQ,
Grant => Grant,
Available => Available,
VOut => VOut,
QOut => QOut,
Request => Request
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Rst <='1';
wait for 100 ns;
Rst <='0';
wait for 100 ns;
Op <= "01";
Vj <= "00000000000000000000000000111000";
Vk <= "00000000000000000000000000000111";
Qj <= "00000";
Qk <= "00010";
wait for Clk_period*10;
Issue <='1';
wait for Clk_period*10;
Issue <='0';
wait for Clk_period*10;
CDBV <= "00000000000000000000000000010110";
CDBQ <= "00010";
wait for Clk_period*10;
Grant <= '1';
wait for Clk_period*10;
Grant <= '0';
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Reset with SW[0]. Clock counter and memory with KEY[0]
-- Each clock cycle reads a character from memory and shows it on the HEX display
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY display IS
PORT ( KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
SW : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );
END ENTITY;
ARCHITECTURE Behavior OF display IS
COMPONENT inst_mem
PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;
COMPONENT count3
PORT ( Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
CONSTANT A : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"41";
CONSTANT b : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"62";
CONSTANT C : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"43";
CONSTANT d : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"64";
CONSTANT E : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"45";
CONSTANT F : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"46";
CONSTANT g : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"67";
CONSTANT h : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"68";
SIGNAL Resetn, Clock : STD_LOGIC;
SIGNAL Count : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL Address : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL char : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
Resetn <= SW(0);
Clock <= KEY(0);
U1: count3 PORT MAP (Resetn, Clock, Count);
Address <= "00" & Count;
U2: inst_mem PORT MAP (Address, Clock, char);
LEDR <= "00" & char;
HEX0 <= "0001000" WHEN char = A ELSE
"0000011" WHEN char = b ELSE
"1000110" WHEN char = C ELSE
"0100001" WHEN char = d ELSE
"0000110" WHEN char = E ELSE
"0001110" WHEN char = F ELSE
"0010000" WHEN char = g ELSE
"0001011" WHEN char = h ELSE
"1111111";
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY count3 IS
PORT ( Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END count3;
ARCHITECTURE Behavior OF count3 IS
SIGNAL Count : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF (Resetn = '0') THEN
Count <= "000";
ELSIF (rising_edge(Clock)) THEN
Count <= Count + '1';
END IF;
END PROCESS;
Q <= Count;
END Behavior;
|
library ieee;
use ieee.std_logic_1164.all;
entity tb_tlc is
end entity tb_tlc;
architecture testbench of tb_tlc is
constant c_CLK_100MHZ_PERIOD : time := 10 ns;
signal s_clk_100MHz : std_logic;
signal s_reset : std_logic;
signal s_south : std_logic_vector(3 - 1 downto 0);
signal s_west : std_logic_vector(3 - 1 downto 0);
signal s_sens_s : std_logic;
signal s_sens_w : std_logic;
begin
uut_tlc : entity work.tlc
port map(
clk => s_clk_100MHz,
reset => s_reset,
south_o => s_south,
west_o => s_west,
sens_s => s_sens_s,
sens_w => s_sens_w
);
p_clk_gen : process
begin
while now < 10000 ns loop
s_clk_100MHz <= '0';
wait for c_CLK_100MHZ_PERIOD / 2;
s_clk_100MHz <= '1';
wait for c_CLK_100MHZ_PERIOD / 2;
end loop;
wait;
end process p_clk_gen;
p_reset_gen : process
begin
s_reset <= '0'; wait for 200 ns;
s_reset <= '1'; wait for 500 ns;
s_reset <= '0';
wait;
end process p_reset_gen;
p_stimulus : process
begin
wait for 745ns;
s_sens_s <= '0';
wait for 100ns;
s_sens_w <= '0';
wait for 100ns;
s_sens_s <= '0';
wait for 100ns;
s_sens_w <= '1';
wait for 100ns;
s_sens_s <= '1';
wait for 100ns;
s_sens_w <= '0';
wait for 100ns;
s_sens_s <= '1';
wait for 100ns;
s_sens_w <= '1';
wait for 100ns;
wait;
end process p_stimulus;
end architecture testbench;
|
<reponame>wesleygrignani/ccsds123.0-B-2_impl
-----------------------------------------------------------------------------------------------------
-- Name: <NAME>
-- Laboratory of Embedded and Distributed Systems (LEDS) - UNIVALI
-----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.ccsds123_b2_package.all;
entity mux_weight_mem is
port (i_weight_from_update : in std_logic_vector(WEIGHT_SIZE-1 downto 0);
i_weight_from_init : in std_logic_vector(WEIGHT_SIZE-1 downto 0);
i_sel : in std_logic;
o_weight_out : out std_logic_vector(WEIGHT_SIZE-1 downto 0));
end mux_weight_mem;
architecture Behavioral of mux_weight_mem is
begin
p_mux : process(i_weight_from_update, i_weight_from_init, i_sel)
begin
case i_sel is
when '1' => o_weight_out <= i_weight_from_init;
when '0' => o_weight_out <= i_weight_from_update;
when others => o_weight_out <= (others => '0');
end case;
end process p_mux;
end Behavioral;
|
<gh_stars>10-100
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package display_types is
type display_mode is (training, running, idle);
end package display_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.display_types.all;
USE work.lcd_types.all;
package display_components is
component display is
PORT (
reset, clock : IN STD_LOGIC;
mode : IN display_mode;
inputs : IN STD_LOGIC_VECTOR(15 downto 0);
class : IN CHAR;
lcd_dd : OUT CHAR_VECTOR(0 to 31);
lcd_cg : OUT CHAR_GRAPHICS_VECTOR(0 to 7)
);
end component;
end package;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE work.display_types.all;
USE work.lcd_types.all;
ENTITY display IS
PORT (
reset, clock : IN STD_LOGIC;
mode : IN display_mode;
inputs : IN STD_LOGIC_VECTOR(15 downto 0);
class : IN CHAR;
lcd_dd : OUT CHAR_VECTOR(0 to 31);
lcd_cg : OUT CHAR_GRAPHICS_VECTOR(0 to 7)
);
END ENTITY display;
ARCHITECTURE display OF display IS
BEGIN
-- character graphics
lcd_cg(0) <=
"00000"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000";
lcd_cg(1) <=
"00000"&
"00000"&
"00000"&
"00000"&
"11111"&
"11111"&
"11111"&
"00000";
lcd_cg(2) <=
"11111"&
"11111"&
"11111"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000";
lcd_cg(3) <=
"11111"&
"11111"&
"11111"&
"00000"&
"11111"&
"11111"&
"11111"&
"00000";
-- switch pattern display
lcd_dd(0) <= "000000" & inputs(15) & inputs(11);
lcd_dd(1) <= "000000" & inputs(14) & inputs(10);
lcd_dd(2) <= "000000" & inputs(13) & inputs(9);
lcd_dd(3) <= "000000" & inputs(12) & inputs(8);
lcd_dd(16) <= "000000" & inputs(7) & inputs(3);
lcd_dd(17) <= "000000" & inputs(6) & inputs(2);
lcd_dd(18) <= "000000" & inputs(5) & inputs(1);
lcd_dd(19) <= "000000" & inputs(4) & inputs(0);
-- NERUAL NET
lcd_dd(4 to 15) <= (x"20", x"4e", x"45", x"55", x"52", x"41", x"4c", x"20", x"4e", x"45", x"54", x"20");
with mode select lcd_dd(20 to 31) <=
-- Training...
(x"20", x"74", x"72", x"61", x"69", x"6e", x"69", x"6e", x"67", x"2e", x"2e", x"2e") when training,
-- Running...
(x"20", x"72", x"75", x"6e", x"6e", x"69", x"6e", x"67", x"2e", x"2e", x"2e", x"20") when running,
-- Pattern:
(x"20", x"70", x"61", x"74", x"74", x"65", x"72", x"6e", x"3a", x"20", class, x"20") when idle;
END ARCHITECTURE display;
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- COPYRIGHT (c) 2020 ALL RIGHT RESERVED
--
-- COMPANY: Ruhr-University Bochum, Security Engineering
-- AUTHOR: <NAME>
--
-- CREATE DATE: 06/05/2020
-- LAST CHANGES: 06/05/2020
-- MODULE NAME: AES_MixColumns
--
-- REVISION: 1.00 - File created
--
-- LICENCE: Please look at licence.txt
-- USAGE INFORMATION: Please look at readme.txt. If licence.txt or readme.txt
-- are missing or if you have questions regarding the code
-- please contact <NAME> (<EMAIL>) and
-- <NAME> (<EMAIL>)
--
-- THIS CODE AND INFORMATION ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
-- KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
-- PARTICULAR PURPOSE.
----------------------------------------------------------------------------------
-- IMPORTS
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- ENTITY
----------------------------------------------------------------------------------
ENTITY AES_MixColumns IS
PORT (
MC_IN : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
MC_OUT : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
END AES_MixColumns;
-- ARCHITECTURE
----------------------------------------------------------------------------------
ARCHITECTURE Structural OF AES_MixColumns IS
-- STRUCTURAL
----------------------------------------------------------------------------------
BEGIN
-- INSTANCES ------------------------------------------------------------------
Column1 : ENTITY work.AES_MixSingleColumn
PORT MAP (
COLUMN => MC_IN (127 DOWNTO 96),
RESULT => MC_OUT(127 DOWNTO 96)
);
Column2 : ENTITY work.AES_MixSingleColumn
PORT MAP (
COLUMN => MC_IN ( 95 DOWNTO 64),
RESULT => MC_OUT( 95 DOWNTO 64)
);
Column3 : ENTITY work.AES_MixSingleColumn
PORT MAP (
COLUMN => MC_IN ( 63 DOWNTO 32),
RESULT => MC_OUT( 63 DOWNTO 32)
);
Column4 : ENTITY work.AES_MixSingleColumn
PORT MAP (
COLUMN => MC_IN ( 31 DOWNTO 0),
RESULT => MC_OUT( 31 DOWNTO 0)
);
-------------------------------------------------------------------------------
END Structural;
|
--------------------------------------------------------------------------------
--
-- Module Name : small_sfifo32
--
-- Copyright 2009 by
-- Alpha Data Parallel Systems Ltd.
-- All Rights Reserved.
--
-- Original Author : <NAME>
-- Created :
--
-- Modified By :
-- Date :
-- Change Notes :
--
-- Description : Small Dual Port RAM Synchronous FIFO
--
-- Configurable data width, fixed depth of 32
--
--
-- Dependencies :
--
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND ALPHA DATA SPECIFICALLY DISCLAIMS ANY
-- WARRANTIES IMPLIED OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
entity small_sfifo64 is
generic (
width : integer := 64);
port (
clk : in std_logic;
rst : in std_logic;
wadv : in std_logic;
wdata : in std_logic_vector(width-1 downto 0);
nfull : out std_logic;
radv : in std_logic;
rempty : out std_logic;
rdata : out std_logic_vector(width-1 downto 0));
end small_sfifo64;
architecture rtl of small_sfifo64 is
type fifo_type is array (0 to 63) of std_logic_vector(width-1 downto 0);
signal ofifo_regs : fifo_type := (others => (others => '0'));
signal ofifo_rptr, ofifo_wptr : std_logic_vector(5 downto 0) := "000000";
signal ofifo_level : std_logic_vector(6 downto 0) := "0000000";
signal ofifo_out, ofifo_in : std_logic_vector(width-1 downto 0) := (others => '0');
signal ofifo_empty : std_logic := '1';
signal ofifo_wr, ofifo_rd, ofifo_wr1 : std_logic := '0';
begin -- rtl
ofifo_wr <= wadv;
ofifo_in <= wdata;
ofifo : process (clk)
begin -- process ofifo
if clk'event and clk = '1' then -- rising clock edge
if rst = '1' then -- asynchronous reset
ofifo_level <= "0000000";
ofifo_rptr <= "000000";
ofifo_wptr <= "000000";
ofifo_empty <= '1';
nfull <= '0';
ofifo_wr1 <= '0';
else
-- Delayed fifo write for improving timing at cost of
-- NFULL and EMPTY being delayed wrt WADV
-- FIFO may have 26 elements before NFULL asserted
ofifo_wr1 <= ofifo_wr;
if ofifo_wr1 = '1' and ofifo_rd = '0' then
ofifo_level <= ofifo_level+1;
ofifo_empty <= '0';
elsif ofifo_wr1 = '0' and ofifo_rd = '1' then
ofifo_level <= ofifo_level-1;
if ofifo_level = "0000001" then
ofifo_empty <= '1';
end if;
end if;
if ofifo_wr = '1' then
ofifo_wptr <= ofifo_wptr+1;
end if;
if ofifo_rd = '1' and ofifo_level /= "0000000" then
ofifo_rptr <= ofifo_rptr+1;
end if;
nfull <= ofifo_level(6) or ofifo_level(5);
end if;
end if;
end process ofifo;
process (clk) is
begin -- process
if rising_edge(clk) then -- rising clock edge
if ofifo_wr = '1' then
ofifo_regs(conv_integer(ofifo_wptr)) <= ofifo_in;
end if;
end if;
end process;
ofifo_out <= ofifo_regs(conv_integer(ofifo_rptr));
ofifo_rd <= radv and not ofifo_empty;
rempty <= ofifo_empty;
rdata <= ofifo_out;
end rtl;
|
<filename>modules/sfp_udpontrig/hdl/IPv4_TX.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer: <NAME>
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP TX
-- doesnt handle segmentation
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - fixed up setting of tx_result control defaults
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added handling of broadcast address
-- Revision 0.05 - Fix cks calc when add of high bits causes another ovf
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_TX is
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4_TX;
architecture Behavioral of IPv4_TX is
type tx_state_type is (
IDLE,
WAIT_MAC, -- waiting for response from ARP for mac lookup
WAIT_CHN, -- waiting for tx access to MAC channel
SEND_ETH_HDR, -- sending the ethernet header
SEND_IP_HDR, -- sending the IP header
SEND_USER_DATA -- sending the users data
);
type crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- Configuration
constant IP_TTL : std_logic_vector (7 downto 0) := x"08";--x"80";
-- TX state variables
signal tx_state : tx_state_type;
attribute fsm_encoding : string;
attribute fsm_encoding of tx_state : signal is "one_hot";
attribute fsm_safe_state : string;
attribute fsm_safe_state of tx_state : signal is "auto_safe_state";
attribute mark_debug : string;
attribute mark_debug of tx_state : signal is "true";
signal tx_count : unsigned (11 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal tx_mac : std_logic_vector (47 downto 0);
signal tx_mac_chn_reqd : std_logic;
signal tx_hdr_cks : std_logic_vector (23 downto 0);
signal mac_lookup_req : std_logic;
signal crc_state : crc_state_type;
signal arp_req_ip_reg : std_logic_vector (31 downto 0);
signal mac_data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_mac_value : std_logic_vector (47 downto 0);
signal set_tx_mac : std_logic;
signal tx_count_val : unsigned (11 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_chn_reqd : set_clr_type;
signal set_mac_lku_req : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
function inv_if_one(s1 : std_logic_vector; en : std_logic) return std_logic_vector is
--this function inverts all the bits of a vector if
--'en' is '1'.
variable Z : std_logic_vector(s1'high downto s1'low);
begin
for i in (s1'low) to s1'high loop
Z(i) := en xor s1(i);
end loop;
return Z;
end inv_if_one; -- end function
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
-- CHIPSCOPE ILA probes
signal probe6 : std_logic_vector(31 downto 0);
attribute keep : string;--keep name for ila probes
attribute keep of tx_state : signal is "true";
attribute keep of tx_count : signal is "true";
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
ip_tx_start, ip_tx, our_ip_address, our_mac_address, arp_req_rslt, --clk,
mac_tx_granted, mac_data_out_ready,
-- state variables
tx_state, tx_count, tx_result_reg, tx_mac, tx_mac_chn_reqd,
mac_lookup_req, tx_hdr_cks, arp_req_ip_reg, mac_data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_mac_value, set_tx_mac, tx_count_mode,
tx_data, set_last, set_chn_reqd, set_mac_lku_req, total_length,
tx_data_valid, tx_count_val
)
begin
-- set output followers
ip_tx_result <= tx_result_reg;
mac_tx_req <= tx_mac_chn_reqd;
arp_req_req.lookup_req <= mac_lookup_req;
arp_req_req.ip <= arp_req_ip_reg;
-- set initial values for combinatorial outputs
mac_data_out_first <= '0';
case tx_state is
when SEND_ETH_HDR | SEND_IP_HDR =>
mac_data_out <= tx_data;
tx_data_valid <= mac_data_out_ready; -- generated internally
mac_data_out_last <= set_last;
when SEND_USER_DATA =>
mac_data_out <= ip_tx.data.data_out;
tx_data_valid <= ip_tx.data.data_out_valid;
mac_data_out_last <= ip_tx.data.data_out_last;
when others =>
mac_data_out <= (others => '0');
tx_data_valid <= '0'; -- not transmitting during this phase
mac_data_out_last <= '0';
end case;
mac_data_out_valid <= tx_data_valid and mac_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
set_tx_mac <= '0';
set_chn_reqd <= HOLD;
set_mac_lku_req <= HOLD;
next_tx_result <= IPTX_RESULT_NONE;
set_tx_result <= '0';
tx_count_val <= (others => '0');
tx_mac_value <= (others => '0');
-- set temp signals
total_length <= std_logic_vector(unsigned(ip_tx.hdr.data_length) + 20); -- total length = user data length + header length (bytes)
-- TX FSM
case tx_state is
when IDLE =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
set_chn_reqd <= CLR;
if ip_tx_start = '1' then
-- check header count for error if too high
if unsigned(ip_tx.hdr.data_length) > 1480 then
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
else
next_tx_result <= IPTX_RESULT_SENDING;
set_tx_result <= '1';
-- TODO - check if we already have the mac addr for this ip, if so, bypass the WAIT_MAC state
if ip_tx.hdr.dst_ip_addr = IP_BC_ADDR then
-- for IP broadcast, dont need to look up the MAC addr
tx_mac_value <= MAC_BC_ADDR;
set_tx_mac <= '1';
next_tx_state <= WAIT_CHN;
set_tx_state <= '1';
else
-- need to req the mac address for this ip
set_mac_lku_req <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
end if;
end if;
else
set_mac_lku_req <= CLR;
end if;
when WAIT_MAC =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
set_mac_lku_req <= CLR; -- clear the request - will have been latched in the ARP layer
if arp_req_rslt.got_mac = '1' then
-- save the MAC we got back from the ARP lookup
tx_mac_value <= arp_req_rslt.mac;
set_tx_mac <= '1';
set_chn_reqd <= SET;
-- check for optimise when already have the channel
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
else
next_tx_state <= WAIT_CHN;
set_tx_state <= '1';
end if;
elsif arp_req_rslt.got_err = '1' then
set_mac_lku_req <= CLR;
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end if;
when WAIT_CHN =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
end if;
-- probably should handle a timeout here
when SEND_ETH_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"00d" then
tx_count_mode <= RST;
next_tx_state <= SEND_IP_HDR;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" =>
mac_data_out_first <= mac_data_out_ready;
tx_data <= tx_mac (47 downto 40); -- trg = mac from ARP lookup
when x"001" => tx_data <= tx_mac (39 downto 32);
when x"002" => tx_data <= tx_mac (31 downto 24);
when x"003" => tx_data <= tx_mac (23 downto 16);
when x"004" => tx_data <= tx_mac (15 downto 8);
when x"005" => tx_data <= tx_mac (7 downto 0);
when x"006" => tx_data <= our_mac_address (47 downto 40); -- src = our mac
when x"007" => tx_data <= our_mac_address (39 downto 32);
when x"008" => tx_data <= our_mac_address (31 downto 24);
when x"009" => tx_data <= our_mac_address (23 downto 16);
when x"00a" => tx_data <= our_mac_address (15 downto 8);
when x"00b" => tx_data <= our_mac_address (7 downto 0);
when x"00c" => tx_data <= x"08"; -- pkt type = 0800 : IP
when x"00d" => tx_data <= x"00";
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_IP_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"013" then
tx_count_val <= x"001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" => tx_data <= x"45"; -- v4, 5 words in hdr
when x"001" => tx_data <= x"00"; -- service type
when x"002" => tx_data <= total_length (15 downto 8); -- total length
when x"003" => tx_data <= total_length (7 downto 0);
when x"004" => tx_data <= x"00"; -- identification
when x"005" => tx_data <= x"00";
when x"006" => tx_data <= x"00"; -- flags and fragment offset
when x"007" => tx_data <= x"00";
when x"008" => tx_data <= IP_TTL; -- TTL
when x"009" => tx_data <= ip_tx.hdr.protocol; -- protocol
when x"00a" => tx_data <= tx_hdr_cks (15 downto 8); -- HDR checksum
when x"00b" => tx_data <= tx_hdr_cks (7 downto 0); -- HDR checksum
when x"00c" => tx_data <= our_ip_address (31 downto 24); -- src ip
when x"00d" => tx_data <= our_ip_address (23 downto 16);
when x"00e" => tx_data <= our_ip_address (15 downto 8);
when x"00f" => tx_data <= our_ip_address (7 downto 0);
when x"010" => tx_data <= ip_tx.hdr.dst_ip_addr (31 downto 24); -- dst ip
when x"011" => tx_data <= ip_tx.hdr.dst_ip_addr (23 downto 16);
when x"012" => tx_data <= ip_tx.hdr.dst_ip_addr (15 downto 8);
when x"013" => tx_data <= ip_tx.hdr.dst_ip_addr (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_USER_DATA =>
ip_tx_data_out_ready <= mac_data_out_ready;-- and mac_data_out_ready_reg; -- in this state, we are always ready to accept user data for tx
if mac_data_out_ready = '1' then
if ip_tx.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_SENT;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
if ip_tx.data.data_out_last = '0' then
next_tx_result <= IPTX_RESULT_ERR;
end if;
elsif ip_tx.data.data_out_last = '1' then
-- TX terminated due to receiving last indication from upstream - end with error
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= ip_tx.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk)--, reset, mac_data_out_ready_reg)
begin
-- if rising_edge(clk) then
-- mac_data_out_ready_reg <= mac_data_out_ready;
-- else
-- mac_data_out_ready_reg <= mac_data_out_ready_reg;
-- end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= x"000";
tx_result_reg <= IPTX_RESULT_NONE;
tx_mac <= (others => '0');
tx_mac_chn_reqd <= '0';
mac_lookup_req <= '0';
else
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- control arp lookup request
case set_mac_lku_req is
when SET =>
arp_req_ip_reg <= ip_tx.hdr.dst_ip_addr;
mac_lookup_req <= '1';
when CLR =>
mac_lookup_req <= '0';
arp_req_ip_reg <= arp_req_ip_reg;
when HOLD =>
mac_lookup_req <= mac_lookup_req;
arp_req_ip_reg <= arp_req_ip_reg;
end case;
-- save MAC
if set_tx_mac = '1' then
tx_mac <= tx_mac_value;
else
tx_mac <= tx_mac;
end if;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Process to calculate CRC in parallel with pkt out processing
-- this process must yield a valid CRC before it is required to be used in the hdr
-----------------------------------------------------------------------------
crc : process (clk)--, reset)
begin
if rising_edge(clk) then
case crc_state is
when IDLE =>
if ip_tx_start = '1' then
tx_hdr_cks <= x"004500"; -- vers & hdr len & service
crc_state <= TOT_LEN;
end if;
when TOT_LEN =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(total_length));
crc_state <= ID;
when ID =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= FLAGS;
when FLAGS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= TTL;
when TTL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(IP_TTL & ip_tx.hdr.protocol));
crc_state <= CKS;
when CKS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= SAH;
when SAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(31 downto 16)));
crc_state <= SAL;
when SAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(15 downto 0)));
crc_state <= DAH;
when DAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
crc_state <= DAL;
when DAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
crc_state <= ADDOVF;
when ADDOVF =>
tx_hdr_cks <= std_logic_vector ((unsigned(tx_hdr_cks) and x"00ffff")+ unsigned(tx_hdr_cks(23 downto 16)));
crc_state <= FINAL;
when FINAL =>
tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))), '1');
crc_state <= WAIT_END;
when WAIT_END =>
tx_hdr_cks <= tx_hdr_cks;
if ip_tx_start = '0' then
crc_state <= IDLE;
else
crc_state <= WAIT_END;
end if;
end case;
end if;
end process;
---------------------------------------------------------------------------
-- Chipscope ILA Debug purpose
---------------------------------------------------------------------------
ILA_GEN : IF True GENERATE--false GENERATE
My_chipscope_ila_probe_IP_TX_6 : entity work.ila_32x8K
PORT MAP (
clk => clk,
probe0 => probe6
);
probe6(11 downto 0)<=--tx_state&
std_logic_vector(tx_count);
probe6(31 downto 12)<=(others=>'0');
END GENERATE;
end Behavioral;
|
----------------------------------------------------------------------------------
-- COPYRIGHT (c) 2016 ALL RIGHT RESERVED
--
-- COMPANY: Ruhr-Universitaet Bochum, Chair for Embedded Security
-- AUTHOR: <NAME>
--
-- CREATE DATA: 17/11/2016
-- MODULE NAME: RoundFunction
--
-- REVISION: 1.00 - File created
--
-- LICENCE: Please look at licence.txt
-- USAGE INFORMATION: Please look at readme.txt. If licence.txt or readme.txt
-- are missing or if you have questions regarding the code
-- please contact <NAME> (<EMAIL>)
-- or <NAME> (<EMAIL>).
--
-- THIS CODE AND INFORMATION ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
-- KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
-- PARTICULAR PURPOSE.
----------------------------------------------------------------------------------
-- IMPORTS
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.SKINNYPKG.ALL;
-- ENTITY
----------------------------------------------------------------------------------
ENTITY RoundFunction IS
GENERIC (BS : BLOCK_SIZE := BLOCK_SIZE_128; TS : TWEAK_SIZE := TWEAK_SIZE_3N);
PORT (
-- KEY PORT -------------------------------------
ROUND_KEY : IN STD_LOGIC_VECTOR((GET_TWEAK_SIZE(BS, TS) - 1) DOWNTO 0);
ROUND_IN : IN STD_LOGIC_VECTOR((GET_BLOCK_SIZE(BS) - 1) DOWNTO 0);
ROUND_OUT : OUT STD_LOGIC_VECTOR((GET_BLOCK_SIZE(BS) - 1) DOWNTO 0);
CONST_IN : IN STD_LOGIC_VECTOR (5 downto 0));
END RoundFunction;
-- ARCHITECTURE : MIXED
----------------------------------------------------------------------------------
ARCHITECTURE Mixed OF RoundFunction IS
-- CONSTANTS ------------------------------------------------------------------
CONSTANT N : INTEGER := GET_BLOCK_SIZE(BS);
CONSTANT T : INTEGER := GET_TWEAK_SIZE(BS, TS);
CONSTANT W : INTEGER := GET_WORD_SIZE(BS);
-- SIGNALS --------------------------------------------------------------------
SIGNAL CURRENT_STATE, NEXT_STATE, KEY_ADDITION,
CONST_ADDITION, SUBSTITUTION, SHIFTROWS : STD_LOGIC_VECTOR((N - 1) DOWNTO 0);
--SIGNAL CONST : STD_LOGIC_VECTOR( 5 DOWNTO 0);
BEGIN
-- CONSTANT GENERATOR ---------------------------------------------------------
--ConstGen : ENTITY work.ConstGenerator
--PORT MAP (
--CLK => CLK,
--INIT => INIT,
--CONST => CONST
--);
-------------------------------------------------------------------------------
-- REGISTER -------------------------------------------------------------------
--R : ENTITY work.ScanFF
--GENERIC MAP (SIZE => N)
--PORT MAP (
-- CLK => CLK,
-- SE => INIT,
-- D => NEXT_STATE,
-- DS => ROUND_IN,
-- Q => CURRENT_STATE
--);
-------------------------------------------------------------------------------
-- S-BOX ----------------------------------------------------------------------
GEN : FOR I IN 0 TO 15 GENERATE
S : ENTITY work.SBox GENERIC MAP (BS => BS) PORT MAP (ROUND_IN((W * (I + 1) - 1) DOWNTO (W * I)), SUBSTITUTION((W * (I + 1) - 1) DOWNTO (W * I)));
END GENERATE;
-------------------------------------------------------------------------------
-- CONSTANT ADDITION ----------------------------------------------------------
N64 : IF BS = BLOCK_SIZE_64 GENERATE
CONST_ADDITION(63 DOWNTO 60) <= SUBSTITUTION(63 DOWNTO 60) XOR CONST_IN(3 DOWNTO 0);
CONST_ADDITION(59 DOWNTO 46) <= SUBSTITUTION(59 DOWNTO 46);
CONST_ADDITION(45 DOWNTO 44) <= SUBSTITUTION(45 DOWNTO 44) XOR CONST_IN(5 DOWNTO 4);
CONST_ADDITION(43 DOWNTO 30) <= SUBSTITUTION(43 DOWNTO 30);
CONST_ADDITION(29) <= NOT(SUBSTITUTION(29));
CONST_ADDITION(28 DOWNTO 0) <= SUBSTITUTION(28 DOWNTO 0);
END GENERATE;
N128 : IF BS = BLOCK_SIZE_128 GENERATE
CONST_ADDITION(127 DOWNTO 124) <= SUBSTITUTION(127 DOWNTO 124);
CONST_ADDITION(123 DOWNTO 120) <= SUBSTITUTION(123 DOWNTO 120) XOR CONST_IN(3 DOWNTO 0);
CONST_ADDITION(119 DOWNTO 90) <= SUBSTITUTION(119 DOWNTO 90);
CONST_ADDITION( 89 DOWNTO 88) <= SUBSTITUTION( 89 DOWNTO 88) XOR CONST_IN(5 DOWNTO 4);
CONST_ADDITION( 87 DOWNTO 58) <= SUBSTITUTION( 87 DOWNTO 58);
CONST_ADDITION(57) <= NOT(SUBSTITUTION(57));
CONST_ADDITION( 56 DOWNTO 0) <= SUBSTITUTION( 56 DOWNTO 0);
END GENERATE;
-------------------------------------------------------------------------------
-- SUBKEY ADDITION ------------------------------------------------------------
T1N : IF TS = TWEAK_SIZE_1N GENERATE
KEY_ADDITION((16 * W - 1) DOWNTO (12 * W)) <= CONST_ADDITION((16 * W - 1) DOWNTO (12 * W)) XOR ROUND_KEY((16 * W - 1) DOWNTO (12 * W));
KEY_ADDITION((12 * W - 1) DOWNTO ( 8 * W)) <= CONST_ADDITION((12 * W - 1) DOWNTO ( 8 * W)) XOR ROUND_KEY((12 * W - 1) DOWNTO ( 8 * W));
END GENERATE;
T2N : IF TS = TWEAK_SIZE_2N GENERATE
KEY_ADDITION((16 * W - 1) DOWNTO (12 * W)) <= CONST_ADDITION((16 * W - 1) DOWNTO (12 * W)) XOR ROUND_KEY((1 * N + 16 * W - 1) DOWNTO (1 * N + 12 * W)) XOR ROUND_KEY((16 * W - 1) DOWNTO (12 * W));
KEY_ADDITION((12 * W - 1) DOWNTO ( 8 * W)) <= CONST_ADDITION((12 * W - 1) DOWNTO ( 8 * W)) XOR ROUND_KEY((1 * N + 12 * W - 1) DOWNTO (1 * N + 8 * W)) XOR ROUND_KEY((12 * W - 1) DOWNTO ( 8 * W));
END GENERATE;
T3N : IF TS = TWEAK_SIZE_3N GENERATE
KEY_ADDITION((16 * W - 1) DOWNTO (12 * W)) <= CONST_ADDITION((16 * W - 1) DOWNTO (12 * W)) XOR ROUND_KEY((2 * N + 16 * W - 1) DOWNTO (2 * N + 12 * W)) XOR ROUND_KEY((1 * N + 16 * W - 1) DOWNTO (1 * N + 12 * W)) XOR ROUND_KEY((16 * W - 1) DOWNTO (12 * W));
KEY_ADDITION((12 * W - 1) DOWNTO ( 8 * W)) <= CONST_ADDITION((12 * W - 1) DOWNTO ( 8 * W)) XOR ROUND_KEY((2 * N + 12 * W - 1) DOWNTO (2 * N + 8 * W)) XOR ROUND_KEY((1 * N + 12 * W - 1) DOWNTO (1 * N + 8 * W)) XOR ROUND_KEY((12 * W - 1) DOWNTO ( 8 * W));
END GENERATE;
KEY_ADDITION(( 8 * W - 1) DOWNTO ( 4 * W)) <= CONST_ADDITION(( 8 * W - 1) DOWNTO ( 4 * W));
KEY_ADDITION(( 4 * W - 1) DOWNTO ( 0 * W)) <= CONST_ADDITION(( 4 * W - 1) DOWNTO ( 0 * W));
-------------------------------------------------------------------------------
-- SHIFT ROWS -----------------------------------------------------------------
SR : ENTITY work.ShiftRows GENERIC MAP (BS => BS) PORT MAP (KEY_ADDITION, SHIFTROWS);
-------------------------------------------------------------------------------
-- MIX COLUMNS ----------------------------------------------------------------
MC : ENTITY work.MixColumns GENERIC MAP (BS => BS) PORT MAP (SHIFTROWS, NEXT_STATE);
-------------------------------------------------------------------------------
-- ROUND OUTPUT ---------------------------------------------------------------
ROUND_OUT <= NEXT_STATE;
-------------------------------------------------------------------------------
--CONST_OUT <= CONST;
-- DONE -----------------------------------------------------------------------
--CHK1 : IF BS = BLOCK_SIZE_64 AND TS = TWEAK_SIZE_1N GENERATE DONE <= '1' WHEN (CONST = "111000") ELSE '0'; END GENERATE;
--CHK2 : IF BS = BLOCK_SIZE_64 AND TS = TWEAK_SIZE_2N GENERATE DONE <= '1' WHEN (CONST = "001101") ELSE '0'; END GENERATE;
--CHK3 : IF BS = BLOCK_SIZE_64 AND TS = TWEAK_SIZE_3N GENERATE DONE <= '1' WHEN (CONST = "011010") ELSE '0'; END GENERATE;
--CHK4 : IF BS = BLOCK_SIZE_128 AND TS = TWEAK_SIZE_1N GENERATE DONE <= '1' WHEN (CONST = "011010") ELSE '0'; END GENERATE;
--CHK5 : IF BS = BLOCK_SIZE_128 AND TS = TWEAK_SIZE_2N GENERATE DONE <= '1' WHEN (CONST = "000100") ELSE '0'; END GENERATE;
--CHK6 : IF BS = BLOCK_SIZE_128 AND TS = TWEAK_SIZE_3N GENERATE DONE <= '1' WHEN (CONST = "001010") ELSE '0'; END GENERATE;
-------------------------------------------------------------------------------
END Mixed;
|
<reponame>tukl-msd/median.demonstrator
----------------------------------------------------------------------------------
-- Company: Trenz Electronic GmbH
-- Engineer: <NAME>
----------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
----------------------------------------------------------------------------------
entity axis_raw_unpack_v1_0 is
generic (
C_IMP_TYPE : integer range 0 to 1 := 0;
C_OUT_TYPE : integer range 1 to 4 := 4
);
port (
axis_aclk : in STD_LOGIC;
axis_aresetn : in STD_LOGIC;
-- Ports of Axi Slave Bus Interface S_AXIS
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR(15 downto 0);
s_axis_tuser : in STD_LOGIC;
s_axis_tlast : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
-- Ports of Axi Master Bus Interface M_AXIS
m_axis_tvalid : out STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR(C_OUT_TYPE*16-1 downto 0);
m_axis_tuser : out STD_LOGIC;
m_axis_tlast : out STD_LOGIC;
m_axis_tready : in STD_LOGIC
);
end axis_raw_unpack_v1_0;
----------------------------------------------------------------------------------
architecture arch_imp of axis_raw_unpack_v1_0 is
----------------------------------------------------------------------------------
constant C_DEVICE : STRING := "7SERIES";
constant C_FIFO_SIZE : STRING := "18Kb";
type sm_rx_state_type is (ST_IDLE, ST_PA, ST_PB, ST_PC, ST_PD);
signal sm_rx_state : sm_rx_state_type := ST_IDLE;
type sm_tx_state_type is (ST_WAIT, ST_TXA, ST_TXB, ST_TXC, ST_TXD);
signal sm_tx_state : sm_tx_state_type := ST_WAIT;
type sm_rxp_state_type is (ST_PIDLE, ST_PPA, ST_PPB, ST_PPC, ST_PPD, ST_PPW);
signal sm_rxp_state : sm_rxp_state_type := ST_PIDLE;
signal pixels_data : STD_LOGIC_VECTOR(39 downto 0);
signal last : STD_LOGIC;
signal user : STD_LOGIC;
signal pixel_a : STD_LOGIC_VECTOR(9 downto 0);
signal pixel_b : STD_LOGIC_VECTOR(9 downto 0);
signal pixel_c : STD_LOGIC_VECTOR(9 downto 0);
signal pixel_d : STD_LOGIC_VECTOR(9 downto 0);
signal pixels_valid : STD_LOGIC;
signal buffer_we : STD_LOGIC;
signal buffer_re : STD_LOGIC;
signal buffer_full : STD_LOGIC;
signal buffer_empty : STD_LOGIC;
signal buffer_in_data : STD_LOGIC_VECTOR(41 downto 0);
signal buffer_out_data : STD_LOGIC_VECTOR(41 downto 0);
component srl_fifo is
generic(
C_DEPTH : integer := 32;
C_WIDTH : integer := 8
);
port (
clk_in : in STD_LOGIC;
we_in : in STD_LOGIC;
re_in : in STD_LOGIC;
full_out : out STD_LOGIC;
empty_out : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0);
data_out : out STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0)
);
end component;
----------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
-- 16 bit input implementation
process(axis_aclk)
begin
if(axis_aclk = '1' and axis_aclk'event)then
case sm_rx_state is
when ST_IDLE =>
buffer_we <= '0';
if(s_axis_tvalid = '1')then
pixels_data( 9 downto 2) <= s_axis_tdata( 7 downto 0); -- P0
pixels_data(19 downto 12) <= s_axis_tdata(15 downto 8); -- P1
user <= s_axis_tuser;
if(s_axis_tlast /= '1')then
sm_rx_state <= ST_PA;
end if;
end if;
when ST_PA =>
buffer_we <= '0';
if(s_axis_tvalid = '1')then
pixels_data(29 downto 22) <= s_axis_tdata( 7 downto 0); -- P2
pixels_data(39 downto 32) <= s_axis_tdata(15 downto 8); -- P3
if(s_axis_tuser = '1')then -- Problem
sm_rx_state <= ST_PA;
elsif(s_axis_tlast /= '1')then
sm_rx_state <= ST_PB;
else
sm_rx_state <= ST_IDLE;
end if;
end if;
when ST_PB =>
if((s_axis_tvalid = '1') and (buffer_full = '0'))then
pixel_a( 9 downto 2) <= pixels_data( 9 downto 2);
pixel_a( 1 downto 0) <= s_axis_tdata( 1 downto 0);
pixel_b( 9 downto 2) <= pixels_data(19 downto 12);
pixel_b( 1 downto 0) <= s_axis_tdata( 3 downto 2);
pixel_c( 9 downto 2) <= pixels_data(29 downto 22);
pixel_c( 1 downto 0) <= s_axis_tdata( 5 downto 4);
pixel_d( 9 downto 2) <= pixels_data(39 downto 32);
pixel_d( 1 downto 0) <= s_axis_tdata( 7 downto 6);
last <= s_axis_tlast;
buffer_we <= '1';
pixels_data( 9 downto 2) <= s_axis_tdata(15 downto 8);
if(s_axis_tuser = '1')then -- Problem
sm_rx_state <= ST_PA;
elsif(s_axis_tlast /= '1')then
sm_rx_state <= ST_PC;
else
sm_rx_state <= ST_IDLE;
end if;
end if;
when ST_PC =>
buffer_we <= '0';
if(s_axis_tvalid = '1')then
pixels_data(19 downto 12) <= s_axis_tdata( 7 downto 0); -- P1
pixels_data(29 downto 22) <= s_axis_tdata(15 downto 8); -- P2
if(s_axis_tuser = '1')then -- Problem
sm_rx_state <= ST_PA;
elsif(s_axis_tlast /= '1')then
sm_rx_state <= ST_PD;
else
sm_rx_state <= ST_IDLE;
end if;
end if;
when ST_PD =>
if((s_axis_tvalid = '1') and (buffer_full = '0'))then
pixel_a( 9 downto 2) <= pixels_data( 9 downto 2);
pixel_a( 1 downto 0) <= s_axis_tdata( 9 downto 8);
pixel_b( 9 downto 2) <= pixels_data(19 downto 12);
pixel_b( 1 downto 0) <= s_axis_tdata(11 downto 10);
pixel_c( 9 downto 2) <= pixels_data(29 downto 22);
pixel_c( 1 downto 0) <= s_axis_tdata(13 downto 12);
pixel_d( 9 downto 2) <= s_axis_tdata( 7 downto 0);
pixel_d( 1 downto 0) <= s_axis_tdata(15 downto 14);
buffer_we <= '1';
user <= '0';
last <= s_axis_tlast;
if(s_axis_tuser = '1')then -- Problem
sm_rx_state <= ST_PA;
else
sm_rx_state <= ST_IDLE;
end if;
end if;
end case;
end if;
end process;
process(sm_rx_state, pixels_valid)
begin
case sm_rx_state is
when ST_IDLE => s_axis_tready <= '1';
when ST_PA => s_axis_tready <= '1';
when ST_PB => s_axis_tready <= not buffer_full;
when ST_PC => s_axis_tready <= '1';
when ST_PD => s_axis_tready <= not buffer_full;
end case;
end process;
----------------------------------------------------------------------------------
reg_buf_gen: if C_IMP_TYPE = 0 generate
begin
process(axis_aclk)
begin
if(axis_aclk = '1' and axis_aclk'event)then
if(pixels_valid = '0')then
if(((sm_rx_state = ST_PB) or (sm_rx_state = ST_PD)) and (s_axis_tvalid = '1'))then
pixels_valid <= '1';
end if;
else
if(buffer_re = '1')then
pixels_valid <= '0';
end if;
end if;
end if;
end process;
buffer_full <= pixels_valid;
buffer_empty <= not pixels_valid;
buffer_out_data <= last & user & pixel_d & pixel_c & pixel_b & pixel_a;
end generate;
----------------------------------------------------------------------------------
fifo_buf_gen: if C_IMP_TYPE = 1 generate
begin
buffer_in_data <= last & user & pixel_d & pixel_c & pixel_b & pixel_a;
FIFO_inst: srl_fifo
generic map(
C_DEPTH => 32,
C_WIDTH => 42
)
port map(
clk_in => axis_aclk,
we_in => buffer_we,
re_in => buffer_re,
full_out => buffer_full,
empty_out => buffer_empty,
data_in => buffer_in_data,
data_out => buffer_out_data
);
end generate;
----------------------------------------------------------------------------------
serial_out_gen: if C_OUT_TYPE = 1 generate
begin
process(axis_aclk)
begin
if(axis_aclk = '1' and axis_aclk'event)then
case sm_tx_state is
when ST_WAIT =>
if(buffer_empty = '0')then
m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0);
m_axis_tuser <= buffer_out_data(40);
m_axis_tlast <= '0';
sm_tx_state <= ST_TXA;
end if;
when ST_TXA =>
if(m_axis_tready = '1')then
m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(19 downto 10);
m_axis_tuser <= '0';
m_axis_tlast <= '0';
sm_tx_state <= ST_TXB;
end if;
when ST_TXB =>
if(m_axis_tready = '1')then
m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(29 downto 20);
m_axis_tuser <= '0';
m_axis_tlast <= '0';
sm_tx_state <= ST_TXC;
end if;
when ST_TXC =>
if(m_axis_tready = '1')then
m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(39 downto 30);
m_axis_tuser <= '0';
m_axis_tlast <= buffer_out_data(41);
sm_tx_state <= ST_TXD;
end if;
when ST_TXD =>
if(m_axis_tready = '1')then
if(buffer_empty = '0')then
m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0);
m_axis_tuser <= buffer_out_data(40);
m_axis_tlast <= '0';
sm_tx_state <= ST_TXA;
else
sm_tx_state <= ST_WAIT;
m_axis_tlast <= '0';
end if;
end if;
end case;
end if;
end process;
buffer_re <= '1' when ((sm_tx_state = ST_TXC) and (m_axis_tready = '1')) else '0';
m_axis_tvalid <= '1' when (sm_tx_state /= ST_WAIT) else '0';
end generate; -- serial_out_gen
parallel4_out_gen: if C_OUT_TYPE = 4 generate
begin
m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0);
m_axis_tdata(31 downto 16) <= "000000" & buffer_out_data(19 downto 10);
m_axis_tdata(47 downto 32) <= "000000" & buffer_out_data(29 downto 20);
m_axis_tdata(63 downto 48) <= "000000" & buffer_out_data(39 downto 30);
m_axis_tuser <= buffer_out_data(40);
m_axis_tlast <= buffer_out_data(41);
m_axis_tvalid <= not buffer_empty;
buffer_re <= m_axis_tready;
end generate; -- parallel4_out_gen
----------------------------------------------------------------------------------
end arch_imp;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use WORK.constants.all;
entity shifter is
generic( NBIT : integer := NUMBIT_DATA);
port( A: in std_logic_vector(NBIT-1 downto 0);
B: in std_logic_vector(NBIT-1 downto 0);
logic_arith: in std_logic; -- 0 logic 1 arith
right_left: in std_logic; -- 0 right 1 left
shifter_out: out std_logic_vector(NBIT-1 downto 0));
end entity;
architecture structural of shifter is
component MUX21_GENERIC is
generic(NBIT: integer := NBIT+8);
Port (a: In std_logic_vector(NBIT-1 downto 0);
b: In std_logic_vector(NBIT-1 downto 0);
sel: In std_logic;
Y: Out std_logic_vector(NBIT-1 downto 0));
end component;
component MUX41_GENERIC is
generic(NBIT: integer := NBIT+8);
Port( a:in std_logic_vector(NBIT-1 downto 0);
b: in std_logic_vector(NBIT-1 downto 0);
c: in std_logic_vector(NBIT-1 downto 0);
d: in std_logic_vector(NBIT-1 downto 0);
sel: in std_logic_vector(1 downto 0);
Y: out std_logic_vector(NBIT-1 downto 0));
end component;
component MUX81_GENERIC is
generic(NBIT: integer := NBIT);
Port( a:In std_logic_vector(NBIT-1 downto 0);
b: In std_logic_vector(NBIT-1 downto 0);
c: In std_logic_vector(NBIT-1 downto 0);
d: In std_logic_vector(NBIT-1 downto 0);
e: In std_logic_vector(NBIT-1 downto 0);
f: In std_logic_vector(NBIT-1 downto 0);
g: In std_logic_vector(NBIT-1 downto 0);
h: In std_logic_vector(NBIT-1 downto 0);
sel: In std_logic_vector(2 downto 0);
Y: Out std_logic_vector(NBIT-1 downto 0));
end component;
type first_masks_array is array(0 to NBIT/8-1) of std_logic_vector(NBIT+7 downto 0);
type second_masks_array is array(0 to 7) of std_logic_vector(NBIT-1 downto 0);
signal right_masks_array: first_masks_array;
signal left_masks_array: first_masks_array;
signal chosen_array: first_masks_array;
signal chosen_mask: std_logic_vector(NBIT+7 downto 0);
signal second_masks: second_masks_array;
signal third_sel: std_logic_vector(2 downto 0);
begin
-- STEP 1: Mask preparation and Pre-Shift
-- 4 Mask generarion for Left and Right shift and take care about if it is logic operation or arithmetic
STEP1_MASKS: for i in 1 to NBIT/8 generate
right_masks_array(i-1)(NBIT+7 downto NBIT+8-8*i) <= (others => (A(NBIT-1) and logic_arith));
right_masks_array(i-1)(NBIT+7-8*i downto 0) <= A(NBIT-1 downto 8*(i-1));
left_masks_array(i-1)(NBIT+7 downto 8*i-1) <= '0' & A(NBIT-8*(i-1)-1 downto 0);
left_masks_array(i-1)(8*i-2 downto 0) <= (others => '0');
end generate;
-- Select Left Mask or Right Mask
STEP1: for i in 0 to NBIT/8-1 generate
MUX21_i : MUX21_GENERIC port map(left_masks_array(i), right_masks_array(i), right_left, chosen_array(i));
end generate;
-- STEP 2: Coarse Grain Shift
-- Use MSB(4 and 3) of B to chooses among the 4 masks the nearest to the shift to be operated
STEP2: MUX41_GENERIC port map(chosen_array(3), chosen_array(2), chosen_array(1), chosen_array(0), B(4 downto 3), chosen_mask);
-- Prepare the 8 possible configuration of the chosen mask
STEP2_MASKS: for i in 0 to 7 generate
second_masks(i) <= chosen_mask(NBIT+i-1 downto i);
end generate;
-- STEP 3: Fine Grain Shift
-- Use LSB(2, 1 and 0) of B to chooses among the 8 configuration the correct shift (implement the real shift)
third_sel(2) <= B(2) xor right_left;
third_sel(1) <= B(1) xor right_left;
third_sel(0) <= B(0) xor right_left;
STEP3: MUX81_GENERIC port map(second_masks(7), second_masks(6), second_masks(5), second_masks(4), second_masks(3), second_masks(2), second_masks(1), second_masks(0), third_sel, shifter_out);
end architecture;
|
<reponame>lsst-camera-daq/surf<filename>protocols/jesd204b/rtl/Jesd204bPkg.vhd
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: JESD204B Package File
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library surf;
use surf.StdRtlPkg.all;
package Jesd204bPkg is
-- Constant definitions
--------------------------------------------------------------------------
-- Number of bytes in MGT word (2 or 4).
constant GT_WORD_SIZE_C : positive := 4;
-- 8B10B characters (8-bit values)
-- K.28.5
constant K_CHAR_C : slv(7 downto 0) := x"BC";
-- K.28.0
constant R_CHAR_C : slv(7 downto 0) := x"1C";
-- K.28.3
constant A_CHAR_C : slv(7 downto 0) := x"7C";
-- K.28.7
constant F_CHAR_C : slv(7 downto 0) := x"FC";
-- Register or counter widths
constant SYSRF_DLY_WIDTH_C : positive := 8;
constant RX_STAT_WIDTH_C : positive := 19 + 2*GT_WORD_SIZE_C;
constant TX_STAT_WIDTH_C : positive := 6;
-- AXI packet size at power up
constant AXI_PACKET_SIZE_DEFAULT_C : slv(23 downto 0) := x"00_01_00";
-- TX specific
-- Ramp step or square wave period slv width (max 16)
constant PER_STEP_WIDTH_C : positive := 16;
-- Scrambler/Descrambler PBRS taps for 1 + x^14 + x^15
constant JESD_PRBS_TAPS_C : NaturalArray := (0 => 14, 1 => 15);
-- Sub-types
--------------------------------------------------------------------------
type jesdGtRxLaneType is record
data : slv((GT_WORD_SIZE_C*8)-1 downto 0); -- PHY receive data
dataK : slv(GT_WORD_SIZE_C-1 downto 0); -- PHY receive data is K character
dispErr : slv(GT_WORD_SIZE_C-1 downto 0); -- PHY receive data has disparity error
decErr : slv(GT_WORD_SIZE_C-1 downto 0); -- PHY receive data not in table
rstDone : sl;
cdrStable : sl;
end record jesdGtRxLaneType;
constant JESD_GT_RX_LANE_INIT_C : jesdGtRxLaneType := (
data => (others => '0'),
dataK => (others => '0'),
dispErr => (others => '0'),
decErr => (others => '0'),
rstDone => '0',
cdrStable => '0'
);
type jesdGtTxLaneType is record
data : slv((GT_WORD_SIZE_C*8)-1 downto 0); -- PHY receive data
dataK : slv(GT_WORD_SIZE_C-1 downto 0); -- PHY receive data is K character
end record jesdGtTxLaneType;
constant JESD_GT_TX_LANE_INIT_C : jesdGtTxLaneType := (
data => (others => '0'),
dataK => (others => '0'));
-- Arrays
type jesdGtRxLaneTypeArray is array (natural range <>) of jesdGtRxLaneType;
type jesdGtTxLaneTypeArray is array (natural range <>) of jesdGtTxLaneType;
type fixLatDataArray is array (natural range <>) of slv((GT_WORD_SIZE_C*8+GT_WORD_SIZE_C*2)-1 downto 0);
type sampleDataArray is array (natural range <>) of slv((GT_WORD_SIZE_C*8)-1 downto 0);
type sampleDataVectorArray is array (natural range<>, natural range<>) of slv((GT_WORD_SIZE_C*8)-1 downto 0);
type rxStatuRegisterArray is array (natural range <>) of slv((RX_STAT_WIDTH_C)-1 downto 0);
type txStatuRegisterArray is array (natural range <>) of slv((TX_STAT_WIDTH_C)-1 downto 0);
type alignTxArray is array (natural range <>) of slv((GT_WORD_SIZE_C)-1 downto 0);
-- Functions
--------------------------------------------------------------------------
-- Detect K character
function detKcharFunc(data_slv : slv; charisk_slv : slv; bytes_int : positive) return std_logic;
-- Output variable index from SLV (use in variable length shift register)
function varIndexOutFunc(shft_slv : slv; index_slv : slv) return std_logic;
-- Detect position of first non K character (Swapped)
function detectPosFuncSwap(data_slv : slv; charisk_slv : slv; bytes_int : positive) return std_logic_vector;
-- Detect position of first non K character
function detectPosFunc(data_slv : slv; charisk_slv : slv; bytes_int : positive) return std_logic_vector;
-- Byte swap slv (bytes int 2 or 4)
function byteSwapSlv(data_slv : slv; bytes_int : positive) return std_logic_vector;
-- Swap little and big endians (bytes int 2 or 4)
function endianSwapSlv(data_slv : slv; bytes_int : positive) return std_logic_vector;
-- Align the data within the data buffer according to the position of the byte alignment word
function JesdDataAlign(data_slv : slv; position_slv : slv; bytes_int : positive) return std_logic_vector;
-- Align the character within the buffer according to the position of the byte alignment word
function JesdCharAlign(char_slv : slv; position_slv : slv; bytes_int : positive) return std_logic_vector;
-- Convert standard logic vector to integer
function slvToInt(data_slv : slv) return integer;
-- Convert integer to standard logic vector
function intToSlv(data_int : integer; bytes_int : positive) return std_logic_vector;
-- Output offset binary zero
function outSampleZero(F_int : positive; bytes_int : positive) return std_logic_vector;
-- Invert functions
-- Invert signed
function invSigned(input : slv) return std_logic_vector;
function invData(data : slv; F_int : positive; bytes_int : positive) return std_logic_vector;
procedure jesdScrambler (
dataIn : in slv(15 downto 0);
lfsrIn : in slv(14 downto 0);
dataOut : inout slv(15 downto 0);
lfsrOut : inout slv(14 downto 0));
end Jesd204bPkg;
package body Jesd204bPkg is
-- Functions
--------------------------------------------------------------------------
-- Detect K character
function detKcharFunc(data_slv : slv; charisk_slv : slv; bytes_int : positive) return std_logic is
begin
if(bytes_int = 2) then
if(data_slv (7 downto 0) = K_CHAR_C and
data_slv (15 downto 8) = K_CHAR_C and
charisk_slv = (charisk_slv'range => '1')
) then
return '1';
else
return '0';
end if;
elsif(bytes_int = 4) then
if(data_slv (7 downto 0) = K_CHAR_C and
data_slv (15 downto 8) = K_CHAR_C and
data_slv (23 downto 16) = K_CHAR_C and
data_slv (31 downto 24) = K_CHAR_C and
charisk_slv = (charisk_slv'range => '1')
) then
return '1';
else
return '0';
end if;
else
return '0';
end if;
end detKcharFunc;
-- Output variable index from SLV (use in variable length shift register)
function varIndexOutFunc(shft_slv : slv; index_slv : slv) return std_logic is
variable i : integer;
begin
-- Return the index
i := to_integer(unsigned(index_slv));
return shft_slv(i);
end varIndexOutFunc;
-- Detect position of first non K character
function detectPosFunc(data_slv : slv; charisk_slv : slv; bytes_int : positive) return std_logic_vector is
begin
-- GT word is 2 bytes
if(bytes_int = 2) then
if(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C
) then
return "01";
elsif(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) = K_CHAR_C and
charisk_slv(1) = '1'
) then
return "10";
else
return "11";
end if;
-- GT word is 4 bytes wide
elsif(bytes_int = 4) then
if(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C and
data_slv (23 downto 16) /= K_CHAR_C and
data_slv (31 downto 24) /= K_CHAR_C
) then
return "0001";
elsif(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C and
data_slv (23 downto 16) /= K_CHAR_C and
data_slv (31 downto 24) = K_CHAR_C and
charisk_slv(3) = '1'
) then
return "0010";
elsif(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C and
data_slv (23 downto 16) = K_CHAR_C and
data_slv (31 downto 24) = K_CHAR_C and
charisk_slv(3 downto 2) = "11"
) then
return "0100";
elsif(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) = K_CHAR_C and
data_slv (23 downto 16) = K_CHAR_C and
data_slv (31 downto 24) = K_CHAR_C and
charisk_slv(3 downto 1) = "111"
) then
return "1000";
else
return "1111";
end if;
else
return (bytes_int-1 downto 0 => '1');
end if;
end detectPosFunc;
-- Detect position of first non K character (Swapped bits/bytes)
function detectPosFuncSwap(data_slv : slv; charisk_slv : slv; bytes_int : positive) return std_logic_vector is
begin
-- GT word is 2 bytes
if(bytes_int = 2) then
if(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C
) then
return "01";
elsif(data_slv (7 downto 0) = K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C and
charisk_slv(0) = '1'
) then
return "10";
else
return "11";
end if;
-- GT word is 4 bytes wide
elsif(bytes_int = 4) then
if(data_slv (7 downto 0) /= K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C and
data_slv (23 downto 16) /= K_CHAR_C and
data_slv (31 downto 24) /= K_CHAR_C
) then
return "0001";
elsif(data_slv (7 downto 0) = K_CHAR_C and
data_slv (15 downto 8) /= K_CHAR_C and
data_slv (23 downto 16) /= K_CHAR_C and
data_slv (31 downto 24) /= K_CHAR_C and
charisk_slv(0) = '1'
) then
return "0010";
elsif(data_slv (7 downto 0) = K_CHAR_C and
data_slv (15 downto 8) = K_CHAR_C and
data_slv (23 downto 16) /= K_CHAR_C and
data_slv (31 downto 24) /= K_CHAR_C and
charisk_slv(1 downto 0) = "11"
) then
return "0100";
elsif(data_slv (7 downto 0) = K_CHAR_C and
data_slv (15 downto 8) = K_CHAR_C and
data_slv (23 downto 16) = K_CHAR_C and
data_slv (31 downto 24) /= K_CHAR_C and
charisk_slv(2 downto 0) = "111"
) then
return "1000";
else
return "1111";
end if;
else
return (bytes_int-1 downto 0 => '1');
end if;
end detectPosFuncSwap;
-- Byte swap slv (bytes int 2 or 4)
function byteSwapSlv(data_slv : slv; bytes_int : positive) return std_logic_vector is
begin
if(bytes_int = 2) then
return data_slv(7 downto 0) & data_slv(15 downto 8);
elsif(bytes_int = 4) then
return data_slv(7 downto 0) & data_slv(15 downto 8) & data_slv(23 downto 16) & data_slv(31 downto 24);
else
return data_slv;
end if;
end byteSwapSlv;
-- Swap little or big endian (bytes int 2 or 4)
function endianSwapSlv(data_slv : slv; bytes_int : positive) return std_logic_vector is
begin
if(bytes_int = 2) then
return data_slv;
elsif(bytes_int = 4) then
return data_slv(15 downto 0) & data_slv(31 downto 16);
else
return data_slv;
end if;
end endianSwapSlv;
-- Align the data within the data buffer according to the position of the byte alignment word
function JesdDataAlign(data_slv : slv; position_slv : slv; bytes_int : positive) return std_logic_vector is
begin
if(bytes_int = 2) then
if (position_slv(1 downto 0) = "01") then
return data_slv (31 downto 16);
elsif (position_slv(1 downto 0) = "10") then
return data_slv (31-8 downto 16-8);
else
return data_slv (31 downto 16);
end if;
elsif(bytes_int = 4) then
if (position_slv(3 downto 0) = "0001") then
return data_slv(63 downto 32);
elsif (position_slv(3 downto 0) = "0010") then
return data_slv(63-1*8 downto 32-1*8);
elsif (position_slv(3 downto 0) = "0100") then
return data_slv(63-2*8 downto 32-2*8);
elsif (position_slv(3 downto 0) = "1000") then
return data_slv(63-3*8 downto 32-3*8);
else
return data_slv(63 downto 32);
end if;
else
return data_slv;
end if;
end JesdDataAlign;
-- Align the char within the buffer according to the position of the byte alignment word
function JesdCharAlign(char_slv : slv; position_slv : slv; bytes_int : positive) return std_logic_vector is
begin
if(bytes_int = 2) then
if (position_slv(1 downto 0) = "01") then
return char_slv (3 downto 2);
elsif (position_slv(1 downto 0) = "10") then
return char_slv (3-1 downto 2-1);
else
return char_slv (3 downto 2);
end if;
elsif(bytes_int = 4) then
if (position_slv(3 downto 0) = "0001") then
return char_slv(7 downto 4);
elsif (position_slv(3 downto 0) = "0010") then
return char_slv(7-1 downto 4-1);
elsif (position_slv(3 downto 0) = "0100") then
return char_slv(7-2 downto 4-2);
elsif (position_slv(3 downto 0) = "1000") then
return char_slv(7-3 downto 4-3);
else
return char_slv(7 downto 4);
end if;
else
return char_slv;
end if;
end JesdCharAlign;
-- Convert standard logic vector to integer
function slvToInt(data_slv : slv) return integer is
begin
return to_integer(unsigned(data_slv));
end slvToInt;
-- Convert integer to standard logic vector
function intToSlv(data_int : integer; bytes_int : positive) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(data_int, bytes_int));
end IntToSlv;
-- Output zero sample data depending on word size and Frame size
function outSampleZero(F_int : positive; bytes_int : positive) return std_logic_vector is
constant SAMPLES_IN_WORD_C : positive := (bytes_int/F_int);
variable vSlv : slv((bytes_int*8)-1 downto 0);
begin
vSlv := (others => '0');
for i in (SAMPLES_IN_WORD_C-1) downto 0 loop
vSlv(i*8*F_int+8*F_int-1) := '1';
end loop;
return vSlv;
end outSampleZero;
-- Invert Signed
function invSigned(input : slv) return std_logic_vector is
variable vOutput : signed(input'range);
begin
vOutput := - signed(input);
return std_logic_vector(vOutput);
end invSigned;
-- Output zero sample data depending on word size and Frame size
function invData(data : slv; F_int : positive; bytes_int : positive) return std_logic_vector is
constant SAMPLES_IN_WORD_C : positive := (bytes_int/F_int);
variable vSlv : slv((bytes_int*8)-1 downto 0);
begin
vSlv := data;
for i in (SAMPLES_IN_WORD_C-1) downto 0 loop
vSlv(i*8*F_int+8*F_int-1 downto i*8*F_int) := invSigned(vSlv(i*8*F_int+8*F_int-1 downto i*8*F_int));
end loop;
return vSlv;
end invData;
-- lfsr(14:0)=1+x^14+x^15
procedure jesdScrambler (
dataIn : in slv(15 downto 0);
lfsrIn : in slv(14 downto 0);
dataOut : inout slv(15 downto 0);
lfsrOut : inout slv(14 downto 0)) is
begin
lfsrOut(0) := lfsrIn(0) xor lfsrIn(1) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13);
lfsrOut(1) := lfsrIn(0) xor lfsrIn(1) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(2) := lfsrIn(1) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(3) := lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(4) := lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(5) := lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(6) := lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(7) := lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(8) := lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(9) := lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(10) := lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(11) := lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(12) := lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(13) := lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
lfsrOut(14) := lfsrIn(0) xor lfsrIn(1) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(14);
dataOut(0) := dataIn(0) xor lfsrIn(14);
dataOut(1) := dataIn(1) xor lfsrIn(13) xor lfsrIn(14);
dataOut(2) := dataIn(2) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(3) := dataIn(3) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(4) := dataIn(4) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(5) := dataIn(5) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(6) := dataIn(6) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(7) := dataIn(7) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(8) := dataIn(8) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(9) := dataIn(9) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(10) := dataIn(10) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(11) := dataIn(11) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(12) := dataIn(12) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(13) := dataIn(13) xor lfsrIn(1) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(14) := dataIn(14) xor lfsrIn(0) xor lfsrIn(1) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13) xor lfsrIn(14);
dataOut(15) := dataIn(15) xor lfsrIn(0) xor lfsrIn(1) xor lfsrIn(2) xor lfsrIn(3) xor lfsrIn(4) xor lfsrIn(5) xor lfsrIn(6) xor lfsrIn(7) xor lfsrIn(8) xor lfsrIn(9) xor lfsrIn(10) xor lfsrIn(11) xor lfsrIn(12) xor lfsrIn(13);
end procedure;
end package body Jesd204bPkg;
|
<gh_stars>1-10
------------------------------------------------------------------------------------------------
-- WWW.DEADLINE-DESIGN.COM --
------------------------------------------------------------------------------------------------
-- --
-- This software representation and its inclusive documentation are provided AS-IS and with --
-- all faults; is without warranty expressed or implied, including but not limited to, --
-- warranties of merchantability or fitness for a particular purpose. --
-- --
-- All trademarks are the property of their respective owners. --
-- --
-- DESIGN UNITS : pre_scaler_srle_based(dynamic) --
-- --
-- FILE NAME : pre_scaler_srle_based.vhd --
-- --
-- PURPOSE : The purpose of this design unit is to provide a minimal footprint yet --
-- somewhat flexible multi-use clock enable tick based clock pre-scaler. --
-- Every attempt is made at inferring functionality as opposed to --
-- instantiating functionality to permit easier portability. --
-- --
-- NOTE : This design unit utilizes the LUT based shift register primitive where --
-- possible for a more efficient footprint. The primitive can be found in --
-- various Xilinx FPGA families. --
-- --
-- This design unit does utilize certain elements contained within the --
-- D_D_pkg PACKAGE (D_D_pkg.vhd). Be sure to compile the package into the --
-- DEADLINE LIBRARY prior to compiling this design unit into the DEADLINE --
-- LIBRARY. --
-- --
-- This design unit does utilize the srle(dynamic) primitive (srle.vhd). --
-- Be sure to compile the primitive into the DEADLINE LIBRARY prior to --
-- compiling this design unit into the DEADLINE LIBRARY. --
-- --
-- GENERIC DECLARATIONS --
-- --
-- PRE_SCALE_SRL_DEPTH - Pre-scale divider LUT based SRL depth. --
-- Ideally this should be 16 or 32 to permit single --
-- primitive instantion. However a multiple of 16 --
-- that is greater than 32 is possible. --
-- --
-- PORT DECLARATIONS --
-- --
-- i_clock - Global clock input. --
-- --
-- i_enable - Pre-scaler module enable input. --
-- --
-- i_pre_scale_div - Pre-scale divide clock enable tick rate input. --
-- The divide rate is i_pre_scale_div + 1. --
-- It may be set statically, or can be dynamic --
-- (so long as it is properly flushed prior to the --
-- dynamic change. --
-- --
-- o_pre_scale_rate_tick - Pre-scale divided clock enable tick output. --
-- --
-- LIMITATIONS : The SRL LUT shift register is permanently clock enabled. This permits a --
-- simpler meachanism for flushing when the pre-scaler module is disabled. --
-- --
-- In order to properly flush the SRL based shift registers, i_enable must --
-- be de-asserted for no less thant pre_scale_srl_depth + 1 clock cycles. --
-- --
-- If i_pre_scale_div is utilized(adjusted) dynamically, be sure to first --
-- flush the SRL LUT shift register using i_enable, prior to making the --
-- change and re-asserting i_enable. --
-- --
-- Ensure that the PRE_SCALE_SRL_DEPTH GENERIC value is a multiple of 16 so --
-- that it is compatible with SRL LUT based shift register depths. --
-- --
-- ERRORS : No known errors. --
-- --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- MODULE HISTORY --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- --
-- VERSION AUTHOR DATE COMMENTS --
-- 0.0 D-D 30 Jan 22 - Created. --
-- --
-- D-D 01 Feb 22 - Incorporated revised srle(dynamic) COMPONENT. --
-- --
-- D-D 04 Feb 22 - Changed PRE_SCALE_SRL_INIT GENERIC to a local CONSTANT. --
-- --
-- D-D 08 Feb 22 - Corrected typo in titleblock. --
-- --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- LIBRARY UTILIZATION(S) --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY DEADLINE;
USE DEADLINE.ALL;
USE DEADLINE.D_D_pkg.ALL;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- ENTITY and ARCHITECTURE(S) --
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
ENTITY pre_scaler_srle_based IS
GENERIC (
PRE_SCALE_SRL_DEPTH : INTEGER := 16
);
PORT (
i_clock : IN STD_LOGIC;
i_enable : IN STD_LOGIC;
i_pre_scale_div : IN STD_LOGIC_VECTOR((find_bit_width(PRE_SCALE_SRL_DEPTH-1)-1) DOWNTO 0);
o_pre_scale_rate_tick : OUT STD_LOGIC
);
END pre_scaler_srle_based;
ARCHITECTURE dynamic OF pre_scaler_srle_based IS
------------------------------
-- COMPONENT DECLARATION(S) --
------------------------------
COMPONENT srle IS
GENERIC (
CLOCK_POL_RISING : BOOLEAN := TRUE;
SRLDEPTH : INTEGER := 16;
SRLTYPE : STRING := "srl";
SRLINIT : STRING := "0000"
);
PORT (
i_clock : IN STD_LOGIC;
i_clock_enable : IN STD_LOGIC;
i_tap_sel : IN STD_LOGIC_VECTOR((find_bit_width(SRLDEPTH-1)-1) DOWNTO 0);
i_data : IN STD_LOGIC;
o_data : OUT STD_LOGIC
);
END COMPONENT;
---------------
-- CONSTANTS --
---------------
CONSTANT PRE_SCALE_SRL_INIT : STRING := SRLEn_gen_hex_INIT_string('0',PRE_SCALE_SRL_DEPTH);
-------------
-- SIGNALS --
-------------
SIGNAL enable_dly : STD_LOGIC; -- Pre-scaler enable delay
SIGNAL srl_pre_scale : STD_LOGIC; -- Pre-scaler SRL output
SIGNAL srl_pre_scale_token : STD_LOGIC; -- Pre-scaler SRL input token
----------------
-- ATTRIBUTES --
----------------
BEGIN
------------------------------------------------------------------------------------------------
-- PRE-SCALER RATE GENERATION --
------------------------------------------------------------------------------------------------
-- --
-- i_enable when de-asserted should be de-asserted for a minimum of clocks equal to the --
-- pre_scale_srl_depth + 1 to ensure proper flushing. When asserted, the pre-scaler is active --
-- and output clock enable ticks are generated at the divide rate of the input clock. --
-- --
-- i_pre_scale_div is the clock divider value. Specifically the divider rate is equal to --
-- i_pre_scale_div + 1. If i_pre_scale_div is to be utilized dynamically, it is important to --
-- flush the SRL based shift register prior to making any change to the divider value. --
-- i_enable should be de-asserted long enough to flush the SRL based shift register, then --
-- i_pre_scale_div may be changed, followed by re-asserting i_enable to commence generation of--
-- the pre-scaler rate tick/pulses at the new divider value rate. --
-- --
-- srl_pre_scale_token is a simple gate which permits the SRL based shift register to be --
-- flushed when the pre-scaler is disabled and also permits it to be loaded with a single --
-- initial '1' pulse when i_enable transitions from de-asserted to asserted. --
-- --
-- o_pre_scale_rate_tick is a simple single clock wide pulse (or tick) with a rate at the --
-- pre-scaler divide rate as set by i_pre_scale_div. De-assertion of i_enable is utilized to --
-- synchronously put o_pre_scale_rate_tick in the inactive reset state and thereby stop --
-- output/generation of pre-scaler rate tick/pulses. --
-- --
------------------------------------------------------------------------------------------------
---------------------------------
-- PRE-SCALER RATE TICK OUTPUT --
---------------------------------
PRESCALEOUT: PROCESS(i_clock)
BEGIN
IF RISING_EDGE(i_clock)
THEN IF (i_enable = '0')
THEN o_pre_scale_rate_tick <= '0';
ELSE o_pre_scale_rate_tick <= srl_pre_scale;
END IF;
END IF;
END PROCESS;
--------------------------------------------------------
-- ONE CLOCK ENABLE DELAY FOR DEASSERT EDGE DETECTION --
--------------------------------------------------------
PRESCALEENADLY: PROCESS(i_clock)
BEGIN
IF RISING_EDGE(i_clock)
THEN enable_dly <= i_enable;
END IF;
END PROCESS;
-----------------------------------
-- PRE-SCALE DIVIDER INPUT TOKEN --
-----------------------------------
PRESCALETOKEN: srl_pre_scale_token <= ((srl_pre_scale AND enable_dly) OR -- Normal loopback
(i_enable AND NOT(enable_dly))); -- Initial token
------------------------------------------------
-- PRE-SCALE DIVIDER SRL BASED SHIFT REGISTER --
------------------------------------------------
PRESCALEGEN: srle GENERIC MAP (
CLOCK_POL_RISING => TRUE,
SRLDEPTH => PRE_SCALE_SRL_DEPTH,
SRLTYPE => "srl",
SRLINIT => PRE_SCALE_SRL_INIT
)
PORT MAP (
i_clock => i_clock,
i_clock_enable => '1',
i_tap_sel => i_pre_scale_div,
i_data => srl_pre_scale_token,
o_data => srl_pre_scale
);
END dynamic;
-------------------------------------------- END OF CODE ---------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.pkg.all;
entity RISCV is
port
(
CLK : in std_logic;
PC : in std_logic_vector (3 downto 0);
Instruction : out std_logic_vector(31 downto 0);
ALU_Result : out std_logic_vector (31 downto 0)
);
end entity RISCV;
architecture test of RISCV is
signal PC_Sync : std_logic_vector (3 downto 0);
signal Aux_Instruction : std_logic_vector (31 downto 0);
signal Aux_ALU_Result : std_logic_vector (31 downto 0);
signal WE_REG : std_logic := '0';
signal RD_1, RD_2 : std_logic_vector (31 downto 0);
signal read_validity : std_logic;
begin
-- FF at the entry
input_reg : process(CLK)
begin
if (rising_edge(CLK)) then
PC_Sync <= PC;
end if;
end process input_reg;
Ins_Mem : Instruction_Memory
port map (PC_Sync, Aux_Instruction);
RISCV_Reg : RISCV_Register_file
generic map
(
N => 32,
N_cod => 5
)
port map
(
CLK => CLK, -- : in std_logic;
we => WE_REG, -- : in std_logic; // we = Write enable
rs1 => Aux_Instruction (19 downto 15), -- : in std_logic_vector(n_cod-1 downto 0); // rs = Read Selection
rs2 => Aux_Instruction (24 downto 20), -- : in std_logic_vector(n_cod-1 downto 0); // rs = Read Selection
ws => Aux_Instruction (11 downto 7), -- : in std_logic_vector(n_cod-1 downto 0); // ws = Write Selection
wd => Aux_ALU_Result, -- : in std_logic_vector(n-1 downto 0); // wd = Write Data
rd1 => RD_1, -- : out std_logic_vector(n-1 downto 0) // rd = Read Data
rd2 => RD_2,
read_validity => read_validity);
Instruction <= Aux_Instruction;
ALU_Result <= (others => '0');
end test;
|
-- AVALON MM-slave wrapper around the core gcd IP
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.misc_gcd.all;
entity avs_gcd is
port (avs_s0_address : in std_logic_vector(3 downto 0) := (others => '0');
-- 0000 : control/status register (b1=start, b0=rdy)
-- 0001 : a register
-- 0010 : b register
-- 0011 : params_0031acc register
-- 0100 : params_0031n register
-- 0101 : result register
avs_s0_read : in std_logic := '0';
avs_s0_readdata : out std_logic_vector(31 downto 0);
avs_s0_write : in std_logic := '0';
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0');
clock_clk : in std_logic := '0';
reset_reset : in std_logic := '0');
end entity;
architecture rtl of avs_gcd is
component gcd is
port (signal clk : in std_logic;
signal reset : in std_logic;
signal start : in std_logic;
signal rdy : out std_logic;
signal a: in caml_int;
signal b: in caml_int;
signal params_0031acc: out caml_int;
signal params_0031n: out caml_int;
signal result: out caml_int);
end component;
signal a: caml_int;
signal b: caml_int;
signal params_0031acc: caml_int;
signal params_0031n: caml_int;
signal result: caml_int;
signal start: std_logic;
signal rdy: std_logic;type write_state_t is (Idle, StartAsserted);
signal write_state: write_state_t;
begin
gcd_CC : component gcd
port map (clk => clock_clk,
reset => reset_reset,
start => start,
rdy => rdy,
a => a,
b => b,
params_0031acc => params_0031acc,
params_0031n => params_0031n,
result => result);
WRITE: process (clock_clk, reset_reset)
begin
if reset_reset = '1' then
write_state <= Idle;
elsif rising_edge(clock_clk) then
case write_state is
when StartAsserted =>
start <= '0';
write_state <= Idle;
when Idle =>
if avs_s0_write = '1' then
case avs_s0_address is
when "0000" => -- writing CSR asserts start for one clock period
start <= '1';
write_state <= StartAsserted;
when "0001" => a <= signed(avs_s0_writedata(30 downto 0));
when "0010" => b <= signed(avs_s0_writedata(30 downto 0));
when others => NULL;
end case;
end if;
end case;
end if;
end process;
READ: process (clock_clk)
begin
if rising_edge(clock_clk) then
if avs_s0_read = '1' then
case avs_s0_address is
when "0000" => avs_s0_readdata <= X"0000000" & "000" & rdy;
-- when reading CSR, bit 0 is rdy
when "0001" => avs_s0_readdata <= "0" & std_logic_vector(a);
when "0010" => avs_s0_readdata <= "0" & std_logic_vector(b);
when "0011" => avs_s0_readdata <= "0" & std_logic_vector(params_0031acc);
when "0100" => avs_s0_readdata <= "0" & std_logic_vector(params_0031n);
when "0101" => avs_s0_readdata <= "0" & std_logic_vector(result);
when others => null;
end case;
end if;
end if;
end process;
end architecture;
|
<reponame>mkotormus/G3_OrchestraConductorDemo<filename>src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_logic_pkt_fifo.vhd
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`protect end_protected
|
<reponame>datacipy/VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity barrel is
Port (
A : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0)
);
end entity;
architecture mmux of Barrel is
component mux is
port ( sel : in STD_LOGIC;
in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
y: out STD_LOGIC
);
end component;
signal I1: STD_LOGIC_VECTOR (7 downto 0);
signal I2: STD_LOGIC_VECTOR (7 downto 0);
begin
m1: entity work.mux port map (S(0),A(0),'0',I1(0));
mux1_loop: for i in 1 to 7 generate
mux_L1: entity work.mux port map (S(0),A(i),A(i-1),I1(i));
end generate;
m2a: entity work.mux port map (S(1),I1(0),'0',I2(0));
m2b: entity work.mux port map (S(1),I1(1),'0',I2(1));
mux2_loop: for i in 2 to 7 generate
mux_L2: entity work.mux port map (S(1),I1(i),I1(i-2),I2(i));
end generate;
mux3_loop1: for i in 0 to 3 generate
mux_L3a: entity work.mux port map (S(2),I2(i),'0',Q(i));
end generate;
mux3_loop2: for i in 4 to 7 generate
mux_L3b: entity work.mux port map (S(2),I2(i),I2(i-4),Q(i));
end generate;
end architecture;
architecture mux8r of barrel is
begin
mux0: entity work.mux8w port map (S,A(0),A(1),A(2),A(3),A(4),A(5),A(6),A(7),Q(0));
mux1: entity work.mux8w port map (S,A(1),A(2),A(3),A(4),A(5),A(6),A(7),'0',Q(1));
mux2: entity work.mux8w port map (S,A(2),A(3),A(4),A(5),A(6),A(7),'0','0',Q(2));
mux3: entity work.mux8w port map (S,A(3),A(4),A(5),A(6),A(7),'0','0','0',Q(3));
mux4: entity work.mux8w port map (S,A(4),A(5),A(6),A(7),'0','0','0','0',Q(4));
mux5: entity work.mux8w port map (S,A(5),A(6),A(7),'0','0','0','0','0',Q(5));
mux6: entity work.mux8w port map (S,A(6),A(7),'0','0','0','0','0','0',Q(6));
mux7: entity work.mux8w port map (S,A(7),'0','0','0','0','0','0','0',Q(7));
end architecture;
architecture mux8L of barrel is
begin
mux0: entity work.mux8w port map (S,A(0),'0','0','0','0','0','0','0',Q(0));
mux1: entity work.mux8w port map (S,A(1),A(0),'0','0','0','0','0','0',Q(1));
mux2: entity work.mux8w port map (S,A(2),A(1),A(0),'0','0','0','0','0',Q(2));
mux3: entity work.mux8w port map (S,A(3),A(2),A(1),A(0),'0','0','0','0',Q(3));
mux4: entity work.mux8w port map (S,A(4),A(3),A(2),A(1),A(0),'0','0','0',Q(4));
mux5: entity work.mux8w port map (S,A(5),A(4),A(3),A(2),A(1),A(0),'0','0',Q(5));
mux6: entity work.mux8w port map (S,A(6),A(5),A(4),A(3),A(2),A(1),A(0),'0',Q(6));
mux7: entity work.mux8w port map (S,A(7),A(6),A(5),A(4),A(3),A(2),A(1),A(0),Q(7));
end architecture;
|
<filename>example/RISCV_OLD/RTL/Memory_tb.vhd
--
-- Created by deutschmann on 13.02.18
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.SCAM_Model_types.all;
entity Memory_tb is
end entity Memory_tb;
architecture sim of Memory_tb is
component Memory is
port (
clk : in std_logic;
rst : in std_logic;
CtlToMem_port : in MemoryAccess;
CtlToMem_port_sync : in bool;
CtlToMem_port_notify : out bool;
MemToCtl_port : out Unsigned (31 downto 0);
MemToCtl_port_sync : in bool;
MemToCtl_port_notify : out bool;
MemToDec_port : out Unsigned (31 downto 0);
MemToDec_port_sync : in bool;
MemToDec_port_notify : out bool
);
end component;
-- Input
signal clk : std_logic := '0';
signal rst : std_logic;
signal CtlToMem_port : MemoryAccess;
signal CtlToMem_port_sync : bool;
signal MemToCtl_port_sync : bool;
signal MemToDec_port_sync : bool;
-- Output
signal MemToCtl_port : Unsigned (31 downto 0);
signal MemToDec_port : Unsigned (31 downto 0);
signal CtlToMem_port_notify : bool;
signal MemToCtl_port_notify : bool;
signal MemToDec_port_notify : bool;
begin
-- Clock
clk <= not clk after 10 ns;
-- Reset
rst <= '1', '0' after 20 ns;
dut: Memory
port map (
clk => clk,
rst => rst,
CtlToMem_port => CtlToMem_port,
CtlToMem_port_sync => CtlToMem_port_sync,
CtlToMem_port_notify => CtlToMem_port_notify,
MemToCtl_port => MemToCtl_port,
MemToCtl_port_sync => MemToCtl_port_sync,
MemToCtl_port_notify => MemToCtl_port_notify,
MemToDec_port => MemToDec_port,
MemToDec_port_sync => MemToDec_port_sync,
MemToDec_port_notify => MemToDec_port_notify
);
stimuli: process
begin
-- Write X"CD" at Address 244 (Byte)
wait for 20 ns;
wait for 5 ns;
CtlToMem_port.addrIn <= to_unsigned(244, 32);
CtlToMem_port.dataIn <= X"67890BCD";
CtlToMem_port.mask <= MT_B;
CtlToMem_port.req <= MEM_STORE;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
wait for 20 ns;
-- Write X"0BCD" at Address 248 (Halfword)
CtlToMem_port.addrIn <= to_unsigned(248, 32);
CtlToMem_port.dataIn <= X"67890BCD";
CtlToMem_port.mask <= MT_H;
CtlToMem_port.req <= MEM_STORE;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
wait for 20 ns;
-- Write X"67890BCD" at Address 252 (Word)
CtlToMem_port.addrIn <= to_unsigned(252, 32);
CtlToMem_port.dataIn <= X"67890BCD";
CtlToMem_port.mask <= MT_W;
CtlToMem_port.req <= MEM_STORE;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
wait for 20 ns;
-- Load Content at Address 244
CtlToMem_port.addrIn <= to_unsigned(244, 32);
CtlToMem_port.dataIn <= X"00000000";
CtlToMem_port.mask <= MT_W;
CtlToMem_port.req <= MEM_LOAD;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
assert MemToCtl_port = X"000000CD" report "unexpected value for MemToCtl_port" severity warning;
assert MemToCtl_port_notify = true report "unexpected value for MemToCtl_port_notify" severity warning;
MemToCtl_port_sync <= true;
wait for 20 ns;
MemToCtl_port_sync <= false;
-- Load Content at Address 248
CtlToMem_port.addrIn <= to_unsigned(248, 32);
CtlToMem_port.dataIn <= X"00000000";
CtlToMem_port.mask <= MT_W;
CtlToMem_port.req <= MEM_LOAD;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
assert MemToCtl_port = X"00000BCD" report "unexpected value for MemToCtl_port" severity warning;
assert MemToCtl_port_notify = true report "unexpected value for MemToCtl_port_notify" severity warning;
MemToCtl_port_sync <= true;
wait for 20 ns;
MemToCtl_port_sync <= false;
-- Load Content at Address 252 as Byte
CtlToMem_port.addrIn <= to_unsigned(252, 32);
CtlToMem_port.dataIn <= X"00000000";
CtlToMem_port.mask <= MT_B;
CtlToMem_port.req <= MEM_LOAD;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
assert MemToCtl_port = X"FFFFFFCD" report "unexpected value for MemToCtl_port" severity warning;
assert MemToCtl_port_notify = true report "unexpected value for MemToCtl_port_notify" severity warning;
MemToCtl_port_sync <= true;
wait for 20 ns;
MemToCtl_port_sync <= false;
-- Load Content at Address 252 as Halfword
CtlToMem_port.addrIn <= to_unsigned(252, 32);
CtlToMem_port.dataIn <= X"00000000";
CtlToMem_port.mask <= MT_H;
CtlToMem_port.req <= MEM_LOAD;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
assert MemToCtl_port = X"00000BCD" report "unexpected value for MemToCtl_port" severity warning;
assert MemToCtl_port_notify = true report "unexpected value for MemToCtl_port_notify" severity warning;
MemToCtl_port_sync <= true;
wait for 20 ns;
MemToCtl_port_sync <= false;
-- Load Content at Address 252 as Word
CtlToMem_port.addrIn <= to_unsigned(252, 32);
CtlToMem_port.dataIn <= X"00000000";
CtlToMem_port.mask <= MT_W;
CtlToMem_port.req <= MEM_LOAD;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
assert MemToCtl_port = X"67890BCD" report "unexpected value for MemToCtl_port" severity warning;
assert MemToCtl_port_notify = true report "unexpected value for MemToCtl_port_notify" severity warning;
MemToCtl_port_sync <= true;
wait for 20 ns;
MemToCtl_port_sync <= false;
-- Read Instruction at Address 252
CtlToMem_port.addrIn <= to_unsigned(252, 32);
CtlToMem_port.dataIn <= X"00000000";
CtlToMem_port.mask <= MT_W;
CtlToMem_port.req <= MEM_RD_I;
CtlToMem_port_sync <= true;
wait for 20 ns;
CtlToMem_port_sync <= false;
assert MemToDec_port = X"67890BCD" report "unexpected value for MemToDec_port" severity warning;
assert MemToDec_port_notify = true report "unexpected value for MemToDec_port_notify" severity warning;
MemToDec_port_sync <= true;
wait for 20 ns;
MemToDec_port_sync <= false;
wait;
end process stimuli;
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:45:31 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_sim_netlist.vhdl
-- Design : system_auto_cc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_dmem is
port (
dout_i : out STD_LOGIC_VECTOR ( 57 downto 0 );
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_dmem : entity is "dmem";
end system_auto_cc_0_dmem;
architecture STRUCTURE of system_auto_cc_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_57 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(1 downto 0),
DIB(1 downto 0) => DI(3 downto 2),
DIC(1 downto 0) => DI(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(13 downto 12),
DIB(1 downto 0) => DI(15 downto 14),
DIC(1 downto 0) => DI(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(19 downto 18),
DIB(1 downto 0) => DI(21 downto 20),
DIC(1 downto 0) => DI(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(25 downto 24),
DIB(1 downto 0) => DI(27 downto 26),
DIC(1 downto 0) => DI(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(31 downto 30),
DIB(1 downto 0) => DI(33 downto 32),
DIC(1 downto 0) => DI(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(37 downto 36),
DIB(1 downto 0) => DI(39 downto 38),
DIC(1 downto 0) => DI(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(43 downto 42),
DIB(1 downto 0) => DI(45 downto 44),
DIC(1 downto 0) => DI(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(49 downto 48),
DIB(1 downto 0) => DI(51 downto 50),
DIC(1 downto 0) => DI(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_54_57: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(55 downto 54),
DIB(1 downto 0) => DI(57 downto 56),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_57_n_0,
DOA(0) => RAM_reg_0_15_54_57_n_1,
DOB(1) => RAM_reg_0_15_54_57_n_2,
DOB(0) => RAM_reg_0_15_54_57_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(7 downto 6),
DIB(1 downto 0) => DI(9 downto 8),
DIC(1 downto 0) => DI(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => dout_i(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => dout_i(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => dout_i(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => dout_i(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => dout_i(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => dout_i(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => dout_i(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => dout_i(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => dout_i(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => dout_i(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => dout_i(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => dout_i(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => dout_i(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => dout_i(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => dout_i(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => dout_i(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => dout_i(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => dout_i(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => dout_i(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => dout_i(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => dout_i(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => dout_i(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => dout_i(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => dout_i(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => dout_i(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => dout_i(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => dout_i(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => dout_i(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => dout_i(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => dout_i(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => dout_i(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => dout_i(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => dout_i(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => dout_i(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => dout_i(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => dout_i(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => dout_i(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => dout_i(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => dout_i(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => dout_i(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => dout_i(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => dout_i(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => dout_i(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => dout_i(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => dout_i(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_1,
Q => dout_i(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_0,
Q => dout_i(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_3,
Q => dout_i(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_2,
Q => dout_i(57),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => dout_i(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => dout_i(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => dout_i(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => dout_i(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => dout_i(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_dmem_81 is
port (
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_dmem_81 : entity is "dmem";
end system_auto_cc_0_dmem_81;
architecture STRUCTURE of system_auto_cc_0_dmem_81 is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_57 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(1 downto 0),
DIB(1 downto 0) => I123(3 downto 2),
DIC(1 downto 0) => I123(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(13 downto 12),
DIB(1 downto 0) => I123(15 downto 14),
DIC(1 downto 0) => I123(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(19 downto 18),
DIB(1 downto 0) => I123(21 downto 20),
DIC(1 downto 0) => I123(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(25 downto 24),
DIB(1 downto 0) => I123(27 downto 26),
DIC(1 downto 0) => I123(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(31 downto 30),
DIB(1 downto 0) => I123(33 downto 32),
DIC(1 downto 0) => I123(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(37 downto 36),
DIB(1 downto 0) => I123(39 downto 38),
DIC(1 downto 0) => I123(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(43 downto 42),
DIB(1 downto 0) => I123(45 downto 44),
DIC(1 downto 0) => I123(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(49 downto 48),
DIB(1 downto 0) => I123(51 downto 50),
DIC(1 downto 0) => I123(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_54_57: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(55 downto 54),
DIB(1 downto 0) => I123(57 downto 56),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_57_n_0,
DOA(0) => RAM_reg_0_15_54_57_n_1,
DOB(1) => RAM_reg_0_15_54_57_n_2,
DOB(0) => RAM_reg_0_15_54_57_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(7 downto 6),
DIB(1 downto 0) => I123(9 downto 8),
DIC(1 downto 0) => I123(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_dmem__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 144 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_dmem__parameterized0\ : entity is "dmem";
end \system_auto_cc_0_dmem__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_dmem__parameterized0\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_0 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_1 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_2 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_3 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_4 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_5 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_0 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_1 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_2 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_3 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_4 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_5 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_0 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_1 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_2 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_3 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_4 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_5 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_0 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_1 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_2 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_3 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_4 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_5 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_0 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_1 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_2 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_3 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_4 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_0 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_1 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_2 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_3 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_4 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_5 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_0 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_1 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_2 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_3 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_4 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_5 : STD_LOGIC;
signal RAM_reg_0_15_144_144_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_4 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_5 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_0 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_1 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_2 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_3 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_4 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_0 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_1 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_2 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_3 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_4 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_5 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_0 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_1 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_2 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_3 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_4 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_5 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_0 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_1 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_2 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_3 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_4 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_5 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_0 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_1 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_2 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_3 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_4 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_5 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_0 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_1 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_2 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_3 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_4 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_102_107 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_108_113 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_114_119 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_120_125 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_126_131 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_132_137 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_138_143 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_144_144 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_65 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_66_71 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_72_77 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_78_83 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_84_89 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_90_95 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_96_101 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(1 downto 0),
DIB(1 downto 0) => I115(3 downto 2),
DIC(1 downto 0) => I115(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_102_107: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(103 downto 102),
DIB(1 downto 0) => I115(105 downto 104),
DIC(1 downto 0) => I115(107 downto 106),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_102_107_n_0,
DOA(0) => RAM_reg_0_15_102_107_n_1,
DOB(1) => RAM_reg_0_15_102_107_n_2,
DOB(0) => RAM_reg_0_15_102_107_n_3,
DOC(1) => RAM_reg_0_15_102_107_n_4,
DOC(0) => RAM_reg_0_15_102_107_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_108_113: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(109 downto 108),
DIB(1 downto 0) => I115(111 downto 110),
DIC(1 downto 0) => I115(113 downto 112),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_108_113_n_0,
DOA(0) => RAM_reg_0_15_108_113_n_1,
DOB(1) => RAM_reg_0_15_108_113_n_2,
DOB(0) => RAM_reg_0_15_108_113_n_3,
DOC(1) => RAM_reg_0_15_108_113_n_4,
DOC(0) => RAM_reg_0_15_108_113_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_114_119: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(115 downto 114),
DIB(1 downto 0) => I115(117 downto 116),
DIC(1 downto 0) => I115(119 downto 118),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_114_119_n_0,
DOA(0) => RAM_reg_0_15_114_119_n_1,
DOB(1) => RAM_reg_0_15_114_119_n_2,
DOB(0) => RAM_reg_0_15_114_119_n_3,
DOC(1) => RAM_reg_0_15_114_119_n_4,
DOC(0) => RAM_reg_0_15_114_119_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_120_125: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(121 downto 120),
DIB(1 downto 0) => I115(123 downto 122),
DIC(1 downto 0) => I115(125 downto 124),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_120_125_n_0,
DOA(0) => RAM_reg_0_15_120_125_n_1,
DOB(1) => RAM_reg_0_15_120_125_n_2,
DOB(0) => RAM_reg_0_15_120_125_n_3,
DOC(1) => RAM_reg_0_15_120_125_n_4,
DOC(0) => RAM_reg_0_15_120_125_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_126_131: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(127 downto 126),
DIB(1 downto 0) => I115(129 downto 128),
DIC(1 downto 0) => I115(131 downto 130),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_126_131_n_0,
DOA(0) => RAM_reg_0_15_126_131_n_1,
DOB(1) => RAM_reg_0_15_126_131_n_2,
DOB(0) => RAM_reg_0_15_126_131_n_3,
DOC(1) => RAM_reg_0_15_126_131_n_4,
DOC(0) => RAM_reg_0_15_126_131_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(13 downto 12),
DIB(1 downto 0) => I115(15 downto 14),
DIC(1 downto 0) => I115(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_132_137: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(133 downto 132),
DIB(1 downto 0) => I115(135 downto 134),
DIC(1 downto 0) => I115(137 downto 136),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_132_137_n_0,
DOA(0) => RAM_reg_0_15_132_137_n_1,
DOB(1) => RAM_reg_0_15_132_137_n_2,
DOB(0) => RAM_reg_0_15_132_137_n_3,
DOC(1) => RAM_reg_0_15_132_137_n_4,
DOC(0) => RAM_reg_0_15_132_137_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_138_143: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(139 downto 138),
DIB(1 downto 0) => I115(141 downto 140),
DIC(1 downto 0) => I115(143 downto 142),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_138_143_n_0,
DOA(0) => RAM_reg_0_15_138_143_n_1,
DOB(1) => RAM_reg_0_15_138_143_n_2,
DOB(0) => RAM_reg_0_15_138_143_n_3,
DOC(1) => RAM_reg_0_15_138_143_n_4,
DOC(0) => RAM_reg_0_15_138_143_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_144_144: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1) => '0',
DIA(0) => I115(144),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED(1),
DOA(0) => RAM_reg_0_15_144_144_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(19 downto 18),
DIB(1 downto 0) => I115(21 downto 20),
DIC(1 downto 0) => I115(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(25 downto 24),
DIB(1 downto 0) => I115(27 downto 26),
DIC(1 downto 0) => I115(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(31 downto 30),
DIB(1 downto 0) => I115(33 downto 32),
DIC(1 downto 0) => I115(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(37 downto 36),
DIB(1 downto 0) => I115(39 downto 38),
DIC(1 downto 0) => I115(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(43 downto 42),
DIB(1 downto 0) => I115(45 downto 44),
DIC(1 downto 0) => I115(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(49 downto 48),
DIB(1 downto 0) => I115(51 downto 50),
DIC(1 downto 0) => I115(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(55 downto 54),
DIB(1 downto 0) => I115(57 downto 56),
DIC(1 downto 0) => I115(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(61 downto 60),
DIB(1 downto 0) => I115(63 downto 62),
DIC(1 downto 0) => I115(65 downto 64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_65_n_0,
DOA(0) => RAM_reg_0_15_60_65_n_1,
DOB(1) => RAM_reg_0_15_60_65_n_2,
DOB(0) => RAM_reg_0_15_60_65_n_3,
DOC(1) => RAM_reg_0_15_60_65_n_4,
DOC(0) => RAM_reg_0_15_60_65_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(67 downto 66),
DIB(1 downto 0) => I115(69 downto 68),
DIC(1 downto 0) => I115(71 downto 70),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_66_71_n_0,
DOA(0) => RAM_reg_0_15_66_71_n_1,
DOB(1) => RAM_reg_0_15_66_71_n_2,
DOB(0) => RAM_reg_0_15_66_71_n_3,
DOC(1) => RAM_reg_0_15_66_71_n_4,
DOC(0) => RAM_reg_0_15_66_71_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(7 downto 6),
DIB(1 downto 0) => I115(9 downto 8),
DIC(1 downto 0) => I115(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(73 downto 72),
DIB(1 downto 0) => I115(75 downto 74),
DIC(1 downto 0) => I115(77 downto 76),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_72_77_n_0,
DOA(0) => RAM_reg_0_15_72_77_n_1,
DOB(1) => RAM_reg_0_15_72_77_n_2,
DOB(0) => RAM_reg_0_15_72_77_n_3,
DOC(1) => RAM_reg_0_15_72_77_n_4,
DOC(0) => RAM_reg_0_15_72_77_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(79 downto 78),
DIB(1 downto 0) => I115(81 downto 80),
DIC(1 downto 0) => I115(83 downto 82),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_78_83_n_0,
DOA(0) => RAM_reg_0_15_78_83_n_1,
DOB(1) => RAM_reg_0_15_78_83_n_2,
DOB(0) => RAM_reg_0_15_78_83_n_3,
DOC(1) => RAM_reg_0_15_78_83_n_4,
DOC(0) => RAM_reg_0_15_78_83_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(85 downto 84),
DIB(1 downto 0) => I115(87 downto 86),
DIC(1 downto 0) => I115(89 downto 88),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_84_89_n_0,
DOA(0) => RAM_reg_0_15_84_89_n_1,
DOB(1) => RAM_reg_0_15_84_89_n_2,
DOB(0) => RAM_reg_0_15_84_89_n_3,
DOC(1) => RAM_reg_0_15_84_89_n_4,
DOC(0) => RAM_reg_0_15_84_89_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(91 downto 90),
DIB(1 downto 0) => I115(93 downto 92),
DIC(1 downto 0) => I115(95 downto 94),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_90_95_n_0,
DOA(0) => RAM_reg_0_15_90_95_n_1,
DOB(1) => RAM_reg_0_15_90_95_n_2,
DOB(0) => RAM_reg_0_15_90_95_n_3,
DOC(1) => RAM_reg_0_15_90_95_n_4,
DOC(0) => RAM_reg_0_15_90_95_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(97 downto 96),
DIB(1 downto 0) => I115(99 downto 98),
DIC(1 downto 0) => I115(101 downto 100),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_96_101_n_0,
DOA(0) => RAM_reg_0_15_96_101_n_1,
DOB(1) => RAM_reg_0_15_96_101_n_2,
DOB(0) => RAM_reg_0_15_96_101_n_3,
DOC(1) => RAM_reg_0_15_96_101_n_4,
DOC(0) => RAM_reg_0_15_96_101_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_5,
Q => Q(100),
R => '0'
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_4,
Q => Q(101),
R => '0'
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_1,
Q => Q(102),
R => '0'
);
\gpr1.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_0,
Q => Q(103),
R => '0'
);
\gpr1.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_3,
Q => Q(104),
R => '0'
);
\gpr1.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_2,
Q => Q(105),
R => '0'
);
\gpr1.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_5,
Q => Q(106),
R => '0'
);
\gpr1.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_4,
Q => Q(107),
R => '0'
);
\gpr1.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_1,
Q => Q(108),
R => '0'
);
\gpr1.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_0,
Q => Q(109),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_3,
Q => Q(110),
R => '0'
);
\gpr1.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_2,
Q => Q(111),
R => '0'
);
\gpr1.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_5,
Q => Q(112),
R => '0'
);
\gpr1.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_4,
Q => Q(113),
R => '0'
);
\gpr1.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_1,
Q => Q(114),
R => '0'
);
\gpr1.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_0,
Q => Q(115),
R => '0'
);
\gpr1.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_3,
Q => Q(116),
R => '0'
);
\gpr1.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_2,
Q => Q(117),
R => '0'
);
\gpr1.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_5,
Q => Q(118),
R => '0'
);
\gpr1.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_4,
Q => Q(119),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_1,
Q => Q(120),
R => '0'
);
\gpr1.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_0,
Q => Q(121),
R => '0'
);
\gpr1.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_3,
Q => Q(122),
R => '0'
);
\gpr1.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_2,
Q => Q(123),
R => '0'
);
\gpr1.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_5,
Q => Q(124),
R => '0'
);
\gpr1.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_4,
Q => Q(125),
R => '0'
);
\gpr1.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_1,
Q => Q(126),
R => '0'
);
\gpr1.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_0,
Q => Q(127),
R => '0'
);
\gpr1.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_3,
Q => Q(128),
R => '0'
);
\gpr1.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_2,
Q => Q(129),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_5,
Q => Q(130),
R => '0'
);
\gpr1.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_4,
Q => Q(131),
R => '0'
);
\gpr1.dout_i_reg[132]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_1,
Q => Q(132),
R => '0'
);
\gpr1.dout_i_reg[133]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_0,
Q => Q(133),
R => '0'
);
\gpr1.dout_i_reg[134]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_3,
Q => Q(134),
R => '0'
);
\gpr1.dout_i_reg[135]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_2,
Q => Q(135),
R => '0'
);
\gpr1.dout_i_reg[136]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_5,
Q => Q(136),
R => '0'
);
\gpr1.dout_i_reg[137]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_4,
Q => Q(137),
R => '0'
);
\gpr1.dout_i_reg[138]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_1,
Q => Q(138),
R => '0'
);
\gpr1.dout_i_reg[139]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_0,
Q => Q(139),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[140]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_3,
Q => Q(140),
R => '0'
);
\gpr1.dout_i_reg[141]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_2,
Q => Q(141),
R => '0'
);
\gpr1.dout_i_reg[142]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_5,
Q => Q(142),
R => '0'
);
\gpr1.dout_i_reg[143]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_4,
Q => Q(143),
R => '0'
);
\gpr1.dout_i_reg[144]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_144_144_n_1,
Q => Q(144),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => Q(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => Q(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_1,
Q => Q(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_0,
Q => Q(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_3,
Q => Q(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_2,
Q => Q(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_5,
Q => Q(64),
R => '0'
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_4,
Q => Q(65),
R => '0'
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_1,
Q => Q(66),
R => '0'
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_0,
Q => Q(67),
R => '0'
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_3,
Q => Q(68),
R => '0'
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_2,
Q => Q(69),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_5,
Q => Q(70),
R => '0'
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_4,
Q => Q(71),
R => '0'
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_1,
Q => Q(72),
R => '0'
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_0,
Q => Q(73),
R => '0'
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_3,
Q => Q(74),
R => '0'
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_2,
Q => Q(75),
R => '0'
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_5,
Q => Q(76),
R => '0'
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_4,
Q => Q(77),
R => '0'
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_1,
Q => Q(78),
R => '0'
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_0,
Q => Q(79),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_3,
Q => Q(80),
R => '0'
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_2,
Q => Q(81),
R => '0'
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_5,
Q => Q(82),
R => '0'
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_4,
Q => Q(83),
R => '0'
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_1,
Q => Q(84),
R => '0'
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_0,
Q => Q(85),
R => '0'
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_3,
Q => Q(86),
R => '0'
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_2,
Q => Q(87),
R => '0'
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_5,
Q => Q(88),
R => '0'
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_4,
Q => Q(89),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_1,
Q => Q(90),
R => '0'
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_0,
Q => Q(91),
R => '0'
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_3,
Q => Q(92),
R => '0'
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_2,
Q => Q(93),
R => '0'
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_5,
Q => Q(94),
R => '0'
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_4,
Q => Q(95),
R => '0'
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_1,
Q => Q(96),
R => '0'
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_0,
Q => Q(97),
R => '0'
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_3,
Q => Q(98),
R => '0'
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_2,
Q => Q(99),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_dmem__parameterized1\ is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_dmem__parameterized1\ : entity is "dmem";
end \system_auto_cc_0_dmem__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_dmem__parameterized1\ is
signal RAM_reg_0_15_0_2_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_2_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_2_n_3 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_2 : label is "";
begin
RAM_reg_0_15_0_2: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => m_axi_bresp(1 downto 0),
DIB(1) => '0',
DIB(0) => m_axi_bid(0),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_2_n_0,
DOA(0) => RAM_reg_0_15_0_2_n_1,
DOB(1) => NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED(1),
DOB(0) => RAM_reg_0_15_0_2_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_2_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_2_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_2_n_3,
Q => Q(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_dmem__parameterized2\ is
port (
Q : out STD_LOGIC_VECTOR ( 131 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_dmem__parameterized2\ : entity is "dmem";
end \system_auto_cc_0_dmem__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_dmem__parameterized2\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_0 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_1 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_2 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_3 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_4 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_5 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_0 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_1 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_2 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_3 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_4 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_5 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_0 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_1 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_2 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_3 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_4 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_5 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_0 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_1 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_2 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_3 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_4 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_5 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_0 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_1 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_2 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_3 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_4 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_4 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_5 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_0 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_1 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_2 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_3 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_4 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_0 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_1 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_2 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_3 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_4 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_5 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_0 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_1 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_2 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_3 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_4 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_5 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_0 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_1 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_2 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_3 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_4 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_5 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_0 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_1 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_2 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_3 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_4 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_5 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_0 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_1 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_2 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_3 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_4 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_102_107 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_108_113 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_114_119 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_120_125 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_126_131 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_65 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_66_71 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_72_77 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_78_83 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_84_89 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_90_95 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_96_101 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(1 downto 0),
DIB(1 downto 0) => I127(3 downto 2),
DIC(1 downto 0) => I127(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_102_107: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(103 downto 102),
DIB(1 downto 0) => I127(105 downto 104),
DIC(1 downto 0) => I127(107 downto 106),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_102_107_n_0,
DOA(0) => RAM_reg_0_15_102_107_n_1,
DOB(1) => RAM_reg_0_15_102_107_n_2,
DOB(0) => RAM_reg_0_15_102_107_n_3,
DOC(1) => RAM_reg_0_15_102_107_n_4,
DOC(0) => RAM_reg_0_15_102_107_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_108_113: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(109 downto 108),
DIB(1 downto 0) => I127(111 downto 110),
DIC(1 downto 0) => I127(113 downto 112),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_108_113_n_0,
DOA(0) => RAM_reg_0_15_108_113_n_1,
DOB(1) => RAM_reg_0_15_108_113_n_2,
DOB(0) => RAM_reg_0_15_108_113_n_3,
DOC(1) => RAM_reg_0_15_108_113_n_4,
DOC(0) => RAM_reg_0_15_108_113_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_114_119: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(115 downto 114),
DIB(1 downto 0) => I127(117 downto 116),
DIC(1 downto 0) => I127(119 downto 118),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_114_119_n_0,
DOA(0) => RAM_reg_0_15_114_119_n_1,
DOB(1) => RAM_reg_0_15_114_119_n_2,
DOB(0) => RAM_reg_0_15_114_119_n_3,
DOC(1) => RAM_reg_0_15_114_119_n_4,
DOC(0) => RAM_reg_0_15_114_119_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_120_125: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(121 downto 120),
DIB(1 downto 0) => I127(123 downto 122),
DIC(1 downto 0) => I127(125 downto 124),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_120_125_n_0,
DOA(0) => RAM_reg_0_15_120_125_n_1,
DOB(1) => RAM_reg_0_15_120_125_n_2,
DOB(0) => RAM_reg_0_15_120_125_n_3,
DOC(1) => RAM_reg_0_15_120_125_n_4,
DOC(0) => RAM_reg_0_15_120_125_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_126_131: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(127 downto 126),
DIB(1 downto 0) => I127(129 downto 128),
DIC(1 downto 0) => I127(131 downto 130),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_126_131_n_0,
DOA(0) => RAM_reg_0_15_126_131_n_1,
DOB(1) => RAM_reg_0_15_126_131_n_2,
DOB(0) => RAM_reg_0_15_126_131_n_3,
DOC(1) => RAM_reg_0_15_126_131_n_4,
DOC(0) => RAM_reg_0_15_126_131_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(13 downto 12),
DIB(1 downto 0) => I127(15 downto 14),
DIC(1 downto 0) => I127(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(19 downto 18),
DIB(1 downto 0) => I127(21 downto 20),
DIC(1 downto 0) => I127(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(25 downto 24),
DIB(1 downto 0) => I127(27 downto 26),
DIC(1 downto 0) => I127(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(31 downto 30),
DIB(1 downto 0) => I127(33 downto 32),
DIC(1 downto 0) => I127(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(37 downto 36),
DIB(1 downto 0) => I127(39 downto 38),
DIC(1 downto 0) => I127(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(43 downto 42),
DIB(1 downto 0) => I127(45 downto 44),
DIC(1 downto 0) => I127(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(49 downto 48),
DIB(1 downto 0) => I127(51 downto 50),
DIC(1 downto 0) => I127(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(55 downto 54),
DIB(1 downto 0) => I127(57 downto 56),
DIC(1 downto 0) => I127(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(61 downto 60),
DIB(1 downto 0) => I127(63 downto 62),
DIC(1 downto 0) => I127(65 downto 64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_65_n_0,
DOA(0) => RAM_reg_0_15_60_65_n_1,
DOB(1) => RAM_reg_0_15_60_65_n_2,
DOB(0) => RAM_reg_0_15_60_65_n_3,
DOC(1) => RAM_reg_0_15_60_65_n_4,
DOC(0) => RAM_reg_0_15_60_65_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(67 downto 66),
DIB(1 downto 0) => I127(69 downto 68),
DIC(1 downto 0) => I127(71 downto 70),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_66_71_n_0,
DOA(0) => RAM_reg_0_15_66_71_n_1,
DOB(1) => RAM_reg_0_15_66_71_n_2,
DOB(0) => RAM_reg_0_15_66_71_n_3,
DOC(1) => RAM_reg_0_15_66_71_n_4,
DOC(0) => RAM_reg_0_15_66_71_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(7 downto 6),
DIB(1 downto 0) => I127(9 downto 8),
DIC(1 downto 0) => I127(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(73 downto 72),
DIB(1 downto 0) => I127(75 downto 74),
DIC(1 downto 0) => I127(77 downto 76),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_72_77_n_0,
DOA(0) => RAM_reg_0_15_72_77_n_1,
DOB(1) => RAM_reg_0_15_72_77_n_2,
DOB(0) => RAM_reg_0_15_72_77_n_3,
DOC(1) => RAM_reg_0_15_72_77_n_4,
DOC(0) => RAM_reg_0_15_72_77_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(79 downto 78),
DIB(1 downto 0) => I127(81 downto 80),
DIC(1 downto 0) => I127(83 downto 82),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_78_83_n_0,
DOA(0) => RAM_reg_0_15_78_83_n_1,
DOB(1) => RAM_reg_0_15_78_83_n_2,
DOB(0) => RAM_reg_0_15_78_83_n_3,
DOC(1) => RAM_reg_0_15_78_83_n_4,
DOC(0) => RAM_reg_0_15_78_83_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(85 downto 84),
DIB(1 downto 0) => I127(87 downto 86),
DIC(1 downto 0) => I127(89 downto 88),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_84_89_n_0,
DOA(0) => RAM_reg_0_15_84_89_n_1,
DOB(1) => RAM_reg_0_15_84_89_n_2,
DOB(0) => RAM_reg_0_15_84_89_n_3,
DOC(1) => RAM_reg_0_15_84_89_n_4,
DOC(0) => RAM_reg_0_15_84_89_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(91 downto 90),
DIB(1 downto 0) => I127(93 downto 92),
DIC(1 downto 0) => I127(95 downto 94),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_90_95_n_0,
DOA(0) => RAM_reg_0_15_90_95_n_1,
DOB(1) => RAM_reg_0_15_90_95_n_2,
DOB(0) => RAM_reg_0_15_90_95_n_3,
DOC(1) => RAM_reg_0_15_90_95_n_4,
DOC(0) => RAM_reg_0_15_90_95_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(97 downto 96),
DIB(1 downto 0) => I127(99 downto 98),
DIC(1 downto 0) => I127(101 downto 100),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_96_101_n_0,
DOA(0) => RAM_reg_0_15_96_101_n_1,
DOB(1) => RAM_reg_0_15_96_101_n_2,
DOB(0) => RAM_reg_0_15_96_101_n_3,
DOC(1) => RAM_reg_0_15_96_101_n_4,
DOC(0) => RAM_reg_0_15_96_101_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_5,
Q => Q(100),
R => '0'
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_4,
Q => Q(101),
R => '0'
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_1,
Q => Q(102),
R => '0'
);
\gpr1.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_0,
Q => Q(103),
R => '0'
);
\gpr1.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_3,
Q => Q(104),
R => '0'
);
\gpr1.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_2,
Q => Q(105),
R => '0'
);
\gpr1.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_5,
Q => Q(106),
R => '0'
);
\gpr1.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_4,
Q => Q(107),
R => '0'
);
\gpr1.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_1,
Q => Q(108),
R => '0'
);
\gpr1.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_0,
Q => Q(109),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_3,
Q => Q(110),
R => '0'
);
\gpr1.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_2,
Q => Q(111),
R => '0'
);
\gpr1.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_5,
Q => Q(112),
R => '0'
);
\gpr1.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_4,
Q => Q(113),
R => '0'
);
\gpr1.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_1,
Q => Q(114),
R => '0'
);
\gpr1.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_0,
Q => Q(115),
R => '0'
);
\gpr1.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_3,
Q => Q(116),
R => '0'
);
\gpr1.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_2,
Q => Q(117),
R => '0'
);
\gpr1.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_5,
Q => Q(118),
R => '0'
);
\gpr1.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_4,
Q => Q(119),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_1,
Q => Q(120),
R => '0'
);
\gpr1.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_0,
Q => Q(121),
R => '0'
);
\gpr1.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_3,
Q => Q(122),
R => '0'
);
\gpr1.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_2,
Q => Q(123),
R => '0'
);
\gpr1.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_5,
Q => Q(124),
R => '0'
);
\gpr1.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_4,
Q => Q(125),
R => '0'
);
\gpr1.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_1,
Q => Q(126),
R => '0'
);
\gpr1.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_0,
Q => Q(127),
R => '0'
);
\gpr1.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_3,
Q => Q(128),
R => '0'
);
\gpr1.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_2,
Q => Q(129),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_5,
Q => Q(130),
R => '0'
);
\gpr1.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_4,
Q => Q(131),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => Q(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => Q(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_1,
Q => Q(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_0,
Q => Q(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_3,
Q => Q(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_2,
Q => Q(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_5,
Q => Q(64),
R => '0'
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_4,
Q => Q(65),
R => '0'
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_1,
Q => Q(66),
R => '0'
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_0,
Q => Q(67),
R => '0'
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_3,
Q => Q(68),
R => '0'
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_2,
Q => Q(69),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_5,
Q => Q(70),
R => '0'
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_4,
Q => Q(71),
R => '0'
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_1,
Q => Q(72),
R => '0'
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_0,
Q => Q(73),
R => '0'
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_3,
Q => Q(74),
R => '0'
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_2,
Q => Q(75),
R => '0'
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_5,
Q => Q(76),
R => '0'
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_4,
Q => Q(77),
R => '0'
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_1,
Q => Q(78),
R => '0'
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_0,
Q => Q(79),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_3,
Q => Q(80),
R => '0'
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_2,
Q => Q(81),
R => '0'
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_5,
Q => Q(82),
R => '0'
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_4,
Q => Q(83),
R => '0'
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_1,
Q => Q(84),
R => '0'
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_0,
Q => Q(85),
R => '0'
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_3,
Q => Q(86),
R => '0'
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_2,
Q => Q(87),
R => '0'
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_5,
Q => Q(88),
R => '0'
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_4,
Q => Q(89),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_1,
Q => Q(90),
R => '0'
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_0,
Q => Q(91),
R => '0'
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_3,
Q => Q(92),
R => '0'
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_2,
Q => Q(93),
R => '0'
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_5,
Q => Q(94),
R => '0'
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_4,
Q => Q(95),
R => '0'
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_1,
Q => Q(96),
R => '0'
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_0,
Q => Q(97),
R => '0'
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_3,
Q => Q(98),
R => '0'
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_2,
Q => Q(99),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__2\ : label is "soft_lutpair27";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__6\(0)
);
\gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__6\(1)
);
\gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__6\(2)
);
\gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__6\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__6\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__6\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__6\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__6\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__2_n_0\,
I1 => \ram_empty_i_i_3__2_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__2_n_0\
);
\ram_empty_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_20 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_20 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_20;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_20 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__0\ : label is "soft_lutpair21";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => \ram_empty_i_i_3__0_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_41 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_41 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_41;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_41 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_2 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_3 : label is "soft_lutpair15";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => plusOp(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => ram_empty_i_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_62 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_62 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_62;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_62 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__3\ : label is "soft_lutpair9";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__8\(0)
);
\gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__8\(1)
);
\gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__8\(2)
);
\gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__8\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__8\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__3_n_0\,
I1 => \ram_empty_i_i_3__3_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__3_n_0\
);
\ram_empty_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_86 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_86 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_86;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_86 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__1\ : label is "soft_lutpair3";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__2\(0)
);
\gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__2\(1)
);
\gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__2\(2)
);
\gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__2\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__2\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__1_n_0\,
I1 => \ram_empty_i_i_3__1_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__1_n_0\
);
\ram_empty_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft;
architecture STRUCTURE of system_auto_cc_0_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\out\(1 downto 0) <= curr_fwft_state(1 downto 0);
\aempty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_bready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_bvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_18 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[144]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_18 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_18;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_18 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[144]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => \goreg_dm.dout_i_reg[144]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_wready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_wvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_wvalid
);
\ram_empty_i_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_39 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_39 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_39;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_39 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[57]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => \goreg_dm.dout_i_reg[57]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_awready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_awvalid
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_60 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[131]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_60 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_60;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_60 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[131]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => \goreg_dm.dout_i_reg[131]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_rready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_84 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_84 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_84;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_84 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[57]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => \goreg_dm.dout_i_reg[57]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_arready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_arvalid
);
\ram_empty_i_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_19 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_19 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_19;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_19 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_40 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_40 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_40;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_40 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_61 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_61 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_61;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_61 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_85 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_85 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_85;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_85 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_1 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_1;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_10 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_10 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_10;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_11 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_11 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_11;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_11 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_12 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_12 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_12;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_12 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_13 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_13 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_13;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_13 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_14 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_14 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_14;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_14 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_15 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_15 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_15;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_15 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_2 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_2 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_2;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_3 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_3 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_3;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_31 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_31 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_31;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_31 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_32 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_32 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_32;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_32 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_33 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_33 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_33;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_33 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_34 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_34 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_34;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_34 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_35 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_35 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_35;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_35 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_36 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_36 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_36;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_36 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_4 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_4 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_4;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_5 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_5 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_5;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_52 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_52 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_52;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_52 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_53 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_53 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_53;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_53 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_54 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_54 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_54;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_54 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_55 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_55 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_55;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_55 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_56 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_56 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_56;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_56 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_57 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_57 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_57;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_57 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_75 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_75 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_75;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_75 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_76 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_76 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_76;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_76 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_77 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_77 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_77;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_77 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_78 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_78 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_78;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_78 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_79 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_79 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_79;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_79 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_80 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_80 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_80;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_80 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_21\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_21\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_21\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_21\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_42\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_42\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_42\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_42\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_63\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_63\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_63\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_63\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_87\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_87\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_87\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_87\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_22\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_22\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_22\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_22\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_43\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_43\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_43\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_43\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_64\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_64\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_64\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_64\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_88\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_88\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_88\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_88\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_23\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_23\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_23\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_23\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_44\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_44\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_44\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_44\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_65\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_65\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_65\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_65\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_89\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_89\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_89\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_89\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_24\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_24\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_24\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_24\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_45\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_45\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_45\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_45\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_66\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_66\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_66\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_66\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_90\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_90\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_90\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_90\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_25\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_25\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_25\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_25\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_46\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_46\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_46\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_46\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_67\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_67\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_67\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_67\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_91\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_91\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_91\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_91\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_26\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_26\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_26\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_26\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_47\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_47\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_47\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_47\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_68\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_68\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_68\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_68\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_92\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_92\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_92\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_92\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair29";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_17 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_17 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_17;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_17 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__2\ : label is "soft_lutpair23";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__5\(0)
);
\gic0.gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__5\(1)
);
\gic0.gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__5\(2)
);
\gic0.gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__5\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__5\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_38 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_38 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_38;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_38 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__1\ : label is "soft_lutpair17";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__4\(0)
);
\gic0.gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__4\(1)
);
\gic0.gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__4\(2)
);
\gic0.gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__4\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__4\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_59 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_59 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_59;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_59 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__0\ : label is "soft_lutpair11";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__3\(0)
);
\gic0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__3\(1)
);
\gic0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__3\(2)
);
\gic0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__3\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__3\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_83 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_83 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_83;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_83 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__3\ : label is "soft_lutpair5";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__7\(0)
);
\gic0.gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__7\(1)
);
\gic0.gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__7\(2)
);
\gic0.gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__7\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__7\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_bvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_bready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_bready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_bvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_16 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_16 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_16;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_16 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_wvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_wready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_wready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_37 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_37 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_37;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_37 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_awvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_awready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_awready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_58 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_58 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_58;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_58 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_rready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_rready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_rvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_82 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_82 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_82;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_82 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_arvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_arready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair25";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => ram_full_i_i_4_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => ram_full_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_27 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_27 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_27;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_27 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__1_n_0\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair13";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_42\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_43\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_44\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_45\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_46\
port map (
D(0) => p_0_out,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_47\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out_1(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out_1(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out_1(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__1_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__1_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_2__1_n_0\
);
\ram_full_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_4__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_48 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_48 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_48;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_48 is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair7";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_63\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_64\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_65\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_66\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_67\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_68\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__0_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__0_n_0\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_6 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_6 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_6;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_6 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair19";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_21\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_22\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_23\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_24\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_25\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_26\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__2_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__2_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__2_n_0\
);
\ram_full_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_70 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_70 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_70;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_70 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair1";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_87\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_88\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_89\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_90\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_91\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_92\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__3_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__3_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__3_n_0\
);
\ram_full_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_memory is
port (
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_memory : entity is "memory";
end system_auto_cc_0_memory;
architecture STRUCTURE of system_auto_cc_0_memory is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.system_auto_cc_0_dmem
port map (
DI(57 downto 0) => DI(57 downto 0),
dout_i(57) => \gdm.dm_gen.dm_n_0\,
dout_i(56) => \gdm.dm_gen.dm_n_1\,
dout_i(55) => \gdm.dm_gen.dm_n_2\,
dout_i(54) => \gdm.dm_gen.dm_n_3\,
dout_i(53) => \gdm.dm_gen.dm_n_4\,
dout_i(52) => \gdm.dm_gen.dm_n_5\,
dout_i(51) => \gdm.dm_gen.dm_n_6\,
dout_i(50) => \gdm.dm_gen.dm_n_7\,
dout_i(49) => \gdm.dm_gen.dm_n_8\,
dout_i(48) => \gdm.dm_gen.dm_n_9\,
dout_i(47) => \gdm.dm_gen.dm_n_10\,
dout_i(46) => \gdm.dm_gen.dm_n_11\,
dout_i(45) => \gdm.dm_gen.dm_n_12\,
dout_i(44) => \gdm.dm_gen.dm_n_13\,
dout_i(43) => \gdm.dm_gen.dm_n_14\,
dout_i(42) => \gdm.dm_gen.dm_n_15\,
dout_i(41) => \gdm.dm_gen.dm_n_16\,
dout_i(40) => \gdm.dm_gen.dm_n_17\,
dout_i(39) => \gdm.dm_gen.dm_n_18\,
dout_i(38) => \gdm.dm_gen.dm_n_19\,
dout_i(37) => \gdm.dm_gen.dm_n_20\,
dout_i(36) => \gdm.dm_gen.dm_n_21\,
dout_i(35) => \gdm.dm_gen.dm_n_22\,
dout_i(34) => \gdm.dm_gen.dm_n_23\,
dout_i(33) => \gdm.dm_gen.dm_n_24\,
dout_i(32) => \gdm.dm_gen.dm_n_25\,
dout_i(31) => \gdm.dm_gen.dm_n_26\,
dout_i(30) => \gdm.dm_gen.dm_n_27\,
dout_i(29) => \gdm.dm_gen.dm_n_28\,
dout_i(28) => \gdm.dm_gen.dm_n_29\,
dout_i(27) => \gdm.dm_gen.dm_n_30\,
dout_i(26) => \gdm.dm_gen.dm_n_31\,
dout_i(25) => \gdm.dm_gen.dm_n_32\,
dout_i(24) => \gdm.dm_gen.dm_n_33\,
dout_i(23) => \gdm.dm_gen.dm_n_34\,
dout_i(22) => \gdm.dm_gen.dm_n_35\,
dout_i(21) => \gdm.dm_gen.dm_n_36\,
dout_i(20) => \gdm.dm_gen.dm_n_37\,
dout_i(19) => \gdm.dm_gen.dm_n_38\,
dout_i(18) => \gdm.dm_gen.dm_n_39\,
dout_i(17) => \gdm.dm_gen.dm_n_40\,
dout_i(16) => \gdm.dm_gen.dm_n_41\,
dout_i(15) => \gdm.dm_gen.dm_n_42\,
dout_i(14) => \gdm.dm_gen.dm_n_43\,
dout_i(13) => \gdm.dm_gen.dm_n_44\,
dout_i(12) => \gdm.dm_gen.dm_n_45\,
dout_i(11) => \gdm.dm_gen.dm_n_46\,
dout_i(10) => \gdm.dm_gen.dm_n_47\,
dout_i(9) => \gdm.dm_gen.dm_n_48\,
dout_i(8) => \gdm.dm_gen.dm_n_49\,
dout_i(7) => \gdm.dm_gen.dm_n_50\,
dout_i(6) => \gdm.dm_gen.dm_n_51\,
dout_i(5) => \gdm.dm_gen.dm_n_52\,
dout_i(4) => \gdm.dm_gen.dm_n_53\,
dout_i(3) => \gdm.dm_gen.dm_n_54\,
dout_i(2) => \gdm.dm_gen.dm_n_55\,
dout_i(1) => \gdm.dm_gen.dm_n_56\,
dout_i(0) => \gdm.dm_gen.dm_n_57\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_57\,
Q => Q(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_47\,
Q => Q(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_46\,
Q => Q(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_45\,
Q => Q(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_44\,
Q => Q(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_43\,
Q => Q(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_42\,
Q => Q(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_41\,
Q => Q(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_40\,
Q => Q(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_39\,
Q => Q(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_38\,
Q => Q(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_56\,
Q => Q(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_37\,
Q => Q(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_36\,
Q => Q(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_35\,
Q => Q(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_34\,
Q => Q(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_33\,
Q => Q(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_32\,
Q => Q(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_31\,
Q => Q(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_30\,
Q => Q(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_29\,
Q => Q(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_28\,
Q => Q(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_55\,
Q => Q(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_27\,
Q => Q(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_26\,
Q => Q(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_25\,
Q => Q(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_24\,
Q => Q(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_23\,
Q => Q(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_22\,
Q => Q(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_21\,
Q => Q(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_20\,
Q => Q(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_19\,
Q => Q(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_18\,
Q => Q(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_54\,
Q => Q(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_17\,
Q => Q(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_16\,
Q => Q(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_15\,
Q => Q(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_14\,
Q => Q(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_13\,
Q => Q(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_12\,
Q => Q(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_11\,
Q => Q(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_10\,
Q => Q(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_9\,
Q => Q(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_8\,
Q => Q(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_53\,
Q => Q(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_7\,
Q => Q(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_6\,
Q => Q(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_5\,
Q => Q(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_4\,
Q => Q(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_3\,
Q => Q(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_2\,
Q => Q(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_1\,
Q => Q(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_0\,
Q => Q(57),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_52\,
Q => Q(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_51\,
Q => Q(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_50\,
Q => Q(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_49\,
Q => Q(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_48\,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_memory_73 is
port (
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_memory_73 : entity is "memory";
end system_auto_cc_0_memory_73;
architecture STRUCTURE of system_auto_cc_0_memory_73 is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.system_auto_cc_0_dmem_81
port map (
E(0) => E(0),
I123(57 downto 0) => I123(57 downto 0),
Q(57) => \gdm.dm_gen.dm_n_0\,
Q(56) => \gdm.dm_gen.dm_n_1\,
Q(55) => \gdm.dm_gen.dm_n_2\,
Q(54) => \gdm.dm_gen.dm_n_3\,
Q(53) => \gdm.dm_gen.dm_n_4\,
Q(52) => \gdm.dm_gen.dm_n_5\,
Q(51) => \gdm.dm_gen.dm_n_6\,
Q(50) => \gdm.dm_gen.dm_n_7\,
Q(49) => \gdm.dm_gen.dm_n_8\,
Q(48) => \gdm.dm_gen.dm_n_9\,
Q(47) => \gdm.dm_gen.dm_n_10\,
Q(46) => \gdm.dm_gen.dm_n_11\,
Q(45) => \gdm.dm_gen.dm_n_12\,
Q(44) => \gdm.dm_gen.dm_n_13\,
Q(43) => \gdm.dm_gen.dm_n_14\,
Q(42) => \gdm.dm_gen.dm_n_15\,
Q(41) => \gdm.dm_gen.dm_n_16\,
Q(40) => \gdm.dm_gen.dm_n_17\,
Q(39) => \gdm.dm_gen.dm_n_18\,
Q(38) => \gdm.dm_gen.dm_n_19\,
Q(37) => \gdm.dm_gen.dm_n_20\,
Q(36) => \gdm.dm_gen.dm_n_21\,
Q(35) => \gdm.dm_gen.dm_n_22\,
Q(34) => \gdm.dm_gen.dm_n_23\,
Q(33) => \gdm.dm_gen.dm_n_24\,
Q(32) => \gdm.dm_gen.dm_n_25\,
Q(31) => \gdm.dm_gen.dm_n_26\,
Q(30) => \gdm.dm_gen.dm_n_27\,
Q(29) => \gdm.dm_gen.dm_n_28\,
Q(28) => \gdm.dm_gen.dm_n_29\,
Q(27) => \gdm.dm_gen.dm_n_30\,
Q(26) => \gdm.dm_gen.dm_n_31\,
Q(25) => \gdm.dm_gen.dm_n_32\,
Q(24) => \gdm.dm_gen.dm_n_33\,
Q(23) => \gdm.dm_gen.dm_n_34\,
Q(22) => \gdm.dm_gen.dm_n_35\,
Q(21) => \gdm.dm_gen.dm_n_36\,
Q(20) => \gdm.dm_gen.dm_n_37\,
Q(19) => \gdm.dm_gen.dm_n_38\,
Q(18) => \gdm.dm_gen.dm_n_39\,
Q(17) => \gdm.dm_gen.dm_n_40\,
Q(16) => \gdm.dm_gen.dm_n_41\,
Q(15) => \gdm.dm_gen.dm_n_42\,
Q(14) => \gdm.dm_gen.dm_n_43\,
Q(13) => \gdm.dm_gen.dm_n_44\,
Q(12) => \gdm.dm_gen.dm_n_45\,
Q(11) => \gdm.dm_gen.dm_n_46\,
Q(10) => \gdm.dm_gen.dm_n_47\,
Q(9) => \gdm.dm_gen.dm_n_48\,
Q(8) => \gdm.dm_gen.dm_n_49\,
Q(7) => \gdm.dm_gen.dm_n_50\,
Q(6) => \gdm.dm_gen.dm_n_51\,
Q(5) => \gdm.dm_gen.dm_n_52\,
Q(4) => \gdm.dm_gen.dm_n_53\,
Q(3) => \gdm.dm_gen.dm_n_54\,
Q(2) => \gdm.dm_gen.dm_n_55\,
Q(1) => \gdm.dm_gen.dm_n_56\,
Q(0) => \gdm.dm_gen.dm_n_57\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \m_axi_arid[0]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \m_axi_arid[0]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \m_axi_arid[0]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \m_axi_arid[0]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \m_axi_arid[0]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \m_axi_arid[0]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \m_axi_arid[0]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \m_axi_arid[0]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \m_axi_arid[0]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \m_axi_arid[0]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \m_axi_arid[0]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \m_axi_arid[0]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \m_axi_arid[0]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_arid[0]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_arid[0]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_arid[0]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_arid[0]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_arid[0]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_arid[0]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_arid[0]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_arid[0]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_arid[0]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \m_axi_arid[0]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_arid[0]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_arid[0]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_arid[0]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_arid[0]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_arid[0]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_arid[0]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_arid[0]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_arid[0]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_arid[0]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_arid[0]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \m_axi_arid[0]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_arid[0]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_arid[0]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_arid[0]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_arid[0]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_arid[0]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_arid[0]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_arid[0]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_arid[0]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_arid[0]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_arid[0]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \m_axi_arid[0]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_arid[0]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_arid[0]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_arid[0]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_arid[0]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_arid[0]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_arid[0]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_arid[0]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_arid[0]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \m_axi_arid[0]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \m_axi_arid[0]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \m_axi_arid[0]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \m_axi_arid[0]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \m_axi_arid[0]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_memory__parameterized0\ is
port (
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_memory__parameterized0\ : entity is "memory";
end \system_auto_cc_0_memory__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_memory__parameterized0\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_100\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_101\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_102\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_103\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_104\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_105\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_106\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_107\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_108\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_109\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_110\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_111\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_112\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_113\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_114\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_115\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_116\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_117\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_118\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_119\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_120\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_121\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_122\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_123\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_124\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_125\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_126\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_127\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_128\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_129\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_130\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_131\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_132\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_133\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_134\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_135\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_136\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_137\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_138\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_139\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_140\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_141\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_142\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_143\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_144\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_65\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_66\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_67\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_68\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_69\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_70\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_71\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_72\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_73\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_74\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_75\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_76\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_77\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_78\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_79\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_80\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_81\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_82\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_83\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_84\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_85\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_86\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_87\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_88\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_89\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_90\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_91\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_92\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_93\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_94\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_95\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_96\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_97\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_98\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_99\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\system_auto_cc_0_dmem__parameterized0\
port map (
E(0) => E(0),
I115(144 downto 0) => I115(144 downto 0),
Q(144) => \gdm.dm_gen.dm_n_0\,
Q(143) => \gdm.dm_gen.dm_n_1\,
Q(142) => \gdm.dm_gen.dm_n_2\,
Q(141) => \gdm.dm_gen.dm_n_3\,
Q(140) => \gdm.dm_gen.dm_n_4\,
Q(139) => \gdm.dm_gen.dm_n_5\,
Q(138) => \gdm.dm_gen.dm_n_6\,
Q(137) => \gdm.dm_gen.dm_n_7\,
Q(136) => \gdm.dm_gen.dm_n_8\,
Q(135) => \gdm.dm_gen.dm_n_9\,
Q(134) => \gdm.dm_gen.dm_n_10\,
Q(133) => \gdm.dm_gen.dm_n_11\,
Q(132) => \gdm.dm_gen.dm_n_12\,
Q(131) => \gdm.dm_gen.dm_n_13\,
Q(130) => \gdm.dm_gen.dm_n_14\,
Q(129) => \gdm.dm_gen.dm_n_15\,
Q(128) => \gdm.dm_gen.dm_n_16\,
Q(127) => \gdm.dm_gen.dm_n_17\,
Q(126) => \gdm.dm_gen.dm_n_18\,
Q(125) => \gdm.dm_gen.dm_n_19\,
Q(124) => \gdm.dm_gen.dm_n_20\,
Q(123) => \gdm.dm_gen.dm_n_21\,
Q(122) => \gdm.dm_gen.dm_n_22\,
Q(121) => \gdm.dm_gen.dm_n_23\,
Q(120) => \gdm.dm_gen.dm_n_24\,
Q(119) => \gdm.dm_gen.dm_n_25\,
Q(118) => \gdm.dm_gen.dm_n_26\,
Q(117) => \gdm.dm_gen.dm_n_27\,
Q(116) => \gdm.dm_gen.dm_n_28\,
Q(115) => \gdm.dm_gen.dm_n_29\,
Q(114) => \gdm.dm_gen.dm_n_30\,
Q(113) => \gdm.dm_gen.dm_n_31\,
Q(112) => \gdm.dm_gen.dm_n_32\,
Q(111) => \gdm.dm_gen.dm_n_33\,
Q(110) => \gdm.dm_gen.dm_n_34\,
Q(109) => \gdm.dm_gen.dm_n_35\,
Q(108) => \gdm.dm_gen.dm_n_36\,
Q(107) => \gdm.dm_gen.dm_n_37\,
Q(106) => \gdm.dm_gen.dm_n_38\,
Q(105) => \gdm.dm_gen.dm_n_39\,
Q(104) => \gdm.dm_gen.dm_n_40\,
Q(103) => \gdm.dm_gen.dm_n_41\,
Q(102) => \gdm.dm_gen.dm_n_42\,
Q(101) => \gdm.dm_gen.dm_n_43\,
Q(100) => \gdm.dm_gen.dm_n_44\,
Q(99) => \gdm.dm_gen.dm_n_45\,
Q(98) => \gdm.dm_gen.dm_n_46\,
Q(97) => \gdm.dm_gen.dm_n_47\,
Q(96) => \gdm.dm_gen.dm_n_48\,
Q(95) => \gdm.dm_gen.dm_n_49\,
Q(94) => \gdm.dm_gen.dm_n_50\,
Q(93) => \gdm.dm_gen.dm_n_51\,
Q(92) => \gdm.dm_gen.dm_n_52\,
Q(91) => \gdm.dm_gen.dm_n_53\,
Q(90) => \gdm.dm_gen.dm_n_54\,
Q(89) => \gdm.dm_gen.dm_n_55\,
Q(88) => \gdm.dm_gen.dm_n_56\,
Q(87) => \gdm.dm_gen.dm_n_57\,
Q(86) => \gdm.dm_gen.dm_n_58\,
Q(85) => \gdm.dm_gen.dm_n_59\,
Q(84) => \gdm.dm_gen.dm_n_60\,
Q(83) => \gdm.dm_gen.dm_n_61\,
Q(82) => \gdm.dm_gen.dm_n_62\,
Q(81) => \gdm.dm_gen.dm_n_63\,
Q(80) => \gdm.dm_gen.dm_n_64\,
Q(79) => \gdm.dm_gen.dm_n_65\,
Q(78) => \gdm.dm_gen.dm_n_66\,
Q(77) => \gdm.dm_gen.dm_n_67\,
Q(76) => \gdm.dm_gen.dm_n_68\,
Q(75) => \gdm.dm_gen.dm_n_69\,
Q(74) => \gdm.dm_gen.dm_n_70\,
Q(73) => \gdm.dm_gen.dm_n_71\,
Q(72) => \gdm.dm_gen.dm_n_72\,
Q(71) => \gdm.dm_gen.dm_n_73\,
Q(70) => \gdm.dm_gen.dm_n_74\,
Q(69) => \gdm.dm_gen.dm_n_75\,
Q(68) => \gdm.dm_gen.dm_n_76\,
Q(67) => \gdm.dm_gen.dm_n_77\,
Q(66) => \gdm.dm_gen.dm_n_78\,
Q(65) => \gdm.dm_gen.dm_n_79\,
Q(64) => \gdm.dm_gen.dm_n_80\,
Q(63) => \gdm.dm_gen.dm_n_81\,
Q(62) => \gdm.dm_gen.dm_n_82\,
Q(61) => \gdm.dm_gen.dm_n_83\,
Q(60) => \gdm.dm_gen.dm_n_84\,
Q(59) => \gdm.dm_gen.dm_n_85\,
Q(58) => \gdm.dm_gen.dm_n_86\,
Q(57) => \gdm.dm_gen.dm_n_87\,
Q(56) => \gdm.dm_gen.dm_n_88\,
Q(55) => \gdm.dm_gen.dm_n_89\,
Q(54) => \gdm.dm_gen.dm_n_90\,
Q(53) => \gdm.dm_gen.dm_n_91\,
Q(52) => \gdm.dm_gen.dm_n_92\,
Q(51) => \gdm.dm_gen.dm_n_93\,
Q(50) => \gdm.dm_gen.dm_n_94\,
Q(49) => \gdm.dm_gen.dm_n_95\,
Q(48) => \gdm.dm_gen.dm_n_96\,
Q(47) => \gdm.dm_gen.dm_n_97\,
Q(46) => \gdm.dm_gen.dm_n_98\,
Q(45) => \gdm.dm_gen.dm_n_99\,
Q(44) => \gdm.dm_gen.dm_n_100\,
Q(43) => \gdm.dm_gen.dm_n_101\,
Q(42) => \gdm.dm_gen.dm_n_102\,
Q(41) => \gdm.dm_gen.dm_n_103\,
Q(40) => \gdm.dm_gen.dm_n_104\,
Q(39) => \gdm.dm_gen.dm_n_105\,
Q(38) => \gdm.dm_gen.dm_n_106\,
Q(37) => \gdm.dm_gen.dm_n_107\,
Q(36) => \gdm.dm_gen.dm_n_108\,
Q(35) => \gdm.dm_gen.dm_n_109\,
Q(34) => \gdm.dm_gen.dm_n_110\,
Q(33) => \gdm.dm_gen.dm_n_111\,
Q(32) => \gdm.dm_gen.dm_n_112\,
Q(31) => \gdm.dm_gen.dm_n_113\,
Q(30) => \gdm.dm_gen.dm_n_114\,
Q(29) => \gdm.dm_gen.dm_n_115\,
Q(28) => \gdm.dm_gen.dm_n_116\,
Q(27) => \gdm.dm_gen.dm_n_117\,
Q(26) => \gdm.dm_gen.dm_n_118\,
Q(25) => \gdm.dm_gen.dm_n_119\,
Q(24) => \gdm.dm_gen.dm_n_120\,
Q(23) => \gdm.dm_gen.dm_n_121\,
Q(22) => \gdm.dm_gen.dm_n_122\,
Q(21) => \gdm.dm_gen.dm_n_123\,
Q(20) => \gdm.dm_gen.dm_n_124\,
Q(19) => \gdm.dm_gen.dm_n_125\,
Q(18) => \gdm.dm_gen.dm_n_126\,
Q(17) => \gdm.dm_gen.dm_n_127\,
Q(16) => \gdm.dm_gen.dm_n_128\,
Q(15) => \gdm.dm_gen.dm_n_129\,
Q(14) => \gdm.dm_gen.dm_n_130\,
Q(13) => \gdm.dm_gen.dm_n_131\,
Q(12) => \gdm.dm_gen.dm_n_132\,
Q(11) => \gdm.dm_gen.dm_n_133\,
Q(10) => \gdm.dm_gen.dm_n_134\,
Q(9) => \gdm.dm_gen.dm_n_135\,
Q(8) => \gdm.dm_gen.dm_n_136\,
Q(7) => \gdm.dm_gen.dm_n_137\,
Q(6) => \gdm.dm_gen.dm_n_138\,
Q(5) => \gdm.dm_gen.dm_n_139\,
Q(4) => \gdm.dm_gen.dm_n_140\,
Q(3) => \gdm.dm_gen.dm_n_141\,
Q(2) => \gdm.dm_gen.dm_n_142\,
Q(1) => \gdm.dm_gen.dm_n_143\,
Q(0) => \gdm.dm_gen.dm_n_144\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_144\,
Q => \m_axi_wdata[127]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \m_axi_wdata[127]\(100),
R => '0'
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \m_axi_wdata[127]\(101),
R => '0'
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \m_axi_wdata[127]\(102),
R => '0'
);
\goreg_dm.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \m_axi_wdata[127]\(103),
R => '0'
);
\goreg_dm.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \m_axi_wdata[127]\(104),
R => '0'
);
\goreg_dm.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \m_axi_wdata[127]\(105),
R => '0'
);
\goreg_dm.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \m_axi_wdata[127]\(106),
R => '0'
);
\goreg_dm.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \m_axi_wdata[127]\(107),
R => '0'
);
\goreg_dm.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_wdata[127]\(108),
R => '0'
);
\goreg_dm.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_wdata[127]\(109),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_134\,
Q => \m_axi_wdata[127]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_wdata[127]\(110),
R => '0'
);
\goreg_dm.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_wdata[127]\(111),
R => '0'
);
\goreg_dm.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_wdata[127]\(112),
R => '0'
);
\goreg_dm.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_wdata[127]\(113),
R => '0'
);
\goreg_dm.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_wdata[127]\(114),
R => '0'
);
\goreg_dm.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_wdata[127]\(115),
R => '0'
);
\goreg_dm.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_wdata[127]\(116),
R => '0'
);
\goreg_dm.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_wdata[127]\(117),
R => '0'
);
\goreg_dm.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_wdata[127]\(118),
R => '0'
);
\goreg_dm.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_wdata[127]\(119),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_133\,
Q => \m_axi_wdata[127]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_wdata[127]\(120),
R => '0'
);
\goreg_dm.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_wdata[127]\(121),
R => '0'
);
\goreg_dm.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_wdata[127]\(122),
R => '0'
);
\goreg_dm.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_wdata[127]\(123),
R => '0'
);
\goreg_dm.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_wdata[127]\(124),
R => '0'
);
\goreg_dm.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_wdata[127]\(125),
R => '0'
);
\goreg_dm.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_wdata[127]\(126),
R => '0'
);
\goreg_dm.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_wdata[127]\(127),
R => '0'
);
\goreg_dm.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_wdata[127]\(128),
R => '0'
);
\goreg_dm.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_wdata[127]\(129),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_132\,
Q => \m_axi_wdata[127]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_wdata[127]\(130),
R => '0'
);
\goreg_dm.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_wdata[127]\(131),
R => '0'
);
\goreg_dm.dout_i_reg[132]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_wdata[127]\(132),
R => '0'
);
\goreg_dm.dout_i_reg[133]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_wdata[127]\(133),
R => '0'
);
\goreg_dm.dout_i_reg[134]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_wdata[127]\(134),
R => '0'
);
\goreg_dm.dout_i_reg[135]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_wdata[127]\(135),
R => '0'
);
\goreg_dm.dout_i_reg[136]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_wdata[127]\(136),
R => '0'
);
\goreg_dm.dout_i_reg[137]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_wdata[127]\(137),
R => '0'
);
\goreg_dm.dout_i_reg[138]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_wdata[127]\(138),
R => '0'
);
\goreg_dm.dout_i_reg[139]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_wdata[127]\(139),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_131\,
Q => \m_axi_wdata[127]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[140]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_wdata[127]\(140),
R => '0'
);
\goreg_dm.dout_i_reg[141]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_wdata[127]\(141),
R => '0'
);
\goreg_dm.dout_i_reg[142]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_wdata[127]\(142),
R => '0'
);
\goreg_dm.dout_i_reg[143]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_wdata[127]\(143),
R => '0'
);
\goreg_dm.dout_i_reg[144]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_wdata[127]\(144),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_130\,
Q => \m_axi_wdata[127]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_129\,
Q => \m_axi_wdata[127]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_128\,
Q => \m_axi_wdata[127]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_127\,
Q => \m_axi_wdata[127]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_126\,
Q => \m_axi_wdata[127]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_125\,
Q => \m_axi_wdata[127]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_143\,
Q => \m_axi_wdata[127]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_124\,
Q => \m_axi_wdata[127]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_123\,
Q => \m_axi_wdata[127]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_122\,
Q => \m_axi_wdata[127]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_121\,
Q => \m_axi_wdata[127]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_120\,
Q => \m_axi_wdata[127]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_119\,
Q => \m_axi_wdata[127]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_118\,
Q => \m_axi_wdata[127]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_117\,
Q => \m_axi_wdata[127]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_116\,
Q => \m_axi_wdata[127]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_115\,
Q => \m_axi_wdata[127]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_142\,
Q => \m_axi_wdata[127]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_114\,
Q => \m_axi_wdata[127]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_113\,
Q => \m_axi_wdata[127]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_112\,
Q => \m_axi_wdata[127]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_111\,
Q => \m_axi_wdata[127]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_110\,
Q => \m_axi_wdata[127]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_109\,
Q => \m_axi_wdata[127]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_108\,
Q => \m_axi_wdata[127]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_107\,
Q => \m_axi_wdata[127]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_106\,
Q => \m_axi_wdata[127]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_105\,
Q => \m_axi_wdata[127]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_141\,
Q => \m_axi_wdata[127]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_104\,
Q => \m_axi_wdata[127]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_103\,
Q => \m_axi_wdata[127]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_102\,
Q => \m_axi_wdata[127]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_101\,
Q => \m_axi_wdata[127]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_100\,
Q => \m_axi_wdata[127]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_99\,
Q => \m_axi_wdata[127]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_98\,
Q => \m_axi_wdata[127]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_97\,
Q => \m_axi_wdata[127]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_96\,
Q => \m_axi_wdata[127]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_95\,
Q => \m_axi_wdata[127]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_140\,
Q => \m_axi_wdata[127]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_94\,
Q => \m_axi_wdata[127]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_93\,
Q => \m_axi_wdata[127]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_92\,
Q => \m_axi_wdata[127]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_91\,
Q => \m_axi_wdata[127]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_90\,
Q => \m_axi_wdata[127]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_89\,
Q => \m_axi_wdata[127]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_88\,
Q => \m_axi_wdata[127]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_87\,
Q => \m_axi_wdata[127]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_86\,
Q => \m_axi_wdata[127]\(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_85\,
Q => \m_axi_wdata[127]\(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_139\,
Q => \m_axi_wdata[127]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_84\,
Q => \m_axi_wdata[127]\(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_83\,
Q => \m_axi_wdata[127]\(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_82\,
Q => \m_axi_wdata[127]\(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_81\,
Q => \m_axi_wdata[127]\(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_80\,
Q => \m_axi_wdata[127]\(64),
R => '0'
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_79\,
Q => \m_axi_wdata[127]\(65),
R => '0'
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_78\,
Q => \m_axi_wdata[127]\(66),
R => '0'
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_77\,
Q => \m_axi_wdata[127]\(67),
R => '0'
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_76\,
Q => \m_axi_wdata[127]\(68),
R => '0'
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_75\,
Q => \m_axi_wdata[127]\(69),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_138\,
Q => \m_axi_wdata[127]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_74\,
Q => \m_axi_wdata[127]\(70),
R => '0'
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_73\,
Q => \m_axi_wdata[127]\(71),
R => '0'
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_72\,
Q => \m_axi_wdata[127]\(72),
R => '0'
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_71\,
Q => \m_axi_wdata[127]\(73),
R => '0'
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_70\,
Q => \m_axi_wdata[127]\(74),
R => '0'
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_69\,
Q => \m_axi_wdata[127]\(75),
R => '0'
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_68\,
Q => \m_axi_wdata[127]\(76),
R => '0'
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_67\,
Q => \m_axi_wdata[127]\(77),
R => '0'
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_66\,
Q => \m_axi_wdata[127]\(78),
R => '0'
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_65\,
Q => \m_axi_wdata[127]\(79),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_137\,
Q => \m_axi_wdata[127]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_64\,
Q => \m_axi_wdata[127]\(80),
R => '0'
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_63\,
Q => \m_axi_wdata[127]\(81),
R => '0'
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_62\,
Q => \m_axi_wdata[127]\(82),
R => '0'
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_61\,
Q => \m_axi_wdata[127]\(83),
R => '0'
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_60\,
Q => \m_axi_wdata[127]\(84),
R => '0'
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_59\,
Q => \m_axi_wdata[127]\(85),
R => '0'
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_58\,
Q => \m_axi_wdata[127]\(86),
R => '0'
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \m_axi_wdata[127]\(87),
R => '0'
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \m_axi_wdata[127]\(88),
R => '0'
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \m_axi_wdata[127]\(89),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_136\,
Q => \m_axi_wdata[127]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \m_axi_wdata[127]\(90),
R => '0'
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \m_axi_wdata[127]\(91),
R => '0'
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \m_axi_wdata[127]\(92),
R => '0'
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \m_axi_wdata[127]\(93),
R => '0'
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \m_axi_wdata[127]\(94),
R => '0'
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \m_axi_wdata[127]\(95),
R => '0'
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \m_axi_wdata[127]\(96),
R => '0'
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \m_axi_wdata[127]\(97),
R => '0'
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \m_axi_wdata[127]\(98),
R => '0'
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \m_axi_wdata[127]\(99),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_135\,
Q => \m_axi_wdata[127]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_memory__parameterized1\ is
port (
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_memory__parameterized1\ : entity is "memory";
end \system_auto_cc_0_memory__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_memory__parameterized1\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \goreg_dm.dout_i[0]_i_1_n_0\ : STD_LOGIC;
signal \goreg_dm.dout_i[1]_i_1_n_0\ : STD_LOGIC;
signal \goreg_dm.dout_i[2]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
\gdm.dm_gen.dm\: entity work.\system_auto_cc_0_dmem__parameterized1\
port map (
E(0) => E(0),
Q(2) => \gdm.dm_gen.dm_n_0\,
Q(1) => \gdm.dm_gen.dm_n_1\,
Q(0) => \gdm.dm_gen.dm_n_2\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
s_aclk => s_aclk
);
\goreg_dm.dout_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \gdm.dm_gen.dm_n_2\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => s_axi_bready,
I5 => \^s_axi_bresp\(0),
O => \goreg_dm.dout_i[0]_i_1_n_0\
);
\goreg_dm.dout_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \gdm.dm_gen.dm_n_1\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => s_axi_bready,
I5 => \^s_axi_bresp\(1),
O => \goreg_dm.dout_i[1]_i_1_n_0\
);
\goreg_dm.dout_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \gdm.dm_gen.dm_n_0\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => s_axi_bready,
I5 => \^s_axi_bid\(0),
O => \goreg_dm.dout_i[2]_i_1_n_0\
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \goreg_dm.dout_i[0]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \goreg_dm.dout_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \goreg_dm.dout_i[2]_i_1_n_0\,
Q => \^s_axi_bid\(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_memory__parameterized2\ is
port (
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_memory__parameterized2\ : entity is "memory";
end \system_auto_cc_0_memory__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_memory__parameterized2\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_100\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_101\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_102\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_103\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_104\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_105\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_106\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_107\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_108\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_109\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_110\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_111\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_112\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_113\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_114\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_115\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_116\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_117\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_118\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_119\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_120\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_121\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_122\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_123\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_124\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_125\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_126\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_127\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_128\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_129\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_130\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_131\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_65\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_66\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_67\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_68\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_69\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_70\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_71\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_72\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_73\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_74\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_75\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_76\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_77\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_78\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_79\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_80\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_81\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_82\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_83\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_84\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_85\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_86\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_87\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_88\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_89\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_90\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_91\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_92\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_93\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_94\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_95\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_96\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_97\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_98\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_99\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\system_auto_cc_0_dmem__parameterized2\
port map (
E(0) => E(0),
I127(131 downto 0) => I127(131 downto 0),
Q(131) => \gdm.dm_gen.dm_n_0\,
Q(130) => \gdm.dm_gen.dm_n_1\,
Q(129) => \gdm.dm_gen.dm_n_2\,
Q(128) => \gdm.dm_gen.dm_n_3\,
Q(127) => \gdm.dm_gen.dm_n_4\,
Q(126) => \gdm.dm_gen.dm_n_5\,
Q(125) => \gdm.dm_gen.dm_n_6\,
Q(124) => \gdm.dm_gen.dm_n_7\,
Q(123) => \gdm.dm_gen.dm_n_8\,
Q(122) => \gdm.dm_gen.dm_n_9\,
Q(121) => \gdm.dm_gen.dm_n_10\,
Q(120) => \gdm.dm_gen.dm_n_11\,
Q(119) => \gdm.dm_gen.dm_n_12\,
Q(118) => \gdm.dm_gen.dm_n_13\,
Q(117) => \gdm.dm_gen.dm_n_14\,
Q(116) => \gdm.dm_gen.dm_n_15\,
Q(115) => \gdm.dm_gen.dm_n_16\,
Q(114) => \gdm.dm_gen.dm_n_17\,
Q(113) => \gdm.dm_gen.dm_n_18\,
Q(112) => \gdm.dm_gen.dm_n_19\,
Q(111) => \gdm.dm_gen.dm_n_20\,
Q(110) => \gdm.dm_gen.dm_n_21\,
Q(109) => \gdm.dm_gen.dm_n_22\,
Q(108) => \gdm.dm_gen.dm_n_23\,
Q(107) => \gdm.dm_gen.dm_n_24\,
Q(106) => \gdm.dm_gen.dm_n_25\,
Q(105) => \gdm.dm_gen.dm_n_26\,
Q(104) => \gdm.dm_gen.dm_n_27\,
Q(103) => \gdm.dm_gen.dm_n_28\,
Q(102) => \gdm.dm_gen.dm_n_29\,
Q(101) => \gdm.dm_gen.dm_n_30\,
Q(100) => \gdm.dm_gen.dm_n_31\,
Q(99) => \gdm.dm_gen.dm_n_32\,
Q(98) => \gdm.dm_gen.dm_n_33\,
Q(97) => \gdm.dm_gen.dm_n_34\,
Q(96) => \gdm.dm_gen.dm_n_35\,
Q(95) => \gdm.dm_gen.dm_n_36\,
Q(94) => \gdm.dm_gen.dm_n_37\,
Q(93) => \gdm.dm_gen.dm_n_38\,
Q(92) => \gdm.dm_gen.dm_n_39\,
Q(91) => \gdm.dm_gen.dm_n_40\,
Q(90) => \gdm.dm_gen.dm_n_41\,
Q(89) => \gdm.dm_gen.dm_n_42\,
Q(88) => \gdm.dm_gen.dm_n_43\,
Q(87) => \gdm.dm_gen.dm_n_44\,
Q(86) => \gdm.dm_gen.dm_n_45\,
Q(85) => \gdm.dm_gen.dm_n_46\,
Q(84) => \gdm.dm_gen.dm_n_47\,
Q(83) => \gdm.dm_gen.dm_n_48\,
Q(82) => \gdm.dm_gen.dm_n_49\,
Q(81) => \gdm.dm_gen.dm_n_50\,
Q(80) => \gdm.dm_gen.dm_n_51\,
Q(79) => \gdm.dm_gen.dm_n_52\,
Q(78) => \gdm.dm_gen.dm_n_53\,
Q(77) => \gdm.dm_gen.dm_n_54\,
Q(76) => \gdm.dm_gen.dm_n_55\,
Q(75) => \gdm.dm_gen.dm_n_56\,
Q(74) => \gdm.dm_gen.dm_n_57\,
Q(73) => \gdm.dm_gen.dm_n_58\,
Q(72) => \gdm.dm_gen.dm_n_59\,
Q(71) => \gdm.dm_gen.dm_n_60\,
Q(70) => \gdm.dm_gen.dm_n_61\,
Q(69) => \gdm.dm_gen.dm_n_62\,
Q(68) => \gdm.dm_gen.dm_n_63\,
Q(67) => \gdm.dm_gen.dm_n_64\,
Q(66) => \gdm.dm_gen.dm_n_65\,
Q(65) => \gdm.dm_gen.dm_n_66\,
Q(64) => \gdm.dm_gen.dm_n_67\,
Q(63) => \gdm.dm_gen.dm_n_68\,
Q(62) => \gdm.dm_gen.dm_n_69\,
Q(61) => \gdm.dm_gen.dm_n_70\,
Q(60) => \gdm.dm_gen.dm_n_71\,
Q(59) => \gdm.dm_gen.dm_n_72\,
Q(58) => \gdm.dm_gen.dm_n_73\,
Q(57) => \gdm.dm_gen.dm_n_74\,
Q(56) => \gdm.dm_gen.dm_n_75\,
Q(55) => \gdm.dm_gen.dm_n_76\,
Q(54) => \gdm.dm_gen.dm_n_77\,
Q(53) => \gdm.dm_gen.dm_n_78\,
Q(52) => \gdm.dm_gen.dm_n_79\,
Q(51) => \gdm.dm_gen.dm_n_80\,
Q(50) => \gdm.dm_gen.dm_n_81\,
Q(49) => \gdm.dm_gen.dm_n_82\,
Q(48) => \gdm.dm_gen.dm_n_83\,
Q(47) => \gdm.dm_gen.dm_n_84\,
Q(46) => \gdm.dm_gen.dm_n_85\,
Q(45) => \gdm.dm_gen.dm_n_86\,
Q(44) => \gdm.dm_gen.dm_n_87\,
Q(43) => \gdm.dm_gen.dm_n_88\,
Q(42) => \gdm.dm_gen.dm_n_89\,
Q(41) => \gdm.dm_gen.dm_n_90\,
Q(40) => \gdm.dm_gen.dm_n_91\,
Q(39) => \gdm.dm_gen.dm_n_92\,
Q(38) => \gdm.dm_gen.dm_n_93\,
Q(37) => \gdm.dm_gen.dm_n_94\,
Q(36) => \gdm.dm_gen.dm_n_95\,
Q(35) => \gdm.dm_gen.dm_n_96\,
Q(34) => \gdm.dm_gen.dm_n_97\,
Q(33) => \gdm.dm_gen.dm_n_98\,
Q(32) => \gdm.dm_gen.dm_n_99\,
Q(31) => \gdm.dm_gen.dm_n_100\,
Q(30) => \gdm.dm_gen.dm_n_101\,
Q(29) => \gdm.dm_gen.dm_n_102\,
Q(28) => \gdm.dm_gen.dm_n_103\,
Q(27) => \gdm.dm_gen.dm_n_104\,
Q(26) => \gdm.dm_gen.dm_n_105\,
Q(25) => \gdm.dm_gen.dm_n_106\,
Q(24) => \gdm.dm_gen.dm_n_107\,
Q(23) => \gdm.dm_gen.dm_n_108\,
Q(22) => \gdm.dm_gen.dm_n_109\,
Q(21) => \gdm.dm_gen.dm_n_110\,
Q(20) => \gdm.dm_gen.dm_n_111\,
Q(19) => \gdm.dm_gen.dm_n_112\,
Q(18) => \gdm.dm_gen.dm_n_113\,
Q(17) => \gdm.dm_gen.dm_n_114\,
Q(16) => \gdm.dm_gen.dm_n_115\,
Q(15) => \gdm.dm_gen.dm_n_116\,
Q(14) => \gdm.dm_gen.dm_n_117\,
Q(13) => \gdm.dm_gen.dm_n_118\,
Q(12) => \gdm.dm_gen.dm_n_119\,
Q(11) => \gdm.dm_gen.dm_n_120\,
Q(10) => \gdm.dm_gen.dm_n_121\,
Q(9) => \gdm.dm_gen.dm_n_122\,
Q(8) => \gdm.dm_gen.dm_n_123\,
Q(7) => \gdm.dm_gen.dm_n_124\,
Q(6) => \gdm.dm_gen.dm_n_125\,
Q(5) => \gdm.dm_gen.dm_n_126\,
Q(4) => \gdm.dm_gen.dm_n_127\,
Q(3) => \gdm.dm_gen.dm_n_128\,
Q(2) => \gdm.dm_gen.dm_n_129\,
Q(1) => \gdm.dm_gen.dm_n_130\,
Q(0) => \gdm.dm_gen.dm_n_131\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_131\,
Q => \s_axi_rid[0]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \s_axi_rid[0]\(100),
R => '0'
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \s_axi_rid[0]\(101),
R => '0'
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \s_axi_rid[0]\(102),
R => '0'
);
\goreg_dm.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \s_axi_rid[0]\(103),
R => '0'
);
\goreg_dm.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \s_axi_rid[0]\(104),
R => '0'
);
\goreg_dm.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \s_axi_rid[0]\(105),
R => '0'
);
\goreg_dm.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \s_axi_rid[0]\(106),
R => '0'
);
\goreg_dm.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \s_axi_rid[0]\(107),
R => '0'
);
\goreg_dm.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \s_axi_rid[0]\(108),
R => '0'
);
\goreg_dm.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \s_axi_rid[0]\(109),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_121\,
Q => \s_axi_rid[0]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \s_axi_rid[0]\(110),
R => '0'
);
\goreg_dm.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \s_axi_rid[0]\(111),
R => '0'
);
\goreg_dm.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \s_axi_rid[0]\(112),
R => '0'
);
\goreg_dm.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \s_axi_rid[0]\(113),
R => '0'
);
\goreg_dm.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \s_axi_rid[0]\(114),
R => '0'
);
\goreg_dm.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \s_axi_rid[0]\(115),
R => '0'
);
\goreg_dm.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \s_axi_rid[0]\(116),
R => '0'
);
\goreg_dm.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \s_axi_rid[0]\(117),
R => '0'
);
\goreg_dm.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \s_axi_rid[0]\(118),
R => '0'
);
\goreg_dm.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \s_axi_rid[0]\(119),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_120\,
Q => \s_axi_rid[0]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \s_axi_rid[0]\(120),
R => '0'
);
\goreg_dm.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \s_axi_rid[0]\(121),
R => '0'
);
\goreg_dm.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \s_axi_rid[0]\(122),
R => '0'
);
\goreg_dm.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \s_axi_rid[0]\(123),
R => '0'
);
\goreg_dm.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \s_axi_rid[0]\(124),
R => '0'
);
\goreg_dm.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \s_axi_rid[0]\(125),
R => '0'
);
\goreg_dm.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_rid[0]\(126),
R => '0'
);
\goreg_dm.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_rid[0]\(127),
R => '0'
);
\goreg_dm.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_rid[0]\(128),
R => '0'
);
\goreg_dm.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_rid[0]\(129),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_119\,
Q => \s_axi_rid[0]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_rid[0]\(130),
R => '0'
);
\goreg_dm.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_rid[0]\(131),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_118\,
Q => \s_axi_rid[0]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_117\,
Q => \s_axi_rid[0]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_116\,
Q => \s_axi_rid[0]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_115\,
Q => \s_axi_rid[0]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_114\,
Q => \s_axi_rid[0]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_113\,
Q => \s_axi_rid[0]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_112\,
Q => \s_axi_rid[0]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_130\,
Q => \s_axi_rid[0]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_111\,
Q => \s_axi_rid[0]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_110\,
Q => \s_axi_rid[0]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_109\,
Q => \s_axi_rid[0]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_108\,
Q => \s_axi_rid[0]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_107\,
Q => \s_axi_rid[0]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_106\,
Q => \s_axi_rid[0]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_105\,
Q => \s_axi_rid[0]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_104\,
Q => \s_axi_rid[0]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_103\,
Q => \s_axi_rid[0]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_102\,
Q => \s_axi_rid[0]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_129\,
Q => \s_axi_rid[0]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_101\,
Q => \s_axi_rid[0]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_100\,
Q => \s_axi_rid[0]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_99\,
Q => \s_axi_rid[0]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_98\,
Q => \s_axi_rid[0]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_97\,
Q => \s_axi_rid[0]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_96\,
Q => \s_axi_rid[0]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_95\,
Q => \s_axi_rid[0]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_94\,
Q => \s_axi_rid[0]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_93\,
Q => \s_axi_rid[0]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_92\,
Q => \s_axi_rid[0]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_128\,
Q => \s_axi_rid[0]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_91\,
Q => \s_axi_rid[0]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_90\,
Q => \s_axi_rid[0]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_89\,
Q => \s_axi_rid[0]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_88\,
Q => \s_axi_rid[0]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_87\,
Q => \s_axi_rid[0]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_86\,
Q => \s_axi_rid[0]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_85\,
Q => \s_axi_rid[0]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_84\,
Q => \s_axi_rid[0]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_83\,
Q => \s_axi_rid[0]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_82\,
Q => \s_axi_rid[0]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_127\,
Q => \s_axi_rid[0]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_81\,
Q => \s_axi_rid[0]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_80\,
Q => \s_axi_rid[0]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_79\,
Q => \s_axi_rid[0]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_78\,
Q => \s_axi_rid[0]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_77\,
Q => \s_axi_rid[0]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_76\,
Q => \s_axi_rid[0]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_75\,
Q => \s_axi_rid[0]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_74\,
Q => \s_axi_rid[0]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_73\,
Q => \s_axi_rid[0]\(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_72\,
Q => \s_axi_rid[0]\(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_126\,
Q => \s_axi_rid[0]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_71\,
Q => \s_axi_rid[0]\(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_70\,
Q => \s_axi_rid[0]\(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_69\,
Q => \s_axi_rid[0]\(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_68\,
Q => \s_axi_rid[0]\(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_67\,
Q => \s_axi_rid[0]\(64),
R => '0'
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_66\,
Q => \s_axi_rid[0]\(65),
R => '0'
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_65\,
Q => \s_axi_rid[0]\(66),
R => '0'
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_64\,
Q => \s_axi_rid[0]\(67),
R => '0'
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_63\,
Q => \s_axi_rid[0]\(68),
R => '0'
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_62\,
Q => \s_axi_rid[0]\(69),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_125\,
Q => \s_axi_rid[0]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_61\,
Q => \s_axi_rid[0]\(70),
R => '0'
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_60\,
Q => \s_axi_rid[0]\(71),
R => '0'
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_59\,
Q => \s_axi_rid[0]\(72),
R => '0'
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_58\,
Q => \s_axi_rid[0]\(73),
R => '0'
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \s_axi_rid[0]\(74),
R => '0'
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \s_axi_rid[0]\(75),
R => '0'
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \s_axi_rid[0]\(76),
R => '0'
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \s_axi_rid[0]\(77),
R => '0'
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \s_axi_rid[0]\(78),
R => '0'
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \s_axi_rid[0]\(79),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_124\,
Q => \s_axi_rid[0]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \s_axi_rid[0]\(80),
R => '0'
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \s_axi_rid[0]\(81),
R => '0'
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \s_axi_rid[0]\(82),
R => '0'
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \s_axi_rid[0]\(83),
R => '0'
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \s_axi_rid[0]\(84),
R => '0'
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \s_axi_rid[0]\(85),
R => '0'
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \s_axi_rid[0]\(86),
R => '0'
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \s_axi_rid[0]\(87),
R => '0'
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \s_axi_rid[0]\(88),
R => '0'
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \s_axi_rid[0]\(89),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_123\,
Q => \s_axi_rid[0]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \s_axi_rid[0]\(90),
R => '0'
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \s_axi_rid[0]\(91),
R => '0'
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \s_axi_rid[0]\(92),
R => '0'
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \s_axi_rid[0]\(93),
R => '0'
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \s_axi_rid[0]\(94),
R => '0'
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \s_axi_rid[0]\(95),
R => '0'
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \s_axi_rid[0]\(96),
R => '0'
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \s_axi_rid[0]\(97),
R => '0'
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \s_axi_rid[0]\(98),
R => '0'
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \s_axi_rid[0]\(99),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_122\,
Q => \s_axi_rid[0]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic : entity is "rd_logic";
end system_auto_cc_0_rd_logic;
architecture STRUCTURE of system_auto_cc_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_2\,
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as
port map (
AR(0) => AR(0),
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr
port map (
AR(0) => AR(0),
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_2\,
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_28 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_28 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_28;
architecture STRUCTURE of system_auto_cc_0_rd_logic_28 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_39
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[57]\(0) => \goreg_dm.dout_i_reg[57]\(0),
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_40
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_41
port map (
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_49 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[131]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_49 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_49;
architecture STRUCTURE of system_auto_cc_0_rd_logic_49 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_60
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[131]\(0) => \goreg_dm.dout_i_reg[131]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_61
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_62
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_7 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[144]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_7 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_7;
architecture STRUCTURE of system_auto_cc_0_rd_logic_7 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_18
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[144]\(0) => \goreg_dm.dout_i_reg[144]\(0),
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_19
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_20
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_71 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_71 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_71;
architecture STRUCTURE of system_auto_cc_0_rd_logic_71 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_84
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[57]\(0) => \goreg_dm.dout_i_reg[57]\(0),
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_85
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_86
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_1
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_3
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_4
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_5
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_30 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_30 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_30;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_30 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_31
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_32
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_33
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_34
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_35
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_36
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_51 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_51 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_51;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_51 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ <= \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_52
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_53
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_54
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_55
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_56
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_57
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_74 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_74 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_74;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_74 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_75
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_76
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_77
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_78
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_79
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_80
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_9 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_9 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_9;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_9 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_10
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_11
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_12
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_13
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_14
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_15
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic : entity is "wr_logic";
end system_auto_cc_0_wr_logic;
architecture STRUCTURE of system_auto_cc_0_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_29 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_29 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_29;
architecture STRUCTURE of system_auto_cc_0_wr_logic_29 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_37
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_38
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_50 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_50 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_50;
architecture STRUCTURE of system_auto_cc_0_wr_logic_50 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_58
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_59
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_72 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_72 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_72;
architecture STRUCTURE of system_auto_cc_0_wr_logic_72 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_82
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_83
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_8 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_8 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_8;
architecture STRUCTURE of system_auto_cc_0_wr_logic_8 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_16
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_17
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_ramfifo is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_auto_cc_0_fifo_generator_ramfifo;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_27
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
Q(3 downto 0) => p_22_out(3 downto 0),
\gc0.count_d1_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gc0.count_d1_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gc0.count_d1_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gc0.count_d1_reg[3]\(0) => p_0_out_0(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_23_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out_1(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_28
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[57]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_29
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out_1(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gntv_or_sync_fifo.mem\: entity work.system_auto_cc_0_memory
port map (
DI(57 downto 0) => DI(57 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
Q(57 downto 0) => Q(57 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => p_18_out,
s_aclk => s_aclk
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_30
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_23_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_ramfifo_69 is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_ramfifo_69 : entity is "fifo_generator_ramfifo";
end system_auto_cc_0_fifo_generator_ramfifo_69;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_ramfifo_69 is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rach : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_70
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rach,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_71
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[57]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_72
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gntv_or_sync_fifo.mem\: entity work.system_auto_cc_0_memory_73
port map (
E(0) => p_18_out,
I123(57 downto 0) => I123(57 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_arid[0]\(57 downto 0) => \m_axi_arid[0]\(57 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_74
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rach,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo";
end \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_6
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_15_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_7
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[144]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_8
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_cc_0_memory__parameterized0\
port map (
E(0) => p_18_out,
I115(144 downto 0) => I115(144 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_wdata[127]\(144 downto 0) => \m_axi_wdata[127]\(144 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_9
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_15_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo";
end \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal \gr1.gr1_int.rfwft/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_wrch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_wrch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\out\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\out\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_cc_0_memory__parameterized1\
port map (
E(0) => p_18_out,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
\gpregsm1.curr_fwft_state_reg[1]_0\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0)
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_wrch,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
port (
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\ : entity is "fifo_generator_ramfifo";
end \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rdch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_48
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rdch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_49
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[131]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_50
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_cc_0_memory__parameterized2\
port map (
E(0) => p_18_out,
I127(131 downto 0) => I127(131 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_rid[0]\(131 downto 0) => \s_axi_rid[0]\(131 downto 0)
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_51
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ => \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rdch,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_top is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_top : entity is "fifo_generator_top";
end system_auto_cc_0_fifo_generator_top;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_top is
begin
\grf.rf\: entity work.system_auto_cc_0_fifo_generator_ramfifo_69
port map (
I123(57 downto 0) => I123(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[0]\(57 downto 0) => \m_axi_arid[0]\(57 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_top_0 is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_top_0 : entity is "fifo_generator_top";
end system_auto_cc_0_fifo_generator_top_0;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_top_0 is
begin
\grf.rf\: entity work.system_auto_cc_0_fifo_generator_ramfifo
port map (
DI(57 downto 0) => DI(57 downto 0),
Q(57 downto 0) => Q(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_top__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top";
end \system_auto_cc_0_fifo_generator_top__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_top__parameterized0\ is
begin
\grf.rf\: entity work.\system_auto_cc_0_fifo_generator_ramfifo__parameterized0\
port map (
I115(144 downto 0) => I115(144 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[127]\(144 downto 0) => \m_axi_wdata[127]\(144 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_top__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top";
end \system_auto_cc_0_fifo_generator_top__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_top__parameterized1\ is
begin
\grf.rf\: entity work.\system_auto_cc_0_fifo_generator_ramfifo__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_top__parameterized2\ is
port (
inverted_reset : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_top__parameterized2\ : entity is "fifo_generator_top";
end \system_auto_cc_0_fifo_generator_top__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_top__parameterized2\ is
begin
\grf.rf\: entity work.\system_auto_cc_0_fifo_generator_ramfifo__parameterized2\
port map (
I127(131 downto 0) => I127(131 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ => inverted_reset,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[0]\(131 downto 0) => \s_axi_rid[0]\(131 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_v13_1_3_synth is
port (
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
s_axi_awready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 );
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 );
DI : in STD_LOGIC_VECTOR ( 57 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_auto_cc_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_v13_1_3_synth is
signal inverted_reset : STD_LOGIC;
begin
\gaxi_full_lite.gread_ch.grach2.axi_rach\: entity work.system_auto_cc_0_fifo_generator_top
port map (
I123(57 downto 0) => I123(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[0]\(57 downto 0) => \m_axi_arid[0]\(57 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gaxi_full_lite.gread_ch.grdch2.axi_rdch\: entity work.\system_auto_cc_0_fifo_generator_top__parameterized2\
port map (
I127(131 downto 0) => I127(131 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[0]\(131 downto 0) => \s_axi_rid[0]\(131 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gaxi_full_lite.gwrite_ch.gwach2.axi_wach\: entity work.system_auto_cc_0_fifo_generator_top_0
port map (
DI(57 downto 0) => DI(57 downto 0),
Q(57 downto 0) => Q(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch\: entity work.\system_auto_cc_0_fifo_generator_top__parameterized0\
port map (
I115(144 downto 0) => I115(144 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[127]\(144 downto 0) => \m_axi_wdata[127]\(144 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch\: entity work.\system_auto_cc_0_fifo_generator_top__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 17 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 28;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 58;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 132;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 58;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 145;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_auto_cc_0_fifo_generator_v13_1_3;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
dout(17) <= \<const0>\;
dout(16) <= \<const0>\;
dout(15) <= \<const0>\;
dout(14) <= \<const0>\;
dout(13) <= \<const0>\;
dout(12) <= \<const0>\;
dout(11) <= \<const0>\;
dout(10) <= \<const0>\;
dout(9) <= \<const0>\;
dout(8) <= \<const0>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const0>\;
dout(3) <= \<const0>\;
dout(2) <= \<const0>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
empty <= \<const0>\;
full <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.system_auto_cc_0_fifo_generator_v13_1_3_synth
port map (
DI(57) => s_axi_awid(0),
DI(56 downto 29) => s_axi_awaddr(27 downto 0),
DI(28 downto 21) => s_axi_awlen(7 downto 0),
DI(20 downto 18) => s_axi_awsize(2 downto 0),
DI(17 downto 16) => s_axi_awburst(1 downto 0),
DI(15) => s_axi_awlock(0),
DI(14 downto 11) => s_axi_awcache(3 downto 0),
DI(10 downto 8) => s_axi_awprot(2 downto 0),
DI(7 downto 4) => s_axi_awqos(3 downto 0),
DI(3 downto 0) => s_axi_awregion(3 downto 0),
I115(144 downto 17) => s_axi_wdata(127 downto 0),
I115(16 downto 1) => s_axi_wstrb(15 downto 0),
I115(0) => s_axi_wlast,
I123(57) => s_axi_arid(0),
I123(56 downto 29) => s_axi_araddr(27 downto 0),
I123(28 downto 21) => s_axi_arlen(7 downto 0),
I123(20 downto 18) => s_axi_arsize(2 downto 0),
I123(17 downto 16) => s_axi_arburst(1 downto 0),
I123(15) => s_axi_arlock(0),
I123(14 downto 11) => s_axi_arcache(3 downto 0),
I123(10 downto 8) => s_axi_arprot(2 downto 0),
I123(7 downto 4) => s_axi_arqos(3 downto 0),
I123(3 downto 0) => s_axi_arregion(3 downto 0),
I127(131) => m_axi_rid(0),
I127(130 downto 3) => m_axi_rdata(127 downto 0),
I127(2 downto 1) => m_axi_rresp(1 downto 0),
I127(0) => m_axi_rlast,
Q(57) => m_axi_awid(0),
Q(56 downto 29) => m_axi_awaddr(27 downto 0),
Q(28 downto 21) => m_axi_awlen(7 downto 0),
Q(20 downto 18) => m_axi_awsize(2 downto 0),
Q(17 downto 16) => m_axi_awburst(1 downto 0),
Q(15) => m_axi_awlock(0),
Q(14 downto 11) => m_axi_awcache(3 downto 0),
Q(10 downto 8) => m_axi_awprot(2 downto 0),
Q(7 downto 4) => m_axi_awqos(3 downto 0),
Q(3 downto 0) => m_axi_awregion(3 downto 0),
m_aclk => m_aclk,
\m_axi_arid[0]\(57) => m_axi_arid(0),
\m_axi_arid[0]\(56 downto 29) => m_axi_araddr(27 downto 0),
\m_axi_arid[0]\(28 downto 21) => m_axi_arlen(7 downto 0),
\m_axi_arid[0]\(20 downto 18) => m_axi_arsize(2 downto 0),
\m_axi_arid[0]\(17 downto 16) => m_axi_arburst(1 downto 0),
\m_axi_arid[0]\(15) => m_axi_arlock(0),
\m_axi_arid[0]\(14 downto 11) => m_axi_arcache(3 downto 0),
\m_axi_arid[0]\(10 downto 8) => m_axi_arprot(2 downto 0),
\m_axi_arid[0]\(7 downto 4) => m_axi_arqos(3 downto 0),
\m_axi_arid[0]\(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\m_axi_wdata[127]\(144 downto 17) => m_axi_wdata(127 downto 0),
\m_axi_wdata[127]\(16 downto 1) => m_axi_wstrb(15 downto 0),
\m_axi_wdata[127]\(0) => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[0]\(131) => s_axi_rid(0),
\s_axi_rid[0]\(130 downto 3) => s_axi_rdata(127 downto 0),
\s_axi_rid[0]\(2 downto 1) => s_axi_rresp(1 downto 0),
\s_axi_rid[0]\(0) => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 28;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 57;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 28;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 57;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 28;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 132;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 145;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 128;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 131;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 132;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 17;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 128;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 145;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 145;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "axi_clock_converter_v2_1_10_axi_clock_converter";
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "1'b1";
end system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter;
architecture STRUCTURE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
signal \<const0>\ : STD_LOGIC;
signal async_conv_reset_n : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXI_ADDR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 28;
attribute C_AXI_ARUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_AWUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_BUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_DATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 128;
attribute C_AXI_ID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_RUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_WUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 58;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 132;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 58;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 145;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_FAMILY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SYNCHRONIZER_STAGE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
begin
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi\: entity work.system_auto_cc_0_fifo_generator_v13_1_3
port map (
almost_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\,
almost_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\,
axi_ar_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\(4 downto 0),
axi_ar_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\,
axi_ar_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\(4 downto 0),
axi_ar_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\,
axi_ar_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\,
axi_ar_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\(4 downto 0),
axi_aw_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\(4 downto 0),
axi_aw_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\,
axi_aw_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\(4 downto 0),
axi_aw_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\,
axi_aw_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\,
axi_aw_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\(4 downto 0),
axi_b_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\(4 downto 0),
axi_b_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\,
axi_b_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\(4 downto 0),
axi_b_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\,
axi_b_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\,
axi_b_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\(4 downto 0),
axi_r_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\(4 downto 0),
axi_r_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\,
axi_r_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\,
axi_r_prog_empty_thresh(3 downto 0) => B"0000",
axi_r_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\,
axi_r_prog_full_thresh(3 downto 0) => B"0000",
axi_r_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\(4 downto 0),
axi_r_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\,
axi_r_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\,
axi_r_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\(4 downto 0),
axi_w_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\(4 downto 0),
axi_w_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\,
axi_w_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\,
axi_w_prog_empty_thresh(3 downto 0) => B"0000",
axi_w_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\,
axi_w_prog_full_thresh(3 downto 0) => B"0000",
axi_w_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\(4 downto 0),
axi_w_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\,
axi_w_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\,
axi_w_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\(4 downto 0),
axis_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\(10 downto 0),
axis_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\,
axis_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\(10 downto 0),
axis_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\,
axis_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\,
axis_wr_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\(9 downto 0),
dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\,
din(17 downto 0) => B"000000000000000000",
dout(17 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\(17 downto 0),
empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\,
full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => m_axi_aclk,
m_aclk_en => '1',
m_axi_araddr(27 downto 0) => m_axi_araddr(27 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(0) => m_axi_arid(0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(27 downto 0) => m_axi_awaddr(27 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(0) => m_axi_awid(0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\(0),
m_axi_wvalid => m_axi_wvalid,
m_axis_tdata(7 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\(7 downto 0),
m_axis_tdest(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\(0),
m_axis_tid(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\(0),
m_axis_tkeep(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\(0),
m_axis_tlast => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\,
m_axis_tready => '0',
m_axis_tstrb(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\(0),
m_axis_tuser(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\(3 downto 0),
m_axis_tvalid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\,
overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\,
prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\(9 downto 0),
rd_en => '0',
rd_rst => '0',
rd_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\,
rst => '0',
s_aclk => s_axi_aclk,
s_aclk_en => '1',
s_aresetn => async_conv_reset_n,
s_axi_araddr(27 downto 0) => s_axi_araddr(27 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(27 downto 0) => s_axi_awaddr(27 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid,
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\,
sleep => '0',
srst => '0',
underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\,
valid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\,
wr_ack => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\,
wr_clk => '0',
wr_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\(9 downto 0),
wr_en => '0',
wr_rst => '0',
wr_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_aresetn,
I1 => m_axi_aresetn,
O => async_conv_reset_n
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_cc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_cc_0 : entity is "system_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_cc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_cc_0 : entity is "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4";
end system_auto_cc_0;
architecture STRUCTURE of system_auto_cc_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of inst : label is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of inst : label is 28;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of inst : label is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of inst : label is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of inst : label is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of inst : label is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of inst : label is 57;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of inst : label is 1;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of inst : label is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of inst : label is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of inst : label is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of inst : label is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of inst : label is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of inst : label is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of inst : label is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of inst : label is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of inst : label is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of inst : label is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of inst : label is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of inst : label is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of inst : label is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of inst : label is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of inst : label is 58;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of inst : label is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of inst : label is 28;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of inst : label is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of inst : label is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of inst : label is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of inst : label is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of inst : label is 57;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of inst : label is 1;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of inst : label is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of inst : label is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of inst : label is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of inst : label is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of inst : label is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of inst : label is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of inst : label is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of inst : label is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of inst : label is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of inst : label is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of inst : label is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of inst : label is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of inst : label is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of inst : label is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of inst : label is 58;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 28;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of inst : label is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of inst : label is 1;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of inst : label is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of inst : label is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of inst : label is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of inst : label is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of inst : label is 3;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of inst : label is 58;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of inst : label is 58;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of inst : label is 3;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of inst : label is 132;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of inst : label is 145;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of inst : label is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of inst : label is 128;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of inst : label is 131;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of inst : label is 1;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of inst : label is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of inst : label is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of inst : label is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of inst : label is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of inst : label is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of inst : label is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of inst : label is 132;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of inst : label is 17;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of inst : label is 128;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of inst : label is 145;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of inst : label is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of inst : label is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of inst : label is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of inst : label is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of inst : label is 16;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of inst : label is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of inst : label is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of inst : label is 145;
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of inst : label is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of inst : label is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of inst : label is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of inst : label is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of inst : label is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of inst : label is "1'b1";
attribute downgradeipidentifiedwarnings of inst : label is "yes";
begin
inst: entity work.system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
port map (
m_axi_aclk => m_axi_aclk,
m_axi_araddr(27 downto 0) => m_axi_araddr(27 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => m_axi_aresetn,
m_axi_arid(0) => m_axi_arid(0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(27 downto 0) => m_axi_awaddr(27 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(0) => m_axi_awid(0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(27 downto 0) => s_axi_araddr(27 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(27 downto 0) => s_axi_awaddr(27 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
----------------------------------------------------------------------------
-- GPIO_demo.vhd -- Nexys3 GPIO/UART Demonstration Project
----------------------------------------------------------------------------
-- Author: <NAME>
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- The GPIO/UART Demo project demonstrates a simple usage of the Nexys3's
-- GPIO and UART in an ISE design. The behavior is as follows:
--
-- *The 8 User LEDs are tied to the 8 User Switches. While the center
-- User button is pressed, the LEDs are instead tied to GND
-- *The 7-Segment display counts from 0 to 9 on each of it 4
-- digits. This count is reset when the center button is pressed.
-- Also, single anodes of the 7-Segment display are blanked by
-- holding BTNU, BTNL, BTND, or BTNR. Holding the center button
-- blanks all the 7-Segment anodes.
-- *An introduction message is sent across the UART when the device
-- is finished being configured, and after the center User button
-- is pressed.
-- *A message is sent over UART whenever BTNU, BTNL, BTND, or BTNR is
-- pressed.
-- *Note that the center user button behaves as a user reset button
-- and is referred to as such in the code comments below
--
-- All UART communication can be captured by attaching the UART port to a
-- computer running a Terminal program with 9600 Baud Rate, 8 data bits, no
-- parity, and 1 stop bit.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--The IEEE.std_logic_unsigned contains definitions that allow
--std_logic_vector types to be used with the + operator to instantiate a
--counter.
use IEEE.std_logic_unsigned.all;
entity GPIO_demo is
Port ( SW : in STD_LOGIC_VECTOR (7 downto 0);
BTN : in STD_LOGIC_VECTOR (4 downto 0);
CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
SSEG_CA : out STD_LOGIC_VECTOR (7 downto 0);
SSEG_AN : out STD_LOGIC_VECTOR (3 downto 0);
UART_TXD : out STD_LOGIC;
PMODBT_RST : out STD_LOGIC;
PMODBT_CTS : out STD_LOGIC);
end GPIO_demo;
architecture Behavioral of GPIO_demo is
component UART_TX_CTRL
Port(
SEND : in std_logic;
DATA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
READY : out std_logic;
UART_TX : out std_logic
);
end component;
component btn_debounce
Port(
BTN_I : in std_logic_vector(4 downto 0);
CLK : in std_logic;
BTN_O : out std_logic_vector(4 downto 0)
);
end component;
--The type definition for the UART state machine type. Here is a description of what
--occurs during each state:
-- RST_REG -- Do Nothing. This state is entered after configuration or a user reset.
-- The state is set to LD_INIT_STR.
-- LD_INIT_STR -- The Welcome String is loaded into the sendStr variable and the strIndex
-- variable is set to zero. The welcome string length is stored in the StrEnd
-- variable. The state is set to SEND_CHAR.
-- SEND_CHAR -- uartSend is set high for a single clock cycle, signaling the character
-- data at sendStr(strIndex) to be registered by the UART_TX_CTRL at the next
-- cycle. Also, strIndex is incremented (behaves as if it were post
-- incremented after reading the sendStr data). The state is set to RDY_LOW.
-- RDY_LOW -- Do nothing. Wait for the READY signal from the UART_TX_CTRL to go low,
-- indicating a send operation has begun. State is set to WAIT_RDY.
-- WAIT_RDY -- Do nothing. Wait for the READY signal from the UART_TX_CTRL to go high,
-- indicating a send operation has finished. If READY is high and strEnd =
-- StrIndex then state is set to WAIT_BTN, else if READY is high and strEnd /=
-- StrIndex then state is set to SEND_CHAR.
-- WAIT_BTN -- Do nothing. Wait for a button press on BTNU, BTNL, BTND, or BTNR. If a
-- button press is detected, set the state to LD_BTN_STR.
-- LD_BTN_STR -- The Button String is loaded into the sendStr variable and the strIndex
-- variable is set to zero. The button string length is stored in the StrEnd
-- variable. The state is set to SEND_CHAR.
type UART_STATE_TYPE is (RST_REG, LD_INIT_STR, SEND_CHAR, RDY_LOW, WAIT_RDY, WAIT_BTN, LD_BTN_STR);
--The CHAR_ARRAY type is a variable length array of 8 bit std_logic_vectors.
--Each std_logic_vector contains an ASCII value and represents a character in
--a string. The character at index 0 is meant to represent the first
--character of the string, the character at index 1 is meant to represent the
--second character of the string, and so on.
type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0);
constant TMR_CNTR_MAX : std_logic_vector(26 downto 0) := "101111101011110000100000000"; --"100,000,000 = clk cycles per second
constant TMR_VAL_MAX : std_logic_vector(3 downto 0) := "1001"; --9
constant MAX_STR_LEN : integer := 27;
constant WELCOME_STR_LEN : natural := 27;
constant BTN_STR_LEN : natural := 24;
--Welcome string definition. Note that the values stored at each index
--are the ASCII values of the indicated character.
constant WELCOME_STR : CHAR_ARRAY(0 to 26) := (X"0A", --\n
X"0D", --\r
X"4E", --N
X"45", --E
X"58", --X
X"59", --Y
X"53", --S
X"33", --3
X"20", --
X"47", --G
X"50", --P
X"49", --I
X"4F", --O
X"2F", --/
X"55", --U
X"41", --A
X"52", --R
X"54", --T
X"20", --
X"44", --D
X"45", --E
X"4D", --M
X"4F", --O
X"21", --!
X"0A", --\n
X"0A", --\n
X"0D"); --\r
--Button press string definition.
constant BTN_STR : CHAR_ARRAY(0 to 23) := (X"42", --B
X"75", --u
X"74", --t
X"74", --t
X"6F", --o
X"6E", --n
X"20", --
X"70", --p
X"72", --r
X"65", --e
X"73", --s
X"73", --s
X"20", --
X"64", --d
X"65", --e
X"74", --t
X"65", --e
X"63", --c
X"74", --t
X"65", --e
X"64", --d
X"21", --!
X"0A", --\n
X"0D"); --\r
--This is used to determine when the 7-segment display should be
--incremented
signal tmrCntr : std_logic_vector(26 downto 0) := (others => '0');
--This counter keeps track of which number is currently being displayed
--on the 7-segment.
signal tmrVal : std_logic_vector(3 downto 0) := (others => '0');
--Contains the current string being sent over uart.
signal sendStr : CHAR_ARRAY(0 to (MAX_STR_LEN - 1));
--Contains the length of the current string being sent over uart.
signal strEnd : natural;
--Contains the index of the next character to be sent over uart
--within the sendStr variable.
signal strIndex : natural;
--Used to determine when a button press has occured
signal btnReg : std_logic_vector (3 downto 0) := "0000";
signal btnDetect : std_logic;
--UART_TX_CTRL control signals
signal uartRdy : std_logic;
signal uartSend : std_logic := '0';
signal uartData : std_logic_vector (7 downto 0):= "00000000";
signal uartTX : std_logic;
--Current uart state signal
signal uartState : UART_STATE_TYPE := RST_REG;
--Debounced btn signals used to prevent single button presses
--from being interpreted as multiple button presses.
signal btnDeBnc : std_logic_vector(4 downto 0);
begin
PMODBT_RST <= '1';
PMODBT_CTS <= '0';
with BTN(4) select
LED <= SW when '0',
"00000000" when others;
with BTN(4) select
SSEG_AN <= btnDeBnc(3 downto 0) when '0',
"1111" when others;
--This process controls the counter that triggers the 7-segment
--to be incremented. It counts 100,000,000 and then resets.
timer_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((tmrCntr = TMR_CNTR_MAX) or (BTN(4) = '1')) then
tmrCntr <= (others => '0');
else
tmrCntr <= tmrCntr + 1;
end if;
end if;
end process;
--This process increments the digit being displayed on the
--7-segment display every second.
timer_inc_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (BTN(4) = '1') then
tmrVal <= (others => '0');
elsif (tmrCntr = TMR_CNTR_MAX) then
if (tmrVal = TMR_VAL_MAX) then
tmrVal <= (others => '0');
else
tmrVal <= tmrVal + 1;
end if;
end if;
end if;
end process;
--This select statement encodes the value of tmrVal to the necessary
--cathode signals to display it on the 7-segment
with tmrVal select
SSEG_CA <= "11000000" when "0000",
"11111001" when "0001",
"10100100" when "0010",
"10110000" when "0011",
"10011001" when "0100",
"10010010" when "0101",
"10000010" when "0110",
"11111000" when "0111",
"10000000" when "1000",
"10010000" when "1001",
"11111111" when others;
btn_reg_process : process (CLK)
begin
if (rising_edge(CLK)) then
btnReg <= btnDeBnc(3 downto 0);
end if;
end process;
--btnDetect goes high for a single clock cycle when a btn press is
--detected. This triggers a UART message to begin being sent.
btnDetect <= '1' when ((btnReg(0)='0' and btnDeBnc(0)='1') or
(btnReg(1)='0' and btnDeBnc(1)='1') or
(btnReg(2)='0' and btnDeBnc(2)='1') or
(btnReg(3)='0' and btnDeBnc(3)='1') ) else
'0';
--Next Uart state logic (states described above)
next_uartState_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btnDeBnc(4) = '1') then
uartState <= RST_REG;
else
case uartState is
when RST_REG =>
uartState <= LD_INIT_STR;
when LD_INIT_STR =>
uartState <= SEND_CHAR;
when SEND_CHAR =>
uartState <= RDY_LOW;
when RDY_LOW =>
uartState <= WAIT_RDY;
when WAIT_RDY =>
if (uartRdy = '1') then
if (strEnd = strIndex) then
uartState <= WAIT_BTN;
else
uartState <= SEND_CHAR;
end if;
end if;
when WAIT_BTN =>
if (btnDetect = '1') then
uartState <= LD_BTN_STR;
end if;
when LD_BTN_STR =>
uartState <= SEND_CHAR;
when others=> --should never be reached
uartState <= RST_REG;
end case;
end if ;
end if;
end process;
--Loads the sendStr and strEnd signals when a LD state is
--is reached.
string_load_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (uartState = LD_INIT_STR) then
sendStr <= WELCOME_STR;
strEnd <= WELCOME_STR_LEN;
elsif (uartState = LD_BTN_STR) then
sendStr(0 to 23) <= BTN_STR;
strEnd <= BTN_STR_LEN;
end if;
end if;
end process;
--Conrols the strIndex signal so that it contains the index
--of the next character that needs to be sent over uart
char_count_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (uartState = LD_INIT_STR or uartState = LD_BTN_STR) then
strIndex <= 0;
elsif (uartState = SEND_CHAR) then
strIndex <= strIndex + 1;
end if;
end if;
end process;
--Controls the UART_TX_CTRL signals
char_load_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (uartState = SEND_CHAR) then
uartSend <= '1';
uartData <= sendStr(strIndex);
else
uartSend <= '0';
end if;
end if;
end process;
--Debounces btn signals
Inst_btn_debounce: btn_debounce port map(
BTN_I => BTN,
CLK => CLK,
BTN_O => btnDeBnc
);
--Component used to send a byte of data over a UART line.
Inst_UART_TX_CTRL: UART_TX_CTRL port map(
SEND => uartSend,
DATA => uartData,
CLK => CLK,
READY => uartRdy,
UART_TX => uartTX
);
UART_TXD <= uartTX;
end Behavioral;
|
------------------------------------------------------------------------------
-- file with the vhdl_descriptions of the cells used in the --
-- 'ontwerppracticum'. --
------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mir_nin IS
PORT(I: INOUT STD_LOGIC;
G: OUT STD_LOGIC);
END mir_nin;
ARCHITECTURE dataflow OF mir_nin IS
BEGIN
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mir_pin IS
PORT(I: INOUT STD_LOGIC;
G: OUT STD_LOGIC);
END mir_pin;
ARCHITECTURE dataflow OF mir_pin IS
BEGIN
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mir_nout IS
PORT(O: INOUT STD_LOGIC;
I: IN STD_LOGIC;
G: IN STD_LOGIC);
END mir_nout;
ARCHITECTURE dataflow OF mir_nout IS
BEGIN
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mir_pout IS
PORT(O: INOUT STD_LOGIC;
I: IN STD_LOGIC;
G: IN STD_LOGIC);
END mir_pout;
ARCHITECTURE dataflow OF mir_pout IS
BEGIN
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ln3x3 IS
PORT(G: IN STD_LOGIC;
D: INOUT STD_LOGIC;
S: IN STD_LOGIC);
END ln3x3;
ARCHITECTURE dataflow OF ln3x3 IS
BEGIN
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY lp3x3 IS
PORT(G: IN STD_LOGIC;
D: INOUT STD_LOGIC;
S: IN STD_LOGIC);
END lp3x3;
ARCHITECTURE dataflow OF lp3x3 IS
BEGIN
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY osc10 IS
PORT(e: IN STD_LOGIC;
f: OUT STD_LOGIC;
xi: IN STD_LOGIC;
xo: INOUT STD_LOGIC := 'Z');
END osc10;
ARCHITECTURE dataflow OF osc10 IS
BEGIN
lbl1:
process(e, xo, xi)
begin
if (e /= '1') then
f <= '1';
elsif (xo = 'Z') then
f <= xi;
else
f <= NOT xo;
end if;
end process;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY iv110 IS
PORT (A: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END iv110;
ARCHITECTURE dataflow OF iv110 IS
BEGIN
Y <= NOT(A) after 1.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY no210 IS
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END no210;
ARCHITECTURE dataflow OF no210 IS
BEGIN
Y <= A NOR B after 1.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY no310 IS
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
C: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END no310;
ARCHITECTURE dataflow OF no310 IS
BEGIN
Y <= NOT(A OR B OR C) after 2.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY na210 IS
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END na210;
ARCHITECTURE dataflow OF na210 IS
BEGIN
Y <= A NAND B after 1.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY na310 IS
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
C: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END na310;
ARCHITECTURE dataflow OF na310 IS
BEGIN
Y <= NOT(A AND B AND C) after 2.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ex210 IS
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END ex210;
ARCHITECTURE dataflow OF ex210 IS
BEGIN
Y <= A XOR B after 2.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY buf40 IS
PORT (A: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END buf40;
ARCHITECTURE dataflow OF buf40 IS
BEGIN
Y <= A after 2.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tbuf10 IS
PORT (A: IN STD_LOGIC;
E: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END tbuf10;
ARCHITECTURE dataflow OF tbuf10 IS
BEGIN
Y <= A after 2.5 ns when (E = '1') else 'Z' after 2.5 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tinv10 IS
PORT (A: IN STD_LOGIC;
E: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END tinv10;
ARCHITECTURE dataflow OF tinv10 IS
BEGIN
Y <= not A after 1.5 ns when (E = '1') else 'Z' after 1.5 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mu111 IS
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
S: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END mu111;
ARCHITECTURE dataflow OF mu111 IS
BEGIN
Y <= (NOT(S) AND A) OR (S AND B) after 2.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mu210 IS
PORT (S1:IN STD_LOGIC;
S2:IN STD_LOGIC;
A: IN STD_LOGIC;
B: IN STD_LOGIC;
C: IN STD_LOGIC;
D: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END mu210;
ARCHITECTURE dataflow OF mu210 IS
BEGIN
Y <= (NOT(S1) AND NOT(S2) AND A) OR
( S1 AND NOT(S2) AND B) OR
(NOT(S1) AND S2 AND C) OR
( S1 AND S2 And D) after 4.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY de211 IS
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y0: OUT STD_LOGIC;
Y1: OUT STD_LOGIC;
Y2: OUT STD_LOGIC;
Y3: OUT STD_LOGIC);
END de211;
ARCHITECTURE dataflow OF de211 IS
BEGIN
Y0 <= NOT(A) AND NOT(B) after 4.0 ns;
Y1 <= A AND NOT(B) after 4.0 ns;
Y2 <= NOT(A) AND B after 4.0 ns;
Y3 <= A AND B after 4.0 ns;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dfn10 IS
PORT (D: IN STD_LOGIC;
CK: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END dfn10;
ARCHITECTURE dataflow OF dfn10 IS
SIGNAL Q_INT: std_logic;
BEGIN
Q <= Q_INT;
PROCESS(CK, D)
BEGIN
IF(CK'event AND CK='1') THEN
-- pragma translate_off
assert D'quiet(2.0 ns)
report "setup_violation"
severity warning;
-- pragma translate_on
Q_INT <= D after 4.0 ns;
END IF;
-- pragma translate_off
IF (D'event AND CK = '1' AND (D = Q_INT)) THEN
assert CK'quiet(1.0 ns)
report "hold_violation"
severity warning;
END IF;
-- pragma translate_on
END PROCESS;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dfr11 IS
PORT (D: IN STD_LOGIC;
R: IN STD_LOGIC;
CK: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END dfr11;
ARCHITECTURE dataflow OF dfr11 IS
SIGNAL Q_INT: std_logic;
BEGIN
Q <= Q_INT;
PROCESS(CK, D, R)
BEGIN
IF(CK'event AND CK='1') THEN
-- pragma translate_off
assert D'quiet(2.0 ns)
report "setup_violation of D"
severity warning;
-- pragma translate_on
IF (R='1') THEN
-- pragma translate_off
assert R'quiet(2.0 ns)
report "setup_violation of R"
severity warning;
-- pragma translate_on
Q_INT <= '0' after 4.0 ns;
ELSE
Q_INT <= D after 4.0 ns;
END IF;
END IF;
-- pragma translate_off
IF (D'event AND CK = '1' AND (D = Q_INT)) THEN
assert CK'quiet(1.0 ns)
report "hold_violation of D"
severity warning;
END IF;
IF (R'event AND R = '0' AND CK = '1' AND (Q_INT /= '0')) THEN
assert CK'quiet(1.0 ns)
report "hold_violation of R"
severity warning;
END IF;
-- pragma translate_on
END PROCESS;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dfa11 IS
PORT (D: IN STD_LOGIC;
R: IN STD_LOGIC;
CK: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END dfa11;
ARCHITECTURE dataflow OF dfa11 IS
SIGNAL Q_INT: std_logic;
BEGIN
Q <= Q_INT;
PROCESS(CK, D, R)
BEGIN
IF (R='1') THEN
Q_INT <= '0' after 4.0 ns;
ELSIF(CK'event AND CK='1') THEN
-- pragma translate_off
assert D'quiet(2.0 ns)
report "setup_violation of D"
severity warning;
-- pragma translate_on
Q_INT <= D after 4.0 ns;
END IF;
-- pragma translate_off
IF (D'event AND CK = '1' AND (D = Q_INT)) THEN
assert CK'quiet(1.0 ns)
report "hold_violation of D"
severity warning;
END IF;
-- pragma translate_on
END PROCESS;
END dataflow;
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Thu Dec 9 13:46:09 2021
-- Host : F210-27 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ start_rom_sim_netlist.vhdl
-- Design : start_rom
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux is
port (
\^douta\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DOADO : in STD_LOGIC_VECTOR ( 3 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
clka : in STD_LOGIC;
DOUTA : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux is
signal \douta[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 5 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[0]_INST_0_i_1_n_0\,
I1 => DOUTA(0),
I2 => sel_pipe_d1(5),
I3 => \douta[0]\(0),
I4 => sel_pipe_d1(4),
I5 => \douta[0]_0\(0),
O => \^douta\(0)
);
\douta[0]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => sel_pipe_d1(2),
I1 => sel_pipe_d1(0),
I2 => DOADO(0),
I3 => sel_pipe_d1(1),
I4 => sel_pipe_d1(3),
O => \douta[0]_INST_0_i_1_n_0\
);
\douta[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[1]_INST_0_i_1_n_0\,
I1 => \douta[1]\(0),
I2 => sel_pipe_d1(5),
I3 => \douta[1]_0\(0),
I4 => sel_pipe_d1(4),
I5 => \douta[1]_1\(0),
O => \^douta\(1)
);
\douta[1]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => sel_pipe_d1(2),
I1 => sel_pipe_d1(0),
I2 => DOADO(1),
I3 => sel_pipe_d1(1),
I4 => sel_pipe_d1(3),
O => \douta[1]_INST_0_i_1_n_0\
);
\douta[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[2]_INST_0_i_1_n_0\,
I1 => \douta[2]\(0),
I2 => sel_pipe_d1(5),
I3 => \douta[2]_0\(0),
I4 => sel_pipe_d1(4),
I5 => \douta[2]_1\(0),
O => \^douta\(2)
);
\douta[2]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => sel_pipe_d1(2),
I1 => sel_pipe_d1(0),
I2 => DOADO(2),
I3 => sel_pipe_d1(1),
I4 => sel_pipe_d1(3),
O => \douta[2]_INST_0_i_1_n_0\
);
\douta[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \douta[3]_INST_0_i_1_n_0\,
I1 => \douta[3]\(0),
I2 => sel_pipe_d1(5),
I3 => \douta[3]_0\(0),
I4 => sel_pipe_d1(4),
I5 => \douta[3]_1\(0),
O => \^douta\(3)
);
\douta[3]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => sel_pipe_d1(2),
I1 => sel_pipe_d1(0),
I2 => DOADO(3),
I3 => sel_pipe_d1(1),
I4 => sel_pipe_d1(3),
O => \douta[3]_INST_0_i_1_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(3),
Q => sel_pipe_d1(3),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(4),
Q => sel_pipe_d1(4),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(5),
Q => sel_pipe_d1(5),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(2),
Q => sel_pipe(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(3),
Q => sel_pipe(3),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(4),
Q => sel_pipe(4),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(5),
Q => sel_pipe(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF0000",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFE80000001EFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000BFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFE000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00003FFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFD0001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0005FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF001FFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFC007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE007FFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFE03FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"C1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF87FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFE3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFF3FFFFFF9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FF7FFFFFFFFFFFE3FFFFFFFFFFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FF9FFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FF7FFDF7FF77FFFFFF7FFFCFFF7FFFFFFFFD41FFF7EA17FEFFFFFF7FFFC7FFDF",
INIT_47 => X"7FFF8FFFBFBFFFFFF7FFFFFF7EFF82FFFFFFFFFFE83FFFFFFFFFEFFFFFFFDC17",
INIT_48 => X"17FE0300FFC000001FFFA00007FFC0000FFFFFFFFFFFFFFFFFFFFFFFF7FFFFFF",
INIT_49 => X"FFFC017FC0000003FFFFFE0700FFF0003E001E0000000FFFE0001FFFFFFFE060",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFE0000000FFF40000FF800007E0000000FE0001FFFFFFF",
INIT_4B => X"C0000001FFA00003FFFFFFFC0000FFC0000FF8000003FFE00000FFC00001FFFF",
INIT_4C => X"00000FC0000001FC0000FFFFFFFFFF0007F80000007FFFFFC0C00FFE00078003",
INIT_4D => X"0000007FE800001FC000003FFFFFFFFFFFFFFFFFFFFFFFC0000001FFC00001FF",
INIT_4E => X"00000FFFFFF80000FFC000F800780000003FF000007FFFFFFF80001FF80000FF",
INIT_4F => X"FFFFFFFFF80000003FF000003FE00001F80000003F80000FFFFFFFFFC000FF00",
INIT_50 => X"00000FFFFFFFF00000FF00000FE000000FF8000003F0000007FFFFFFFFFFFFFF",
INIT_51 => X"0007F00003FFFFFFFFF0001FE0000001FFFFFF00000FF8001E000F00000007FC",
INIT_52 => X"00007C000000FFFFFFFFFFFFFFFFFFFFFFFF00000007F0000007FC00003F0000",
INIT_53 => X"E00001FF00038001E0000000FE000001FFFFFFFE00003FE00001FC000001FE00",
INIT_54 => X"000000FE000000FF802007E0000000FE00001FFFFFFFFC0000FC0000003FFFFF",
INIT_55 => X"FFC01803FC00C01F8000003FC000000F8000001FFFFFFFFFFFFFFFFFFFFFFFE0",
INIT_56 => X"FFFFFFFF80001F81E01F07FFFFFC00001FE00078003C0F00F81F8000003FFFFF",
INIT_57 => X"7FFFFFFFFFFFFFFFFFFFFFFFFC0F00F81FC000001FF00200FC0F80781FC01807",
INIT_58 => X"FF003B81F01E03F801C07BFFFFFFF803C07F803E03F01FC07BF800E01EF001C0",
INIT_59 => X"C03DFDC041FF81F01F03F80F007FFFFFFFE01401F03E01C0FFFFFF801003FB80",
INIT_5A => X"07803E03F80FFE00BC03FC00780FFFFFFFFFFFFFFFFFFFFFFFFF81F01E03F001",
INIT_5B => X"807E07C0381FFFFFF007C07FF81FC007F03E03C07C01780FFFFFFFFF01F80FF0",
INIT_5C => X"FFFFFFFFFFFFFFF03E03C07C017807FFF8183FF03E03E07F01F80FFFFFFFFC07",
INIT_5D => X"780FC03F01FFFFFFFFE03F81FE01F80FC07F01FFC03F807F807F01FFFFFFFFFF",
INIT_5E => X"FE07C07C0FE07E00FFFFFFFF80FC07C0F80703FFFFFE00FC07FF03F800FE07C0",
INIT_5F => X"3FF807F00FE00FE03FFFFFFFFFFFFFFFFFFFFFFFFE07C0780F007F00FFFF0307",
INIT_60 => X"7FFFFFC03F807FE07F001FC0F80F01F00FE03FFFFFFFFC07F01FC07F01F80FE0",
INIT_61 => X"FFFFC0F80F01F00FE01FFFE060FFC0F80F81FC0FC01FFFFFFFE03F80F81F00E0",
INIT_62 => X"FFFFFFFF80FE03F80FE03F01FC07FE01FE01FC03FC07FFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"80F803FFFFFFFC07F01F03E01C0FFFFFF80FE01FFC0FC003F81F01E03E01FC07",
INIT_64 => X"007F80FFFFFFFFFFFFFFFFFFFFFFFFF81F01E03C03FC03FFF8080FF81F01F03F",
INIT_65 => X"03FF81F8007F03E03C07803F80FFFFFFFFF03FC07F01FC07E03F80FF803FC03F",
INIT_66 => X"07803F807FFF8301FF03E03E07F01F807FFFFFFF807E01E07C0381FFFFFF00FE",
INIT_67 => X"F00FE03F00FC07F01FF007F807F00FF01FFFFFFFFFFFFFFFFFFFFFFFFF03E03C",
INIT_68 => X"FFF01FC01C0F80703FFFFFE03FC03FF03F000FE07C0780F00FF01FFFFFFFFE07",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFE07C0780E00FF00FFFF0703FE07C07C0FE03F00FFFFF",
INIT_6A => X"FC0F80F01F01FE03FFFFFFFFC0FC01FC07F01F80FE03FF00FF00FE03FE03FFFF",
INIT_6B => X"FE0E03FC0F80F81FC07C01FFFFFFFC03FC0781F00E07FFFFFC07F807FE07C081",
INIT_6C => X"F01FC07FE01FE01FC07FC07FFFFFFFFFFFFFFFFFFFFFFFFC0F80F01C01FE01FF",
INIT_6D => X"3E01C0FFFFFF80FF007FC0F0103F81F01E03E03FC07FFFFFFFF81FC07F80FC03",
INIT_6E => X"FFFFFFFFFF81F01E03C03FC03FFF81C0FF81F01F03F80F007FFFFFFF007F80F0",
INIT_6F => X"07F80FFFFFFFFF03F00FF01F803F07F80FFC03FC03F00FF80FFFFFFFFFFFFFFF",
INIT_70 => X"03E07F01F00FFFFFFFF00FF01E07C0381FFFFFF03FE01FF81F0207F03E03C078",
INIT_71 => X"7F807E01FF01FFFFFFFFFFFFFFFFFFFFFFFFF03E03C07807F807FFF0381FF03E",
INIT_72 => X"FE07FC03FF03C0C0FE07C0780F00FF01FFFFFFFFE03E00FF03E00FFFFF01FF80",
INIT_73 => X"07C0780E00FF00FFFE0383FE07C07C0FC07803FFFFFFFE03FE01C0F80703FFFF",
INIT_74 => X"FFFFFF003FFFFC03FFFFE03FE00FF00FC03FE03FFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_75 => X"7FFFFFFFC07FC0381F00E07FFFFFFFFFC07FE070181FC0F80F01F00FE03FFFFF",
INIT_76 => X"07FFFFFFFFFFFFFFFFFFFFFFFFC0F80F01C00FE01FFF80703FC0F80F81FFFF80",
INIT_77 => X"0F0103F81F01E03F01FC07FFFFFFFFFFE00FFFFE007FFFFC07FE00FE01FC07FC",
INIT_78 => X"FC03FFF81E07F81F01F03FFFE00FFFFFFFF80FF80703E01C0FFFFFFFFFF80FFC",
INIT_79 => X"FFC00FFFFF80FFC03FC03F80FF80FFFFFFFFFFFFFFFFFFFFFFFFF81F01E03C03",
INIT_7A => X"FF0060FC0381FFFFFFFFFF01FF81C0607F03E03C0FE01F80FFFFFFFFFFFC00FF",
INIT_7B => X"FFFFFFFFFFFFFFFF07E03C0FC03F807FFF03C0FF83E03E0FFFF003FFFFFFFF01",
INIT_7C => X"07FFFC03F01FFFFFFFFFFF007FFFF803FFFFF01FFC01F807F01FF01FFFFFFFFF",
INIT_7D => X"0FFFFC07FFFFFC003FFFFFFFC03FC00FFF807FFFFFFFFFFFE01FF0300C0FFFFC",
INIT_7E => X"03FF001F00FE01FE03FFFFFFFFFFFFFFFFFFFFFFFFFFFC07FFF807F00FFFE070",
INIT_7F => X"FFFFFFFFFFFC03FE070381FFFF80FFFFC07E03FFFFFFFFFF8007FFFE007FFFFE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFF80FFFF007E01FFF80E03FFFF80FFFFFF801FFFFFFFF807F801FFF00F",
INIT_01 => X"7FFFFFFFFFE003FFFF800FFFFFC07FF803601F801FC07FFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFF003FFFFFFFF00FF007FFE01FFFFFFFFFFFF807FC0E0303FFFF01FFFFC03C0",
INIT_03 => X"F807F80FFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFF002C03FFF03E07FFFF01FFF",
INIT_04 => X"F00FF8180E07FFFE03FFFFC0000FFFFFFFFFFC007FFFC007FFFE000FFE000003",
INIT_05 => X"FFFE000007FFE07C0FFFFE03FFFFFC007FFFFFFFE01FE00FFFC03FFFFFFFFFFF",
INIT_06 => X"800FFFF800FFFFC001FFF000007F803F01FFFFFFFFFFFFFFFFFFFFFFFFFFFE03",
INIT_07 => X"FFFC03FC01FFF807FFFFFFFFFFFE01FF0301C0FFFFC07FFFFC0001FFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFC07FFFC00000FFF80F80FFFFC07FFFFE003FFFFF",
INIT_09 => X"1FFFF80FFFFFD0003FFFFFFFFFE007FFFF001FFFF8003FFF00000FE003E03FFF",
INIT_0A => X"FF81F01FFFF80FFFFFC00FFFFFFFFF807F803FFF00FFFFFFFFFFFFC03FE0C078",
INIT_0B => X"FFFF0007FFF00001FE006407FFFFFFFFFFFFFFFFFFFFFFFFFFF80FFFFE00001F",
INIT_0C => X"FFE01FFFFFFFFFFFF807FC1C0703FFFF01FFFFE80007FFFFFFFFF001FFFFC00F",
INIT_0D => X"FFFFFFFFFFFFFF01FFFFE00003FFF01F03FFFF01FFFFF800FFFFFFFFF00FF007",
INIT_0E => X"FC0000FFFFFFFFFE003FFFE003FFFFE000FFFE00003FC00000FFFFFFFFFFFFFF",
INIT_0F => X"E03FFFFE003FFFFFFFFE01FE00FFFC03FFFFFFFFFFFF00FF8381E07FFFE03FFF",
INIT_10 => X"C00007FE00001FFFFFFFFFFFFFFFFFFFFFFFFFFFE03FFFFC00007FFE03E03FFF",
INIT_11 => X"FFFFFFE01FF060780FFFFC07FFFF00001FFFFFFFFFC007FFFE007FFFFC001FFF",
INIT_12 => X"FFFC07FFFFC0000FFF80040FFFFC07FFFF001FFFFFFFFFC03FC01FFF807FFFFF",
INIT_13 => X"FFFFE003FFFF800FFFFFFC03FFFC0700FFE00003FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFF807F803FFF00FFFFFFFFFFFFC03FE080F01FFFF80FFFFC01E03FFFF",
INIT_15 => X"007FFFFFFFFFFFFFFFFFFFFFFFFFFF80FFFFF80E01FFF00001FFFF80FFFFF007",
INIT_16 => X"C180E03FFFF01FFFE00FC07FFFFFFFFE00FFFFE003FFFFFFC07FFF81E01FFE00",
INIT_17 => X"01C03FFC00003FFFF01FFFF800FFFFFFFFFF00FF007FFE01FFFFFFFFFFFF807F",
INIT_18 => X"FC01FFFFFFF80FFFE03C03FFC0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFFF",
INIT_19 => X"1FE00FFFC03FFFFFFFFFFFF00FF8303C07FFFE03FFFC03F80FFFFFFFFF003FFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFE03FFFFC07807FF800003FFFE03FFFF801FFFFFFFFFE0",
INIT_1B => X"C07FFF80FF01FFFFFFFFF003FFFF007FFFFFFF01FFFC03807FFE8001FFFFFFFF",
INIT_1C => X"007FFFC07FFFC00FFFFFFFFFFC03FC00FFF807FFFFFFFFFFFE01FF040F80FFFF",
INIT_1D => X"E03FFF80F00FFFFDE03FFFFFFFFFFFFFFFFFFFFFFFFFFFC07FFFF00700FFF800",
INIT_1E => X"FFFFFFFFFFFFC03FE081F01FFFF80FFFF00FE03FFFFFFFF800FFFFE007FFFFFF",
INIT_1F => X"FFFFFFFFF80FFFFF01E01FFF000007FFF80FFFFC03FFFFFFFFFF807F801FFF00",
INIT_20 => X"07FFFFFFFF807FFFFC01FFFFFFFC07FFE03E01FFFFFC07FFFFFFFFFFFFFFFFFF",
INIT_21 => X"FF007FFFFFFFFFF00FF003FFE01FFFFFFFFFFFF007FC103E03FFFF01FFFC03FC",
INIT_22 => X"3FFFFF80FFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFFC07C03FFE00000FFFF01FF",
INIT_23 => X"FE01FF800FC07FFFE03FFF007F80FFFFFFFFE00F807E00FC07FFFF80FFF807C0",
INIT_24 => X"3FFFF00F807FF807E03FFFE03FFFE01F80FFFFFFFF01FF00FFFC03FFFFFFFFEF",
INIT_25 => X"03F81FE00FC07FFFF01FFF807807FFFFF01FFFFFFFFFFFFFFFFFFFFFFFFFFFE0",
INIT_26 => X"FFFFE03FE01FFF807FFFFFFFF87FC03FF001F80FFFFC07FFF01FF01FFFFFFFF8",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFC07FFFF00F00FFF01FC07FFFC07FFFC03F01FFF",
INIT_28 => X"01FFFF80FFFE03FE03FFFFFFFF807F03FC07F80F80FE03FFE01F00FFFFFE03FF",
INIT_29 => X"FFC03F80FFFF80FFFF00FE03FFFFFFFC07FC03FFF00FFFFFFFFC0FF807FE003F",
INIT_2A => X"01F01FC07FFC07E01FFFFFC07FFFFFFFFFFFFFFFFFFFFFFFFFFF80FFFFE03E01",
INIT_2B => X"7FFE01FFFFFFFF81FF00FFC00FE03FFFF01FFFC07FC07FFFFFFFF01FE07F00FF",
INIT_2C => X"FFFFFFFFFFFFFFF01FFFF80FC03FF803F80FFFF01FFFC01FC07FFFFFFF807F80",
INIT_2D => X"F80FF80FFFFFFFFE03FC0FE01FE03E03F80FFF807C03FFFFF80FFFFFFFFFFFFF",
INIT_2E => X"FE03FFFC03F80FFFFFFFF00FF01FFFC03FFFFFFFF03FE00FF801FC07FFFE03FF",
INIT_2F => X"F01F807FFFFF01FFFFFFFFFFFFFFFFFFFFFFFFFFFE03FFFE01F807FF807F01FF",
INIT_30 => X"FFFE07FC03FF001F80FFFFC07FFF01FF01FFFFFFFF803F81F803FC07C07F01FF",
INIT_31 => X"FFFFC07FFFE01F00FFF01FE01FFFC07FFF80FF01FFFFFFFC01FE03FFF807FFFF",
INIT_32 => X"FFFFF00FF03F00FF80F80FE03FFC07F00FFFFFE03FFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"E03FFFFFFFC03FC07FFF00FFFFFFFF80FF007FE007F01FFFF80FFFE03FE03FFF",
INIT_34 => X"FC07FFFFFFFFFFFFFFFFFFFFFFFFFFF80FFFF807E01FFE03FC03FFF80FFFF01F",
INIT_35 => X"FC01FE03FFFF01FFFC03FC07FFFFFFFE01FE07E01FF01F01FC07FF00FE01FFFF",
INIT_36 => X"01FC03FF807F00FFFF01FFFE01FC07FFFFFFFC03F007FFE01FFFFFFFF80FE01F",
INIT_37 => X"FC03FC03E03F80FFF00FC03FFFFF80FFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFE",
INIT_38 => X"80FE01FFFC03FFFFFFFF01FE03FF801FC07FFFE03FFF003F80FFFFFFFFC07FC0",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFE03FFFE03F807FF01FE01FFFE03FFFC03F00FFFFFFFF",
INIT_3A => X"FC07FFF00FF01FFFFFFFF807F81F807F807C07F01FFC03F807FFFFF01FFFFFFF",
INIT_3B => X"FE03FFFC07FFF807E01FFFFFFFF01F807FFF807FFFFFFFF01FC03FF007F80FFF",
INIT_3C => X"FE03FF00FF00FFFFFE03FFFFFFFFFFFFFFFFFFFFFFFFFFFC07FFFC07F00FFC03",
INIT_3D => X"0FFFFFFFFE07F00FFE01FF01FFFF80FFFF007E03FFFFFFFF80FE03F80FF00F80",
INIT_3E => X"FFFFFFFFFF80FFFF00FE01FF807FC03FFF80FFFF01FE03FFFFFFFE01F80FFFF0",
INIT_3F => X"C07FFFFFFFF01F807F007E01F01FC07FF01FE01FFFFFC07FFFFFFFFFFFFFFFFF",
INIT_40 => X"FFC03FC07FFFFFFFE01E00FFFE01FFFFFFFF803E03FFC01FE03FFFF01FFFC007",
INIT_41 => X"03FFFFF80FFFFFFFFFFFFFFFFFFFFFFFFFFFF01FFFE03FC03FF80FF807FFF01F",
INIT_42 => X"03007FF807FC07FFFE03FFFE00D80FFFFFFFFC00F80FF01F803E03F80FFE01FC",
INIT_43 => X"03FFFC03F807FF00FF807FFE03FFFC03E00FFFFFFFFC01C03FFFC03FFFFFFFF8",
INIT_44 => X"C01601FC01A007C000001800700007FFE0000FFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_45 => X"FFFFFF80000FFF0000FFFFFFFF80000FFF01FC001FF80007FF8000001FFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFF80007F800F0000E00060003FC0007FFC02401FF",
INIT_47 => X"8003FF0000FFFC000003FFFFFFFC00003FC00000F8000003001E0000FFFC0001",
INIT_48 => X"01C000C0007F80007FF000003FFFFFFFF80001FFE0001FFFFFFFF00003FFE01F",
INIT_49 => X"001F0000006003C0001FFF80003FFFFFFFFFFFFFFFFFFFFFFFFF0000FF003E00",
INIT_4A => X"7FFC0003FFFFFFFF00007FFC07F0007FE0001FFFC000007FFFFFFF800007F800",
INIT_4B => X"FFFFFFFFFFFFFFE0001FE007C000380018000FF0000FFF800007FFFFFFFF0000",
INIT_4C => X"FFFC00000FFFFFFFF80000FFC00003E000000C00780003FFF00007FFFFFFFFFF",
INIT_4D => X"FE0001FFF00000FFFFFFFFE0001FFF80007FFFFFFFE0000FFF81FE000FFC0003",
INIT_4E => X"800F00007FFE0000FFFFFFFFFFFFFFFFFFFFFFFFFC0003FC0078000700030001",
INIT_4F => X"FFFFFC0007FFF01FC001FF80007FFFA00001FFFFFFFF80001FF800007C000001",
INIT_50 => X"FFFF80007F801F0000E00060003FC0003FFE00001FFFFFFFFF0003FFF0000FFF",
INIT_51 => X"FFFFFFF80103FF00080F8000003003E0000FFFC0001FFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"0203FFFFFFFFF001FFFE0001FFFFFFFFC000FFFE07F8003FF0000FFFFD00003F",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000FF007E0001C000C0007F80007FFE0",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFF809FBFFC07FFFFFFFFFEFFBFFFFFFF",
INIT_55 => X"FF7FFFFFFFFFFFFFFFFFFFFFFE80FFFFFFFFFFFE807FFFFFFFFFFFFFFFFF00BF",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"FFF7DFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBDF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFC7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0007FFFFFFFFFFF",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4B => X"FFFFFFFFFFF00001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000FFFFFFFFFFFFFFFFFFFFF",
INIT_4F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_50 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF00000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000007FFF",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFF000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000003FFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFF0000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFE0000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000001FFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFF80000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"0000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFF80000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000F",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFF800000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"00001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"0000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFB800000000000000000000000003BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000003FFFFF",
INIT_4B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4C => X"00000000000000000000017FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD00000000",
INIT_4E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4F => X"FFFFFFFFFFFFFFFFFF8000000000000000000000000000000FFFFFFFFFFFFFFF",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"0000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000040400",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFF000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000000000000",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_59 => X"000000000100000400000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000000000003FFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"00000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFE0000000000000000000000000000000000FFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000001000000040000",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"E00000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000000000001F",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"00020000000080000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFE000000000000000000000000000000000003FFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"0000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFF800000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000000000000000000000",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"00000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000001FFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"0000000100000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000040",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFE000000000000080000000020000000000000FFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000000001000000000400",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"F8000000000000200000000080000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000000000000000000000000000000",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFC000000000000000000000000000000000001FFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"00000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000000000000000",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFF800000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"000000000040000000100000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000000000000FFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"0000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFF800000000000008000000200000000000003FFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFF80000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"000000080000200000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFF800000000000000000000000000000000FFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"0800000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000200",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFF00000000000000080800000000000001FFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"00007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"E000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000003FFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"0000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"FFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFF",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4D => X"000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000",
INIT_4F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"C00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"0000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000007FF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFF80000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
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INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000001FFFFFFFF",
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INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
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INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
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INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
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INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0FF",
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INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF801FFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFF800FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE003FFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"E8003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFC0002FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00001FFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFF800001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4000000FFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFDE00000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"00000000001FFFFF000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000FFFFFF800000000000000000000",
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INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"000000000000000000000000000000000000000003FFFFFFFF80000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000FFFFFFFFF800000000000000000000000000000000000000000000000000",
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INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000003FFFFFFFFF800000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"FFF8000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"00000000000000000001FFFFFFFFFF0000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"00000000000000000000000000000000000000000000007FFFFFFFFFF0000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"000000000FFFFFFFFFFE00000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"000000000000000000000000000000000001FFFFFFFFFFC00000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"FFFFFFFFFC000000000000000000000000000000000000000000000000000000",
INIT_70 => X"000000000000000000000000000000000000000000000000000000000000007F",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000FFFFFFFFFFF8000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000001FFFFFFFFFFF0",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"000000000000003FFFFFFFFFFE00000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"00000000000000000000000000000000000000000FFFFFFFFFFFE00000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0001FFFFFFFFFFFC000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000003FFFFFFFFFFF8000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"FFFFF00000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000007FFFFFF",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"00000000000000000000FFFFFFFFFFFE00000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"00000000000000000000000000000000000000000000001FFFFFFFFFFFC00000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000001FFFFFFFFFFFFFFF",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000FFFFFFFFFFFE000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"FFC0000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000001FFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"000000000000000000000000000000000000000000007FFFFFFFFFFF00000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000FFFFFFFFFFFE000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000001FFFFFFFFFFFC000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"FFFFFFFF00000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000001FFF",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"000000000000000000000003FFFFFFFFFFE00000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_2_n_0\ : STD_LOGIC;
signal ena_array : STD_LOGIC_VECTOR ( 48 to 48 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_01 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_02 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_03 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_04 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_05 => X"0000000000000000000000000000001111233333333333333333333333333333",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 0) => B"0000000000000000",
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => DOADO(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena_array(48),
ENBWREN => '0',
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_2_n_0\,
I1 => addra(12),
O => ena_array(48)
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => addra(14),
I1 => ena,
I2 => addra(16),
I3 => addra(17),
I4 => addra(15),
I5 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFF000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000007FFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFC000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00001FFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFE00007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0003FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000FFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFE003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00FFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFC01FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC07FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"81FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF83FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0FFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFF1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFE0007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FF8003F800F8000000FFFFF000FFFFFFFF03C0FFF81E1FFF000000FFFFF8003F",
INIT_47 => X"FFFFF0007FC00003F8000000FF0303FFFFFFFFFFF82FFE0000001FFFFFF0381F",
INIT_48 => X"1FFF01007FC000000FFFE00003FF40000FFFFFFFFFFFFFFFFFFFFFFFF0000000",
INIT_49 => X"FFF801FFC0000003FFFFFE07007FE0007E001E0000000FFFA0001FFFFFFFE040",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFE0000001FFFA00007F000007E0000000FE0400FFFFFFF",
INIT_4B => X"C0000001FFC00003FFFFFFFC0000FFE0000FF8000001FFC000007F800001FFFF",
INIT_4C => X"00000FC0000001FC0001FFFFFFFFFF000FF80000007FFFFFC0C007FC000FC003",
INIT_4D => X"0000003FF800000FF000003FFFFFFFFFFFFFFFFFFFFFFFC0000003FF800000FE",
INIT_4E => X"00000FFFFFF800007F8001F000780000003FE000007FFFFFFF80001FFC00007F",
INIT_4F => X"FFFFFFFFF80000007FF000001FC00001F80000003F80001FFFFFFFFFC000FF00",
INIT_50 => X"00000FFFFFFFF00001FF80000FE0000007FC000001F8000007FFFFFFFFFFFFFF",
INIT_51 => X"0007F00003FFFFFFFFE0001FE0000001FFFFFF00000FF0003E000F00000007F8",
INIT_52 => X"00003E000000FFFFFFFFFFFFFFFFFFFFFFFF0000000FF8000003F800003F0000",
INIT_53 => X"E00000FE0007C001E0000000FF000001FFFFFFFE00003FF00000FC000000FF00",
INIT_54 => X"000001FE0000007F002007E0000000FE00003FFFFFFFFC0001FC0000003FFFFF",
INIT_55 => X"FFC01803FE00C03F8000001FE0000007C000001FFFFFFFFFFFFFFFFFFFFFFFE0",
INIT_56 => X"FFFFFFFF00001F81E01F07FFFFFC00001FC000F0003C0F00F81FC000003FFFFF",
INIT_57 => X"43FFFFFFFFFFFFFFFFFFFFFFFC0F00F83FC000000FE00600FC0F80F81FC01803",
INIT_58 => X"0F000781E00F03F8034047FFFFFFF807803FC07E03F0004047F0008001E00140",
INIT_59 => X"0003FE00C11F81E00F03F80780FFFFFFFFE00803F07E03E0FFFFFF800801FC00",
INIT_5A => X"0FC07E07F007FE00FC03FC01F007FFFFFFFFFFFFFFFFFFFFFFFF81F00F07E001",
INIT_5B => X"C07E0FC07C1FFFFFF007C07FF81FC007F03C01E07E01F007FFFFFFFF00F80FF8",
INIT_5C => X"FFFFFFFFFFFFFFF03E01E0FC01F807FFFC101FF03C01E07F01F00FFFFFFFF803",
INIT_5D => X"3C0F803E00FFFFFFFFE03F81FF01F807C0FE00FF801F807F007E00FFFFFFFFFF",
INIT_5E => X"FE07803C0FE03F01FFFFFFFF80FC07C1F80F83FFFFFE01FC07FF03F000FE0780",
INIT_5F => X"1FF80FF00FF00FC01FFFFFFFFFFFFFFFFFFFFFFFFE07C03C1F807F00FFFF0203",
INIT_60 => X"7FFFFFC07F00FFE07F001FC0F00781F807C01FFFFFFFFC07F01FE07F00F81FC0",
INIT_61 => X"FFFFC0F80783F00FE01FFFE040FFC0F00781FC07E03FFFFFFFE03F00783F01F0",
INIT_62 => X"FFFFFFFF80FE03FC0FE03F03F803FE00FE01FC01F803FFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"81FC07FFFFFFF803F01F07E03E0FFFFFF807F00FFC0FC003F81E00F03E01F803",
INIT_64 => X"807F007FFFFFFFFFFFFFFFFFFFFFFFF81F00F07C01FC03FFFC0C1FF81E00F03F",
INIT_65 => X"03FF81F0007F03C01E07C03F007FFFFFFFF03FC07F80FC07E07F007FC03FC03F",
INIT_66 => X"0F807F807FFF0381FF03C01E07F03F00FFFFFFFF00FE01E0FC07C1FFFFFF01FE",
INIT_67 => X"F00FF01F80FC0FE00FF807F807E01FE00FFFFFFFFFFFFFFFFFFFFFFFFF03E01E",
INIT_68 => X"FFF01FE03C1F80F83FFFFFE03FC03FF03F000FE07803C0F80FE00FFFFFFFFE07",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFE07C03C1F00FF00FFFE0703FE07803C0FE07E01FFFFF",
INIT_6A => X"FC0F00781E01FC01FFFFFFFFC0FE03FE03E00F81FC01FE00FF00FE03FC01FFFF",
INIT_6B => X"FE0607FC0F00781FC0FC03FFFFFFFC03FC0383F01F07FFFFFC07F807FE07C081",
INIT_6C => X"F03F803FC03FE01FC03F803FFFFFFFFFFFFFFFFFFFFFFFFC0F80783E01FE01FF",
INIT_6D => X"7E03E0FFFFFF81FF00FFC0F8003F81E00F03C03F803FFFFFFFF81F807FC07C01",
INIT_6E => X"FFFFFFFFFF81F00F07803FC03FFFC0C07F81E00F03F81F807FFFFFFF807F8070",
INIT_6F => X"07F007FFFFFFFF03F007F80F007F07F007F803FC03F807F007FFFFFFFFFFFFFF",
INIT_70 => X"01E07F03F00FFFFFFFE00FE01E0FC07C1FFFFFF03FE00FF81F0007F03C01E07C",
INIT_71 => X"7F807E00FE00FFFFFFFFFFFFFFFFFFFFFFFFF03E01E0F007F807FFF01C0FF03C",
INIT_72 => X"FE07FE01FF03C080FE07803C0F80FE00FFFFFFFFFFFC01FFFFE00FFFFE00FF00",
INIT_73 => X"07C03C1F00FF00FFFE0783FE07803C0FFFFC03FFFFFFFC03FC03C1F80F83FFFF",
INIT_74 => X"FFFFFF803FFFF803FFFFC01FF00FF00FC01FC01FFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_75 => X"3FFFFFFF807F80383F01F07FFFFFFF7FC03FE078001FC0F00781F01FC01FFFFF",
INIT_76 => X"03FFFFFFFFFFFFFFFFFFFFFFFFC0F80783E01FE01FFFC0F07FC0F00781FFFF80",
INIT_77 => X"0F0203F81E00F03F01F803FFFFFFFFFFE00FFFFF003FFFF803FE01FE01FC03F8",
INIT_78 => X"FC03FFF01C07F81E00F03FFFC00FFFFFFFF80FF00707E03E0FFFFFFFFFF80FFC",
INIT_79 => X"FFC00FFFFF007FC03FC03F807F007FFFFFFFFFFFFFFFFFFFFFFFF81F00F07C01",
INIT_7A => X"FE00E0FC07C0FFFFFFFFFF01FF81C0407F87C01E0FC03F007FFFFFFFFFFC01FF",
INIT_7B => X"FFFFFFFFFFFFFFFF87E01E0FC07F807FFE0380FF83C01E0FFFF803FFFFFFFF01",
INIT_7C => X"03FFFC03E00FFFFFFFFFFE007FFFF801FFFFE00FF803F807F01FE00FFFFFFFFF",
INIT_7D => X"1FFFF803FFFFFE007FFFFFFFC03FE01FFF80FFFFFFFFFFFFE03FF038180FFFF8",
INIT_7E => X"01FF801F00FC01FC01FFFFFFFFFFFFFFFFFFFFFFFFFFFC03FFF003F00FFFE078",
INIT_7F => X"FFFFFFFFFFFC03FE060181FFFF007FFF807C01FFFFFFFFFFC00FFFFC007FFFFC",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFF807FFF003E01FFF81F01FFFF007FFFFFC00FFFFFFFF807FC03FFF01F",
INIT_01 => X"3FFFFFFFFFF001FFFF001FFFFF803FF802E01FC03F803FFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFF003FFFFFFFF00FF803FFE03FFFFFFFFFFFF807FC0E0703FFFE00FFFFC0340",
INIT_03 => X"F807F007FFFFFFFFFFFFFFFFFFFFFFFFFFF00FFFF005C03FFF03E03FFFE00FFF",
INIT_04 => X"F00FF8180E07FFFC01FFFFC00007FFFFFFFFFC00FFFFE003FFFE0007FF000003",
INIT_05 => X"FFFE000007FFE07C0FFFFC01FFFFF800FFFFFFFFE01FF007FFC07FFFFFFFFFFF",
INIT_06 => X"801FFFF801FFFFC000FFE000007F807E00FFFFFFFFFFFFFFFFFFFFFFFFFFFE01",
INIT_07 => X"FFFC03FE00FFF80FFFFFFFFFFFFE01FF0303C0FFFF803FFFF80000FFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFC03FFFE00000FFFC0780FFFF803FFFFF001FFFFF",
INIT_09 => X"1FFFF007FFFFF0001FFFFFFFFFC003FFFF003FFFF8001FFE00000FF007C01FFF",
INIT_0A => X"FF00F01FFFF007FFFFC00FFFFFFFFF803FC01FFF01FFFFFFFFFFFFC03FE0E038",
INIT_0B => X"FFFF0003FFE00001FF005803FFFFFFFFFFFFFFFFFFFFFFFFFFF807FFFC00001F",
INIT_0C => X"FFE03FFFFFFFFFFFF807FC180F03FFFE00FFFFF80003FFFFFFFFF801FFFF8007",
INIT_0D => X"FFFFFFFFFFFFFF00FFFFC00003FFE03F03FFFE00FFFFF801FFFFFFFFF007F803",
INIT_0E => X"F800007FFFFFFFFF003FFFF003FFFFE0007FFF00003FE000007FFFFFFFFFFFFF",
INIT_0F => X"C01FFFFC007FFFFFFFFE00FF007FFC07FFFFFFFFFFFF00FF8381E07FFFC01FFF",
INIT_10 => X"E00007FC00000FFFFFFFFFFFFFFFFFFFFFFFFFFFE01FFFFE00007FFE07E07FFF",
INIT_11 => X"FFFFFFE01FF0607C0FFFF803FFFF00000FFFFFFFFF800FFFFE007FFFFC000FFF",
INIT_12 => X"FFFC03FFFFC0000FFF80FC07FFF803FFFF800FFFFFFFFFC01FE00FFF80FFFFFF",
INIT_13 => X"FFFFF001FFFF001FFFFFFC01FFF80700FFE00001FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFF803FC01FFF01FFFFFFFFFFFFC03FE040701FFFF007FFF801201FFFF",
INIT_15 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFF807FFFF00E01FFF00000FFFF007FFFF007",
INIT_16 => X"C001E03FFFE00FFFF007803FFFFFFFFE007FFFE007FFFFFF803FFF81E01FFE00",
INIT_17 => X"01C03FFE00003FFFE00FFFFC00FFFFFFFFFF00FF803FFE03FFFFFFFFFFFF807F",
INIT_18 => X"F800FFFFFFF007FFE01C03FFE00007FFFFFFFFFFFFFFFFFFFFFFFFFFF00FFFFF",
INIT_19 => X"1FF007FFC07FFFFFFFFFFFF00FF8103C07FFFC01FFFC01F007FFFFFFFF803FFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFE01FFFFC03807FFC00003FFFC01FFFF803FFFFFFFFFE0",
INIT_1B => X"803FFF00FE00FFFFFFFFF007FFFF007FFFFFFE00FFF807807FFF8000FFFFFFFF",
INIT_1C => X"007FFF803FFFE007FFFFFFFFFC03FE01FFF80FFFFFFFFFFFFE01FF000F80FFFF",
INIT_1D => X"C01FFF80F00FFFFE201FFFFFFFFFFFFFFFFFFFFFFFFFFFC03FFFF80F00FFF000",
INIT_1E => X"FFFFFFFFFFFFC03FE000F01FFFF007FFF01FC01FFFFFFFFC01FFFFC00FFFFFFF",
INIT_1F => X"FFFFFFFFF807FFFE01E01FFE00000FFFF007FFFC03FFFFFFFFFF807FC03FFF01",
INIT_20 => X"03FFFFFFFF007FFFFC03FFFFFFF803FFE03E01FFFFF803FFFFFFFFFFFFFFFFFF",
INIT_21 => X"FF007FFFFFFFFFF00FF807FFE03FFFFFFFFFFFF80FFC103E03FFFE00FFFC03F8",
INIT_22 => X"3FFFFF007FFFFFFFFFFFFFFFFFFFFFFFFFFF00FFFFC07C03FFE00001FFFE00FF",
INIT_23 => X"FF01FF800FC07FFFC01FFF80FF007FFFFFFFE00FFFFF00FFFFFFFF007FFC03C0",
INIT_24 => X"1FFFF807807FF807E01FFFC01FFFC00FFFFFFFFFFF01FE00FFFC07FFFFFFFFF5",
INIT_25 => X"01F00FC01FC0FFFFE00FFF00F807FFFFE00FFFFFFFFFFFFFFFFFFFFFFFFFFFE0",
INIT_26 => X"FFFFE03FC01FFF80FFFFFFFFE83FC03FF000F80FFFF803FFE01FE00FFFFFFFFC",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFC03FFFE01F00FFF00FC07FFF803FFFC03F03FFF",
INIT_28 => X"01FFFF007FFC03FC01FFFFFFFF007E01FC07F81FFFFC01FFF01F00FFFFFC01FF",
INIT_29 => X"FFE01FC0FFFF007FFF007E07FFFFFFF807F803FFF01FFFFFFFF807F803FE003F",
INIT_2A => X"03F03F803FFC07E01FFFFF803FFFFFFFFFFFFFFFFFFFFFFFFFFF807FFFE03E01",
INIT_2B => X"7FFE03FFFFFFFF00FF007FC00FE03FFFE00FFFC03F803FFFFFFFF01FC03F007F",
INIT_2C => X"FFFFFFFFFFFFFFF00FFFF80FC03FFC07F80FFFE00FFFE01FC0FFFFFFFF00FF00",
INIT_2D => X"F807F007FFFFFFFE01F807E01FE07E07F007FF00FC03FFFFF007FFFFFFFFFFFF",
INIT_2E => X"FC01FFF807F81FFFFFFFE00FE01FFFC07FFFFFFFE01FE01FF800FC07FFFC01FF",
INIT_2F => X"F01F807FFFFE00FFFFFFFFFFFFFFFFFFFFFFFFFFFE01FFFF00F807FF00FF01FF",
INIT_30 => X"FFFC07FC03FF003F80FFFF803FFF01FE00FFFFFFFF807F00FC03FC0FC0FE00FF",
INIT_31 => X"FFFFC03FFFE03F00FFF01FC03FFF803FFF007F03FFFFFFFE01FE01FFF80FFFFF",
INIT_32 => X"FFFFF00FE01F80FF81F81FC01FFC07F00FFFFFC01FFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"E07FFFFFFFC03FC03FFF01FFFFFFFFC0FF807FE00FF01FFFF007FFC03FC01FFF",
INIT_34 => X"F803FFFFFFFFFFFFFFFFFFFFFFFFFFF807FFF807E01FFE03F807FFF007FFE00F",
INIT_35 => X"FC00FE03FFFE00FFF803F803FFFFFFFE01FC03F00FF03F03F803FF807E01FFFF",
INIT_36 => X"01FC03FF807F807FFE00FFFE03FC0FFFFFFFFC07F00FFFE03FFFFFFFF80FF01F",
INIT_37 => X"7E01FC07E07F007FE01FC03FFFFF007FFFFFFFFFFFFFFFFFFFFFFFFFFF00FFFF",
INIT_38 => X"007E01FFFC07FFFFFFFF01FC01FF803FC07FFFC01FFF807F007FFFFFFFC07F80",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFE01FFFC01F807FF01FF01FFFC01FFF807F81FFFFFFFF",
INIT_3A => X"F803FFF00FE00FFFFFFFF807F80FC03F80FC0FE00FFC03F807FFFFE00FFFFFFF",
INIT_3B => X"FE03FFF803FFF00FF03FFFFFFFE00FC07FFF80FFFFFFFFF03FC07FF007F80FFF",
INIT_3C => X"FC01FF80FF00FFFFFC01FFFFFFFFFFFFFFFFFFFFFFFFFFFC03FFFC07F00FFE03",
INIT_3D => X"1FFFFFFFFC07F00FFE00FF01FFFF007FFF00FC01FFFFFFFF80FF01F80FF01F81",
INIT_3E => X"FFFFFFFFFF807FFF01FE01FFC03FC03FFF007FFE00FC07FFFFFFFE01F007FFF0",
INIT_3F => X"803FFFFFFFE00FC03F80FC03F03F803FE00FE01FFFFF803FFFFFFFFFFFFFFFFF",
INIT_40 => X"FFE03FC0FFFFFFFFE03E01FFFE03FFFFFFFFC07C03FFC03FE03FFFE00FFFE00F",
INIT_41 => X"03FFFFF007FFFFFFFFFFFFFFFFFFFFFFFFFFF00FFFC01FC03FF007F807FFE00F",
INIT_42 => X"07803FF807FC07FFFC01FFFE00B007FFFFFFFE01F807F01F807E07F007FE03FC",
INIT_43 => X"01FFFC07F807FF01FF80FFFC01FFFC01F01FFFFFFFF803C07FFFC07FFFFFFFF8",
INIT_44 => X"C00A00FE01400FC000000C00780003FFE0000FFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_45 => X"FFFFFF802007FF00007FFFFFFF00400FFF00F8001FF80007FFC000001FFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFF80007F800F0000600070003FC0007FF803803FF",
INIT_47 => X"8003FF0000FFF8000003FFFFFFF800001FE00001F8000001801F00007FFC0001",
INIT_48 => X"00C000E0007F80007FF800007FFFFFFFF00001FFE0000FFFFFFFF00001FFE03F",
INIT_49 => X"003F0000003001E0000FFF80003FFFFFFFFFFFFFFFFFFFFFFFFF0000FF003E00",
INIT_4A => X"3FFC0001FFFFFFFE00007FFC07F0007FE0001FFF8000007FFFFFFF800003FC00",
INIT_4B => X"FFFFFFFFFFFFFFE0001FE003C00018001C000FF0000FFF80000FFFFFFFFF0000",
INIT_4C => X"FFF800000FFFFFFFF000007FC00007E0000006007C0001FFF00007FFFFFFFFFF",
INIT_4D => X"FE0001FFF00001FFFFFFFFF0001FFF80003FFFFFFFF0001FFF81FE000FFC0003",
INIT_4E => X"C01F80003FFE0000FFFFFFFFFFFFFFFFFFFFFFFFFC0003FC00F8000300038001",
INIT_4F => X"FFFFFE0003FFF03FC001FF80007FFFE00001FFFFFFFF80000FF80000FC000000",
INIT_50 => X"FFFF80007F801F0000600070003FC0003FFF00003FFFFFFFFE0007FFF00007FF",
INIT_51 => X"FFFFFFF80001FF80181F8000001801F00007FFC0001FFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"0007FFFFFFFFE001FFFE0000FFFFFFFFE000FFFE07F8003FF0000FFFFF00003F",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000FF007E0000C000E0007F80007FFF0",
INIT_54 => X"FFBEFEFFFBFFFFFEFFFFF9FFFBFFFFFFFF00FFFFF802FFFFFFFFFBFFFFFFFEFF",
INIT_55 => X"FFFFFFFDFFFEFFFF7EFFFFFFFF807F7FFFFFFFFF803FFFFFFFDFFFFFFFFE00FF",
INIT_56 => X"FFFFC9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFF",
INIT_57 => X"FFF9BFFFFFFFFFFFFFFFFFFB3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDBF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFC7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0007FFFFFFFFFFF",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4B => X"FFFFFFFFFFF00001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000FFFFFFFFFFFFFFFFFFFFF",
INIT_4F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_50 => X"0000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF00000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000007FFF",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFF000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000007FFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFF0000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFE0000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000001FFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFF80000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000003FFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"0000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFF80000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000F",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"00001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"0000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFF800000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000003FFFFF",
INIT_4B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4C => X"0000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000",
INIT_4E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4F => X"FFFFFFFFFFFFFFFFFF8000000000000000000000000000000FFFFFFFFFFFFFFF",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"0000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000000000020800",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFF000000000000004001000000000000007FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000020000800000000000",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_59 => X"000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFC0000000000000400000400000000000007FFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"00000400000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000010",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFE0000000000000400000040000000000000FFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"E00000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000000000001F",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"00000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFE000000000000000000000000000000000003FFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"0000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFF800000000000020000000020000000000000FFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000000000000000000000",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"00000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000000000000003FFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"0000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFE000000000000000000000000000000000000FFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000000000000000000000",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"F8000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFC000000000000000000000000000000000001FFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"00100000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000000001000000",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFF800000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000000000000FFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"0000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFC00000000000000000000000000000000007FFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000008000000800",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFF80000000000000800000200000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000000080000080000000000000",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFF800000000000004000100000000000000FFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"0000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFF80000000000000063000000000000001FFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"00007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"E000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000003FFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"0000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"FFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFF",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4D => X"000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000",
INIT_4F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"C00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"0000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFFFFFFFFFFFE00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFF800000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000007FFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFC00000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000007FF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFF80000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000001FFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFF00000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFC0000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000001FFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFF8000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000FFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"00000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFF80000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000003FFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFC000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000007FFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFE00003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8003FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4D => X"FFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"FE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9FFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFE1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFF07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE07FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80FF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFE00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00FFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFF001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC001FFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"F0001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFF80001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000FFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFF000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000007FFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFE000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
ENA : out STD_LOGIC;
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
\^ena\ : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \^ena_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
ENA <= \^ena_1\;
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"003FFF8000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"007FFE0FFF8FFFFFFF80001FFF80000000FE410007E61801FFFFFF00001FFFC0",
INIT_47 => X"80003FFF803FFFFC0FFFFFFF81FC820000000000183001FFFFFFF000000FE418",
INIT_48 => X"1001030000000000100060000400C0000000000000000000000000000FFFFFFF",
INIT_49 => X"0000010000000002000000050000100000001000000000006000100000000060",
INIT_4A => X"0000000000000000000000000000008000000800000000000000204010000000",
INIT_4B => X"0000000000000002000000000000002000080000000200200000804000000000",
INIT_4C => X"00000000000000040001000000000100000000000040000000C0000200000002",
INIT_4D => X"0000004008000010000000000000000000000000000000000000000040000001",
INIT_4E => X"0000080000000000804000000040000000001000004000000000001004000080",
INIT_4F => X"0000000000000000001000000020000000000000008000000000000040000000",
INIT_50 => X"0000080000000000010080000000000008000000020000000000000000000000",
INIT_51 => X"0000100002000000001000100000000100000000000008000000080000000004",
INIT_52 => X"0000400000000000000000000000000000000000000000000000040000000000",
INIT_53 => X"0000000100000001000000000100000100000000000020100001000000010000",
INIT_54 => X"0000000000000000802000000000000200000000000000000100000000200000",
INIT_55 => X"000018000200C000000000200000000800000000000000000000000000000000",
INIT_56 => X"0000000000000001E01F0400000000000020000800200F00F800000000200000",
INIT_57 => X"7C0000000000000000000000000F00F80040000000100600000F807800401804",
INIT_58 => X"F1003C000010000801407C00000000004040400200001FC07C0800A01F100140",
INIT_59 => X"403E03C0C1E00010100008000000000000000C02000200208000000014020780",
INIT_5A => X"0000400008080000C00000008800000000000000000000000000001010001001",
INIT_5B => X"0040004004100000000000400800000000000200000108080000000001000808",
INIT_5C => X"0000000000000000020200000180000000002000020200010000000000000404",
INIT_5D => X"4000000101000000000000810100000800010100400000008041000000000000",
INIT_5E => X"0000404000200100000000008004000008008200000001040001000800000000",
INIT_5F => X"2008000000000020000000000000000000000000000040400080400000000100",
INIT_60 => X"4000000000808020010000000008000008202000000000001000204000000020",
INIT_61 => X"0000000808001000000000002080000808000408002000000000208080010010",
INIT_62 => X"0000000000020004080020000404000100000002040000000000000000000000",
INIT_63 => X"8104040000000404001000200208000000081000040000000000010000000404",
INIT_64 => X"8000800000000000000000000000000001010000020000000404000001010000",
INIT_65 => X"0200800800000000200000008080000000002040008000040000808000000000",
INIT_66 => X"0000400000008200000020200010008080000000008000000400410000000100",
INIT_67 => X"0000102080800010100800000000001000000000000000000000000000002020",
INIT_68 => X"0010000000008008200000000000001001000000000400080810100000000004",
INIT_69 => X"0000000000000000000000040400100000000000400000040400020000100000",
INIT_6A => X"0000008001010202000000000082000204000000020201000000020202000000",
INIT_6B => X"0200040000808000400000000000000004040010010400000000000002000080",
INIT_6C => X"0000404020000000400040000000000000000000000000000080800200000000",
INIT_6D => X"0200208000000000000040080000000010002020404000000000100040408002",
INIT_6E => X"0000000000001010004000000000010080001010000800000000000000008000",
INIT_6F => X"0408080000000002000008108041040808040000000008080000000000000000",
INIT_70 => X"0200010010000000001000001000400410000000200010080102000000020004",
INIT_71 => X"0000000101000000000000000000000000000002020008000000000020000002",
INIT_72 => X"00040002010000C0000000400000810100000000000001000000000001010080",
INIT_73 => X"0040400100000000000482000040400000000200000002020200000800820000",
INIT_74 => X"0000008000000402000020201000000000202000000000000000000000000000",
INIT_75 => X"40000000004040000100104000003F8040002008080000000800000020200000",
INIT_76 => X"0000000000000000000000000000080800000000000040100000080800000080",
INIT_77 => X"0103000000010001000404000000000000080001004000040400010000040404",
INIT_78 => X"0000000800000001010000000000000000080808000020020800000000080804",
INIT_79 => X"0000000000808000200000800080000000000000000000000000000101000002",
INIT_7A => X"0100008400400000000001010080000000000020082020808000000000040100",
INIT_7B => X"0000000000000000042020084000000000004000802020080008020000000101",
INIT_7C => X"0400000010100000000001004000080200001010000200001010100000000000",
INIT_7D => X"1000040400000000000000000020201000800000000000002000100000000000",
INIT_7E => X"0200002000020002000000000000000000000000000004040008040000002008",
INIT_7F => X"0000000000040002010080000000800040420200000000004000000000000002",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena_1\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000080800000400000000102000080800000000000000000040402001000",
INIT_01 => X"4000000000000000008010000040400803000040004000000000000000000000",
INIT_02 => X"0010000000000000808040020000000000000080004020500000001000040340",
INIT_03 => X"0004080000000000000000000000000000101000100300000002000000101000",
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INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena_1\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => addra(17),
I1 => addra(16),
I2 => \^ena\,
O => \^ena_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
ENA : out STD_LOGIC;
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
\^ena\ : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \^ena_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
ENA <= \^ena_1\;
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_62 => X"FFF0000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000007FFFFFF",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"000000000000000000000000000000000001FFFFFFFFFFC00000000000000000",
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INIT_6F => X"FFFFFFFFF8000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"00000000000000000000000007FFFFFFFFFF0000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000001FFFFFFFFFFF0",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"000000000000003FFFFFFFFFFE00000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"000000000000000000000000000000000000000007FFFFFFFFFFC00000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000FFFFFFFFFFF8000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000001FFFFFFFFFFF0000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena_1\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"000000000000000000007FFFFFFFFFFC00000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000003FFFFFFFFFFE0000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"FFFFFFFFFFC00000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000007",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000000000000000000000000001FFFFFFFFFFF000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_63 => X"FFFFFFFFF0000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000003FFFFFFFFFFFFF000000007FFFFFFFFFFFFE0",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"FFFC000000007FFFFFFFFFFFFC00000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000007FFFFFFFFF",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"00000000000000001FFFFFFFFFFFFF800000000FFFFFFFFFFFFFC00000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000007FFFFFFFFFFFFC000000001FFFFFFFFFFFFF0000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"FFFFF00000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"000000000000000000000000000000001FFFFFFFFFFFFF8000000003FFFFFFFF",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"FFFFFFFFF0000000007FFFFFFFFFFFFE00000000000000000000000000000000",
INIT_79 => X"000000000000000000000000000000000000000000000000000000000003FFFF",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"00000000000000000000007FFFFFFFFFFFFE000000000FFFFFFFFFFFFFC00000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"00000000FFFFFFFFFFFFF8000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000FFFFFFFFFFFFF80",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena_1\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(17),
I1 => addra(16),
I2 => \^ena\,
O => \^ena_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
ENA : out STD_LOGIC;
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
\^ena\ : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \^ena_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
ENA <= \^ena_1\;
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"000000000001FFFFFFFFFFFFF0000000001FFFFFFFFFFFFF0000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"FFFFFFFFFFE00000000000000000000000000000000000000000000000000000",
INIT_03 => X"000000000000000000000000000000000000003FFFFFFFFFFFFE0000000003FF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"07FFFFFFFFFFFFC0000000007FFFFFFFFFFFFC00000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"8000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000FFFFFFFFFFFFFC000000001FFFFFFFFFFFFF",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"FFFF8000000003FFFFFFFFFFFFF0000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000001FFFFFFFFF",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"000000000000000003FFFFFFFFFFFFF0000000007FFFFFFFFFFFFE0000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"000FFFFFFFFFFFFF800000000000000000000000000000000000000000000000",
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INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"000000000000000000000001FFFFFFFFFFFFF800000003FFFFFFFFFFFFF00000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3C => X"00000000000000000000000000000000000000000000000000000000FFFFFFFF",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"000000000000000000000000007FFFFFFFFFFC00000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000007FFFFFFFFFFC0000000000000000000000000",
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INIT_5F => X"F800000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"000000000000000000000000000000000000000000000000000000FFFFFFFFFF",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"00000000000000001FFFFFFFFFFF000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"00000000000000000000000000000000000000000003FFFFFFFFFFE000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000007FFFFFFFFFFC0000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"000000000000000000000000000000000FFFFFFFFFFF80000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"FFFFFFF000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"000000000000000000000000000000000000000000000000000000000001FFFF",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"00000000000000000000003FFFFFFFFFFE000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"00000000000000000000000000000000000000000000000007FFFFFFFFFFC000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"000000000000FFFFFFFFFFF80000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"000000000000000000000000000000000000001FFFFFFFFFFF00000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"03FFFFFFFFFFE000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"00000000000000000000000000007FFFFFFFFFFC000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"FF80000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000FFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena_1\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena_1\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(16),
I1 => addra(17),
I2 => \^ena\,
O => \^ena_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4C => X"FFFFF03FFFFFFE03FFFE0000000000FFF007FFFFFF8000003F3FF801FFF83FFC",
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INIT_77 => X"F0FCFC07E1FE0FC0FE03F800000000001FF00000FF800003F801FE01FE03F803",
INIT_78 => X"03FC0007E3F807E0FE0FC0003FF000000007F007F8FC1FC1F00000000007F003",
INIT_79 => X"003FF000007F003FC03FC07F807F80000000000000000000000007E0FE0FC3FC",
INIT_7A => X"00FF1F03F83F0000000000FE007E3FBF80FC3FC1F01FC07F000000000003FE00",
INIT_7B => X"0000000000000000F81FC1F03FC07F8001FC3F007C1FC1F00007FC00000000FE",
INIT_7C => X"F80003FC0FE00000000000FF800007FC00000FE007FC07F80FE00FF000000000",
INIT_7D => X"E00003F8000001FF800000003FC01FE0007F0000000000001FE00FC7F7F00007",
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INIT_7F => X"000000000003FC01F8FE7E0000FF00003F81FC00000000003FF00003FF800001",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"000000007F0000FF81FE0007F0FC00007F0000007FF000000007F803FC000FE0",
INIT_01 => X"80000000000FFE00007FE000003F8007FC1FE03FC03FC0000000000000000000",
INIT_02 => X"000FFC00000000FF007F8001FC0000000000007F803F1F8FC0001FE00003FCBF",
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INIT_04 => X"0FF007E7F1F80003FC00003FFFF00000000003FF80001FFC0001FFF000FFFFFC",
INIT_05 => X"0001FFFFF8001F83F00001FC000003FF000000001FE00FF0003F800000000000",
INIT_06 => X"7FE00007FF00003FFE000FFFFF807F80FF0000000000000000000000000001FC",
INIT_07 => X"0003FC01FE0007F0000000000001FE00FCFE3F00007F800003FFFE0000000000",
INIT_08 => X"0000000000000000000000003F80001FFFFF0003F87F00003F800000FFC00000",
INIT_09 => X"E0000FF000000FFFC0000000001FF80000FFC00007FFC000FFFFF00FF81FE000",
INIT_0A => X"007E0FE00007F000003FF0000000007FC03FC000FE0000000000003FC01F1FC7",
INIT_0B => X"0000FFF8000FFFFE01FF83FC0000000000000000000000000007F00001FFFFE0",
INIT_0C => X"001FC0000000000007F803E7F0FC0001FE000007FFF80000000007FE00003FF0",
INIT_0D => X"00000000000000FE00001FFFFC001FC0FC0000FE000007FE000000000FF807F8",
INIT_0E => X"03FFFF0000000001FFC0000FFC00001FFF0000FFFFC01FFFFF80000000000000",
INIT_0F => X"1FC00001FF8000000001FF00FF0003F8000000000000FF007C7E1F80003FC000",
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INIT_11 => X"0000001FE00F9F87F00007F80000FFFFE0000000003FF00001FF800003FFE000",
INIT_12 => X"0003F800003FFFF0007F03F00003F800007FF0000000003FE01FE0007F000000",
INIT_13 => X"00000FFC00007FE0000003FC0003F8FF001FFFFE000000000000000000000000",
INIT_14 => X"0000000007FC03FC000FE0000000000003FC01FBF0FE0000FF00007FE9FC0000",
INIT_15 => X"FFC0000000000000000000000000007F000007F1FE000FFFFF00007F00000FF8",
INIT_16 => X"3F7E1FC0001FE0000FF03F8000000001FF80001FF80000003F80007E1FE001FF",
INIT_17 => X"FE3FC001FFFFC0000FE00003FF0000000000FF007F8001FC0000000000007F80",
INIT_18 => X"03FF00000007F0001FC3FC001FFFF8000000000000000000000000000FE00000",
INIT_19 => X"E00FF0003F8000000000000FF007CFC3F80003FC0003FC07F0000000007FC000",
INIT_1A => X"00000000000000000001FC00003FC7F8003FFFFC0001FC00007FC0000000001F",
INIT_1B => X"7F80007F00FE000000000FF80000FF80000000FE0003F87F80007FFF00000000",
INIT_1C => X"FF80003F80001FF00000000003FC01FE0007F0000000000001FE00FBF07F0000",
INIT_1D => X"1FC0007F0FF00000DFE0000000000000000000000000003F800007F0FF0007FF",
INIT_1E => X"0000000000003FC01F7E0FE0000FF0000FE01FC000000003FE00001FF0000000",
INIT_1F => X"0000000007F00001FE1FE001FFFFF00007F00003FC00000000007F803FC000FE",
INIT_20 => X"F8000000007F800003FC00000003F8001FC1FE000003FC000000000000000000",
INIT_21 => X"00FF80000000000FF007F8001FC000000000000FF803EFC1FC0001FE0003FC03",
INIT_22 => X"C000007F8000000000000000000000000000FE00003F83FC001FFFFE0000FE00",
INIT_23 => X"01FE007FF03F80003FC0007F807F000000001FF00000FF000000007F0003F83F",
INIT_24 => X"C00007F07F8007F81FC0001FC0001FE00000000000FE00FF0003F80000000000",
INIT_25 => X"FC07E01FE03F00000FE000FF07F800000FF0000000000000000000000000001F",
INIT_26 => X"00001FC01FE0007F0000000007803FC00FFE07F00007F8000FE00FE000000003",
INIT_27 => X"00000000000000000000000003F80000FE0FF000FE03F80003F80003FC0FE000",
INIT_28 => X"FE0000FF0003FC01FC000000007F80FC03F807E00001FC001FE0FF000001FE00",
INIT_29 => X"001FC07F00007F0000FF01FC00000007F803FC000FE000000007F007F801FFC0",
INIT_2A => X"FC0FE03F8003F81FE000003FC0000000000000000000000000007F00001FC1FE",
INIT_2B => X"8001FC000000007E00FF003FF01FC0001FE0003FC03F800000000FE01F80FF00",
INIT_2C => X"000000000000000FE00007F03FC003F807F0000FE0001FE03F800000007F807F",
INIT_2D => X"07F807F000000001FC03F01FE01F81FC07F0007F03FC000007F8000000000000",
INIT_2E => X"01FC0003FC07F00000000FF01FE0003F800000000FE01FE007FE03F80003FC00",
INIT_2F => X"0FE07F800000FF0000000000000000000000000001FC0000FE07F8007F00FE00",
INIT_30 => X"0001F803FC00FFC07F00007F8000FE00FE000000007F807E03FC03F03F80FE00",
INIT_31 => X"00003F80001FC0FF000FE01FC0003F8000FF80FE00000001FE01FE0007F00000",
INIT_32 => X"00000FF00FC07F007E07F01FC003F80FF000001FE00000000000000000000000",
INIT_33 => X"1FC00000003FC03F8000FE000000003F007F801FF80FE0000FF0003FC01FC000",
INIT_34 => X"03FC0000000000000000000000000007F00007F81FE001FC03F80007F0001FE0",
INIT_35 => X"03FE01FC0001FE0003FC03F800000001FE03F80FF00FC0FE03F8007F81FE0000",
INIT_36 => X"FE03FC007F807F0000FE0001FC03F800000003F80FF0001FC000000007F00FE0",
INIT_37 => X"01FE03F81FC07F001FE03FC000007F8000000000000000000000000000FE0000",
INIT_38 => X"FF01FE0003F800000000FE01FE007FC03F80003FC0007F807F000000003F807F",
INIT_39 => X"000000000000000000001FC0001FC07F800FE00FE0001FC0007F807F00000000",
INIT_3A => X"07F8000FF00FE000000007F807E03FC07F03F80FE003FC07F800000FF0000000",
INIT_3B => X"01FC0003F80007F00FE00000000FF03F80007F000000000FC03F800FF807F000",
INIT_3C => X"01FC007F00FF000001FE0000000000000000000000000003F80003F80FF001FC",
INIT_3D => X"E000000003F80FF001FF00FE0000FF0000FF01FC000000007F01FC07F00FE07F",
INIT_3E => X"00000000007F0000FF01FE003FC03FC0007F0000FE01FC00000001FE07F0000F",
INIT_3F => X"3F800000001FE03F80FF01FC0FE03F800FE01FE000003FC00000000000000000",
INIT_40 => X"001FC03F800000001FC1FE0001FC000000003F81FC003FC01FC0001FE0001FF0",
INIT_41 => X"FC000007F8000000000000000000000000000FE0001FE03FC007F007F8000FE0",
INIT_42 => X"F87F8007F803F80003FC0001FF07F000000001FE07F00FE07F81FC07F001FC03",
INIT_43 => X"FC0003F807F800FE007F0001FC0003FC0FF000000003FC3FC0003F8000000007",
INIT_44 => X"3FE1FE01FE1FF03FFFFFE3FF87FFF8001FFFF000000000000000000000000001",
INIT_45 => X"0000007FFFF000FFFF800000007FFFF000FF07FFE007FFF8003FFFFFE0000000",
INIT_46 => X"00000000000000000000000007FFF807FF0FFFF9FFF8FFFC03FFF8007FC7FE00",
INIT_47 => X"7FFC00FFFF0003FFFFFC00000007FFFFC03FFFFE07FFFFFC7FE0FFFF0003FFFE",
INIT_48 => X"FF3FFF1FFF807FFF8007FFFFC000000007FFFE001FFFF00000000FFFFC001FC0",
INIT_49 => X"FFC0FFFFFF8FFC1FFFE0007FFFC0000000000000000000000000FFFF00FFC1FF",
INIT_4A => X"8003FFFE00000000FFFF8003F80FFF801FFFE0007FFFFF800000007FFFF803FF",
INIT_4B => X"000000000000001FFFE01FF83FFFE7FFE3FFF00FFFF0007FFFF800000000FFFF",
INIT_4C => X"0003FFFFF000000007FFFF003FFFF81FFFFFF1FF83FFFC000FFFF80000000000",
INIT_4D => X"01FFFE000FFFFF000000000FFFE0007FFFC00000001FFFE0007E01FFF003FFFC",
INIT_4E => X"3FF07FFF8001FFFF00000000000000000000000003FFFC03FF07FFFCFFFC7FFE",
INIT_4F => X"000001FFF8000FC03FFE007FFF80001FFFFE000000007FFFE007FFFF03FFFFFE",
INIT_50 => X"00007FFF807FE0FFFF9FFF8FFFC03FFFC000FFFFE000000000FFFC000FFFF800",
INIT_51 => X"00000007FFFC007FF7E07FFFFFC7FE0FFFF0003FFFE000000000000000000000",
INIT_52 => X"FFFC000000000FFE0001FFFF000000001FFE0001F807FFC00FFFF00000FFFFC0",
INIT_53 => X"0000000000000000000000000000000FFFF00FF81FFFF3FFF1FFF807FFF8000F",
INIT_54 => X"00000000000000000000020000000000007F000007FC00000000000000000000",
INIT_55 => X"000000000001000001000000007F0080000000007F800000000000000001FF00",
INIT_56 => X"0000140000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0002000000000000000000048000000000000000000000000000000000000200",
INIT_58 => X"0000000000000000000000000000000000000000000000000000028000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => DOUTA(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => \^ena\,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(3 downto 0) => DOADO(3 downto 0),
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
ena => ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
port (
ENA : out STD_LOGIC;
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
\^ena\ : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ is
port (
ENA : out STD_LOGIC;
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
\^ena\ : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ is
port (
ENA : out STD_LOGIC;
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
\^ena\ : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ is
port (
DOUTA : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ENA : in STD_LOGIC;
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
DOUTA(0) => DOUTA(0),
ENA => ENA,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => \^ena\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
signal ram_douta : STD_LOGIC;
signal \ramloop[10].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
begin
\has_mux_a.A\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux
port map (
DOADO(3) => \ramloop[3].ram.r_n_0\,
DOADO(2) => \ramloop[3].ram.r_n_1\,
DOADO(1) => \ramloop[3].ram.r_n_2\,
DOADO(0) => \ramloop[3].ram.r_n_3\,
DOUTA(0) => \ramloop[2].ram.r_n_0\,
addra(5 downto 0) => addra(17 downto 12),
clka => clka,
\^douta\(3 downto 0) => douta(3 downto 0),
\douta[0]\(0) => \ramloop[1].ram.r_n_0\,
\douta[0]_0\(0) => ram_douta,
\douta[1]\(0) => \ramloop[6].ram.r_n_0\,
\douta[1]_0\(0) => \ramloop[5].ram.r_n_0\,
\douta[1]_1\(0) => \ramloop[4].ram.r_n_0\,
\douta[2]\(0) => \ramloop[9].ram.r_n_1\,
\douta[2]_0\(0) => \ramloop[8].ram.r_n_1\,
\douta[2]_1\(0) => \ramloop[7].ram.r_n_1\,
\douta[3]\(0) => \ramloop[12].ram.r_n_0\,
\douta[3]_0\(0) => \ramloop[11].ram.r_n_0\,
\douta[3]_1\(0) => \ramloop[10].ram.r_n_0\,
ena => ena
);
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
DOUTA(0) => ram_douta,
ENA => \ramloop[7].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[10].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\
port map (
DOUTA(0) => \ramloop[10].ram.r_n_0\,
ENA => \ramloop[7].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[11].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\
port map (
DOUTA(0) => \ramloop[11].ram.r_n_0\,
ENA => \ramloop[8].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[12].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\
port map (
DOUTA(0) => \ramloop[12].ram.r_n_0\,
ENA => \ramloop[9].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
DOUTA(0) => \ramloop[1].ram.r_n_0\,
ENA => \ramloop[8].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
DOUTA(0) => \ramloop[2].ram.r_n_0\,
ENA => \ramloop[9].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(3) => \ramloop[3].ram.r_n_0\,
DOADO(2) => \ramloop[3].ram.r_n_1\,
DOADO(1) => \ramloop[3].ram.r_n_2\,
DOADO(0) => \ramloop[3].ram.r_n_3\,
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
ena => ena
);
\ramloop[4].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\
port map (
DOUTA(0) => \ramloop[4].ram.r_n_0\,
ENA => \ramloop[7].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[5].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\
port map (
DOUTA(0) => \ramloop[5].ram.r_n_0\,
ENA => \ramloop[8].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[6].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\
port map (
DOUTA(0) => \ramloop[6].ram.r_n_0\,
ENA => \ramloop[9].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[7].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\
port map (
DOUTA(0) => \ramloop[7].ram.r_n_1\,
ENA => \ramloop[7].ram.r_n_0\,
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[8].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\
port map (
DOUTA(0) => \ramloop[8].ram.r_n_1\,
ENA => \ramloop[8].ram.r_n_0\,
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
\^ena\ => ena
);
\ramloop[9].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\
port map (
DOUTA(0) => \ramloop[9].ram.r_n_1\,
ENA => \ramloop[9].ram.r_n_0\,
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
\^ena\ => ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
douta(3 downto 0) => douta(3 downto 0),
ena => ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
douta(3 downto 0) => douta(3 downto 0),
ena => ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 17 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 17 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 18;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 18;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "24";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 8.585074 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "start_rom.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "start_rom.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 196978;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 196978;
attribute C_READ_LATENCY_A : integer;
attribute C_READ_LATENCY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_READ_LATENCY_B : integer;
attribute C_READ_LATENCY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 4;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 4;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 196978;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 196978;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 4;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is 4;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "artix7";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3_synth
port map (
addra(17 downto 0) => addra(17 downto 0),
clka => clka,
douta(3 downto 0) => douta(3 downto 0),
ena => ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 17 downto 0 );
douta : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "start_rom,blk_mem_gen_v8_4_3,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 18;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 18;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "24";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 8.585074 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "start_rom.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "start_rom.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 196978;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 196978;
attribute C_READ_LATENCY_A : integer;
attribute C_READ_LATENCY_A of U0 : label is 1;
attribute C_READ_LATENCY_B : integer;
attribute C_READ_LATENCY_B of U0 : label is 1;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 4;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 4;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 196978;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 196978;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 4;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 4;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_3
port map (
addra(17 downto 0) => addra(17 downto 0),
addrb(17 downto 0) => B"000000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(3 downto 0) => B"0000",
dinb(3 downto 0) => B"0000",
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => NLW_U0_doutb_UNCONNECTED(3 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(17 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(17 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(17 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(17 downto 0),
s_axi_rdata(3 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(3 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(3 downto 0) => B"0000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
entity LPF_HB_LAB is
port(CLK : in STD_LOGIC;
RST : in STD_LOGIC;
X : in STD_LOGIC_VECTOR(13 downto 0);
Y : out STD_LOGIC_VECTOR(13 downto 0)
);
end LPF_HB_LAB;
architecture synt of LPF_HB_LAB is
constant a : signed(11 downto 0) := to_signed(integer(-0.156*2.0**11),12);
constant b : signed(11 downto 0) := to_signed(integer(0.727*2.0**11),12);
constant c : signed(11 downto 0) := to_signed(integer(-0.269*2.0**11),12);
signal yi : signed(13 downto 0);
signal xi, xi_1, xi_2 : signed(19 downto 0);
signal qi_1, qi_2, pi, pi_1 : signed(31 downto 0);
begin
LPF: process(CLK,RST)
variable yt : signed(19 downto 0);
variable sm_2 : signed(19 downto 0);
variable qi : signed(19 downto 0);
begin
if RST = '1' then
xi <= (others => '0');
pi <= (others => '0');
xi_1 <= (others => '0');
xi_2 <= (others => '0');
qi_1 <= (others => '0');
qi_2 <= (others => '0');
pi_1 <= (others => '0');
yi <= (others => '0');
elsif CLK = '1' and CLK'event then
xi <= RESIZE(signed(X&"0000"), 20);
xi_1 <= xi;
xi_2 <= xi_1;
qi := xi- qi_2(30 downto 11) - pi_1(30 downto 11);
qi_1 <= qi * b;
qi_2 <= qi_1;
pi_1 <= qi * c;
sm_2 := xi_2 + qi_1(30 downto 11) + pi_1(30 downto 11);
yt := sm_2 + xi_1;
yi <= yt(16 downto 3);
end if;
end process;
Y <= std_logic_vector(yi);
end synt;
|
<gh_stars>1-10
library verilog;
use verilog.vl_types.all;
entity Coherent_Coff is
port(
clk : in vl_logic;
Data_A : in vl_logic_vector(11 downto 0);
Data_B : in vl_logic_vector(11 downto 0);
Data_C : in vl_logic_vector(11 downto 0);
Data_D : in vl_logic_vector(11 downto 0);
Data_E : in vl_logic_vector(11 downto 0);
Data_F : in vl_logic_vector(11 downto 0);
Data_G : in vl_logic_vector(11 downto 0);
Data_H : in vl_logic_vector(11 downto 0);
Coff : out vl_logic_vector(7 downto 0)
);
end Coherent_Coff;
|
library verilog;
use verilog.vl_types.all;
entity final_design is
port(
clk : in vl_logic;
pc_reset : in vl_logic;
flags : out vl_logic_vector(3 downto 0)
);
end final_design;
|
-- clkctrl_c5.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity clkctrl_c5 is
port (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
ena : in std_logic := '0'; -- .ena
outclk : out std_logic -- altclkctrl_output.outclk
);
end entity clkctrl_c5;
architecture rtl of clkctrl_c5 is
component clkctrl_c5_altclkctrl_0 is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component clkctrl_c5_altclkctrl_0;
begin
altclkctrl_0 : component clkctrl_c5_altclkctrl_0
port map (
inclk => inclk, -- altclkctrl_input.inclk
ena => ena, -- .ena
outclk => outclk -- altclkctrl_output.outclk
);
end architecture rtl; -- of clkctrl_c5
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ghdlex;
use ghdlex.ghpi_netpp.all;
library work;
use work.global_config.all;
entity tb_versa_ecp5 is
end entity;
architecture sim of tb_versa_ecp5 is
constant UCLK_PERIOD : time :=
real(500000000) / real(50100000) * (1 ns);
constant SYSCLK_PERIOD : time :=
real(500000000) / real(CONFIG_SYSCLK) * (1 ns);
constant MACCLK_PERIOD : time := 8000 ps;
signal clk : std_logic := '0';
signal uclk : std_logic := '0';
signal reset_n : std_logic := '1';
-- Alternative LED on versa_ecp5 board:
signal led : std_logic_vector(7 downto 0);
signal tck, tms, tdi, tdo : std_logic := '0';
-- I2C bus:
signal i2c_scl : std_logic;
signal i2c_sda : std_logic;
-- Internal Slave (bridge) bus:
signal slv_scl : std_logic;
signal slv_sda : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
signal spi_sclk : std_logic;
signal spi_cs : std_logic;
signal macio_miim_clk : std_logic; --! MIIM clk
signal macio_rgmii_tx : std_logic; --! RGMII TX ctr pin
signal macio_rgmii_rx : std_logic; --!
signal macio_mdc : std_logic; --!
signal macio_mdio : std_logic; --!
signal mac_mclk : std_logic := '0';
signal macio_mii_txclk : std_logic;
signal macio_mii_txen : std_logic;
signal macio_mii_txd : std_logic_vector(3 downto 0);
signal macio_mii_txerr : std_logic;
signal macio_mii_rxclk : std_logic;
signal macio_mii_rxd : std_logic_vector(3 downto 0);
signal macio_rgmii_rc : std_logic;
signal macio_rgmii_tc : std_logic;
signal uart_tx : std_logic;
signal uart_rx : std_logic;
begin
initialize:
process
variable retval : integer;
begin
retval := netpp_init("VersaECP5Sim");
wait;
end process;
-- Loopback UART:
-- uart_rx <= uart_tx;
vuart: entity work.VirtualUART
generic map (
DIVIDER => CONFIG_SYSCLK / CONFIG_DEFAULT_UART_BAUDRATE / 16 - 1
)
port map (
rxi => uart_tx,
rxirq => open,
txo => uart_rx,
clk => uclk
);
uut: entity work.versa_ecp5_top
generic map ( SIMULATION => true)
port map (
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
-- clk_out => open,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
-- spi_sclk => spi_sclk,
spi_cs => spi_cs,
twi_scl => i2c_scl,
twi_sda => i2c_sda,
txd_uart => uart_rx,
rxd_uart => uart_tx,
oled => led,
dip_sw => "00110001",
-- phy_rgmii_txclk => macio_mii_txclk,
-- phy_rgmii_txctl => macio_rgmii_tc,
-- phy_rgmii_txd => macio_mii_txd,
-- phy_rgmii_rxclk => macio_mii_rxclk,
-- phy_rgmii_rxctl => macio_rgmii_rc,
-- phy_rgmii_rxd => macio_mii_rxd,
-- ts_mac_coremdc => macio_mdc,
-- ts_mac_coremdio => macio_mdio,
reset_n => reset_n,
clk_in => clk
);
-- Loopback:
-- We need to supply an external rxclk:
macio_mii_rxclk <= mac_mclk;
process (mac_mclk)
begin
if rising_edge(mac_mclk) then
macio_mii_rxd <= macio_mii_txd;
macio_rgmii_rc <= macio_rgmii_tc;
elsif falling_edge(mac_mclk) then
macio_mii_rxd <= macio_mii_txd;
macio_rgmii_rc <= macio_rgmii_tc;
end if;
end process;
clkgen:
clk <= not clk after SYSCLK_PERIOD;
uclk <= not uclk after UCLK_PERIOD;
-- Only for GMII simulation:
mac_mclk <= not mac_mclk after 40 ns;
-- Pull to (weak) H:
i2c_scl <= 'H';
i2c_sda <= 'H';
macio_mdio <= 'L'; -- To have a defined input for simulation
process
begin
global_throttle <= '0';
wait for 6 us;
reset_n <= '0';
wait for 100 ns;
reset_n <= '1';
wait;
end process;
end sim;
|
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|
<reponame>synvue/generic-fifo<filename>hw/tester/os-vvm/CoveragePkg.vhd
--
-- File Name: CoveragePkg.vhd
-- Design Unit Name: CoveragePkg
-- Revision: STANDARD VERSION, revision 2013.05
--
-- Maintainer: <NAME> email: <EMAIL>
-- Contributor(s):
-- <NAME> SynthWorks
-- <NAME> Creonic. Inspired GetMinBinVal, GetMinPoint, GetCov
-- <NAME> Aldec. Inspired GetBin function
--
--
-- Package Defines
-- Functional coverage modeling utilities and data structure
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Latest standard version available at:
-- http://www.SynthWorks.com/downloads
--
-- Revision History:
-- Date Version Description
-- 06/2010: 0.1 Initial revision
-- 09/2010 Release in SynthWorks' VHDL Testbenches and Verification classes
-- 02/2011: 1.0 Requires VHDL-2008 types integer_vector and boolean_vecctor
-- Changed CoverBinType to facilitage long term support of cross coverage
-- 02/2011: 1.1 Added GetMinCov, GetMaxCov, CountCovHoles, GetCovHole
-- 04/2011: 2.0 Added CovPType
-- 06/2011: 2.1 Removed Signal Based Coverage
-- 07/2011: 2.2 Added Weight, AtLeast, randomization with percentage thresholds
-- Randomization with weights/weight modes
-- Cleaned up parameter naming
-- 11/2011: 2.2a Made ALL_RANGE and constants in ZERO_BIN and ONE_BIN have a 1 index
-- rather than 0 to match the range of BinVal
-- 12/2011: 2.2b Fixed minor inconsistencies on interface declarations.
-- Library RandomPkg is assumed to be in the same library as CoveragePkg
-- 01/2012: 2.3 Added Function GetBin from <NAME>.
-- Made write for RangeArrayType visible
-- 01/2012: 2.4
-- Added bin merging and deletion for overlapping bins
-- Renamed RandCovHole to RandCovBinVal - maintained old version calls new
-- Renamed GetCovHole to GetHoleBinVal - maintained old version calls new
-- 04/2013: 2013.04
-- Added control for merging and deletion.
-- Note: Merging will change in a future revision.
-- Merging is off by default. Use function SetMerging to turn it on.
-- Added RandCovPoint for integer.
-- Thresholding is now enabled or disabled by an internal variable.
-- Enable or disable using SetThresholding. Off by default.
-- Revised RandCovPoint and RandCovBinVal to use thresholding.
-- Thresholding is also turned on by SetCovThreshold(Percent).
-- Added coverage target multiplier as a multiplier to all AtLeast values.
-- Multiplier is CovTarget/100. It is 100% by default.
-- Change it with SetCovTarget. Removed the default value from
-- the PercentCov parameter of all methods (RandCovPoint,
-- RandCovBinVal, IsCovered, CountCovHoles, GetHoleBinVal, and
-- WriteCovHoles). Replaced the default value with an
-- overloaded function that uses coverage target instead.
-- Added ILLEGAL_FAILURE mode to illegal bin control.
-- When set, if an illegal bin is encountered, a severity
-- failure will be generated.
-- Added manual bin iteration support.
-- BinIndex: GetNumBins, GetMinIndex, GetMaxIndex
-- BinVal: GetBinVal(BinIndex), GetMinBinVal, GetMaxBinVal
-- Point: GetPoint (BinIndex), GetMinPoint, GetMaxPoint
-- Added FileOpenWriteBin and FileCloseWriteBin
-- Opens default file for WriteBin, WriteCovHoles, and DumpBin
-- Added CompareBins to facilitate comparing two coverage models.
-- Added error checking to methods.
-- Uninitialized model checks to WriteBin, WriteCovHoles, and WriteCovDb.
-- Check AddBins or AddCross do not change the current BinVal size.
-- Added IsInitialized to check if a coverage model is initialized.
-- Added GetBinInfo and GetBinValLength to get bin information
-- WriteBins and WriteCovHoles only print weight if the selected WeightMode uses the weight.
-- Changed WriteCovDb default for File_Open_Kind to WRITE_MODE
-- Generally only one WriteCovDb is needed per coverage model.
-- Updated WriteCovDb and ReadCovDb for new internal control/state variables
-- in the order of ThresholdingEnable, CovTarget, and MergingEnable.
-- To manually edit old file, add FALSE, 100.0, FALSE to end of first line
-- Removed IgnoreBin with AtLeast and Weight parameters.
-- These are zero for ignore bins.
-- Working on consistency of naming. The following have changed:
-- New Name Old Name Why
-- CovBinErrCnt GetErrorCount Consistency between packages
-- GetMinCount GetMinCov[return integer] Naming clarity
-- GetMaxCount GetMaxCov[return integer] Naming clarity
-- SetName SetItemName SetName now does multi-line messages
--
-- The following methods with an AtLeast parameter are deprecated,
-- RandCovPoint, RandCovBinVal, IsCovered, CountCovHoles,
-- GetHoleBinVal, and WriteCovHoles.
-- 5/2013 2013.05
-- No changes of substance.
-- Removed extra variable declaration in functions GetHoleBinval,
-- RandCovBinVal, RandCovHole, GetHoleBinVal
-- Using work.RandomPkg.NULL_RANGE_TYPE to remove NULL range warnings
--
--
--
-- Development Notes:
-- The coverage procedures are named ICover to avoid conflicts with
-- future language changes which may add cover as a keyword
-- Procedure WriteBin writes each CovBin on a separate line, as such
-- it was inappropriate to overload either textio write or to_string
-- In the notes VHDL-2008 notes refers to
-- composites with unconstrained elements
--
--
-- Copyright (c) 2010 - 2013 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
-- Credits:
-- CovBinBaseType is inspired by a structure proposed in the
-- paper "Functional Coverage - without SystemVerilog!"
-- by <NAME> and <NAME>. Presented at DVCon 2010
-- However the approach in their paper uses entities and
-- architectures where this approach relies on functions
-- and procedures, so the usage models differ greatly however.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
use work.RandomPkg.all ;
use work.RandomBasePkg.all ;
package CoveragePkg is
-- CovPType allocates bins that are multiples of MIN_NUM_BINS
constant MIN_NUM_BINS : integer := 2**7 ; -- power of 2
type RangeType is record
min : integer ;
max : integer ;
end record ;
type RangeArrayType is array (integer range <>) of RangeType ;
constant ALL_RANGE : RangeArrayType := (1=>(Integer'left, Integer'right)) ;
procedure write ( file f : text ; BinVal : RangeArrayType ) ;
-- CovBinBaseType.action values.
-- Note that coverage counting depends on these values
constant COV_COUNT : integer := 1 ;
constant COV_IGNORE : integer := 0 ;
constant COV_ILLEGAL : integer := -1 ;
-- Used for easy manual entry. Order: min, max, action
-- Intentionally did not use a record to allow other input
-- formats in the future with VHDL-2008 unconstrained arrays
-- of unconstrained elements
type CovBinManualType is array (natural range <>) of integer_vector(0 to 2) ;
type CovBinBaseType is record
BinVal : RangeArrayType(1 to 1) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovBinType is array (natural range <>) of CovBinBaseType ;
constant ALL_BIN : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ALL_COUNT : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ALL_ILLEGAL : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_ILLEGAL, Count => 0, AtLeast => 0, Weight => 0 )) ;
constant ALL_IGNORE : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_IGNORE, Count => 0, AtLeast => 0, Weight => 0 )) ;
constant ZERO_BIN : CovBinType := (0 => ( BinVal => (1=>(0,0)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ONE_BIN : CovBinType := (0 => ( BinVal => (1=>(1,1)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant NULL_BIN : CovBinType(work.RandomPkg.NULL_RANGE_TYPE) := (others => ( BinVal => ALL_RANGE, Action => integer'high, Count => 0, AtLeast => integer'high, Weight => integer'high )) ;
type CountModeType is (COUNT_FIRST, COUNT_ALL) ;
type IllegalModeType is (ILLEGAL_ON, ILLEGAL_FAILURE, ILLEGAL_OFF) ;
type WeightModeType is (AT_LEAST, WEIGHT, REMAIN, REMAIN_EXP, REMAIN_SCALED, REMAIN_WEIGHT ) ;
-- In VHDL-2008 CovMatrix?BaseType and CovMatrix?Type will be subsumed
-- by CovBinBaseType and CovBinType with RangeArrayType as an unconstrained array.
type CovMatrix2BaseType is record
BinVal : RangeArrayType(1 to 2) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix2Type is array (natural range <>) of CovMatrix2BaseType ;
type CovMatrix3BaseType is record
BinVal : RangeArrayType(1 to 3) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix3Type is array (natural range <>) of CovMatrix3BaseType ;
type CovMatrix4BaseType is record
BinVal : RangeArrayType(1 to 4) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix4Type is array (natural range <>) of CovMatrix4BaseType ;
type CovMatrix5BaseType is record
BinVal : RangeArrayType(1 to 5) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix5Type is array (natural range <>) of CovMatrix5BaseType ;
type CovMatrix6BaseType is record
BinVal : RangeArrayType(1 to 6) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix6Type is array (natural range <>) of CovMatrix6BaseType ;
type CovMatrix7BaseType is record
BinVal : RangeArrayType(1 to 7) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix7Type is array (natural range <>) of CovMatrix7BaseType ;
type CovMatrix8BaseType is record
BinVal : RangeArrayType(1 to 8) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix8Type is array (natural range <>) of CovMatrix8BaseType ;
type CovMatrix9BaseType is record
BinVal : RangeArrayType(1 to 9) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix9Type is array (natural range <>) of CovMatrix9BaseType ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer ;
function ToMinPoint (A : RangeArrayType) return integer_vector ;
-- BinVal to Minimum Point
------------------------------------------------------------
procedure ToRandPoint(
-- BinVal to Random Point
-- better as a function, however, inout not supported on functions
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer
) ;
------------------------------------------------------------
procedure ToRandPoint(
-- BinVal to Random Point
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer_vector
) ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
type CovPType is protected
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) ;
procedure FileCloseWriteBin ;
-- procedure FileOpenWriteCovDb (FileName : string; OpenKind : File_Open_Kind ) ;
-- procedure FileCloseWriteCovDb ;
procedure SetIllegalMode (A : IllegalModeType) ;
procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) ;
procedure SetName (NameIn : String) ;
procedure DeallocateName ; -- clear name
procedure SetThresholding(A : boolean := TRUE ) ; -- 2.5
procedure SetCovThreshold (Percent : real) ;
procedure SetCovTarget (Percent : real) ; -- 2.5
impure function GetCovTarget return real ; -- 2.5
procedure SetMerging(A : boolean := TRUE ) ; -- 2.5
procedure SetCountMode (A : CountModeType) ;
procedure InitSeed (S : string ) ;
procedure InitSeed (I : integer ) ;
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
procedure SetBinSize (NewNumBins : integer) ;
------------------------------------------------------------
procedure AddBins (
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) ;
procedure AddBins (AtLeast : integer ; CovBin : CovBinType) ;
procedure AddBins (CovBin : CovBinType) ;
------------------------------------------------------------
procedure AddCross(
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
procedure Deallocate ;
procedure ICover( CovPoint : integer) ;
procedure ICover( CovPoint : integer_vector) ;
procedure SetCovZero ;
impure function IsInitialized return boolean ;
impure function GetNumBins return integer ;
impure function GetMinIndex return integer ;
impure function GetMinCov return real ; -- PercentCov
impure function GetMinCount return integer ; -- Count
impure function GetMaxIndex return integer ;
impure function GetMaxCov return real ; -- PercentCov
impure function GetMaxCount return integer ; -- Count
impure function CountCovHoles ( PercentCov : real ) return integer ;
impure function CountCovHoles return integer ;
impure function IsCovered return boolean ;
impure function IsCovered ( PercentCov : real ) return boolean ;
impure function GetCov return real ; -- PercentCov of entire model/all bins
-- Return BinVal
impure function GetBinVal ( BinIndex : integer ) return RangeArrayType ;
impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType ;
impure function RandCovBinVal return RangeArrayType ;
impure function GetMinBinVal return RangeArrayType ;
impure function GetMaxBinVal return RangeArrayType ;
impure function GetHoleBinVal ( ReqHoleNum : integer ; CovTargetPercent : real ) return RangeArrayType ;
impure function GetHoleBinVal ( CovTargetPercent : real ) return RangeArrayType ;
impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- Return Points
impure function RandCovPoint return integer ;
impure function RandCovPoint ( PercentCov : real ) return integer ;
impure function RandCovPoint return integer_vector ;
impure function RandCovPoint ( PercentCov : real ) return integer_vector ;
impure function GetPoint ( BinIndex : integer ) return integer ;
impure function GetPoint ( BinIndex : integer ) return integer_vector ;
impure function GetMinPoint return integer ;
impure function GetMinPoint return integer_vector ;
impure function GetMaxPoint return integer ;
impure function GetMaxPoint return integer_vector ;
-- GetBin returns an internal value of the coverage data structure
-- The return value may change as the package evolves
-- Use it only for debugging.
-- GetBinInfo is a for development only.
impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType ;
impure function GetBinValLength return integer ;
impure function GetBin ( BinIndex : integer ) return CovBinBaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType ;
-- procedure WriteBin ( file f : text ) ;
procedure WriteBin ;
procedure WriteBin ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ;
procedure WriteCovHoles ( PercentCov : real ) ;
procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure DumpBin ; -- Development only
procedure ReadCovDb (FileName : string) ;
procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
impure function GetErrorCount return integer ;
-- These support usage of cross coverage constants
-- Also support the older AddBins(GenCross(...)) methodology
-- which has been replaced by AddCross
procedure AddBins (CovBin : CovMatrix2Type) ;
procedure AddBins (CovBin : CovMatrix3Type) ;
procedure AddBins (CovBin : CovMatrix4Type) ;
procedure AddBins (CovBin : CovMatrix5Type) ;
procedure AddBins (CovBin : CovMatrix6Type) ;
procedure AddBins (CovBin : CovMatrix7Type) ;
procedure AddBins (CovBin : CovMatrix8Type) ;
procedure AddBins (CovBin : CovMatrix9Type) ;
------------------------------------------------------------
-- Remaining are Deprecated
--
-- Deprecated. Replaced by SetName with multi-line support
procedure SetItemName (ItemNameIn : String) ; -- deprecated
-- Deprecated. Consistency across packages
impure function CovBinErrCnt return integer ;
-- Deprecated. Due to name changes to promote greater consistency
-- Maintained for backward compatibility.
-- RandCovHole replaced by RandCovBinVal
impure function RandCovHole ( PercentCov : real ) return RangeArrayType ; -- Deprecated
impure function RandCovHole return RangeArrayType ; -- Deprecated
-- GetCovHole replaced by GetHoleBinVal
impure function GetCovHole ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetCovHole ( PercentCov : real ) return RangeArrayType ;
impure function GetCovHole ( ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- Deprecated/ Subsumed by versions with PercentCov Parameter
-- Maintained for backward compatibility only and
-- may be removed in the future.
impure function GetMinCov return integer ;
impure function GetMaxCov return integer ;
impure function CountCovHoles ( AtLeast : integer ) return integer ;
impure function IsCovered ( AtLeast : integer ) return boolean ;
impure function RandCovBinVal ( AtLeast : integer ) return RangeArrayType ;
impure function RandCovHole ( AtLeast : integer ) return RangeArrayType ; -- Deprecated
impure function RandCovPoint (AtLeast : integer ) return integer ;
impure function RandCovPoint (AtLeast : integer ) return integer_vector ;
impure function GetHoleBinVal ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ;
impure function GetCovHole ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ;
procedure WriteCovHoles ( AtLeast : integer ) ;
procedure WriteCovHoles ( FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
end protected CovPType ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType ;
variable ErrorCount : inout integer
) ;
--
-- Support for AddBins and AddCross
--
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType ;
-- Each item in range in a separate CovBin
function GenBin(AtLeast : integer ; Min, Max, NumBin : integer ) return CovBinType ;
function GenBin(Min, Max, NumBin : integer ) return CovBinType ;
function GenBin(Min, Max : integer) return CovBinType ;
function GenBin(A : integer) return CovBinType ;
------------------------------------------------------------
function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType ;
------------------------------------------------------------
-- All items in range in a single CovBin
function IllegalBin ( Min, Max : integer ) return CovBinType ;
function IllegalBin ( A : integer ) return CovBinType ;
----------------------------------------------------------
-- function IgnoreBin (
----------------------------------------------------------
-- AtLeast : integer ;
-- Weight : integer ;
-- Min, Max : integer ;
-- NumBin : integer
-- ) return CovBinType ;
-- function IgnoreBin (AtLeast : integer ; Min, Max, NumBin : integer) return CovBinType ;
-- All items in range in a single CovBin
------------------------------------------------------------
function IgnoreBin (Min, Max, NumBin : integer) return CovBinType ;
------------------------------------------------------------
function IgnoreBin (Min, Max : integer) return CovBinType ;
function IgnoreBin (A : integer) return CovBinType ;
------------------------------------------------------------
function GenBin (
-- Manual entry format for CovBin within lots of extra parens
------------------------------------------------------------
ManualBin : CovBinManualType
) return CovBinType ;
-- With VHDL-2008, there will be one GenCross that returns CovBinType
-- and has inputs initialized to NULL_BIN - see AddCross
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type ;
function GenCross(AtLeast : integer ; Bin1, Bin2 : CovBinType) return CovMatrix2Type ;
function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type ;
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type ;
function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type ;
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type ;
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type ;
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type ;
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type ;
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type ;
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type ;
------------------------------------------------------------
procedure increment( signal Count : inout integer ) ;
procedure increment( signal Count : inout integer ; enable : boolean ) ;
procedure increment( signal Count : inout integer ; enable : std_ulogic ) ;
------------------------------------------------------------
-- Utilities. Remove if added to std.standard
function to_integer ( B : boolean ) return integer ;
function to_integer ( SL : std_logic ) return integer ;
function to_integer_vector ( BV : boolean_vector ) return integer_vector ;
function to_integer_vector ( SLV : std_logic_vector ) return integer_vector ;
end package CoveragePkg ;
--- //////////////////////////////////////////////////////////////////////////////////////////////
--- //////////////////////////////////////////////////////////////////////////////////////////////
package body CoveragePkg is
------------------------------------------------------------
function inside (
-- package local
------------------------------------------------------------
CovPoint : integer ;
BinVal : RangeType
) return boolean is
begin
return CovPoint >= BinVal.min and CovPoint <= BinVal.max ;
end function inside ;
------------------------------------------------------------
function inside (
-- package local
------------------------------------------------------------
CovPoint : integer_vector ;
BinVal : RangeArrayType
) return boolean is
alias iCovPoint : integer_vector(BinVal'range) is CovPoint ;
begin
for i in BinVal'range loop
if not (iCovPoint(i) >= BinVal(i).min and iCovPoint(i) <= BinVal(i).max) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function inside ;
------------------------------------------------------------
function inside (
-- package local, used by InsertBin
-- True when BinVal1 is inside BinVal2
------------------------------------------------------------
BinVal1 : RangeArrayType ;
BinVal2 : RangeArrayType
) return boolean is
alias iBinVal2 : RangeArrayType(BinVal1'range) is BinVal2 ;
begin
for i in BinVal1'range loop
if not (BinVal1(i).min >= iBinVal2(i).min and BinVal1(i).max <= iBinVal2(i).max) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function inside ;
------------------------------------------------------------
procedure write ( file f : text ; CovPoint : integer_vector ) is
-- package local. called by ICover
------------------------------------------------------------
alias iCovPoint : integer_vector(1 to CovPoint'length) is CovPoint ;
begin
write(f, "(" & integer'image(iCovPoint(1)) ) ;
for i in 2 to iCovPoint'right loop
write(f, "," & integer'image(iCovPoint(i)) ) ;
end loop ;
write(f, ")") ;
end procedure write ;
------------------------------------------------------------
procedure write ( file f : text ; BinVal : RangeArrayType ) is
-- called by WriteBin and WriteCovHoles
------------------------------------------------------------
begin
for i in BinVal'range loop
if BinVal(i).min = BinVal(i).max then
write(f, "(" & integer'image(BinVal(i).min) & ") " ) ;
elsif (BinVal(i).min = integer'left) and (BinVal(i).max = integer'right) then
write(f, "(ALL) " ) ;
else
write(f, "(" & integer'image(BinVal(i).min) & " to " &
integer'image(BinVal(i).max) & ") " ) ;
end if ;
end loop ;
end procedure write ;
------------------------------------------------------------
-- package local
function failed (InValid : boolean ; Message : string := " ") return boolean is
-- Move to TbUtilPkg and make visible?
------------------------------------------------------------
begin
if InValid then
report Message severity failure ;
end if ;
return InValid ;
end function failed ;
------------------------------------------------------------
-- package local
procedure EmptyOrCommentLine (
-- Better as Function, but not supported in VHDL functions
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) is
variable Valid : boolean ;
variable Char : character ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
Empty := TRUE ;
-- if line empty (null or 0 length), Empty = TRUE
if L = null or L.all'length = 0 then
return ;
end if ;
-- if line starts with '#', empty = TRUE
if L.all(1) = '#' then
return ;
end if ;
-- if line starts with '--', empty = TRUE
if L.all'length >= 2 and L.all(1) = '-' and L.all(2) = '-' then
return ;
end if ;
-- Otherwise, remove white space and check for end of line
-- Code borrowed from <NAME>, skip_whitespace
WhiteSpLoop : while L /= null and L.all'length > 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (L, Char, Valid) ;
else
Empty := FALSE ;
exit WhiteSpLoop ;
end if ;
end loop WhiteSpLoop ;
end procedure EmptyOrCommentLine ;
------------------------------------------------------------
-- package local for now
procedure read (
-- if public, also create one that does not use valid flag
------------------------------------------------------------
variable buf : inout line ;
variable BinVal : out RangeArrayType ;
variable Valid : out boolean
) is
variable ReadValid : boolean ;
begin
for i in BinVal'range loop
read(buf, BinVal(i).min, ReadValid) ;
exit when not ReadValid ;
read(buf, BinVal(i).max, ReadValid) ;
exit when not ReadValid ;
end loop ;
Valid := ReadValid ;
end procedure read ;
------------------------------------------------------------
procedure write (
-- package local for now
------------------------------------------------------------
variable buf : inout line ;
constant BinVal : in RangeArrayType
) is
begin
for i in BinVal'range loop
write(buf, BinVal(i).min) ;
write(buf, ' ') ;
write(buf, BinVal(i).max) ;
write(buf, ' ') ;
end loop ;
end procedure write ;
-- ------------------------------------------------------------
function BinLengths (
-- package local, used by AddCross, GenCross
-- ------------------------------------------------------------
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) return integer_vector is
variable result : integer_vector(1 to 20) := (others => 0 ) ;
variable i : integer := result'left ;
variable Len : integer ;
begin
loop
case i is
when 1 => Len := Bin1'length ;
when 2 => Len := Bin2'length ;
when 3 => Len := Bin3'length ;
when 4 => Len := Bin4'length ;
when 5 => Len := Bin5'length ;
when 6 => Len := Bin6'length ;
when 7 => Len := Bin7'length ;
when 8 => Len := Bin8'length ;
when 9 => Len := Bin9'length ;
when 10 => Len := Bin10'length ;
when 11 => Len := Bin11'length ;
when 12 => Len := Bin12'length ;
when 13 => Len := Bin13'length ;
when 14 => Len := Bin14'length ;
when 15 => Len := Bin15'length ;
when 16 => Len := Bin16'length ;
when 17 => Len := Bin17'length ;
when 18 => Len := Bin18'length ;
when 19 => Len := Bin19'length ;
when 20 => Len := Bin20'length ;
when others => Len := 0 ;
end case ;
result(i) := Len ;
exit when Len = 0 ;
i := i + 1 ;
exit when i = 21 ;
end loop ;
return result(1 to (i-1)) ;
end function BinLengths ;
-- ------------------------------------------------------------
function CalcNumCrossBins ( BinLens : integer_vector ) return integer is
-- package local, used by AddCross
-- ------------------------------------------------------------
variable result : integer := 1 ;
begin
for i in BinLens'range loop
result := result * BinLens(i) ;
end loop ;
return result ;
end function CalcNumCrossBins ;
-- ------------------------------------------------------------
procedure IncBinIndex (
-- package local, used by AddCross
-- ------------------------------------------------------------
variable BinIndex : inout integer_vector ;
constant BinLens : in integer_vector
) is
alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ;
alias aBinLens : integer_vector(aBinIndex'range) is BinLens ;
begin
-- increment right most one, then if overflow, increment next
-- assumes bins numbered from 1 to N. - assured by ConcatenateBins
for i in aBinIndex'reverse_range loop
aBinIndex(i) := aBinIndex(i) + 1 ;
exit when aBinIndex(i) <= aBinLens(i) ;
aBinIndex(i) := 1 ;
end loop ;
end procedure IncBinIndex ;
-- ------------------------------------------------------------
function ConcatenateBins (
-- package local, used by AddCross
-- ------------------------------------------------------------
BinIndex : integer_vector ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) return CovBinType is
alias aBin1 : CovBinType (1 to Bin1'length) is Bin1 ;
alias aBin2 : CovBinType (1 to Bin2'length) is Bin2 ;
alias aBin3 : CovBinType (1 to Bin3'length) is Bin3 ;
alias aBin4 : CovBinType (1 to Bin4'length) is Bin4 ;
alias aBin5 : CovBinType (1 to Bin5'length) is Bin5 ;
alias aBin6 : CovBinType (1 to Bin6'length) is Bin6 ;
alias aBin7 : CovBinType (1 to Bin7'length) is Bin7 ;
alias aBin8 : CovBinType (1 to Bin8'length) is Bin8 ;
alias aBin9 : CovBinType (1 to Bin9'length) is Bin9 ;
alias aBin10 : CovBinType (1 to Bin10'length) is Bin10 ;
alias aBin11 : CovBinType (1 to Bin11'length) is Bin11 ;
alias aBin12 : CovBinType (1 to Bin12'length) is Bin12 ;
alias aBin13 : CovBinType (1 to Bin13'length) is Bin13 ;
alias aBin14 : CovBinType (1 to Bin14'length) is Bin14 ;
alias aBin15 : CovBinType (1 to Bin15'length) is Bin15 ;
alias aBin16 : CovBinType (1 to Bin16'length) is Bin16 ;
alias aBin17 : CovBinType (1 to Bin17'length) is Bin17 ;
alias aBin18 : CovBinType (1 to Bin18'length) is Bin18 ;
alias aBin19 : CovBinType (1 to Bin19'length) is Bin19 ;
alias aBin20 : CovBinType (1 to Bin20'length) is Bin20 ;
alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ;
variable result : CovBinType(aBinIndex'range) ;
begin
for i in aBinIndex'range loop
case i is
when 1 => result(i) := aBin1(aBinIndex(i)) ;
when 2 => result(i) := aBin2(aBinIndex(i)) ;
when 3 => result(i) := aBin3(aBinIndex(i)) ;
when 4 => result(i) := aBin4(aBinIndex(i)) ;
when 5 => result(i) := aBin5(aBinIndex(i)) ;
when 6 => result(i) := aBin6(aBinIndex(i)) ;
when 7 => result(i) := aBin7(aBinIndex(i)) ;
when 8 => result(i) := aBin8(aBinIndex(i)) ;
when 9 => result(i) := aBin9(aBinIndex(i)) ;
when 10 => result(i) := aBin10(aBinIndex(i)) ;
when 11 => result(i) := aBin11(aBinIndex(i)) ;
when 12 => result(i) := aBin12(aBinIndex(i)) ;
when 13 => result(i) := aBin13(aBinIndex(i)) ;
when 14 => result(i) := aBin14(aBinIndex(i)) ;
when 15 => result(i) := aBin15(aBinIndex(i)) ;
when 16 => result(i) := aBin16(aBinIndex(i)) ;
when 17 => result(i) := aBin17(aBinIndex(i)) ;
when 18 => result(i) := aBin18(aBinIndex(i)) ;
when 19 => result(i) := aBin19(aBinIndex(i)) ;
when 20 => result(i) := aBin20(aBinIndex(i)) ;
when others => report "ConcatenateBins: More than 20 bins not supported" severity failure ;
end case ;
end loop ;
return result ;
end function ConcatenateBins ;
------------------------------------------------------------
function MergeState( CrossBins : CovBinType) return integer is
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
variable resultState : integer ;
begin
resultState := COV_COUNT ;
for i in CrossBins'range loop
if CrossBins(i).action = COV_ILLEGAL then
return COV_ILLEGAL ;
end if ;
if CrossBins(i).action = COV_IGNORE then
resultState := COV_IGNORE ;
end if ;
end loop ;
return resultState ;
end function MergeState ;
------------------------------------------------------------
function MergeBinVal( CrossBins : CovBinType) return RangeArrayType is
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
alias aCrossBins : CovBinType(1 to CrossBins'length) is CrossBins ;
variable BinVal : RangeArrayType(aCrossBins'range) ;
begin
for i in aCrossBins'range loop
BinVal(i to i) := aCrossBins(i).BinVal ;
end loop ;
return BinVal ;
end function MergeBinVal ;
------------------------------------------------------------
function MergeAtLeast(
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
Action : in integer ;
AtLeast : in integer ;
CrossBins : in CovBinType
) return integer is
variable Result : integer := AtLeast ;
begin
if Action /= COV_COUNT then
return 0 ;
end if ;
for i in CrossBins'range loop
if CrossBins(i).Action = Action then
Result := maximum (Result, CrossBins(i).AtLeast) ;
end if ;
end loop ;
return result ;
end function MergeAtLeast ;
------------------------------------------------------------
function MergeWeight(
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
Action : in integer ;
Weight : in integer ;
CrossBins : in CovBinType
) return integer is
variable Result : integer := Weight ;
begin
if Action /= COV_COUNT then
return 0 ;
end if ;
for i in CrossBins'range loop
if CrossBins(i).Action = Action then
Result := maximum (Result, CrossBins(i).Weight) ;
end if ;
end loop ;
return result ;
end function MergeWeight ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer is
-- Used in testing
------------------------------------------------------------
begin
return A(A'left).min ;
end function ToMinPoint ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer_vector is
-- Used in testing
------------------------------------------------------------
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i).min ;
end loop ;
return result ;
end function ToMinPoint ;
------------------------------------------------------------
procedure ToRandPoint(
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer
) is
begin
result := RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
end procedure ToRandPoint ;
------------------------------------------------------------
procedure ToRandPoint(
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer_vector
) is
variable VectorVal : integer_vector(BinVal'range) ;
begin
for i in BinVal'range loop
VectorVal(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ;
end loop ;
result := VectorVal ;
end procedure ToRandPoint ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
type CovPType is protected body
-- Name Data Structure
type LineListType ;
type LineListPtrType is access LineListType ;
type LineListType is record
Name : Line ;
NextPtr : LineListPtrType ;
end record LineListType ;
-- CoverageBin Data Structures
type RangeArrayPtrType is access RangeArrayType ;
type CovBinBaseTempType is record
BinVal : RangeArrayPtrType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
PercentCov : real ;
OrderCount : integer ;
end record CovBinBaseTempType ;
type CovBinTempType is array (natural range <>) of CovBinBaseTempType ;
type CovBinPtrType is access CovBinTempType ;
variable CovBinPtr : CovBinPtrType ;
variable NumBins : integer := 0 ;
variable BinValLength : integer := 1 ;
variable OrderCount : integer := 0 ; -- for statistics
-- Internal Modes and Names
variable IllegalMode : IllegalModeType := ILLEGAL_ON ;
variable WeightMode : WeightModeType := AT_LEAST ;
variable WeightScale : real := 1.0 ;
variable NameHeadPtr : LineListPtrType := NULL ;
variable NameTailPtr : LineListPtrType := NULL ;
variable ThresholdingEnable : boolean := FALSE ; -- thresholding disabled by default
variable CovThreshold : real := 45.0 ;
variable CovTarget : real := 100.0 ;
variable MergingEnable : boolean := FALSE ; -- merging disabled by default
variable CountMode : CountModeType := COUNT_FIRST ;
-- Randomization Variable
variable RV : RandomPType ;
variable RvSeedInit : boolean := FALSE ;
file WriteBinFile : text ;
variable WriteBinFileInit : boolean := FALSE ;
-- file WriteCovDbFile : text ;
-- variable WriteCovDbFileInit : boolean := FALSE ;
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
WriteBinFileInit := TRUE ;
file_open( WriteBinFile , FileName , OpenKind );
end procedure FileOpenWriteBin ;
------------------------------------------------------------
procedure FileCloseWriteBin is
------------------------------------------------------------
begin
WriteBinFileInit := FALSE ;
file_close( WriteBinFile) ;
end procedure FileCloseWriteBin ;
-- ------------------------------------------------------------
-- procedure FileOpenWriteCovDb (FileName : string; OpenKind : File_Open_Kind ) is
-- ------------------------------------------------------------
-- begin
-- WriteCovDbFileInit := TRUE ;
-- file_open( WriteCovDbFile , FileName , OpenKind );
-- end procedure FileOpenWriteCovDb ;
--
-- ------------------------------------------------------------
-- procedure FileCloseWriteCovDb is
-- ------------------------------------------------------------
-- begin
-- WriteCovDbFileInit := FALSE ;
-- file_close( WriteCovDbFile );
-- end procedure FileCloseWriteCovDb ;
------------------------------------------------------------
procedure SetIllegalMode (A : IllegalModeType) is
------------------------------------------------------------
begin
IllegalMode := A ;
end procedure SetIllegalMode ;
------------------------------------------------------------
procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) is
------------------------------------------------------------
begin
WeightMode := A ;
WeightScale := Scale ;
if (WeightMode = REMAIN_EXP) and (WeightScale > 2.0) then
write(OUTPUT, "%%WARNING: WeightScale > 2.0 and large Counts can cause RandCovPoint to fail due to integer values out of range" & LF) ;
end if ;
if (WeightScale < 1.0) and (WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED) then
report "WeightScale must be > 1.0 when WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED"
severity failure ;
WeightScale := 1.0 ;
end if;
if WeightScale <= 0.0 then
report "WeightScale must be > 0.0" severity failure ;
WeightScale := 1.0 ;
end if;
end procedure SetWeightMode ;
------------------------------------------------------------
procedure SetName (NameIn : String) is
------------------------------------------------------------
variable NamePtr : line ;
begin
NamePtr := new string'(NameIn) ;
if NameHeadPtr = NULL then
NameHeadPtr := new LineListType'(NamePtr, NULL) ;
NameTailPtr := NameHeadPtr ;
if not RvSeedInit then
RV.InitSeed(NameIn) ;
RvSeedInit := TRUE ;
end if ;
else
NameTailPtr.NextPtr := new LineListType'(NamePtr, NULL) ;
NameTailPtr := NameTailPtr.NextPtr ;
end if ;
end procedure SetName ;
------------------------------------------------------------
-- pt local for now -- file formal parameter not allowed with a public method
procedure WriteBinName ( file f : text ; S : string ; Prefix : string := "%%" ) is
------------------------------------------------------------
variable CurPtr : LineListPtrType ;
variable buf : line ;
begin
if NameHeadPtr = NULL then
if Prefix'length + S'length > 0 then
write(buf, Prefix & S) ;
writeline(f, buf) ;
-- write(f, Prefix & S & LF);
end if ;
else
write(buf, Prefix & S & NameHeadPtr.Name.all) ;
writeline(f, buf) ;
-- write(f, Prefix & S & NameHeadPtr.Name.all & LF) ;
CurPtr := NameHeadPtr.NextPtr ;
while CurPtr /= NULL loop
write(buf, Prefix & CurPtr.Name.all) ;
writeline(f, buf) ;
-- write(f, Prefix & CurPtr.Name.all & LF) ;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
end procedure WriteBinName ;
------------------------------------------------------------
procedure DeallocateName is
------------------------------------------------------------
variable CurPtr : LineListPtrType ;
begin
while NameHeadPtr /= NULL loop
CurPtr := NameHeadPtr ;
NameHeadPtr := NameHeadPtr.NextPtr ;
deallocate( CurPtr.Name) ;
deallocate( CurPtr ) ;
end loop ;
NameTailPtr := NULL ; -- contents deallocated above
end procedure DeallocateName ;
------------------------------------------------------------
-- pt local
impure function NumberOfNames return integer is
------------------------------------------------------------
variable CurPtr : LineListPtrType ;
variable Count : integer := 0 ;
begin
CurPtr := NameHeadPtr ;
while CurPtr /= NULL loop
Count := Count + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return Count ;
end function NumberOfNames ;
------------------------------------------------------------
procedure SetThresholding (A : boolean := TRUE ) is
------------------------------------------------------------
begin
ThresholdingEnable := A ;
end procedure SetThresholding ;
------------------------------------------------------------
procedure SetCovThreshold (Percent : real) is
------------------------------------------------------------
begin
ThresholdingEnable := TRUE ;
if Percent >= 0.0 then
CovThreshold := Percent + 0.0001 ; -- used in less than
else
CovThreshold := 0.0001 ; -- used in less than
report "Invalid Threshold Value " & real'image(Percent) severity failure ;
end if ;
end procedure SetCovThreshold ;
------------------------------------------------------------
procedure SetCovTarget (Percent : real) is
------------------------------------------------------------
begin
CovTarget := Percent ;
end procedure SetCovTarget ;
------------------------------------------------------------
impure function GetCovTarget return real is
------------------------------------------------------------
begin
return CovTarget ;
end function GetCovTarget ;
------------------------------------------------------------
procedure SetMerging (A : boolean := TRUE ) is
------------------------------------------------------------
begin
MergingEnable := A ;
end procedure SetMerging ;
------------------------------------------------------------
procedure SetCountMode (A : CountModeType) is
------------------------------------------------------------
begin
CountMode := A ;
end procedure SetCountMode ;
------------------------------------------------------------
procedure InitSeed (S : string ) is
------------------------------------------------------------
begin
RV.InitSeed(S) ;
RvSeedInit := TRUE ;
end procedure InitSeed ;
------------------------------------------------------------
procedure InitSeed (I : integer ) is
------------------------------------------------------------
begin
RV.InitSeed(I) ;
RvSeedInit := TRUE ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
------------------------------------------------------------
begin
RV.SetSeed(RandomSeedIn) ;
RvSeedInit := TRUE ;
end procedure SetSeed ;
------------------------------------------------------------
impure function GetSeed return RandomSeedType is
------------------------------------------------------------
begin
return RV.GetSeed ;
end function GetSeed ;
------------------------------------------------------------
procedure SetBinSize (NewNumBins : integer) is
-- Sets a CovBin to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
------------------------------------------------------------
variable oldCovBinPtr : CovBinPtrType ;
begin
if CovBinPtr = NULL then
CovBinPtr := new CovBinTempType(1 to NewNumBins) ;
elsif NewNumBins > CovBinPtr'length then
-- make message bigger
oldCovBinPtr := CovBinPtr ;
CovBinPtr := new CovBinTempType(1 to NewNumBins) ;
CovBinPtr.all(1 to NumBins) := oldCovBinPtr.all(1 to NumBins) ;
deallocate(oldCovBinPtr) ;
end if ;
end procedure SetBinSize ;
------------------------------------------------------------
-- pt local
procedure CheckBinValLength( CurBinValLength : integer ; Caller : string ) is
begin
if NumBins = 0 then
BinValLength := CurBinValLength ; -- number of points in cross
else
assert BinValLength = CurBinValLength
report Caller & ": Cross bins with different sizes prohibited"
severity failure ;
end if;
end procedure CheckBinValLength ;
------------------------------------------------------------
-- pt local
impure function NormalizeNumBins( ReqNumBins : integer ) return integer is
variable NormNumBins : integer := MIN_NUM_BINS ;
begin
while NormNumBins < ReqNumBins loop
NormNumBins := NormNumBins + MIN_NUM_BINS ;
end loop ;
return NormNumBins ;
end function NormalizeNumBins ;
------------------------------------------------------------
-- pt local
procedure GrowBins (ReqNumBins : integer) is
variable oldCovBinPtr : CovBinPtrType ;
variable NewNumBins : integer ;
begin
NewNumBins := NumBins + ReqNumBins ;
if CovBinPtr = NULL then
CovBinPtr := new CovBinTempType(1 to NormalizeNumBins(NewNumBins)) ;
elsif NewNumBins > CovBinPtr'length then
-- make message bigger
oldCovBinPtr := CovBinPtr ;
CovBinPtr := new CovBinTempType(1 to NormalizeNumBins(NewNumBins)) ;
CovBinPtr.all(1 to NumBins) := oldCovBinPtr.all(1 to NumBins) ;
deallocate(oldCovBinPtr) ;
end if ;
end procedure GrowBins ;
------------------------------------------------------------
-- pt local, called by InsertBin
-- Finds index of bin if it is inside an existing bins
procedure FindBinInside(
BinVal : RangeArrayType ;
Position : out integer ;
FoundInside : out boolean
) is
begin
Position := NumBins + 1 ;
FoundInside := FALSE ;
FindLoop : for i in 1 to NumBins loop
-- skip this CovBin if CovPoint is not in it
next FindLoop when not inside(BinVal, CovBinPtr(i).BinVal.all) ;
Position := i ;
FoundInside := TRUE ;
exit ;
end loop ;
end procedure FindBinInside ;
------------------------------------------------------------
-- pt local
-- All insertion comes here
-- Enforces the general insertion use model:
-- Earlier bins supercede later bins - except with COUNT_ALL
-- Add Illegal and Ignore bins first to remove regions of larger count bins
-- Later ignore bins can be used to miss an illegal catch-all
-- Add Illegal bins last as a catch-all to find things that missed other bins
procedure InsertBin(
BinVal : RangeArrayType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
PercentCov : real := 0.0
) is
variable Position : integer ;
variable FoundInside : boolean ;
begin
FindBinInside(BinVal, Position, FoundInside) ;
if not MergingEnable or CountMode = COUNT_ALL or not FoundInside then
-- Usage: general insertion
NumBins := NumBins + 1 ;
CovBinPtr.all(NumBins).BinVal := new RangeArrayType'(BinVal) ;
CovBinPtr.all(NumBins).Action := Action ;
CovBinPtr.all(NumBins).Count := Count ;
CovBinPtr.all(NumBins).AtLeast := AtLeast ;
CovBinPtr.all(NumBins).Weight := Weight ;
CovBinPtr.all(NumBins).PercentCov := PercentCov ;
CovBinPtr.all(NumBins).OrderCount := 0 ; --- Metrics for evaluating randomization order Temp
elsif Action = COV_COUNT then
if CovBinPtr.all(Position).Action = COV_COUNT then
if CovBinPtr.all(Position).BinVal.all = BinVal then
-- Usage: When count bins are equal, merge them.
CovBinPtr.all(Position).AtLeast := CovBinPtr.all(Position).AtLeast + AtLeast ;
CovBinPtr.all(Position).Weight := CovBinPtr.all(Position).Weight + Weight ;
CovBinPtr.all(Position).Count := CovBinPtr.all(Position).Count + Count ;
CovBinPtr.all(Position).PercentCov :=
real(CovBinPtr.all(Position).Count)*100.0/maximum(real(CovBinPtr.all(Position).AtLeast), 1.0) ;
else
-- Usage: Count bin inside a previous count bin is an error, unless COUNT_ALL
-- ?? Can we run into this algorithmically? - if so can add variable to allow it
-- if CountMode /= COUNT_ALL then -- this check is redundant
report "InsertBin (AddBins/AddCross): inserted count bin is a subset of prior count bin" severity failure ;
-- end if ;
end if;
else
-- Usage: Drop count bin when in either ignore or illegal bin
-- Facilitates capture of count bins
null ; -- quietly drop the bin
end if ;
elsif ACTION = COV_IGNORE then
-- Usage: Most likely an error.
-- Potential: fine grain entry of catch-all ignore bins
-- However, ignore bins are non-signaling, so fine grain entry not useful
report "InsertBin (AddBins/AddCross): inserted ignore bin dropped. It is a subset of prior bin" severity error ;
-- null ; -- quietly drop the bin
elsif ACTION = COV_ILLEGAL then
-- Usage: fine grain entry of catch-all illegal bins,
-- Illegal bins are signaling. Drop the ones with overlap.
report "InsertBin (AddBins/AddCross): inserted illegal bin dropped. It is a subset of prior bin" severity error ;
-- null ; -- quietly drop the bin
end if ;
end procedure InsertBin ;
------------------------------------------------------------
procedure AddBins (
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) is
variable calcAtLeast : integer ;
variable calcWeight : integer ;
begin
CheckBinValLength( 1, "AddBins") ;
GrowBins(CovBin'length) ;
for i in CovBin'range loop
if CovBin(i).Action = COV_COUNT then
calcAtLeast := maximum(AtLeast, CovBin(i).AtLeast) ;
calcWeight := maximum(Weight, CovBin(i).Weight) ;
else
calcAtLeast := 0 ;
calcWeight := 0 ;
end if ;
InsertBin(
BinVal => CovBin(i).BinVal,
Action => CovBin(i).Action,
Count => CovBin(i).Count,
AtLeast => calcAtLeast,
Weight => calcWeight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (AtLeast : integer ; CovBin : CovBinType) is
------------------------------------------------------------
begin
AddBins(AtLeast, 0, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovBinType) is
------------------------------------------------------------
begin
AddBins(0, 0, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddCross(
-- Cross existing bins
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
constant BIN_LENS : integer_vector :=
BinLengths(
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable calcAction, calcCount, calcAtLeast, calcWeight : integer ;
variable calcBinVal : RangeArrayType(BinIndex'range) ;
begin
CheckBinValLength( BIN_LENS'length, "AddCross") ;
GrowBins(NUM_NEW_BINS) ;
calcCount := 0 ;
for MatrixIndex in 1 to NUM_NEW_BINS loop
CrossBins := ConcatenateBins(BinIndex,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
calcAction := MergeState(CrossBins) ;
calcBinVal := MergeBinVal(CrossBins) ;
calcAtLeast := MergeAtLeast( calcAction, AtLeast, CrossBins) ;
calcWeight := MergeWeight ( calcAction, Weight, CrossBins) ;
InsertBin(calcBinVal, calcAction, calcCount, calcAtLeast, calcWeight) ;
IncBinIndex( BinIndex, BIN_LENS) ; -- increment right most one, then if overflow, increment next
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
-- Cross existing bins
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(AtLeast, 0,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
-- Cross existing bins
------------------------------------------------------------
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(0, 0,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
begin
for i in 1 to NumBins loop
deallocate(CovBinPtr(i).BinVal) ;
end loop ;
deallocate(CovBinPtr) ;
DeallocateName ;
-- Restore internal variables to their default values
NumBins := 0 ;
OrderCount := 0 ;
BinValLength := 1 ;
IllegalMode := ILLEGAL_ON ;
WeightMode := AT_LEAST ;
WeightScale := 1.0 ;
ThresholdingEnable := FALSE ;
CovThreshold := 45.0 ;
CovTarget := 100.0 ;
MergingEnable := FALSE ;
CountMode := COUNT_FIRST ;
-- RvSeedInit := FALSE ;
end procedure deallocate ;
------------------------------------------------------------
procedure ICover ( CovPoint : integer) is
------------------------------------------------------------
begin
ICover((1=> CovPoint)) ;
end procedure ICover ;
------------------------------------------------------------
procedure ICover( CovPoint : integer_vector) is
------------------------------------------------------------
begin
CovLoop : for i in 1 to NumBins loop
-- skip this CovBin if CovPoint is not in it
next CovLoop when not inside(CovPoint, CovBinPtr(i).BinVal.all) ;
-- found CovPoint in this CovBin, run this code and exit.
CovBinPtr(i).Count := CovBinPtr(i).Count + CovBinPtr(i).action ;
-- place holder for actions to do to weight vector
CovBinPtr(i).PercentCov := real(CovBinPtr(i).Count)*100.0/maximum(real(CovBinPtr(i).AtLeast), 1.0) ;
-- OrderCount handling
OrderCount := OrderCount + 1 ;
CovBinPtr(i).OrderCount := OrderCount + CovBinPtr(i).OrderCount ;
if CovBinPtr(i).action = COV_ILLEGAL and IllegalMode /= ILLEGAL_OFF then
write(OUTPUT, "%%Illegal Value: " ) ;
write(OUTPUT, CovPoint) ;
write(OUTPUT, " is in an illegal Bin. " & "Time: " & time'image(now) & LF) ;
if IllegalMode = ILLEGAL_FAILURE then
report "Illegal Value" severity failure ;
end if ;
end if ;
exit CovLoop when CountMode = COUNT_FIRST ; -- only find first one
end loop CovLoop ;
end procedure ICover ;
------------------------------------------------------------
procedure SetCovZero is
------------------------------------------------------------
begin
for i in 1 to NumBins loop
CovBinPtr(i).Count := 0 ;
CovBinPtr(i).PercentCov := 0.0 ;
CovBinPtr(i).OrderCount := 0 ;
end loop ;
OrderCount := 0 ;
end procedure SetCovZero ;
------------------------------------------------------------
impure function IsInitialized return boolean is
------------------------------------------------------------
begin
return NumBins > 0 ;
end function IsInitialized ;
------------------------------------------------------------
impure function GetNumBins return integer is
------------------------------------------------------------
begin
return NumBins ;
end function GetNumBins ;
------------------------------------------------------------
impure function GetMinIndex return integer is
------------------------------------------------------------
variable MinCov : real := real'right ; -- big number
variable MinIndex : integer := NumBins ;
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < MinCov then
MinCov := CovBinPtr(i).PercentCov ;
MinIndex := i ;
end if ;
end loop CovLoop ;
return MinIndex ;
end function GetMinIndex ;
------------------------------------------------------------
impure function GetMinCov return real is
------------------------------------------------------------
variable MinCov : real := real'right ; -- big number
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < MinCov then
MinCov := CovBinPtr(i).PercentCov ;
end if ;
end loop CovLoop ;
return MinCov ;
end function GetMinCov ;
------------------------------------------------------------
impure function GetMinCount return integer is
------------------------------------------------------------
variable MinCount : integer := integer'right ; -- big number
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < MinCount then
MinCount := CovBinPtr(i).Count ;
end if ;
end loop CovLoop ;
return MinCount ;
end function GetMinCount ;
------------------------------------------------------------
impure function GetMaxIndex return integer is
------------------------------------------------------------
variable MaxCov : real := 0.0 ;
variable MaxIndex : integer := NumBins ;
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov > MaxCov then
MaxCov := CovBinPtr(i).PercentCov ;
MaxIndex := i ;
end if ;
end loop CovLoop ;
return MaxIndex ;
end function GetMaxIndex ;
------------------------------------------------------------
impure function GetMaxCov return real is
------------------------------------------------------------
variable MaxCov : real := 0.0 ;
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov > MaxCov then
MaxCov := CovBinPtr(i).PercentCov ;
end if ;
end loop CovLoop ;
return MaxCov ;
end function GetMaxCov ;
------------------------------------------------------------
impure function GetMaxCount return integer is
------------------------------------------------------------
variable MaxCount : integer := 0 ;
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count > MaxCount then
MaxCount := CovBinPtr(i).Count ;
end if ;
end loop CovLoop ;
return MaxCount ;
end function GetMaxCount ;
------------------------------------------------------------
impure function CountCovHoles ( PercentCov : real ) return integer is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < PercentCov then
HoleCount := HoleCount + 1 ;
end if ;
end loop CovLoop ;
return HoleCount ;
end function CountCovHoles ;
------------------------------------------------------------
impure function CountCovHoles return integer is
------------------------------------------------------------
begin
return CountCovHoles(CovTarget) ;
end function CountCovHoles ;
------------------------------------------------------------
impure function IsCovered ( PercentCov : real ) return boolean is
------------------------------------------------------------
begin
-- assert NumBins >= 1 report "IsCovered: Empty Coverage Model" severity failure ;
return CountCovHoles(PercentCov) = 0 ;
end function IsCovered ;
------------------------------------------------------------
impure function IsCovered return boolean is
------------------------------------------------------------
begin
-- assert NumBins >= 1 report "IsCovered: Empty Coverage Model" severity failure ;
return CountCovHoles(CovTarget) = 0 ;
end function IsCovered ;
------------------------------------------------------------
impure function GetCov return real is
------------------------------------------------------------
variable TotalCovGoal, TotalCovCount : integer := 0 ;
begin
BinLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT then
TotalCovGoal := TotalCovGoal + CovBinPtr(i).AtLeast ;
if CovBinPtr(i).Count <= CovBinPtr(i).AtLeast then
TotalCovCount := TotalCovCount + CovBinPtr(i).Count ;
else
-- do not count the extra values that exceed their cov goal
TotalCovCount := TotalCovCount + CovBinPtr(i).AtLeast ;
end if ;
end if ;
end loop BinLoop ;
return 100.0 * real(TotalCovCount) / real(TotalCovGoal) ;
end function GetCov ;
------------------------------------------------------------
impure function GetHoleBinVal ( ReqHoleNum : integer ; CovTargetPercent : real ) return RangeArrayType is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < CovTargetPercent then
HoleCount := HoleCount + 1 ;
if HoleCount = ReqHoleNum then
return CovBinPtr(i).BinVal.all ;
end if ;
end if ;
end loop CovLoop ;
write(OUTPUT, "%%Error GetHoleBinVal did not find hole. " &
"HoleCount = " & integer'image(HoleCount) &
"ReqHoleNum = " & integer'image(ReqHoleNum) & LF) ;
return CovBinPtr(NumBins).BinVal.all ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( CovTargetPercent : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(1, CovTargetPercent) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ReqHoleNum, CovTarget) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function CalcWeight ( BinIndex : integer ; MaxCovPercent : real ) return integer is
-- pt local
------------------------------------------------------------
begin
case WeightMode is
when AT_LEAST => -- AtLeast
return CovBinPtr(BinIndex).AtLeast ;
when WEIGHT => -- Weight
return CovBinPtr(BinIndex).Weight ;
when REMAIN => -- (Adjust * AtLeast) - Count
return integer( Ceil( MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovBinPtr(BinIndex).Count ;
when REMAIN_EXP => -- Weight * (REMAIN **WeightScale)
-- Experimental may be removed
-- CAUTION: for large numbers and/or WeightScale > 2.0, result can be > 2**31 (max integer value)
-- both Weight and WeightScale default to 1
return CovBinPtr(BinIndex).Weight *
integer( Ceil (
( (MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0) -
real(CovBinPtr(BinIndex).Count) ) ** WeightScale ) );
when REMAIN_SCALED => -- (WeightScale * Adjust * AtLeast) - Count
-- Experimental may be removed
-- Biases remainder toward AT_LEAST value.
-- WeightScale must be > 1.0
return integer( Ceil( WeightScale * MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovBinPtr(BinIndex).Count ;
when REMAIN_WEIGHT => -- Weight * ((WeightScale * Adjust * AtLeast) - Count)
-- Experimental may be removed
-- WeightScale must be > 1.0
return CovBinPtr(BinIndex).Weight * (
integer( Ceil( WeightScale * MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovBinPtr(BinIndex).Count) ;
end case ;
end function CalcWeight ;
------------------------------------------------------------
impure function RandHoleIndex ( CovTargetPercent : real ) return integer is
-- pt local
------------------------------------------------------------
variable WeightVec : integer_vector(0 to NumBins-1) ; -- Prep for change to DistInt
variable MaxCovPercent : real ;
variable MinCovPercent : real ;
begin
MinCovPercent := GetMinCov ;
if ThresholdingEnable then
MaxCovPercent := MinCovPercent + CovThreshold ;
if MinCovPercent < CovTargetPercent then
-- Clip at CovTargetPercent until reach CovTargetPercent
MaxCovPercent := minimum(MaxCovPercent, CovTargetPercent);
end if ;
else
if MinCovPercent < CovTargetPercent then
MaxCovPercent := CovTargetPercent ;
else
-- Done, Enable all bins
MaxCovPercent := GetMaxCov + 1.0 ;
-- MaxCovPercent := real'right ; -- weight scale issues
end if ;
end if ;
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < MaxCovPercent then
-- Calculate Weight based on WeightMode
-- Scale to current percentage goal: MaxCov which can be < or > 100.0
WeightVec(i-1) := CalcWeight(i, MaxCovPercent) ;
else
WeightVec(i-1) := 0 ;
end if ;
end loop CovLoop ;
-- DistInt returns integer range 0 to Numbins-1
-- Caution: DistInt can fail when sum(WeightVec) > 2**31
-- See notes in CalcWeight for REMAIN_EXP
return 1 + RV.DistInt( WeightVec ) ; -- return range 1 to NumBins
end function RandHoleIndex ;
------------------------------------------------------------
impure function GetBinVal ( BinIndex : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return CovBinPtr( BinIndex ).BinVal.all ;
end function GetBinVal ;
------------------------------------------------------------
impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return CovBinPtr( RandHoleIndex(PercentCov) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
impure function RandCovBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return CovBinPtr( RandHoleIndex( CovTarget ) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
impure function GetMinBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetBinVal( GetMinIndex ) ;
end function GetMinBinVal ;
------------------------------------------------------------
impure function GetMaxBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetBinVal( GetMaxIndex ) ;
end function GetMaxBinVal ;
------------------------------------------------------------
-- impure function RandCovPoint( BinVal : RangeArrayType ) return integer_vector is
impure function ToRandPoint( BinVal : RangeArrayType ) return integer_vector is
-- pt local
------------------------------------------------------------
variable CovPoint : integer_vector(BinVal'range) ;
variable normCovPoint : integer_vector(1 to BinVal'length) ;
begin
for i in BinVal'range loop
CovPoint(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ;
end loop ;
normCovPoint := CovPoint ;
return normCovPoint ;
end function ToRandPoint ;
------------------------------------------------------------
impure function ToRandPoint( BinVal : RangeArrayType ) return integer is
-- pt local
------------------------------------------------------------
begin
return RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
end function ToRandPoint ;
------------------------------------------------------------
impure function RandCovPoint return integer is
------------------------------------------------------------
begin
return ToRandPoint(RandCovBinVal(CovTarget)) ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(RandCovBinVal(PercentCov)) ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(RandCovBinVal(CovTarget)) ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint ( PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(RandCovBinVal(PercentCov)) ;
end function RandCovPoint ;
------------------------------------------------------------
impure function GetPoint ( BinIndex : integer ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(GetBinVal(BinIndex)) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetPoint ( BinIndex : integer ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(GetBinVal(BinIndex)) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetMinPoint return integer is
------------------------------------------------------------
begin
return ToRandPoint(GetBinVal( GetMinIndex )) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMinPoint return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(GetBinVal( GetMinIndex )) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMaxPoint return integer is
------------------------------------------------------------
begin
return ToRandPoint(GetBinVal( GetMaxIndex )) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetMaxPoint return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(GetBinVal( GetMaxIndex )) ;
end function GetMaxPoint ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
variable result : CovBinBaseType ;
begin
result.BinVal := ALL_RANGE;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBinInfo ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength return integer is
-- ------------------------------------------------------------
begin
return BinValLength ;
end function GetBinValLength ;
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
variable result : CovBinBaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix2BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix3BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix4BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix5BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix6BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix7BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix8BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix9BaseType ;
begin
result.BinVal := CovBinPtr(BinIndex).BinVal.all;
result.Action := CovBinPtr(BinIndex).Action;
result.Count := CovBinPtr(BinIndex).Count;
result.AtLeast := CovBinPtr(BinIndex).AtLeast;
result.Weight := CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
------------------------------------------------------------
-- pt local for now -- file formal parameter not allowed with method
procedure WriteBin ( file f : text ) is
------------------------------------------------------------
begin
WriteBinName(f, "WriteBin: ") ;
if NumBins < 1 then
Write(f, "%%FATAL, Coverage Model is empty. Nothing to print." & LF ) ;
report "Coverage model is empty. Nothing to print." severity failure ;
end if ;
for i in 1 to NumBins loop -- CovBinPtr.all'range
if CovBinPtr(i).count < 0 then
write(f, "%%Illegal Bin:") ;
write(f, CovBinPtr(i).BinVal.all) ;
write(f, " Count = " & integer'image(-CovBinPtr(i).count)) ;
write(f, "" & LF) ;
elsif CovBinPtr(i).action = COV_COUNT then
write(f, "%% Bin:") ;
write(f, CovBinPtr(i).BinVal.all) ;
write(f, " Count = " & integer'image(CovBinPtr(i).count)) ;
write(f, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ;
if WeightMode = WEIGHT or WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(f, " Weight = " & integer'image(CovBinPtr(i).Weight)) ;
end if ;
write(f, "" & LF) ;
end if ;
end loop ;
write(f, "" & LF) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin is
------------------------------------------------------------
begin
if WriteBinFileInit then
WriteBin(WriteBinFile) ;
else
WriteBin(OUTPUT) ;
end if ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin (FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file BinFile : text open OpenKind is FileName ;
begin
WriteBin(BinFile) ;
end procedure WriteBin ;
------------------------------------------------------------
-- Development only
-- pt local for now -- file formal parameter not allowed with method
procedure DumpBin ( file f : text ) is
------------------------------------------------------------
begin
WriteBinName(f, "DumpBin: ") ;
-- if NumBins < 1 then
-- Write(f, "%%FATAL, Coverage Model is empty. Nothing to print." & LF ) ;
-- end if ;
for i in 1 to NumBins loop -- CovBinPtr.all'range
write(f, "%% Bin:") ;
write(f, CovBinPtr(i).BinVal.all) ;
case CovBinPtr(i).action is
when COV_COUNT => write(f, " Count = ") ;
when COV_IGNORE => write(f, " Ignore = ") ;
when COV_ILLEGAL => write(f, " Illegal = ") ;
when others => write(f, " BOGUS BOGUS BOGUS = ") ;
end case ;
write(f, integer'image(CovBinPtr(i).count)) ;
-- write(f, " Count = " & integer'image(CovBinPtr(i).count)) ;
write(f, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ;
write(f, " Weight = " & integer'image(CovBinPtr(i).Weight)) ;
write(f, " OrderCount = " & integer'image(CovBinPtr(i).OrderCount)) ;
if CovBinPtr(i).count > 0 then
write(f, " Normalized OrderCount = " & integer'image(CovBinPtr(i).OrderCount/CovBinPtr(i).count)) ;
end if ;
write(f, "" & LF) ;
end loop ;
write(f, "" & LF) ;
end procedure DumpBin ;
------------------------------------------------------------
procedure DumpBin is
------------------------------------------------------------
begin
if WriteBinFileInit then
DumpBin(WriteBinFile) ;
else
DumpBin(OUTPUT) ;
end if ;
end procedure DumpBin ;
------------------------------------------------------------
-- pt local
procedure WriteCovHoles ( file f : text; PercentCov : real := 100.0 ) is
------------------------------------------------------------
begin
WriteBinName(f, "WriteCovHoles: ") ;
if NumBins < 1 then
Write(f, "%%FATAL, Coverage Model is empty. Nothing to print." & LF ) ;
report "Coverage model is empty. Nothing to print." severity failure ;
end if ;
CovLoop : for i in 1 to NumBins loop
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < PercentCov then
write(f, "%% Bin:") ;
write(f, CovBinPtr(i).BinVal.all) ;
write(f, " Count = " & integer'image(CovBinPtr(i).Count)) ;
write(f, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ;
if WeightMode = WEIGHT or WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(f, " Weight = " & integer'image(CovBinPtr(i).Weight)) ;
end if ;
write(f, "" & LF) ;
end if ;
end loop CovLoop ;
write(f, "" & LF) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles is
------------------------------------------------------------
begin
if WriteBinFileInit then
WriteCovHoles(WriteBinFile, CovTarget) ;
else
WriteCovHoles(OUTPUT, CovTarget) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( PercentCov : real ) is
------------------------------------------------------------
begin
if WriteBinFileInit then
WriteCovHoles(WriteBinFile, PercentCov) ;
else
WriteCovHoles(OUTPUT, PercentCov) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
begin
WriteCovHoles(CovHoleFile, CovTarget) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
begin
WriteCovHoles(CovHoleFile, PercentCov) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- pt local
impure function FindBin (
------------------------------------------------------------
BinVal : RangeArrayType ;
Action : integer
) return integer is
begin
for i in 1 to NumBins loop
if BinVal = CovBinPtr(i).BinVal.all and Action = CovBinPtr(i).Action then
return i ;
end if;
end loop ;
return 0 ;
end function FindBin ;
------------------------------------------------------------
-- pt local
procedure ReadCovVars (file CovDbFile : text; Good : out boolean ) is
------------------------------------------------------------
variable buf : line ;
variable Empty : boolean ;
variable ReadValid : boolean ;
variable GoodLoop1 : boolean ;
variable iSeed : RandomSeedType ;
variable iIllegalMode : integer ;
variable iWeightMode : integer ;
variable iWeightScale : real ;
variable iCovThreshold : real ;
variable iCountMode : integer ;
variable iNumberOfNames : integer ;
variable iThresholdingEnable : boolean ;
variable iCovTarget : real ;
variable iMergingEnable : boolean ;
begin
ReadLoop1 : while not EndFile(CovDbFile) loop
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty) ;
next when Empty ;
read(buf, iSeed, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading Seed") ;
RV.SetSeed( iSeed ) ;
RvSeedInit := TRUE ;
read(buf, iCovThreshold, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading CovThreshold") ;
CovThreshold := iCovThreshold ;
read(buf, iIllegalMode, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading IllegalMode") ;
IllegalMode := IllegalModeType'val( iIllegalMode ) ;
read(buf, iWeightMode, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading WeightMode") ;
WeightMode := WeightModeType'val( iWeightMode ) ;
read(buf, iWeightScale, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading WeightScale") ;
WeightScale := iWeightScale ;
read(buf, iCountMode, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading CountMode") ;
CountMode := CountModeType'val( iCountMode ) ;
read(buf, iThresholdingEnable, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading CountMode") ;
ThresholdingEnable := iThresholdingEnable ;
read(buf, iCovTarget, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading CountMode") ;
CovTarget := iCovTarget ;
read(buf, iMergingEnable, ReadValid) ;
exit ReadLoop1 when failed(not ReadValid, "ReadCovDb: Failed while reading CountMode") ;
MergingEnable := iMergingEnable ;
exit ReadLoop1 ;
end loop ReadLoop1 ;
GoodLoop1 := ReadValid ;
ReadLoop2 : while not EndFile(CovDbFile) loop
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty) ;
next when Empty ;
read(buf, iNumberOfNames, ReadValid) ;
exit ReadLoop2 when failed(not ReadValid, "ReadCovDb: Failed while reading NumberOfNames") ;
for i in 1 to iNumberOfNames loop
ReadLine(CovDbFile, buf) ;
SetName(buf.all) ;
end loop ;
exit ReadLoop2 ;
end loop ReadLoop2 ;
Good := ReadValid and GoodLoop1 ;
end procedure ReadCovVars ;
------------------------------------------------------------
-- pt local
procedure ReadCovDbInfo (
------------------------------------------------------------
File CovDbFile : text ;
variable NumRangeItems : out integer ;
variable NumLines : out integer ;
variable Good : out boolean
) is
variable buf : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
begin
ReadLoop : while not EndFile(CovDbFile) loop
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty) ;
next when Empty ;
read(buf, NumRangeItems, ReadValid) ;
exit ReadLoop when failed(not ReadValid, "ReadCovDb: Failed while reading NumRangeItems") ;
read(buf, NumLines, ReadValid) ;
assert ReadValid
report "ReadCovDb: Failed while reading NumLines"
severity failure ;
exit ;
end loop ReadLoop ;
Good := ReadValid ;
end procedure ReadCovDbInfo ;
------------------------------------------------------------
-- pt local
procedure ReadCovDb (
------------------------------------------------------------
File CovDbFile : text ;
constant NumRangeItems : in integer ;
constant NumLines : in integer ;
variable Good : out boolean
) is
variable buf : line ;
variable Empty : boolean ;
variable ReadValid : boolean ;
-- Format: Action Count min1 max1 min2 max2 ....
variable Action : integer ;
variable Count : integer ;
variable BinVal : RangeArrayType(1 to NumRangeItems) ;
variable index : integer ;
variable AtLeast : integer ;
variable Weight : integer ;
variable PercentCov : real ;
begin
GrowBins(NumLines) ;
ReadLoop : for i in 1 to NumLines loop
exit ReadLoop when failed(EndFile(CovDbFile), "ReadCovDb: Did not read specified number of lines") ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty) ;
next when Empty ; -- replace with EmptyLine(buf)
read(buf, Action, ReadValid) ;
exit ReadLoop when failed(not ReadValid, "ReadCovDb: Failed while reading Action") ;
read(buf, Count, ReadValid) ;
exit ReadLoop when failed(not ReadValid, "ReadCovDb: Failed while reading Count") ;
read(buf, AtLeast, ReadValid) ;
exit ReadLoop when failed(not ReadValid, "ReadCovDb: Failed while reading AtLeast") ;
read(buf, Weight, ReadValid) ;
exit ReadLoop when failed(not ReadValid, "ReadCovDb: Failed while reading Weight") ;
read(buf, PercentCov, ReadValid) ;
exit ReadLoop when failed(not ReadValid, "ReadCovDb: Failed while reading PercentCov") ;
read(buf, BinVal, ReadValid) ;
exit ReadLoop when failed(not ReadValid, "ReadCovDb: Failed while reading BinVal") ;
index := FindBin(BinVal, Action) ;
if index > 0 then -- found it.
-- Should count add to current count?
CovBinPtr(index).Count := Count ;
else
InsertBin(BinVal, Action, Count, AtLeast, Weight, PercentCov) ;
end if ;
end loop ReadLoop ;
Good := ReadValid ;
end ReadCovDb ;
------------------------------------------------------------
-- pt local
procedure ReadCovDb ( File CovDbFile : text ) is
-- procedure ReadCovDb (FileName : string) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
-- file CovDbFile : text open READ_MODE is FileName ;
variable NumRangeItems : integer ;
variable NumLines : integer ;
variable ReadValid : boolean ;
begin
ReadLoop : loop
-- Read coverage private variables to the file
ReadCovVars(CovDbFile, ReadValid) ;
exit when not ReadValid ;
-- Get Coverage dimensions and number of items in file.
ReadCovDbInfo(CovDbFile, NumRangeItems, NumLines, ReadValid) ;
exit when not ReadValid ;
-- Read the file
ReadCovDb(CovDbFile, NumRangeItems, NumLines, ReadValid) ;
exit ;
end loop ReadLoop ;
end ReadCovDb ;
------------------------------------------------------------
procedure ReadCovDb (FileName : string) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file CovDbFile : text open READ_MODE is FileName ;
begin
ReadCovDb(CovDbFile) ;
end procedure ReadCovDb ;
------------------------------------------------------------
-- pt local
procedure WriteCovVars (file CovDbFile : text ) is
------------------------------------------------------------
variable buf : line ;
begin
-- write coverage private variables to the file
write(buf, RV.GetSeed ) ;
write(buf, ' ') ;
write(buf, CovThreshold) ;
write(buf, ' ') ;
write(buf, IllegalModeType'pos(IllegalMode)) ;
write(buf, ' ') ;
write(buf, WeightModeType'pos(WeightMode)) ;
write(buf, ' ') ;
write(buf, WeightScale) ;
write(buf, ' ') ;
write(buf, CountModeType'pos(CountMode)) ;
write(buf, ' ') ;
write(buf, ThresholdingEnable) ; -- boolean
write(buf, ' ') ;
write(buf, CovTarget) ; -- Real
write(buf, ' ') ;
write(buf, MergingEnable) ; -- boolean
write(buf, ' ') ;
writeline(CovDbFile, buf) ;
write(buf, NumberOfNames ) ;
writeline(CovDbFile, buf) ;
WriteBinName(CovDbFile, "", "") ;
end procedure WriteCovVars ;
------------------------------------------------------------
-- pt local
procedure WriteCovDb (file CovDbFile : text ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
variable buf : line ;
begin
-- write Cover variables to the file
WriteCovVars( CovDbFile ) ;
-- write NumRangeItems, NumLines
write(buf, CovBinPtr(1).BinVal'length) ;
write(buf, ' ') ;
write(buf, NumBins) ;
write(buf, ' ') ;
writeline(CovDbFile, buf) ;
-- write coverage to a file
writeloop : for LineCount in 1 to NumBins loop
write(buf, CovBinPtr(LineCount).Action) ;
write(buf, ' ') ;
write(buf, CovBinPtr(LineCount).Count) ;
write(buf, ' ') ;
write(buf, CovBinPtr(LineCount).AtLeast) ;
write(buf, ' ') ;
write(buf, CovBinPtr(LineCount).Weight) ;
write(buf, ' ') ;
write(buf, CovBinPtr(LineCount).PercentCov) ;
write(buf, ' ') ;
write(buf, CovBinPtr(LineCount).BinVal.all) ;
writeline(CovDbFile, buf) ;
end loop WriteLoop ;
end procedure WriteCovDb ;
------------------------------------------------------------
procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file CovDbFile : text open OpenKind is FileName ;
begin
WriteCovDb(CovDbFile) ;
end procedure WriteCovDb ;
-- ------------------------------------------------------------
-- procedure WriteCovDb is
-- ------------------------------------------------------------
-- begin
-- if WriteCovDbFileInit then
-- WriteCovDb(WriteCovDbFile) ;
-- else
-- report "CoveragePkg: WriteCovDb file not specified" severity failure ;
-- end if ;
-- end procedure WriteCovDb ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable ErrorCnt : integer := 0 ;
begin
if NumBins < 1 then
return 1 ; -- return error if model empty
else
for i in 1 to NumBins loop
if CovBinPtr(i).count < 0 then -- illegal CovBin
ErrorCnt := ErrorCnt + CovBinPtr(i).count ;
end if ;
end loop ;
return - ErrorCnt ;
end if ;
end function GetErrorCount ;
------------------------------------------------------------
-- These support the older AddBins(GenCross(...)) methodology
-- which has been replaced by AddCross
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix2Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix3Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix4Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix5Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix6Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix7Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix8Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix9Type) is
------------------------------------------------------------
begin
GrowBins(CovBin'length) ;
for i in CovBin'range loop
InsertBin(
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight
) ;
end loop ;
end procedure AddBins ;
-- ------------------------------------------------------------
-- ------------------------------------------------------------
-- Deprecated. Due to name changes to promote greater consistency
-- Maintained for backward compatibility.
-- ------------------------------------------------------------
------------------------------------------------------------
impure function CovBinErrCnt return integer is
-- Deprecated. Name changed to ErrorCount for package to package consistency
------------------------------------------------------------
begin
return GetErrorCount ;
end function CovBinErrCnt ;
------------------------------------------------------------
-- Deprecated. Same as RandCovBinVal
impure function RandCovHole ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(PercentCov) ;
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. Same as RandCovBinVal
impure function RandCovHole return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal ;
end function RandCovHole ;
-- GetCovHole replaced by GetHoleBinVal
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ReqHoleNum, PercentCov) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(PercentCov) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ReqHoleNum) ;
end function GetCovHole ;
-- ------------------------------------------------------------
-- ------------------------------------------------------------
-- Deprecated / Subsumed by versions with PercentCov Parameter
-- Maintained for backward compatibility only and
-- may be removed in the future.
-- ------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Replaced by SetName with multi-line support
procedure SetItemName (ItemNameIn : String) is
------------------------------------------------------------
begin
SetName(ItemNameIn) ;
end procedure SetItemName ;
------------------------------------------------------------
-- Deprecated. Same as GetMinCount
impure function GetMinCov return integer is
------------------------------------------------------------
begin
return GetMinCount ;
end function GetMinCov ;
------------------------------------------------------------
-- Deprecated. Same as GetMaxCount
impure function GetMaxCov return integer is
------------------------------------------------------------
begin
return GetMaxCount ;
end function GetMaxCov ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function CountCovHoles ( AtLeast : integer ) return integer is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to NumBins loop
-- if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < minimum(AtLeast, CovBinPtr(i).AtLeast) then
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < AtLeast then
HoleCount := HoleCount + 1 ;
end if ;
end loop CovLoop ;
return HoleCount ;
end function CountCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function IsCovered ( AtLeast : integer ) return boolean is
------------------------------------------------------------
begin
return CountCovHoles(AtLeast) = 0 ;
end function IsCovered ;
------------------------------------------------------------
impure function CalcWeight ( BinIndex : integer ; MaxAtLeast : integer ) return integer is
-- pt local
------------------------------------------------------------
begin
case WeightMode is
when AT_LEAST =>
return CovBinPtr(BinIndex).AtLeast ;
when WEIGHT =>
return CovBinPtr(BinIndex).Weight ;
when REMAIN =>
return MaxAtLeast - CovBinPtr(BinIndex).Count ;
when REMAIN_SCALED =>
-- Experimental may be removed
return integer( Ceil( WeightScale * real(MaxAtLeast))) -
CovBinPtr(BinIndex).Count ;
when REMAIN_WEIGHT =>
-- Experimental may be removed
return CovBinPtr(BinIndex).Weight * (
integer( Ceil( WeightScale * real(MaxAtLeast))) -
CovBinPtr(BinIndex).Count ) ;
when others =>
report "Selected Weight Mode not Supported with depricated RandCovPoint(AtLeast), see RandCovPoint(PercentCov)"
severity failure ;
return MaxAtLeast - CovBinPtr(BinIndex).Count ;
end case ;
end function CalcWeight ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
-- If keep this, need to be able to scale AtLeast Value
impure function RandHoleIndex ( AtLeast : integer ) return integer is
-- pt local
------------------------------------------------------------
variable WeightVec : integer_vector(0 to NumBins-1) ; -- Prep for change to DistInt
variable MinCount, AdjAtLeast, MaxAtLeast : integer ;
begin
MinCount := GetMinCov ;
-- iAtLeast := integer(ceil(CovTarget * real(AtLeast)/100.0)) ;
if ThresholdingEnable then
AdjAtLeast := MinCount + integer(CovThreshold) + 1 ;
if MinCount < AtLeast then
-- Clip at AtLeast until reach AtLeast
AdjAtLeast := minimum(AdjAtLeast, AtLeast) ;
end if ;
else
if MinCount < AtLeast then
AdjAtLeast := AtLeast ; -- Valid
else
-- Done, Enable all bins
-- AdjAtLeast := integer'right ; -- Get All
AdjAtLeast := GetMaxCov + 1 ; -- Get All
end if ;
end if;
MaxAtLeast := AdjAtLeast ;
CovLoop : for i in 1 to NumBins loop
-- if not ThresholdingEnable then
-- -- When not thresholding, consider bin Bin.AtLeast
-- -- iBinAtLeast := integer(ceil(CovTarget * real(CovBinPtr(i).AtLeast)/100.0)) ;
-- MaxAtLeast := maximum(AdjAtLeast, CovBinPtr(i).AtLeast) ;
-- end if ;
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < MaxAtLeast then
WeightVec(i-1) := CalcWeight(i, MaxAtLeast ) ; -- CovBinPtr(i).Weight ;
else
WeightVec(i-1) := 0 ;
end if ;
end loop CovLoop ;
-- DistInt returns integer range 0 to Numbins-1
return 1 + RV.DistInt( WeightVec ) ; -- return range 1 to NumBins
end function RandHoleIndex ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovBinVal (AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return CovBinPtr( RandHoleIndex(AtLeast) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
-- Maintained for backward compatibility. Repeated until aliases work for methods
------------------------------------------------------------
-- Deprecated+ New versions use PercentCov. Name change.
impure function RandCovHole (AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(AtLeast) ; -- GetBinVal
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovPoint (AtLeast : integer ) return integer is
------------------------------------------------------------
variable BinVal : RangeArrayType(1 to 1) ;
begin
BinVal := RandCovBinVal(AtLeast) ;
return RV.RandInt(BinVal(1).min, BinVal(1).max) ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint (AtLeast : integer ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(RandCovBinVal(AtLeast)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function GetHoleBinVal ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to NumBins loop
-- if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < minimum(AtLeast, CovBinPtr(i).AtLeast) then
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < AtLeast then
HoleCount := HoleCount + 1 ;
if HoleCount = ReqHoleNum then
return CovBinPtr(i).BinVal.all ;
end if ;
end if ;
end loop CovLoop ;
write(OUTPUT, "%%Error GetHoleBinVal did not find hole. " &
"HoleCount = " & integer'image(HoleCount) &
"ReqHoleNum = " & integer'image(ReqHoleNum) & LF) ;
return CovBinPtr(NumBins).BinVal.all ;
end function GetHoleBinVal ;
------------------------------------------------------------
-- Deprecated+. New versions use PercentCov. Name Change.
impure function GetCovHole ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ReqHoleNum, AtLeast) ;
end function GetCovHole ;
------------------------------------------------------------
-- pt local
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( file f : text; AtLeast : integer ) is
------------------------------------------------------------
-- variable minAtLeast : integer ;
begin
WriteBinName(f, "WriteCovHoles: ") ;
if NumBins < 1 then
Write(f, "%%FATAL, Coverage Model is empty. Nothing to print." & LF ) ;
report "Coverage model is empty. Nothing to print." severity failure ;
end if ;
CovLoop : for i in 1 to NumBins loop
-- minAtLeast := minimum(AtLeast,CovBinPtr(i).AtLeast) ;
-- if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < minAtLeast then
if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < AtLeast then
write(f, "%% Bin:") ;
write(f, CovBinPtr(i).BinVal.all) ;
write(f, " Count = " & integer'image(CovBinPtr(i).Count)) ;
write(f, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ;
if WeightMode = WEIGHT or WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(f, " Weight = " & integer'image(CovBinPtr(i).Weight)) ;
end if;
write(f, "" & LF) ;
end if ;
end loop CovLoop ;
write(f, "" & LF) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( AtLeast : integer ) is
------------------------------------------------------------
begin
if WriteBinFileInit then
WriteCovHoles(WriteBinFile, AtLeast) ;
else
WriteCovHoles(OUTPUT, AtLeast) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
begin
WriteCovHoles(CovHoleFile, AtLeast) ;
end procedure WriteCovHoles ;
end protected body CovPType ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType ;
variable ErrorCount : inout integer
) is
variable NumBins1, NumBins2 : integer ;
variable BinInfo1, BinInfo2 : CovBinBaseType ;
variable BinVal1, BinVal2 : RangeArrayType(1 to Bin1.GetBinValLength) ;
begin
NumBins1 := Bin1.GetNumBins ;
NumBins2 := Bin2.GetNumBins ;
if (NumBins1 /= NumBins2) then
write(OUTPUT, "Bins have different lengths" & LF) ;
ErrorCount := ErrorCount + 1 ;
return ;
end if ;
for i in 1 to NumBins1 loop
BinInfo1 := Bin1.GetBinInfo(i) ;
BinInfo2 := Bin2.GetBinInfo(i) ;
BinVal1 := Bin1.GetBinVal(i) ;
BinVal2 := Bin2.GetBinVal(i) ;
if BinInfo1 /= BinInfo2 or BinVal1 /= BinVal2 then
ErrorCount := ErrorCount + 1 ;
write(OUTPUT, "%% Bin:" & integer'image(i) & " miscompare." & LF) ;
write(OUTPUT, "%% Bin1: ") ;
write(OUTPUT, BinVal1) ;
write(OUTPUT, " Action = " & integer'image(BinInfo1.action)) ;
write(OUTPUT, " Count = " & integer'image(BinInfo1.count)) ;
write(OUTPUT, " AtLeast = " & integer'image(BinInfo1.AtLeast)) ;
write(OUTPUT, " Weight = " & integer'image(BinInfo1.Weight)) ;
write(OUTPUT, ""& LF) ;
write(OUTPUT, "%% Bin2: ") ;
write(OUTPUT, BinVal2) ;
write(OUTPUT, " Action = " & integer'image(BinInfo2.action)) ;
write(OUTPUT, " Count = " & integer'image(BinInfo2.count)) ;
write(OUTPUT, " AtLeast = " & integer'image(BinInfo2.AtLeast)) ;
write(OUTPUT, " Weight = " & integer'image(BinInfo2.Weight)) ;
write(OUTPUT, ""& LF) ;
end if ;
end loop ;
end procedure CompareBins ;
------------------------------------------------------------
-- package local, Used by GenBin, IllegalBin, and IgnoreBin
function MakeBin(
------------------------------------------------------------
Min, Max : integer ;
NumBin : integer ;
AtLeast : integer ;
Weight : integer ;
Action : integer
) return CovBinType is
variable iCovBin : CovBinType(1 to NumBin) ;
variable TotalBins : integer ; -- either real or integer
variable rMax, rCurMin, rNextMin, rNumItemsInBin, rRemainingBins : real ; -- must be real
begin
if Min > Max then
report "MakeBin (GenBin, IllegalBin, IgnoreBin): Min must be <= Max"
severity failure ;
return NULL_BIN ;
elsif NumBin <= 0 then
report "MakeBin (GenBin, IllegalBin, IgnoreBin): NumBin must be <= 0"
severity failure ;
return NULL_BIN ;
elsif NumBin = 1 then
iCovBin(1) := (
BinVal => (1 => (Min, Max)),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
return iCovBin ;
else
rCurMin := real(Min) ;
rMax := real(Max) ;
rRemainingBins := (minimum( real(NumBin), rMax - rCurMin + 1.0 )) ;
TotalBins := integer(rRemainingBins) ;
for i in iCovBin'range loop
exit when rRemainingBins = 0.0 ;
rNumItemsInBin := trunc((rMax - rCurMin + 1.0) / rRemainingBins) ; -- can be too large
rNextMin := rCurMin + rNumItemsInBin ; -- can be 2**31
iCovBin(i) := (
BinVal => (1 => (integer(rCurMin), integer(rNextMin - 1.0))),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
rCurMin := rNextMin ;
rRemainingBins := rRemainingBins - 1.0 ;
end loop ;
return iCovBin(1 to TotalBins) ;
end if ;
end function MakeBin ;
-- Old version with bug
-- ------------------------------------------------------------
-- -- package local, Used by GenBin, IllegalBin, and IgnoreBin
-- function MakeBin(
-- ------------------------------------------------------------
-- Min, Max : integer ;
-- NumBin : integer ;
-- AtLeast : integer ;
-- Weight : integer ;
-- Action : integer
-- ) return CovBinType is
-- constant CheckParms : boolean := failed(Min > Max, "MakeBin (GenBin, IllegalBin, IgnoreBin): Min must be <= Max") ;
-- constant CALC_NUM_BINS : integer := minimum(NumBin, Max-Min+1) ;
-- variable iCovBin : CovBinType(0 to CALC_NUM_BINS -1) ;
-- variable CurMin, NextMin, RemainingBins, NumItemsInBin : integer ;
-- begin
-- CurMin := Min ;
-- for i in iCovBin'range loop
-- RemainingBins := CALC_NUM_BINS - i ;
-- NumItemsInBin := (Max - CurMin + 1) / RemainingBins ;
-- NextMin := CurMin + NumItemsInBin ;
-- iCovBin(i) := (
-- BinVal => (1 => (CurMin, NextMin - 1)),
-- Action => Action,
-- Count => 0,
-- Weight => Weight,
-- AtLeast => AtLeast
-- ) ;
-- CurMin := NextMin ;
-- end loop ;
-- return iCovBin ;
-- end function MakeBin ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType is
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => AtLeast,
Weight => Weight,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin(AtLeast : integer ; Min, Max, NumBin : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => AtLeast,
Weight => 1,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin( Min, Max, NumBin : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 1,
Weight => 1,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( Min, Max : integer) return CovBinType is
------------------------------------------------------------
begin
-- default, create a separate CovBin for each value
-- AtLeast and Weight = 1 (must use longer version to specify)
return MakeBin(
Min => Min,
Max => Max,
NumBin => Max - Min + 1,
AtLeast => 1,
Weight => 1,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( A : integer) return CovBinType is
------------------------------------------------------------
begin
-- default, create a separate CovBin for each value
-- AtLeast and Weight = 1 (must use longer version to specify)
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 1,
Weight => 1,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
------------------------------------------------------------
function IllegalBin ( Min, Max : integer ) return CovBinType is
------------------------------------------------------------
begin
-- default, generate one CovBin with the entire range of values
return MakeBin(
Min => Min,
Max => Max,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
------------------------------------------------------------
function IllegalBin ( A : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
----------------------------------------------------------
-- function IgnoreBin (
----------------------------------------------------------
-- AtLeast : integer ;
-- Weight : integer ;
-- Min, Max : integer ;
-- NumBin : integer
-- ) return CovBinType is
-- begin
-- return MakeBin(
-- Min => Min,
-- Max => Max,
-- NumBin => NumBin,
-- AtLeast => AtLeast,
-- Weight => Weight,
-- Action => COV_IGNORE
-- ) ;
-- end function IgnoreBin ;
----------------------------------------------------------
-- function IgnoreBin (AtLeast : integer ; Min, Max, NumBin : integer) return CovBinType is
----------------------------------------------------------
-- begin
-- return MakeBin(
-- Min => Min,
-- Max => Max,
-- NumBin => NumBin,
-- AtLeast => AtLeast,
-- Weight => 0,
-- Action => COV_IGNORE
-- ) ;
-- end function IgnoreBin ;
------------------------------------------------------------
function IgnoreBin (Min, Max, NumBin : integer) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function IgnoreBin (Min, Max : integer) return CovBinType is
------------------------------------------------------------
begin
-- default, generate one CovBin with the entire range of values
return MakeBin(
Min => Min,
Max => Max,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function IgnoreBin (A : integer) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function GenBin (
-- Manual entry format for CovBin within lots of extra parens
------------------------------------------------------------
ManualBin : CovBinManualType
) return CovBinType is
alias imBin : CovBinManualType (1 to ManualBin'length) is ManualBin ;
variable iCovBin : CovBinType(imBin'range) ;
begin
for i in iCovBin'range loop
iCovBin(i) := ( (1 => (imBin(i)(0),imBin(i)(1))), imBin(i)(2), 0, 1, 1) ;
end loop ;
return iCovBin ;
end function GenBin ;
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix2Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross(AtLeast : integer ; Bin1, Bin2 : CovBinType) return CovMatrix2Type is
-- Cross existing bins -- use AddCross instead
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2) ;
end function GenCross ;
------------------------------------------------------------
function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type is
-- Cross existing bins -- use AddCross instead
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix3Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2, Bin3) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2, Bin3) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix4Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix5Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix6Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix7Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix8Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix9Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is
------------------------------------------------------------
begin
return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
end function GenCross ;
------------------------------------------------------------
procedure increment( signal Count : inout integer ) is
------------------------------------------------------------
begin
Count <= Count + 1 ;
end procedure increment ;
------------------------------------------------------------
procedure increment( signal Count : inout integer ; enable : boolean ) is
------------------------------------------------------------
begin
if enable then
Count <= Count + 1 ;
end if ;
end procedure increment ;
------------------------------------------------------------
procedure increment( signal Count : inout integer ; enable : std_ulogic ) is
------------------------------------------------------------
begin
if to_x01(enable) = '1' then
Count <= Count + 1 ;
end if ;
end procedure increment ;
------------------------------------------------------------
function to_integer ( B : boolean ) return integer is
------------------------------------------------------------
begin
if B then
return 1 ;
else
return 0 ;
end if ;
end function to_integer ;
------------------------------------------------------------
function to_integer ( SL : std_logic ) return integer is
-------------------------------------------------------------
begin
case SL is
when '1' | 'H' => return 1 ;
when '0' | 'L' => return 0 ;
when others => return -1 ;
end case ;
end function to_integer ;
------------------------------------------------------------
function to_integer_vector ( BV : boolean_vector ) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(BV'range) ;
begin
for i in BV'range loop
result(i) := to_integer(BV(i)) ;
end loop ;
return result ;
end function to_integer_vector ;
------------------------------------------------------------
function to_integer_vector ( SLV : std_logic_vector ) return integer_vector is
-------------------------------------------------------------
variable result : integer_vector(SLV'range) ;
begin
for i in SLV'range loop
result(i) := to_integer(SLV(i)) ;
end loop ;
return result ;
end function to_integer_vector ;
end package body CoveragePkg ;
|
<filename>MiniALU/bitwise_shift_left.vhd
-- takes in a 4-bit integer and shifts it to the left by one bit
-- we can do shift left by using our adder as shifting left is the equivalent of
-- doubling the number
library IEEE;
use ieee.std_logic_1164.all;
entity bitwise_shift_left is
port (A : in std_logic_vector(3 downto 0);
-- shift = how many positions we will shift left by
shift: in positive:=1;
res : out std_logic_vector(3 downto 0));
end entity bitwise_shift_left;
architecture arch of bitwise_shift_left is
component unsigned_nbit_adder
port(op1, op2 : in std_logic_vector(3 downto 0);
Cin : in std_logic;
signed: in std_logic;
extended_op2: in std_logic;
sum : out std_logic_vector(3 downto 0);
carry_out : out std_logic);
end component;
-- making a vector to hold our result
signal res_buff : std_logic_vector(3 downto 0);
signal A_buff: std_logic_vector(3 downto 0);
begin
A_buff <= A;
adder: for i in 0 to 0 generate
adder_i: unsigned_nbit_adder port map(op1=>A, op2=>A_buff, Cin=>'0', signed=>'0', extended_op2=>'0',sum=>res_buff);
end generate;
res <= res_buff;
end arch;
|
<gh_stars>0
-- (C) 2001-2018 Intel Corporation. All rights reserved.
-- This simulation model contains highly confidential and
-- proprietary information of Intel and is being provided
-- in accordance with and subject to the protections of the
-- applicable Intel Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Intel
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files from any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs
-- for use exclusively in logic devices manufactured by Intel and sold
-- by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details. Intel products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Intel assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- ACDS 18.1
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "VCS"
`protect encrypt_agent_info = "J-2014.12-SP1 -- Feb 26, 2015"
`protect key_keyowner = "Synopsys"
`protect key_keyname = "<KEY>"
`protect key_method = "rsa"
`protect encoding = (enctype = "base64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
<KEY>
`protect data_method = "aes128-cbc"
`protect encoding = (enctype = "base64", line_length = 76, bytes = 6336)
`protect data_block
<KEY>
<KEY>
`protect end_protected
|
-------------------------------------------------------------------------------
--
-- File: Circular_Buffer.vhd
-- Author: <NAME>
-- Original Project: Zmod DAC 1411 AXI Adapter
-- Date: 15 January 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
--This module implements the circular buffer and the AXI Stream to BRAM bridge.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Circular_Buffer is
Generic
(
kBufferSize: integer range 0 to 1024 := 14
);
Port ( SysClk : in STD_LOGIC; --100MHz input clock
AxiStreamClk : in STD_LOGIC; --AXI Stream input clock
AxiLiteClk : in std_logic; --AXI Lite input clock
sRst_n : in STD_LOGIC; --Active low synchronous reset signal synchronized with SysClk
xsRst_n : in STD_LOGIC; --Active low synchronous reset signal synchronized with AxiStreamClk
sInitDone_n: in STD_LOGIC; --Input flag (active low) indicating that the Zmod DAC Low Level
-- Controller has succesfully completed initialization
sCh1Out : out STD_LOGIC_VECTOR (13 downto 0); --Channel1 data output
sCh2Out : out STD_LOGIC_VECTOR (13 downto 0); --Channel2 data output
--AXI Stream (MM2S)
s_axis_mm2s_tdata : in STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_mm2s_tkeep : in STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_mm2s_tvalid : in STD_LOGIC;
s_axis_mm2s_tready : out STD_LOGIC;
s_axis_mm2s_tlast : in STD_LOGIC;
sDacEn: in STD_LOGIC; -- Control signal that enables the circular buffer's output address
-- counter and closes the Zmod DAC 1411 output relay contacts
sTransferLength : in STD_LOGIC_VECTOR (kBufferSize-1 downto 0); -- Buffer's length synchronised in the SysClk domain
xsTransferLength : in std_logic_vector (kBufferSize-1 downto 0); -- Buffer's length synchronised in the AxiStreamClk domain
sOutAddrCntRst : in std_logic; -- Control bit that resets the circular buffer's output address counter
sDivRate : in std_logic_vector(13 downto 0); -- Factor by which the default 100MHz increment rate of the circular's buffer
-- output address counter is divided
lBufferFull : out STD_LOGIC --Flag indicating that the number of samples specified in the MM2S_Lenght registers
--have been loaded in the circular buffer
);
end Circular_Buffer;
architecture Behavioral of Circular_Buffer is
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
component HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic);
end component HandshakeData;
type BufferDataArray_t is array (27 downto 0) of std_logic_vector(0 downto 0);
type WeDataArray_t is array (27 downto 0) of std_logic_vector(0 downto 0);
type FsmStates_t is (StIdle, StArm, StWaitTrigger, StLoadBufferNormal, StLoadBufferNone, StBufferFullPush, StBufferFullAck, StSendBufferDummy,
StSendBuffer, StSetStop, StSetStopAck, StOutAddrCntPush, StOutAddrCntAck, StWaitStop);
--Active high reset signal
signal aRst_p : std_logic;
--Buffer write channel related signals
signal xsBufferInputData : std_logic_vector (27 downto 0);
signal xsEnaBuffer : std_logic_vector (27 downto 0);
signal xsBitValid : std_logic_vector (31 downto 0);
signal xsWeaBuffer : std_logic_vector (27 downto 0);
signal xsWeaArray : WeDataArray_t;
signal xsBufferInputArray : BufferDataArray_t;
signal xsInAddrCounter, xsInAddrCounterR : std_logic_vector (kBufferSize-1 downto 0); --conter used to generate the BRAM write port address
--Buffer read channel and BRAM to Axi Stream related signals
signal sBufferOutputData : std_logic_vector (27 downto 0);
signal sEnbBuffer : std_logic_vector (27 downto 0);
signal sBufferOutArray : BufferDataArray_t;
signal sOutAddrCntAux : std_logic_vector (13 downto 0);
signal sOutAddrCntEn : std_logic;
signal sOutAddrCounter, sOutAddrCounterR : std_logic_vector (kBufferSize-1 downto 0);
signal xsBufferFull : std_logic; --flag indicating that the buffer was loaded successfuly
signal sLoadOutCnt : std_logic_vector (0 downto 0); --signal that resets the BRAM read address port counter once the buffer is filled (in system clock domain)
signal xsLoadOutCnt : std_logic; --signal that resets the BRAM read address port counter once the buffer is filled (in system Axi Stream clock domain)
signal xsTvalidDisable : std_logic; --signal used to deassert s_axis_s2mm_tvalid once all requested bytes have been transfered
--Buffer control state machine related signals
signal sCurrentState, sNextState : FsmStates_t;
signal fsmcfg_state, fsmcfg_state_r : std_logic_vector(4 downto 0);
--Axi Stream interface related signals
--Control register and status register write strobe signals
signal sBufferFull : std_logic_vector(0 downto 0); --pulse indicating the buffer has aquired the requested amount of data
--Clock domain crossing related signals
signal sBufFullRdy, sBufFullPush, lBufFullValid : std_logic;
begin
aRst_p <= not sRst_n;
s_axis_mm2s_tready <= '1';
xsBufferInputData <= s_axis_mm2s_tdata(31 downto 18) & s_axis_mm2s_tdata(15 downto 2);
ProcBufferPortAssign : process (xsWeaBuffer)
begin
for Index in 0 to 27 loop
xsWeaArray(Index)(0) <= s_axis_mm2s_tvalid; --assume tkeep = "1111" for all valid data;
xsBufferInputArray(Index)(0) <= xsBufferInputData(Index);
sBufferOutputData(Index) <= sBufferOutArray(Index)(0);
end loop;
end process;
xsEnaBuffer <= (others => '1');
sEnbBuffer <= (others => '1');
GenerateBuffer : for Index in 0 to 27 generate
InstBRAM_Buffer : blk_mem_gen_0
PORT MAP (
clka => AxiStreamClk,
ena => xsEnaBuffer(Index),
wea => xsWeaArray(Index),
addra => xsInAddrCounter,
dina => xsBufferInputArray(Index),
clkb => SysClk,
enb => sEnbBuffer(Index),
addrb => sOutAddrCounter,
doutb => sBufferOutArray(Index)
);
end generate GenerateBuffer;
sCh1Out <= sBufferOutputData(27 downto 14);
sCh2Out <= sBufferOutputData(13 downto 0);
--Input Buffer Address Counter
ProcInAddrCounter: process (AxiStreamClk)
begin
if (AxiStreamClk' event and AxiStreamClk = '1') then
if ((xsRst_n = '0') or (s_axis_mm2s_tlast = '1'))then
xsInAddrCounter <= (others => '0');
xsInAddrCounterR <= (others => '0');
else
xsInAddrCounterR <= xsInAddrCounter;
if(s_axis_mm2s_tvalid = '1') then
xsInAddrCounter <= xsInAddrCounter + '1';
end if;
end if;
end if;
end process;
ProcBufferFull: process (AxiStreamClk)
begin
if (AxiStreamClk' event and AxiStreamClk = '1') then
if (xsRst_n = '0') then
xsBufferFull <= '0';
else
if ((s_axis_mm2s_tlast = '1') and (xsInAddrCounter = xsTransferLength - '1')) then
xsBufferFull <= '1';
else
xsBufferFull <= '0';
end if;
end if;
end if;
end process;
ProcOutAddrCntEn: process (SysClk)
begin
if (SysClk' event and SysClk = '1') then
if (sRst_n = '0' or sOutAddrCntRst = '1') then
sOutAddrCntAux <= (others => '0');
sOutAddrCntEn <= '0';
else
if(sDacEn = '1') then
if(sOutAddrCntAux = sDivRate) then
sOutAddrCntAux <= (others => '0');
sOutAddrCntEn <= '1';
else
sOutAddrCntAux <= sOutAddrCntAux + '1';
sOutAddrCntEn <= '0';
end if;
end if;
end if;
end if;
end process;
ProcOutAddrCounter: process (SysClk)
begin
if (SysClk' event and SysClk = '1') then
if (sRst_n = '0' or sOutAddrCntRst = '1') then
sOutAddrCounter <= (others => '0');
sOutAddrCounterR <= (others => '0');
else
sOutAddrCounterR <= sOutAddrCounter;
if((sDacEn = '1') and (sOutAddrCntEn = '1'))then
if(sOutAddrCounter = (sTransferLength - '1')) then
sOutAddrCounter <= (others => '0');
else
sOutAddrCounter <= sOutAddrCounter + '1';
end if;
end if;
end if;
end if;
end process;
----------------------------------------CLOCK DOMAIN CROSSING----------------------------------------------------------
InstBufFullHandShake : HandshakeData -- synchronization module for AXI LITE LENGTH register crossing to PROG_CLK clock domain
generic map (
kDataWidth => 1
)
Port map (
InClk => AxiStreamClk,
OutClk => AxiLiteClk,
iData => "1",
oData => open, -- synchronized output
iPush => xsBufferFull,
iRdy => open,
oAck => '1',
oValid => lBufFullValid, -- indicates valid synchronized data
aReset => aRst_p
);
lBufferFull <= lBufFullValid;
end Behavioral;
|
-- Copyright (c) 2020 <NAME>
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity APUF_Mutual_Order is
generic (stage_n: integer := 2);
port (
paths: in std_logic_vector(1 to 4);
-- [4, 0] for switch block 0.
challenge: in std_logic_vector(5 * stage_n - 1 downto 0);
response_mutual_order: out std_logic_vector(1 to 6));
end APUF_Mutual_Order;
architecture Behavioral of APUF_Mutual_Order is
component Switch_Block_4x4 is port (
input: in std_logic_vector(0 to 3);
challenge: in std_logic_vector(4 downto 0);
output: out std_logic_vector(0 to 3));
end component;
component Arbiter_Mutual_Order is port (
permutation: in std_logic_vector(1 to 4); -- a1 to a4 in the paper
mutual_order: out std_logic_vector(1 to 6));
end component;
type switch_block_io_array is array (0 to stage_n - 1) of std_logic_vector(1 to 4);
signal switch_block_out: switch_block_io_array;
begin
assert (stage_n > 0)
report "Number of stages must be positive in APUF must be positive."
severity failure;
FIRST_SWITCH_BLOCK: Switch_Block_4x4 port map (
input => paths,
challenge => challenge(4 downto 0),
output => switch_block_out(0));
SWITCH_BLOCKS: for i in 1 to stage_n - 1 generate
SWITCH_BLOCK: Switch_Block_4x4 port map (
input => switch_block_out(i-1),
challenge => challenge((i+1)*5 - 1 downto (i*5)),
output => switch_block_out(i));
end generate SWITCH_BLOCKS;
APUF_ARBITER: Arbiter_Mutual_Order port map (
permutation => switch_block_out(stage_n - 1),
mutual_order => response_mutual_order);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package state is
constant STATE_SIZE: integer := 2;
subtype state_t is unsigned(STATE_SIZE - 1 downto 0);
constant ST_FETCH: state_t := "00";
constant ST_DECODE: state_t := "01";
constant ST_EXECUTE: state_t := "10";
end package state;
|
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'LCLS2 Common Carrier Core'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'LCLS2 Common Carrier Core', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiStreamPkg.all;
use surf.SsiPkg.all;
use surf.AxiLitePkg.all;
use surf.I2cPkg.all;
library amc_carrier_core;
use amc_carrier_core.AmcCarrierPkg.all;
use amc_carrier_core.AmcCarrierSysRegPkg.all;
use amc_carrier_core.FpgaTypePkg.all;
library unisim;
use unisim.vcomponents.all;
entity AmcCarrierSysReg is
generic (
TPD_G : time := 1 ns;
BUILD_INFO_G : BuildInfoType;
APP_TYPE_G : AppType := APP_NULL_TYPE_C;
MPS_SLOT_G : boolean := false; -- false = Normal Operation, true = MPS message concentrator (Slot#2 only)
GEN_PWR_I2C_G : boolean := true;
FSBL_G : boolean := false);
port (
-- Primary AXI-Lite Interface
axilClk : in sl;
axilRst : in sl;
sAxilReadMasters : in AxiLiteReadMasterArray(1 downto 0);
sAxilReadSlaves : out AxiLiteReadSlaveArray(1 downto 0);
sAxilWriteMasters : in AxiLiteWriteMasterArray(1 downto 0);
sAxilWriteSlaves : out AxiLiteWriteSlaveArray(1 downto 0);
-- Timing AXI-Lite Interface
timingReadMaster : out AxiLiteReadMasterType;
timingReadSlave : in AxiLiteReadSlaveType;
timingWriteMaster : out AxiLiteWriteMasterType;
timingWriteSlave : in AxiLiteWriteSlaveType;
-- BSA AXI-Lite Interface
bsaReadMaster : out AxiLiteReadMasterType;
bsaReadSlave : in AxiLiteReadSlaveType;
bsaWriteMaster : out AxiLiteWriteMasterType;
bsaWriteSlave : in AxiLiteWriteSlaveType;
-- ETH AXI-Lite Interface
ethReadMaster : out AxiLiteReadMasterType;
ethReadSlave : in AxiLiteReadSlaveType;
ethWriteMaster : out AxiLiteWriteMasterType;
ethWriteSlave : in AxiLiteWriteSlaveType;
-- DDR PHY AXI-Lite Interface
ddrReadMaster : out AxiLiteReadMasterType;
ddrReadSlave : in AxiLiteReadSlaveType;
ddrWriteMaster : out AxiLiteWriteMasterType;
ddrWriteSlave : in AxiLiteWriteSlaveType;
ddrMemReady : in sl;
ddrMemError : in sl;
-- MPS PHY AXI-Lite Interface
mpsReadMaster : out AxiLiteReadMasterType;
mpsReadSlave : in AxiLiteReadSlaveType;
mpsWriteMaster : out AxiLiteWriteMasterType;
mpsWriteSlave : in AxiLiteWriteSlaveType;
-- Local Configuration
localMac : out slv(47 downto 0);
localIp : out slv(31 downto 0);
ethLinkUp : in sl := '0';
----------------------
-- Top Level Interface
----------------------
-- AXI-Lite Interface
appReadMaster : out AxiLiteReadMasterType;
appReadSlave : in AxiLiteReadSlaveType;
appWriteMaster : out AxiLiteWriteMasterType;
appWriteSlave : in AxiLiteWriteSlaveType;
-- BSI Interface
bsiBus : out bsiBusType;
----------------
-- Core Ports --
----------------
-- Crossbar Ports
xBarSin : out slv(1 downto 0);
xBarSout : out slv(1 downto 0);
xBarConfig : out sl;
xBarLoad : out sl;
-- IPMC Ports
ipmcScl : inout sl;
ipmcSda : inout sl;
-- Configuration PROM Ports
calScl : inout sl := 'Z';
calSda : inout sl := 'Z';
-- VCCINT DC/DC Ports
pwrScl : inout sl := 'Z';
pwrSda : inout sl := 'Z';
-- Clock Cleaner Ports
timingClkScl : inout sl := 'Z';
timingClkSda : inout sl := 'Z';
-- DDR3L SO-DIMM Ports
ddrScl : inout sl := 'Z';
ddrSda : inout sl := 'Z';
-- SYSMON Ports
vPIn : in sl;
vNIn : in sl);
end AmcCarrierSysReg;
architecture mapping of AmcCarrierSysReg is
-- FSBL Timeout Duration
constant TIMEOUT_C : integer := integer(10.0 / AXI_CLK_PERIOD_C);
constant NUM_AXI_MASTERS_C : natural := 15;
constant VERSION_INDEX_C : natural := 0;
constant SYSMON_INDEX_C : natural := 1;
constant BOOT_MEM_INDEX_C : natural := 2;
constant XBAR_INDEX_C : natural := 3;
constant CONFIG_I2C_INDEX_C : natural := 4;
constant CLK_I2C_INDEX_C : natural := 5;
constant DDR_I2C_INDEX_C : natural := 6;
constant IPMC_INDEX_C : natural := 7;
constant TIMING_INDEX_C : natural := 8;
constant BSA_INDEX_C : natural := 9;
constant ETH_INDEX_C : natural := 10;
constant DDR_INDEX_C : natural := 11;
constant MPS_INDEX_C : natural := 12;
constant PWR_I2C_INDEX_C : natural := 13;
constant APP_INDEX_C : natural := 14;
constant AXI_CROSSBAR_MASTERS_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXI_MASTERS_C-1 downto 0) := (
VERSION_INDEX_C => (
baseAddr => VERSION_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
SYSMON_INDEX_C => (
baseAddr => SYSMON_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
BOOT_MEM_INDEX_C => (
baseAddr => BOOT_MEM_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
XBAR_INDEX_C => (
baseAddr => XBAR_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
CONFIG_I2C_INDEX_C => (
baseAddr => CONFIG_I2C_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
CLK_I2C_INDEX_C => (
baseAddr => CLK_I2C_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
DDR_I2C_INDEX_C => (
baseAddr => DDR_I2C_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
IPMC_INDEX_C => (
baseAddr => IPMC_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
ETH_INDEX_C => (
baseAddr => ETH_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
TIMING_INDEX_C => (
baseAddr => TIMING_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
BSA_INDEX_C => (
baseAddr => BSA_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
DDR_INDEX_C => (
baseAddr => DDR_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
MPS_INDEX_C => (
baseAddr => MPS_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
PWR_I2C_INDEX_C => (
baseAddr => PWR_I2C_ADDR_C,
addrBits => 24,
connectivity => x"FFFF"),
APP_INDEX_C => (
baseAddr => APP_ADDR_C,
addrBits => 31,
connectivity => x"FFFF"));
constant TIME_DEVICE_MAP_C : I2cAxiLiteDevArray(0 to 0) := (
0 => MakeI2cAxiLiteDevType(
i2cAddress => "1010100",
dataSize => 16, -- in units of bits
addrSize => 16, -- in units of bits
endianness => '1')); -- Big endian
constant DDR_DEVICE_MAP_C : I2cAxiLiteDevArray(0 to 0) := (
0 => MakeI2cAxiLiteDevType(
i2cAddress => "1010000", -- SRD Memory (1010) (Lookup tool at www.micron.com/spd)
dataSize => 8, -- in units of bits
addrSize => 8, -- in units of bits
endianness => '1')); -- Big endian
constant PWR_DEVICE_MAP_C : I2cAxiLiteDevArray(0 to 0) := (
0 => MakeI2cAxiLiteDevType(
i2cAddress => "0001010", -- EM2280P01QI: ADDR1=0Ohm, ADDR0=10kOhm --> Address=0x0A
dataSize => 16, -- in units of bits
addrSize => 8, -- in units of bits
repeatStart => '1', -- repeated start
endianness => '0')); -- Little endian
signal mAxilWriteMasters : AxiLiteWriteMasterArray(NUM_AXI_MASTERS_C-1 downto 0);
signal mAxilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXI_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C);
signal mAxilReadMasters : AxiLiteReadMasterArray(NUM_AXI_MASTERS_C-1 downto 0);
signal mAxilReadSlaves : AxiLiteReadSlaveArray(NUM_AXI_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C);
signal bootCsL : sl;
signal bootSck : sl;
signal bootMosi : sl;
signal bootMiso : sl;
signal di : slv(3 downto 0);
signal do : slv(3 downto 0);
signal axilRstL : sl;
signal bootCmd : sl;
signal bootRdy : sl;
signal bootArmed : sl;
signal bootstart : sl;
signal bootReq : sl;
signal bootAddr : slv(31 downto 0);
signal upTimeCnt : slv(31 downto 0);
signal userValues : Slv32Array(0 to 63) := (others => x"00000000");
begin
--------------------------
-- AXI-Lite: Crossbar Core
--------------------------
U_XBAR : entity surf.AxiLiteCrossbar
generic map (
TPD_G => TPD_G,
NUM_SLAVE_SLOTS_G => 2,
NUM_MASTER_SLOTS_G => NUM_AXI_MASTERS_C,
MASTERS_CONFIG_G => AXI_CROSSBAR_MASTERS_CONFIG_C)
port map (
axiClk => axilClk,
axiClkRst => axilRst,
sAxiWriteMasters => sAxilWriteMasters,
sAxiWriteSlaves => sAxilWriteSlaves,
sAxiReadMasters => sAxilReadMasters,
sAxiReadSlaves => sAxilReadSlaves,
mAxiWriteMasters => mAxilWriteMasters,
mAxiWriteSlaves => mAxilWriteSlaves,
mAxiReadMasters => mAxilReadMasters,
mAxiReadSlaves => mAxilReadSlaves);
--------------------------
-- AXI-Lite Version Module
--------------------------
U_Version : entity surf.AxiVersion
generic map (
TPD_G => TPD_G,
BUILD_INFO_G => BUILD_INFO_G,
CLK_PERIOD_G => 6.4E-9,
XIL_DEVICE_G => "ULTRASCALE",
EN_DEVICE_DNA_G => true)
port map (
-- AXI-Lite Interface
axiClk => axilClk,
axiRst => axilRst,
upTimeCnt => upTimeCnt,
userValues => userValues,
fpgaReload => bootCmd,
axiReadMaster => mAxilReadMasters(VERSION_INDEX_C),
axiReadSlave => mAxilReadSlaves(VERSION_INDEX_C),
axiWriteMaster => mAxilWriteMasters(VERSION_INDEX_C),
axiWriteSlave => mAxilWriteSlaves(VERSION_INDEX_C));
userValues(0) <= AMC_CARRIER_CORE_VERSION_C;
userValues(1) <= CPSW_TARBALL_ADDR_C;
userValues(2 to 63) <= (others => x"00000000");
bootRdy <= ddrMemReady and not(ddrMemError);
process(axilClk)
begin
if rising_edge(axilClk) then
-- Check for reset
if axilRst = '1' then
bootArmed <= '0' after TPD_G;
bootstart <= '0' after TPD_G;
else
-- Reset the flag
bootstart <= '0' after TPD_G;
-- Check for IPMI boot request
if (bootReq = '1')then
bootArmed <= '1' after TPD_G;
end if;
-- Check for Application boot request
if (FSBL_G = false) and (bootCmd = '1') then
bootArmed <= '1' after TPD_G;
end if;
-- Check if DDR passed and armed
if (bootRdy = '1') and (bootArmed = '1') then
-- Set the flag
bootstart <= '1' after TPD_G;
-- Reset the flag
bootArmed <= '0' after TPD_G;
end if;
end if;
end if;
end process;
U_Iprog : entity surf.Iprog
generic map (
TPD_G => TPD_G,
XIL_DEVICE_G => "ULTRASCALE")
port map (
clk => axilClk,
rst => axilRst,
start => bootstart,
bootAddress => bootAddr);
--------------------------
-- AXI-Lite: SYSMON Module
--------------------------
U_SysMon : entity amc_carrier_core.AmcCarrierSysMon
generic map (
TPD_G => TPD_G)
port map (
-- SYSMON Ports
vPIn => vPIn,
vNIn => vNIn,
-- AXI-Lite Register Interface
axilReadMaster => mAxilReadMasters(SYSMON_INDEX_C),
axilReadSlave => mAxilReadSlaves(SYSMON_INDEX_C),
axilWriteMaster => mAxilWriteMasters(SYSMON_INDEX_C),
axilWriteSlave => mAxilWriteSlaves(SYSMON_INDEX_C),
-- Clocks and Resets
axilClk => axilClk,
axilRst => axilRst);
------------------------------
-- AXI-Lite: Boot Flash Module
------------------------------
U_BootProm : entity surf.AxiMicronN25QCore
generic map (
TPD_G => TPD_G,
MEM_ADDR_MASK_G => x"00000000", -- Using hardware write protection
AXI_CLK_FREQ_G => AXI_CLK_FREQ_C, -- units of Hz
SPI_CLK_FREQ_G => (AXI_CLK_FREQ_C/4.0)) -- units of Hz
port map (
-- FLASH Memory Ports
csL => bootCsL,
sck => bootSck,
mosi => bootMosi,
miso => bootMiso,
-- AXI-Lite Register Interface
axiReadMaster => mAxilReadMasters(BOOT_MEM_INDEX_C),
axiReadSlave => mAxilReadSlaves(BOOT_MEM_INDEX_C),
axiWriteMaster => mAxilWriteMasters(BOOT_MEM_INDEX_C),
axiWriteSlave => mAxilWriteSlaves(BOOT_MEM_INDEX_C),
-- Clocks and Resets
axiClk => axilClk,
axiRst => axilRst);
U_STARTUPE3 : STARTUPE3
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 0.0) -- Set the Configuration Clock Frequency(ns) for simulation
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
DI => di, -- 4-bit output: Allow receiving on the D[3:0] input pins
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
DO => do, -- 4-bit input: Allows control of the D[3:0] pin outputs
DTS => "1110", -- 4-bit input: Allows tristate of the D[3:0] pins
FCSBO => bootCsL, -- 1-bit input: Contols the FCS_B pin for flash access
FCSBTS => '0', -- 1-bit input: Tristate the FCS_B pin
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => bootSck, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => axilRstL, -- 1-bit input: User DONE pin output control
USRDONETS => '0'); -- 1-bit input: User DONE 3-state enable output
axilRstL <= not(axilRst); -- IPMC uses DONE to determine if FPGA is ready
do <= "111" & bootMosi;
bootMiso <= di(1);
----------------------------------
-- AXI-Lite: Clock Crossbar Module
----------------------------------
U_Sy56040 : entity surf.AxiSy56040Reg
generic map (
TPD_G => TPD_G,
XBAR_DEFAULT_G => xbarDefault(APP_TYPE_G, MPS_SLOT_G),
AXI_CLK_FREQ_G => AXI_CLK_FREQ_C)
port map (
-- XBAR Ports
xBarSin => xBarSin,
xBarSout => xBarSout,
xBarConfig => xBarConfig,
xBarLoad => xBarLoad,
-- AXI-Lite Register Interface
axiReadMaster => mAxilReadMasters(XBAR_INDEX_C),
axiReadSlave => mAxilReadSlaves(XBAR_INDEX_C),
axiWriteMaster => mAxilWriteMasters(XBAR_INDEX_C),
axiWriteSlave => mAxilWriteSlaves(XBAR_INDEX_C),
-- Clocks and Resets
axiClk => axilClk,
axiRst => axilRst);
----------------------------------------
-- AXI-Lite: Configuration Memory Module
----------------------------------------
-- AxiI2cRegMaster_0 : entity surf.AxiI2cEeprom
-- generic map (
-- TPD_G => TPD_G,
-- ADDR_WIDTH_G => 13,
-- I2C_ADDR_G => "1010000",
-- I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz
-- AXI_CLK_FREQ_G => AXI_CLK_FREQ_C)
-- port map (
-- -- I2C Ports
-- scl => calScl,
-- sda => calSda,
-- -- AXI-Lite Register Interface
-- axilReadMaster => mAxilReadMasters(CONFIG_I2C_INDEX_C),
-- axilReadSlave => mAxilReadSlaves(CONFIG_I2C_INDEX_C),
-- axilWriteMaster => mAxilWriteMasters(CONFIG_I2C_INDEX_C),
-- axilWriteSlave => mAxilWriteSlaves(CONFIG_I2C_INDEX_C),
-- -- Clocks and Resets
-- axilClk => axilClk,
-- axilRst => axilRst);
---------------------------------
-- AXI-Lite: Clock Cleaner Module
---------------------------------
-- AxiI2cRegMaster_1 : entity surf.AxiI2cRegMaster
-- generic map (
-- TPD_G => TPD_G,
-- I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz
-- DEVICE_MAP_G => TIME_DEVICE_MAP_C,
-- AXI_CLK_FREQ_G => AXI_CLK_FREQ_C)
-- port map (
-- -- I2C Ports
-- scl => timingClkScl,
-- sda => timingClkSda,
-- -- AXI-Lite Register Interface
-- axiReadMaster => mAxilReadMasters(CLK_I2C_INDEX_C),
-- axiReadSlave => mAxilReadSlaves(CLK_I2C_INDEX_C),
-- axiWriteMaster => mAxilWriteMasters(CLK_I2C_INDEX_C),
-- axiWriteSlave => mAxilWriteSlaves(CLK_I2C_INDEX_C),
-- -- Clocks and Resets
-- axiClk => axilClk,
-- axiRst => axilRst);
-------------------------------
-- AXI-Lite: DDR Monitor Module
-------------------------------
-- AxiI2cRegMaster_2 : entity surf.AxiI2cRegMaster
-- generic map (
-- TPD_G => TPD_G,
-- I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz
-- DEVICE_MAP_G => DDR_DEVICE_MAP_C,
-- AXI_CLK_FREQ_G => AXI_CLK_FREQ_C)
-- port map (
-- -- I2C Ports
-- scl => ddrScl,
-- sda => ddrSda,
-- -- AXI-Lite Register Interface
-- axiReadMaster => mAxilReadMasters(DDR_I2C_INDEX_C),
-- axiReadSlave => mAxilReadSlaves(DDR_I2C_INDEX_C),
-- axiWriteMaster => mAxilWriteMasters(DDR_I2C_INDEX_C),
-- axiWriteSlave => mAxilWriteSlaves(DDR_I2C_INDEX_C),
-- -- Clocks and Resets
-- axiClk => axilClk,
-- axiRst => axilRst);
-----------------------
-- AXI-Lite: BSI Module
-----------------------
U_Bsi : entity amc_carrier_core.AmcCarrierBsi
generic map (
TPD_G => TPD_G,
BUILD_INFO_G => BUILD_INFO_G)
port map (
-- DDR Memory Status
ddrMemReady => ddrMemReady,
ddrMemError => ddrMemError,
-- Local Configurations
localMac => localMac,
localIp => localIp,
ethLinkUp => ethLinkUp,
bootReq => bootReq,
bootAddr => bootAddr,
upTimeCnt => upTimeCnt,
-- Application Interface
bsiBus => bsiBus,
-- I2C Ports
scl => ipmcScl,
sda => ipmcSda,
-- AXI-Lite Register Interface
axilReadMaster => mAxilReadMasters(IPMC_INDEX_C),
axilReadSlave => mAxilReadSlaves(IPMC_INDEX_C),
axilWriteMaster => mAxilWriteMasters(IPMC_INDEX_C),
axilWriteSlave => mAxilWriteSlaves(IPMC_INDEX_C),
-- Clocks and Resets
axilClk => axilClk,
axilRst => axilRst);
-------------------------------
-- AXI-Lite: PWR Monitor Module
-------------------------------
GEN_PWR_I2C : if (GEN_PWR_I2C_G) and (ULTRASCALE_PLUS_C) and (FSBL_G = false) generate
-- AxiI2cRegMaster_3 : entity surf.AxiI2cRegMaster
-- generic map (
-- TPD_G => TPD_G,
-- I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz
-- DEVICE_MAP_G => PWR_DEVICE_MAP_C,
-- AXI_CLK_FREQ_G => AXI_CLK_FREQ_C)
-- port map (
-- -- I2C Ports
-- scl => pwrScl,
-- sda => pwrSda,
-- -- AXI-Lite Register Interface
-- axiReadMaster => mAxilReadMasters(PWR_I2C_INDEX_C),
-- axiReadSlave => mAxilReadSlaves(PWR_I2C_INDEX_C),
-- axiWriteMaster => mAxilWriteMasters(PWR_I2C_INDEX_C),
-- axiWriteSlave => mAxilWriteSlaves(PWR_I2C_INDEX_C),
-- -- Clocks and Resets
-- axiClk => axilClk,
-- axiRst => axilRst);
AxiI2cRegMaster_3 : entity surf.AxiLitePMbusMaster
generic map (
TPD_G => TPD_G,
I2C_ADDR_G => "0001010",
I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz
AXI_CLK_FREQ_G => AXI_CLK_FREQ_C)
port map (
-- I2C Ports
scl => pwrScl,
sda => pwrSda,
-- AXI-Lite Register Interface
axilReadMaster => mAxilReadMasters(PWR_I2C_INDEX_C),
axilReadSlave => mAxilReadSlaves(PWR_I2C_INDEX_C),
axilWriteMaster => mAxilWriteMasters(PWR_I2C_INDEX_C),
axilWriteSlave => mAxilWriteSlaves(PWR_I2C_INDEX_C),
-- Clocks and Resets
axilClk => axilClk,
axilRst => axilRst);
end generate;
--------------------------------------
-- Map the AXI-Lite to Timing Firmware
--------------------------------------
timingReadMaster <= mAxilReadMasters(TIMING_INDEX_C);
mAxilReadSlaves(TIMING_INDEX_C) <= timingReadSlave;
timingWriteMaster <= mAxilWriteMasters(TIMING_INDEX_C);
mAxilWriteSlaves(TIMING_INDEX_C) <= timingWriteSlave;
--------------------------------------
-- Map the AXI-Lite to BSA Firmware
--------------------------------------
bsaReadMaster <= mAxilReadMasters(BSA_INDEX_C);
mAxilReadSlaves(BSA_INDEX_C) <= bsaReadSlave;
bsaWriteMaster <= mAxilWriteMasters(BSA_INDEX_C);
mAxilWriteSlaves(BSA_INDEX_C) <= bsaWriteSlave;
----------------------------------------
-- Map the AXI-Lite to ETH Firmware
----------------------------------------
ethReadMaster <= mAxilReadMasters(ETH_INDEX_C);
mAxilReadSlaves(ETH_INDEX_C) <= ethReadSlave;
ethWriteMaster <= mAxilWriteMasters(ETH_INDEX_C);
mAxilWriteSlaves(ETH_INDEX_C) <= ethWriteSlave;
---------------------------------------
-- Map the AXI-Lite to DDR PHY Firmware
---------------------------------------
ddrReadMaster <= mAxilReadMasters(DDR_INDEX_C);
mAxilReadSlaves(DDR_INDEX_C) <= ddrReadSlave;
ddrWriteMaster <= mAxilWriteMasters(DDR_INDEX_C);
mAxilWriteSlaves(DDR_INDEX_C) <= ddrWriteSlave;
---------------------------------------
-- Map the AXI-Lite to MPS PHY Firmware
---------------------------------------
mpsReadMaster <= mAxilReadMasters(MPS_INDEX_C);
mAxilReadSlaves(MPS_INDEX_C) <= mpsReadSlave;
mpsWriteMaster <= mAxilWriteMasters(MPS_INDEX_C);
mAxilWriteSlaves(MPS_INDEX_C) <= mpsWriteSlave;
-------------------------------------------
-- Map the AXI-Lite to Application Firmware
-------------------------------------------
appReadMaster <= mAxilReadMasters(APP_INDEX_C);
mAxilReadSlaves(APP_INDEX_C) <= appReadSlave;
appWriteMaster <= mAxilWriteMasters(APP_INDEX_C);
mAxilWriteSlaves(APP_INDEX_C) <= appWriteSlave;
end mapping;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Mul is
port (
clk : in std_logic; -- The clock
reset : in std_logic;
A, B : in std_logic_vector(7 downto 0); -- The two inputs
P : out std_logic_vector(7 downto 0); -- The product
ready : out std_logic
);
end Mul;
architecture Behavior of Mul is
-- The right shift component
component Rsh is
port (
A, B : in std_logic_vector(7 downto 0);
P : out std_logic_vector(7 downto 0)
);
end component;
-- The left shift component
component Lsh is
port (
A, B : in std_logic_vector(7 downto 0);
P : out std_logic_vector(7 downto 0)
);
end component;
-- The adder
component Adder is
port (
A, B : in std_logic_vector(7 downto 0);
P : out std_logic_vector(7 downto 0);
co : out std_logic
);
end component;
-- Signals
signal output, output_final : std_logic_vector(7 downto 0) := X"00";
signal B_shift, counter_vec, imm, imm2 : std_logic_vector(7 downto 0) := X"00";
signal counter, stage : integer := 0;
begin
rsh_unit : Rsh port map (A => B, B => counter_vec, P => B_shift);
lsh_unit : Lsh port map (A => imm, B => counter_vec, P => imm2);
adder_unit : Adder port map (A => imm2, B => output, P => output_final, co => open);
process (clk) is
begin
-- If we're on a new clock cycle, and the reset bit is set... Then reset
if rising_edge(clk) and reset = '1' then
stage <= 0;
counter <= 0;
ready <= '0';
counter_vec <= X"00";
P <= X"00";
-- Otherwise if we're on a new clock cycle and the reset bit is not set,
-- then start multiplying
elsif rising_edge(clk) and reset = '0' then
-- Output the product and reset
if counter = 8 then
ready <= '1';
counter <= 0;
P <= output_final;
output <= X"00";
else
-- Stage 0: Shift B
if stage = 0 then
counter_vec <= std_logic_vector(to_unsigned(counter, 8));
stage <= 1;
-- Stage 1: B(0) AND A
elsif stage = 1 then
if B_shift(0) = '1' then
imm <= A;
else
imm <= X"00";
end if;
stage <= 2;
-- Stage 3: Add the partial product and end the cyle
elsif stage = 2 then
output <= output_final;
--stage <= 3;
ready <= '0';
counter <= counter + 1;
stage <= 0;
end if;
end if;
end if;
end process;
end architecture;
|
-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2011 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: AHBLSramIf
-- Provides AHB interface to embedded Large SRAM.
--
--
-- Revision Information:
-- Date Description
--
-- SVN Revision Information:
-- SVN $Revision: 4805 $
-- SVN $Date: 2008-11-27 17:48:48 +0530 (Thu, 27 Nov 2008) $
--
-- Resolved SARs
-- SAR Date Who Description
--
-- Notes:
--
-- ********************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
ENTITY AHBLSramIf IS
GENERIC (
--//////////////////////////////////////////////////////////////////////////////
-- Parameter Declarations
--//////////////////////////////////////////////////////////////////////////////
AHB_DWIDTH : integer := 32;
AHB_AWIDTH : integer := 32;
RESP_OKAY : std_logic_vector(1 DOWNTO 0) :=
"00";
RESP_ERROR : std_logic_vector(1 DOWNTO 0) :=
"01";
-- AHB HTRANS definition
TRN_IDLE : std_logic_vector(1 DOWNTO 0) :=
"00";
TRN_BUSY : std_logic_vector(1 DOWNTO 0) :=
"01";
TRN_SEQ : std_logic_vector(1 DOWNTO 0) :=
"11";
TRN_NONSEQ : std_logic_vector(1 DOWNTO 0) :=
"10");
PORT (
--//////////////////////////////////////////////////////////////////////////////
-- I/O Declarations
--//////////////////////////////////////////////////////////////////////////////
-- Inputs
HCLK : IN std_logic;
HRESETN : IN std_logic;
HSEL : IN std_logic;
HTRANS : IN std_logic_vector(1 DOWNTO 0);
HBURST : IN std_logic_vector(2 DOWNTO 0);
HWRITE : IN std_logic;
HSIZE : IN std_logic_vector(2 DOWNTO 0);
HADDR : IN std_logic_vector(19 DOWNTO 0);
HWDATA : IN std_logic_vector(AHB_DWIDTH - 1
DOWNTO 0);
HREADYIN : IN std_logic;
sramahb_ack : IN std_logic;
sramahb_rdata : IN std_logic_vector(AHB_DWIDTH - 1
DOWNTO 0);
HRESP : OUT std_logic_vector(1 DOWNTO 0);
-- Outputs
HREADYOUT : OUT std_logic;
HRDATA : OUT std_logic_vector(AHB_DWIDTH - 1
DOWNTO 0);
ahbsram_req : OUT std_logic;
ahbsram_write : OUT std_logic;
ahbsram_wdata : OUT std_logic_vector(AHB_AWIDTH - 1
DOWNTO 0);
ahbsram_size : OUT std_logic_vector(2 DOWNTO 0);
ahbsram_addr : OUT std_logic_vector(19 DOWNTO 0);
BUSY : IN std_logic);
END ENTITY AHBLSramIf;
ARCHITECTURE translated OF AHBLSramIf IS
-- State Machine parameters
CONSTANT IDLE : std_logic_vector(1 DOWNTO 0) :=
"00";
CONSTANT AHB_WR : std_logic_vector(1 DOWNTO 0) :=
"01";
CONSTANT AHB_RD : std_logic_vector(1 DOWNTO 0) :=
"10";
--//////////////////////////////////////////////////////////////////////////////
-- Register Declarations
--//////////////////////////////////////////////////////////////////////////////
SIGNAL HTRANS_d : std_logic_vector(1 DOWNTO 0);
SIGNAL HBURST_d : std_logic_vector(2 DOWNTO 0);
SIGNAL HSIZE_d : std_logic_vector(2 DOWNTO 0);
SIGNAL HADDR_d : std_logic_vector(19 DOWNTO 0);
SIGNAL HWDATA_d : std_logic_vector(AHB_DWIDTH - 1
DOWNTO 0);
SIGNAL HWRITE_d : std_logic;
SIGNAL HSEL_d : std_logic;
SIGNAL HREADYIN_d : std_logic;
SIGNAL ahbcurr_state : std_logic_vector(1 DOWNTO 0);
SIGNAL ahbnext_state : std_logic_vector(1 DOWNTO 0);
SIGNAL latchahbcmd : std_logic;
SIGNAL ahbsram_req_int : std_logic;
SIGNAL ahbsram_req_d1 : std_logic;
SIGNAL HWDATA_cal : std_logic_vector(AHB_DWIDTH - 1
DOWNTO 0);
--//////////////////////////////////////////////////////////////////////////////
-- Wire Declarations
--//////////////////////////////////////////////////////////////////////////////
SIGNAL validahbcmd : std_logic;
-- Generation of signals required for SRAM
SIGNAL temp_xhdl13 : std_logic;
SIGNAL temp_xhdl14 : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0);
SIGNAL temp_xhdl15 : std_logic_vector(19 DOWNTO 0);
SIGNAL temp_xhdl16 : std_logic_vector(2 DOWNTO 0);
SIGNAL HREADYOUT_xhdl1 : std_logic;
SIGNAL HRESP_xhdl2 : std_logic_vector(1 DOWNTO 0);
SIGNAL HRDATA_xhdl3 : std_logic_vector(AHB_DWIDTH - 1
DOWNTO 0);
SIGNAL ahbsram_req_xhdl4 : std_logic;
SIGNAL ahbsram_write_xhdl5 : std_logic;
SIGNAL ahbsram_wdata_xhdl6 : std_logic_vector(AHB_AWIDTH - 1
DOWNTO 0);
SIGNAL ahbsram_size_xhdl7 : std_logic_vector(2 DOWNTO 0);
SIGNAL ahbsram_addr_xhdl8 : std_logic_vector(19 DOWNTO 0);
FUNCTION to_stdlogic (
val : IN boolean) RETURN std_logic IS
BEGIN
IF (val) THEN
RETURN('1');
ELSE
RETURN('0');
END IF;
END to_stdlogic;
FUNCTION conv_std_logic (
val : IN boolean) RETURN std_logic IS
BEGIN
RETURN(to_stdlogic(val));
END conv_std_logic;
BEGIN
--//////////////////////////////////////////////////////////////////////////////
-- Main body of code
--//////////////////////////////////////////////////////////////////////////////
HREADYOUT <= HREADYOUT_xhdl1;
HRESP <= HRESP_xhdl2;
HRDATA <= HRDATA_xhdl3;
ahbsram_req <= ahbsram_req_xhdl4;
ahbsram_write <= ahbsram_write_xhdl5;
ahbsram_wdata <= ahbsram_wdata_xhdl6;
ahbsram_size <= ahbsram_size_xhdl7;
ahbsram_addr <= ahbsram_addr_xhdl8;
-- Changes to be done when BUSY signal from RAM is used to block UII transactions indicating that SII needs to access the RAMs
-- assign HREADYOUT = !ahbsram_req_int & !BUSY;
-- Generation of valid AHB Command which triggers the AHB Slave State Machine
validahbcmd <= (HREADYIN AND HSEL) AND CONV_STD_LOGIC(HTRANS = TRN_NONSEQ) ;
-- Generation of HRESP
HRESP_xhdl2 <= RESP_OKAY ;
PROCESS (HWDATA)
VARIABLE HWDATA_cal_xhdl9 : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0);
BEGIN
HWDATA_cal_xhdl9 := HWDATA;
HWDATA_cal <= HWDATA_cal_xhdl9;
END PROCESS;
-- Latch all the AHB signals
PROCESS (HCLK, HRESETN)
BEGIN
IF (HRESETN = '0') THEN
HADDR_d <= (OTHERS => '0');
HWDATA_d <= (OTHERS => '0');
HTRANS_d <= "00";
HSIZE_d <= "000";
HBURST_d <= "000";
HWRITE_d <= '0';
HSEL_d <= '0';
HREADYIN_d <= '0';
ELSIF (HCLK'EVENT AND HCLK = '1') THEN
IF (latchahbcmd = '1') THEN
HADDR_d <= HADDR;
HTRANS_d <= HTRANS;
HSIZE_d <= HSIZE;
HBURST_d <= HBURST;
HWRITE_d <= HWRITE;
HWDATA_d <= HWDATA_cal;
HSEL_d <= HSEL;
HREADYIN_d <= HREADYIN;
END IF;
END IF;
END PROCESS;
-- Current State generation
PROCESS (HCLK, HRESETN)
BEGIN
IF (HRESETN = '0') THEN
ahbcurr_state <= IDLE;
ELSIF (HCLK'EVENT AND HCLK = '1') THEN
ahbcurr_state <= ahbnext_state;
END IF;
END PROCESS;
-- Next State and output decoder logic
PROCESS (HWRITE, sramahb_ack, validahbcmd, ahbnext_state, ahbcurr_state,
latchahbcmd)
VARIABLE latchahbcmd_xhdl10 : std_logic;
VARIABLE ahbsram_req_int_xhdl11 : std_logic;
VARIABLE ahbnext_state_xhdl12 : std_logic_vector(1 DOWNTO 0);
BEGIN
latchahbcmd_xhdl10 := '0';
ahbsram_req_int_xhdl11 := '0';
ahbnext_state_xhdl12 := ahbcurr_state;
CASE ahbcurr_state IS
WHEN IDLE =>
IF (validahbcmd = '1') THEN
latchahbcmd_xhdl10 := '1';
IF (HWRITE = '1') THEN
ahbnext_state_xhdl12 := AHB_WR;
ELSE
ahbnext_state_xhdl12 := AHB_RD;
END IF;
END IF;
WHEN AHB_WR =>
latchahbcmd_xhdl10 := '0';
ahbsram_req_int_xhdl11 := '1';
IF (sramahb_ack = '1') THEN
ahbnext_state_xhdl12 := IDLE;
END IF;
WHEN AHB_RD =>
latchahbcmd_xhdl10 := '0';
ahbsram_req_int_xhdl11 := '1';
IF (sramahb_ack = '1') THEN
ahbnext_state_xhdl12 := IDLE;
END IF;
WHEN OTHERS =>
ahbnext_state_xhdl12 := IDLE;
END CASE; -- case (ahbcurr_state)
latchahbcmd <= latchahbcmd_xhdl10;
ahbsram_req_int <= ahbsram_req_int_xhdl11;
ahbnext_state <= ahbnext_state_xhdl12;
END PROCESS;
--Generation of HREADYOUT
HREADYOUT_xhdl1 <= NOT ahbsram_req_int ;
temp_xhdl13 <= HWRITE_d WHEN (ahbsram_req_xhdl4 AND NOT sramahb_ack) = '1' ELSE '0';
ahbsram_write_xhdl5 <= temp_xhdl13 ;
temp_xhdl14 <= HWDATA;
ahbsram_wdata_xhdl6 <= temp_xhdl14 ;
temp_xhdl15 <= HADDR_d WHEN (ahbsram_req_int AND NOT sramahb_ack) = '1' ELSE HADDR_d;
ahbsram_addr_xhdl8 <= temp_xhdl15 ;
temp_xhdl16 <= HSIZE_d WHEN (ahbsram_req_int AND NOT sramahb_ack) = '1' ELSE HSIZE;
ahbsram_size_xhdl7 <= temp_xhdl16 ;
PROCESS (HCLK, HRESETN)
BEGIN
IF (HRESETN = '0') THEN
ahbsram_req_d1 <= '0';
ELSIF (HCLK'EVENT AND HCLK = '1') THEN
ahbsram_req_d1 <= ahbsram_req_int;
END IF;
END PROCESS;
-- Generate the request to the SRAM contol logic when there is AHB read or write request
ahbsram_req_xhdl4 <= (ahbsram_req_int AND NOT ahbsram_req_d1) AND CONV_STD_LOGIC(HBURST_d = "000") ;
-- HRDATA generation
PROCESS (sramahb_rdata, HREADYIN, HREADYOUT_xhdl1 )
VARIABLE HRDATA_xhdl3_xhdl17 : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0);
BEGIN
IF ((HREADYOUT_xhdl1 AND HREADYIN) = '1') THEN
HRDATA_xhdl3_xhdl17 := sramahb_rdata;
ELSE
HRDATA_xhdl3_xhdl17 := sramahb_rdata;
END IF;
HRDATA_xhdl3 <= HRDATA_xhdl3_xhdl17;
END PROCESS;
END ARCHITECTURE translated;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PC is
port(clk:in std_logic;
JMP:in std_logic_vector(3 downto 0);
load:in std_logic;
PC:out std_logic_vector(3 downto 0)
);
end PC;
architecture bhv of PC is
signal q1:std_logic_vector(3 downto 0);
begin
process(clk,q1,load)
begin
if(clk'event and clk='1') then
if load='1' then
q1<=JMP;
else
q1<=q1+1;
end if;
end if;
PC<=q1;
end process;
end bhv;
|
-- generated by newgenasym Tue May 16 21:02:41 2006
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity adp3338 is
port (
GND: INOUT STD_LOGIC;
\in\: INOUT STD_LOGIC;
\out\: INOUT STD_LOGIC;
OUT_T: INOUT STD_LOGIC);
end adp3338;
|
<reponame>Jak94/InterpolationFilters
-- Copyright 2017 <NAME>.
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”); you may not use this file except in
-- compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-- or agreed to in writing, software, hardware and materials distributed under
-- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the
-- specific language governing permissions and limitations under the License.
----------------------------------------------------------------------------------
-- Author: --
--
-- Create Date(mm/aaaa): 09/2017
-- Module Name: data_sink.vhd
-- Project: None
-- Description: Sample the output on rising clock edge if VOUT is '1', then print the results on a results_sim.txt
-- Dependencies: None
-- Revision:
-- 1.0 created
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use IEEE.numeric_std.all;
library std;
use std.textio.all;
entity data_sink is
port (
CLK : in std_logic;
RST_n : in std_logic;
VOUT : in std_logic;
DOUT : in std_logic_vector(16 downto 0));
end data_sink;
architecture beh of data_sink is
begin -- beh
process (CLK, RST_n)
file res_fp : text open WRITE_MODE is "./samples_TB_ProcessingElement/results_sim.txt";
variable line_out : line;
begin -- process
if RST_n = '0' then -- asynchronous reset (active low)
null;
elsif CLK'event and CLK = '1' then -- rising clock edge
if (VOUT = '1') then
write(line_out, to_integer(unsigned(DOUT)));
writeline(res_fp, line_out);
end if;
end if;
end process;
end beh;
|
<reponame>kardandon/SIMPLE-VGA-DRIVER-TO-DISPLAY-256-DIFFERENT-COLORS<gh_stars>0
-- Synthesizable Simple VGA Driver to Display All Possible Colors
-- EE240 class Bogazici University
-- Implemented on Xilinx Spartan VI FPGA chip
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE ieee.std_logic_arith.all ;
USE ieee.std_logic_unsigned.all;
entity ee240_vgadriver is
port (
nreset: in std_logic;
board_clk: in std_logic;
vsync: out std_logic;
hsync: out std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(1 downto 0));
end;
architecture arch_vga_driver of ee240_vgadriver is
component VH_signal is
Port (
Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
V_sync : out STD_LOGIC;
H_sync : out STD_LOGIC
);
end component;
component divider is
Port (
clk_in : in STD_LOGIC;
Reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end component;
component color_gen is
port (
reset: in std_logic;
clk: in std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(1 downto 0));
end component;
signal CLK25 : STD_LOGIC;
begin
divider0: divider port map(clk => board_clk, Reset => nreset, clk_out => CLK25);
color_gen0: color_gen port map(reset => nreset, clk => CLK25, red => red, green => green, blue => blue);
VH_signal0: VH_signal port map(Reset => nreset, Clock => CLK25, V_sync => vsync, H_sync => hsync);
end arch_vga_driver;
|
<filename>examples/example1/autogen/example1.vhd
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity MySyncAdder is port(
addClk_clk, addClk_reset_n: in std_ulogic;
isAdd: in std_ulogic; -- WIRE
useOldZ_asX: in std_ulogic; -- WIRE
useOldZ_asY: in std_ulogic; -- WIRE
xx: in u8; -- Latch
yy: in u8; -- Latch
zz: out u8 -- reg
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity MySyncLOP is port(
lopClk_clk, lopClk_reset_n: in std_ulogic;
oper: in u4; -- reg
rx: in u8; -- reg
ry: in u8; -- reg
xorMaskIdx: in unsigned(2 downto 0); -- reg
result: out u8; -- reg
lastAND: out u8 -- Latch
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity Example1 is port(
clk_clk, clk_reset_n: in std_ulogic;
in_ry: in u8; -- WIRE
outa: out u8; -- WIRE
outb: out u8 -- WIRE
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- MySyncAdder ------------------------------------
architecture rtl of MySyncAdder is
----- internal regs/wires/etc --------
signal dg_c_zz: u8;
signal dg_o_zz: u8;
begin
MyMainProcess: process (all)
variable srcX: u8;
variable srcY: u8;
begin
dg_c_zz <= dg_o_zz; -- reg preload
srcX := X"00"; -- local-var zero-init
srcY := X"00"; -- local-var zero-init
if (useOldZ_asX = '1') then
srcX := dg_o_zz;
else
srcX := yy;
end if;
if (useOldZ_asY = '1') then
srcY := dg_o_zz;
else
srcY := xx;
end if;
if (isAdd = '1') then
dg_c_zz <= (srcX + srcY);
else
dg_c_zz <= (srcX - srcY);
end if;
end process;
----[ sync clock pump for addClk ]------
process begin
wait until rising_edge(addClk_clk);
dg_o_zz <= dg_c_zz;
end process;
------[ output registers/wires/latches ] --------------
zz <= dg_o_zz;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- MySyncLOP ------------------------------------
architecture rtl of MySyncLOP is
signal ClockCounter: u32; -- reg
----- internal regs/wires/etc --------
signal dg_c_oper: u4;
signal dg_c_rx: u8;
signal dg_c_ry: u8;
signal dg_c_xorMaskIdx: unsigned(2 downto 0);
signal dg_c_result: u8;
signal dg_o_result: u8;
signal dg_l_lastAND: u8;
signal dg_c_ClockCounter: u32;
begin
calcResult: process (all)
variable xorRemap: unsigned(2 downto 0);
variable xorMask: u8;
variable tmpRes: u8;
begin
dg_c_result <= dg_o_result; -- reg preload
dg_l_lastAND <= dg_l_lastAND; -- latch preload
dg_c_ClockCounter <= ClockCounter; -- reg preload
xorRemap := "000"; -- local-var zero-init
xorMask := X"00"; -- local-var zero-init
tmpRes := X"00"; -- local-var zero-init
case xorMaskIdx is
when "000" => xorRemap := "011";
when "001" => xorRemap := "010";
when "010" => xorRemap := "001";
when "011" => xorRemap := "000";
when "100" => xorRemap := "010";
when others => xorRemap := "001";
end case;
case xorRemap is
when "000" => xorMask := X"FF";
when "001" => xorMask := X"11";
when "010" | "100" | "111" => xorMask := X"33";
when others => xorMask := X"00";
end case;
case oper is
when X"0" =>
tmpRes := (rx and ry);
dg_l_lastAND <= tmpRes;
when X"1" =>
tmpRes := (rx or ry);
when X"2" =>
tmpRes := (rx xor ry);
when X"3" =>
tmpRes := (not (rx or ry));
when others => null;
end case;
dg_c_result <= (tmpRes xor xorMask);
dg_c_ClockCounter <= ClockCounter + X"00000001";
end process;
----[ sync clock pump for lopClk ]------
process begin
wait until rising_edge(lopClk_clk);
dg_o_result <= dg_c_result;
ClockCounter <= dg_c_ClockCounter;
if lopClk_reset_n = '0' then
dg_o_result <= X"99";
ClockCounter <= X"00000100";
end if;
end process;
------[ output registers/wires/latches ] --------------
result <= dg_o_result;
lastAND <= dg_l_lastAND;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- Example1 ------------------------------------
architecture rtl of Example1 is
type MyFSM is (
MyFSM_init,
MyFSM_adding,
MyFSM_add_oldx,
MyFSM_add_oldy,
MyFSM_lopping);
signal fsm: MyFSM; -- reg
signal count: u8; -- reg
----- internal regs/wires/etc --------
signal dg_w_outa: u8;
signal dg_w_outb: u8;
signal dg_c_fsm: MyFSM;
signal dg_c_count: u8;
----- unit signals -------------
signal adder_isAdd : std_ulogic;
signal adder_useOldZ_asX : std_ulogic;
signal adder_useOldZ_asY : std_ulogic;
signal adder_xx : u8;
signal adder_yy : u8;
signal adder_zz : u8;
signal lop_oper : u4;
signal dg_c_lop_oper : u4;
signal lop_rx : u8;
signal dg_c_lop_rx : u8;
signal lop_ry : u8;
signal dg_c_lop_ry : u8;
signal lop_xorMaskIdx : unsigned(2 downto 0);
signal dg_c_lop_xorMaskIdx : unsigned(2 downto 0);
signal lop_result : u8;
signal lop_lastAND : u8;
signal lop_lopClk_clk, lop_lopClk_reset_n : std_ulogic;
function ChooseLOPOperation (counter : u8) return u4 is
variable result: u4;
begin
result := X"0"; -- local-var zero-init
case counter(1 downto 0) is
when "00" => result := X"1";
when "01" => result := X"2";
when "10" => result := X"3";
when others => result := X"0";
end case;
return result;
end;
begin
dg_comb_proc1: process (all)
begin
dg_w_outa <= X"00"; -- wire pre-zero-init
dg_w_outb <= X"00"; -- wire pre-zero-init
dg_w_outa <= adder_zz;
dg_w_outb <= (lop_result + lop_lastAND);
end process;
main: process (all)
variable resetCount: std_ulogic;
begin
dg_c_fsm <= fsm; -- reg preload
dg_c_count <= count; -- reg preload
adder_isAdd <= '0'; -- wire pre-zero-init
adder_useOldZ_asX <= '0'; -- wire pre-zero-init
adder_useOldZ_asY <= '0'; -- wire pre-zero-init
adder_xx <= adder_xx; -- latch preload
adder_yy <= adder_yy; -- latch preload
dg_c_lop_oper <= lop_oper; -- reg preload
dg_c_lop_rx <= lop_rx; -- reg preload
dg_c_lop_xorMaskIdx <= lop_xorMaskIdx; -- reg preload
resetCount := '0'; -- local-var zero-init
case fsm is
when MyFSM_init =>
dg_c_fsm <= MyFSM_adding;
resetCount := '1';
adder_yy <= in_ry;
when MyFSM_adding =>
adder_isAdd <= '1';
adder_xx <= count;
if (dg_boolToBit(count = X"05") = '1') then
dg_c_fsm <= MyFSM_add_oldx;
resetCount := '1';
end if;
when MyFSM_add_oldx =>
adder_useOldZ_asX <= '1';
if (dg_boolToBit(count = X"03") = '1') then
dg_c_fsm <= MyFSM_add_oldy;
resetCount := '1';
end if;
when MyFSM_add_oldy =>
adder_useOldZ_asY <= '1';
adder_xx <= count;
dg_c_fsm <= MyFSM_lopping;
resetCount := '1';
when MyFSM_lopping =>
dg_c_lop_oper <= ChooseLOPOperation(count);
dg_c_lop_rx <= lop_rx + X"01";
dg_c_lop_xorMaskIdx <= lop_xorMaskIdx - "001";
when others => null;
end case;
if ((not clk_reset_n) = '1') then
dg_c_lop_oper <= X"2";
end if;
if (resetCount = '1') then
dg_c_count <= X"00";
else
dg_c_count <= (count + 1);
end if;
end process;
-------[ sub-units ]-----------
adder : entity work.MySyncAdder port map(
addClk_clk => clk_clk,
addClk_reset_n => clk_reset_n,
isAdd => adder_isAdd,
useOldZ_asX => adder_useOldZ_asX,
useOldZ_asY => adder_useOldZ_asY,
xx => adder_xx,
yy => adder_yy,
zz => adder_zz
);
lop : entity work.MySyncLOP port map(
lopClk_clk => lop_lopClk_clk,
lopClk_reset_n => lop_lopClk_reset_n,
oper => lop_oper,
rx => lop_rx,
ry => lop_ry,
xorMaskIdx => lop_xorMaskIdx,
result => lop_result,
lastAND => lop_lastAND
);
-------[ links ]----------
lop_lopClk_clk <= clk_clk;
lop_lopClk_reset_n <= clk_reset_n;
----[ sync clock pump for clk ]------
process begin
wait until rising_edge(clk_clk);
fsm <= dg_c_fsm;
count <= dg_c_count;
lop_oper <= dg_c_lop_oper;
lop_rx <= dg_c_lop_rx;
lop_ry <= dg_c_lop_ry;
lop_xorMaskIdx <= dg_c_lop_xorMaskIdx;
if clk_reset_n = '0' then
fsm <= MyFSM_init;
end if;
end process;
------[ output registers/wires/latches ] --------------
outa <= dg_w_outa;
outb <= dg_w_outb;
end;
|
<gh_stars>0
-- lcdctrl.vhd : High-level LCD controller with BUSY
-- Copyright (C) 2011/2012 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): <NAME> <xvasic11 AT stud.fit.vutbr.cz>
--
-- LICENSE TERMS
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. All advertising materials mentioning features or use of this software
-- or firmware must display the following acknowledgement:
--
-- This product includes software developed by the University of
-- Technology, Faculty of Information Technology, Brno and its
-- contributors.
--
-- 4. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software or firmware is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity lcd_controller is
generic (
CMDLEN : integer := 10*10000; -- doba trvani prikazu (1 ms @ 20MHz ~ 10000)
LCD2x16 : boolean := False -- radic pro 2x16 nebo 1x16 LCD displej
);
port (
RST : in std_logic;
CLK : in std_logic;
-- interni rozhrani
DATA_IN : in std_logic_vector (7 downto 0);
WRITE_EN : in std_logic;
BUSY : out std_logic;
--- rozhrani LCD displeje
DISPLAY_RS : out std_logic;
DISPLAY_DATA : inout std_logic_vector(7 downto 0);
DISPLAY_RW : out std_logic;
DISPLAY_EN : out std_logic := '1'
);
end lcd_controller;
architecture behavioral of lcd_controller is
type FSMState is (init, init0, init1, init2, init3, idle, w0, w1, w2, w3, wa0, wa1, wa2, wa3);
function lcdaddrbits(islcd2x16: boolean) return integer is
begin
-- pragma translate off
-- pro simulaci vzdy 1 radkovy displej
return 4;
-- pragma translate on
if (islcd2x16) then return 5; end if;
return 4;
end function;
function lcdhas2rows(islcd2x16: boolean) return boolean is
begin
-- pragma translate off
-- pro simulaci vzdy 1 radkovy displej
return false;
-- pragma translate on
return (islcd2x16);
end function;
signal pstate : FSMState := init; -- FSM present state
signal nstate : FSMState; -- FSM next state
signal addr_reg : std_logic_vector(lcdaddrbits(LCD2x16)-1 downto 0) := (others => '0');
signal addr_inc : std_logic;
signal data_reg : std_logic_vector(7 downto 0);
signal init_data : std_logic_vector(8 downto 0);
signal datareg_en : std_logic;
signal data_sel : std_logic_vector(1 downto 0);
signal t_cnt : integer range 0 to CMDLEN-1 := 0;
signal t_lst : std_logic := '0';
signal t_en : std_logic;
constant INIT_ITEMS : integer := 5 + 8*2;
signal init_cnt : integer range 0 to INIT_ITEMS-1;
signal init_inc : std_logic;
signal init_lst : std_logic;
signal addr_data : std_logic_vector(7 downto 0);
begin
DISPLAY_RS <= '1' when (data_sel="11") else -- write char
init_data(8);
init_data <= "000111000" when (init_cnt=0) else -- Set Function
"000000001" when (init_cnt=1) else -- Clear Display
"000000010" when (init_cnt=2) else -- Cursor Home
"000001100" when (init_cnt=3) else -- Display on/off Control
"000000110" when (init_cnt=4) else -- Entry Mode Set
"001010000" when (init_cnt=5) else -- Own character #0x02, #0x0A
"100000001" when (init_cnt=6) else
"001010001" when (init_cnt=7) else
"100000001" when (init_cnt=8) else
"001010010" when (init_cnt=9) else
"100000001" when (init_cnt=10) else
"001010011" when (init_cnt=11) else
"100000101" when (init_cnt=12) else
"001010100" when (init_cnt=13) else
"100001001" when (init_cnt=14) else
"001010101" when (init_cnt=15) else
"100011111" when (init_cnt=16) else
"001010110" when (init_cnt=17) else
"100001000" when (init_cnt=18) else
"001010111" when (init_cnt=19) else
"100000100" when (init_cnt=20) else
"000000000";
DISPLAY_DATA <= init_data(7 downto 0) when (data_sel="01") else
addr_data when (data_sel="10") else -- set addr
data_reg when (data_sel="11") else -- write char
(others => 'Z');
addr_data <= "1" & addr_reg(4) & "00" & addr_reg(3 downto 0) when lcdhas2rows(LCD2x16) else -- LCD 2x16 (FITkit 2.x)
"1" & addr_reg(3) & "000" & addr_reg(2 downto 0); -- LCD 1x16 (FITkit 1.x)
process (RST, CLK)
begin
if (RST = '1') then
t_cnt <= 0;
elsif (CLK'event) and (CLK = '1') then
if (t_en = '1') then
t_lst <= '0';
if (t_cnt /= (CMDLEN-1)) then
t_cnt <= t_cnt + 1;
else
t_cnt <= 0;
t_lst <= '1';
end if;
end if;
end if;
end process;
-- data register
process(CLK, RST)
begin
if (RST = '1') then
data_reg <= (others => '0');
addr_reg <= (others => '0');
init_cnt <= 0;
elsif (CLK='1') and (CLK'event) then
if (WRITE_EN='1') and (datareg_en='1') then
data_reg <= DATA_IN;
end if;
if (addr_inc = '1') then
addr_reg <= addr_reg + 1;
end if;
if (init_inc = '1') then
init_cnt <= init_cnt + 1;
end if;
end if;
end process;
init_lst <= '1' when init_cnt = (INIT_ITEMS - 1) else '0';
-- FSM present state
process(CLK, RST)
begin
if (RST = '1') then
pstate <= init;
elsif (CLK='1') and (CLK'event) then
pstate <= nstate;
end if;
end process;
-- FSM next state logic, output logic
process(pstate, WRITE_EN, t_lst, init_lst)
begin
nstate <= init;
DISPLAY_RW <= '0';
DISPLAY_EN <= '0';
data_sel <= "00";
datareg_en <= '0';
BUSY <= '1';
t_en <= '1';
addr_inc <= '0';
init_inc <= '0';
case pstate is
when init =>
nstate <= init0;
-- Display Init
when init0 =>
nstate <= init0;
if (t_lst = '1') then
nstate <= init1;
end if;
data_sel <= "01";
when init1 =>
nstate <= init1;
if (t_lst = '1') then
nstate <= init2;
end if;
data_sel <= "01";
DISPLAY_EN <= '1';
when init2 =>
nstate <= init2;
if (t_lst = '1') then
nstate <= init3;
end if;
data_sel <= "01";
when init3 =>
nstate <= init3;
if (t_lst = '1') then
init_inc <= '1';
if (init_lst = '1') then
nstate <= idle;
else
nstate <= init0;
end if;
end if;
data_sel <= "01";
-- Idle
when idle =>
BUSY <= '0';
t_en <= '0';
datareg_en <= '1';
nstate <= idle;
if (WRITE_EN = '1') then
nstate <= wa0;
end if;
-- Write address
when wa0 =>
nstate <= wa0;
if (t_lst = '1') then
nstate <= wa1;
end if;
data_sel <= "10";
when wa1 =>
nstate <= wa1;
if (t_lst = '1') then
nstate <= wa2;
end if;
data_sel <= "10";
DISPLAY_EN <= '1';
when wa2 =>
nstate <= wa2;
if (t_lst = '1') then
nstate <= wa3;
end if;
data_sel <= "10";
when wa3 =>
nstate <= wa3;
if (t_lst = '1') then
nstate <= w0;
addr_inc <= '1';
end if;
data_sel <= "10";
-- Write character
when w0 =>
nstate <= w0;
if (t_lst = '1') then
nstate <= w1;
end if;
data_sel <= "11";
when w1 =>
nstate <= w1;
if (t_lst = '1') then
nstate <= w2;
end if;
data_sel <= "11";
DISPLAY_EN <= '1';
when w2 =>
nstate <= w2;
if (t_lst = '1') then
nstate <= w3;
end if;
data_sel <= "11";
when w3 =>
nstate <= w3;
if (t_lst = '1') then
nstate <= idle;
end if;
data_sel <= "11";
end case;
end process;
end behavioral;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Jan 29 20:27:27 2019
-- Host : ManoharVohra-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top custom_backward_backward_lite_0_0 -prefix
-- custom_backward_backward_lite_0_0_ custom_backward_backward_lite_0_0_stub.vhdl
-- Design : custom_backward_backward_lite_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity custom_backward_backward_lite_0_0 is
Port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
in_stream_TVALID : in STD_LOGIC;
in_stream_TREADY : out STD_LOGIC;
in_stream_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
in_stream_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end custom_backward_backward_lite_0_0;
architecture stub of custom_backward_backward_lite_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n,in_stream_TVALID,in_stream_TREADY,in_stream_TDATA[31:0],in_stream_TLAST[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "backward_lite,Vivado 2018.2";
begin
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CONTROLUNIT IS PORT (
INSTRUCTION:IN STD_LOGIC_VECTOR(6 DOWNTO 0);
ALU_SELECTORS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
TWO_FETCHES,OP_GROUP:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
BRANCH,MR,MW,P_IN,P_OUT,SP_INC,SP_DEC,WB1,WB2,CALL,RET,
ALU_ENABLE,RTI,NO_OPERANDS,IGNORE_RSRC2:OUT STD_LOGIC;
BUFFERWRITEENABLE : IN STD_LOGIC ;
TWO_FETCHES_FROM_FETCHING : IN STD_LOGIC;
WRONGDECISION:IN STD_LOGIC) ;
END CONTROLUNIT ;
ARCHITECTURE BEHAVIORAL OF CONTROLUNIT IS
BEGIN
PROCESS(INSTRUCTION,BUFFERWRITEENABLE,TWO_FETCHES_FROM_FETCHING,WRONGDECISION)
BEGIN
IF BUFFERWRITEENABLE='1' OR TWO_FETCHES_FROM_FETCHING = '1' OR WRONGDECISION = '1' THEN
BRANCH <='0';
MR <='0';
MW <='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='1';
IGNORE_RSRC2 <='1';
ELSE
CASE (INSTRUCTION) IS
WHEN "0000000" => --NOP
BRANCH <='0';
MR <='0';
MW <='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='1';
IGNORE_RSRC2 <='1';
WHEN
"0000001" => --NOT
BRANCH<='0';
ALU_SELECTORS<="0000";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN
"0000010" => --INC
BRANCH<='0';
ALU_SELECTORS<="0001";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "0000011" => --DEC
BRANCH<='0';
ALU_SELECTORS<="0010";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "0000100" => --OUT
BRANCH<='0';
MR<='0';
MW<='1';
P_IN<='0';
P_OUT<='1';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN
"0000101" => --IN
BRANCH<='0';
MR<='1';
MW<='0';
P_IN<='1';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "0100000" => --JZ
BRANCH<='1';
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="01";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "0100001" => --JMP
BRANCH<='0';
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="01";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "0100010" => --CALL
BRANCH<='0';
MR<='0';
MW<='1';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='1';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="01";
CALL<='1';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "0100111" => --RET
BRANCH<='0';
MR<='1';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='1';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="01";
CALL<='0';
RET<='1';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='1';
IGNORE_RSRC2 <='1';
WHEN "0100101" => --RTI
BRANCH<='0';
MR<='1';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='1';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="01";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='1';
NO_OPERANDS <='1';
IGNORE_RSRC2 <='1';
WHEN "1000000" => --SWAP
BRANCH<='0';
ALU_SELECTORS<="0011";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='1';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='0';
WHEN "1000001" => --ADD
BRANCH<='0';
ALU_SELECTORS<="0100";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='0';
WHEN "1000010" => --OR
BRANCH<='0';
ALU_SELECTORS<="1000";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='0';
WHEN "1000011" => --SUB
BRANCH<='0';
ALU_SELECTORS<="0110";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='0';
WHEN "1000100" => --AND
BRANCH<='0';
ALU_SELECTORS<="0111";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='0';
WHEN "1001101" => --IADD
BRANCH<='0';
ALU_SELECTORS<="0101";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="01";
WB1<='1';
WB2<='0';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "1001110" => --SHL
BRANCH<='0';
ALU_SELECTORS<="1001";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="01";
WB1<='0';
WB2<='1';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "1001111" => --SHR
BRANCH<='0';
ALU_SELECTORS<="1011";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="01";
WB1<='0';
WB2<='1';
OP_GROUP<="10";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "1100000" => --PUSH
BRANCH<='0';
MR<='0';
MW<='1';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='1';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="11";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "1100001" => --POP
BRANCH<='0';
MR<='1';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='1';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='1';
WB2<='0';
OP_GROUP<="11";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "1101010" => --LDM
BRANCH<='0';
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="01";
WB1<='1';
WB2<='0';
OP_GROUP<="11";
CALL<='0';
RET<='0';
ALU_ENABLE<='1';
ALU_SELECTORS<="1010";
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "1110101" => --LDD
BRANCH<='0';
MR<='1';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="10";
WB1<='1';
WB2<='0';
OP_GROUP<="11";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN "1110110" => --STD
BRANCH<='0';
MR<='0';
MW<='1';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="10";
WB1<='0';
WB2<='0';
OP_GROUP<="11";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='1';
WHEN OTHERS =>
BRANCH<='0';
ALU_SELECTORS<="0000";
MR<='0';
MW<='0';
P_IN<='0';
P_OUT<='0';
SP_INC<='0';
SP_DEC<='0';
TWO_FETCHES<="00";
WB1<='0';
WB2<='0';
OP_GROUP<="00";
CALL<='0';
RET<='0';
ALU_ENABLE<='0';
RTI<='0';
NO_OPERANDS <='0';
IGNORE_RSRC2 <='0';
END CASE;
END IF ;
END PROCESS ;
END BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
--
-- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
-- All of the components are assembled and instanciated on this board.
--
entity level_shift_test01 is
port (
pi_base_clk : in std_logic;
pi_sw : in std_logic_vector(9 downto 0);
pi_btn_n : in std_logic_vector(3 downto 0);
po_led_r : out std_logic_vector(9 downto 0);
po_led_g : out std_logic_vector(7 downto 0);
pio_gpio0 : inout std_logic_vector(7 downto 0);
pio_gpio1 : inout std_logic_vector(7 downto 0)
);
end level_shift_test01;
architecture rtl of level_shift_test01 is
--slow down button update timing.
constant FREQ_DEVIDE : integer := 1000000;
signal reg_cnt_devider : integer range 0 to FREQ_DEVIDE;
signal reg_8bit_cnt : std_logic_vector(7 downto 0);
signal wr_rst_n : std_logic;
signal wr_direction : std_logic;
signal wr_dvd : std_logic;
begin
wr_rst_n <= pi_btn_n(0);
wr_direction <= pi_sw(9);
wr_dvd <= pi_sw(8);
gpio_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
pio_gpio0 <= (others => 'Z');
pio_gpio1 <= (others => 'Z');
po_led_r <= (others => '0');
po_led_g <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (wr_direction = '0') then
--case off = cp gpio 1 to 0
pio_gpio0 <= (others => 'Z');
pio_gpio1 <= pi_sw(7 downto 0);
po_led_r <= pi_sw;
po_led_g <= pio_gpio0;
else
--on = cp gpio 0 to 1
pio_gpio0 <= reg_8bit_cnt;
pio_gpio1 <= (others => 'Z');
po_led_r(7 downto 0) <= pio_gpio1;
po_led_r(9 downto 8) <= pi_sw(9 downto 8);
po_led_g <= reg_8bit_cnt;
end if;
end if;
end process;
--key3 button proc.
key3_cnt_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_8bit_cnt <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (wr_dvd = '1') then
--slow down count up
if (pi_btn_n(3) = '0' and reg_cnt_devider = 0) then
reg_8bit_cnt <= reg_8bit_cnt + 1;
end if;
else
--clock speed count up.
if (pi_btn_n(3) = '0') then
reg_8bit_cnt <= reg_8bit_cnt + 1;
end if;
end if;
end if;
end process;
--
cnt_devide_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_cnt_devider <= 0;
elsif (rising_edge(pi_base_clk)) then
reg_cnt_devider <= reg_cnt_devider + 1;
end if;
end process;
end rtl;
|
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.env.finish;
entity testbench is
end entity testbench;
architecture tb of testbench is
component ALU is
generic (N: natural :=32);
port
(
CLK : in std_logic;
A : in std_logic_vector (N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
Funct_3 : in std_logic_vector (2 downto 0);
Funct_7 : in std_logic_vector (6 downto 0);
Result : out std_logic_vector (N-1 downto 0);
Zero : out std_logic;
Sign : out std_logic;
Overflow : out std_logic
);
end component ALU;
signal clk,z,s,o : std_logic := '0';
signal a,b,r : std_logic_vector (3 downto 0) := "0000";
signal f3 : std_logic_vector (2 downto 0) := "000";
signal f7 : std_logic_vector (6 downto 0) := "0000000";
signal One : std_logic_vector (3 downto 0) := "0001";
constant CLK_PERIOD : time := 20 ns;
constant N_nat : natural := 4;
signal done : boolean := false;
begin
b <= "0001";
gen_clk: process(clk) is
begin
if not done then
clk <= not clk after CLK_PERIOD/2;
else
clk <= '0';
end if;
end process gen_clk;
A_stimulus : process is
begin
if not done then
wait for 2*CLK_PERIOD;
a <= std_logic_vector(unsigned(a) + unsigned(One));
end if;
end process A_stimulus;
F7_F3_stimulus : process is
begin
if not done then
wait for 33*CLK_PERIOD;
f7 <= "0100000";
end if;
wait for 10*CLK_PERIOD;
done <= true;
end process F7_F3_stimulus;
uut_ALU : ALU generic map(N => 4)
port map (clk,a,b,f3,f7,r,z,s,o);
finish_process : process (clk) is
begin
if done then
finish;
end if;
end process finish_process;
end tb;
|
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<KEY>
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`protect end_protected
|
<filename>alsu.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY ALSU IS
PORT(
A,B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CIN : IN STD_LOGIC;
COUT : out STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
FLAGS : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END ALSU;
ARCHITECTURE ALSU_FUNC OF ALSU IS
COMPONENT ALU IS
PORT(
A,B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CIN : IN STD_LOGIC;
COUT: OUT STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT PARTA IS
PORT(
A,B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
CIN : IN STD_LOGIC;
COUT: OUT STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
SIGNAL F0,F1,TMP_F: STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL C0,C1: STD_LOGIC;
begin
ALU_C: ALU PORT MAP (B,A,S,CIN,C0,F0);
PART_A: PARTA PORT MAP (A,B,S (1 DOWNTO 0),CIN,C1,F1);
F<= F1 WHEN S(3 DOWNTO 2)="00"
ELSE F0;
COUT<= C1 WHEN S(3 DOWNTO 2)="00"
ELSE C0;
TMP_F <= F1 WHEN S(3 DOWNTO 2)="00"
ELSE F0;
-- Flag(0) => C
-- Flag(1) => Z
-- Flag(2) => N
-- Flag(3) => P
-- Flag(4) => O
-- FLAG <= (OTHERS => 'Z');
FLAGS(0) <= C1 WHEN S(3 DOWNTO 2)="00"
ELSE C0;
FLAGS(1) <= '1' WHEN TMP_F = X"0000"
ELSE '0';
FLAGS(2) <= TMP_F(15);
FLAGS(3) <= NOT TMP_F(0);
FLAGS(4) <= '1' WHEN (S="0001" AND ((A(15)='0' AND B(15)='0' AND TMP_F(15)='1') OR (A(15)='1' AND B(15)='1' AND TMP_F(15)='0')))
OR (S="0010" AND ((A(15)='0' AND B(15)='1' AND TMP_F(15)='1') OR (A(15)='1' AND B(15)='0' AND TMP_F(15)='0')))
ELSE '0';
END ALSU_FUNC;
|
<gh_stars>0
-- File : address_decoder_v1.vhd
-- Author : <NAME>
-- Team : Arun and <NAME> Team Mentor : <NAME>
-- usage : level 2 of control flow , interfaces the address decoder and master controller. , has statemachines for all the modes of instructions
-- supported by master controller. generates the required control signals for data flow and address decoder.
-- DLM : 6/23/2016 7:36 AM
-- Tested : modelsim student edition 10.4 a
-- Todo : none.
-- error : none.
-- warning: none.
-- copyright : ArunJeevaraj. 2016. Lund University.
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity address_decoder_v1 is
port(
address : out std_logic_vector(13 downto 0);
row_cnt : in std_logic_vector(5 downto 0);
row_set : in std_logic_vector(3 downto 0);
mat_index : in std_logic_vector(3 downto 0);
mat_order : in std_logic_vector(5 downto 0);
ram_sel_in: in std_logic_vector(3 downto 0);
to_ram_sel: out std_logic_vector(3 downto 0)
);
end entity;
architecture beh of address_decoder_v1 is
-- used to fill up the LUT.
-- decimal to hex.. max 10 bits needed log2(O_60*14)
-- may use 13 bits of constant for row offset address. as it only needs 13 bits.
-- and for mat, index use seperate constants that are 14 bits long.
constant O_8 : unsigned(13 downto 0):="00"&x"008"; -- offset by 8.
constant O_12 : unsigned(13 downto 0):="00"&x"00c"; -- offset by 12.
constant O_16 : unsigned(13 downto 0):="00"&x"010"; -- offset by 16.
constant O_20 : unsigned(13 downto 0):="00"&x"014"; -- offest by 20.
constant O_24 : unsigned(13 downto 0):="00"&x"018"; -- offset by 24.
constant O_28 : unsigned(13 downto 0):="00"&x"01C"; -- offset by 28.
constant O_32 : unsigned(13 downto 0):="00"&x"020"; -- offset by 32.
constant O_36 : unsigned(13 downto 0):="00"&x"024"; -- offset by 36.
constant O_40 : unsigned(13 downto 0):="00"&x"028"; -- offset by 40.
constant O_44 : unsigned(13 downto 0):="00"&x"02c"; -- offset by 44.
constant O_48 : unsigned(13 downto 0):="00"&x"030"; -- offset by 48.
constant O_52 : unsigned(13 downto 0):="00"&x"034"; -- offset by 52.
constant O_56 : unsigned(13 downto 0):="00"&x"038"; -- offset by 52.
constant O_60 : unsigned(13 downto 0):="00"&x"03c"; -- offset by 60.
constant O_64 : unsigned(13 downto 0):="00"&x"040"; -- offset by 64.
constant O_80 : unsigned(13 downto 0):="00"&x"050"; -- offset by 80.
constant O_100 : unsigned(13 downto 0):="00"&x"064"; -- offset by 80.
constant O_144 : unsigned(13 downto 0):="00"&x"090"; -- offset by 80.
constant O_196 : unsigned(13 downto 0):="00"&x"0c4"; -- offset by 80.
constant O_256 : unsigned(13 downto 0):="00"&x"100"; -- offset by 80.
constant O_324 : unsigned(13 downto 0):="00"&x"144"; -- offset by 80.
constant O_400 : unsigned(13 downto 0):="00"&x"190"; -- offset by 80.
constant O_484 : unsigned(13 downto 0):="00"&x"1e4"; -- offset by 80.
constant O_576 : unsigned(13 downto 0):="00"&x"240"; -- offset by 80.
constant O_676 : unsigned(13 downto 0):="00"&x"2a4"; -- offset by 80.
constant O_784 : unsigned(13 downto 0):="00"&x"310"; -- offset by 80.
constant O_900 : unsigned(13 downto 0):="00"&x"384"; -- offset by 80.
constant c_test : unsigned(3 downto 0):="1010";
--- zeros bit to concatenate.
constant
ZEROS_8BL : unsigned(7 downto 0) :=(others=>'0');
-- mat_index address max bits needed .. 14 log2(60*15*15)
signal mat_index_address, -- add all these three addresses to get the address out.
row_set_address,
row_cnt_address,
address_out :unsigned(13 downto 0); -- generate the offset addresses.
signal enc_mat_order: std_logic_vector(3 downto 0); -- only multiples of 4 is used for LUT. so to optimize the LUT.
-- encode the mat_order to a 4 bit value from the 6 bit value.
begin
-- only multiples of 4 is used for LUT. so to optimize the LUT.
-- encode the mat_order to a 4 bit value from the 6 bit value.
mat_order_encode: process(mat_order)
begin
case mat_order is
when "001000"=> --8
enc_mat_order <=x"0";
when "001100"=> --12
enc_mat_order <=x"1";
when "010000"=> --16
enc_mat_order <=x"2";
when "010100"=>-- d20
enc_mat_order <=x"3";
when "011000"=>-- d24
enc_mat_order <=x"4";
when "010110"=>-- d28
enc_mat_order <=x"5";
when "100000"=>-- d32
enc_mat_order <=x"6";
when "100100"=>-- d36
enc_mat_order <=x"7";
when "101000"=>-- d40
enc_mat_order <=x"8";
when "101100"=>-- d44
enc_mat_order <=x"9";
when "110000"=>-- d48
enc_mat_order <=x"a";
when "110100"=>-- d52
enc_mat_order <=x"b";
when "111000"=>-- d56
enc_mat_order <=x"c";
when "111100"=>-- d60
enc_mat_order <=x"d";
-- optional to encode 63 as 64... ? have to change the row_cnt_max and other max values in the mat controller if need be.
when others =>
enc_mat_order <= (others=>'0');
end case;
end process;
-- get the offset address from mat_order- and row_set from mat controller.- A LUT is set up here for that.
-- this can be placed in a ram, but for this much of table a look up table should suffix.
row_set_address_gen: process(enc_mat_order,row_set)
begin
case enc_mat_order is
-- only making for multiples of d4.
-- for four no offset needed.
when x"0"=>-- when mat_order is d8
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_8;
when others=>
row_set_address <= (others=>'0');
end case;
when x"1"=>-- d12
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_12;
when x"2"=>
row_set_address <= O_24;
when others=>
row_set_address <= (others=>'0');
end case;
when x"2"=>--d16
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_16;
when x"2"=>
row_set_address <= O_32;
when x"3"=>
row_set_address <= O_48;
when others=> -- is not used for the d16 case.
row_set_address <= (others=>'0');
end case;
when x"3"=>-- d20
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_20;
when x"2"=>
row_set_address <= O_40;
when x"3"=>
row_set_address <= O_60;
when x"4"=>
row_set_address <= O_80;
when others=>
row_set_address <= (others=>'0');
end case;
when x"4"=>-- d24
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_24;
when x"2"=>
row_set_address <= O_48;
when x"3"=>
row_set_address <= O_48 + O_24; --O_72.
when x"4"=>
row_set_address <= O_48 + O_48; --O_96.
when x"5"=>
row_set_address <= O_48 + O_48 + O_48 + O_24; --O_120
when others=>
row_set_address <= (others=>'0');
end case;
when x"5"=>-- d28
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_28;
when x"2"=>
row_set_address <= O_28 + O_28; --56.
when x"3"=>
row_set_address <= O_28 + O_28 + O_28;
when x"4"=>
row_set_address <= O_28 + O_28 + O_28 + O_28;
when x"5"=>
row_set_address <= O_28 + O_28 + O_28 + O_28 + O_28;
when x"6"=>
row_set_address <= O_28 + O_28 + O_28 + O_28 + O_28 + O_28;
when others=>
row_set_address <= (others=>'0');
end case;
when x"6"=>-- d32
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_32;
when x"2"=>
row_set_address <= O_32 + O_32;
when x"3"=>
row_set_address <= O_32 + O_32 + O_32;
when x"4"=>
row_set_address <= O_32 + O_32 + O_32 + O_32;
when x"5"=>
row_set_address <= O_32 + O_32 + O_32 + O_32 + O_32;
when x"6"=>
row_set_address <= O_32 + O_32 + O_32 + O_32 + O_32 + O_32;
when x"7"=>
row_set_address <= O_32 + O_32 + O_32 + O_32 + O_32 + O_32 + O_32;
when others=>
row_set_address <= (others=>'0');
end case;
when x"7"=>-- d36
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_36;
when x"2"=>
row_set_address <= O_36 + O_36;
when x"3"=>
row_set_address <= O_36 + O_36 + O_36;
when x"4"=>
row_set_address <= O_36 + O_36 + O_36 + O_36;
when x"5"=>
row_set_address <= O_36 + O_36 + O_36 + O_36 + O_36;
when x"6"=>
row_set_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"7"=>
row_set_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"8"=>
row_set_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when others=>
row_set_address <= (others=>'0');
end case;
when x"8"=>-- d40
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_40;
when x"2"=>
row_set_address <= O_40 + O_40;
when x"3"=>
row_set_address <= O_40 + O_40 + O_40;
when x"4"=>
row_set_address <= O_40 + O_40 + O_40 + O_40;
when x"5"=>
row_set_address <= O_40 + O_40 + O_40 + O_40 + O_40;
when x"6"=>
row_set_address <= O_40 + O_40 + O_40 + O_40 + O_40 + O_40;
when x"7"=>
row_set_address <= O_40 + O_40 + O_40 + O_40 + O_40 + O_40 + O_40;
when x"8"=>
row_set_address <= O_40 + O_40 + O_40 + O_40 + O_40 + O_40 + O_40 + O_40;
when x"9"=>
row_set_address <= O_40 + O_40 + O_40 + O_40 + O_40 + O_40 + O_40 + O_40 + O_40;
when others=>
row_set_address <= (others=>'0');
end case;
when x"9"=>-- d44
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_44;
when x"2"=>
row_set_address <= O_44 + O_44;
when x"3"=>
row_set_address <= O_44 + O_44 + O_44;
when x"4"=>
row_set_address <= O_44 + O_44 + O_44 + O_44;
when x"5"=>
row_set_address <= O_44 + O_44 + O_44 + O_44 + O_44;
when x"6"=>
row_set_address <= O_44 + O_44 + O_44 + O_44 + O_44 + O_44;
when x"7"=>
row_set_address <= O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44;
when x"8"=>
row_set_address <= O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44;
when x"9"=>
row_set_address <= O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44;
when x"a"=>
row_set_address <= O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44 + O_44;
when others=>
row_set_address <= (others=>'0');
end case;
when x"a"=>-- d48
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_48;
when x"2"=>
row_set_address <= O_48 + O_48;
when x"3"=>
row_set_address <= O_48 + O_48 + O_48;
when x"4"=>
row_set_address <= O_48 + O_48 + O_48 + O_48;
when x"5"=>
row_set_address <= O_48 + O_48 + O_48 + O_48 + O_48;
when x"6"=>
row_set_address <= O_48 + O_48 + O_48 + O_48 + O_48 + O_48;
when x"7"=>
row_set_address <= O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48;
when x"8"=>
row_set_address <= O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48;
when x"9"=>
row_set_address <= O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48;
when x"a"=>
row_set_address <= O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48;
when x"b"=>
row_set_address <= O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48 + O_48;
when others=>
row_set_address <= (others=>'0');
end case;
when x"b"=>-- d52
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_52;
when x"2"=>
row_set_address <= O_52 + O_52;
when x"3"=>
row_set_address <= O_52 + O_52 + O_52;
when x"4"=>
row_set_address <= O_52 + O_52 + O_52 + O_52;
when x"5"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52;
when x"6"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52 + O_52;
when x"7"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52;
when x"8"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52;
when x"9"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52;
when x"a"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52;
when x"b"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52;
when x"c"=>
row_set_address <= O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52 + O_52;
when others=>
row_set_address <= (others=>'0');
end case;
when x"c"=>-- d56
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_56;
when x"2"=>
row_set_address <= O_56 + O_56;
when x"3"=>
row_set_address <= O_56 + O_56 + O_56;
when x"4"=>
row_set_address <= O_56 + O_56 + O_56 + O_56;
when x"5"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56;
when x"6"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when x"7"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when x"8"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when x"9"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when x"a"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when x"b"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when x"c"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when x"d"=>
row_set_address <= O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56 + O_56;
when others=>
row_set_address <= (others=>'0');
end case;
when x"d"=>-- d60
case row_set is
when x"0"=>
row_set_address <= (others=>'0');
when x"1"=>
row_set_address <= O_60;
when x"2"=>
row_set_address <= O_60 + O_60;
when x"3"=>
row_set_address <= O_60 + O_60 + O_60;
when x"4"=>
row_set_address <= O_60 + O_60 + O_60 + O_60;
when x"5"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60;
when x"6"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"7"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"8"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"9"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"a"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"b"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"c"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"d"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when x"e"=>
row_set_address <= O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60 + O_60;
when others=>
row_set_address <= (others=>'0');
end case;
when others =>
row_set_address <=(others =>'0');
end case;
end process;
--LUT for the MAT index.
-- have to generate matrix offset address based on mat_index and mat_order.
mat_index_address_gen: process(mat_index,enc_mat_order)
begin
case enc_mat_order is
when x"0"=>-- when mat_order is d8
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_16; -- 8*8/2
when x"2" =>
mat_index_address <= O_16 + O_16;
when x"3" =>
mat_index_address <= O_16 + O_16 + O_16;
when x"4" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16;
when x"5" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16;
when x"6" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"7" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"8" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"9" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"a" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"b" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"c" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"d" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"e" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when x"f" =>
mat_index_address <= O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16 + O_16;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"1"=>-- when 12
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_36; --12 *12/4
when x"2" =>
mat_index_address <= O_36 + O_36;
when x"3" =>
mat_index_address <= O_36 + O_36 + O_36;
when x"4" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36;
when x"5" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36;
when x"6" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"7" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"8" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"9" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"a" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"b" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"c" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"d" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"e" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when x"f" =>
mat_index_address <= O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36 + O_36;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"2"=> --16
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_64; --16*16/4 = 64
when x"2" =>
mat_index_address <= O_64 + O_64;
when x"3" =>
mat_index_address <= O_64 + O_64 + O_64;
when x"4" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64;
when x"5" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64;
when x"6" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"7" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"8" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"9" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"a" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"b" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"c" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"d" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"e" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when x"f" =>
mat_index_address <= O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64 + O_64;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"3"=> --20
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_100; --20*20/4 = 100
when x"2" =>
mat_index_address <= O_100 + O_100;
when x"3" =>
mat_index_address <= O_100 + O_100 + O_100;
when x"4" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100;
when x"5" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100;
when x"6" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"7" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"8" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"9" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"a" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"b" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"c" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"d" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"e" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when x"f" =>
mat_index_address <= O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100 + O_100;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"4"=> --24
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_144; --24*24/4 = 64
when x"2" =>
mat_index_address <= O_144 + O_144;
when x"3" =>
mat_index_address <= O_144 + O_144 + O_144;
when x"4" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144;
when x"5" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144;
when x"6" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"7" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"8" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"9" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"a" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"b" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"c" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"d" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"e" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when x"f" =>
mat_index_address <= O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144 + O_144;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"5"=> --28
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_196; --28*28/4 = 64
when x"2" =>
mat_index_address <= O_196 + O_196;
when x"3" =>
mat_index_address <= O_196 + O_196 + O_196;
when x"4" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196;
when x"5" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196;
when x"6" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"7" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"8" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"9" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"a" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"b" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"c" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"d" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"e" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when x"f" =>
mat_index_address <= O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196 + O_196;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"6"=> --32
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_256; --32*32/4 = 64
when x"2" =>
mat_index_address <= O_256 + O_256;
when x"3" =>
mat_index_address <= O_256 + O_256 + O_256;
when x"4" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256;
when x"5" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256;
when x"6" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"7" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"8" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"9" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"a" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"b" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"c" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"d" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"e" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when x"f" =>
mat_index_address <= O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256 + O_256;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"7"=> --36
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_324; --36*36/4 = 64
when x"2" =>
mat_index_address <= O_324 + O_324;
when x"3" =>
mat_index_address <= O_324 + O_324 + O_324;
when x"4" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324;
when x"5" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324;
when x"6" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"7" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"8" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"9" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"a" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"b" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"c" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"d" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"e" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when x"f" =>
mat_index_address <= O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324 + O_324;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"8"=>
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_400; --16*16/4 = 64
when x"2" =>
mat_index_address <= O_400 + O_400;
when x"3" =>
mat_index_address <= O_400 + O_400 + O_400;
when x"4" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400;
when x"5" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400;
when x"6" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"7" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"8" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"9" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"a" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"b" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"c" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"d" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"e" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when x"f" =>
mat_index_address <= O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400 + O_400;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"9"=>
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_484; --16*16/4 = 64
when x"2" =>
mat_index_address <= O_484 + O_484;
when x"3" =>
mat_index_address <= O_484 + O_484 + O_484;
when x"4" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484;
when x"5" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484;
when x"6" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"7" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"8" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"9" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"a" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"b" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"c" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"d" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"e" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when x"f" =>
mat_index_address <= O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484 + O_484;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"a"=>
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_576; --16*16/4 = 64
when x"2" =>
mat_index_address <= O_576 + O_576;
when x"3" =>
mat_index_address <= O_576 + O_576 + O_576;
when x"4" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576;
when x"5" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576;
when x"6" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"7" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"8" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"9" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"a" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"b" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"c" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"d" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"e" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when x"f" =>
mat_index_address <= O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576 + O_576;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"b"=>
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_676; --16*16/4 = 64
when x"2" =>
mat_index_address <= O_676 + O_676;
when x"3" =>
mat_index_address <= O_676 + O_676 + O_676;
when x"4" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676;
when x"5" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676;
when x"6" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"7" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"8" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"9" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"a" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"b" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"c" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"d" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"e" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when x"f" =>
mat_index_address <= O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676 + O_676;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"c"=>
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_784; --16*16/4 = 64
when x"2" =>
mat_index_address <= O_784 + O_784;
when x"3" =>
mat_index_address <= O_784 + O_784 + O_784;
when x"4" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784;
when x"5" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784;
when x"6" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"7" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"8" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"9" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"a" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"b" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"c" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"d" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"e" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when x"f" =>
mat_index_address <= O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784 + O_784;
when others=>
mat_index_address <= (others=>'0');
end case;
when x"d"=> --60
case mat_index is
when x"0" =>
mat_index_address <= (others=>'0');
when x"1" =>
mat_index_address <= O_900; --60*60/4 = 64
when x"2" =>
mat_index_address <= O_900 + O_900;
when x"3" =>
mat_index_address <= O_900 + O_900 + O_900;
when x"4" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900;
when x"5" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900;
when x"6" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"7" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"8" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"9" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"a" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"b" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"c" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"d" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"e" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when x"f" =>
mat_index_address <= O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900 + O_900;
when others=>
mat_index_address <= (others=>'0');
end case;
when others=>
mat_index_address <=(others =>'0');
end case;
end process;
-- row_cnt_address_generate.
row_cnt_address <= ZEROS_8BL & unsigned(row_cnt);
-- ram_sel_generate.
ram_sel_out_gen: process(ram_sel_in)
begin
if(ram_sel_in(3 downto 2)="01") then -- select all the RAMS.
to_ram_sel <="1111";
elsif(ram_sel_in(3 downto 2)="10") then -- deselect all the RAMS.
to_ram_sel <="0000";
else
case ram_sel_in(1 downto 0) is
when "00"=>
to_ram_sel<="0001";
when "01"=>
to_ram_sel<="0010";
when "10"=>
to_ram_sel<="0100";
when "11"=>
to_ram_sel<="1000";
when others=>
to_ram_sel<=(others=>'0');
end case;
end if;
end process;
address <= std_logic_vector(address_out);
-- decode the final address for the RAM.
address_gen : process (mat_index_address,row_set_address,row_cnt_address)
begin
address_out <= mat_index_address + row_set_address + row_cnt_address;
end process;
end beh;
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library ieee; use ieee.std_logic_1164.all;
entity tb_ROM_write_data is
end entity tb_ROM_write_data;
architecture writer of tb_ROM_write_data is
begin
process is
subtype word is std_logic_vector(0 to 7);
type load_file_type is file of word;
file load_file : load_file_type open write_mode is "tb_ROM.dat";
begin
write(load_file, word'(X"00"));
write(load_file, word'(X"01"));
write(load_file, word'(X"02"));
write(load_file, word'(X"03"));
write(load_file, word'(X"04"));
write(load_file, word'(X"05"));
write(load_file, word'(X"06"));
write(load_file, word'(X"07"));
write(load_file, word'(X"08"));
write(load_file, word'(X"09"));
write(load_file, word'(X"0A"));
write(load_file, word'(X"0B"));
write(load_file, word'(X"0C"));
write(load_file, word'(X"0D"));
write(load_file, word'(X"0E"));
write(load_file, word'(X"0F"));
wait;
end process;
end architecture writer;
library ieee; use ieee.std_logic_1164.all;
entity tb_ROM is
end entity tb_ROM;
architecture test of tb_ROM is
signal sel : std_logic;
signal address : std_logic_vector(3 downto 0);
signal data : std_logic_vector(0 to 7);
begin
dut : entity work.ROM(behavioral)
generic map ( load_file_name => "tb_ROM.dat" )
port map ( sel, address, data );
end architecture test;
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