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--
library IEEE;
use IEEE.std_logic_1164.all;
entity o3 is
port (
A: in STD_LOGIC;
B: in STD_LOGIC;
D: in STD_LOGIC;
Z: out STD_LOGIC
);
end o3;
architecture o3 of o3 is
begin
-- <<enter your statements here>>
Z <= A or B or D after 6ns;
end o3;
|
-- --------------------------------------------------------------------
-- Title : Test vector for numeric_bit package.
-- Test of minimum and maximum functions
-- Test of find_leftmost and find_leftmost functions
-- Test of + and - with a single BIT
-- Test of new to_signed and to_unsigned functions
-- Test of overloaded shift functions
-- Test of single bit boolean operations
--
-- Last Modified: $Date: 2007-09-12 08:57:33-04 $
-- RCS ID: $Id: test_bminmax.vhdl,v 1.2 2007-09-12 08:57:33-04 l435385 Exp $
--
-- Created for VHDL-200X-ft, <NAME> (<EMAIL>)
-- -----------------------------------------------------------------------------
library vunit_lib;
context vunit_lib.vunit_context;
entity test_bminmax is
generic (
runner_cfg : string);
end entity test_bminmax;
use std.textio.all;
library ieee;
use ieee.numeric_bit.all;
architecture testbench of test_bminmax is
procedure report_error (
errmes : in STRING; -- error message
actual : in UNSIGNED; -- data from algorithm
expected : in UNSIGNED) is -- reference data
begin -- function report_error
if actual /= expected then
report errmes & " " & to_string (actual) & " /= " & to_string (expected)
severity failure;
end if;
return;
end procedure report_error;
procedure report_error (
errmes : in STRING; -- error message
actual : in SIGNED; -- data from algorithm
expected : in SIGNED) is -- reference data
begin -- function report_error
if actual /= expected then
report errmes & " " & to_string (actual) & " /= " & to_string (expected)
severity failure;
end if;
return;
end procedure report_error;
signal start_booleantest, booleantest_done : BOOLEAN := false;
signal start_sizerestest, sizerestest_done : BOOLEAN := false;
signal start_matchtest, matchtest_done : BOOLEAN := false;
signal start_edgetest, edgetest_done : BOOLEAN := false; -- edge test
signal clk : BIT; -- clock signal (for edge test)
begin -- architecture testbench
-- purpose: Test routines for the minmax packages
testblock : process is
variable x, y, z, a, b, c : INTEGER; -- integers
variable as, bs, cs : SIGNED (7 downto 0); -- signed
variable asr, bsr, csr : SIGNED (0 to 7); -- reverse signed
variable au, bu, cu : UNSIGNED (7 downto 0); -- unsigned
variable aur, bur, cur : UNSIGNED (0 to 7); -- reverse signed
variable aslv, bslv : BIT_VECTOR (7 downto 0); -- slvs
variable check7uf1, check7uf2, check7uf3 : UNSIGNED (6 downto 0);
variable check7sf1, check7sf2, check7sf3 : SIGNED (6 downto 0);
variable s, s1 : BIT;
variable check6, check6t : UNSIGNED (5 downto 0);
variable check5, check5t : UNSIGNED (4 downto 0);
variable checks6, checks6t : SIGNED (5 downto 0);
variable checks5, checks5t : SIGNED (4 downto 0);
---------------------------------------------------------------------------
-- Name space violation! if we use "min" for minimum
constant delay : TIME := 1 min; -- one minute delay
begin -- process
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Test minimum and maximum") then
-- Integer versions to be placed in "standard" package.
--x := 1;
--y := 2;
--z := max (x,y);
--assert (z = 2) report "Max miscompare, 2" severity failure;
--z := max (y,x);
--assert (z = 2) report "Max miscompare, r2" severity failure;
--z := min (x, y);
--assert (z = 1) report "Min miscompare, 1" severity failure;
--z := min (y, x);
--assert (z = 1) report "Min miscompare, r1" severity failure;
as := "10000001";
bs := "00000010";
cs := maximum (as, bs);
assert (cs = "00000010") report "Max miscompare 02x" severity failure;
cs := maximum (bs, cs);
assert (cs = "00000010") report "Max miscompare 02xr" severity failure;
cs := minimum (as, bs);
assert (cs = "10000001") report "Min miscompare 81x" severity failure;
cs := minimum (bs, as);
assert (cs = "10000001") report "Min miscompare 81xr" severity failure;
au := "10000010";
bu := "00000100";
cu := maximum (au, bu);
assert (cu = "10000010") report "Max miscompare 82x" severity failure;
cu := maximum (bu, cu);
assert (cu = "10000010") report "Max miscompare 82xr" severity failure;
cu := minimum (au, bu);
assert (cu = "00000100") report "Min miscompare 04x" severity failure;
cu := minimum (bu, au);
assert (cu = "00000100") report "Min miscompare 04xr" severity failure;
elsif run("Checking the overloads for minimum and maximum") then
check5 := "00110";
check6 := "000111";
assert (check6 > check5) report to_string(check6) & " > " & to_string(check5)
& " miscompare" severity failure;
assert (check5 < check6) report to_string(check5) & " < " & to_string(check6)
& " miscompare" severity failure;
check6t := maximum (check6, check5);
assert (check6t = check6) report "max (" & to_string(check6) & ", "
& to_string(check5) & ") = " & to_string (check6t) severity failure;
check6t := maximum (check5, check6);
assert (check6t = check6) report "max (" & to_string(check5) & ", "
& to_string(check6) & ") = " & to_string (check6t) severity failure;
check6t := minimum (check6, check5);
assert (check6t = check5) report "min (" & to_string(check6) & ", "
& to_string(check5) & ") = " & to_string (check6t) severity failure;
check6t := minimum (check5, check6);
assert (check6t = check5) report "min (" & to_string(check5) & ", "
& to_string(check6) & ") = " & to_string (check6t) severity failure;
checks5 := "01110";
checks6 := "001111";
assert (checks6 > checks5) report to_string(checks6) & " > " & to_string(checks5)
& " miscompare" severity failure;
assert (checks5 < checks6) report to_string(checks5) & " < " & to_string(checks6)
& " miscompare" severity failure;
checks6t := maximum (checks6, checks5);
assert (checks6t = checks6) report "max (" & to_string(checks6) & ", "
& to_string(checks5) & ") = " & to_string (checks6t) severity failure;
checks6t := maximum (checks5, checks6);
assert (checks6t = checks6) report "max (" & to_string(checks5) & ", "
& to_string(checks6) & ") = " & to_string (checks6t) severity failure;
checks6t := minimum (checks6, checks5);
assert (checks6t = checks5) report "min (" & to_string(checks6) & ", "
& to_string(checks5) & ") = " & to_string (checks6t) severity failure;
checks6t := minimum (checks5, checks6);
assert (checks6t = checks5) report "min (" & to_string(checks5) & ", "
& to_string(checks6) & ") = " & to_string (checks6t) severity failure;
elsif run("Test find_rightmost and find_leftmost") then
au := "00100001";
x := find_rightmost (au, '1');
assert (x = 0) report "unsigned find_rightmost error 0" severity failure;
x := find_rightmost (au, '0');
assert (x = 1) report "find_rightmost error 1" severity failure;
x := find_leftmost (au, '1');
assert (x = 5) report "unsigned find_leftmost error 1" severity failure;
x := find_leftmost (au, '0');
assert (x = 7) report "unsigned find_leftmost error 7" severity failure;
au := "00000000";
x := find_rightmost (au, '1');
assert (x = -1) report "unsigned0 find_rightmost error -1" severity failure;
x := find_leftmost (au, '1');
assert (x = -1) report "unsigned0 find_leftmost error -1" severity failure;
au := "11111111";
x := find_rightmost (au, '0');
assert (x = -1) report "unsigned1 find_rightmost error -1" severity failure;
x := find_leftmost (au, '0');
assert (x = -1) report "unsigned1 find_leftmost error -1" severity failure;
as := "00100001";
x := find_rightmost (as, '1');
assert (x = 0) report "signed find_rightmost error 0" severity failure;
x := find_rightmost (as, '0');
assert (x = 1) report "signed find_rightmost error 1" severity failure;
x := find_leftmost (as, '1');
assert (x = 5) report "signed find_leftmost error 1" severity failure;
x := find_leftmost (as, '0');
assert (x = 7) report "signed find_leftmost error 7" severity failure;
as := "00000000";
x := find_rightmost (as, '1');
assert (x = -1) report "signed0 find_rightmost error -1" severity failure;
x := find_leftmost (as, '1');
assert (x = -1) report "signed0 find_leftmost error -1" severity failure;
as := "11111111";
x := find_rightmost (as, '0');
assert (x = -1) report "signed1 find_rightmost error -1" severity failure;
x := find_leftmost (as, '0');
assert (x = -1) report "signed1 find_leftmost error -1" severity failure;
elsif run("Test of + and - with a single BIT") then
s := '1';
au := "00000000";
bu := au + s;
cu := "00000001";
assert (bu = cu) report to_string(au) & " + " & BIT'image(s) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '0';
au := "00000000";
bu := au + s;
cu := "00000000";
assert (bu = cu) report to_string(au) & " + " & BIT'image(s) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '1';
au := "11111111";
bu := au + s;
cu := "00000000";
assert (bu = cu) report to_string(au) & " + " & BIT'image(s) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '1';
au := "00000000";
bu := s + au;
cu := "00000001";
assert (bu = cu) report BIT'image(s) & " + " & to_string(au) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '0';
au := "00000000";
bu := s + au;
cu := "00000000";
assert (bu = cu) report BIT'image(s) & " + " & to_string(au) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '1';
au := "11111111";
bu := s + au;
cu := "00000000";
assert (bu = cu) report BIT'image(s) & " + " & to_string(au) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '1';
au := "00000001";
bu := au - s;
cu := "00000000";
assert (bu = cu) report to_string(au) & " - " & BIT'image(s) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '1';
au := "11111111";
bu := au - s;
cu := "11111110";
assert (bu = cu) report to_string(au) & " - " & BIT'image(s) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '1';
au := "00000001";
bu := s - au;
cu := "00000000";
assert (bu = cu) report BIT'image(s) & " - " & to_string(au) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
s := '0';
au := "00000001";
bu := s - au;
cu := "11111111";
assert (bu = cu) report BIT'image(s) & " - " & to_string(au) & LF
& to_string (bu) & " /= " & LF & to_string (cu)
severity failure;
-- signed
s := '1';
as := "00000000";
bs := as + s;
cs := "00000001";
assert (bs = cs) report to_string(as) & " + " & BIT'image(s) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '0';
as := "00000000";
bs := as + s;
cs := "00000000";
assert (bs = cs) report to_string(as) & " + " & BIT'image(s) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '1';
as := "10000000";
bs := as + s;
cs := "10000001";
assert (bs = cs) report to_string(as) & " + " & BIT'image(s) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '1';
as := "11111111";
bs := as + s;
cs := "00000000";
assert (bs = cs) report to_string(as) & " + " & BIT'image(s) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '1';
as := "00000000";
bs := s + as;
cs := "00000001";
assert (bs = cs) report BIT'image(s) & " + " & to_string(as) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '1';
as := "00000001";
bs := s + as;
cs := "00000010";
assert (bs = cs) report BIT'image(s) & " + " & to_string(as) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '1';
as := "00000000";
bs := as - s;
cs := "11111111";
assert (bs = cs) report to_string(as) & " - " & BIT'image(s) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '1';
as := "00000001";
bs := as - s;
cs := "00000000";
assert (bs = cs) report to_string(as) & " - " & BIT'image(s) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '1';
as := "00000001";
bs := s - as;
cs := "00000000";
assert (bs = cs) report BIT'image(s) & " - " & to_string(as) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
s := '0';
as := "00000001";
bs := s - as;
cs := "11111111";
assert (bs = cs) report BIT'image(s) & " - " & to_string(as) & LF
& to_string (bs) & " /= " & LF & to_string (cs)
severity failure;
--elsif run("Test new add_carry procedures") then
-- check7uf1 := "0000001"; -- 1
-- check7uf2 := "0000001"; -- 1
-- s := '0';
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "0000010"; -- 2
-- s := '0';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- check7uf1 := "0000001"; -- 1
-- check7uf2 := "0000001"; -- 1
-- s := '1';
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "0000011"; -- 3
-- s := '0';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- check7uf1 := "0000001"; -- 1
-- check7uf2 := "0000110"; -- 6
-- s := '0';
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "0000111"; -- 7
-- s := '0';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- check7uf1 := "0000001"; -- 1
-- check7uf2 := "0000110"; -- 6
-- s := '1'; -- 1
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "0001000"; -- 8
-- s := '0';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- check7uf1 := "1111111"; -- 127
-- check7uf2 := "1111111"; -- 127
-- s := '0';
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "1111110"; -- 126
-- s := '1';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- check7uf1 := "1111111"; -- 127
-- check7uf2 := "1111111"; -- 127
-- s := '1';
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "1111111"; -- 127
-- s := '1';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- check7uf1 := "1111111"; -- 63
-- check7uf2 := "0000000"; -- 0
-- s := '1';
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "0000000"; -- 0
-- s := '1';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- check7uf1 := "1111110"; -- 63
-- check7uf2 := "0000000"; -- 0
-- s := '1';
-- add_carry (L => check7uf1,
-- R => check7uf2,
-- c_in => s,
-- result => check7uf3,
-- c_out => s1);
-- check7uf1 := "1111111"; -- 0
-- s := '0';
-- assert (s1 = s)
-- report "add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("add_carry", check7uf3, check7uf1);
-- -- SIGNED add_carry test
-- check7sf1 := "0000000";
-- check7sf2 := "0000000";
-- s := '0';
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- check7sf1 := "0000000";
-- s := '0';
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "0000010"; -- 2
-- check7sf2 := "0000011"; -- 3
-- s := '0'; -- 0
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '0';
-- check7sf1 := "0000101"; -- 5
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "0000010"; -- 2
-- check7sf2 := "0000011"; -- 3
-- s := '1'; -- 1
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '0';
-- check7sf1 := "0000110"; -- 6
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "0111111"; -- 63
-- check7sf2 := "0000001"; -- 1
-- s := '0'; -- 0
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '1';
-- check7sf1 := "1000000"; -- -128
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "0111111"; -- 63
-- check7sf2 := "0000000"; -- 0
-- s := '1'; -- 1
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '1';
-- check7sf1 := "1000000"; -- -128
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "1111111"; -- -1
-- check7sf2 := "1111111"; -- -1
-- s := '0';
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- check7sf1 := "1111110"; -- -2
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "1111111"; -- -1
-- check7sf2 := "0000001"; -- +1
-- s := '0';
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '0';
-- check7sf1 := "0000000"; -- 0
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "1111111"; -- -1
-- check7sf2 := "0000001"; -- +1
-- s := '1'; -- +1
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '0';
-- check7sf1 := "0000001"; -- 1
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "1000000"; -- -128
-- check7sf2 := "1111111"; -- -1
-- s := '0';
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '1';
-- check7sf1 := "0111111"; -- 63
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
-- check7sf1 := "1000000"; -- -128
-- check7sf2 := "1111111"; -- -1
-- s := '1'; -- +1
-- add_carry (L => check7sf1,
-- R => check7sf2,
-- c_in => s,
-- result => check7sf3,
-- c_out => s1);
-- s := '0';
-- check7sf1 := "1000000"; -- -128
-- assert (s1 = s)
-- report "signed add_carry c_out reported was " & to_string (s1)
-- & " should be " & to_string (s) severity failure;
-- report_error ("signed add_carry", check7sf3, check7sf1);
elsif run("Test sla and srl for unsigned") then
check7uf1 := "0110100"; -- 6.5
check7uf2 := check7uf1 srl 1;
check7uf3 := "0011010"; -- 3.25
report_error ("SRL test", check7uf2, check7uf3);
check7uf2 := check7uf1 srl -1;
check7uf3 := "1101000"; -- 13
report_error ("SRL test -1", check7uf2, check7uf3);
check7uf2 := check7uf1 srl 55;
check7uf3 := "0000000";
report_error ("SRL test 55", check7uf2, check7uf3);
check7uf2 := check7uf1 srl -55;
check7uf3 := "0000000";
report_error ("SRL test -55", check7uf2, check7uf3);
check7uf1 := "0110100"; -- 6.5
check7uf2 := check7uf1 sll -1;
check7uf3 := "0011010"; -- 3.25
report_error ("SLL test", check7uf2, check7uf3);
check7uf2 := check7uf1 sll 1;
check7uf3 := "1101000"; -- 13
report_error ("SLL test -1", check7uf2, check7uf3);
check7uf2 := check7uf1 sll -55;
check7uf3 := "0000000";
report_error ("SLL test 55", check7uf2, check7uf3);
check7uf2 := check7uf1 sll 55;
check7uf3 := "0000000";
report_error ("SLL test -55", check7uf2, check7uf3);
check7uf1 := "0110100"; -- 6.5
check7uf2 := check7uf1 ror 1;
check7uf3 := "0011010"; -- 3.25
report_error ("ror test", check7uf2, check7uf3);
check7uf2 := check7uf1 ror -1;
check7uf3 := "1101000"; -- 13
report_error ("ror test -1", check7uf2, check7uf3);
check7uf2 := check7uf1 ror 55;
check7uf3 := "1101000";
report_error ("ror test 55", check7uf2, check7uf3);
check7uf2 := check7uf1 ror -55;
check7uf3 := "0011010";
report_error ("ror test -55", check7uf2, check7uf3);
check7uf1 := "0110100"; -- 6.5
check7uf2 := check7uf1 rol -1;
check7uf3 := "0011010"; -- 3.25
report_error ("rol test", check7uf2, check7uf3);
check7uf2 := check7uf1 rol 1;
check7uf3 := "1101000"; -- 13
report_error ("rol test -1", check7uf2, check7uf3);
check7uf2 := check7uf1 rol -53;
check7uf3 := "0100011";
report_error ("rol test 53", check7uf2, check7uf3);
check7uf2 := check7uf1 rol 53;
check7uf3 := "1000110";
report_error ("rol test -53", check7uf2, check7uf3);
check7uf1 := "0110100"; -- 6.5
check7uf2 := check7uf1 sra 1;
check7uf3 := "0011010"; -- 3.25
report_error ("SRa test", check7uf2, check7uf3);
check7uf2 := check7uf1 sra -1;
check7uf3 := "1101000"; -- 13
report_error ("SRa test -1", check7uf2, check7uf3);
check7uf2 := check7uf1 sra 55;
check7uf3 := "0000000";
report_error ("SRa test 55", check7uf2, check7uf3);
check7uf2 := check7uf1 sra -55;
check7uf3 := "0000000";
report_error ("SRa test -55", check7uf2, check7uf3);
check7uf1 := "0110100"; -- 6.5
check7uf2 := check7uf1 sla -1;
check7uf3 := "0011010"; -- 3.25
report_error ("SLa test", check7uf2, check7uf3);
check7uf2 := check7uf1 sla 1;
check7uf3 := "1101000"; -- 13
report_error ("SLa test -1", check7uf2, check7uf3);
check7uf2 := check7uf1 sla -55;
check7uf3 := "0000000";
report_error ("SLa test 55", check7uf2, check7uf3);
check7uf2 := check7uf1 sla 55;
check7uf3 := "0000000";
report_error ("SLa test -55", check7uf2, check7uf3);
check7uf1 := "1110100"; -- 14.5
check7uf2 := check7uf1 sra 1;
check7uf3 := "0111010"; -- 16.25
report_error ("SRa test carry", check7uf2, check7uf3);
check7uf1 := "1110100"; -- 14.5
check7uf2 := check7uf1 sra -1;
check7uf3 := "1101000"; -- 13
report_error ("SRa test -carry", check7uf2, check7uf3);
check7uf1 := "0110101"; -- 6.625
check7uf2 := check7uf1 sra 1;
check7uf3 := "0011010";
report_error ("SRa test carry-", check7uf2, check7uf3);
check7uf1 := "0110101"; -- 6.625
check7uf2 := check7uf1 sra -1;
check7uf3 := "1101010";
report_error ("SRa test -carry-", check7uf2, check7uf3);
check7uf1 := "1110100"; -- 14.5
check7uf2 := check7uf1 sla -1;
check7uf3 := "0111010";
report_error ("Sla test -carry", check7uf2, check7uf3);
check7uf1 := "1110100"; -- 14.5
check7uf2 := check7uf1 sla 1;
check7uf3 := "1101000"; -- 13
report_error ("Sla test carry", check7uf2, check7uf3);
check7uf1 := "0110101"; -- 6.625
check7uf2 := check7uf1 sla -1;
check7uf3 := "0011010";
report_error ("Sla test -carry-", check7uf2, check7uf3);
check7uf1 := "0110101"; -- 6.625
check7uf2 := check7uf1 sla 1;
check7uf3 := "1101010";
report_error ("Sla test carry-", check7uf2, check7uf3);
elsif run("Test sla and sra for signed") then
check7sf1 := "0110100"; -- 6.5
check7sf2 := check7sf1 srl 1;
check7sf3 := "0011010"; -- 3.25
report_error ("SRL test", check7sf2, check7sf3);
check7sf2 := check7sf1 srl -1;
check7sf3 := "1101000"; -- 13
report_error ("SRL test -1", check7sf2, check7sf3);
check7sf2 := check7sf1 srl 55;
check7sf3 := "0000000";
report_error ("SRL test 55", check7sf2, check7sf3);
check7sf2 := check7sf1 srl -55;
check7sf3 := "0000000";
report_error ("SRL test -55", check7sf2, check7sf3);
check7sf1 := "0110100"; -- 6.5
check7sf2 := check7sf1 sll -1;
check7sf3 := "0011010"; -- 3.25
report_error ("SLL test", check7sf2, check7sf3);
check7sf2 := check7sf1 sll 1;
check7sf3 := "1101000"; -- 13
report_error ("SLL test -1", check7sf2, check7sf3);
check7sf2 := check7sf1 sll -55;
check7sf3 := "0000000";
report_error ("SLL test 55", check7sf2, check7sf3);
check7sf2 := check7sf1 sll 55;
check7sf3 := "0000000";
report_error ("SLL test -55", check7sf2, check7sf3);
check7sf1 := "0110100"; -- 6.5
check7sf2 := check7sf1 ror 1;
check7sf3 := "0011010"; -- 3.25
report_error ("ror test", check7sf2, check7sf3);
check7sf2 := check7sf1 ror -1;
check7sf3 := "1101000"; -- 13
report_error ("ror test -1", check7sf2, check7sf3);
check7sf2 := check7sf1 ror 55;
check7sf3 := "1101000";
report_error ("ror test 55", check7sf2, check7sf3);
check7sf2 := check7sf1 ror -55;
check7sf3 := "0011010";
report_error ("ror test -55", check7sf2, check7sf3);
check7sf1 := "0110100"; -- 6.5
check7sf2 := check7sf1 rol -1;
check7sf3 := "0011010"; -- 3.25
report_error ("rol test", check7sf2, check7sf3);
check7sf2 := check7sf1 rol 1;
check7sf3 := "1101000"; -- 13
report_error ("rol test -1", check7sf2, check7sf3);
check7sf2 := check7sf1 rol -53;
check7sf3 := "0100011";
report_error ("rol test 53", check7sf2, check7sf3);
check7sf2 := check7sf1 rol 53;
check7sf3 := "1000110";
report_error ("rol test -53", check7sf2, check7sf3);
check7sf1 := "0110100"; -- 6.5
check7sf2 := check7sf1 sra 1;
check7sf3 := "0011010"; -- 3.25
report_error ("SRa test", check7sf2, check7sf3);
check7sf2 := check7sf1 sra -1;
check7sf3 := "1101000"; -- 13
report_error ("SRa test -1", check7sf2, check7sf3);
check7sf2 := check7sf1 sra 55;
check7sf3 := "0000000";
report_error ("SRa test 55", check7sf2, check7sf3);
check7sf2 := check7sf1 sra -55;
check7sf3 := "0000000";
report_error ("SRa test -55", check7sf2, check7sf3);
check7sf1 := "0110100"; -- 6.5
check7sf2 := check7sf1 sla -1;
check7sf3 := "0011010"; -- 3.25
report_error ("SLa test", check7sf2, check7sf3);
check7sf2 := check7sf1 sla 1;
check7sf3 := "1101000"; -- 13
report_error ("SLa test -1", check7sf2, check7sf3);
check7sf2 := check7sf1 sla -55;
check7sf3 := "0000000";
report_error ("SLa test 55", check7sf2, check7sf3);
check7sf2 := check7sf1 sla 55;
check7sf3 := "0000000";
report_error ("SLa test -55", check7sf2, check7sf3);
check7sf1 := "1110100"; -- 14.5
check7sf2 := check7sf1 sra 1;
check7sf3 := "1111010"; -- 16.25
report_error ("SRa test carry", check7sf2, check7sf3);
check7sf1 := "1110100"; -- 14.5
check7sf2 := check7sf1 sra -1;
check7sf3 := "1101000"; -- 13
report_error ("SRa test -carry", check7sf2, check7sf3);
check7sf1 := "0110101"; -- 6.625
check7sf2 := check7sf1 sra 1;
check7sf3 := "0011010";
report_error ("SRa test carry-", check7sf2, check7sf3);
check7sf1 := "0110101"; -- 6.625
check7sf2 := check7sf1 sra -1;
check7sf3 := "1101010";
report_error ("SRa test -carry-", check7sf2, check7sf3);
check7sf1 := "1110100"; -- 14.5
check7sf2 := check7sf1 sla -1;
check7sf3 := "1111010";
report_error ("Sla test -carry", check7sf2, check7sf3);
check7sf1 := "1110100"; -- 14.5
check7sf2 := check7sf1 sla 1;
check7sf3 := "1101000"; -- 13
report_error ("Sla test carry", check7sf2, check7sf3);
check7sf1 := "0110101"; -- 6.625
check7sf2 := check7sf1 sla -1;
check7sf3 := "0011010";
report_error ("Sla test -carry-", check7sf2, check7sf3);
check7sf1 := "0110101"; -- 6.625
check7sf2 := check7sf1 sla 1;
check7sf3 := "1101010";
report_error ("Sla test carry-", check7sf2, check7sf3);
--elsif run("Test of new conversion functions") then
-- check7sf1 := "0000001";
-- check7uf1 := remove_sign (check7sf1);
-- assert (check7uf1 = UNSIGNED(check7sf1))
-- report "remove_sign (""" & to_string(check7sf1) & """ /= """
-- & to_string(check7uf1) & """)"
-- severity failure;
-- check7sf1 := "1111111";
-- check7uf1 := remove_sign (check7sf1);
-- assert (check7uf1 = 1)
-- report "remove_sign (""" & to_string(check7sf1) & """ /= """
-- & to_string(check7uf1) & """)"
-- severity failure;
-- check7sf1 := "1000000";
-- check7uf1 := remove_sign (check7sf1);
-- assert (check7uf1 = 64)
-- report "remove_sign (""" & to_string(check7sf1) & """ /= """
-- & to_string(check7uf1) & """)"
-- severity failure;
-- check7uf1 := "0000001";
-- as := add_sign (check7uf1);
-- assert (as = SIGNED ("0" & check7uf1))
-- report "add_sign (""" & to_string (check7uf1) & """ /= """
-- & to_string (as) & """)"
-- severity failure;
-- check7uf1 := "1111111";
-- as := add_sign (check7uf1);
-- assert (as = SIGNED ("0" & check7uf1))
-- report "add_sign (""" & to_string (check7uf1) & """ /= """
-- & to_string (as) & """)"
-- severity failure;
elsif run("Test edge functionality") then
start_edgetest <= true;
wait until edgetest_done;
elsif run("Boolean test") then
start_booleantest <= true;
wait until booleantest_done;
elsif run("Test the size_res functions") then
start_sizerestest <= true;
wait until sizerestest_done;
elsif run("Test the match function") then
start_matchtest <= true;
wait until matchtest_done;
end if;
end loop;
test_runner_cleanup(runner);
wait;
end process testblock;
verify : process is
subtype bv4 is BIT_VECTOR(0 to 3);
variable a_bv : bv4;
variable a_suv : UNSIGNED(0 to 3);
variable a_slv : SIGNED(0 to 3);
variable b_su : BIT;
variable b_bv : bv4;
begin
wait until start_booleantest;
for a_val in 0 to 15 loop
a_bv := BIT_VECTOR(to_unsigned(a_val, 4));
a_suv := UNSIGNED(a_bv);
a_slv := SIGNED(a_bv);
for b in BIT loop
b_su := b;
b_bv := bv4'(others => b);
assert BIT_VECTOR(a_suv and b_su) = BIT_VECTOR'(a_bv and b_bv)
report "error in a_suv and b_su" severity failure;
assert BIT_VECTOR(a_slv and b_su) = BIT_VECTOR'(a_bv and b_bv)
report "error in a_slv and b_su" severity failure;
assert BIT_VECTOR(b_su and a_suv) = BIT_VECTOR'(b_bv and a_bv)
report "error in b_su and a_suv" severity failure;
assert BIT_VECTOR(b_su and a_slv) = BIT_VECTOR'(b_bv and a_bv)
report "error in b_su and a_slv" severity failure;
assert BIT_VECTOR(a_suv nand b_su) = BIT_VECTOR'(a_bv nand b_bv)
report "error in a_suv nand b_su" severity failure;
assert BIT_VECTOR(a_slv nand b_su) = BIT_VECTOR'(a_bv nand b_bv)
report "error in a_slv nand b_su" severity failure;
assert BIT_VECTOR(b_su nand a_suv) = BIT_VECTOR'(b_bv nand a_bv)
report "error in b_su nand a_suv" severity failure;
assert BIT_VECTOR(b_su nand a_slv) = BIT_VECTOR'(b_bv nand a_bv)
report "error in b_su nand a_slv" severity failure;
assert BIT_VECTOR(a_suv or b_su) = BIT_VECTOR'(a_bv or b_bv)
report "error in a_suv or b_su" severity failure;
assert BIT_VECTOR(a_slv or b_su) = BIT_VECTOR'(a_bv or b_bv)
report "error in a_slv or b_su" severity failure;
assert BIT_VECTOR(b_su or a_suv) = BIT_VECTOR'(b_bv or a_bv)
report "error in b_su or a_suv" severity failure;
assert BIT_VECTOR(b_su or a_slv) = BIT_VECTOR'(b_bv or a_bv)
report "error in b_su or a_slv" severity failure;
assert BIT_VECTOR(a_suv nor b_su) = BIT_VECTOR'(a_bv nor b_bv)
report "error in a_suv nor b_su" severity failure;
assert BIT_VECTOR(a_slv nor b_su) = BIT_VECTOR'(a_bv nor b_bv)
report "error in a_slv nor b_su" severity failure;
assert BIT_VECTOR(b_su nor a_suv) = BIT_VECTOR'(b_bv nor a_bv)
report "error in b_su nor a_suv" severity failure;
assert BIT_VECTOR(b_su nor a_slv) = BIT_VECTOR'(b_bv nor a_bv)
report "error in b_su nor a_slv" severity failure;
assert BIT_VECTOR(a_suv xor b_su) = BIT_VECTOR'(a_bv xor b_bv)
report "error in a_suv xor b_su" severity failure;
assert BIT_VECTOR(a_slv xor b_su) = BIT_VECTOR'(a_bv xor b_bv)
report "error in a_slv xor b_su" severity failure;
assert BIT_VECTOR(b_su xor a_suv) = BIT_VECTOR'(b_bv xor a_bv)
report "error in b_su xor a_suv" severity failure;
assert BIT_VECTOR(b_su xor a_slv) = BIT_VECTOR'(b_bv xor a_bv)
report "error in b_su xor a_slv" severity failure;
assert BIT_VECTOR(a_suv xnor b_su) = BIT_VECTOR'(a_bv xnor b_bv)
report "error in a_suv xnor b_su" severity failure;
assert BIT_VECTOR(a_slv xnor b_su) = BIT_VECTOR'(a_bv xnor b_bv)
report "error in a_slv xnor b_su" severity failure;
assert BIT_VECTOR(b_su xnor a_suv) = BIT_VECTOR'(b_bv xnor a_bv)
report "error in b_su xnor a_suv" severity failure;
assert BIT_VECTOR(b_su xnor a_slv) = BIT_VECTOR'(b_bv xnor a_bv)
report "error in b_su xnor a_slv" severity failure;
wait for 1 ns;
end loop;
end loop;
booleantest_done <= true;
wait;
end process verify;
-- purpose: test the match function
-- type : combinational
-- inputs :
-- outputs:
matchtest : process is
variable aslv, bslv : BIT_VECTOR (7 downto 0); -- slvs
variable asulv, bsulv : BIT_VECTOR (7 downto 0); -- sulvs
variable s, s1, s2 : BIT;
variable auns, buns : UNSIGNED (7 downto 0);
variable as, bs : SIGNED (7 downto 0);
variable check6, check6t : UNSIGNED (6 downto 0);
variable checks6, checks6t : SIGNED (6 downto 0);
variable b : BOOLEAN;
begin
wait until start_matchtest;
-- ?=
-- unsigned
auns := "00000010";
buns := "00000010";
s := auns ?= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?= buns;
assert s = '0'
report "uns " & to_string(auns) & " ?= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?= buns;
assert s = '0'
report "uns " & to_string(auns) & " ?= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000010";
s := auns ?= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?= " & to_string(buns)
& " = " & to_string (s)
severity failure;
-- signed
as := "00000010";
bs := "00000010";
s := as ?= bs;
assert s = '1'
report "s " & to_string(as) & " ?= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?= bs;
assert s = '0'
report "s " & to_string(as) & " ?= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?= bs;
assert s = '0'
report "s " & to_string(as) & " ?= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000010";
s := as ?= bs;
assert s = '1'
report "s " & to_string(as) & " ?= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000010";
bs := "11000010";
s := checks6 ?= bs;
assert s = '1'
report "s " & to_string(checks6) & " ?= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000011";
bs := "11000010";
s := checks6 ?= bs;
assert s = '0'
report "s " & to_string(checks6) & " ?= " & to_string(bs)
& " = " & to_string (s)
severity failure;
-- unsigned
auns := "00000010";
buns := "00000010";
s := auns ?/= buns;
assert s = '0'
report "uns " & to_string(auns) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?/= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?/= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000010";
s := auns ?/= buns;
assert s = '0'
report "uns " & to_string(auns) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
check6 := "1000010";
buns := "11000010";
s := check6 ?/= buns;
assert s = '1'
report "uns a " & to_string(check6) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
check6 := "1000011";
buns := "11000010";
s := check6 ?/= buns;
assert s = '1'
report "uns b " & to_string(check6) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
check6 := "1000010";
buns := "01000010";
s := check6 ?/= buns;
assert s = '0'
report "uns c " & to_string(check6) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
check6 := "0000011";
buns := "00000011";
s := check6 ?/= buns;
assert s = '0'
report "uns d " & to_string(check6) & " ?/= " & to_string(buns)
& " = " & to_string (s)
severity failure;
-- ?<
auns := "00000010";
buns := "00000010";
s := auns ?< buns;
assert s = '0'
report "uns " & to_string(auns) & " ?< " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?< buns;
assert s = '1'
report "uns " & to_string(auns) & " ?< " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?< buns;
assert s = '1'
report "uns " & to_string(auns) & " ?< " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000010";
s := auns ?< buns;
assert s = '0'
report "uns " & to_string(auns) & " ?< " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "10000010";
buns := "00000010";
s := auns ?< buns;
assert s = '0'
report "uns " & to_string(auns) & " ?< " & to_string(buns)
& " = " & to_string (s)
severity failure;
-- ?<=
auns := "00000010";
buns := "00000010";
s := auns ?<= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?<= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?<= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?<= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?<= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?<= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "10000011";
buns := "00000011";
s := auns ?<= buns;
assert s = '0'
report "uns " & to_string(auns) & " ?<= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000010";
s := auns ?<= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?<= " & to_string(buns)
& " = " & to_string (s)
severity failure;
-- ?>
auns := "00000010";
buns := "00000010";
s := auns ?> buns;
assert s = '0'
report "uns " & to_string(auns) & " ?> " & to_string(buns)
& " = " & to_string (s)
severity failure;
buns := "00000010";
auns := "00000011";
s := auns ?> buns;
assert s = '1'
report "uns " & to_string(auns) & " ?> " & to_string(buns)
& " = " & to_string (s)
severity failure;
buns := "00000010";
auns := "00000011";
s := auns ?> buns;
assert s = '1'
report "uns " & to_string(auns) & " ?> " & to_string(buns)
& " = " & to_string (s)
severity failure;
buns := "10000010";
auns := "00000011";
s := auns ?> buns;
assert s = '0'
report "uns " & to_string(auns) & " ?> " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000010";
s := auns ?> buns;
assert s = '0'
report "uns " & to_string(auns) & " ?> " & to_string(buns)
& " = " & to_string (s)
severity failure;
-- ?>=
auns := "00000010";
buns := "00000010";
s := auns ?>= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?>= " & to_string(buns)
& " = " & to_string (s)
severity failure;
buns := "00000010";
auns := "00000011";
s := auns ?>= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?>= " & to_string(buns)
& " = " & to_string (s)
severity failure;
buns := "00000010";
auns := "00000011";
s := auns ?>= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?>= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000011";
s := auns ?>= buns;
assert s = '0'
report "uns " & to_string(auns) & " ?>= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "10000010";
buns := "00000011";
s := auns ?>= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?>= " & to_string(buns)
& " = " & to_string (s)
severity failure;
auns := "00000010";
buns := "00000010";
s := auns ?>= buns;
assert s = '1'
report "uns " & to_string(auns) & " ?>= " & to_string(buns)
& " = " & to_string (s)
severity failure;
check6 := "1000010";
buns := "01000010";
s := check6 ?= buns;
assert s = '1'
report "s " & to_string(check6) & " ?= " & to_string(buns)
& " = " & to_string (s)
severity failure;
check6 := "1000010";
buns := "11000010";
s := check6 ?= buns;
assert s = '0'
report "s " & to_string(check6) & " ?= " & to_string(buns)
& " = " & to_string (s)
severity failure;
check6 := "0000010";
buns := "00000010";
s := check6 ?= buns;
assert s = '1'
report "s " & to_string(check6) & " ?= " & to_string(buns)
& " = " & to_string (s)
severity failure;
-- signed
as := "00000010";
bs := "00000010";
s := as ?/= bs;
assert s = '0'
report "s " & to_string(as) & " ?/= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?/= bs;
assert s = '1'
report "s " & to_string(as) & " ?/= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?/= bs;
assert s = '1'
report "s " & to_string(as) & " ?/= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000010";
s := as ?/= bs;
assert s = '0'
report "s " & to_string(as) & " ?/= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000010";
bs := "11000010";
s := checks6 ?/= bs;
assert s = '0'
report "s one " & to_string(checks6) & " ?/= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000011";
bs := "11000010";
s := checks6 ?/= bs;
assert s = '1'
report "s two " & to_string(checks6) & " ?/= " & to_string(bs)
& " = " & to_string (s)
severity failure;
-- ?<
as := "00000010";
bs := "00000010";
s := as ?< bs;
assert s = '0'
report "s " & to_string(as) & " ?< " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?< bs;
assert s = '1'
report "s " & to_string(as) & " ?< " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?< bs;
assert s = '1'
report "s " & to_string(as) & " ?< " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000010";
s := as ?< bs;
assert s = '0'
report "s " & to_string(as) & " ?< " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "10000010";
bs := "00000010";
s := as ?< bs;
assert s = '1'
report "s " & to_string(as) & " ?< " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000010";
bs := "11000011";
s := checks6 ?< bs;
assert s = '1'
report "s " & to_string(checks6) & " ?< " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000011";
bs := "11000010";
s := checks6 ?< bs;
assert s = '0'
report "s " & to_string(checks6) & " ?< " & to_string(bs)
& " = " & to_string (s)
severity failure;
-- ?<=
as := "00000010";
bs := "00000010";
s := as ?<= bs;
assert s = '1'
report "s " & to_string(as) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?<= bs;
assert s = '1'
report "s " & to_string(as) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?<= bs;
assert s = '1'
report "s " & to_string(as) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "10000011";
bs := "00000011";
s := as ?<= bs;
assert s = '1'
report "s " & to_string(as) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000010";
bs := "11000011";
s := checks6 ?<= bs;
assert s = '1'
report "s " & to_string(checks6) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000011";
bs := "11000010";
s := checks6 ?<= bs;
assert s = '0'
report "s " & to_string(checks6) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000011";
bs := "11000011";
s := checks6 ?<= bs;
assert s = '1'
report "s " & to_string(checks6) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000010";
s := as ?<= bs;
assert s = '1'
report "s " & to_string(as) & " ?<= " & to_string(bs)
& " = " & to_string (s)
severity failure;
-- ?>
as := "00000010";
bs := "00000010";
s := as ?> bs;
assert s = '0'
report "s " & to_string(as) & " ?> " & to_string(bs)
& " = " & to_string (s)
severity failure;
bs := "00000010";
as := "00000011";
s := as ?> bs;
assert s = '1'
report "s " & to_string(as) & " ?> " & to_string(bs)
& " = " & to_string (s)
severity failure;
bs := "00000010";
as := "00000011";
s := as ?> bs;
assert s = '1'
report "s " & to_string(as) & " ?> " & to_string(bs)
& " = " & to_string (s)
severity failure;
bs := "10000010";
as := "00000011";
s := as ?> bs;
assert s = '1'
report "s " & to_string(as) & " ?> " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000011";
bs := "11000010";
s := checks6 ?> bs;
assert s = '1'
report "s " & to_string(checks6) & " ?> " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000010";
bs := "11000011";
s := checks6 ?> bs;
assert s = '0'
report "s " & to_string(checks6) & " ?> " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000010";
s := as ?> bs;
assert s = '0'
report "s " & to_string(as) & " ?> " & to_string(bs)
& " = " & to_string (s)
severity failure;
-- ?>=
as := "00000010";
bs := "00000010";
s := as ?>= bs;
assert s = '1'
report "s " & to_string(as) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
bs := "00000010";
as := "00000011";
s := as ?>= bs;
assert s = '1'
report "s " & to_string(as) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
bs := "00000010";
as := "00000011";
s := as ?>= bs;
assert s = '1'
report "s " & to_string(as) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000011";
s := as ?>= bs;
assert s = '0'
report "s " & to_string(as) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "10000010";
bs := "00000011";
s := as ?>= bs;
assert s = '0'
report "s " & to_string(as) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000010";
bs := "11000010";
s := checks6 ?>= bs;
assert s = '1'
report "s " & to_string(checks6) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1111011"; -- -5
bs := "11111010"; -- -6
s := checks6 ?>= bs;
assert s = '1'
report "s " & to_string(checks6) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
checks6 := "1000010";
bs := "11000011";
s := checks6 ?>= bs;
assert s = '0'
report "s " & to_string(checks6) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
as := "00000010";
bs := "00000010";
s := as ?>= bs;
assert s = '1'
report "s " & to_string(as) & " ?>= " & to_string(bs)
& " = " & to_string (s)
severity failure;
matchtest_done <= true;
wait;
end process matchtest;
-- purpose: test the size_res functions
-- type : combinational
-- inputs :
-- outputs:
sizerestest : process is
variable checkint : INTEGER;
variable check6, check6t : UNSIGNED (5 downto 0);
variable check5, check5t : UNSIGNED (4 downto 0);
variable checks6, checks6t : SIGNED (5 downto 0);
variable checks5, checks5t : SIGNED (4 downto 0);
variable nulls : SIGNED (0 downto 1);
variable nullu : UNSIGNED (0 downto 1); -- null arrays
begin
wait until start_sizerestest;
check6 := "000111"; -- 7
check5 := resize (check6, check5);
check5t := "00111"; -- 7
report_error ("resize size_res", check5, check5t);
check5 := "01000"; -- 8
check6 := resize (check5, check6);
check6t := "001000"; -- 8
report_error ("resize size_res", check6, check6t);
nullu := resize (check5, nullu);
check5 := resize (nullu, check5);
check5t := (others => '0');
report_error ("resize (null, check5)", check5, check5t);
checkint := 4;
check5 := to_unsigned(checkint, check5);
check5t := "00100"; -- 4
report_error ("to_unsigned(4, size_res)", check5, check5t);
nullu := to_unsigned (checkint, nullu);
-- signed
checks6 := "000111"; -- 7
checks5 := resize (checks6, checks5);
checks5t := "00111"; -- 7
report_error ("resize s size_res", checks5, checks5t);
checks5 := "01000"; -- 8
checks6 := resize (checks5, checks6);
checks6t := "001000"; -- 8
report_error ("resize s size_res", checks6, checks6t);
nulls := resize (checks5, nulls);
checks5 := resize (nulls, checks5);
checks5t := (others => '0');
report_error ("resize (null, checks5)", checks5, checks5t);
checkint := 4;
checks5 := to_signed(checkint, checks5);
checks5t := "00100"; -- 4
report_error ("to_signed(4, size_res)", checks5, checks5t);
nulls := to_signed (checkint, nulls);
sizerestest_done <= true;
wait;
end process sizerestest;
-- purpose: clock driver
-- type : combinational
-- inputs :
-- outputs:
clkprc : process is
constant clock_period : TIME := 4 ns;
begin -- process clkprc
if (not edgetest_done) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- Copy of the test in "test_standard_additions". To test the edge
-- functionality now that the "rising_edge" and "falling_edge" function have
-- been moved into "standard".
-- purpose: test the edge functions
edgetest : process is
begin
wait until start_edgetest;
wait for 1 ns;
assert (not rising_edge(clk)) report "False rising_edge detection"
severity failure;
wait until rising_edge (clk);
assert (now = 2 ns) report "Rising edge of clock not in sync"
severity failure;
wait for 1 ns;
assert (not falling_edge(clk)) report "False falling_edge detection"
severity failure;
wait until falling_edge (clk);
assert (now = 4 ns) report "Falling edge of clock not in sync"
severity failure;
wait for 1 ns;
assert (not falling_edge(clk)) report "False falling_edge detection"
severity failure;
wait until rising_edge (clk);
assert (now = 6 ns) report "2 Rising edge of clock not in sync"
severity failure;
wait for 1 ns;
assert (not rising_edge(clk)) report "False rising_edge detection"
severity failure;
wait until falling_edge (clk);
assert (now = 8 ns) report "2 Falling edge of clock not in sync"
severity failure;
wait until rising_edge (clk);
assert (now = 10 ns) report "3 Rising edge of clock not in sync"
severity failure;
wait until falling_edge (clk);
assert (now = 12 ns) report "4 Falling edge of clock not in sync"
severity failure;
edgetest_done <= true;
end process edgetest;
end architecture testbench;
|
--
-- Copyright (c) 2018 Allmine Inc
--
library work;
use work.bk_globals.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blake is
port( clk : in std_logic;
chn_in : in std_logic_vector(511 downto 0);
msg_in : in std_logic_vector(1023 downto 0);
slt_in : in std_logic_vector(255 downto 0);
cnt_in : in std_logic_vector(127 downto 0);
dout : out std_logic_vector(511 downto 0)
);
end blake;
architecture rtl of blake is
--components
component bk_round
port ( clk : in std_logic;
state : in std_logic_vector(1023 downto 0);
msg : in std_logic_vector(1023 downto 0);
chain : out std_logic_vector(1023 downto 0)
);
end component;
component bk_reg
port ( clk : in std_logic;
st_in : in std_logic_vector(1023 downto 0);
st_out : out std_logic_vector(1023 downto 0)
);
end component;
component bk_hreg
port ( clk : in std_logic;
st_in : in std_logic_vector(511 downto 0);
st_out : out std_logic_vector(511 downto 0)
);
end component;
component bk_sigma
port ( clk : in std_logic;
round_w : in std_logic_vector(3 downto 0);
msg: in std_logic_vector(1023 downto 0);
sigma: out std_logic_vector(1023 downto 0)
);
end component;
----------------------------------------------------------------------------
-- Internal signal declarations
----------------------------------------------------------------------------
signal rii_st, rii_msg : std_logic_vector(1023 downto 0);
signal r00_st, r00_msg : std_logic_vector(1023 downto 0);
signal r00_sin, r00_sout, r00_min, r00_mout : std_logic_vector(1023 downto 0);
signal r01_sin, r01_sout, r01_min, r01_mout : std_logic_vector(1023 downto 0);
signal r02_sin, r02_sout, r02_min, r02_mout : std_logic_vector(1023 downto 0);
signal r03_sin, r03_sout, r03_min, r03_mout : std_logic_vector(1023 downto 0);
signal r04_sin, r04_sout, r04_min, r04_mout : std_logic_vector(1023 downto 0);
signal r05_sin, r05_sout, r05_min, r05_mout : std_logic_vector(1023 downto 0);
signal r06_sin, r06_sout, r06_min, r06_mout : std_logic_vector(1023 downto 0);
signal r07_sin, r07_sout, r07_min, r07_mout : std_logic_vector(1023 downto 0);
signal r08_sin, r08_sout, r08_min, r08_mout : std_logic_vector(1023 downto 0);
signal r09_sin, r09_sout, r09_min, r09_mout : std_logic_vector(1023 downto 0);
signal r10_sin, r10_sout, r10_min, r10_mout : std_logic_vector(1023 downto 0);
signal r11_sin, r11_sout, r11_min, r11_mout : std_logic_vector(1023 downto 0);
signal r12_sin, r12_sout, r12_min, r12_mout : std_logic_vector(1023 downto 0);
signal r13_sin, r13_sout, r13_min, r13_mout : std_logic_vector(1023 downto 0);
signal r14_sin, r14_sout, r14_min, r14_mout : std_logic_vector(1023 downto 0);
signal r15_sin, r15_sout, r15_min, r15_mout : std_logic_vector(1023 downto 0);
signal rii_chain, roo_chain, roo_hout : std_logic_vector(511 downto 0);
signal r00a_hout, r00b_hout : std_logic_vector(511 downto 0);
signal r01a_hout, r01b_hout : std_logic_vector(511 downto 0);
signal r02a_hout, r02b_hout : std_logic_vector(511 downto 0);
signal r03a_hout, r03b_hout : std_logic_vector(511 downto 0);
signal r04a_hout, r04b_hout : std_logic_vector(511 downto 0);
signal r05a_hout, r05b_hout : std_logic_vector(511 downto 0);
signal r06a_hout, r06b_hout : std_logic_vector(511 downto 0);
signal r07a_hout, r07b_hout : std_logic_vector(511 downto 0);
signal r08a_hout, r08b_hout : std_logic_vector(511 downto 0);
signal r09a_hout, r09b_hout : std_logic_vector(511 downto 0);
signal r10a_hout, r10b_hout : std_logic_vector(511 downto 0);
signal r11a_hout, r11b_hout : std_logic_vector(511 downto 0);
signal r12a_hout, r12b_hout : std_logic_vector(511 downto 0);
signal r13a_hout, r13b_hout : std_logic_vector(511 downto 0);
signal r14a_hout, r14b_hout : std_logic_vector(511 downto 0);
signal r15a_hout, r15b_hout : std_logic_vector(511 downto 0);
signal cnt_i : std_logic_vector(255 downto 0);
begin -- Rtl
-- State initialization
cnt_i <= cnt_in(63 downto 0) & cnt_in(63 downto 0) & cnt_in(127 downto 64) & cnt_in(127 downto 64);
rii_st(1023 downto 512) <= chn_in;
rii_st(511 downto 256) <= slt_in xor const_t(1023 downto 768);
rii_st(255 downto 0) <= cnt_i xor const_t(767 downto 512);
mrii_map : bk_reg port map(clk, rii_st, r00_st);
rii_msg <= msg_in xor const_r;
mmii_map : bk_reg port map(clk, rii_msg, r00_msg);
mc00_map : bk_round port map(clk, r00_st, r00_msg, r00_sin);
mr00_map : bk_reg port map(clk, r00_sin, r00_sout);
ms00_map : bk_sigma port map(clk, "0000", r00_msg, r00_min);
mm00_map : bk_reg port map(clk, r00_min, r00_mout);
mc01_map : bk_round port map(clk, r00_sout, r00_mout, r01_sin);
mr01_map : bk_reg port map(clk, r01_sin, r01_sout);
ms01_map : bk_sigma port map(clk, "0001", r00_mout, r01_min);
mm01_map : bk_reg port map(clk, r01_min, r01_mout);
mc02_map : bk_round port map(clk, r01_sout, r01_mout, r02_sin);
mr02_map : bk_reg port map(clk, r02_sin, r02_sout);
ms02_map : bk_sigma port map(clk, "0010", r01_mout, r02_min);
mm02_map : bk_reg port map(clk, r02_min, r02_mout);
mc03_map : bk_round port map(clk, r02_sout, r02_mout, r03_sin);
mr03_map : bk_reg port map(clk, r03_sin, r03_sout);
ms03_map : bk_sigma port map(clk, "0011", r02_mout, r03_min);
mm03_map : bk_reg port map(clk, r03_min, r03_mout);
mc04_map : bk_round port map(clk, r03_sout, r03_mout, r04_sin);
mr04_map : bk_reg port map(clk, r04_sin, r04_sout);
ms04_map : bk_sigma port map(clk, "0100", r03_mout, r04_min);
mm04_map : bk_reg port map(clk, r04_min, r04_mout);
mc05_map : bk_round port map(clk, r04_sout, r04_mout, r05_sin);
mr05_map : bk_reg port map(clk, r05_sin, r05_sout);
ms05_map : bk_sigma port map(clk, "0101", r04_mout, r05_min);
mm05_map : bk_reg port map(clk, r05_min, r05_mout);
mc06_map : bk_round port map(clk, r05_sout, r05_mout, r06_sin);
mr06_map : bk_reg port map(clk, r06_sin, r06_sout);
ms06_map : bk_sigma port map(clk, "0110", r05_mout, r06_min);
mm06_map : bk_reg port map(clk, r06_min, r06_mout);
mc07_map : bk_round port map(clk, r06_sout, r06_mout, r07_sin);
mr07_map : bk_reg port map(clk, r07_sin, r07_sout);
ms07_map : bk_sigma port map(clk, "0111", r06_mout, r07_min);
mm07_map : bk_reg port map(clk, r07_min, r07_mout);
mc08_map : bk_round port map(clk, r07_sout, r07_mout, r08_sin);
mr08_map : bk_reg port map(clk, r08_sin, r08_sout);
ms08_map : bk_sigma port map(clk, "1000", r07_mout, r08_min);
mm08_map : bk_reg port map(clk, r08_min, r08_mout);
mc09_map : bk_round port map(clk, r08_sout, r08_mout, r09_sin);
mr09_map : bk_reg port map(clk, r09_sin, r09_sout);
ms09_map : bk_sigma port map(clk, "1001", r08_mout, r09_min);
mm09_map : bk_reg port map(clk, r09_min, r09_mout);
mc10_map : bk_round port map(clk, r09_sout, r09_mout, r10_sin);
mr10_map : bk_reg port map(clk, r10_sin, r10_sout);
ms10_map : bk_sigma port map(clk, "0000", r09_mout, r10_min);
mm10_map : bk_reg port map(clk, r10_min, r10_mout);
mc11_map : bk_round port map(clk, r10_sout, r10_mout, r11_sin);
mr11_map : bk_reg port map(clk, r11_sin, r11_sout);
ms11_map : bk_sigma port map(clk, "0001", r10_mout, r11_min);
mm11_map : bk_reg port map(clk, r11_min, r11_mout);
mc12_map : bk_round port map(clk, r11_sout, r11_mout, r12_sin);
mr12_map : bk_reg port map(clk, r12_sin, r12_sout);
ms12_map : bk_sigma port map(clk, "0010", r11_mout, r12_min);
mm12_map : bk_reg port map(clk, r12_min, r12_mout);
mc13_map : bk_round port map(clk, r12_sout, r12_mout, r13_sin);
mr13_map : bk_reg port map(clk, r13_sin, r13_sout);
ms13_map : bk_sigma port map(clk, "0011", r12_mout, r13_min);
mm13_map : bk_reg port map(clk, r13_min, r13_mout);
mc14_map : bk_round port map(clk, r13_sout, r13_mout, r14_sin);
mr14_map : bk_reg port map(clk, r14_sin, r14_sout);
ms14_map : bk_sigma port map(clk, "0100", r13_mout, r14_min);
mm14_map : bk_reg port map(clk, r14_min, r14_mout);
mc15_map : bk_round port map(clk, r14_sout, r14_mout, r15_sin);
mr15_map : bk_reg port map(clk, r15_sin, r15_sout);
-- ms15_map : bk_sigma port map("0101", r14_mout, r15_min);
-- mm15_map : bk_reg port map(clk, r15_min, r15_mout);
mhii_map : bk_hreg port map(clk, chn_in, rii_chain);
mh00a_map : bk_hreg port map(clk, rii_chain, r00a_hout);
mh00b_map : bk_hreg port map(clk, r00a_hout, r00b_hout);
mh01a_map : bk_hreg port map(clk, r00b_hout, r01a_hout);
mh01b_map : bk_hreg port map(clk, r01a_hout, r01b_hout);
mh02a_map : bk_hreg port map(clk, r01b_hout, r02a_hout);
mh02b_map : bk_hreg port map(clk, r02a_hout, r02b_hout);
mh03a_map : bk_hreg port map(clk, r02b_hout, r03a_hout);
mh03b_map : bk_hreg port map(clk, r03a_hout, r03b_hout);
mh04a_map : bk_hreg port map(clk, r03b_hout, r04a_hout);
mh04b_map : bk_hreg port map(clk, r04a_hout, r04b_hout);
mh05a_map : bk_hreg port map(clk, r04b_hout, r05a_hout);
mh05b_map : bk_hreg port map(clk, r05a_hout, r05b_hout);
mh06a_map : bk_hreg port map(clk, r05b_hout, r06a_hout);
mh06b_map : bk_hreg port map(clk, r06a_hout, r06b_hout);
mh07a_map : bk_hreg port map(clk, r06b_hout, r07a_hout);
mh07b_map : bk_hreg port map(clk, r07a_hout, r07b_hout);
mh08a_map : bk_hreg port map(clk, r07b_hout, r08a_hout);
mh08b_map : bk_hreg port map(clk, r08a_hout, r08b_hout);
mh09a_map : bk_hreg port map(clk, r08b_hout, r09a_hout);
mh09b_map : bk_hreg port map(clk, r09a_hout, r09b_hout);
mh10a_map : bk_hreg port map(clk, r09b_hout, r10a_hout);
mh10b_map : bk_hreg port map(clk, r10a_hout, r10b_hout);
mh11a_map : bk_hreg port map(clk, r10b_hout, r11a_hout);
mh11b_map : bk_hreg port map(clk, r11a_hout, r11b_hout);
mh12a_map : bk_hreg port map(clk, r11b_hout, r12a_hout);
mh12b_map : bk_hreg port map(clk, r12a_hout, r12b_hout);
mh13a_map : bk_hreg port map(clk, r12b_hout, r13a_hout);
mh13b_map : bk_hreg port map(clk, r13a_hout, r13b_hout);
mh14a_map : bk_hreg port map(clk, r13b_hout, r14a_hout);
mh14b_map : bk_hreg port map(clk, r14a_hout, r14b_hout);
mh15a_map : bk_hreg port map(clk, r14b_hout, r15a_hout);
mh15b_map : bk_hreg port map(clk, r15a_hout, r15b_hout);
roo_chain <= r15b_hout xor r15_sout(1023 downto 512) xor r15_sout(511 downto 0);
mhoo_map : bk_hreg port map(clk, roo_chain, roo_hout);
dout <= roo_hout;
end rtl;
|
--------------------------------------------------------------------------------
-- Title : Receiver FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_rx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the receiver side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is built around an Inferred Dual Port RAM,
-- giving a total memory capacity of 4096 bytes.
--
-- Frame data received from the MAC receiver is written into the
-- FIFO on the rx_mac_aclk. An end-of-frame marker is written to
-- the BRAM parity bit on the last byte of data stored for a frame.
-- This acts as frame deliniation.
--
-- The rx_axis_mac_tvalid, rx_axis_mac_tlast, and rx_axis_mac_tuser signals
-- qualify the frame. A frame which ends with rx_axis_mac_tuser asserted
-- indicates a bad frame and will cause the FIFO write address
-- pointer to be reset to the base address of that frame. In this
-- way the bad frame will be overwritten with the next received
-- frame and is therefore dropped from the FIFO.
--
-- Frames will also be dropped from the FIFO if an overflow occurs.
-- If there is not enough memory capacity in the FIFO to store the
-- whole of an incoming frame, the write address pointer will be
-- reset and the overflow signal asserted.
--
-- When there is at least one complete frame in the FIFO,
-- the 8-bit AxiStream read interface's rx_axis_fifo_tvalid signal will
-- be enabled allowing data to be read from the FIFO.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The read clock (user side) should
-- always operate at an equal or faster frequency than the write
-- clock (MAC side).
--
-- The FIFO is designed to work with a minimum frame length of 8
-- bytes.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
-- Requirements :
-- * Minimum frame size of 8 bytes
-- * Spacing between good/bad frame signaling (encoded by
-- rx_axis_mac_tvalid, rx_axis_mac_tlast, rx_axis_mac_tuser), is at least 64
-- clock cycles
-- * Write AxiStream clock is 125MHz downto 1.25MHz
-- * Read AxiStream clock equal to or faster than write clock,
-- and downto 20MHz
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the Receiver FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_rx_client_fifo is
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0) := (others => '0');
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_rx_client_fifo;
architecture RTL of tri_mode_ethernet_mac_0_rx_client_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the block RAM
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_bram_tdp
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
-- Encoded read state machine states
type rd_state_typ is (WAIT_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
QUEUE_SOF_s,
SOF_s,
DATA_s,
EOF_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states
type wr_state_typ is (IDLE_s,
FRAME_s,
GF_s,
BF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe_long is array(0 to 2) of std_logic;
type cntl_pipe_short is array(0 to 1) of std_logic;
signal wr_en : std_logic;
signal wr_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0) := (others => '0');
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_dv_pipe : cntl_pipe_long;
signal wr_gfbf_pipe : cntl_pipe_short;
signal wr_gf : std_logic;
signal wr_bf : std_logic;
signal wr_eof_bram_pipe : cntl_pipe_short;
signal wr_eof_bram : std_logic;
signal frame_in_fifo : std_logic;
signal rd_addr : unsigned(11 downto 0) := (others => '0');
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram : std_logic_vector(8 downto 0);
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_delay : std_logic_vector(7 downto 0) := (others => '0');
signal rd_valid_pipe : std_logic_vector(1 downto 0);
signal rd_eof_bram : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_pull_frame : std_logic;
signal rd_eof : std_logic;
signal wr_store_frame_tog : std_logic := '0';
signal rd_store_frame_sync : std_logic;
signal rd_store_frame_delay : std_logic := '0';
signal rd_store_frame : std_logic;
signal rd_frames : unsigned(8 downto 0) := (others => '0');
signal wr_fifo_full : std_logic;
signal old_rd_addr : std_logic_vector(1 downto 0);
signal update_addr_tog : std_logic;
signal update_addr_tog_sync : std_logic;
signal update_addr_tog_sync_reg : std_logic;
signal wr_rd_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_diff_in : unsigned(12 downto 0) := (others => '0');
signal wr_addr_diff : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_status : unsigned(3 downto 0) := (others => '0');
signal rx_axis_fifo_tlast_int : std_logic;
signal doa_l_unused : std_logic_vector(8 downto 0);
signal doa_u_unused : std_logic_vector(8 downto 0);
signal rx_fifo_reset : std_logic;
signal rx_mac_reset : std_logic;
--------------------------------------------------------------------------------
-- Begin FIFO architecture
--------------------------------------------------------------------------------
begin
-- invert reset sense as architecture is optimised for active high resets
rx_fifo_reset <= not rx_fifo_resetn;
rx_mac_reset <= not rx_mac_resetn;
------------------------------------------------------------------------------
-- Read state machines and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are WAIT, QUEUE1, QUEUE2, QUEUE3, QUEUE_SOF, SOF, DATA, EOF.
-- Clock state to next state.
clock_rds_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_state <= WAIT_s;
else
rd_state <= rd_nxt_state;
end if;
end if;
end process clock_rds_p;
rx_axis_fifo_tlast <= rx_axis_fifo_tlast_int;
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rx_axis_fifo_tready,
rx_axis_fifo_tlast_int, rd_valid_pipe)
begin
case rd_state is
when WAIT_s =>
-- Wait until there is a full frame in the FIFO, then
-- start to load the pipeline.
if frame_in_fifo = '1' and rx_axis_fifo_tlast_int = '0' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= WAIT_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_SOF_s;
when QUEUE_SOF_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_s;
when SOF_s =>
-- A new frame begins immediately following end of last frame.
if rx_axis_fifo_tready = '1' then
rd_nxt_state <= DATA_s;
else
rd_nxt_state <= SOF_s;
end if;
when DATA_s =>
-- Read data from the FIFO. When the EOF marker is detected from
-- the BRAM output, move to the EOF state.
if rx_axis_fifo_tready = '1' and rd_eof = '1' then
rd_nxt_state <= EOF_s;
else
rd_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- Hold in this state until tready is asserted and the EOF
-- marker (tlast) is accepted on interface.
-- If there is another frame in the FIFO, then it will already be
-- queued into the pipeline so so move straight to SOF state.
if rx_axis_fifo_tready = '1' then
if rd_valid_pipe(1) = '1' then
rd_nxt_state <= SOF_s;
else
rd_nxt_state <= WAIT_s;
end if;
else
rd_nxt_state <= EOF_s;
end if;
when others =>
rd_nxt_state <= WAIT_s;
end case;
end process next_rds_p;
-- Detect if frame_in_fifo was high 3 reads ago.
-- This is used to ensure we only treat data in the pipeline as valid if
-- frame_in_fifo goes high at or before the EOF marker of the current frame.
-- It may be that there is valid data (i.e a partial frame has been written)
-- but until the end of that frame we do not know if it is a good frame.
rd_valid_pipe_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if (rx_axis_fifo_tready = '1') then
rd_valid_pipe <= rd_valid_pipe(0) & frame_in_fifo;
end if;
end if;
end process rd_valid_pipe_p;
-- Decode tlast signal from EOF marker.
rd_ll_decode_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tlast_int <= '0';
elsif rx_axis_fifo_tready = '1' then
-- Assert tlast signal when the EOF marker has been detected, and
-- continue to drive it until it has been accepted on the interface.
case rd_state is
when EOF_s =>
rx_axis_fifo_tlast_int <= '1';
when others =>
rx_axis_fifo_tlast_int <= '0';
end case;
end if;
end if;
end process rd_ll_decode_p;
-- Decode the tvalid output based on state.
rd_ll_src_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tvalid <= '0';
else
case rd_state is
when QUEUE_SOF_s =>
rx_axis_fifo_tvalid <= '1';
when SOF_s =>
rx_axis_fifo_tvalid <= '1';
when DATA_s =>
rx_axis_fifo_tvalid <= '1';
when EOF_s =>
rx_axis_fifo_tvalid <= '1';
when others =>
if rx_axis_fifo_tready = '1' then
rx_axis_fifo_tvalid <= '0';
end if;
end case;
end if;
end if;
end process rd_ll_src_p;
-- Decode internal control signals.
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en_p : process(rd_state, rx_axis_fifo_tready)
begin
case rd_state is
when WAIT_s =>
rd_en <= '0';
when QUEUE1_s =>
rd_en <= '1';
when QUEUE2_s =>
rd_en <= '1';
when QUEUE3_s =>
rd_en <= '1';
when QUEUE_SOF_s =>
rd_en <= '1';
when others =>
rd_en <= rx_axis_fifo_tready;
end case;
end process rd_en_p;
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
-- When the current frame is done, and if there is no frame in the FIFO, then
-- the FIFO must wait until a new frame is written in. This requires the read
-- address to be moved back to where the new frame will be written. The
-- pipeline is then reloaded using the QUEUE states.
p_rd_addr_reload : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_addr_reload <= '0';
else
if rd_state = EOF_s and rd_nxt_state = WAIT_s then
rd_addr_reload <= '1';
else
rd_addr_reload <= '0';
end if;
end if;
end if;
end process p_rd_addr_reload;
-- Data is available if there is at least one frame stored in the FIFO.
p_rd_avail : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
frame_in_fifo <= '0';
else
if rd_frames /= (rd_frames'range => '0') then
frame_in_fifo <= '1';
else
frame_in_fifo <= '0';
end if;
end if;
end if;
end process p_rd_avail;
-- When a frame has been stored we need to synchronize that event to the
-- read clock domain for frame count store.
resync_wr_store_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => rx_fifo_aclk,
data_in => wr_store_frame_tog,
data_out => rd_store_frame_sync
);
p_delay_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
rd_store_frame_delay <= rd_store_frame_sync;
end if;
end process p_delay_rd_store;
-- Edge detect of the resynchronized frame count. This creates a pulse
-- when a new frame has been stored.
p_sync_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_store_frame <= '0';
else
-- Edge detector
if (rd_store_frame_delay xor rd_store_frame_sync) = '1' then
rd_store_frame <= '1';
else
rd_store_frame <= '0';
end if;
end if;
end if;
end process p_sync_rd_store;
-- This creates a pulse when a new frame has begun to be output.
p_rd_pull_frame : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_pull_frame <= '0';
else
if rd_state = SOF_s and rd_nxt_state /= SOF_s then
rd_pull_frame <= '1';
elsif rd_state = QUEUE_SOF_s and rd_nxt_state /= QUEUE_SOF_s then
rd_pull_frame <= '1';
else
rd_pull_frame <= '0';
end if;
end if;
end if;
end process p_rd_pull_frame;
-- Up/down counter to monitor the number of frames stored within the FIFO.
-- Note:
-- * increments at the end of a frame write cycle
-- * decrements at the beginning of a frame read cycle
p_rd_frames : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_frames <= (others => '0');
else
-- A frame is written to the FIFO in this cycle, and no frame is being
-- read out on the same cycle.
if rd_store_frame = '1' and rd_pull_frame = '0' then
rd_frames <= rd_frames + 1;
-- A frame is being read out on this cycle and no frame is being
-- written on the same cycle.
elsif rd_store_frame = '0' and rd_pull_frame = '1' then
rd_frames <= rd_frames - 1;
end if;
end if;
end if;
end process p_rd_frames;
------------------------------------------------------------------------------
-- Write state machines and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are IDLE, FRAME, GF, BF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_state <= IDLE_s;
else
wr_state <= wr_nxt_state;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinatorial.
next_wrs_p : process(wr_state, wr_dv_pipe(1), wr_gf, wr_bf, wr_fifo_full)
begin
case wr_state is
when IDLE_s =>
-- There is data in incoming pipeline when dv_pipe(1) goes high.
if wr_dv_pipe(1) = '1' then
wr_nxt_state <= FRAME_s;
else
wr_nxt_state <= IDLE_s;
end if;
when FRAME_s =>
-- If FIFO is full then go to overflow state.
-- If the good or bad flag is detected, then the end of the frame
-- has been reached and the gf or bf state is visited before idle.
-- Otherwise remain in frame state while data is written to FIFO.
if wr_fifo_full = '1' then
wr_nxt_state <= OVFLOW_s;
elsif wr_gf = '1' then
wr_nxt_state <= GF_s;
elsif wr_bf = '1' then
wr_nxt_state <= BF_s;
else
wr_nxt_state <= FRAME_s;
end if;
when GF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when BF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when OVFLOW_s =>
-- Wait until the good or bad flag received.
if wr_gf = '1' or wr_bf = '1' then
wr_nxt_state <= IDLE_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= IDLE_s;
end case;
end process next_wrs_p;
-- Decode control signals, combinatorial.
-- wr_en is used to enable the BRAM write and loading of the input pipeline.
wr_en <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- Increment the write address when we are receiving valid frame data.
wr_addr_inc <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- If the FIFO overflows or a frame is to be dropped, we need to move the
-- write address back to the start of the frame. This allows the data to be
-- overwritten.
wr_addr_reload <= '1' when wr_state = BF_s or wr_state = OVFLOW_s else '0';
-- The start address is saved when in the idle state.
wr_start_addr_load <= '1' when wr_state = IDLE_s else '0';
-- We need to know when a frame is stored, in order to increment the count of
-- frames stored in the FIFO.
p_wr_store_tog : process (rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if wr_state = GF_s then
wr_store_frame_tog <= not wr_store_frame_tog;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when data is being written into the FIFO.
wr_addr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_addr <= (others => '0');
else
if wr_addr_reload = '1' then
wr_addr <= wr_start_addr;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process wr_addr_p;
-- Store the start address.
wr_staddr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_start_addr <= (others => '0');
else
if wr_start_addr_load = '1' then
wr_start_addr <= wr_addr;
end if;
end if;
end if;
end process wr_staddr_p;
-- Read address is incremented when data is being read from the FIFO.
rd_addr_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_addr <= (others => '0');
else
if rd_addr_reload = '1' then
rd_addr <= rd_addr - 3;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process rd_addr_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_data_pipe(0) <= rx_axis_mac_tdata;
wr_data_pipe(1) <= wr_data_pipe(0);
wr_data_bram <= wr_data_pipe(1);
end if;
end process reg_din_p;
-- The valid input enables BRAM write and is a condition for other signals.
reg_dv_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_dv_pipe(0) <= rx_axis_mac_tvalid;
wr_dv_pipe(1) <= wr_dv_pipe(0);
wr_dv_pipe(2) <= wr_dv_pipe(1);
end if;
end process reg_dv_p;
-- End of frame flag set when tlast and tvalid are asserted together.
reg_eof_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_eof_bram_pipe(0) <= rx_axis_mac_tlast;
wr_eof_bram_pipe(1) <= wr_eof_bram_pipe(0);
wr_eof_bram <= wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_eof_p;
-- Upon arrival of EOF flag, the frame is good if tuser signal
-- is low, and bad if tuser signal is high.
reg_gf_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_gfbf_pipe(0) <= rx_axis_mac_tuser;
wr_gfbf_pipe(1) <= wr_gfbf_pipe(0);
wr_gf <= (not wr_gfbf_pipe(1)) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
wr_bf <= wr_gfbf_pipe(1) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_gf_p;
-- Register data outputs from BRAM.
-- No resets to allow for SRL16 target.
reg_dout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_data_delay <= rd_data_bram;
rd_data_pipe <= rd_data_delay;
rx_axis_fifo_tdata <= rd_data_pipe;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_eof <= rd_eof_bram(0);
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Overflow functionality
------------------------------------------------------------------------------
-- to minimise the number of read address updates the bottom 6 bits of the
-- read address are not passed across and the write domain will only sample
-- them when bits 5 and 4 of the read address transition from 01 to 10.
-- Since this is for full detection this just means that if the read stops
-- the write will hit full up to 64 locations early
-- need to use two bits and look for an increment transition as reload can cause
-- a decrement on this boundary (decrement is only by 3 so above bit 2 should be safe)
p_rd_addr_tog : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
old_rd_addr <= (others => '0');
update_addr_tog <= '0';
else
old_rd_addr <= std_logic_vector(rd_addr(5 downto 4));
if rd_addr(5 downto 4) = "10" and old_rd_addr = "01" then
update_addr_tog <= not update_addr_tog;
end if;
end if;
end if;
end process p_rd_addr_tog;
sync_rd_addr_tog: tri_mode_ethernet_mac_0_sync_block
port map (
clk => rx_mac_aclk,
data_in => update_addr_tog,
data_out => update_addr_tog_sync
);
-- Obtain the difference between write and read pointers.
p_sample_addr : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
update_addr_tog_sync_reg <= '0';
wr_rd_addr(11 downto 6) <= (others => '0');
else
update_addr_tog_sync_reg <= update_addr_tog_sync;
if update_addr_tog_sync_reg /= update_addr_tog_sync then
wr_rd_addr(11 downto 6) <= rd_addr(11 downto 6);
end if;
end if;
end if;
end process p_sample_addr;
wr_rd_addr(5 downto 0) <= "000000";
wr_addr_diff_in <= ('0' & wr_rd_addr) - ('0' & wr_addr);
-- Obtain the difference between write and read pointers.
p_addr_diff : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_addr_diff <= (others => '0');
else
wr_addr_diff <= wr_addr_diff_in(11 downto 0);
end if;
end if;
end process p_addr_diff;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_full <= '0';
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1';
else
wr_fifo_full <= '0';
end if;
end if;
end if;
end process p_wr_full;
-- Decode the overflow indicator output.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_wr_fifo_status : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_status <= "0000";
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000";
else
wr_fifo_status(3) <= not wr_addr_diff(11);
wr_fifo_status(2) <= not wr_addr_diff(10);
wr_fifo_status(1) <= not wr_addr_diff(9);
wr_fifo_status(0) <= not wr_addr_diff(8);
end if;
end if;
end if;
end process p_wr_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram;
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
rd_eof_bram(0) <= rd_eof_data_bram(8);
rd_data_bram <= rd_eof_data_bram(7 downto 0);
rx_ramgen_i : tri_mode_ethernet_mac_0_bram_tdp
generic map (
DATA_WIDTH => 9,
ADDR_WIDTH => 12
)
port map (
b_dout => rd_eof_data_bram,
a_addr => std_logic_vector(wr_addr(11 downto 0)),
b_addr => std_logic_vector(rd_addr(11 downto 0)),
a_clk => rx_mac_aclk,
b_clk => rx_fifo_aclk,
a_din => wr_eof_data_bram,
b_en => rd_en,
a_rst => rx_mac_reset,
b_rst => rx_fifo_reset,
a_wr => wr_en
);
end RTL;
|
<filename>rtl/UARTTX.vhdl
--
-- simple UART, bit clock is the clk_in
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity UARTTX is
port (
clk_in : in std_logic := '0'; -- 50 MHz clock
data_in : in std_logic_vector(7 downto 0) := (others => '0');
start_in : in std_logic := '0';
tx_busy_o : out std_logic;
tx_o : out std_logic
);
end entity UARTTX;
architecture rtl of UARTTX is
signal state : integer range 0 to 15 := 0;
signal txbuff : std_logic_vector(10 downto 0) := "10000000001";
signal bit_cnt : integer range 0 to 63 := 0;
signal tx_busy : std_logic := '0';
begin
tx_o <= txbuff(0);
tx_busy_o <= tx_busy;
process(clk_in)
begin
if (rising_edge(clk_in)) then
if bit_cnt = 0 then
case state is
when 0 => -- wait for start condition
if start_in = '1' then
state <= 1;
txbuff <= '1' & data_in & "01"; -- stop bit, data & start condition.
tx_busy <= '1';
end if;
when 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 =>
txbuff <= '1' & txbuff(10 downto 1); -- shift
state <= state + 1;
when others =>
state <= 0;
tx_busy <= '0';
end case;
end if;
if state /= 0 then
if bit_cnt = 0 then
bit_cnt <= 49;
else
bit_cnt <= bit_cnt - 1;
end if;
else
bit_cnt <= 0;
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:05:59 04/06/2014
-- Design Name:
-- Module Name: C:/Users/Tom/projs/code/square_wave/square_wave_test.vhd
-- Project Name: square_wave
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: square_wave
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY square_wave_test IS
END square_wave_test;
ARCHITECTURE behavior OF square_wave_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT square_wave
PORT(
x_in : IN std_logic_vector(9 downto 0);
enable : IN std_logic;
square_out : OUT std_logic_vector(11 downto 0);
pwm_length : IN std_logic_vector(9 downto 0)
);
END COMPONENT;
--Inputs
signal x_in : std_logic_vector(9 downto 0) := (others => '0');
signal enable : std_logic := '0';
signal pwm_length : std_logic_vector(9 downto 0) := (others => '0');
--Outputs
signal square_out : std_logic_vector(11 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
signal x_sig: unsigned(9 downto 0);
signal pwm_sig: unsigned(9 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: square_wave PORT MAP (
x_in => x_in,
enable => enable,
square_out => square_out,
pwm_length => pwm_length
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
enable <= '1';
-- insert stimulus here
loop
pwm_sig <= to_unsigned(to_integer(pwm_sig) + 1,10);
pwm_length <= std_logic_vector(pwm_sig);
for i in 0 to 2 ** x_sig'length loop
x_sig <= to_unsigned(to_integer(x_sig) + 1,10);
x_in <= std_logic_vector(x_sig);
wait for 10 ns;
end loop;
wait for 10 ns;
end loop;
wait;
end process;
END;
|
<filename>labs/PROJECT/downcounter/encoder_ky040.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:41:55 04/30/2020
-- Design Name:
-- Module Name: encoder_ky040 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encoder_ky040 is
generic (
g_NBIT : positive := 4 -- Number of bits
);
port ( srst_n_i : in STD_LOGIC; -- Synchronous reset
clk_i : in STD_LOGIC; --clock
inA : in STD_LOGIC; --pin A
inB : in STD_LOGIC; --pin B
enc_sw : in std_logic; -- Switch of the encoder
final_pos : out STD_LOGIC_VECTOR (g_NBIT-1 downto 0)
);
end encoder_ky040;
architecture Behavioral of encoder_ky040 is
signal counter_e : std_logic_vector(g_NBIT-1 downto 0):= B"0000"; -- encoder
signal previousstateA : std_logic := '0';
signal stateA: std_logic;
signal stateB: std_logic;
begin
stateA <= inA;
stateB <= inB;
--------------------------------------------------------------------
-- PROCESS OF CALCULATION OF THE ENCODER POSITION
--
--------------------------------------------------------------------
encoder_process : process(clk_i)
begin
if rising_edge(clk_i) then
if srst_n_i='0' then
counter_e <= (others => '0'); -- Clear all bits
elsif enc_sw = '1' then
if stateA /= previousstateA then
if stateB /= stateA then
counter_e <= counter_e + 1;
else
counter_e <= counter_e - 1;
end if;
previousstateA <= stateA;
end if;
end if;
end if;
end process encoder_process;
final_pos <= std_logic_vector(counter_e);
end Behavioral;
|
<gh_stars>1000+
----------------------------------------------------------------------------------
-- Engineer: <NAME> <<EMAIL>>
--
-- Module Name: output_serialiser - Behavioral
-- Description: A 5-bit SDR output serialiser
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity output_serialiser is
Port ( clk_load : in STD_LOGIC;
clk_output : in STD_LOGIC;
strobe : in STD_LOGIC;
ser_data : in STD_LOGIC_VECTOR (4 downto 0);
reset : in STD_LOGIC;
ser_output : out STD_LOGIC);
end output_serialiser;
architecture Behavioral of output_serialiser is
signal clk0, clk1, clkdiv : std_logic;
signal cascade1, cascade2, cascade3, cascade4 : std_logic;
begin
clkdiv <= clk_load;
clk0 <= clk_output;
clk1 <= '0';
OSERDES2_master : OSERDES2
generic map (
BYPASS_GCLK_FF => FALSE, -- Bypass CLKDIV syncronization registers (TRUE/FALSE)
DATA_RATE_OQ => "SDR", -- Output Data Rate ("SDR" or "DDR")
DATA_RATE_OT => "SDR", -- 3-state Data Rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width (2-8)
OUTPUT_MODE => "SINGLE_ENDED", -- "SINGLE_ENDED" or "DIFFERENTIAL"
SERDES_MODE => "MASTER", -- "NONE", "MASTER" or "SLAVE"
TRAIN_PATTERN => 0 -- Training Pattern (0-15)
) port map (
OQ => ser_output, -- 1-bit output: Data output to pad or IODELAY2
SHIFTOUT1 => cascade1, -- 1-bit output: Cascade data output
SHIFTOUT2 => cascade2, -- 1-bit output: Cascade 3-state output
SHIFTOUT3 => open, -- 1-bit output: Cascade differential data output
SHIFTOUT4 => open, -- 1-bit output: Cascade differential 3-state output
SHIFTIN1 => '1', -- 1-bit input: Cascade data input
SHIFTIN2 => '1', -- 1-bit input: Cascade 3-state input
SHIFTIN3 => cascade3, -- 1-bit input: Cascade differential data input
SHIFTIN4 => cascade4, -- 1-bit input: Cascade differential 3-state input
TQ => open, -- 1-bit output: 3-state output to pad or IODELAY2
CLK0 => CLK0, -- 1-bit input: I/O clock input
CLK1 => CLK1, -- 1-bit input: Secondary I/O clock input
CLKDIV => CLKDIV, -- 1-bit input: Logic domain clock input
-- D1 - D4: 1-bit (each) input: Parallel data inputs
D1 => ser_data(4),
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => strobe, -- 1-bit input: Data strobe input
OCE => '1', -- 1-bit input: Clock enable input
RST => reset, -- 1-bit input: Asynchrnous reset input
-- T1 - T4: 1-bit (each) input: 3-state control inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1', -- 1-bit input: 3-state clock enable input
TRAIN => '0' -- 1-bit input: Training pattern enable input
);
OSERDES2_slave : OSERDES2
generic map (
BYPASS_GCLK_FF => FALSE, -- Bypass CLKDIV syncronization registers (TRUE/FALSE)
DATA_RATE_OQ => "SDR", -- Output Data Rate ("SDR" or "DDR")
DATA_RATE_OT => "SDR", -- 3-state Data Rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width (2-8)
OUTPUT_MODE => "SINGLE_ENDED", -- "SINGLE_ENDED" or "DIFFERENTIAL"
SERDES_MODE => "SLAVE", -- "NONE", "MASTER" or "SLAVE"
TRAIN_PATTERN => 0 -- Training Pattern (0-15)
) port map (
OQ => open, -- 1-bit output: Data output to pad or IODELAY2
SHIFTOUT1 => open, -- 1-bit output: Cascade data output
SHIFTOUT2 => open, -- 1-bit output: Cascade 3-state output
SHIFTOUT3 => cascade3, -- 1-bit output: Cascade differential data output
SHIFTOUT4 => cascade4, -- 1-bit output: Cascade differential 3-state output
SHIFTIN1 => cascade1, -- 1-bit input: Cascade data input
SHIFTIN2 => cascade2, -- 1-bit input: Cascade 3-state input
SHIFTIN3 => '1', -- 1-bit input: Cascade differential data input
SHIFTIN4 => '1', -- 1-bit input: Cascade differential 3-state input
TQ => open, -- 1-bit output: 3-state output to pad or IODELAY2
CLK0 => CLK0, -- 1-bit input: I/O clock input
CLK1 => CLK1, -- 1-bit input: Secondary I/O clock input
CLKDIV => CLKDIV, -- 1-bit input: Logic domain clock input
-- D1 - D4: 1-bit (each) input: Parallel data inputs
D1 => ser_data(0),
D2 => ser_data(1),
D3 => ser_data(2),
D4 => ser_data(3),
IOCE => strobe, -- 1-bit input: Data strobe input
OCE => '1', -- 1-bit input: Clock enable input
RST => '0', -- 1-bit input: Asynchrnous reset input
-- T1 - T4: 1-bit (each) input: 3-state control inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1', -- 1-bit input: 3-state clock enable input
TRAIN => '0' -- 1-bit input: Training pattern enable input
);
end Behavioral;
|
<reponame>GieeFoR/VHDL-Processor<filename>processor/ALU.vhd<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is port (
clk : in std_logic;
A : in signed(15 downto 0);
B : in signed(15 downto 0);
Salu : in signed (4 downto 0);
Y : out signed(15 downto 0);
C, Z, S, P : out std_logic
);
end entity;
architecture rtl of ALU is
begin
process (clk, Salu, A, B)
--zmienne varA i varB służą do przechowania wartości
--podanych odpowiednio na wejście A i B ALU
variable result, varA, varB : signed (16 downto 0);
variable CF, ZF, SF, PF : std_logic;
begin
varA(16) := '0';
varA(15 downto 0) := A;
varB(16) := '0';
varB(15 downto 0) := B;
case Salu is
--przepisanie wejścia A na wyjście
when "00000" =>
result := varA;
--przepisanie wejścia B na wyjście
when "00001" =>
result := varB;
--dodawanie
when "00010" =>
result := varA + varB;
--odejmowanie
when "00011" =>
result := varA - varB;
--operacja OR
when "00100" =>
result := varA or varB;
--operacja AND
when "00101" =>
result := varA and varB;
--operacja XOR
when "00110" =>
result := varA xor varB;
--operacja XNOR
when "00111" =>
result := varA xnor varB;
--operacja NOT dla B
when "01000" =>
result := not varB;
--operacja NOT dla A
when "01001" =>
result := not varA;
-- liczba B z odwrotnym znakiem
when "01010" =>
result := to_signed(0, 17) - varB;
-- liczba A z odwrotnym znakiem
when "01011" =>
result := to_signed(0, 17) - varA;
-- wyzerowanie wyjścia
when "01100" =>
result := to_signed(0, 17);
-- suma wejść z przeniesieniem
when "01101" =>
if(CF = '1') then
result := varA + varB + to_signed(1, 17);
else
result := varA + varB;
end if;
-- różnica wejść z przeniesieniem
when "01110" =>
if(CF = '1') then
result := varA - varB - to_signed(1, 17);
else
result := varA - varB;
end if;
--inkrementacja A
when "01111" =>
result := varA + to_signed(1, 17);
--inkrementacja B
when "10000" =>
result := varB + to_signed(1, 17);
--dekrementacja A
when "10001" =>
result := varA - to_signed(1, 17);
--inkrementacja B
when "10010" =>
result := varB - to_signed(1, 17);
--shift right
when "10011" =>
result(16) := '0';
result(15 downto 0) := varA (16 downto 1);
--shift left
when "10100" =>
result(0) := '0';
result(16 downto 1) := varA(15 downto 0);
--porównanie dwóch wejść ze sobą
when "10101" =>
if(varA = varB) then
result := to_signed(1,17);
else
result := to_signed(0,17);
end if;
--RPL8 (zamiana 4 starszych bitów z 4 młodszymi bitami wartości 8-bitowej)
when "10110" =>
result(16 downto 8) := varA(16 downto 8);
result(3 downto 0) := varA(7 downto 4);
result(7 downto 4) := varA(3 downto 0);
--RPL4 (zamiana 2 starszych bitów z 2 młodszymi bitami wartości 4-bitowej)
when "10111" =>
result(16 downto 4) := varA(16 downto 4);
result(1 downto 0) := varA(3 downto 2);
result(3 downto 2) := varA(1 downto 0);
when others => null;
end case;
Y <= result(15 downto 0);
Z <= ZF;
S <= SF;
C <= CF;
P <= PF;
if(clk'event and clk = '1') then
if(result = to_signed(0, 17)) then
ZF := '1';
else
ZF := '0';
end if;
if(result(15) = '1') then
SF := '1';
else
SF := '0';
end if;
CF := result(16);
PF := result(15) xor result(14) xor result(13) xor result(12) xor result(11) xor result(10) xor result(9) xor result(8) xor
result(7) xor result(6) xor result(5) xor result(4) xor result(3) xor result(2) xor result(1) xor result(0);
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:23:11 04/06/2016
-- Design Name:
-- Module Name: ALU_RESULT_STORAGE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_RESULT_STORAGE is
PORT (CLK_F,CLK_DEC,CLK_OP,CLK_EX,CLK_WB : in STD_LOGIC;
COUNTER_FOR_WRITING_DATA : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COUNTER_FOR_OUTPUT_TO_1_CYCLE_AGO: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COUNTER_FOR_OUTPUT_TO_2_CYCLE_AGO:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
ALU_RESULT_IN :in STD_LOGIC_vector(15 downto 0);
ALU_RESULT_OUT_FOR_DATA_1_CYCLE_AGO :out STD_LOGIC_vector(15 downto 0);
ALU_RESULT_OUT_FOR_DATA_2_CYCLE_AGO:out STD_LOGIC_vector(15 downto 0)
);
end ALU_RESULT_STORAGE;
architecture Behavioral of ALU_RESULT_STORAGE is
type ALU_ARRAY is array (0 to 7) of std_logic_vector(15 downto 0);
signal ALU_SIGNAL : ALU_ARRAY:=(x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000");
signal ALU_INTERNAL_SIGNAL_SIGNAL_FOR_1_CYCLE_AGO,ALU_INTERNAL_SIGNAL_SIGNAL_FOR_2_CYCLE_AGO :STD_LOGIC_VECTOR(15 DOWNTO 0);
signal CORRECTED_COUNTER_FOR_OUTPUT_TO_1_CYCLE_AGO : STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
PROCESS(CLK_OP)
BEGIN
--CORRECTED_COUNTER_FOR_OUTPUT_TO_1_CYCLE_AGO<=COUNTER_FOR_OUTPUT_TO_1_CYCLE_AGO+"001";
if FALLING_EDGE(CLK_OP) then
ALU_signal(to_integer(unsigned(COUNTER_FOR_WRITING_DATA)))<=ALU_RESULT_IN;
end if;
end process;
with COUNTER_FOR_OUTPUT_TO_1_CYCLE_AGO select
ALU_INTERNAL_SIGNAL_SIGNAL_FOR_1_CYCLE_AGO <=
ALU_SIGNAL(to_integer(unsigned(COUNTER_FOR_OUTPUT_TO_1_CYCLE_AGO)))WHEN "000",
ALU_SIGNAL(to_integer(unsigned(COUNTER_FOR_OUTPUT_TO_1_CYCLE_AGO)))WHEN OTHERS;
with COUNTER_FOR_OUTPUT_TO_2_CYCLE_AGO select
ALU_INTERNAL_SIGNAL_SIGNAL_FOR_2_CYCLE_AGO <=
ALU_SIGNAL(to_integer(unsigned(COUNTER_FOR_OUTPUT_TO_2_CYCLE_AGO)))WHEN "000",
ALU_SIGNAL(to_integer(unsigned(COUNTER_FOR_OUTPUT_TO_2_CYCLE_AGO)))WHEN OTHERS;
PROCESS(CLK_OP)
BEGIN
if RISING_EDGE(CLK_OP) then
ALU_RESULT_OUT_FOR_DATA_1_CYCLE_AGO<=ALU_INTERNAL_SIGNAL_SIGNAL_FOR_1_CYCLE_AGO;
end if;
end process;
PROCESS(CLK_EX)
BEGIN
if RISING_EDGE(CLK_EX) then
ALU_RESULT_OUT_FOR_DATA_2_CYCLE_AGO<=ALU_INTERNAL_SIGNAL_SIGNAL_FOR_2_CYCLE_AGO;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
-- This is a generic parallel in, serial out shift register architecture
-- Outputs a serial clk, data line, and active low chip select
-- This design is only capable of running with SCLK = i_CLK / 2 or lower (SCLK = i_clk invalid)
entity output_serial_interface is
generic(
NUM_BITS : integer := 24; -- i_data bit width
SCLK_DIV : integer := 2 -- o_sclk = i_clk / SCLK_DIV
);
port (
i_clk : in std_logic;
i_rst : in std_logic;
i_data : in std_logic_vector(NUM_BITS-1 downto 0);
i_wr_en: in std_logic;
o_data : out std_logic := '0';
o_sclk : out std_logic := '0';
o_cs_n : out std_logic := '1';
o_state: out std_logic_vector(1 downto 0) := "00";
o_busy : out std_logic := '0'
);
end output_serial_interface;
architecture rtl of output_serial_interface is
constant NUM_CLKS : integer := NUM_BITS * SCLK_DIV; --number of sclk edges to product
type state_t is (init, idle, write);
signal state : state_t := init;
signal sclk : std_logic := '0';
signal sclk_en : boolean := FALSE;
signal wr_complete : boolean := FALSE;
signal bit_cnt : integer range 0 to NUM_BITS := 0;
signal clk_edge_cnt : integer range 0 to NUM_BITS := 0;
begin
-- state machine control
SM : process(i_clk)
begin
if rising_edge(i_clk) then
if i_rst = '1' then
state <= init;
o_cs_n <= '1';
sclk_en <= FALSE;
o_state <= "00";
o_busy <= '0';
else
case state is
when init =>
o_state <= "00";
state <= idle; -- pass through state for now
o_busy <= '0';
when idle =>
o_state <= "01";
o_busy <= '0';
if i_wr_en = '1' then
state <= write;
else
sclk_en <= FALSE;
o_cs_n <= '1';
end if;
when write =>
o_busy <= '1';
if wr_complete = FALSE then
o_state <= "10";
sclk_en <= TRUE;
o_cs_n <= '0';
else
sclk_en <= FALSE;
o_cs_n <= '1';
state <= idle;
end if;
end case;
end if;
end if;
end process;
sclk_gen : process(i_clk) is
-- process to generate the sclk when we are in write state
variable cnt : integer range 0 to SCLK_DIV := 0;
--variable clk_edge_cnt : integer range 0 to NUM_BITS := 0;
begin
if rising_edge(i_clk) then
if i_rst = '1' then
cnt := 0;
sclk <= '0';
elsif sclk_en = TRUE then
if clk_edge_cnt < NUM_CLKS then
cnt := cnt + 1;
if cnt = (SCLK_DIV - 1) then
sclk <= not sclk;
cnt := 0;
clk_edge_cnt <= clk_edge_cnt + 1;
end if;
end if;
else
sclk <= '0';
cnt := 0;
clk_edge_cnt <= 0;
end if;
end if;
o_sclk <= sclk;
end process;
write_data : process(i_clk, sclk) is
constant MSB : integer := NUM_BITS - 1;
--variable bit_cnt : integer range 0 to NUM_BITS := 0;
begin
if rising_edge(i_clk) then
if i_rst = '1' then
bit_cnt <= 0;
o_data <= '0';
end if;
if i_wr_en = '1' then
wr_complete <= FALSE;
if bit_cnt = 0 then
o_data <= i_data(MSB); -- setup first bit early
bit_cnt <= 1;
end if;
else
if bit_cnt > NUM_BITS then
wr_complete <= TRUE;
o_data <= '0';
bit_cnt <= 0;
--bit_cnt <= 1;
end if;
end if;
end if;
-- shift data bit out on sclk edge MSB first
if falling_edge(sclk) then
if wr_complete = FALSE then
if bit_cnt <= MSB then
o_data <= i_data(MSB-bit_cnt); --(bit_cnt+1) since we already setup the first bit above
end if;
bit_cnt <= bit_cnt + 1;
end if;
end if;
end process;
end rtl;
|
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2LcEhZwPJtPMBTgRe6X2zTvN4g0FxuL4RzHeJb8=
`protect end_protected
|
-- Copyright (c) 2019 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- The frame buffer is a memory device used for caching graphics data. It is
-- used by the sprite renderer to ensure glitch-free graphics.
--
-- Internally, it contains two memory pages which are accessed alternately for
-- reading and writing, so that while one page is being written to, the other
-- is being read from.
--
-- When the flip signal is asserted, the pages are swapped. The page that was
-- previously being written to will be read from, and the page that was being
-- read from will be written to.
--
-- The frame buffer automatically clears pixels during read operations, so that
-- the write page is clean when it is flipped.
entity frame_buffer is
generic (
ADDR_WIDTH : natural := 8;
DATA_WIDTH : natural := 8
);
port (
-- clock
clk : in std_logic := '1';
-- chip select
cs : in std_logic := '1';
-- flip the pages
flip : in std_logic := '0';
-- write-only port
addr_wr : in unsigned(ADDR_WIDTH-1 downto 0);
din : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
wren : in std_logic := '0';
-- read-only port
addr_rd : in unsigned(ADDR_WIDTH-1 downto 0);
dout : out std_logic_vector(DATA_WIDTH-1 downto 0);
rden : in std_logic := '1'
);
end frame_buffer;
architecture arch of frame_buffer is
signal addr_a, addr_b : unsigned(ADDR_WIDTH-1 downto 0);
signal din_a, din_b : std_logic_vector(DATA_WIDTH-1 downto 0);
signal dout_a, dout_b : std_logic_vector(DATA_WIDTH-1 downto 0);
signal rden_a, rden_b : std_logic;
signal wren_a, wren_b : std_logic;
begin
page_a : entity work.dual_port_ram
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH
)
port map (
clk => clk,
cs => cs,
addr_wr => addr_a,
din => din_a,
wren => wren_a,
addr_rd => addr_a,
dout => dout_a,
rden => rden_a
);
page_b : entity work.dual_port_ram
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH
)
port map (
clk => clk,
cs => cs,
addr_wr => addr_b,
din => din_b,
wren => wren_b,
addr_rd => addr_b,
dout => dout_b,
rden => rden_b
);
addr_a <= addr_rd when flip = '0' else addr_wr;
addr_b <= addr_rd when flip = '1' else addr_wr;
rden_a <= rden;
rden_b <= rden;
wren_a <= wren when flip = '1' else rden;
wren_b <= wren when flip = '0' else rden;
din_a <= din when wren = '1' and flip = '1' else (others => '0');
din_b <= din when wren = '1' and flip = '0' else (others => '0');
-- output
dout <= dout_a when rden = '1' and flip = '0' else
dout_b when rden = '1' and flip = '1' else
(others => '0');
end arch;
|
<filename>Multiplier/Project/VHDL/add_sub.vhd<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add_sub is
port (
add_sub_in_a:in std_logic_vector(7 downto 0 );
add_sub_in_b:in std_logic_vector(7 downto 0 );
add_sub_out:out std_logic_vector(7 downto 0 );
add_sub_sel:in std_logic
);
end add_sub ;
---// when the sel is ONE = Addition when select zero = subtraction \\---
architecture behaviour of add_sub is
begin
process (add_sub_in_a,add_sub_in_b,add_sub_sel)
begin
if (add_sub_sel='1')then
add_sub_out<=add_sub_in_a+add_sub_in_b;
else
add_sub_out<=add_sub_in_a-add_sub_in_b;
end if ;
end process;
end behaviour;
|
<filename>rocket_soc/techmap/mem/romprn_tech.vhd
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author <NAME> - <EMAIL>
--! @brief Technology specific Galileo PRN ROM codes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity RomPrn_tech is
generic (
generic_tech : integer := 0
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of RomPrn_tech is
component RomPrn_inferred is
port (
clk : in std_ulogic;
inAdr : in std_logic_vector(12 downto 0);
outData : out std_logic_vector(31 downto 0)
);
end component;
component RomPrn_micron180 is
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
begin
genrom0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
romprn_infer : RomPrn_inferred port map
(
i_clk,
i_address,
o_data
);
end generate;
genrom1 : if generic_tech = micron180 generate
romprn_micr : RomPrn_micron180 port map
(
i_clk,
i_address,
o_data
);
end generate;
end;
|
<filename>source/main.vhd
-----------------------------
--! @author <NAME>
--! @date 18.03.2021
--! @file main.vhd
--! @version C
--! @copyright Copyright (c) 2021 <NAME>
--!
--! @brief *Project name:* Delay line
--! *Module name:* Delay line TOP entity
--!
--! @details *Detailed description*:
--! Tis is very long CARRY4 delay line for delay testing on oscilloscope.
--! **Revision:**
--! A - initial design
--! B - this version are for delay line testing
--! C - clock_wiz(PLL) are now placed in separate entity. Add loopback clock output and input for testing delay line and avoid Vivado warnings.
--! D -
LIBRARY IEEE; --always use this library
USE IEEE.std_logic_unsigned.ALL; --extends the std_logic_arith library
USE IEEE.std_logic_arith.ALL; --basic arithmetic operations for representing integers in standard ways
USE IEEE.numeric_std.ALL; --use this library if arithmetic required
USE IEEE.std_logic_1164.ALL; --always use this library
ENTITY main IS
GENERIC (
g_DELAY_LINE_COUNT : INTEGER := 4; --! count of delay lines
g_DL_ELEMENT_COUNT : INTEGER := 128 * 4 --! delay element count in delay line. It must be n*4.
);
PORT (
-- -- Hardware on Basys 3 development board
i_clk : IN STD_LOGIC; --! 100MHz clock
o_clock : OUT STD_LOGIC; --! In FPGA (PLL) generated test signal that is connected to output pin without delay
o_clock_loopback : OUT STD_LOGIC; --! o_clock_loopback and i_clock_loopback are routed together on the board
i_clock_loopback : IN STD_LOGIC; --! o_clock_loopback and i_clock_loopback are routed together on the board
o_delay_clock : OUT STD_LOGIC --! In FPGA generated test signal that is driven through delay line and then to output pin for comparison with not delayed clock
);
END main; --! Delay line TOP entity
ARCHITECTURE rtl OF main IS
SIGNAL w_clk10 : STD_LOGIC; --! 10MHz clock for testing delay loop
SIGNAL w_clk100 : STD_LOGIC; --! 100MHz main clock
SIGNAL w_delay_interconnect : STD_LOGIC_VECTOR(g_DELAY_LINE_COUNT - 1 DOWNTO 0); --! interconnections of individual delay lines
SIGNAL w_term_code : STD_LOGIC_VECTOR(g_DL_ELEMENT_COUNT - 1 DOWNTO 0); --! interconnections of individual delay lines
ATTRIBUTE keep : STRING;
ATTRIBUTE keep OF w_clk10 : SIGNAL IS "true";
ATTRIBUTE keep OF w_clk100 : SIGNAL IS "true";
BEGIN
---------------------------------------------------------
-- outputs --
---------------------------------------------------------
o_clock <= w_clk10;
o_clock_loopback <= w_clk10;
o_delay_clock <= w_delay_interconnect(g_DELAY_LINE_COUNT - 1);
---------------------------------------------------------
-- instantiate sub entities --
---------------------------------------------------------
--! Clock generator entity
clock_gen_inst : ENTITY work.clock_gen
PORT MAP(
i_clk => i_clk, --! Main clock input. For Basys3 board it is 100MHz
o_clock100 => w_clk100, --! In FPGA (PLL) generated clock
o_clock10 => w_clk10 --! In FPGA (PLL) generated clock
);
-- INSTANTIATION Template
--! FIFO memory 512x512
fifo_instance : ENTITY work.fifo_generator_0
PORT MAP(
rst => '0',
wr_clk => w_clk100,
rd_clk => w_clk100,
din => std_logic_vector(to_unsigned(0,512)),
wr_en => '1',
rd_en => '1'--,
-- dout => dout,
-- full => full,
-- empty => empty
);
-- End INSTANTIATION Template
--! delay line No.0
--!
delay_line_inst_0 : ENTITY work.delay_line
GENERIC MAP(
g_DL_ELEMENT_COUNT => g_DL_ELEMENT_COUNT/g_DELAY_LINE_COUNT,
g_LOCATION => "SLICE_X36Y50"
)
PORT MAP(
i_clk => w_clk100, --! Main clock for D-Flip-Flops
i_trigger_in => i_clock_loopback, --! Input of delay line
o_loop_out => w_delay_interconnect(0), --! Output of delay line
o_dff_q => w_term_code(g_DL_ELEMENT_COUNT - 1 DOWNTO 0),
i_D => "0000", --! DI for CARRY4 block
i_S => "1111", --! S for CARRY4 block
i_nReset => '1', --! Synchronous reset input for D-Flip-Flops
i_clock_enable => '1' --! Clock enable input for D-Flip-Flops
);
--! delay line No.1
--!
delay_line_inst_1 : ENTITY work.delay_line
GENERIC MAP(
g_DL_ELEMENT_COUNT => g_DL_ELEMENT_COUNT/g_DELAY_LINE_COUNT,
g_LOCATION => "SLICE_X38Y50"
)
PORT MAP(
i_clk => w_clk100, --! Main clock for D-Flip-Flops
i_trigger_in => w_delay_interconnect(0), --! Input of delay line
o_loop_out => w_delay_interconnect(1), --! Output of delay line
o_dff_q => o_dff_q,
i_D => "0000", --! DI for CARRY4 block
i_S => "1111", --! S for CARRY4 block
i_nReset => '1', --! Synchronous reset input for D-Flip-Flops
i_clock_enable => '1' --! Clock enable input for D-Flip-Flops
);
--! delay line No.2
--!
delay_line_inst_2 : ENTITY work.delay_line
GENERIC MAP(
g_DL_ELEMENT_COUNT => g_DL_ELEMENT_COUNT/g_DELAY_LINE_COUNT,
g_LOCATION => "SLICE_X40Y50"
)
PORT MAP(
i_clk => w_clk100, --! Main clock for D-Flip-Flops
i_trigger_in => w_delay_interconnect(1), --! Input of delay line
o_loop_out => w_delay_interconnect(2), --! Output of delay line
o_dff_q => o_dff_q,
i_D => "0000", --! DI for CARRY4 block
i_S => "1111", --! S for CARRY4 block
i_nReset => '1', --! Synchronous reset input for D-Flip-Flops
i_clock_enable => '1' --! Clock enable input for D-Flip-Flops
);
--! delay line No.3
--!
delay_line_inst_3 : ENTITY work.delay_line
GENERIC MAP(
g_DL_ELEMENT_COUNT => g_DL_ELEMENT_COUNT/g_DELAY_LINE_COUNT,
g_LOCATION => "SLICE_X42Y50"
)
PORT MAP(
i_clk => w_clk100, --! Main clock for D-Flip-Flops
i_trigger_in => w_delay_interconnect(2), --! Input of delay line
o_loop_out => w_delay_interconnect(3), --! Output of delay line
o_dff_q => o_dff_q,
i_D => "0000", --! DI for CARRY4 block
i_S => "1111", --! S for CARRY4 block
i_nReset => '1', --! Synchronous reset input for D-Flip-Flops
i_clock_enable => '1' --! Clock enable input for D-Flip-Flops
);
---------------------------------------------------------
-- reg-state logic --
---------------------------------------------------------
---------------------------------------------------------
-- next-state logic --
---------------------------------------------------------
END rtl;
|
-- This package contains support functions for standard codec building
--
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2015, <NAME> <EMAIL>
library vunit_lib;
context vunit_lib.vunit_context;
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_complex.all;
use ieee.numeric_bit.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
use ieee.float_pkg.all;
use std.textio.all;
package com_std_codec_builder_pkg is
type std_ulogic_array is array (integer range <>) of std_ulogic;
function to_byte_array (
constant value : bit_vector)
return string;
function from_byte_array (
constant byte_array : string)
return bit_vector;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out integer);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out real);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out time);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out boolean);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out bit);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out std_ulogic);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out severity_level);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out file_open_status);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out file_open_kind);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out character);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out std_ulogic_array);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out string);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out boolean_vector);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out bit_vector);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out integer_vector);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out real_vector);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out time_vector);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out std_ulogic_vector);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out complex);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out complex_polar);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_bit.unsigned);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_bit.signed);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_std.unsigned);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_std.signed);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ufixed);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out sfixed);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out float);
function encode_array_header (
constant range_left1 : string;
constant range_right1 : string;
constant is_ascending1 : string;
constant range_left2 : string := "";
constant range_right2 : string := "";
constant is_ascending2 : string := "T")
return string;
end package com_std_codec_builder_pkg;
package body com_std_codec_builder_pkg is
function to_byte_array (
constant value : bit_vector)
return string is
variable ret_val : string(1 to (value'length + 7) / 8);
variable value_int : ieee.numeric_bit.unsigned(value'length - 1 downto 0) := ieee.numeric_bit.unsigned(value);
begin
for i in ret_val'reverse_range loop
ret_val(i) := character'val(to_integer(value_int and to_unsigned(255, value_int'length)));
value_int := value_int srl 8;
end loop;
return ret_val;
end function to_byte_array;
function from_byte_array (
constant byte_array : string)
return bit_vector is
variable byte_array_int : string(1 to byte_array'length) := byte_array;
variable ret_val : bit_vector(byte_array'length*8-1 downto 0);
begin
for i in byte_array_int'range loop
ret_val((byte_array_int'length-i)*8 + 7 downto (byte_array_int'length-i)*8) := bit_vector(ieee.numeric_bit.to_unsigned(character'pos(byte_array_int(i)), 8));
end loop;
return ret_val;
end function from_byte_array;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out integer) is
begin
result := to_integer(ieee.numeric_bit.signed(from_byte_array(code(index to index + 3))));
index := index + 4;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out real) is
variable f64 : float64;
begin
result := to_real(to_float(to_slv(from_byte_array(code(index to index + 7))), f64));
index := index + 8;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out time) is
constant resolution : time := std.env.resolution_limit;
variable code_int : string(1 to 8) := code(index to index + 7);
variable r : time;
variable b : integer;
begin
-- @TODO assumes time is 8 bytes
r := resolution * 0;
for i in code_int'range loop
b := character'pos(code_int(i));
r := r * 256;
if i = 1 and b >= 128 then
b := b - 256;
end if;
r := r + b * resolution;
end loop;
index := index + 8;
result := r;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out boolean) is
begin
result := code(index) = 'T';
index := index + 1;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out bit) is
begin
if code(index) = '1' then
result := '1';
else
result := '0';
end if;
index := index + 1;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out std_ulogic) is
begin
result := std_ulogic'value("'" & code(index) & "'");
index := index + 1;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out severity_level) is
begin
result := severity_level'val(character'pos(code(index)));
index := index + 1;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out file_open_status) is
begin
result := file_open_status'val(character'pos(code(index)));
index := index + 1;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out file_open_kind) is
begin
result := file_open_kind'val(character'pos(code(index)));
index := index + 1;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out character) is
begin
result := code(index);
index := index + 1;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out std_ulogic_array) is
variable i : integer := result'left;
variable upper_nibble : natural;
begin
index := index + 9;
if result'ascending then
while i <= result'right loop
if i /= result'right then
upper_nibble := character'pos(code(index))/16;
result(i + 1) := std_ulogic'val(upper_nibble);
else
upper_nibble := 0;
end if;
result(i) := std_ulogic'val(character'pos(code(index)) - upper_nibble*16);
i := i + 2;
index := index + 1;
end loop;
else
while i >= result'right loop
if i /= result'right then
upper_nibble := character'pos(code(index))/16;
result(i - 1) := std_ulogic'val(upper_nibble);
else
upper_nibble := 0;
end if;
result(i) := std_ulogic'val(character'pos(code(index)) - upper_nibble*16);
i := i - 2;
index := index + 1;
end loop;
end if;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out string) is
begin
result := code(index + 9 to index + 9 + result'length - 1);
index := index + 9 + result'length;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out boolean_vector) is
variable result_bv : bit_vector(result'range);
begin
decode(code, index, result_bv);
for i in result'range loop
result(i) := result_bv(i) = '1';
end loop;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out bit_vector) is
constant n_bytes : natural := (result'length + 7) / 8;
variable result_temp : bit_vector(n_bytes * 8 - 1 downto 0);
begin
result_temp := from_byte_array(code(index + 9 to index + 9 + n_bytes - 1));
result := result_temp(result'length - 1 downto 0);
index := index + 9 + n_bytes;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out integer_vector) is
begin
index := index + 9;
for i in result'range loop
decode(code, index, result(i));
end loop;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out real_vector) is
begin
index := index + 9;
for i in result'range loop
decode(code, index, result(i));
end loop;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out time_vector) is
begin
index := index + 9;
for i in result'range loop
decode(code, index, result(i));
end loop;
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out std_ulogic_vector) is
variable result_sula : std_ulogic_array(result'range);
begin
decode(code, index, result_sula);
result := std_ulogic_vector(result_sula);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out complex) is
begin
decode(code, index, result.re);
decode(code, index, result.im);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out complex_polar) is
begin
decode(code, index, result.mag);
decode(code, index, result.arg);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_bit.unsigned) is
variable result_bv : bit_vector(result'range);
begin
decode(code, index, result_bv);
result := ieee.numeric_bit.unsigned(result_bv);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_bit.signed) is
variable result_bv : bit_vector(result'range);
begin
decode(code, index, result_bv);
result := ieee.numeric_bit.signed(result_bv);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_std.unsigned) is
variable result_slv : std_ulogic_vector(result'range);
begin
decode(code, index, result_slv);
result := ieee.numeric_std.unsigned(result_slv);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ieee.numeric_std.signed) is
variable result_slv : std_ulogic_vector(result'range);
begin
decode(code, index, result_slv);
result := ieee.numeric_std.signed(result_slv);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out ufixed) is
variable result_sula : std_ulogic_array(result'range);
begin
decode(code, index, result_sula);
result := ufixed(result_sula);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out sfixed) is
variable result_sula : std_ulogic_array(result'range);
begin
decode(code, index, result_sula);
result := sfixed(result_sula);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out float) is
variable result_sula : std_ulogic_array(result'range);
begin
decode(code, index, result_sula);
result := float(result_sula);
end;
function encode_array_header (
constant range_left1 : string;
constant range_right1 : string;
constant is_ascending1 : string;
constant range_left2 : string := "";
constant range_right2 : string := "";
constant is_ascending2 : string := "T")
return string is
begin
if range_left2 = "" then
return range_left1 & range_right1 & is_ascending1;
else
return range_left1 & range_right1 & is_ascending1 & range_left2 & range_right2 & is_ascending2;
end if;
end function encode_array_header;
end package body com_std_codec_builder_pkg;
|
-- bug fix 21.11.2005 : -added scaling of 2 before addition, and at the path of
-- multiplication of 1
-- new_implmentation 18.7.2005 : -added one pipeline stage between multipliers
-- -and adders.
-- bug fix 18.7.2005 : -moved register from output of multiplier to output
-- -of unit, to correspond opther units.
-- bug fix 8.8.2005 : - removed one extra register. now latency is always 3,
-- not 4 when starting multiplication.
-- bug fix 16.9.04 : - constant value "dout8" corrected
-- - bus tap dimensions after multiplication corrected
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity cmul is
generic (
DataW : integer := 32;
HalfW : integer := 16);
port(
clk : in std_logic;
--enable : IN std_logic;
operand : in std_logic_vector (DataW-1 downto 0);
rstx : in std_logic;
trigger : in std_logic_vector (DataW-1 downto 0);
result : out std_logic_vector (DataW-1 downto 0)
);
-- Declarations
end cmul;
architecture struct of cmul is
-- Architecture declarations
-- Internal signal declarations
signal dout : std_logic_vector(HalfW-1 downto 0);
signal dout1 : std_logic_vector(HalfW-1 downto 0);
signal dout2 : std_logic_vector(HalfW-1 downto 0);
signal dout3 : std_logic_vector(HalfW-1 downto 0);
signal dout4 : std_logic_vector(HalfW-1 downto 0);
signal dout5 : std_logic_vector(HalfW-1 downto 0);
signal dout6 : std_logic_vector(DataW-1 downto 0);
signal dout7 : std_logic_vector(DataW-1 downto 0);
signal dout8 : std_logic_vector(DataW-1 downto 0);
signal eq : std_logic;
signal i1 : std_logic_vector(HalfW-1 downto 0);
signal i2 : std_logic_vector(HalfW-1 downto 0);
signal prod : std_logic_vector(DataW-1 downto 0);
signal prod1 : std_logic_vector(DataW-1 downto 0);
signal prod2 : std_logic_vector(DataW-1 downto 0);
signal prod3 : std_logic_vector(DataW-1 downto 0);
signal r1 : std_logic_vector(HalfW-1 downto 0);
signal r2 : std_logic_vector(HalfW-1 downto 0);
-- ModuleWare signal declarations(v1.4) for instance 'I15' of 'adff'
--SIGNAL mw_I15reg_cval : std_logic_vector(DataW-1 DOWNTO 0);
-- ModuleWare signal declarations(v1.4) for instance 'I7' of 'split'
signal mw_I7temp_din : std_logic_vector(DataW-1 downto 0);
-- ModuleWare signal declarations(v1.4) for instance 'I8' of 'split'
signal mw_I8temp_din : std_logic_vector(DataW-1 downto 0);
begin
-- ModuleWare code(v1.4) for instance 'I14' of 'add'
I14combo_proc : process (dout2, dout3)
variable temp_din0 : std_logic_vector(HalfW downto 0);
variable temp_din1 : std_logic_vector(HalfW downto 0);
variable sum : signed(HalfW downto 0);
variable carry : std_logic;
begin
temp_din0 := dout2(HalfW-1) & dout2;
temp_din1 := dout3(HalfW-1) & dout3;
carry := '0';
sum := signed(temp_din0) + signed(temp_din1) + carry;
dout5 <= conv_std_logic_vector(sum(HalfW-1 downto 0), HalfW);
end process I14combo_proc;
-- ModuleWare code(v1.4) for instance 'I15' of 'adff'
result <= dout7;
-- ModuleWare code(v1.4) for instance 'I16' of 'cmp'
I16combo_proc : process (trigger, dout8)
variable leq : std_logic;
begin
leq := '0';
if (signed(trigger) = signed(dout8)) then
leq := '1';
end if;
eq <= not(leq);
end process I16combo_proc;
-- ModuleWare code(v1.4) for instance 'I17' of 'constval'
dout8 <= "01111111111111110000000000000000";
-- ModuleWare code(v1.4) for instance 'I19' of 'merge'
dout6 <= dout4 & dout5;
-- ModuleWare code(v1.4) for instance 'I0' of 'mult'
I0combo_proc : process (r1, r2)
--VARIABLE temp_in_prod : signed(DataW-1 DOWNTO 0);
begin
--temp_in_prod := (signed(r1) * signed(r2));
--prod <= std_logic_vector(temp_in_prod);
prod <= sxt(conv_std_logic_vector(signed(r1) * signed(r2), prod'length)(DataW-1 downto 1), prod'length);
--prod <= sxt(conv_std_logic_vector(signed(r1) * signed(r2),prod'length-1),prod'length);
end process I0combo_proc;
-- ModuleWare code(v1.4) for instance 'I1' of 'mult'
I1combo_proc : process (i1, i2)
--VARIABLE temp_in_prod : signed(DataW-1 DOWNTO 0);
begin
--temp_in_prod := (signed(i1) * signed(i2));
--prod1 <= std_logic_vector(temp_in_prod);
--prod1 <= sxt(conv_std_logic_vector(signed(i1) * signed(i2),prod1'length-1),prod1'length);
prod1 <= sxt(conv_std_logic_vector(signed(i1) * signed(i2), prod1'length)(DataW-1 downto 1), prod1'length);
end process I1combo_proc;
-- ModuleWare code(v1.4) for instance 'I2' of 'mult'
I2combo_proc : process (r1, i2)
--VARIABLE temp_in_prod : signed(DataW-1 DOWNTO 0);
begin
--temp_in_prod := (signed(r1) * signed(i2));
--prod2 <= std_logic_vector(temp_in_prod);
--prod2 <= sxt(conv_std_logic_vector(signed(r1) * signed(i2),prod2'length-1),prod2'length);
prod2 <= sxt(conv_std_logic_vector(signed(r1) * signed(i2), prod2'length)(DataW-1 downto 1), prod2'length);
end process I2combo_proc;
-- ModuleWare code(v1.4) for instance 'I3' of 'mult'
I3combo_proc : process (i1, r2)
--VARIABLE temp_in_prod : signed(DataW-1 DOWNTO 0);
begin
--temp_in_prod := (signed(i1) * signed(r2));
--prod3 <= std_logic_vector(temp_in_prod);
--prod3 <= sxt(conv_std_logic_vector(signed(i1) * signed(r2),prod3'length-1),prod3'length);
prod3 <= sxt(conv_std_logic_vector(signed(i1) * signed(r2), prod3'length)(DataW-1 downto 1), prod3'length);
end process I3combo_proc;
-- ModuleWare code(v1.4) for instance 'I18' of 'mux'
I18combo_proc : process(operand, dout6, eq)
begin
case eq is
-- if the operand is passed through straighlty
-- operand must be divided by 2(extend sign and shift one to left)
when '0'|'L' => dout7 <=
operand(dataw-1 downto dataw-1) &
operand(dataw-1 downto dataw/2+1) &
operand(dataw/2-1 downto dataw/2-1)&
operand(dataw/2-1 downto 1);
when '1'|'H' => dout7 <= dout6;
when others => dout7 <= (others => 'X');
end case;
end process I18combo_proc;
-- ModuleWare code(v1.4) for instance 'I7' of 'split'
mw_I7temp_din <= trigger;
I7combo_proc : process (mw_I7temp_din)
variable itemp : std_logic_vector(DataW-1 downto 0);
begin
itemp := mw_I7temp_din(DataW-1 downto 0);
i1 <= itemp(HalfW-1 downto 0);
r1 <= itemp(DataW-1 downto HalfW);
end process I7combo_proc;
-- ModuleWare code(v1.4) for instance 'I8' of 'split'
mw_I8temp_din <= operand;
I8combo_proc : process (mw_I8temp_din)
variable itemp : std_logic_vector(DataW-1 downto 0);
begin
itemp := mw_I8temp_din(DataW-1 downto 0);
i2 <= itemp(HalfW-1 downto 0);
r2 <= itemp(DataW-1 downto HalfW);
end process I8combo_proc;
-- ModuleWare code(v1.4) for instance 'I13' of 'sub'
I13combo_proc : process (dout, dout1)
variable temp_din0 : std_logic_vector(HalfW downto 0);
variable temp_din1 : std_logic_vector(HalfW downto 0);
variable diff : signed(HalfW downto 0);
variable borrow : std_logic;
begin
temp_din0 := dout(HalfW-1) & dout;
temp_din1 := dout1(HalfW-1) & dout1;
borrow := '0';
diff := signed(temp_din0) - signed(temp_din1) - borrow;
dout4 <= conv_std_logic_vector(diff(HalfW-1 downto 0), HalfW);
end process I13combo_proc;
-- ModuleWare code(v1.4) for instance 'I9' of 'tap'
dout <= prod(DataW-2 downto HalfW-1);
-- ModuleWare code(v1.4) for instance 'I10' of 'tap'
dout1 <= prod1(DataW-2 downto HalfW-1);
-- ModuleWare code(v1.4) for instance 'I11' of 'tap'
dout2 <= prod2(DataW-2 downto HalfW-1);
-- ModuleWare code(v1.4) for instance 'I12' of 'tap'
dout3 <= prod3(DataW-2 downto HalfW-1);
-- Instance port mappings.
end struct;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity cmul_pipeline_2 is
generic (
DataW : integer := 32;
HalfW : integer := 16);
port(
clk : in std_logic;
enable : in std_logic;
operand : in std_logic_vector (DataW-1 downto 0);
rstx : in std_logic;
trigger : in std_logic_vector (DataW-1 downto 0);
result : out std_logic_vector (DataW-1 downto 0)
);
-- Declarations
end cmul_pipeline_2;
architecture struct of cmul_pipeline_2 is
-- Architecture declarations
-- Internal signal declarations
signal dout : std_logic_vector(HalfW-1 downto 0);
signal dout1 : std_logic_vector(HalfW-1 downto 0);
signal dout2 : std_logic_vector(HalfW-1 downto 0);
signal dout3 : std_logic_vector(HalfW-1 downto 0);
signal dout4 : std_logic_vector(HalfW-1 downto 0);
signal dout5 : std_logic_vector(HalfW-1 downto 0);
signal dout6 : std_logic_vector(DataW-1 downto 0);
signal dout7 : std_logic_vector(DataW-1 downto 0);
signal dout8 : std_logic_vector(DataW-1 downto 0);
signal eq : std_logic;
signal i1 : std_logic_vector(HalfW-1 downto 0);
signal i2 : std_logic_vector(HalfW-1 downto 0);
signal prod : std_logic_vector(DataW-1 downto 0);
signal prod1 : std_logic_vector(DataW-1 downto 0);
signal prod2 : std_logic_vector(DataW-1 downto 0);
signal prod3 : std_logic_vector(DataW-1 downto 0);
signal r1 : std_logic_vector(HalfW-1 downto 0);
signal r2 : std_logic_vector(HalfW-1 downto 0);
signal operand_reg : std_logic_vector(DataW-1 downto 0);
signal temp : std_logic_vector(DataW-1 downto 0);
signal temp1 : std_logic_vector(DataW-1 downto 0);
signal temp2 : std_logic_vector(DataW-1 downto 0);
signal temp3 : std_logic_vector(DataW-1 downto 0);
-- ModuleWare signal declarations(v1.4) for instance 'I15' of 'adff'
--SIGNAL mw_I15reg_cval : std_logic_vector(DataW-1 DOWNTO 0);
-- ModuleWare signal declarations(v1.4) for instance 'I7' of 'split'
signal mw_I7temp_din : std_logic_vector(DataW-1 downto 0);
-- ModuleWare signal declarations(v1.4) for instance 'I8' of 'split'
signal mw_I8temp_din : std_logic_vector(DataW-1 downto 0);
begin
-- ModuleWare code(v1.4) for instance 'I14' of 'add'
I14combo_proc : process (dout2, dout3)
variable temp_din0 : std_logic_vector(HalfW downto 0);
variable temp_din1 : std_logic_vector(HalfW downto 0);
variable sum : signed(HalfW downto 0);
variable carry : std_logic;
begin
temp_din0 := dout2(HalfW-1) & dout2;
temp_din1 := dout3(HalfW-1) & dout3;
carry := '0';
sum := signed(temp_din0) + signed(temp_din1) + carry;
dout5 <= conv_std_logic_vector(sum(HalfW-1 downto 0), HalfW);
end process I14combo_proc;
-- ModuleWare code(v1.4) for instance 'I15' of 'adff'
result <= dout7;
-- ModuleWare code(v1.4) for instance 'I16' of 'cmp'
--I16combo_proc : PROCESS (trigger, dout8)
--VARIABLE leq : std_logic;
--BEGIN
-- leq := '0';
-- IF (signed(trigger) = signed(dout8)) THEN
-- leq := '1';
-- END IF;
-- eq <= NOT(leq);
--END PROCESS I16combo_proc;
-- ModuleWare code(v1.4) for instance 'I17' of 'constval'
dout8 <= "01111111111111110000000000000000";
-- ModuleWare code(v1.4) for instance 'I19' of 'merge'
dout6 <= dout4 & dout5;
-- ModuleWare code(v1.4) for instance 'I0' of 'mult'
I0combo_proc : process (r1, r2)
--VARIABLE temp_in_prod : std_logic_vector(DataW-1 DOWNTO 0);
begin
--temp_in_prod := conv_std_logic_vector(signed(r1) * signed(r2),temp_in_prod'length);
prod <= sxt(conv_std_logic_vector(signed(r1) * signed(r2), prod'length)(DataW-1 downto 1), prod'length);
end process I0combo_proc;
-- ModuleWare code(v1.4) for instance 'I1' of 'mult'
I1combo_proc : process (i1, i2)
--VARIABLE temp_in_prod : std_logic_vector(DataW-1 DOWNTO 0);
begin
--temp_in_prod := conv_std_logic_vector(signed(i1) * signed(i2),temp_in_prod'length);
--prod1 <= sxt(temp_in_prod(DataW-1 downto 0),prod1'length);
prod1 <= sxt(conv_std_logic_vector(signed(i1) * signed(i2), prod1'length)(DataW-1 downto 1), prod1'length);
end process I1combo_proc;
-- ModuleWare code(v1.4) for instance 'I2' of 'mult'
I2combo_proc : process (r1, i2)
--VARIABLE temp_in_prod : signed(DataW-1 DOWNTO 0);
begin
--temp_in_prod := (signed(r1) * signed(i2));
--prod2 <= std_logic_vector(temp_in_prod);
--prod2 <= sxt(conv_std_logic_vector(signed(r1) * signed(i2),prod2'length-1),prod2'length);
prod2 <= sxt(conv_std_logic_vector(signed(r1) * signed(i2), prod2'length)(DataW-1 downto 1), prod2'length);
end process I2combo_proc;
-- ModuleWare code(v1.4) for instance 'I3' of 'mult'
I3combo_proc : process (i1, r2)
--VARIABLE temp_in_prod : signed(DataW-1 DOWNTO 0);
begin
--temp_in_prod := (signed(i1) * signed(r2));
--prod3 <= std_logic_vector(temp_in_prod);
--prod3 <= sxt(conv_std_logic_vector(signed(i1) * signed(r2),prod3'length-1),prod3'length);
prod3 <= sxt(conv_std_logic_vector(signed(i1) * signed(r2), prod3'length)(DataW-1 downto 1), prod3'length);
end process I3combo_proc;
-- ModuleWare code(v1.4) for instance 'I18' of 'mux'
I18combo_proc : process(operand_reg, dout6, eq)
begin
case eq is
-- if the operand is passed through straighlty
-- real part and imaginary part of
-- operand must be divided by 2(extend sign and shift one to left)
when '0'|'L' =>
dout7 <= operand_reg(dataw-1 downto dataw-1) &
operand_reg(dataw-1 downto dataw/2+1) &
operand_reg(dataw/2-1 downto dataw/2-1) &
operand_reg(dataw/2-1 downto 1);
when '1'|'H' => dout7 <= dout6;
when others => dout7 <= (others => 'X');
end case;
end process I18combo_proc;
-- ModuleWare code(v1.4) for instance 'I7' of 'split'
mw_I7temp_din <= trigger;
I7combo_proc : process (mw_I7temp_din)
variable itemp : std_logic_vector(DataW-1 downto 0);
begin
itemp := mw_I7temp_din(DataW-1 downto 0);
i1 <= itemp(HalfW-1 downto 0);
r1 <= itemp(DataW-1 downto HalfW);
end process I7combo_proc;
-- ModuleWare code(v1.4) for instance 'I8' of 'split'
mw_I8temp_din <= operand;
I8combo_proc : process (mw_I8temp_din)
variable itemp : std_logic_vector(DataW-1 downto 0);
begin
itemp := mw_I8temp_din(DataW-1 downto 0);
i2 <= itemp(HalfW-1 downto 0);
r2 <= itemp(DataW-1 downto HalfW);
end process I8combo_proc;
-- ModuleWare code(v1.4) for instance 'I13' of 'sub'
I13combo_proc : process (dout, dout1)
variable temp_din0 : std_logic_vector(HalfW downto 0);
variable temp_din1 : std_logic_vector(HalfW downto 0);
variable diff : signed(HalfW downto 0);
variable borrow : std_logic;
begin
temp_din0 := dout(HalfW-1) & dout;
temp_din1 := dout1(HalfW-1) & dout1;
borrow := '0';
diff := signed(temp_din0) - signed(temp_din1) - borrow;
dout4 <= conv_std_logic_vector(diff(HalfW-1 downto 0), HalfW);
end process I13combo_proc;
pipeline_stage : process (clk, rstx)
begin -- process pipeline_stage
if rstx = '0' then -- asynchronous reset (active low)
dout <= (others => '0');
dout1 <= (others => '0');
dout2 <= (others => '0');
dout3 <= (others => '0');
operand_reg <= (others => '0');
eq <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if (enable = '1' or enable = 'H') then
dout <= prod(DataW-2 downto HalfW-1);
dout1 <= prod1(DataW-2 downto HalfW-1);
dout2 <= prod2(DataW-2 downto HalfW-1);
dout3 <= prod3(DataW-2 downto HalfW-1);
operand_reg <= operand;
if (signed(trigger) = signed(dout8)) then
eq <= '0';
else
eq <= '1';
end if;
end if;
end if;
end process pipeline_stage;
-- ModuleWare code(v1.4) for instance 'I9' of 'tap'
--dout <= prod(DataW-2 DOWNTO HalfW-1);
-- ModuleWare code(v1.4) for instance 'I10' of 'tap'
--dout1 <= prod1(DataW-2 DOWNTO HalfW-1);
-- ModuleWare code(v1.4) for instance 'I11' of 'tap'
--dout2 <= prod2(DataW-2 DOWNTO HalfW-1);
-- ModuleWare code(v1.4) for instance 'I12' of 'tap'
--dout3 <= prod3(DataW-2 DOWNTO HalfW-1);
-- Instance port mappings.
end struct;
-------------------------------------------------------------------------------
-- 3 clock cycles
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fu_cmul_always_3 is
generic (
DataW : integer := 32;
HalfW : integer := 16);
port (
clk : in std_logic;
rstx : in std_logic;
t1data : in std_logic_vector(DataW-1 downto 0);
o1data : in std_logic_vector(DataW-1 downto 0);
t1load : in std_logic;
o1load : in std_logic;
r1data : out std_logic_vector(DataW-1 downto 0);
glock : in std_logic);
end fu_cmul_always_3;
architecture rtl of fu_cmul_always_3 is
component cmul_pipeline_2
generic (
DataW : integer;
HalfW : integer);
port (
clk : in std_logic;
rstx : in std_logic;
enable : in std_logic;
trigger : in std_logic_vector (DataW-1 downto 0);
operand : in std_logic_vector (DataW-1 downto 0);
result : out std_logic_vector (DataW-1 downto 0));
end component;
signal t1reg : std_logic_vector (DataW-1 downto 0);
signal o1reg : std_logic_vector (DataW-1 downto 0);
signal r1reg : std_logic_vector (DataW-1 downto 0);
signal result_en_reg : std_logic_vector(1 downto 0);
signal control : std_logic_vector(1 downto 0);
signal r1 : std_logic_vector(DataW-1 downto 0);
begin -- rtl
fu_core : cmul_pipeline_2
generic map (
DataW => DataW,
HalfW => HalfW)
port map (
clk => clk,
rstx => rstx,
enable => result_en_reg(0),
operand => o1reg,
trigger => t1reg,
result => r1);
control <= o1load&t1load;
regs : process (clk, rstx)
begin -- process regs
if rstx = '0' then -- asynchronous reset (active low)
t1reg <= (others => '0');
o1reg <= (others => '0');
result_en_reg <= (others => '0');
r1reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if (glock = '0') then
case control is
when "11" =>
t1reg <= t1data;
o1reg <= o1data;
when "10" =>
o1reg <= o1data;
when "01" =>
t1reg <= t1data;
when others => null;
end case;
-- update result only when a new operation was triggered
--result_en_reg <= t1load;
-- update result eneable register when t1load is active
-- add one register for pipeline register control and
-- second register for result control
result_en_reg(1) <= result_en_reg(0);
result_en_reg(0) <= t1load;
if result_en_reg(1) = '1' then
r1reg <= r1;
end if;
end if;
end if;
end process regs;
r1data <= r1reg;
--r1data <= r1;
end rtl;
-------------------------------------------------------------------------------
-- 2 clock cycles
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fu_cmul_always_2 is
generic (
DataW : integer := 32;
HalfW : integer := 16);
port (
clk : in std_logic;
rstx : in std_logic;
t1data : in std_logic_vector(DataW-1 downto 0);
o1data : in std_logic_vector(DataW-1 downto 0);
t1load : in std_logic;
o1load : in std_logic;
r1data : out std_logic_vector(DataW-1 downto 0);
glock : in std_logic);
end fu_cmul_always_2;
architecture rtl of fu_cmul_always_2 is
component cmul
generic (
DataW : integer;
HalfW : integer);
port (
clk : in std_logic;
rstx : in std_logic;
--enable : IN std_logic;
trigger : in std_logic_vector (DataW-1 downto 0);
operand : in std_logic_vector (DataW-1 downto 0);
result : out std_logic_vector (DataW-1 downto 0));
end component;
signal t1reg : std_logic_vector (DataW-1 downto 0);
signal o1reg : std_logic_vector (DataW-1 downto 0);
signal r1reg : std_logic_vector (DataW-1 downto 0);
signal result_en_reg : std_logic;
signal control : std_logic_vector(1 downto 0);
signal r1 : std_logic_vector(DataW-1 downto 0);
begin -- rtl
fu_core : cmul
generic map (
DataW => DataW,
HalfW => HalfW)
port map (
clk => clk,
rstx => rstx,
--enable => result_en_reg(1),
operand => o1reg,
trigger => t1reg,
result => r1);
control <= o1load&t1load;
regs : process (clk, rstx)
begin -- process regs
if rstx = '0' then -- asynchronous reset (active low)
t1reg <= (others => '0');
o1reg <= (others => '0');
r1reg <= (others => '0');
result_en_reg <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if (glock = '0') then
case control is
when "11" =>
t1reg <= t1data;
o1reg <= o1data;
when "10" =>
o1reg <= o1data;
when "01" =>
t1reg <= t1data;
when others => null;
end case;
-- update result only when a new operation was triggered
result_en_reg <= t1load;
if result_en_reg = '1' then
r1reg <= r1;
end if;
end if;
end if;
end process regs;
r1data <= r1reg;
--r1data <= r1;
end rtl;
|
<reponame>shaeon/Learn-FPGA-Programming<filename>CH9/build/IP/pix_clk/proc_common_v3_00_a/hdl/src/vhdl/pix_clk_soft_reset.vhd
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: <NAME>
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity pix_clk_soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end pix_clk_soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of pix_clk_soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
<filename>rtl/bus/apb/nf_apb_gpio.vhd
--
-- File : nf_apb_gpio.vhd
-- Autor : <NAME>.
-- Data : 2019.11.29
-- Language : VHDL
-- Description : This is APB GPIO module
-- Copyright(c) : 2019 <NAME>.
--
library ieee;
use ieee.std_logic_1164.all;
library nf;
use nf.nf_settings.all;
use nf.nf_ahb_pkg.all;
use nf.nf_help_pkg.all;
use nf.nf_components.all;
entity nf_apb_gpio is
generic
(
gpio_w : integer := NF_GPIO_WIDTH;
apb_addr_w : integer
);
port
(
-- clock and reset
pclk : in std_logic; -- pclock
presetn : in std_logic; -- presetn
-- APB GPIO slave side
paddr_s : in std_logic_vector(apb_addr_w-1 downto 0); -- APB - GPIO-slave PADDR
pwdata_s : in std_logic_vector(31 downto 0); -- APB - GPIO-slave PWDATA
prdata_s : out std_logic_vector(31 downto 0); -- APB - GPIO-slave PRDATA
pwrite_s : in std_logic; -- APB - GPIO-slave PWRITE
psel_s : in std_logic; -- APB - GPIO-slave PSEL
penable_s : in std_logic; -- APB - GPIO-slave PENABLE
pready_s : out std_logic; -- APB - GPIO-slave PREADY
-- GPIO side
gpi : in std_logic_vector(gpio_w-1 downto 0); -- GPIO input
gpo : out std_logic_vector(gpio_w-1 downto 0); -- GPIO output
gpd : out std_logic_vector(gpio_w-1 downto 0) -- GPIO direction
);
end nf_apb_gpio;
architecture rtl of nf_apb_gpio is
signal pready_ff : std_logic_vector(0 downto 0);
signal psel_slv : std_logic_vector(0 downto 0);
signal addr : std_logic_vector(31 downto 0); -- address for gpio module
signal rd : std_logic_vector(31 downto 0); -- read data from gpio module
signal wd : std_logic_vector(31 downto 0); -- write data for gpio module
signal we : std_logic; -- write enable for gpio module
begin
addr <= ( 31 downto (paddr_s'left+1) => '0' ) & paddr_s;
we <= pwrite_s and penable_s and psel_s;
wd <= pwdata_s;
prdata_s <= rd;
psel_slv(0) <= psel_s;
pready_s <= pready_ff(0);
pready_reg : nf_register generic map( 1 ) port map ( pclk, presetn, psel_slv, pready_ff );
-- creating one nf_gpio unit
nf_gpio_0 : nf_gpio
generic map
(
gpio_w => gpio_w
)
port map
(
-- reset and clock
clk => pclk, -- clk
resetn => presetn, -- resetn
-- bus side
addr => addr, -- address
we => we, -- write enable
wd => wd, -- write data
rd => rd, -- read data
-- GPIO side
gpi => gpi, -- GPIO input
gpo => gpo, -- GPIO output
gpd => gpd -- GPIO direction
);
end rtl; -- nf_apb_gpio
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity ha is
port(
a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic
);
end ha;
architecture behavior of ha is
begin
s <= a xor b;
c <= a and b;
end architecture;
|
<gh_stars>0
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2019.2.1
-- Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xfExtractPixels is
port (
ap_ready : OUT STD_LOGIC;
tmp_buf_0_V_read : IN STD_LOGIC_VECTOR (23 downto 0);
tmp_buf_1_V_read : IN STD_LOGIC_VECTOR (23 downto 0);
tmp_buf_2_V_read : IN STD_LOGIC_VECTOR (23 downto 0);
tmp_buf_3_V_read : IN STD_LOGIC_VECTOR (23 downto 0);
val1_V_read : IN STD_LOGIC_VECTOR (23 downto 0);
pos_r : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (23 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (23 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (23 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (23 downto 0) );
end;
architecture behav of xfExtractPixels is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_logic_0 : STD_LOGIC := '0';
signal zext_ln321_fu_60_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal write_flag_fu_64_p6 : STD_LOGIC_VECTOR (0 downto 0);
signal write_flag4_fu_78_p6 : STD_LOGIC_VECTOR (0 downto 0);
signal write_flag8_fu_106_p6 : STD_LOGIC_VECTOR (0 downto 0);
signal write_flag1_fu_92_p6 : STD_LOGIC_VECTOR (0 downto 0);
signal select_ln78_fu_120_p3 : STD_LOGIC_VECTOR (23 downto 0);
signal select_ln78_1_fu_128_p3 : STD_LOGIC_VECTOR (23 downto 0);
signal select_ln78_2_fu_136_p3 : STD_LOGIC_VECTOR (23 downto 0);
signal select_ln78_3_fu_144_p3 : STD_LOGIC_VECTOR (23 downto 0);
component ip_accel_app_mux_bdk IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (0 downto 0);
din1 : IN STD_LOGIC_VECTOR (0 downto 0);
din2 : IN STD_LOGIC_VECTOR (0 downto 0);
din3 : IN STD_LOGIC_VECTOR (0 downto 0);
din4 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
ip_accel_app_mux_bdk_U559 : component ip_accel_app_mux_bdk
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 1,
din1_WIDTH => 1,
din2_WIDTH => 1,
din3_WIDTH => 1,
din4_WIDTH => 2,
dout_WIDTH => 1)
port map (
din0 => ap_const_lv1_1,
din1 => ap_const_lv1_0,
din2 => ap_const_lv1_0,
din3 => ap_const_lv1_0,
din4 => zext_ln321_fu_60_p1,
dout => write_flag_fu_64_p6);
ip_accel_app_mux_bdk_U560 : component ip_accel_app_mux_bdk
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 1,
din1_WIDTH => 1,
din2_WIDTH => 1,
din3_WIDTH => 1,
din4_WIDTH => 2,
dout_WIDTH => 1)
port map (
din0 => ap_const_lv1_0,
din1 => ap_const_lv1_1,
din2 => ap_const_lv1_0,
din3 => ap_const_lv1_0,
din4 => zext_ln321_fu_60_p1,
dout => write_flag4_fu_78_p6);
ip_accel_app_mux_bdk_U561 : component ip_accel_app_mux_bdk
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 1,
din1_WIDTH => 1,
din2_WIDTH => 1,
din3_WIDTH => 1,
din4_WIDTH => 2,
dout_WIDTH => 1)
port map (
din0 => ap_const_lv1_0,
din1 => ap_const_lv1_0,
din2 => ap_const_lv1_0,
din3 => ap_const_lv1_1,
din4 => zext_ln321_fu_60_p1,
dout => write_flag1_fu_92_p6);
ip_accel_app_mux_bdk_U562 : component ip_accel_app_mux_bdk
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 1,
din1_WIDTH => 1,
din2_WIDTH => 1,
din3_WIDTH => 1,
din4_WIDTH => 2,
dout_WIDTH => 1)
port map (
din0 => ap_const_lv1_0,
din1 => ap_const_lv1_0,
din2 => ap_const_lv1_1,
din3 => ap_const_lv1_0,
din4 => zext_ln321_fu_60_p1,
dout => write_flag8_fu_106_p6);
ap_ready <= ap_const_logic_1;
ap_return_0 <= select_ln78_fu_120_p3;
ap_return_1 <= select_ln78_1_fu_128_p3;
ap_return_2 <= select_ln78_2_fu_136_p3;
ap_return_3 <= select_ln78_3_fu_144_p3;
select_ln78_1_fu_128_p3 <=
val1_V_read when (write_flag4_fu_78_p6(0) = '1') else
tmp_buf_1_V_read;
select_ln78_2_fu_136_p3 <=
val1_V_read when (write_flag8_fu_106_p6(0) = '1') else
tmp_buf_2_V_read;
select_ln78_3_fu_144_p3 <=
val1_V_read when (write_flag1_fu_92_p6(0) = '1') else
tmp_buf_3_V_read;
select_ln78_fu_120_p3 <=
val1_V_read when (write_flag_fu_64_p6(0) = '1') else
tmp_buf_0_V_read;
zext_ln321_fu_60_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(pos_r),2));
end behav;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design full system
-- Project :
-------------------------------------------------------------------------------
-- File : cryo_tb.vhd
-- Author : <NAME> <<EMAIL>>
-- Company :
-- Created : 2017-05-22
-- Last update: 2019-07-24
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library STD;
use STD.textio.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.all;
use work.StdRtlPkg.all;
use work.AxiStreamPkg.all;
use work.EpixHrCorePkg.all;
use work.AxiLitePkg.all;
use work.AxiPkg.all;
use work.Pgp2bPkg.all;
use work.SsiPkg.all;
use work.SsiCmdMasterPkg.all;
use work.HrAdcPkg.all;
use work.Code8b10bPkg.all;
use work.AppPkg.all;
use work.BuildInfoPkg.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity cryo_dune_tb is
generic (
TPD_G : time := 1 ns;
BUILD_INFO_G : BuildInfoType := BUILD_INFO_C;
IDLE_PATTERN_C : slv(11 downto 0) := x"03F" -- "11 0100 0000 0111"
);
end cryo_dune_tb;
-------------------------------------------------------------------------------
architecture arch of cryo_dune_tb is
--file definitions
constant DATA_BITS : natural := 12;
constant DEPTH_C : natural := 1024;
constant FILENAME_C : string := "/afs/slac.stanford.edu/u/re/ddoering/localGit/epix-hr-dev/firmware/simulations/CryoEncDec/sin.csv";
--simulation constants to select data type
constant CH_ID : natural := 0;
constant CH_WF : natural := 1;
constant DATA_TYPE_C : natural := CH_ID;
subtype word_t is slv(DATA_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH_C - 1) of word_t;
impure function readWaveFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : integer; --slv(DATA_BITS - 1 downto 0);
variable TempWordSlv : slv(16 - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
for i in 0 to DEPTH_C - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
read(CurrentLine, TempWord);
TempWordSlv := toSlv(TempWord, 16);
Result(i) := TempWordSlv(15 downto 16 - DATA_BITS);
end loop;
return Result;
end function;
-- waveform signal
signal ramWaveform : ram_t := readWaveFile(FILENAME_C);
signal ramTestWaveform : ram_t := readWaveFile(FILENAME_C);
-----------------------------------------------------------------------------
-- Signals to mimic top module io
-----------------------------------------------------------------------------
-----------------------
-- Application Ports --
-----------------------
-- System Ports
signal digPwrEn : sl;
signal anaPwrEn : sl;
signal syncDigDcDc : sl;
signal syncAnaDcDc : sl;
signal syncDcDc : slv(6 downto 0);
signal daqTg : sl;
signal connTgOut : sl;
signal connMps : sl;
signal connRun : sl;
-- Fast ADC Ports
signal adcSpiClk : sl;
signal adcSpiData : sl;
signal adcSpiCsL : sl;
signal adcPdwn : sl;
signal adcClkP : sl;
signal adcClkM : sl;
signal adcDoClkP : sl;
signal adcDoClkM : sl;
signal adcFrameClkP : sl;
signal adcFrameClkM : sl;
signal adcMonDoutP : slv(4 downto 0);
signal adcMonDoutN : slv(4 downto 0);
-- Slow ADC
signal slowAdcSclk : sl;
signal slowAdcDin : sl;
signal slowAdcCsL : sl;
signal slowAdcRefClk : sl;
signal slowAdcDout : sl;
signal slowAdcDrdy : sl;
signal slowAdcSync : sl;
-- Slow DACs Port
signal sDacCsL : slv(4 downto 0);
signal hsDacCsL : sl;
signal hsDacLoad : sl;
signal dacClrL : sl;
signal dacSck : sl;
signal dacDin : sl;
-- ASIC Gbps Ports
signal asicDataP : slv(23 downto 0);
signal asicDataN : slv(23 downto 0);
-- ASIC Control Ports
signal asicR0 : sl;
signal asicSamClkEn : sl;
signal asicPpmat : sl;
signal asicGlblRst : sl;
signal asicSync : sl;
signal asicAcq : sl;
signal asicRoClkP : slv(3 downto 0);
signal asicRoClkN : slv(3 downto 0);
-- SACI Ports
signal asicSaciCmd : sl;
signal asicSaciClk : sl;
signal asicSaciSel : slv(3 downto 0);
signal asicSaciRsp : sl;
-- Spare Ports
signal spareHpP : slv(11 downto 0);
signal spareHpN : slv(11 downto 0);
signal spareHrP : slv(5 downto 0);
signal spareHrN : slv(5 downto 0);
-- GTH Ports
signal gtRxP : sl;
signal gtRxN : sl;
signal gtTxP : sl;
signal gtTxN : sl;
signal gtRefP : sl;
signal gtRefN : sl;
signal smaRxP : sl;
signal smaRxN : sl;
signal smaTxP : sl;
signal smaTxN : sl;
----------------
-- Core Ports --
----------------
-- Board IDs Ports
signal snIoAdcCard : sl;
signal snIoCarrier : sl;
-- QSFP Ports
signal qsfpRxP : slv(3 downto 0);
signal qsfpRxN : slv(3 downto 0);
signal qsfpTxP : slv(3 downto 0);
signal qsfpTxN : slv(3 downto 0);
signal qsfpClkP : sl := '1';
signal qsfpClkN : sl;
signal qsfpLpMode : sl;
signal qsfpModSel : sl;
signal qsfpInitL : sl;
signal qsfpRstL : sl;
signal qsfpPrstL : sl;
signal qsfpScl : sl;
signal qsfpSda : sl;
-- DDR Ports
signal ddrClkP : sl := '1';
signal ddrClkN : sl;
signal ddrBg : sl;
signal ddrCkP : sl;
signal ddrCkN : sl;
signal ddrCke : sl;
signal ddrCsL : sl;
signal ddrOdt : sl;
signal ddrAct : sl;
signal ddrRstL : sl;
signal ddrA : slv(16 downto 0);
signal ddrBa : slv(1 downto 0);
signal ddrDm : slv(3 downto 0);
signal ddrDq : slv(31 downto 0);
signal ddrDqsP : slv(3 downto 0);
signal ddrDqsN : slv(3 downto 0);
signal ddrPg : sl;
signal ddrPwrEn : sl;
-- SYSMON Ports
signal vPIn : sl;
signal vNIn : sl;
-----------------------------------------------------------------------------
-- Signals to communicate among app and core
-----------------------------------------------------------------------------
-- System Clock and Reset
signal sysClk : sl;
signal sysRst : sl;
signal sysRst_n : sl;
-- AXI-Lite Register Interface (sysClk domain)
signal axilReadMaster : AxiLiteReadMasterType;
signal axilReadSlave : AxiLiteReadSlaveType;
signal axilWriteMaster : AxiLiteWriteMasterType;
signal axilWriteSlave : AxiLiteWriteSlaveType;
-- AXI Stream, one per QSFP lane (sysClk domain)
signal axisMasters : AxiStreamMasterArray(3 downto 0);
signal axisSlaves : AxiStreamSlaveArray(3 downto 0);
-- Auxiliary AXI Stream, (sysClk domain)
signal sAuxAxisMasters : AxiStreamMasterArray(1 downto 0);
signal sAuxAxisSlaves : AxiStreamSlaveArray(1 downto 0);
-- ssi commands (Lane and Vc 0)
signal ssiCmd : SsiCmdMasterType;
-- DDR's AXI Memory Interface (sysClk domain)
signal axiReadMaster : AxiReadMasterType;
signal axiReadSlave : AxiReadSlaveType;
signal axiWriteMaster : AxiWriteMasterType;
signal axiWriteSlave : AxiWriteSlaveType;
-- Microblaze's Interrupt bus (sysClk domain)
signal mbIrq : slv(7 downto 0);
-- encoder
signal EncValidIn : sl := '1';
signal EncReadyIn : sl;
signal EncDataIn : slv(11 downto 0);
signal EncDispIn : slv(1 downto 0) := "00";
signal EncDataKIn : sl;
signal EncValidOut : sl;
signal EncReadyOut : sl := '1';
signal EncDataOut : slv(13 downto 0);
signal EncDataOut_d: Slv14Array(7 downto 0);
signal EncDispOut : slv(1 downto 0);
signal EncSof : sl := '0';
signal EncEof : sl := '0';
signal dClkP : sl := '1'; -- Data clock
signal dClkN : sl := '0';
signal fClkP : sl := '0'; -- Frame clock
signal fClkN : sl := '1';
signal serialDataOut1 : sl;
signal serialDataOut2 : sl;
signal chId : slv(11 downto 0);
-- DUNE system level simulation
signal duneClk : sl := '1';
signal duneClkInt : sl ;
signal duneClkx4 : sl ;
signal duneRst : sl := '1';
signal duneRstInt : sl ;
signal duneRstx4 : sl ;
signal cryoRst : sl ;
signal phaseDuneCryo : slv(7 downto 0);
--
signal duneSyncCmd : slv(15 downto 0) := (others => '0');
signal duneCmdAddr : slv( 7 downto 0) := (others => '0');
signal duneSyncCmdStrobe : sl := '0';
signal duneTimeStamp : slv(31 downto 0);
signal duneCycleTime : slv(6 downto 0);
signal duneSR0 : sl;
signal duneSamClkiEnable : sl;
signal duneSamClkiEnableAtCold : sl;
signal cryoClk : sl;
-- protoDune
signal protoDuneClk : sl := '1';
signal protoDuneClkInt : sl ;
signal protoDuneClkx4 : sl ;
signal protoCryoClk : sl ;
signal protoDuneRst : sl := '1';
signal protoDuneRstInt : sl ;
signal protoDuneRstx4 : sl ;
signal protoCryoRst : sl ;
signal phaseprotoDuneCryo : slv(7 downto 0);
signal dummy : slv(1 downto 0);
begin --
-- clock generation
qsfpClkP <= not qsfpClkP after 6.4 ns;
qsfpClkN <= not qsfpClkP;
ddrClkP <= not ddrCkP after 6.4 ns;
ddrClkN <= not ddrCkP;
-- fClkP <= not fClkP after 7 * 2 ns;
fClkN <= not fClkP;
-- dClkP <= not dClkP after 2 ns;
dClkN <= not dClkP;
-- dunel clk
duneClk <= not duneClk after 8 ns;
protoDuneClk <= not protoDuneClk after 10 ns;
--cable model
duneSamClkiEnableAtCold <= duneSamClkiEnable after 125 ns;
------------------------------------------
-- Generate clocks --
------------------------------------------
-- clkIn : 50.00 MHz -- DUNE base clock
-- clkOut(0) : 50.00 MHz -- Internal copy of the clock
-- clkOut(1) : 200.00 MHz -- DUNE clock times 4 used for the deserializer
-- clkOut(2) : 56.00 MHz -- CRYO clock
U_PROTODUNE_ClockGen : entity work.ClockManagerUltraScale
generic map(
TPD_G => 1 ns,
TYPE_G => "MMCM", -- or "PLL"
INPUT_BUFG_G => true,
FB_BUFG_G => true,
RST_IN_POLARITY_G => '1', -- '0' for active low
NUM_CLOCKS_G => 3,
-- MMCM attributes
BANDWIDTH_G => "OPTIMIZED",
CLKIN_PERIOD_G => 20.0, -- Input period in ns );
DIVCLK_DIVIDE_G => 1,
CLKFBOUT_MULT_F_G => 1.0,
CLKFBOUT_MULT_G => 20,
CLKOUT0_DIVIDE_F_G => 1.0,
CLKOUT0_DIVIDE_G => 20,
CLKOUT0_PHASE_G => 0.0,
CLKOUT0_DUTY_CYCLE_G => 0.5,
CLKOUT0_RST_HOLD_G => 3,
CLKOUT0_RST_POLARITY_G => '1',
CLKOUT1_DIVIDE_G => 5,
CLKOUT1_PHASE_G => 0.0,
CLKOUT1_DUTY_CYCLE_G => 0.5,
CLKOUT1_RST_HOLD_G => 3,
CLKOUT1_RST_POLARITY_G => '1',
CLKOUT2_DIVIDE_G => 18,
CLKOUT2_PHASE_G => 0.0,
CLKOUT2_DUTY_CYCLE_G => 0.5,
CLKOUT2_RST_HOLD_G => 3,
CLKOUT2_RST_POLARITY_G => '1')
port map(
clkIn => protoDuneClk,
rstIn => protoDuneRst,
clkOut(0) => protoDuneClkInt,
clkOut(1) => protoDuneClkx4,
clkOut(2) => protoCryoClk,
rstOut(0) => protoDuneRstInt,
rstOut(1) => protoDuneRstx4,
rstOut(2) => protoCryoRst,
locked => open
);
U_ISERDESE3_50to56 : ISERDESE3
generic map (
DATA_WIDTH => 8, -- Parallel data width (4,8)
FIFO_ENABLE => "FALSE", -- Enables the use of the FIFO
FIFO_SYNC_MODE => "FALSE", -- Enables the use of internal 2-stage synchronizers on the FIFO
IS_CLK_B_INVERTED => '1', -- Optional inversion for CLK_B
IS_CLK_INVERTED => '0', -- Optional inversion for CLK
IS_RST_INVERTED => '0', -- Optional inversion for RST
SIM_DEVICE => "ULTRASCALE" -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
-- ULTRASCALE_PLUS_ES2)
)
port map (
FIFO_EMPTY => OPEN, -- 1-bit output: FIFO empty flag
INTERNAL_DIVCLK => open, -- 1-bit output: Internally divided down clock used when FIFO is
-- disabled (do not connect)
Q => phaseProtoDuneCryo, -- bit registered output
CLK => protoDuneClkx4, -- 1-bit input: High-speed clock
CLKDIV => protoDuneClkInt, -- 1-bit input: Divided Clock
CLK_B => protoDuneClkx4, -- 1-bit input: Inversion of High-speed clock CLK
D => protoCryoClk, -- 1-bit input: Serial Data Input
FIFO_RD_CLK => '1', -- 1-bit input: FIFO read clock
FIFO_RD_EN => '1', -- 1-bit input: Enables reading the FIFO when asserted
RST => protoDuneRstInt -- 1-bit input: Asynchronous Reset
);
------------------------------------------
-- Generate clocks from 156.25 MHz PGP --
------------------------------------------
-- clkIn : 156.25 MHz PGP
-- clkOut(0) : 448.00 MHz -- 8x cryo clock (default 56MHz)
-- clkOut(1) : 112.00 MHz -- 448 clock div 4
-- clkOut(2) : 64.00 MHz -- 448 clock div 7
-- clkOut(3) : 56.00 MHz -- cryo input clock default is 56MHz
U_TB_ClockGen : entity work.ClockManagerUltraScale
generic map(
TPD_G => 1 ns,
TYPE_G => "MMCM", -- or "PLL"
INPUT_BUFG_G => true,
FB_BUFG_G => true,
RST_IN_POLARITY_G => '1', -- '0' for active low
NUM_CLOCKS_G => 2,
-- MMCM attributes
BANDWIDTH_G => "OPTIMIZED",
CLKIN_PERIOD_G => 6.4, -- Input period in ns );
DIVCLK_DIVIDE_G => 8,
CLKFBOUT_MULT_F_G => 45.875,
CLKFBOUT_MULT_G => 5,
CLKOUT0_DIVIDE_F_G => 1.0,
CLKOUT0_DIVIDE_G => 2,
CLKOUT0_PHASE_G => 0.0,
CLKOUT0_DUTY_CYCLE_G => 0.5,
CLKOUT0_RST_HOLD_G => 3,
CLKOUT0_RST_POLARITY_G => '1',
CLKOUT1_DIVIDE_G => 14,
CLKOUT1_PHASE_G => 0.0,
CLKOUT1_DUTY_CYCLE_G => 0.5,
CLKOUT1_RST_HOLD_G => 3,
CLKOUT1_RST_POLARITY_G => '1')
port map(
clkIn => sysClk,
rstIn => sysRst,
clkOut(0) => dClkP, --bit clk
clkOut(1) => fClkP,
rstOut(0) => dummy(0),
rstOut(1) => dummy(1),
locked => open
);
U_asicModel : entity work.CryoAsicTopLevelModel
generic map(
TPD_G => TPD_G
)
port map(
clk => protoCryoClk,
gRst => protoCryoRst,
-- simulated data
analogData => x"000",
-- saci
saciClk => asicSaciClk,
saciSelL => asicSaciSel(0),
saciCmd => asicSaciCmd,
saciRsp => asicSaciRsp,
-- static control
SRO => duneSR0,--asicR0,
SamClkiEnable => duneSamClkiEnableAtCold,--asicSamClkEn,
-- data out
bitClk0 => open,
frameClk0 => open,
sData0 => open,
bitClk1 => open,
frameClk1 => open,
sData1 => open
);
U_WIBModel_0 : entity work.WIBTopLevelModel
generic map(
TPD_G => TPD_G,
SYSTEM_ENVIRONMENT => "DUNE", -- "PROTODUNE"
THIS_MODULE_CMD_ADDRESS => x"01"
)
port map(
DUNEclk => duneClk,
DUNERst => duneRst,
-- DUNE highSpeed bus
SyncCmd => duneSyncCmd,
CmdAddr => duneCmdAddr,
SyncCmdStrobe => duneSyncCmdStrobe,
timeStamp => duneTimeStamp,
cycleTime => duneCycleTime,
-- level based control
SR0 => duneSR0,
SamCLKiEnable => duneSamClkiEnable,
asicClk => cryoClk
);
-- waveform generation
WaveGen_Proc: process
variable registerData : slv(31 downto 0);
begin
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
wait until duneRst = '0';
wait for 10 us;
-- check reset timestamp command
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0000";
duneCmdAddr <= x"01";
duneSyncCmdStrobe <= '1';
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0000";
duneCmdAddr <= x"00";
duneSyncCmdStrobe <= '0';
wait for 10 us;
-- check reset cycletime command
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0001";
duneCmdAddr <= x"01";
duneSyncCmdStrobe <= '1';
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0000";
duneCmdAddr <= x"00";
duneSyncCmdStrobe <= '0';
wait for 10 us;
-- check reset SamCLKiEnable
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0002";
duneCmdAddr <= x"01";
duneSyncCmdStrobe <= '1';
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0000";
duneCmdAddr <= x"00";
duneSyncCmdStrobe <= '0';
wait for 10 us;
-- check reset SR0 command
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0003";
duneCmdAddr <= x"01";
duneSyncCmdStrobe <= '1';
wait until duneClk = '0';
wait until duneClk = '1';
duneSyncCmd <= x"0000";
duneCmdAddr <= x"00";
duneSyncCmdStrobe <= '0';
wait until sysClk = '1';
wait;
end process WaveGen_Proc;
-------------------------------------------------------------------------------
-- simulation process for channel ID. Counter from 0 to 31
-------------------------------------------------------------------------------
EncValid_Proc: process
begin
wait until fClkP = '1';
EncValidIn <= asicR0;
end process;
-------------------------------------------------------------------------------
-- simulation process for channel ID. Counter from 0 to 31
-------------------------------------------------------------------------------
chId_Proc: process
variable chIdCounter : integer := 0;
begin
wait until fClkP = '1';
if asicR0 = '1' then
chIdCounter := ChIdCounter + 1;
if chIdCounter = 32 then
chIdCounter := 0;
end if;
else
chIdCounter := 0;
end if;
chId <= toSlv(chIdCounter, 12);
end process;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
EncDataIn_Proc: process
variable dataIndex : integer := 0;
begin
wait until fClkP = '1';
if asicR0 = '1' then
if DATA_TYPE_C = CH_ID then
EncDataIn <= chId;
else
EncDataIn <= ramWaveform(dataIndex);
end if;
dataIndex := dataIndex + 1;
if dataIndex = DEPTH_C then
dataIndex := 0;
end if;
else
EncDataIn <= IDLE_PATTERN_C;
end if;
EncDataOut_d(0) <= EncDataOut;
for i in 1 to 7 loop
EncDataOut_d(i) <= EncDataOut_d(i-1);
end loop;
end process;
U_encoder : entity work.SspEncoder12b14b
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => '1',
RST_ASYNC_G => false,
AUTO_FRAME_G => true,
FLOW_CTRL_EN_G => false)
port map(
clk => fClkP,
rst => sysRst,
validIn => EncValidIn,
readyIn => EncReadyIn,
sof => EncSof,
eof => EncEof,
dataIn => EncDataIn,
validOut => EncValidOut,
readyOut => EncReadyOut,
dataOut => EncDataOut);
U_serializer : entity work.serializerSim
generic map(
g_dwidth => 14
)
port map(
clk_i => dClkP,
reset_n_i => sysRst_n,
data_i => EncDataOut, -- "00"&EncDataIn, --
data_o => serialDataOut1
);
U_serializer2 : entity work.serializerSim
generic map(
g_dwidth => 14
)
port map(
clk_i => dClkP,
reset_n_i => sysRst_n,
data_i => EncDataOut_d(7), -- "00"&EncDataIn, --
data_o => serialDataOut2
);
sysRst_n <= not sysRst;
duneRst <= sysRst;
protoDuneRst <= sysRst;
asicDataP(0) <= serialDataOut1;
asicDataN(0) <= not serialDataOut1;
-- asicDataP(0) <= fClkP;
-- asicDataN(0) <= fClkN;
asicDataP(3) <= serialDataOut2;
asicDataN(3) <= not serialDataOut2;
asicDataP(2) <= fClkP;
asicDataN(2) <= fClkN;
asicDataP(5) <= dClkP;
asicDataN(5) <= dClkN;
U_App : entity work.Application
generic map (
TPD_G => TPD_G,
SIMULATION_G => true,
BUILD_INFO_G => BUILD_INFO_G)
port map (
----------------------
-- Top Level Interface
----------------------
-- System Clock and Reset
sysClk => sysClk,
sysRst => sysRst,
-- AXI-Lite Register Interface (sysClk domain)
-- Register Address Range = [0x80000000:0xFFFFFFFF]
sAxilReadMaster => axilReadMaster,
sAxilReadSlave => axilReadSlave,
sAxilWriteMaster => axilWriteMaster,
sAxilWriteSlave => axilWriteSlave,
-- AXI Stream, one per QSFP lane (sysClk domain)
mAxisMasters => axisMasters,
mAxisSlaves => axisSlaves,
-- Auxiliary AXI Stream, (sysClk domain)
sAuxAxisMasters => sAuxAxisMasters,
sAuxAxisSlaves => sAuxAxisSlaves,
ssiCmd => ssiCmd,
-- DDR's AXI Memory Interface (sysClk domain)
-- DDR Address Range = [0x00000000:0x3FFFFFFF]
mAxiReadMaster => axiReadMaster,
mAxiReadSlave => axiReadSlave,
mAxiWriteMaster => axiWriteMaster,
mAxiWriteSlave => axiWriteSlave,
-- Microblaze's Interrupt bus (sysClk domain)
mbIrq => mbIrq,
-----------------------
-- Application Ports --
-----------------------
-- System Ports
digPwrEn => digPwrEn,
anaPwrEn => anaPwrEn,
syncDigDcDc => syncDigDcDc,
syncAnaDcDc => syncAnaDcDc,
syncDcDc => syncDcDc,
led => open,
daqTg => daqTg,
connTgOut => connTgOut,
connMps => connMps,
connRun => connRun,
-- Fast ADC Ports
adcSpiClk => adcSpiClk,
adcSpiData => adcSpiData,
adcSpiCsL => adcSpiCsL,
adcPdwn => adcPdwn,
adcClkP => adcClkP,
adcClkM => adcClkM,
adcDoClkP => adcDoClkP,
adcDoClkM => adcDoClkM,
adcFrameClkP => adcFrameClkP,
adcFrameClkM => adcFrameClkM,
adcMonDoutP => adcMonDoutP,
adcMonDoutN => adcMonDoutN,
-- Slow ADC
slowAdcSclk => slowAdcSclk,
slowAdcDin => slowAdcDin,
slowAdcCsL => slowAdcCsL,
slowAdcRefClk => slowAdcRefClk,
slowAdcDout => slowAdcDout,
slowAdcDrdy => slowAdcDrdy,
slowAdcSync => slowAdcSync,
-- Slow DACs Port
sDacCsL => sDacCsL,
hsDacCsL => hsDacCsL,
hsDacLoad => hsDacLoad,
dacClrL => dacClrL,
dacSck => dacSck,
dacDin => dacDin,
-- ASIC Gbps Ports
asicDataP => asicDataP,
asicDataN => asicDataN,
-- ASIC Control Ports
asicR0 => asicR0,
asicPpmat => asicPpmat,
asicGlblRst => asicGlblRst,
asicSync => asicSync,
asicAcq => asicAcq,
asicRoClkP => asicRoClkP,
asicRoClkN => asicRoClkN,
-- SACI Ports
asicSaciCmd => asicSaciCmd,
asicSaciClk => asicSaciClk,
asicSaciSel => asicSaciSel,
asicSaciRsp => asicSaciRsp,
-- Spare Ports
spareHpP => spareHpP,
spareHpN => spareHpN,
spareHrP => spareHrP,
spareHrN => spareHrN,
-- GTH Ports
gtRxP => gtRxP,
gtRxN => gtRxN,
gtTxP => gtTxP,
gtTxN => gtTxN,
gtRefP => gtRefP,
gtRefN => gtRefN,
smaRxP => smaRxP,
smaRxN => smaRxN,
smaTxP => smaTxP,
smaTxN => smaTxN);
U_Core : entity work.EpixHrCore
generic map (
TPD_G => TPD_G,
BUILD_INFO_G => BUILD_INFO_G,
SIMULATION_G => true)
port map (
----------------------
-- Top Level Interface
----------------------
-- System Clock and Reset
sysClk => sysClk,
sysRst => sysRst,
-- AXI-Lite Register Interface (sysClk domain)
-- Register Address Range = [0x80000000:0xFFFFFFFF]
mAxilReadMaster => axilReadMaster,
mAxilReadSlave => axilReadSlave,
mAxilWriteMaster => axilWriteMaster,
mAxilWriteSlave => axilWriteSlave,
-- AXI Stream, one per QSFP lane (sysClk domain)
sAxisMasters => axisMasters,
sAxisSlaves => axisSlaves,
-- Auxiliary AXI Stream, (sysClk domain)
sAuxAxisMasters => sAuxAxisMasters,
sAuxAxisSlaves => sAuxAxisSlaves,
ssiCmd => ssiCmd,
-- DDR's AXI Memory Interface (sysClk domain)
-- DDR Address Range = [0x00000000:0x3FFFFFFF]
sAxiReadMaster => axiReadMaster,
sAxiReadSlave => axiReadSlave,
sAxiWriteMaster => axiWriteMaster,
sAxiWriteSlave => axiWriteSlave,
-- Microblaze's Interrupt bus (sysClk domain)
mbIrq => mbIrq,
----------------
-- Core Ports --
----------------
-- Board IDs Ports
snIoAdcCard => snIoAdcCard,
snIoCarrier => snIoCarrier,
-- QSFP Ports
qsfpRxP => qsfpRxP,
qsfpRxN => qsfpRxN,
qsfpTxP => qsfpTxP,
qsfpTxN => qsfpTxN,
qsfpClkP => qsfpClkP,
qsfpClkN => qsfpClkN,
qsfpLpMode => qsfpLpMode,
qsfpModSel => qsfpModSel,
qsfpInitL => qsfpInitL,
qsfpRstL => qsfpRstL,
qsfpPrstL => qsfpPrstL,
qsfpScl => qsfpScl,
qsfpSda => qsfpSda,
-- DDR Ports
ddrClkP => ddrClkP,
ddrClkN => ddrClkN,
ddrBg => ddrBg,
ddrCkP => ddrCkP,
ddrCkN => ddrCkN,
ddrCke => ddrCke,
ddrCsL => ddrCsL,
ddrOdt => ddrOdt,
ddrAct => ddrAct,
ddrRstL => ddrRstL,
ddrA => ddrA,
ddrBa => ddrBa,
ddrDm => ddrDm,
ddrDq => ddrDq,
ddrDqsP => ddrDqsP,
ddrDqsN => ddrDqsN,
ddrPg => ddrPg,
ddrPwrEn => ddrPwrEn,
-- SYSMON Ports
vPIn => vPIn,
vNIn => vNIn);
end arch;
|
-- Copyright 2018 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.TestCase_pkg.all;
use work.StreamSource_pkg.all;
use work.StreamSink_pkg.all;
use work.UtilInt_pkg.all;
entity StreamReshaperCtrl_tv is
end StreamReshaperCtrl_tv;
architecture TestVector of StreamReshaperCtrl_tv is
begin
random_tc: process is
constant TEST_STR : string(1 to 44) := "The quick brown fox jumps over the lazy dog.";
variable a : streamsource_type;
variable c : streamsource_type;
variable b : streamsink_type;
variable remain : integer;
variable expect : integer;
begin
tc_open("StreamReshaper-random", "tests normalization of randomized input.");
a.initialize("a");
c.initialize("c");
b.initialize("b");
a.set_total_cyc(-5, 5);
a.set_count(0, a.g_count_max);
for i in 0 to 15 loop
a.push_str(TEST_STR(1 to 44 - i));
a.transmit;
end loop;
-- FIXME: reshapers currently make no assumptions about the "last" flag of
-- the data input stream, even if it's not connected. This leads to it
-- needing to wait for additional input in some rare occasions. There
-- should probably be some generic that can be used to indicate that
-- din_last should be completely ignored to prevent unexpected stalls.
a.push_str("garbage");
a.transmit;
c.set_total_cyc(-5, 5);
c.set_count(0, c.g_count_max);
c.set_last_greed(false);
for i in 0 to 15 loop
c.push_str(TEST_STR(1 to 44 - i));
c.transmit;
end loop;
b.set_total_cyc(-5, 5);
b.unblock;
tc_wait_for(50 us);
-- Check packet data.
-- for i in 0 to 15 loop
-- tc_check(b.pq_get_str, TEST_STR(1 to 44 - i));
-- end loop;
-- tc_check(b.pq_ready, false);
-- Check packet shape.
while b.cq_ready and c.cq_ready loop
tc_check(b.cq_get_ecount, c.cq_get_ecount, "element count");
tc_check(b.cq_get_last, c.cq_get_last, "last");
b.cq_next;
c.cq_next;
end loop;
tc_check(b.cq_ready, false, "out > cin");
tc_check(c.cq_ready, false, "cin > out");
tc_pass;
wait;
end process;
end TestVector;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity vga is
port (
CLK_PIX : in std_logic;
RGB : in std_logic_vector(11 downto 0);
HRT : out integer range 0 to 1663;
VRT : out integer range 0 to 747;
VGA_R, VGA_G, VGA_B : out std_logic_vector(3 downto 0);
VGA_HS, VGA_VS : out std_logic
);
end vga;
architecture behavioral of vga is
-- 1280x720@60, CVR, target 74.5 MHz --
constant h_frm : natural := 1280;
constant h_fpor : natural := 64;
constant h_sync : natural := 128;
-- h_bpor : natural := 192;
constant h_num : natural := 1664;
constant h_pol : std_logic := '1';
constant v_frm : natural := 720;
constant v_fpor : natural := 3;
constant v_sync : natural := 5;
-- v_bpor : natural := 20;
constant v_num : natural := 748;
constant v_pol : std_logic := '1';
signal in_frm : std_logic;
signal h_cnt : integer range 0 to 2047 := 0;
signal v_cnt : integer range 0 to 1023 := 0;
signal h_syn : std_logic := not H_POL;
signal v_syn : std_logic := not V_POL;
signal vga_r_out : std_logic_vector(3 downto 0);
signal vga_g_out : std_logic_vector(3 downto 0);
signal vga_b_out : std_logic_vector(3 downto 0);
begin
-- Horizental counter
process (CLK_PIX)
begin
if rising_edge(CLK_PIX) then
if (h_cnt = h_num - 1) then
h_cnt <= 0;
else
h_cnt <= h_cnt + 1;
end if;
end if;
end process;
-- Vertical counter
process (CLK_PIX)
begin
if (rising_edge(CLK_PIX)) then
if (h_cnt = h_num - 1) then
if (v_cnt = v_num - 1) then
v_cnt <= 0;
else
v_cnt <= v_cnt + 1;
end if;
end if;
end if;
end process;
-- Horizontal sync
process (CLK_PIX)
begin
if rising_edge(CLK_PIX) then
if (h_cnt >= h_frm + h_fpor - 1) and (h_cnt < h_frm + h_fpor + h_sync - 1) then
h_syn <= h_pol;
else
h_syn <= not h_pol;
end if;
end if;
end process;
-- Vertical sync
process (CLK_PIX)
begin
if rising_edge(CLK_PIX) then
if (v_cnt >= v_frm + v_fpor - 1) and (v_cnt < v_frm + v_fpor + v_sync - 1) then
v_syn <= v_pol;
else
v_syn <= not v_pol;
end if;
end if;
end process;
-- Blank area black-out
in_frm <=
'1' when (h_cnt < h_frm) and (v_cnt < v_frm) else
'0';
vga_r_out <= (in_frm & in_frm & in_frm & in_frm) and RGB(11 downto 8);
vga_g_out <= (in_frm & in_frm & in_frm & in_frm) and RGB(7 downto 4);
vga_b_out <= (in_frm & in_frm & in_frm & in_frm) and RGB(3 downto 0);
-- Register outputs
process (CLK_PIX)
begin
if rising_edge(CLK_PIX) then
HRT <= h_cnt;
VRT <= v_cnt;
VGA_HS <= h_syn;
VGA_VS <= v_syn;
VGA_R <= vga_r_out;
VGA_G <= vga_g_out;
VGA_B <= vga_b_out;
end if;
end process;
end behavioral;
|
-- T2 Organizacao e Arquitetura de Computadores I
-- Year 2017/1
-- Members: <NAME>, <NAME>, <NAME>
-- File: pc.vhd
-- Description: PC component, outputs new value during Rising Edge
library ieee;
use ieee.std_logic_1164.all;
entity pc is
port(
pc_in : in std_logic_vector (31 downto 0);
clk : in std_logic;
rst : in std_logic;
pc_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture apc of pc is
begin
process(clk,rst)
begin
if rst = '1' then
pc_out <= "00000000010000000000000000000000";
else if clk = '1' and clk'event then
pc_out <= pc_in;
end if;
end if;
end process;
end architecture;
|
<reponame>meninge/dauphin
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
generic (
WDATA : natural := 16;
SIZE : natural := 784;
WADDR : natural := 10
);
port (
clk : in std_logic;
we: in std_logic;
en: in std_logic;
addr : in std_logic_vector(WADDR-1 downto 0);
di: in std_logic_vector(WDATA-1 downto 0);
do: out std_logic_vector(WDATA-1 downto 0));
end ram;
architecture syn of ram is
type ram_type is array (SIZE-1 downto 0) of std_logic_vector (WDATA-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
---------------------------------------------
----------- Sequential processes ------------
---------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
if we = '1' then
RAM(to_integer(unsigned(addr))) <= di;
end if;
do <= RAM(to_integer(unsigned(addr))) ;
end if;
end if;
end process;
end syn;
|
-------------------------------------------------------------------------------
-- Title : UART Transmitter with Odd-Parity
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
--
-- Data is send with LSB (Least Significat Bit) first.
-- Odd-parity. Example:
--
-- 0000 0000 => parity 1
-- 0000 0001 => parity 0
-- 0000 0010 => parity 0
-- 0000 0011 => parity 1
-- ...
-- 1111 1111 => parity 1
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013 <NAME>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_tx is
port (
txd_p : out std_logic;
busy_p : out std_logic;
data_p : in std_logic_vector(7 downto 0);
empty_p : in std_logic;
re_p : out std_logic;
clk_tx_en : in std_logic;
clk : in std_logic);
end uart_tx;
-------------------------------------------------------------------------------
architecture behavioural of uart_tx is
type transmit_states is (IDLE, START, DATA, PARITY, STOP);
type fifo_states is (IDLE, READ_DATA);
type uart_tx_type is record
state : transmit_states;
state_fifo : fifo_states;
bitcount : integer range 0 to 8;
parity : std_logic;
txd : std_logic; -- Output pin
-- Input FIFO
shift_reg : std_logic_vector(7 downto 0);
fifo_re : std_logic;
end record;
signal r, rin : uart_tx_type := (
state => IDLE,
state_fifo => IDLE,
bitcount => 0,
parity => '0',
txd => '1',
shift_reg => (others => '0'),
fifo_re => '0');
begin
-- Connections between ports and signals
txd_p <= r.txd;
re_p <= r.fifo_re;
busy_p <= '0' when ((r.state = IDLE) and (empty_p = '1')) else '1';
-- Sequential part of finite state machine (FSM)
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-- Combinatorial part of FSM
comb_proc : process(clk_tx_en, data_p, empty_p, r)
variable v : uart_tx_type;
begin
v := r;
v.fifo_re := '0';
case r.state is
when IDLE =>
if empty_p = '0' then
v.fifo_re := '1';
v.state_fifo := READ_DATA;
v.state := START;
end if;
when START =>
if clk_tx_en = '1' then
v.txd := '0';
v.state := DATA;
v.bitcount := 0;
v.parity := '0';
end if;
when DATA =>
if clk_tx_en = '1' then
-- Send data with LSB first
v.txd := r.shift_reg(0);
-- data parity
-- 0 + 0 => 0
-- 0 + 1 => 1
-- 1 + 0 => 1
-- 1 + 1 => 0
-- => xor
v.parity := r.parity xor r.shift_reg(0);
v.shift_reg := '0' & r.shift_reg(7 downto 1);
if r.bitcount = 7 then
v.state := PARITY;
else
v.bitcount := r.bitcount + 1;
end if;
end if;
when PARITY =>
if clk_tx_en = '1' then
v.txd := not r.parity;
v.state := STOP;
end if;
when STOP =>
if clk_tx_en = '1' then
v.txd := '1';
v.state := IDLE;
end if;
end case;
case r.state_fifo is
when IDLE =>
-- Do nothing
when READ_DATA =>
v.state_fifo := IDLE;
v.shift_reg := data_p;
end case;
rin <= v;
end process comb_proc;
-- Component instantiations
end behavioural;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
architecture behavioral of receiver is
signal reset_n : std_logic;
signal delay : std_logic;
signal socadc : std_logic_vector(31 downto 0);
signal encoded_data : std_logic_vector(9 downto 0);
signal buffer_in : std_logic_vector(7 downto 0);
signal buffer_out : signed(7 downto 0);
signal data_in_deframing : std_logic;
signal data_out_deframing : std_logic;
signal data_out_buffer : std_logic_vector(9 downto 0);
signal wout1 : std_logic_vector(15 downto 0);
signal wout2 : std_logic_vector(15 downto 0);
signal delay_counter_out : std_logic_vector(3 downto 0);
signal sndclk : std_logic;
signal clk_50_MHz : std_logic;
signal clk_3_255_MHz : std_logic;
signal clk_320_kHz : std_logic;
signal clk_32_kHz : std_logic;
signal preamble_inserted : std_logic;
signal preamble_found : std_logic;
begin
reset_n <= KEY(0);
delay <= KEY(1);
clk_50_MHz <= CLOCK_50;
data_in_deframing <= GPIO_0(0);
clk_320_kHz <= GPIO_0(1);
preamble_inserted <= GPIO_0(2);
GPIO_1(0) <= data_in_deframing;
GPIO_1(1) <= clk_32_kHz;
GPIO_1(2) <= clk_320_kHz;
GPIO_1(3) <= preamble_inserted;
GPIO_1(4) <= preamble_found;
LEDR(3 downto 0) <= delay_counter_out;
process(clk_32_kHz)
begin
if rising_edge(clk_32_kHz) then
wout1 <= std_logic_vector(buffer_out) & "00000000";
wout2 <= std_logic_vector(buffer_out) & "00000000";
end if;
end process;
s_2_p_inst : entity work.s_2_p
generic map (
word_length_buffer => 10
)
port map (
data_in_buffer => data_out_deframing,
clk_buffer_parallel => clk_32_kHz,
clk_buffer_serial => clk_320_kHz,
reset => reset_n,
delay => delay,
delay_counter_out => delay_counter_out,
data_out_buffer => data_out_buffer
);
deframing_inst : entity work.deframing
generic map (
word_length_deframing => 10,
preamble_receiver => 785,
deframing_length => 32550
)
port map (
data_in_deframing => data_in_deframing,
clk_deframing_in => clk_320_kHz,
reset => reset_n,
data_out_deframing => data_out_deframing,
--clk_deframing_out_serial => ,
clk_deframing_out_parallel => clk_32_kHz,
preamble_found => preamble_found
);
decoder_inst: entity work.decoder_4B5B
generic map (
word_length_out_4B5B_decoder => 8
)
port map (
data_in_4B5B_decoder => data_out_buffer,
clk_4B5B_decoder => clk_32_kHz,
reset => reset_n, -- active low
data_out_4B5B_decoder => buffer_in
);
audiobuffer_inst : entity work.audiobuffer
generic map (
word_length => word_length
)
port map (
rst => reset_n,
clk => clk_32_kHz,
clk_in => sndclk,
clk_out => clk_32_kHz,
data_in => signed(buffer_in),
data_out => buffer_out-- to gpio
);
audio_inst : entity work.audio_interface
port map (
LDATA => (wout1),
RDATA => (wout2),
clk => clk_50_MHz,
Reset => reset_n,
INIT_FINISH => open,
adc_full => open,
AUD_MCLK => AUD_XCK,
AUD_ADCLRCK => AUD_ADCLRCK,
AUD_ADCDAT => AUD_ADCDAT,
AUD_BCLK => AUD_BCLK,
data_over => sndclk,
AUD_DACDAT => AUD_DACDAT,
AUD_DACLRCK => AUD_DACLRCK,
I2C_SDAT => FPGA_I2C_SDAT,
I2C_SCLK => FPGA_I2C_SCLK,
ADCDATA => socadc
);
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.nondeterminism.all;
use work.channel.all;
entity wine_example2 is
end wine_example2;
architecture structure of wine_example2 is
component winery
port(wine_shipping : inout channel);
end component;
component wine_shopAP
port(wine_delivery : inout channel;
wine_selling : inout channel);
end component;
component patron
port(wine_buying : inout channel);
end component;
signal winery_to_shop : channel := init_channel;
signal shop_to_patron : channel := init_channel;
begin
THE_WINERY : winery port map(wine_shipping => winery_to_shop);
THE_SHOP : wine_shopAP port map(wine_delivery => winery_to_shop,
wine_selling => shop_to_patron);
THE_PATRON : patron port map(wine_buying => shop_to_patron);
end structure;
|
--!
--! Copyright 2018 <NAME>, <EMAIL>
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! River Netlist component declaration
use riverlib.types_river.all;
library ambalib;
use ambalib.types_amba4.all;
entity RiverTop is
generic (
memtech : integer := 0;
hartid : integer := 0;
async_reset : boolean := false;
fpu_ena : boolean := true;
coherence_ena : boolean := false;
tracer_ena : boolean := false;
power_sim_estimation : boolean := false
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
-- Memory interface:
i_req_mem_ready : in std_logic; -- AXI request was accepted
o_req_mem_path : out std_logic; -- 0=ctrl; 1=data path
o_req_mem_valid : out std_logic; -- AXI memory request is valid
o_req_mem_type : out std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);-- AXI memory request is write type
o_req_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- AXI memory request address
o_req_mem_strob : out std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);-- Writing strob. 1 bit per Byte
o_req_mem_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0); -- Writing data
i_resp_mem_valid : in std_logic; -- AXI response is valid
i_resp_mem_path : in std_logic; -- 0=ctrl; 1=data path
i_resp_mem_data : in std_logic_vector(L1CACHE_LINE_BITS-1 downto 0); -- Read data
i_resp_mem_load_fault : in std_logic; -- Bus response with SLVERR or DECERR on read
i_resp_mem_store_fault : in std_logic; -- Bus response with SLVERR or DECERR on write
-- Interrupt line from external interrupts controller (PLIC).
i_ext_irq : in std_logic;
o_time : out std_logic_vector(63 downto 0); -- Timer. Clock counter except halt state.
o_exec_cnt : out std_logic_vector(63 downto 0);
-- D$ Snoop interface
i_req_snoop_valid : in std_logic;
i_req_snoop_type : in std_logic_vector(SNOOP_REQ_TYPE_BITS-1 downto 0);
o_req_snoop_ready : out std_logic;
i_req_snoop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_resp_snoop_ready : in std_logic;
o_resp_snoop_valid : out std_logic;
o_resp_snoop_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
o_resp_snoop_flags : out std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
-- Debug interface:
i_dport_valid : in std_logic; -- Debug access from DSU is valid
i_dport_write : in std_logic; -- Write command flag
i_dport_region : in std_logic_vector(1 downto 0); -- Registers region ID: 0=CSR; 1=IREGS; 2=Control
i_dport_addr : in std_logic_vector(11 downto 0); -- Register idx
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Write value
o_dport_ready : out std_logic; -- Response is ready
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Response value
o_halted : out std_logic
);
end;
architecture arch_RiverTop of RiverTop is
-- Control path:
signal w_req_ctrl_ready : std_logic;
signal w_req_ctrl_valid : std_logic;
signal wb_req_ctrl_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_resp_ctrl_valid : std_logic;
signal wb_resp_ctrl_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_resp_ctrl_data : std_logic_vector(31 downto 0);
signal w_resp_ctrl_load_fault : std_logic;
signal w_resp_ctrl_executable : std_logic;
signal w_resp_ctrl_ready : std_logic;
-- Data path:
signal w_req_data_ready : std_logic;
signal w_req_data_valid : std_logic;
signal w_req_data_write : std_logic;
signal wb_req_data_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_req_data_wdata : std_logic_vector(63 downto 0);
signal wb_req_data_wstrb : std_logic_vector(7 downto 0);
signal w_resp_data_valid : std_logic;
signal wb_resp_data_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_resp_data_data : std_logic_vector(63 downto 0);
signal w_resp_data_load_fault : std_logic;
signal w_resp_data_store_fault : std_logic;
signal w_resp_data_er_mpu_load : std_logic;
signal w_resp_data_er_mpu_store : std_logic;
signal wb_resp_data_store_fault_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_resp_data_ready : std_logic;
signal w_mpu_region_we : std_logic;
signal wb_mpu_region_idx : std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
signal wb_mpu_region_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_mpu_region_mask : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal wb_mpu_region_flags : std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
signal wb_flush_address : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_flush_valid : std_logic;
signal wb_data_flush_address : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal w_data_flush_valid : std_logic;
signal w_data_flush_end : std_logic;
signal wb_istate : std_logic_vector(3 downto 0);
signal wb_dstate : std_logic_vector(3 downto 0);
signal wb_cstate : std_logic_vector(1 downto 0);
constant POWER_SIM_STOP_ADDR : std_logic_vector(CFG_SYSBUS_ADDR_BITS-1 downto 0) := "00000000000000000001111111110000";
begin
rtl_generate : if power_sim_estimation = false generate
proc0 : Processor generic map (
hartid => hartid,
async_reset => async_reset,
fpu_ena => fpu_ena,
tracer_ena => tracer_ena
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_req_ctrl_ready => w_req_ctrl_ready,
o_req_ctrl_valid => w_req_ctrl_valid,
o_req_ctrl_addr => wb_req_ctrl_addr,
i_resp_ctrl_valid => w_resp_ctrl_valid,
i_resp_ctrl_addr => wb_resp_ctrl_addr,
i_resp_ctrl_data => wb_resp_ctrl_data,
i_resp_ctrl_load_fault => w_resp_ctrl_load_fault,
i_resp_ctrl_executable => w_resp_ctrl_executable,
o_resp_ctrl_ready => w_resp_ctrl_ready,
i_req_data_ready => w_req_data_ready,
o_req_data_valid => w_req_data_valid,
o_req_data_write => w_req_data_write,
o_req_data_addr => wb_req_data_addr,
o_req_data_wdata => wb_req_data_wdata,
o_req_data_wstrb => wb_req_data_wstrb,
i_resp_data_valid => w_resp_data_valid,
i_resp_data_addr => wb_resp_data_addr,
i_resp_data_data => wb_resp_data_data,
i_resp_data_store_fault_addr => wb_resp_data_store_fault_addr,
i_resp_data_load_fault => w_resp_data_load_fault,
i_resp_data_store_fault => w_resp_data_store_fault,
i_resp_data_er_mpu_load => w_resp_data_er_mpu_load,
i_resp_data_er_mpu_store => w_resp_data_er_mpu_store,
o_resp_data_ready => w_resp_data_ready,
i_ext_irq => i_ext_irq,
o_time => o_time,
o_exec_cnt => o_exec_cnt,
o_mpu_region_we => w_mpu_region_we,
o_mpu_region_idx => wb_mpu_region_idx,
o_mpu_region_addr => wb_mpu_region_addr,
o_mpu_region_mask => wb_mpu_region_mask,
o_mpu_region_flags => wb_mpu_region_flags,
i_dport_valid => i_dport_valid,
i_dport_write => i_dport_write,
i_dport_region => i_dport_region,
i_dport_addr => i_dport_addr,
i_dport_wdata => i_dport_wdata,
o_dport_ready => o_dport_ready,
o_dport_rdata => o_dport_rdata,
o_halted => o_halted,
o_flush_address => wb_flush_address,
o_flush_valid => w_flush_valid,
o_data_flush_address => wb_data_flush_address,
o_data_flush_valid => w_data_flush_valid,
i_data_flush_end => w_data_flush_end,
i_istate => wb_istate,
i_dstate => wb_dstate,
i_cstate => wb_cstate);
end generate rtl_generate;
netlist_generate : if power_sim_estimation = true generate
proc0 : ProcessorNanGate15 port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_req_ctrl_ready => w_req_ctrl_ready,
o_req_ctrl_valid => w_req_ctrl_valid,
o_req_ctrl_addr => wb_req_ctrl_addr,
i_resp_ctrl_valid => w_resp_ctrl_valid,
i_resp_ctrl_addr => wb_resp_ctrl_addr,
i_resp_ctrl_data => wb_resp_ctrl_data,
i_resp_ctrl_load_fault => w_resp_ctrl_load_fault,
i_resp_ctrl_executable => w_resp_ctrl_executable,
o_resp_ctrl_ready => w_resp_ctrl_ready,
i_req_data_ready => w_req_data_ready,
o_req_data_valid => w_req_data_valid,
o_req_data_write => w_req_data_write,
o_req_data_addr => wb_req_data_addr,
o_req_data_wdata => wb_req_data_wdata,
o_req_data_wstrb => wb_req_data_wstrb,
i_resp_data_valid => w_resp_data_valid,
i_resp_data_addr => wb_resp_data_addr,
i_resp_data_data => wb_resp_data_data,
i_resp_data_store_fault_addr => wb_resp_data_store_fault_addr,
i_resp_data_load_fault => w_resp_data_load_fault,
i_resp_data_store_fault => w_resp_data_store_fault,
i_resp_data_er_mpu_load => w_resp_data_er_mpu_load,
i_resp_data_er_mpu_store => w_resp_data_er_mpu_store,
o_resp_data_ready => w_resp_data_ready,
i_ext_irq => i_ext_irq,
o_time => o_time,
o_exec_cnt => o_exec_cnt,
o_mpu_region_we => w_mpu_region_we,
o_mpu_region_idx => wb_mpu_region_idx,
o_mpu_region_addr => wb_mpu_region_addr,
o_mpu_region_mask => wb_mpu_region_mask,
o_mpu_region_flags => wb_mpu_region_flags,
i_dport_valid => i_dport_valid,
i_dport_write => i_dport_write,
i_dport_region => i_dport_region,
i_dport_addr => i_dport_addr,
i_dport_wdata => i_dport_wdata,
o_dport_ready => o_dport_ready,
o_dport_rdata => o_dport_rdata,
o_halted => o_halted,
o_flush_address => wb_flush_address,
o_flush_valid => w_flush_valid,
o_data_flush_address => wb_data_flush_address,
o_data_flush_valid => w_data_flush_valid,
i_data_flush_end => w_data_flush_end,
i_istate => wb_istate,
i_dstate => wb_dstate,
i_cstate => wb_cstate
);
end generate netlist_generate;
assert_end_sim : if power_sim_estimation = true generate
cyclelogic : process (i_clk, i_nrst)
variable my_line : line;
variable clk_counter : std_logic_vector(31 downto 0);
begin
if rising_edge(i_clk) and i_clk = '1' and i_nrst = '0' then
-- reset clk cycle counter
clk_counter := "00000000000000000000000000000000";
write(my_line, string'(" Resetting DUT "));
writeline(output, my_line);
elsif rising_edge(i_clk) and i_clk = '1' and i_nrst = '1' then
-- increment clk cycle counter
clk_counter := clk_counter + '1';
-- print tracing information for simulation and hardware
write(my_line, string'(" CLK("));
hwrite(my_line, clk_counter);
write(my_line, string'(") ADDR(0x"));
hwrite(my_line, wb_resp_ctrl_addr);
write(my_line, string'(") DASM(0x"));
hwrite(my_line, wb_resp_ctrl_data);
write(my_line, string'(") O_CTRL_RDY("));
write(my_line, w_resp_ctrl_ready);
write(my_line, string'(") LFAULT("));
write(my_line, w_resp_ctrl_load_fault);
write(my_line, string'(") EXEC("));
write(my_line, w_resp_ctrl_executable);
write(my_line, string'(")"));
writeline(output, my_line);
-- to prevent infinite sim, we force break when power estimating
assert clk_counter /= "00000000000000011111111111111111" report "Fatal End of Simulation" severity failure;
assert wb_resp_ctrl_addr /= POWER_SIM_STOP_ADDR report "Correct End of Simulation" severity failure;
end if;
end process;
end generate assert_end_sim;
cache0 : CacheTop generic map (
memtech => memtech,
async_reset => async_reset,
coherence_ena => coherence_ena
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_req_ctrl_valid => w_req_ctrl_valid,
i_req_ctrl_addr => wb_req_ctrl_addr,
o_req_ctrl_ready => w_req_ctrl_ready,
o_resp_ctrl_valid => w_resp_ctrl_valid,
o_resp_ctrl_addr => wb_resp_ctrl_addr,
o_resp_ctrl_data => wb_resp_ctrl_data,
o_resp_ctrl_load_fault => w_resp_ctrl_load_fault,
o_resp_ctrl_executable => w_resp_ctrl_executable,
i_resp_ctrl_ready => w_resp_ctrl_ready,
i_req_data_valid => w_req_data_valid,
i_req_data_write => w_req_data_write,
i_req_data_addr => wb_req_data_addr,
i_req_data_wdata => wb_req_data_wdata,
i_req_data_wstrb => wb_req_data_wstrb,
o_req_data_ready => w_req_data_ready,
o_resp_data_valid => w_resp_data_valid,
o_resp_data_addr => wb_resp_data_addr,
o_resp_data_data => wb_resp_data_data,
o_resp_data_store_fault_addr => wb_resp_data_store_fault_addr,
o_resp_data_load_fault => w_resp_data_load_fault,
o_resp_data_store_fault => w_resp_data_store_fault,
o_resp_data_er_mpu_load => w_resp_data_er_mpu_load,
o_resp_data_er_mpu_store => w_resp_data_er_mpu_store,
i_resp_data_ready => w_resp_data_ready,
i_req_mem_ready => i_req_mem_ready,
o_req_mem_path => o_req_mem_path,
o_req_mem_valid => o_req_mem_valid,
o_req_mem_type => o_req_mem_type,
o_req_mem_addr => o_req_mem_addr,
o_req_mem_strob => o_req_mem_strob,
o_req_mem_data => o_req_mem_data,
i_resp_mem_valid => i_resp_mem_valid,
i_resp_mem_path => i_resp_mem_path,
i_resp_mem_data => i_resp_mem_data,
i_resp_mem_load_fault => i_resp_mem_load_fault,
i_resp_mem_store_fault => i_resp_mem_store_fault,
i_mpu_region_we => w_mpu_region_we,
i_mpu_region_idx => wb_mpu_region_idx,
i_mpu_region_addr => wb_mpu_region_addr,
i_mpu_region_mask => wb_mpu_region_mask,
i_mpu_region_flags => wb_mpu_region_flags,
i_req_snoop_valid => i_req_snoop_valid,
i_req_snoop_type => i_req_snoop_type,
o_req_snoop_ready => o_req_snoop_ready,
i_req_snoop_addr => i_req_snoop_addr,
i_resp_snoop_ready => i_resp_snoop_ready,
o_resp_snoop_valid => o_resp_snoop_valid,
o_resp_snoop_data => o_resp_snoop_data,
o_resp_snoop_flags => o_resp_snoop_flags,
i_flush_address => wb_flush_address,
i_flush_valid => w_flush_valid,
i_data_flush_address => wb_data_flush_address,
i_data_flush_valid => w_data_flush_valid,
o_data_flush_end => w_data_flush_end,
o_istate => wb_istate,
o_dstate => wb_dstate,
o_cstate => wb_cstate);
end;
|
<reponame>g-i-wilson/h-vhdl-lib
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/21/2020 05:07:34 PM
-- Design Name:
-- Module Name: shorten - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shorten is
generic (
width : integer;
places : integer
);
port (
input : in STD_LOGIC_VECTOR (width-1 downto 0);
output : out STD_LOGIC_VECTOR (width-1 downto 0);
round_up : in STD_LOGIC;
clk : in STD_LOGIC;
en : in STD_LOGIC;
rst : in STD_LOGIC
);
end shorten;
architecture Behavioral of shorten is
component reg_generic
generic (
reg_len : integer
);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
reg_in : in std_logic_vector(reg_len-1 downto 0);
reg_out : out std_logic_vector(reg_len-1 downto 0)
);
end component;
signal
shifted_sig,
rounded_sig
: std_logic_vector(width-1 downto 0);
begin
shifted_reg : reg_generic
generic map (
reg_len => width
)
port map (
clk => clk,
en => en,
rst => rst,
reg_in => rounded_sig,
reg_out => output
);
shifted_sig <= std_logic_vector(
shift_right(
signed(input),
places
)
);
process (shifted_sig, round_up) begin
if (round_up = '1') then
rounded_sig <= std_logic_vector( signed(shifted_sig) + 1 );
else
rounded_sig <= shifted_sig;
end if;
end process;
end Behavioral;
|
<reponame>ispras/hdl-benchmarks
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: <NAME> - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
port (
clk : in std_logic;
holdn: in std_logic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_logic;
s : out std_logic_vector(31 downto 0);
co : out std_logic
);
end component;
end multlib;
------------------------------------------------------------
-- START: Entities used within the Modified Booth Recoding
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PP_LOW is
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end PP_LOW;
library ieee;
use ieee.std_logic_1164.all;
entity PP_MIDDLE is
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end PP_MIDDLE;
library ieee;
use ieee.std_logic_1164.all;
entity PP_HIGH is
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end PP_HIGH;
library ieee;
use ieee.std_logic_1164.all;
entity R_GATE is
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end R_GATE;
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end DECODER;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Entities within the Wallace-tree
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end FULL_ADDER;
library ieee;
use ieee.std_logic_1164.all;
entity HALF_ADDER is
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end HALF_ADDER;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Entities within the DBLC-tree
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity INVBLOCK is
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end INVBLOCK;
library ieee;
use ieee.std_logic_1164.all;
entity XXOR1 is
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end XXOR1;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK0 is
port
(
A,B,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK0;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1 is
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK1;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2 is
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK2;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1A is
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end BLOCK1A;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2A is
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end BLOCK2A;
library ieee;
use ieee.std_logic_1164.all;
entity PRESTAGE_64 is
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 63);
GOUT: out std_logic_vector(0 to 64)
);
end PRESTAGE_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_0_64 is
port
(
PIN: in std_logic_vector(0 to 63);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 62);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_0_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_1_64 is
port
(
PIN: in std_logic_vector(0 to 62);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 60);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_1_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_2_64 is
port
(
PIN: in std_logic_vector(0 to 60);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 56);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_2_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_3_64 is
port
(
PIN: in std_logic_vector(0 to 56);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 48);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_3_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_4_64 is
port
(
PIN: in std_logic_vector(0 to 48);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 32);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_4_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_5_64 is
port
(
PIN: in std_logic_vector(0 to 32);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_5_64;
library ieee;
use ieee.std_logic_1164.all;
entity XORSTAGE_64 is
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 64);
SUM: out std_logic_vector(0 to 63);
COUT: out std_logic
);
end XORSTAGE_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLCTREE_64 is
port
(
PIN:in std_logic_vector(0 to 63);
GIN:in std_logic_vector(0 to 64);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 64);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_64;
library ieee;
use ieee.std_logic_1164.all;
entity DBLCADDER_64_64 is
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63);
COUT:out std_logic
);
end DBLCADDER_64_64;
------------------------------------------------------------
-- END: Entities within the DBLC-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the Modified Booth recoding
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture PP_LOW of PP_LOW is
begin
PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG;
end PP_LOW;
library ieee;
use ieee.std_logic_1164.all;
architecture PP_MIDDLE of PP_MIDDLE is
begin
PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG)));
end PP_MIDDLE;
library ieee;
use ieee.std_logic_1164.all;
architecture PP_HIGH of PP_HIGH is
begin
PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG));
end PP_HIGH;
library ieee;
use ieee.std_logic_1164.all;
architecture R_GATE of R_GATE is
begin
PPBIT <= (not(INA and INB)) and INC;
end R_GATE;
library ieee;
use ieee.std_logic_1164.all;
architecture DECODER of DECODER is
begin
TWOPOS <= not(not(INA and INB and (not INC)));
TWONEG <= not(not((not INA) and (not INB) and INC));
ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA);
ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA));
end DECODER;
--
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the Wallace-tree
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture FULL_ADDER of FULL_ADDER is
signal TMP: std_logic;
begin
TMP <= DATA_A xor DATA_B;
SAVE <= TMP xor DATA_C;
CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B)));
end FULL_ADDER;
library ieee;
use ieee.std_logic_1164.all;
architecture HALF_ADDER of HALF_ADDER is
begin
SAVE <= DATA_A xor DATA_B;
CARRY <= DATA_A and DATA_B;
end HALF_ADDER;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the DBLC adder
------------------------------------------------------------
-- Architectures for the DBLC-tree
library ieee;
use ieee.std_logic_1164.all;
architecture INVBLOCK_regular of INVBLOCK is
begin
GOUT <= not GIN;
end INVBLOCK_regular;
library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK1_regular of BLOCK1 is
begin
POUT <= not(PIN1 or PIN2);
GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1_regular;
library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK2_regular of BLOCK2 is
begin
POUT <= not(PIN1 and PIN2);
GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2_regular;
library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK1A_regular of BLOCK1A is
begin
GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1A_regular;
library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK2A_regular of BLOCK2A is
begin
GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2A_regular;
library ieee;
use ieee.std_logic_1164.all;
architecture XXOR_regular of XXOR1 is
begin
SUM <= (not (A xor B)) xor GIN;
end XXOR_regular;
library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK0_regular of BLOCK0 is
begin
POUT <= not(A or B);
GOUT <= not(A and B);
end BLOCK0_regular;
library ieee;
use ieee.std_logic_1164.all;
architecture PRESTAGE of PRESTAGE_64 is
component BLOCK0
port
(
A,B,PHI: in std_logic;
POUT,GOUT: out std_logic
);
end component;
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- PRESTAGE
U1:for I in 0 to 63 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_0 of DBLC_0_64 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 64 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_1 of DBLC_1_64 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 64 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_2 of DBLC_2_64 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 64 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_3 of DBLC_3_64 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 64 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_4 of DBLC_4_64 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 64 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
-- The DBLC-tree: Level 5
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_5 of DBLC_5_64 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 64 generate
U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;
library ieee;
use ieee.std_logic_1164.all;
architecture XORSTAGE of XORSTAGE_64 is
component XXOR1
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- XORSTAGE
U2:for I in 0 to 63 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT);
end XORSTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
architecture DBLCTREE of DBLCTREE_64 is
component DBLC_0_64
port
(
PIN: in std_logic_vector(0 to 63);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 62);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_1_64
port
(
PIN: in std_logic_vector(0 to 62);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 60);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_2_64
port
(
PIN: in std_logic_vector(0 to 60);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 56);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_3_64
port
(
PIN: in std_logic_vector(0 to 56);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 48);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_4_64
port
(
PIN: in std_logic_vector(0 to 48);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 32);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_5_64
port
(
PIN: in std_logic_vector(0 to 32);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 64)
);
end component;
signal INTPROP_0: std_logic_vector(0 to 62);
signal INTGEN_0: std_logic_vector(0 to 64);
signal INTPROP_1: std_logic_vector(0 to 60);
signal INTGEN_1: std_logic_vector(0 to 64);
signal INTPROP_2: std_logic_vector(0 to 56);
signal INTGEN_2: std_logic_vector(0 to 64);
signal INTPROP_3: std_logic_vector(0 to 48);
signal INTGEN_3: std_logic_vector(0 to 64);
signal INTPROP_4: std_logic_vector(0 to 32);
signal INTGEN_4: std_logic_vector(0 to 64);
begin -- Architecture DBLCTREE
U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
architecture DBLCADDER of DBLCADDER_64_64 is
component PRESTAGE_64
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 63);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLCTREE_64
port
(
PIN:in std_logic_vector(0 to 63);
GIN:in std_logic_vector(0 to 64);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 64);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_64
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 64);
SUM: out std_logic_vector(0 to 63);
COUT: out std_logic
);
end component;
signal INTPROP: std_logic_vector(0 to 63);
signal INTGEN: std_logic_vector(0 to 64);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 64);
begin -- Architecture DBLCADDER
U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity XXOR2 is
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end XXOR2;
library ieee;
use ieee.std_logic_1164.all;
architecture XXOR_true of XXOR2 is
begin
SUM <= (A xor B) xor GIN;
end XXOR_true;
--
-- Modgen adder created Fri Aug 16 14:47:23 2002
--
library ieee;
use ieee.std_logic_1164.all;
entity DBLCADDER_32_32 is
port
(
OPA:in std_logic_vector(0 to 31);
OPB:in std_logic_vector(0 to 31);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 31);
COUT:out std_logic
);
end DBLCADDER_32_32;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_0_32 is
port
(
PIN: in std_logic_vector(0 to 31);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 30);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_0_32;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_1_32 is
port
(
PIN: in std_logic_vector(0 to 30);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 28);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_1_32;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_2_32 is
port
(
PIN: in std_logic_vector(0 to 28);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 24);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_2_32;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_3_32 is
port
(
PIN: in std_logic_vector(0 to 24);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 16);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_3_32;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_4_32 is
port
(
PIN: in std_logic_vector(0 to 16);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_4_32;
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_0 of DBLC_0_32 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 32 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_1 of DBLC_1_32 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 32 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_2 of DBLC_2_32 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 32 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_3 of DBLC_3_32 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 32 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_4 of DBLC_4_32 is
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_4
GOUT(0 to 15) <= GIN(0 to 15);
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 32 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
library ieee;
use ieee.std_logic_1164.all;
entity XORSTAGE_32 is
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 32);
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic
);
end XORSTAGE_32;
library ieee;
use ieee.std_logic_1164.all;
architecture XORSTAGE of XORSTAGE_32 is
component XXOR1
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component XXOR2
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- XORSTAGE
U2:for I in 0 to 15 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 16 to 31 generate
U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT);
end XORSTAGE;
library ieee;
use ieee.std_logic_1164.all;
entity PRESTAGE_32 is
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 31);
GOUT: out std_logic_vector(0 to 32)
);
end PRESTAGE_32;
library ieee;
use ieee.std_logic_1164.all;
architecture PRESTAGE of PRESTAGE_32 is
component BLOCK0
port
(
A,B,PHI: in std_logic;
POUT,GOUT: out std_logic
);
end component;
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- PRESTAGE
U1:for I in 0 to 31 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
entity DBLCTREE_32 is
port
(
PIN:in std_logic_vector(0 to 31);
GIN:in std_logic_vector(0 to 32);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 32);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_32;
library ieee;
use ieee.std_logic_1164.all;
architecture DBLCTREE of DBLCTREE_32 is
component DBLC_0_32
port
(
PIN: in std_logic_vector(0 to 31);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 30);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_1_32
port
(
PIN: in std_logic_vector(0 to 30);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 28);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_2_32
port
(
PIN: in std_logic_vector(0 to 28);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 24);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_3_32
port
(
PIN: in std_logic_vector(0 to 24);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 16);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_4_32
port
(
PIN: in std_logic_vector(0 to 16);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 32)
);
end component;
signal INTPROP_0: std_logic_vector(0 to 30);
signal INTGEN_0: std_logic_vector(0 to 32);
signal INTPROP_1: std_logic_vector(0 to 28);
signal INTGEN_1: std_logic_vector(0 to 32);
signal INTPROP_2: std_logic_vector(0 to 24);
signal INTGEN_2: std_logic_vector(0 to 32);
signal INTPROP_3: std_logic_vector(0 to 16);
signal INTGEN_3: std_logic_vector(0 to 32);
begin -- Architecture DBLCTREE
U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
architecture DBLCADDER of DBLCADDER_32_32 is
component PRESTAGE_32
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 31);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLCTREE_32
port
(
PIN:in std_logic_vector(0 to 31);
GIN:in std_logic_vector(0 to 32);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 32);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_32
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 32);
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic
);
end component;
signal INTPROP: std_logic_vector(0 to 31);
signal INTGEN: std_logic_vector(0 to 32);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 32);
begin -- Architecture DBLCADDER
U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PRESTAGE_128 is
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 127);
GOUT: out std_logic_vector(0 to 128)
);
end PRESTAGE_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_0_128 is
port
(
PIN: in std_logic_vector(0 to 127);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 126);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_0_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_1_128 is
port
(
PIN: in std_logic_vector(0 to 126);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 124);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_1_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_2_128 is
port
(
PIN: in std_logic_vector(0 to 124);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 120);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_2_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_3_128 is
port
(
PIN: in std_logic_vector(0 to 120);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 112);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_3_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_4_128 is
port
(
PIN: in std_logic_vector(0 to 112);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 96);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_4_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_5_128 is
port
(
PIN: in std_logic_vector(0 to 96);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 64);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_5_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLC_6_128 is
port
(
PIN: in std_logic_vector(0 to 64);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_6_128;
library ieee;
use ieee.std_logic_1164.all;
entity XORSTAGE_128 is
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 128);
SUM: out std_logic_vector(0 to 127);
COUT: out std_logic
);
end XORSTAGE_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLCTREE_128 is
port
(
PIN:in std_logic_vector(0 to 127);
GIN:in std_logic_vector(0 to 128);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 128);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_128;
library ieee;
use ieee.std_logic_1164.all;
entity DBLCADDER_128_128 is
port
(
OPA:in std_logic_vector(0 to 127);
OPB:in std_logic_vector(0 to 127);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 127);
COUT:out std_logic
);
end DBLCADDER_128_128;
library ieee;
use ieee.std_logic_1164.all;
architecture PRESTAGE of PRESTAGE_128 is
component BLOCK0
port
(
A,B,PHI: in std_logic;
POUT,GOUT: out std_logic
);
end component;
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- PRESTAGE
U1:for I in 0 to 127 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_0 of DBLC_0_128 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 128 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_1 of DBLC_1_128 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 128 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_2 of DBLC_2_128 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 128 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_3 of DBLC_3_128 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 128 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_4 of DBLC_4_128 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 128 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
-- The DBLC-tree: Level 5
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_5 of DBLC_5_128 is
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 128 generate
U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;
-- The DBLC-tree: Level 6
library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_6 of DBLC_6_128 is
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- Architecture DBLC_6
GOUT(0 to 63) <= GIN(0 to 63);
U2: for I in 64 to 127 generate
U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 128 to 128 generate
U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I));
end generate U3;
end DBLC_6;
library ieee;
use ieee.std_logic_1164.all;
architecture XORSTAGE of XORSTAGE_128 is
component XXOR1
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component XXOR2
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
begin -- XORSTAGE
U2:for I in 0 to 63 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 64 to 127 generate
U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT);
end XORSTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
architecture DBLCTREE of DBLCTREE_128 is
component DBLC_0_128
port
(
PIN: in std_logic_vector(0 to 127);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 126);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_1_128
port
(
PIN: in std_logic_vector(0 to 126);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 124);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_2_128
port
(
PIN: in std_logic_vector(0 to 124);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 120);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_3_128
port
(
PIN: in std_logic_vector(0 to 120);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 112);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_4_128
port
(
PIN: in std_logic_vector(0 to 112);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 96);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_5_128
port
(
PIN: in std_logic_vector(0 to 96);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 64);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_6_128
port
(
PIN: in std_logic_vector(0 to 64);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 128)
);
end component;
signal INTPROP_0: std_logic_vector(0 to 126);
signal INTGEN_0: std_logic_vector(0 to 128);
signal INTPROP_1: std_logic_vector(0 to 124);
signal INTGEN_1: std_logic_vector(0 to 128);
signal INTPROP_2: std_logic_vector(0 to 120);
signal INTGEN_2: std_logic_vector(0 to 128);
signal INTPROP_3: std_logic_vector(0 to 112);
signal INTGEN_3: std_logic_vector(0 to 128);
signal INTPROP_4: std_logic_vector(0 to 96);
signal INTGEN_4: std_logic_vector(0 to 128);
signal INTPROP_5: std_logic_vector(0 to 64);
signal INTGEN_5: std_logic_vector(0 to 128);
begin -- Architecture DBLCTREE
U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5);
U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
architecture DBLCADDER of DBLCADDER_128_128 is
component PRESTAGE_128
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 127);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLCTREE_128
port
(
PIN:in std_logic_vector(0 to 127);
GIN:in std_logic_vector(0 to 128);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 128);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_128
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 128);
SUM: out std_logic_vector(0 to 127);
COUT: out std_logic
);
end component;
signal INTPROP: std_logic_vector(0 to 127);
signal INTGEN: std_logic_vector(0 to 128);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 128);
begin -- Architecture DBLCADDER
U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 14:49:18 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MULTIPLIER_18_18 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 17);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
holdn: in std_logic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_18_18;
------------------------------------------------------------
-- End: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MUL_17_17 is
port(clk : in std_logic;
holdn: in std_logic;
X: in std_logic_vector(16 downto 0);
Y: in std_logic_vector(16 downto 0);
P: out std_logic_vector(33 downto 0));
end MUL_17_17;
architecture A of MUL_17_17 is
component MULTIPLIER_18_18
port(MULTIPLICAND: in std_logic_vector(0 to 17);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
holdn: in std_logic;
RESULT: out std_logic_vector(0 to 63));
end component;
signal A: std_logic_vector(0 to 17);
signal B: std_logic_vector(0 to 17);
signal Q: std_logic_vector(0 to 63);
begin
U1: MULTIPLIER_18_18 port map(A,B,CLK, holdn, Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(16);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(16);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
end A;
library ieee;
use ieee.std_logic_1164.all;
entity BOOTHCODER_18_18 is
port
(
OPA: in std_logic_vector(0 to 17);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 188)
);
end BOOTHCODER_18_18;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity WALLACE_18_18 is
port
(
SUMMAND: in std_logic_vector(0 to 188);
CARRY: out std_logic_vector(0 to 33);
SUM: out std_logic_vector(0 to 34)
);
end WALLACE_18_18;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------
--
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
architecture BOOTHCODER of BOOTHCODER_18_18 is
-- Components used in the architecture
component PP_LOW
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_MIDDLE
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_HIGH
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component R_GATE
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end component;
component DECODER
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end component;
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 17);
signal INT_MULTIPLIER: std_logic_vector(0 to 35);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
SUMMAND(100) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(101)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(109)
);
SUMMAND(110) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(118)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(102)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(111)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(119)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(126)
);
SUMMAND(127) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(134)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(103)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(112)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(120)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(128)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(135)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(141)
);
SUMMAND(142) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(148)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(104)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(113)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(121)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(129)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(136)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(143)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(149)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(154)
);
SUMMAND(155) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(105)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(114)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(122)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(130)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(137)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(144)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(150)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(156)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(161)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(165)
);
SUMMAND(166) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(170)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(106)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(115)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(123)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(131)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(138)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(145)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(151)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(157)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(162)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(167)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(171)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(174)
);
SUMMAND(175) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(178)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(107)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(116)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(124)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(132)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(139)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(146)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(152)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(158)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(163)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(168)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(172)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(176)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(179)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(181)
);
SUMMAND(182) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(184)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(108)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(117)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(125)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(133)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(140)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(147)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(153)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(159)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(164)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(169)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(173)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(177)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(180)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(183)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(185)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(186)
);
SUMMAND(187) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(188)
);
-- Begin partial product 9
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
architecture WALLACE of WALLACE_18_18 is
-- Components used in the netlist
component FULL_ADDER
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component HALF_ADDER
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 114);
signal INT_SUM: std_logic_vector(0 to 158);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin NO stage
INT_SUM(76) <= SUMMAND(108); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(77), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50),
SAVE => INT_SUM(78), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(51); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79),
SAVE => INT_SUM(80), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin NO stage
INT_SUM(81) <= INT_CARRY(52); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(82) <= INT_CARRY(53); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82),
SAVE => INT_SUM(83), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin NO stage
INT_SUM(84) <= INT_CARRY(54); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End FA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111),
SAVE => INT_SUM(85), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114),
SAVE => INT_SUM(86), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117),
SAVE => INT_SUM(87), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58),
SAVE => INT_SUM(88), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(91), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End HA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120),
SAVE => INT_SUM(92), CARRY => INT_CARRY(70)
);
---- End FA stage
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123),
SAVE => INT_SUM(93), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(94) <= SUMMAND(124); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(95) <= SUMMAND(125); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin NO stage
INT_SUM(97) <= INT_SUM(95); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63),
SAVE => INT_SUM(98), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(99), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67),
SAVE => INT_SUM(100), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin NO stage
INT_SUM(101) <= INT_CARRY(68); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(102), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(103), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70),
SAVE => INT_SUM(104), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin NO stage
INT_SUM(105) <= INT_CARRY(71); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104),
SAVE => INT_SUM(106), CARRY => INT_CARRY(79)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72),
SAVE => INT_SUM(107), CARRY => INT_CARRY(80)
);
---- End HA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73),
SAVE => INT_SUM(108), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin NO stage
INT_SUM(109) <= INT_CARRY(74); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136),
SAVE => INT_SUM(110), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139),
SAVE => INT_SUM(111), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(112) <= SUMMAND(140); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112),
SAVE => INT_SUM(113), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(114), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79),
SAVE => INT_SUM(115), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin NO stage
INT_SUM(116) <= INT_CARRY(80); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143),
SAVE => INT_SUM(117), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146),
SAVE => INT_SUM(118), CARRY => INT_CARRY(88)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= SUMMAND(147); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119),
SAVE => INT_SUM(120), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83),
SAVE => INT_SUM(121), CARRY => INT_CARRY(90)
);
---- End HA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84),
SAVE => INT_SUM(122), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= INT_CARRY(85); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150),
SAVE => INT_SUM(124), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153),
SAVE => INT_SUM(125), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(126), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin NO stage
INT_SUM(127) <= INT_CARRY(88); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89),
SAVE => INT_SUM(128), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin NO stage
INT_SUM(129) <= INT_CARRY(90); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156),
SAVE => INT_SUM(130), CARRY => INT_CARRY(96)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159),
SAVE => INT_SUM(131), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92),
SAVE => INT_SUM(132), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin NO stage
INT_SUM(133) <= INT_CARRY(93); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94),
SAVE => INT_SUM(134), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End HA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162),
SAVE => INT_SUM(135), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(163), DATA_B => SUMMAND(164),
SAVE => INT_SUM(136), CARRY => INT_CARRY(101)
);
---- End HA stage
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(137), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin NO stage
INT_SUM(138) <= INT_CARRY(97); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98),
SAVE => INT_SUM(139), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(140), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169),
SAVE => INT_SUM(141), CARRY => INT_CARRY(105)
);
---- End HA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(142), CARRY => INT_CARRY(106)
);
---- End FA stage
---- Begin NO stage
INT_SUM(143) <= INT_CARRY(101); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102),
SAVE => INT_SUM(144), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End HA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172),
SAVE => INT_SUM(145), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105),
SAVE => INT_SUM(146), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106),
SAVE => INT_SUM(147), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(148), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin NO stage
INT_SUM(149) <= SUMMAND(177); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108),
SAVE => INT_SUM(150), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin NO stage
INT_SUM(151) <= INT_CARRY(109); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180),
SAVE => INT_SUM(152), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin NO stage
INT_SUM(153) <= INT_SUM(152); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(154) <= INT_CARRY(111); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183),
SAVE => INT_SUM(155), CARRY => INT_CARRY(114)
);
---- End FA stage
---- Begin NO stage
INT_SUM(156) <= INT_CARRY(113); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(155), DATA_B => INT_SUM(156),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End HA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin NO stage
INT_SUM(157) <= SUMMAND(184); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(158) <= SUMMAND(185); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(186), DATA_B => SUMMAND(187),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End HA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin NO stage
SUM(34) <= SUMMAND(188); -- At Level 5
---- End NO stage
-- End WT-branch 35
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
architecture RTL of MULTIPLIER_18_18 is
component BOOTHCODER_18_18
port
(
OPA: in std_logic_vector(0 to 17);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 188)
);
end component;
component WALLACE_18_18
port
(
SUMMAND: in std_logic_vector(0 to 188);
CARRY: out std_logic_vector(0 to 33);
SUM: out std_logic_vector(0 to 34)
);
end component;
component DBLCADDER_64_64
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63)
);
end component;
signal PPBIT:std_logic_vector(0 to 188);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_CARRYR: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal INT_SUMR: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_18_18
port map
(
OPA(0 to 17) => MULTIPLICAND(0 to 17),
OPB(0 to 17) => MULTIPLIER(0 to 17),
SUMMAND(0 to 188) => PPBIT(0 to 188)
);
W:WALLACE_18_18
port map
(
SUMMAND(0 to 188) => PPBIT(0 to 188),
CARRY(0 to 33) => INT_CARRY(1 to 34),
SUM(0 to 34) => INT_SUM(0 to 34)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(35) <= LOGIC_ZERO;
INT_CARRY(36) <= LOGIC_ZERO;
INT_CARRY(37) <= LOGIC_ZERO;
INT_CARRY(38) <= LOGIC_ZERO;
INT_CARRY(39) <= LOGIC_ZERO;
INT_CARRY(40) <= LOGIC_ZERO;
INT_CARRY(41) <= LOGIC_ZERO;
INT_CARRY(42) <= LOGIC_ZERO;
INT_CARRY(43) <= LOGIC_ZERO;
INT_CARRY(44) <= LOGIC_ZERO;
INT_CARRY(45) <= LOGIC_ZERO;
INT_CARRY(46) <= LOGIC_ZERO;
INT_CARRY(47) <= LOGIC_ZERO;
INT_CARRY(48) <= LOGIC_ZERO;
INT_CARRY(49) <= LOGIC_ZERO;
INT_CARRY(50) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(35) <= LOGIC_ZERO;
INT_SUM(36) <= LOGIC_ZERO;
INT_SUM(37) <= LOGIC_ZERO;
INT_SUM(38) <= LOGIC_ZERO;
INT_SUM(39) <= LOGIC_ZERO;
INT_SUM(40) <= LOGIC_ZERO;
INT_SUM(41) <= LOGIC_ZERO;
INT_SUM(42) <= LOGIC_ZERO;
INT_SUM(43) <= LOGIC_ZERO;
INT_SUM(44) <= LOGIC_ZERO;
INT_SUM(45) <= LOGIC_ZERO;
INT_SUM(46) <= LOGIC_ZERO;
INT_SUM(47) <= LOGIC_ZERO;
INT_SUM(48) <= LOGIC_ZERO;
INT_SUM(49) <= LOGIC_ZERO;
INT_SUM(50) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
INT_SUMR(35 to 63) <= INT_SUM(35 to 63);
INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63);
INT_CARRYR(0) <= INT_CARRY(0);
reg : if MULPIPE generate
process (PHI) begin
if rising_edge(PHI ) then
if (holdn = '1') then
INT_SUMR(0 to 34) <= INT_SUM(0 to 34);
INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34);
end if;
end if;
end process;
end generate;
noreg : if not MULPIPE generate
INT_SUMR(0 to 34) <= INT_SUM(0 to 34);
INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34);
end generate;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUMR(0 to 63),
OPB(0 to 63) => INT_CARRYR(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI ,
SUM(0 to 63) => RESULT(0 to 63)
);
end RTL;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 14:55:21 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MULTIPLIER_34_10 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 9);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_34_10;
------------------------------------------------------------
-- End: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MUL_33_9 is
port(X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(8 downto 0);
P: out std_logic_vector(41 downto 0));
end MUL_33_9;
library ieee;
use ieee.std_logic_1164.all;
architecture A of MUL_33_9 is
component MULTIPLIER_34_10
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 9);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63));
end component;
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 9);
signal Q: std_logic_vector(0 to 63);
signal CLK: std_logic;
begin
U1: MULTIPLIER_34_10 port map(A,B,CLK,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(8);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
end A;
------------------------------------------------------------
-- END: Top entity
------------------------------------------------------------
-- Form data:
-- Operation=3 (1=Adder,2=Subtracter,3=Multiplier,4=Squarer,5=Mult-Wallace trees,6=Register)
-- Operand width A=33
-- Operand width B=9
-- Buffers=4 (1=Inputs,2=Outputs,3=Both,4=None)
-- Booth rec.=1 (1=Yes,2=No)
-- Pipelining=2 (1=Yes,2=no,3=1step,4=2steps)
-- Pipe steps=0
-- Pipe offset=0
-- Truncation=2 (1=Yes,2=No)
-- Trunclsbs=0
-- Customwallace=2 (1=Yes,2=No,3=Yes by op widths)
-- Wallace #std_logics in columns (MSB to LSB):
-- Out format=3 (1=VHDL,2=Verilog,3=VHDL+std_logic)
-- Verbose=2 (1=Yes,2=No)
-- Accumulate=2 (1=Yes,2=No)
-- Acc width=0
-- Carry-save output=2 (1=Yes,2=No)
--
-- mgen_14764.vhd: Entity descriptions created at Fri Aug 16 14:55:21 2002
--
library ieee;
use ieee.std_logic_1164.all;
entity BOOTHCODER_34_10 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 9);
SUMMAND: out std_logic_vector(0 to 184)
);
end BOOTHCODER_34_10;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity WALLACE_34_10 is
port
(
SUMMAND: in std_logic_vector(0 to 184);
CARRY: out std_logic_vector(0 to 41);
SUM: out std_logic_vector(0 to 42)
);
end WALLACE_34_10;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture BOOTHCODER of BOOTHCODER_34_10 is
-- Components used in the architecture
component PP_LOW
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_MIDDLE
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_HIGH
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component R_GATE
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end component;
component DECODER
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end component;
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 19);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(40)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(45)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(50)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(55)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(60)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(65)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(70)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(75)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(85)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(95)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(100)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(105)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(110)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(115)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(120)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(125)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(130)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(135)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(140)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(145)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(150)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(155)
);
SUMMAND(156) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(41)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(46)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(51)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(56)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(61)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(66)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(71)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(76)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(86)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(96)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(101)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(106)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(111)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(116)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(121)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(126)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(131)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(136)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(141)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(146)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(151)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(157)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(161)
);
SUMMAND(162) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(166)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(42)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(47)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(52)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(57)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(62)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(67)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(72)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(77)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(87)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(97)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(102)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(107)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(112)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(117)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(122)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(127)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(132)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(137)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(142)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(147)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(152)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(158)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(163)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(167)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(170)
);
SUMMAND(171) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(174)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(43)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(48)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(53)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(58)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(63)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(68)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(73)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(78)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(88)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(98)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(103)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(108)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(113)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(118)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(123)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(128)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(133)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(138)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(143)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(148)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(153)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(159)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(164)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(168)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(172)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(175)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(177)
);
SUMMAND(178) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(180)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(44)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(49)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(54)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(59)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(64)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(69)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(74)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(79)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(89)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(99)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(104)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(109)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(114)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(119)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(124)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(129)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(134)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(139)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(144)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(149)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(154)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(165)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(169)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(173)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(176)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(179)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(181)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(182)
);
SUMMAND(183) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(184)
);
-- Begin partial product 5
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the Wallace-tree
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
architecture WALLACE of WALLACE_34_10 is
-- Components used in the netlist
component FULL_ADDER
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component HALF_ADDER
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 95);
signal INT_SUM: std_logic_vector(0 to 133);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End HA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9),
SAVE => INT_SUM(18), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin NO stage
INT_SUM(19) <= INT_CARRY(10); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End FA stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(43), DATA_B => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End HA stage
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin NO stage
INT_SUM(23) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End FA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(24), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End HA stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15),
SAVE => INT_SUM(26), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin NO stage
INT_SUM(27) <= INT_CARRY(16); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End FA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(53), DATA_B => SUMMAND(54),
SAVE => INT_SUM(29), CARRY => INT_CARRY(22)
);
---- End HA stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(30), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin NO stage
INT_SUM(31) <= INT_CARRY(19); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57),
SAVE => INT_SUM(32), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(58), DATA_B => SUMMAND(59),
SAVE => INT_SUM(33), CARRY => INT_CARRY(25)
);
---- End HA stage
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21),
SAVE => INT_SUM(34), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(35) <= INT_CARRY(22); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62),
SAVE => INT_SUM(36), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64),
SAVE => INT_SUM(37), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24),
SAVE => INT_SUM(38), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(39) <= INT_CARRY(25); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67),
SAVE => INT_SUM(40), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(68), DATA_B => SUMMAND(69),
SAVE => INT_SUM(41), CARRY => INT_CARRY(31)
);
---- End HA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(42), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin NO stage
INT_SUM(43) <= INT_CARRY(28); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(73), DATA_B => SUMMAND(74),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(31); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End FA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End HA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End FA stage
---- Begin NO stage
INT_SUM(51) <= INT_CARRY(34); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End FA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(52), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84),
SAVE => INT_SUM(53), CARRY => INT_CARRY(40)
);
---- End HA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36),
SAVE => INT_SUM(54), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(55) <= INT_CARRY(37); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End FA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87),
SAVE => INT_SUM(56), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(88), DATA_B => SUMMAND(89),
SAVE => INT_SUM(57), CARRY => INT_CARRY(43)
);
---- End HA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39),
SAVE => INT_SUM(58), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(59) <= INT_CARRY(40); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(60), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94),
SAVE => INT_SUM(61), CARRY => INT_CARRY(46)
);
---- End HA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin NO stage
INT_SUM(63) <= INT_CARRY(43); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97),
SAVE => INT_SUM(64), CARRY => INT_CARRY(48)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(98), DATA_B => SUMMAND(99),
SAVE => INT_SUM(65), CARRY => INT_CARRY(49)
);
---- End HA stage
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(66), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin NO stage
INT_SUM(67) <= INT_CARRY(46); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102),
SAVE => INT_SUM(68), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(103), DATA_B => SUMMAND(104),
SAVE => INT_SUM(69), CARRY => INT_CARRY(52)
);
---- End HA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48),
SAVE => INT_SUM(70), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin NO stage
INT_SUM(71) <= INT_CARRY(49); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(72), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(108), DATA_B => SUMMAND(109),
SAVE => INT_SUM(73), CARRY => INT_CARRY(55)
);
---- End HA stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51),
SAVE => INT_SUM(74), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin NO stage
INT_SUM(75) <= INT_CARRY(52); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112),
SAVE => INT_SUM(76), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(113), DATA_B => SUMMAND(114),
SAVE => INT_SUM(77), CARRY => INT_CARRY(58)
);
---- End HA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(78), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(55); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End FA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117),
SAVE => INT_SUM(80), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(118), DATA_B => SUMMAND(119),
SAVE => INT_SUM(81), CARRY => INT_CARRY(61)
);
---- End HA stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57),
SAVE => INT_SUM(82), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin NO stage
INT_SUM(83) <= INT_CARRY(58); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End FA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(84), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124),
SAVE => INT_SUM(85), CARRY => INT_CARRY(64)
);
---- End HA stage
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60),
SAVE => INT_SUM(86), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin NO stage
INT_SUM(87) <= INT_CARRY(61); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End FA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127),
SAVE => INT_SUM(88), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(128), DATA_B => SUMMAND(129),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End HA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(91) <= INT_CARRY(64); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End FA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132),
SAVE => INT_SUM(92), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(133), DATA_B => SUMMAND(134),
SAVE => INT_SUM(93), CARRY => INT_CARRY(70)
);
---- End HA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(94), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(67); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139),
SAVE => INT_SUM(97), CARRY => INT_CARRY(73)
);
---- End HA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69),
SAVE => INT_SUM(98), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin NO stage
INT_SUM(99) <= INT_CARRY(70); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142),
SAVE => INT_SUM(100), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(143), DATA_B => SUMMAND(144),
SAVE => INT_SUM(101), CARRY => INT_CARRY(76)
);
---- End HA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(102), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin NO stage
INT_SUM(103) <= INT_CARRY(73); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End FA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147),
SAVE => INT_SUM(104), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(148), DATA_B => SUMMAND(149),
SAVE => INT_SUM(105), CARRY => INT_CARRY(79)
);
---- End HA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(106), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin NO stage
INT_SUM(107) <= INT_CARRY(76); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152),
SAVE => INT_SUM(108), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(153), DATA_B => SUMMAND(154),
SAVE => INT_SUM(109), CARRY => INT_CARRY(82)
);
---- End HA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(110), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(111) <= INT_CARRY(79); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End FA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157),
SAVE => INT_SUM(112), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160),
SAVE => INT_SUM(113), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81),
SAVE => INT_SUM(114), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin NO stage
INT_SUM(115) <= INT_CARRY(82); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163),
SAVE => INT_SUM(116), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(164), DATA_B => SUMMAND(165),
SAVE => INT_SUM(117), CARRY => INT_CARRY(88)
);
---- End HA stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84),
SAVE => INT_SUM(118), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= INT_CARRY(85); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End FA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168),
SAVE => INT_SUM(120), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin NO stage
INT_SUM(121) <= SUMMAND(169); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(122), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= INT_CARRY(88); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172),
SAVE => INT_SUM(124), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin NO stage
INT_SUM(125) <= SUMMAND(173); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90),
SAVE => INT_SUM(126), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End HA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(127), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin NO stage
INT_SUM(128) <= INT_SUM(127); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(129) <= INT_CARRY(92); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(130), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin NO stage
INT_SUM(131) <= INT_CARRY(94); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(130), DATA_B => INT_SUM(131),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End HA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin NO stage
INT_SUM(132) <= SUMMAND(180); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(133) <= SUMMAND(181); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(182), DATA_B => SUMMAND(183),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End HA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin NO stage
SUM(42) <= SUMMAND(184); -- At Level 3
---- End NO stage
-- End WT-branch 43
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture RTL of MULTIPLIER_34_10 is
component BOOTHCODER_34_10
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 9);
SUMMAND: out std_logic_vector(0 to 184)
);
end component;
component WALLACE_34_10
port
(
SUMMAND: in std_logic_vector(0 to 184);
CARRY: out std_logic_vector(0 to 41);
SUM: out std_logic_vector(0 to 42)
);
end component;
component DBLCADDER_64_64
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63)
);
end component;
signal PPBIT:std_logic_vector(0 to 184);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_10
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 9) => MULTIPLIER(0 to 9),
SUMMAND(0 to 184) => PPBIT(0 to 184)
);
W:WALLACE_34_10
port map
(
SUMMAND(0 to 184) => PPBIT(0 to 184),
CARRY(0 to 41) => INT_CARRY(1 to 42),
SUM(0 to 42) => INT_SUM(0 to 42)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(43) <= LOGIC_ZERO;
INT_CARRY(44) <= LOGIC_ZERO;
INT_CARRY(45) <= LOGIC_ZERO;
INT_CARRY(46) <= LOGIC_ZERO;
INT_CARRY(47) <= LOGIC_ZERO;
INT_CARRY(48) <= LOGIC_ZERO;
INT_CARRY(49) <= LOGIC_ZERO;
INT_CARRY(50) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(43) <= LOGIC_ZERO;
INT_SUM(44) <= LOGIC_ZERO;
INT_SUM(45) <= LOGIC_ZERO;
INT_SUM(46) <= LOGIC_ZERO;
INT_SUM(47) <= LOGIC_ZERO;
INT_SUM(48) <= LOGIC_ZERO;
INT_SUM(49) <= LOGIC_ZERO;
INT_SUM(50) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUM(0 to 63),
OPB(0 to 63) => INT_CARRY(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 63) => RESULT(0 to 63)
);
end RTL;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 16:29:15 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MULTIPLIER_34_18 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_34_18;
------------------------------------------------------------
-- End: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MUL_33_17 is
port(X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(16 downto 0);
P: out std_logic_vector(49 downto 0));
end MUL_33_17;
library ieee;
use ieee.std_logic_1164.all;
architecture A of MUL_33_17 is
component MULTIPLIER_34_18
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63));
end component;
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 17);
signal Q: std_logic_vector(0 to 63);
signal CLK: std_logic;
begin
U1: MULTIPLIER_34_18 port map(A,B,CLK,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(16);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
P(42) <= Q(42);
P(43) <= Q(43);
P(44) <= Q(44);
P(45) <= Q(45);
P(46) <= Q(46);
P(47) <= Q(47);
P(48) <= Q(48);
P(49) <= Q(49);
end A;
------------------------------------------------------------
-- END: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity BOOTHCODER_34_18 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 332)
);
end BOOTHCODER_34_18;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Entities within the Wallace-tree
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity WALLACE_34_18 is
port
(
SUMMAND: in std_logic_vector(0 to 332);
CARRY: out std_logic_vector(0 to 49);
SUM: out std_logic_vector(0 to 50)
);
end WALLACE_34_18;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------
--
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
architecture BOOTHCODER of BOOTHCODER_34_18 is
-- Components used in the architecture
component PP_LOW
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_MIDDLE
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_HIGH
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component R_GATE
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end component;
component DECODER
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end component;
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 35);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(108)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(117)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(126)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(135)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(144)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(153)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(162)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(171)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(180)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(189)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(198)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(207)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(216)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(225)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(234)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(243)
);
SUMMAND(244) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(100)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(109)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(118)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(127)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(136)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(145)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(154)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(163)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(172)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(181)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(190)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(199)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(208)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(217)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(226)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(235)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(245)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(253)
);
SUMMAND(254) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(262)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(101)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(110)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(119)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(128)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(137)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(146)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(155)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(164)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(173)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(182)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(191)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(200)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(209)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(218)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(227)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(236)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(246)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(255)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(263)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(270)
);
SUMMAND(271) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(278)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(102)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(111)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(120)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(129)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(138)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(147)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(156)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(165)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(174)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(183)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(192)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(201)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(210)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(219)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(228)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(237)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(247)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(256)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(264)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(272)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(279)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(285)
);
SUMMAND(286) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(292)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(103)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(112)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(121)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(130)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(139)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(148)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(157)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(166)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(175)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(184)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(193)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(202)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(211)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(220)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(229)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(238)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(248)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(257)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(265)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(273)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(280)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(287)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(293)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(298)
);
SUMMAND(299) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(304)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_165:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_166:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_167:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_168:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_169:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_170:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_171:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_172:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(104)
);
PPM_173:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(113)
);
PPM_174:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(122)
);
PPM_175:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(131)
);
PPM_176:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(140)
);
PPM_177:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(149)
);
PPM_178:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(158)
);
PPM_179:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(167)
);
PPM_180:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(176)
);
PPM_181:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(185)
);
PPM_182:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(194)
);
PPM_183:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(203)
);
PPM_184:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(212)
);
PPM_185:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(221)
);
PPM_186:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(230)
);
PPM_187:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(239)
);
PPM_188:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(249)
);
PPM_189:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(258)
);
PPM_190:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(266)
);
PPM_191:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(274)
);
PPM_192:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(281)
);
PPM_193:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(288)
);
PPM_194:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(294)
);
PPM_195:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(300)
);
PPM_196:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(305)
);
PPM_197:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(309)
);
SUMMAND(310) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(314)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_198:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_199:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_200:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_201:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_202:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_203:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(105)
);
PPM_204:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(114)
);
PPM_205:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(123)
);
PPM_206:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(132)
);
PPM_207:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(141)
);
PPM_208:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(150)
);
PPM_209:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(159)
);
PPM_210:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(168)
);
PPM_211:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(177)
);
PPM_212:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(186)
);
PPM_213:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(195)
);
PPM_214:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(204)
);
PPM_215:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(213)
);
PPM_216:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(222)
);
PPM_217:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(231)
);
PPM_218:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(240)
);
PPM_219:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(250)
);
PPM_220:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(259)
);
PPM_221:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(267)
);
PPM_222:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(275)
);
PPM_223:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(282)
);
PPM_224:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(289)
);
PPM_225:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(295)
);
PPM_226:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(301)
);
PPM_227:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(306)
);
PPM_228:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(311)
);
PPM_229:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(315)
);
PPM_230:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(318)
);
SUMMAND(319) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(322)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_231:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_232:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_233:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_234:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(106)
);
PPM_235:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(115)
);
PPM_236:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(124)
);
PPM_237:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(133)
);
PPM_238:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(142)
);
PPM_239:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(151)
);
PPM_240:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(160)
);
PPM_241:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(169)
);
PPM_242:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(178)
);
PPM_243:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(187)
);
PPM_244:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(196)
);
PPM_245:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(205)
);
PPM_246:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(214)
);
PPM_247:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(223)
);
PPM_248:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(232)
);
PPM_249:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(241)
);
PPM_250:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(251)
);
PPM_251:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(260)
);
PPM_252:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(268)
);
PPM_253:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(276)
);
PPM_254:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(283)
);
PPM_255:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(290)
);
PPM_256:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(296)
);
PPM_257:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(302)
);
PPM_258:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(307)
);
PPM_259:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(312)
);
PPM_260:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(316)
);
PPM_261:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(320)
);
PPM_262:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(323)
);
PPM_263:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(325)
);
SUMMAND(326) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(328)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_264:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_265:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(107)
);
PPM_266:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(116)
);
PPM_267:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(125)
);
PPM_268:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(134)
);
PPM_269:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(143)
);
PPM_270:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(152)
);
PPM_271:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(161)
);
PPM_272:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(170)
);
PPM_273:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(179)
);
PPM_274:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(188)
);
PPM_275:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(197)
);
PPM_276:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(206)
);
PPM_277:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(215)
);
PPM_278:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(224)
);
PPM_279:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(233)
);
PPM_280:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(242)
);
PPM_281:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(252)
);
PPM_282:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(261)
);
PPM_283:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(269)
);
PPM_284:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(277)
);
PPM_285:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(284)
);
PPM_286:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(291)
);
PPM_287:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(297)
);
PPM_288:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(303)
);
PPM_289:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(308)
);
PPM_290:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(313)
);
PPM_291:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(317)
);
PPM_292:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(321)
);
PPM_293:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(324)
);
PPM_294:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(327)
);
PPM_295:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(329)
);
PPM_296:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(330)
);
SUMMAND(331) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(332)
);
-- Begin partial product 9
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the Wallace-tree
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
architecture WALLACE of WALLACE_34_18 is
-- Components used in the netlist
component FULL_ADDER
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component HALF_ADDER
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 226);
signal INT_SUM: std_logic_vector(0 to 286);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(76), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51),
SAVE => INT_SUM(77), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52),
SAVE => INT_SUM(78), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(53); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(80), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End HA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110),
SAVE => INT_SUM(81), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113),
SAVE => INT_SUM(82), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116),
SAVE => INT_SUM(83), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83),
SAVE => INT_SUM(84), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58),
SAVE => INT_SUM(85), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59),
SAVE => INT_SUM(86), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(87) <= INT_CARRY(60); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(88), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End HA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119),
SAVE => INT_SUM(89), CARRY => INT_CARRY(70)
);
---- End FA stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(90), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125),
SAVE => INT_SUM(91), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91),
SAVE => INT_SUM(92), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65),
SAVE => INT_SUM(93), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(94), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(67); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68),
SAVE => INT_SUM(96), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End HA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(97), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(98), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134),
SAVE => INT_SUM(99), CARRY => INT_CARRY(79)
);
---- End FA stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99),
SAVE => INT_SUM(100), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(101), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73),
SAVE => INT_SUM(102), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin NO stage
INT_SUM(103) <= INT_CARRY(74); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(104), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End HA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(105), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140),
SAVE => INT_SUM(106), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143),
SAVE => INT_SUM(107), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107),
SAVE => INT_SUM(108), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79),
SAVE => INT_SUM(109), CARRY => INT_CARRY(88)
);
---- End FA stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80),
SAVE => INT_SUM(110), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(111) <= INT_CARRY(81); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82),
SAVE => INT_SUM(112), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End HA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146),
SAVE => INT_SUM(113), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149),
SAVE => INT_SUM(114), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152),
SAVE => INT_SUM(115), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115),
SAVE => INT_SUM(116), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86),
SAVE => INT_SUM(117), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(118), CARRY => INT_CARRY(96)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= INT_CARRY(88); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89),
SAVE => INT_SUM(120), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End HA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155),
SAVE => INT_SUM(121), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158),
SAVE => INT_SUM(122), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161),
SAVE => INT_SUM(123), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123),
SAVE => INT_SUM(124), CARRY => INT_CARRY(101)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93),
SAVE => INT_SUM(125), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94),
SAVE => INT_SUM(126), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin NO stage
INT_SUM(127) <= INT_CARRY(95); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(128), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End HA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164),
SAVE => INT_SUM(129), CARRY => INT_CARRY(105)
);
---- End FA stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(130), CARRY => INT_CARRY(106)
);
---- End FA stage
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170),
SAVE => INT_SUM(131), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131),
SAVE => INT_SUM(132), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(133), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101),
SAVE => INT_SUM(134), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin NO stage
INT_SUM(135) <= INT_CARRY(102); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103),
SAVE => INT_SUM(136), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End HA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173),
SAVE => INT_SUM(137), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(138), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(139), CARRY => INT_CARRY(114)
);
---- End FA stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139),
SAVE => INT_SUM(140), CARRY => INT_CARRY(115)
);
---- End FA stage
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107),
SAVE => INT_SUM(141), CARRY => INT_CARRY(116)
);
---- End FA stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108),
SAVE => INT_SUM(142), CARRY => INT_CARRY(117)
);
---- End FA stage
---- Begin NO stage
INT_SUM(143) <= INT_CARRY(109); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110),
SAVE => INT_SUM(144), CARRY => INT_CARRY(118)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182),
SAVE => INT_SUM(145), CARRY => INT_CARRY(119)
);
---- End FA stage
---- Begin FA stage
FA_121:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185),
SAVE => INT_SUM(146), CARRY => INT_CARRY(120)
);
---- End FA stage
---- Begin FA stage
FA_122:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188),
SAVE => INT_SUM(147), CARRY => INT_CARRY(121)
);
---- End FA stage
---- Begin FA stage
FA_123:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147),
SAVE => INT_SUM(148), CARRY => INT_CARRY(122)
);
---- End FA stage
---- Begin FA stage
FA_124:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114),
SAVE => INT_SUM(149), CARRY => INT_CARRY(123)
);
---- End FA stage
---- Begin FA stage
FA_125:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115),
SAVE => INT_SUM(150), CARRY => INT_CARRY(124)
);
---- End FA stage
---- Begin NO stage
INT_SUM(151) <= INT_CARRY(116); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_126:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117),
SAVE => INT_SUM(152), CARRY => INT_CARRY(125)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End HA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_127:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191),
SAVE => INT_SUM(153), CARRY => INT_CARRY(126)
);
---- End FA stage
---- Begin FA stage
FA_128:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194),
SAVE => INT_SUM(154), CARRY => INT_CARRY(127)
);
---- End FA stage
---- Begin FA stage
FA_129:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197),
SAVE => INT_SUM(155), CARRY => INT_CARRY(128)
);
---- End FA stage
---- Begin FA stage
FA_130:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155),
SAVE => INT_SUM(156), CARRY => INT_CARRY(129)
);
---- End FA stage
---- Begin FA stage
FA_131:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121),
SAVE => INT_SUM(157), CARRY => INT_CARRY(130)
);
---- End FA stage
---- Begin FA stage
FA_132:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122),
SAVE => INT_SUM(158), CARRY => INT_CARRY(131)
);
---- End FA stage
---- Begin NO stage
INT_SUM(159) <= INT_CARRY(123); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_133:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124),
SAVE => INT_SUM(160), CARRY => INT_CARRY(132)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_134:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200),
SAVE => INT_SUM(161), CARRY => INT_CARRY(133)
);
---- End FA stage
---- Begin FA stage
FA_135:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203),
SAVE => INT_SUM(162), CARRY => INT_CARRY(134)
);
---- End FA stage
---- Begin FA stage
FA_136:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206),
SAVE => INT_SUM(163), CARRY => INT_CARRY(135)
);
---- End FA stage
---- Begin FA stage
FA_137:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163),
SAVE => INT_SUM(164), CARRY => INT_CARRY(136)
);
---- End FA stage
---- Begin FA stage
FA_138:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128),
SAVE => INT_SUM(165), CARRY => INT_CARRY(137)
);
---- End FA stage
---- Begin FA stage
FA_139:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129),
SAVE => INT_SUM(166), CARRY => INT_CARRY(138)
);
---- End FA stage
---- Begin NO stage
INT_SUM(167) <= INT_CARRY(130); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_140:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131),
SAVE => INT_SUM(168), CARRY => INT_CARRY(139)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End HA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_141:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209),
SAVE => INT_SUM(169), CARRY => INT_CARRY(140)
);
---- End FA stage
---- Begin FA stage
FA_142:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212),
SAVE => INT_SUM(170), CARRY => INT_CARRY(141)
);
---- End FA stage
---- Begin FA stage
FA_143:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215),
SAVE => INT_SUM(171), CARRY => INT_CARRY(142)
);
---- End FA stage
---- Begin FA stage
FA_144:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171),
SAVE => INT_SUM(172), CARRY => INT_CARRY(143)
);
---- End FA stage
---- Begin FA stage
FA_145:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135),
SAVE => INT_SUM(173), CARRY => INT_CARRY(144)
);
---- End FA stage
---- Begin FA stage
FA_146:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136),
SAVE => INT_SUM(174), CARRY => INT_CARRY(145)
);
---- End FA stage
---- Begin NO stage
INT_SUM(175) <= INT_CARRY(137); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_147:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138),
SAVE => INT_SUM(176), CARRY => INT_CARRY(146)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End HA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_148:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218),
SAVE => INT_SUM(177), CARRY => INT_CARRY(147)
);
---- End FA stage
---- Begin FA stage
FA_149:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221),
SAVE => INT_SUM(178), CARRY => INT_CARRY(148)
);
---- End FA stage
---- Begin FA stage
FA_150:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224),
SAVE => INT_SUM(179), CARRY => INT_CARRY(149)
);
---- End FA stage
---- Begin FA stage
FA_151:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179),
SAVE => INT_SUM(180), CARRY => INT_CARRY(150)
);
---- End FA stage
---- Begin FA stage
FA_152:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142),
SAVE => INT_SUM(181), CARRY => INT_CARRY(151)
);
---- End FA stage
---- Begin FA stage
FA_153:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143),
SAVE => INT_SUM(182), CARRY => INT_CARRY(152)
);
---- End FA stage
---- Begin NO stage
INT_SUM(183) <= INT_CARRY(144); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_154:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145),
SAVE => INT_SUM(184), CARRY => INT_CARRY(153)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End HA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_155:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227),
SAVE => INT_SUM(185), CARRY => INT_CARRY(154)
);
---- End FA stage
---- Begin FA stage
FA_156:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230),
SAVE => INT_SUM(186), CARRY => INT_CARRY(155)
);
---- End FA stage
---- Begin FA stage
FA_157:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233),
SAVE => INT_SUM(187), CARRY => INT_CARRY(156)
);
---- End FA stage
---- Begin FA stage
FA_158:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187),
SAVE => INT_SUM(188), CARRY => INT_CARRY(157)
);
---- End FA stage
---- Begin FA stage
FA_159:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149),
SAVE => INT_SUM(189), CARRY => INT_CARRY(158)
);
---- End FA stage
---- Begin FA stage
FA_160:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150),
SAVE => INT_SUM(190), CARRY => INT_CARRY(159)
);
---- End FA stage
---- Begin NO stage
INT_SUM(191) <= INT_CARRY(151); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_161:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152),
SAVE => INT_SUM(192), CARRY => INT_CARRY(160)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End HA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_162:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236),
SAVE => INT_SUM(193), CARRY => INT_CARRY(161)
);
---- End FA stage
---- Begin FA stage
FA_163:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239),
SAVE => INT_SUM(194), CARRY => INT_CARRY(162)
);
---- End FA stage
---- Begin FA stage
FA_164:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242),
SAVE => INT_SUM(195), CARRY => INT_CARRY(163)
);
---- End FA stage
---- Begin FA stage
FA_165:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195),
SAVE => INT_SUM(196), CARRY => INT_CARRY(164)
);
---- End FA stage
---- Begin FA stage
FA_166:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156),
SAVE => INT_SUM(197), CARRY => INT_CARRY(165)
);
---- End FA stage
---- Begin FA stage
FA_167:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157),
SAVE => INT_SUM(198), CARRY => INT_CARRY(166)
);
---- End FA stage
---- Begin NO stage
INT_SUM(199) <= INT_CARRY(158); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_168:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159),
SAVE => INT_SUM(200), CARRY => INT_CARRY(167)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End HA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_169:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245),
SAVE => INT_SUM(201), CARRY => INT_CARRY(168)
);
---- End FA stage
---- Begin FA stage
FA_170:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248),
SAVE => INT_SUM(202), CARRY => INT_CARRY(169)
);
---- End FA stage
---- Begin FA stage
FA_171:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251),
SAVE => INT_SUM(203), CARRY => INT_CARRY(170)
);
---- End FA stage
---- Begin NO stage
INT_SUM(204) <= SUMMAND(252); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_172:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203),
SAVE => INT_SUM(205), CARRY => INT_CARRY(171)
);
---- End FA stage
---- Begin FA stage
FA_173:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162),
SAVE => INT_SUM(206), CARRY => INT_CARRY(172)
);
---- End FA stage
---- Begin NO stage
INT_SUM(207) <= INT_CARRY(163); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_174:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207),
SAVE => INT_SUM(208), CARRY => INT_CARRY(173)
);
---- End FA stage
---- Begin NO stage
INT_SUM(209) <= INT_CARRY(164); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(210) <= INT_CARRY(165); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_175:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210),
SAVE => INT_SUM(211), CARRY => INT_CARRY(174)
);
---- End FA stage
---- Begin NO stage
INT_SUM(212) <= INT_CARRY(166); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_176:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_177:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255),
SAVE => INT_SUM(213), CARRY => INT_CARRY(175)
);
---- End FA stage
---- Begin FA stage
FA_178:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258),
SAVE => INT_SUM(214), CARRY => INT_CARRY(176)
);
---- End FA stage
---- Begin FA stage
FA_179:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261),
SAVE => INT_SUM(215), CARRY => INT_CARRY(177)
);
---- End FA stage
---- Begin FA stage
FA_180:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170),
SAVE => INT_SUM(216), CARRY => INT_CARRY(178)
);
---- End FA stage
---- Begin FA stage
FA_181:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215),
SAVE => INT_SUM(217), CARRY => INT_CARRY(179)
);
---- End FA stage
---- Begin FA stage
FA_182:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172),
SAVE => INT_SUM(218), CARRY => INT_CARRY(180)
);
---- End FA stage
---- Begin FA stage
FA_183:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173),
SAVE => INT_SUM(219), CARRY => INT_CARRY(181)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End HA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_184:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264),
SAVE => INT_SUM(220), CARRY => INT_CARRY(182)
);
---- End FA stage
---- Begin FA stage
FA_185:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267),
SAVE => INT_SUM(221), CARRY => INT_CARRY(183)
);
---- End FA stage
---- Begin NO stage
INT_SUM(222) <= SUMMAND(268); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(223) <= SUMMAND(269); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_186:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222),
SAVE => INT_SUM(224), CARRY => INT_CARRY(184)
);
---- End FA stage
---- Begin NO stage
INT_SUM(225) <= INT_SUM(223); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_187:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175),
SAVE => INT_SUM(226), CARRY => INT_CARRY(185)
);
---- End FA stage
---- Begin FA stage
FA_188:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178),
SAVE => INT_SUM(227), CARRY => INT_CARRY(186)
);
---- End FA stage
---- Begin FA stage
FA_189:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179),
SAVE => INT_SUM(228), CARRY => INT_CARRY(187)
);
---- End FA stage
---- Begin NO stage
INT_SUM(229) <= INT_CARRY(180); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_190:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_191:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272),
SAVE => INT_SUM(230), CARRY => INT_CARRY(188)
);
---- End FA stage
---- Begin FA stage
FA_192:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275),
SAVE => INT_SUM(231), CARRY => INT_CARRY(189)
);
---- End FA stage
---- Begin FA stage
FA_193:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182),
SAVE => INT_SUM(232), CARRY => INT_CARRY(190)
);
---- End FA stage
---- Begin NO stage
INT_SUM(233) <= INT_CARRY(183); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_194:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232),
SAVE => INT_SUM(234), CARRY => INT_CARRY(191)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184),
SAVE => INT_SUM(235), CARRY => INT_CARRY(192)
);
---- End HA stage
---- Begin FA stage
FA_195:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185),
SAVE => INT_SUM(236), CARRY => INT_CARRY(193)
);
---- End FA stage
---- Begin NO stage
INT_SUM(237) <= INT_CARRY(186); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_196:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End FA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_197:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280),
SAVE => INT_SUM(238), CARRY => INT_CARRY(194)
);
---- End FA stage
---- Begin FA stage
FA_198:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283),
SAVE => INT_SUM(239), CARRY => INT_CARRY(195)
);
---- End FA stage
---- Begin NO stage
INT_SUM(240) <= SUMMAND(284); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_199:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240),
SAVE => INT_SUM(241), CARRY => INT_CARRY(196)
);
---- End FA stage
---- Begin FA stage
FA_200:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190),
SAVE => INT_SUM(242), CARRY => INT_CARRY(197)
);
---- End FA stage
---- Begin FA stage
FA_201:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191),
SAVE => INT_SUM(243), CARRY => INT_CARRY(198)
);
---- End FA stage
---- Begin NO stage
INT_SUM(244) <= INT_CARRY(192); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_202:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_203:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287),
SAVE => INT_SUM(245), CARRY => INT_CARRY(199)
);
---- End FA stage
---- Begin FA stage
FA_204:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290),
SAVE => INT_SUM(246), CARRY => INT_CARRY(200)
);
---- End FA stage
---- Begin NO stage
INT_SUM(247) <= SUMMAND(291); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_205:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247),
SAVE => INT_SUM(248), CARRY => INT_CARRY(201)
);
---- End FA stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195),
SAVE => INT_SUM(249), CARRY => INT_CARRY(202)
);
---- End HA stage
---- Begin FA stage
FA_206:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196),
SAVE => INT_SUM(250), CARRY => INT_CARRY(203)
);
---- End FA stage
---- Begin NO stage
INT_SUM(251) <= INT_CARRY(197); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_207:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End FA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin FA stage
FA_208:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294),
SAVE => INT_SUM(252), CARRY => INT_CARRY(204)
);
---- End FA stage
---- Begin FA stage
FA_209:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297),
SAVE => INT_SUM(253), CARRY => INT_CARRY(205)
);
---- End FA stage
---- Begin FA stage
FA_210:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199),
SAVE => INT_SUM(254), CARRY => INT_CARRY(206)
);
---- End FA stage
---- Begin NO stage
INT_SUM(255) <= INT_CARRY(200); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_211:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201),
SAVE => INT_SUM(256), CARRY => INT_CARRY(207)
);
---- End FA stage
---- Begin NO stage
INT_SUM(257) <= INT_CARRY(202); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_212:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin FA stage
FA_213:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300),
SAVE => INT_SUM(258), CARRY => INT_CARRY(208)
);
---- End FA stage
---- Begin FA stage
FA_214:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303),
SAVE => INT_SUM(259), CARRY => INT_CARRY(209)
);
---- End FA stage
---- Begin FA stage
FA_215:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204),
SAVE => INT_SUM(260), CARRY => INT_CARRY(210)
);
---- End FA stage
---- Begin NO stage
INT_SUM(261) <= INT_CARRY(205); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_216:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206),
SAVE => INT_SUM(262), CARRY => INT_CARRY(211)
);
---- End FA stage
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End HA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin FA stage
FA_217:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306),
SAVE => INT_SUM(263), CARRY => INT_CARRY(212)
);
---- End FA stage
---- Begin HA stage
HA_36:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(307), DATA_B => SUMMAND(308),
SAVE => INT_SUM(264), CARRY => INT_CARRY(213)
);
---- End HA stage
---- Begin FA stage
FA_218:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208),
SAVE => INT_SUM(265), CARRY => INT_CARRY(214)
);
---- End FA stage
---- Begin NO stage
INT_SUM(266) <= INT_CARRY(209); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_219:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210),
SAVE => INT_SUM(267), CARRY => INT_CARRY(215)
);
---- End FA stage
---- Begin HA stage
HA_37:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211),
SAVE => SUM(42), CARRY => CARRY(42)
);
---- End HA stage
-- End WT-branch 43
-- Begin WT-branch 44
---- Begin FA stage
FA_220:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311),
SAVE => INT_SUM(268), CARRY => INT_CARRY(216)
);
---- End FA stage
---- Begin HA stage
HA_38:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(312), DATA_B => SUMMAND(313),
SAVE => INT_SUM(269), CARRY => INT_CARRY(217)
);
---- End HA stage
---- Begin FA stage
FA_221:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212),
SAVE => INT_SUM(270), CARRY => INT_CARRY(218)
);
---- End FA stage
---- Begin NO stage
INT_SUM(271) <= INT_CARRY(213); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_222:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214),
SAVE => INT_SUM(272), CARRY => INT_CARRY(219)
);
---- End FA stage
---- Begin HA stage
HA_39:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215),
SAVE => SUM(43), CARRY => CARRY(43)
);
---- End HA stage
-- End WT-branch 44
-- Begin WT-branch 45
---- Begin FA stage
FA_223:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316),
SAVE => INT_SUM(273), CARRY => INT_CARRY(220)
);
---- End FA stage
---- Begin FA stage
FA_224:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217),
SAVE => INT_SUM(274), CARRY => INT_CARRY(221)
);
---- End FA stage
---- Begin FA stage
FA_225:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218),
SAVE => INT_SUM(275), CARRY => INT_CARRY(222)
);
---- End FA stage
---- Begin HA stage
HA_40:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219),
SAVE => SUM(44), CARRY => CARRY(44)
);
---- End HA stage
-- End WT-branch 45
-- Begin WT-branch 46
---- Begin FA stage
FA_226:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320),
SAVE => INT_SUM(276), CARRY => INT_CARRY(223)
);
---- End FA stage
---- Begin NO stage
INT_SUM(277) <= SUMMAND(321); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_227:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220),
SAVE => INT_SUM(278), CARRY => INT_CARRY(224)
);
---- End FA stage
---- Begin NO stage
INT_SUM(279) <= INT_CARRY(221); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_228:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222),
SAVE => SUM(45), CARRY => CARRY(45)
);
---- End FA stage
-- End WT-branch 46
-- Begin WT-branch 47
---- Begin FA stage
FA_229:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324),
SAVE => INT_SUM(280), CARRY => INT_CARRY(225)
);
---- End FA stage
---- Begin NO stage
INT_SUM(281) <= INT_SUM(280); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(282) <= INT_CARRY(223); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_230:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224),
SAVE => SUM(46), CARRY => CARRY(46)
);
---- End FA stage
-- End WT-branch 47
-- Begin WT-branch 48
---- Begin FA stage
FA_231:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327),
SAVE => INT_SUM(283), CARRY => INT_CARRY(226)
);
---- End FA stage
---- Begin NO stage
INT_SUM(284) <= INT_CARRY(225); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_41:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(283), DATA_B => INT_SUM(284),
SAVE => SUM(47), CARRY => CARRY(47)
);
---- End HA stage
-- End WT-branch 48
-- Begin WT-branch 49
---- Begin NO stage
INT_SUM(285) <= SUMMAND(328); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(286) <= SUMMAND(329); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_232:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226),
SAVE => SUM(48), CARRY => CARRY(48)
);
---- End FA stage
-- End WT-branch 49
-- Begin WT-branch 50
---- Begin HA stage
HA_42:HALF_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(330), DATA_B => SUMMAND(331),
SAVE => SUM(49), CARRY => CARRY(49)
);
---- End HA stage
-- End WT-branch 50
-- Begin WT-branch 51
---- Begin NO stage
SUM(50) <= SUMMAND(332); -- At Level 5
---- End NO stage
-- End WT-branch 51
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture RTL of MULTIPLIER_34_18 is
component BOOTHCODER_34_18
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 332)
);
end component;
component WALLACE_34_18
port
(
SUMMAND: in std_logic_vector(0 to 332);
CARRY: out std_logic_vector(0 to 49);
SUM: out std_logic_vector(0 to 50)
);
end component;
component DBLCADDER_64_64
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63)
);
end component;
signal PPBIT:std_logic_vector(0 to 332);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_18
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 17) => MULTIPLIER(0 to 17),
SUMMAND(0 to 332) => PPBIT(0 to 332)
);
W:WALLACE_34_18
port map
(
SUMMAND(0 to 332) => PPBIT(0 to 332),
CARRY(0 to 49) => INT_CARRY(1 to 50),
SUM(0 to 50) => INT_SUM(0 to 50)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUM(0 to 63),
OPB(0 to 63) => INT_CARRY(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 63) => RESULT(0 to 63)
);
end RTL;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 16:35:11 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MULTIPLIER_34_34 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 33);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 127)
);
end MULTIPLIER_34_34;
------------------------------------------------------------
-- End: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MUL_33_33 is
port(X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(32 downto 0);
P: out std_logic_vector(65 downto 0));
end MUL_33_33;
library ieee;
use ieee.std_logic_1164.all;
architecture A of MUL_33_33 is
component MULTIPLIER_34_34
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 33);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 127));
end component;
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 33);
signal Q: std_logic_vector(0 to 127);
signal CLK: std_logic;
begin
U1: MULTIPLIER_34_34 port map(A,B,CLK,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(17);
B(18) <= Y(18);
B(19) <= Y(19);
B(20) <= Y(20);
B(21) <= Y(21);
B(22) <= Y(22);
B(23) <= Y(23);
B(24) <= Y(24);
B(25) <= Y(25);
B(26) <= Y(26);
B(27) <= Y(27);
B(28) <= Y(28);
B(29) <= Y(29);
B(30) <= Y(30);
B(31) <= Y(31);
B(32) <= Y(32);
B(33) <= Y(32);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
P(42) <= Q(42);
P(43) <= Q(43);
P(44) <= Q(44);
P(45) <= Q(45);
P(46) <= Q(46);
P(47) <= Q(47);
P(48) <= Q(48);
P(49) <= Q(49);
P(50) <= Q(50);
P(51) <= Q(51);
P(52) <= Q(52);
P(53) <= Q(53);
P(54) <= Q(54);
P(55) <= Q(55);
P(56) <= Q(56);
P(57) <= Q(57);
P(58) <= Q(58);
P(59) <= Q(59);
P(60) <= Q(60);
P(61) <= Q(61);
P(62) <= Q(62);
P(63) <= Q(63);
P(64) <= Q(64);
P(65) <= Q(65);
end A;
------------------------------------------------------------
-- END: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity BOOTHCODER_34_34 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 33);
SUMMAND: out std_logic_vector(0 to 628)
);
end BOOTHCODER_34_34;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Entities within the Wallace-tree
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity WALLACE_34_34 is
port
(
SUMMAND: in std_logic_vector(0 to 628);
CARRY: out std_logic_vector(0 to 65);
SUM: out std_logic_vector(0 to 66)
);
end WALLACE_34_34;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------
--
-- mgen_14823.vhd: Architecture description created at Fri Aug 16 16:35:11 2002
--
------------------------------------------------------------
-- START: Architectures used with the Modified Booth recoding
------------------------------------------------------------
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
architecture BOOTHCODER of BOOTHCODER_34_34 is
-- Components used in the architecture
component PP_LOW
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_MIDDLE
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_HIGH
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component R_GATE
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end component;
component DECODER
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end component;
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 67);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(110)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(120)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(132)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(143)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(156)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(168)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(182)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(195)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(210)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(224)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(240)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(255)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(272)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(288)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(306)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(323)
);
SUMMAND(324) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(100)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(111)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(121)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(133)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(144)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(157)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(169)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(183)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(196)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(211)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(225)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(241)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(256)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(273)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(289)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(307)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(325)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(341)
);
SUMMAND(342) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(358)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(101)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(112)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(122)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(134)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(145)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(158)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(170)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(184)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(197)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(212)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(226)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(242)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(257)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(274)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(290)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(308)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(326)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(343)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(359)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(374)
);
SUMMAND(375) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(390)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(102)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(113)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(123)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(135)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(146)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(159)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(171)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(185)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(198)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(213)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(227)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(243)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(258)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(275)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(291)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(309)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(327)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(344)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(360)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(376)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(391)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(405)
);
SUMMAND(406) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(420)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(103)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(114)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(124)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(136)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(147)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(172)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(186)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(199)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(214)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(228)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(244)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(259)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(276)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(292)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(310)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(328)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(345)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(361)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(377)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(392)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(407)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(421)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(434)
);
SUMMAND(435) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(448)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_165:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_166:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_167:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_168:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_169:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_170:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_171:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_172:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(104)
);
PPM_173:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(115)
);
PPM_174:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(125)
);
PPM_175:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(137)
);
PPM_176:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(148)
);
PPM_177:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(161)
);
PPM_178:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(173)
);
PPM_179:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(187)
);
PPM_180:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(200)
);
PPM_181:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(215)
);
PPM_182:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(229)
);
PPM_183:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(245)
);
PPM_184:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(260)
);
PPM_185:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(277)
);
PPM_186:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(293)
);
PPM_187:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(311)
);
PPM_188:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(329)
);
PPM_189:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(346)
);
PPM_190:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(362)
);
PPM_191:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(378)
);
PPM_192:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(393)
);
PPM_193:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(408)
);
PPM_194:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(422)
);
PPM_195:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(436)
);
PPM_196:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(449)
);
PPM_197:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(461)
);
SUMMAND(462) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(474)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_198:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_199:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_200:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_201:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_202:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_203:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(105)
);
PPM_204:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(116)
);
PPM_205:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(126)
);
PPM_206:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(138)
);
PPM_207:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(149)
);
PPM_208:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(162)
);
PPM_209:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(174)
);
PPM_210:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(188)
);
PPM_211:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(201)
);
PPM_212:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(216)
);
PPM_213:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(230)
);
PPM_214:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(246)
);
PPM_215:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(261)
);
PPM_216:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(278)
);
PPM_217:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(294)
);
PPM_218:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(312)
);
PPM_219:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(330)
);
PPM_220:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(347)
);
PPM_221:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(363)
);
PPM_222:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(379)
);
PPM_223:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(394)
);
PPM_224:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(409)
);
PPM_225:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(423)
);
PPM_226:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(437)
);
PPM_227:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(450)
);
PPM_228:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(463)
);
PPM_229:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(475)
);
PPM_230:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(486)
);
SUMMAND(487) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(498)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_231:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_232:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_233:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_234:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(106)
);
PPM_235:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(117)
);
PPM_236:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(127)
);
PPM_237:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(139)
);
PPM_238:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(150)
);
PPM_239:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(163)
);
PPM_240:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(175)
);
PPM_241:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(189)
);
PPM_242:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(202)
);
PPM_243:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(217)
);
PPM_244:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(231)
);
PPM_245:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(247)
);
PPM_246:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(262)
);
PPM_247:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(279)
);
PPM_248:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(295)
);
PPM_249:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(313)
);
PPM_250:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(331)
);
PPM_251:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(348)
);
PPM_252:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(364)
);
PPM_253:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(380)
);
PPM_254:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(395)
);
PPM_255:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(410)
);
PPM_256:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(424)
);
PPM_257:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(438)
);
PPM_258:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(451)
);
PPM_259:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(464)
);
PPM_260:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(476)
);
PPM_261:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(488)
);
PPM_262:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(499)
);
PPM_263:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(509)
);
SUMMAND(510) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(520)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_264:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_265:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(107)
);
PPM_266:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(118)
);
PPM_267:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(128)
);
PPM_268:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(140)
);
PPM_269:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(151)
);
PPM_270:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(164)
);
PPM_271:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(176)
);
PPM_272:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(190)
);
PPM_273:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(203)
);
PPM_274:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(218)
);
PPM_275:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(232)
);
PPM_276:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(248)
);
PPM_277:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(263)
);
PPM_278:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(280)
);
PPM_279:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(296)
);
PPM_280:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(314)
);
PPM_281:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(332)
);
PPM_282:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(349)
);
PPM_283:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(365)
);
PPM_284:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(381)
);
PPM_285:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(396)
);
PPM_286:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(411)
);
PPM_287:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(425)
);
PPM_288:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(439)
);
PPM_289:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(452)
);
PPM_290:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(465)
);
PPM_291:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(477)
);
PPM_292:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(489)
);
PPM_293:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(500)
);
PPM_294:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(511)
);
PPM_295:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(521)
);
PPM_296:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(530)
);
SUMMAND(531) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(540)
);
-- Begin partial product 9
-- Begin decoder block 10
DEC_9:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(17),INB => OPB(18),INC => OPB(19),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39)
);
-- End decoder block 10
-- Begin partial product 10
PPL_9:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(108)
);
RGATE_9:R_GATE
port map
(
INA => OPB(17),INB => OPB(18),INC => OPB(19),
PPBIT => SUMMAND(109)
);
PPM_297:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(119)
);
PPM_298:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(129)
);
PPM_299:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(141)
);
PPM_300:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(152)
);
PPM_301:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(165)
);
PPM_302:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(177)
);
PPM_303:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(191)
);
PPM_304:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(204)
);
PPM_305:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(219)
);
PPM_306:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(233)
);
PPM_307:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(249)
);
PPM_308:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(264)
);
PPM_309:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(281)
);
PPM_310:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(297)
);
PPM_311:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(315)
);
PPM_312:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(333)
);
PPM_313:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(350)
);
PPM_314:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(366)
);
PPM_315:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(382)
);
PPM_316:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(397)
);
PPM_317:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(412)
);
PPM_318:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(426)
);
PPM_319:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(440)
);
PPM_320:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(453)
);
PPM_321:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(466)
);
PPM_322:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(478)
);
PPM_323:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(490)
);
PPM_324:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(501)
);
PPM_325:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(512)
);
PPM_326:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(522)
);
PPM_327:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(532)
);
PPM_328:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(541)
);
PPM_329:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(549)
);
SUMMAND(550) <= LOGIC_ONE;
PPH_9:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(558)
);
-- Begin partial product 10
-- Begin decoder block 11
DEC_10:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(19),INB => OPB(20),INC => OPB(21),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43)
);
-- End decoder block 11
-- Begin partial product 11
PPL_10:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(130)
);
RGATE_10:R_GATE
port map
(
INA => OPB(19),INB => OPB(20),INC => OPB(21),
PPBIT => SUMMAND(131)
);
PPM_330:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(142)
);
PPM_331:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(153)
);
PPM_332:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(166)
);
PPM_333:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(178)
);
PPM_334:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(192)
);
PPM_335:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(205)
);
PPM_336:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(220)
);
PPM_337:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(234)
);
PPM_338:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(250)
);
PPM_339:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(265)
);
PPM_340:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(282)
);
PPM_341:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(298)
);
PPM_342:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(316)
);
PPM_343:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(334)
);
PPM_344:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(351)
);
PPM_345:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(367)
);
PPM_346:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(383)
);
PPM_347:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(398)
);
PPM_348:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(413)
);
PPM_349:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(427)
);
PPM_350:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(441)
);
PPM_351:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(454)
);
PPM_352:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(467)
);
PPM_353:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(479)
);
PPM_354:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(491)
);
PPM_355:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(502)
);
PPM_356:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(513)
);
PPM_357:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(523)
);
PPM_358:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(533)
);
PPM_359:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(542)
);
PPM_360:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(551)
);
PPM_361:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(559)
);
PPM_362:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(566)
);
SUMMAND(567) <= LOGIC_ONE;
PPH_10:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(574)
);
-- Begin partial product 11
-- Begin decoder block 12
DEC_11:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(21),INB => OPB(22),INC => OPB(23),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47)
);
-- End decoder block 12
-- Begin partial product 12
PPL_11:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(154)
);
RGATE_11:R_GATE
port map
(
INA => OPB(21),INB => OPB(22),INC => OPB(23),
PPBIT => SUMMAND(155)
);
PPM_363:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(167)
);
PPM_364:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(179)
);
PPM_365:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(193)
);
PPM_366:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(206)
);
PPM_367:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(221)
);
PPM_368:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(235)
);
PPM_369:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(251)
);
PPM_370:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(266)
);
PPM_371:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(283)
);
PPM_372:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(299)
);
PPM_373:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(317)
);
PPM_374:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(335)
);
PPM_375:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(352)
);
PPM_376:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(368)
);
PPM_377:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(384)
);
PPM_378:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(399)
);
PPM_379:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(414)
);
PPM_380:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(428)
);
PPM_381:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(442)
);
PPM_382:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(455)
);
PPM_383:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(468)
);
PPM_384:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(480)
);
PPM_385:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(492)
);
PPM_386:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(503)
);
PPM_387:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(514)
);
PPM_388:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(524)
);
PPM_389:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(534)
);
PPM_390:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(543)
);
PPM_391:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(552)
);
PPM_392:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(560)
);
PPM_393:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(568)
);
PPM_394:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(575)
);
PPM_395:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(581)
);
SUMMAND(582) <= LOGIC_ONE;
PPH_11:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(588)
);
-- Begin partial product 12
-- Begin decoder block 13
DEC_12:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(23),INB => OPB(24),INC => OPB(25),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51)
);
-- End decoder block 13
-- Begin partial product 13
PPL_12:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(180)
);
RGATE_12:R_GATE
port map
(
INA => OPB(23),INB => OPB(24),INC => OPB(25),
PPBIT => SUMMAND(181)
);
PPM_396:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(194)
);
PPM_397:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(207)
);
PPM_398:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(222)
);
PPM_399:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(236)
);
PPM_400:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(252)
);
PPM_401:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(267)
);
PPM_402:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(284)
);
PPM_403:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(300)
);
PPM_404:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(318)
);
PPM_405:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(336)
);
PPM_406:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(353)
);
PPM_407:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(369)
);
PPM_408:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(385)
);
PPM_409:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(400)
);
PPM_410:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(415)
);
PPM_411:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(429)
);
PPM_412:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(443)
);
PPM_413:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(456)
);
PPM_414:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(469)
);
PPM_415:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(481)
);
PPM_416:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(493)
);
PPM_417:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(504)
);
PPM_418:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(515)
);
PPM_419:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(525)
);
PPM_420:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(535)
);
PPM_421:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(544)
);
PPM_422:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(553)
);
PPM_423:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(561)
);
PPM_424:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(569)
);
PPM_425:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(576)
);
PPM_426:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(583)
);
PPM_427:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(589)
);
PPM_428:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(594)
);
SUMMAND(595) <= LOGIC_ONE;
PPH_12:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(600)
);
-- Begin partial product 13
-- Begin decoder block 14
DEC_13:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(25),INB => OPB(26),INC => OPB(27),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55)
);
-- End decoder block 14
-- Begin partial product 14
PPL_13:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(208)
);
RGATE_13:R_GATE
port map
(
INA => OPB(25),INB => OPB(26),INC => OPB(27),
PPBIT => SUMMAND(209)
);
PPM_429:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(223)
);
PPM_430:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(237)
);
PPM_431:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(253)
);
PPM_432:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(268)
);
PPM_433:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(285)
);
PPM_434:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(301)
);
PPM_435:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(319)
);
PPM_436:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(337)
);
PPM_437:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(354)
);
PPM_438:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(370)
);
PPM_439:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(386)
);
PPM_440:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(401)
);
PPM_441:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(416)
);
PPM_442:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(430)
);
PPM_443:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(444)
);
PPM_444:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(457)
);
PPM_445:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(470)
);
PPM_446:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(482)
);
PPM_447:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(494)
);
PPM_448:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(505)
);
PPM_449:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(516)
);
PPM_450:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(526)
);
PPM_451:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(536)
);
PPM_452:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(545)
);
PPM_453:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(554)
);
PPM_454:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(562)
);
PPM_455:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(570)
);
PPM_456:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(577)
);
PPM_457:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(584)
);
PPM_458:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(590)
);
PPM_459:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(596)
);
PPM_460:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(601)
);
PPM_461:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(605)
);
SUMMAND(606) <= LOGIC_ONE;
PPH_13:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(610)
);
-- Begin partial product 14
-- Begin decoder block 15
DEC_14:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(27),INB => OPB(28),INC => OPB(29),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59)
);
-- End decoder block 15
-- Begin partial product 15
PPL_14:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(238)
);
RGATE_14:R_GATE
port map
(
INA => OPB(27),INB => OPB(28),INC => OPB(29),
PPBIT => SUMMAND(239)
);
PPM_462:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(254)
);
PPM_463:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(269)
);
PPM_464:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(286)
);
PPM_465:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(302)
);
PPM_466:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(320)
);
PPM_467:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(338)
);
PPM_468:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(355)
);
PPM_469:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(371)
);
PPM_470:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(387)
);
PPM_471:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(402)
);
PPM_472:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(417)
);
PPM_473:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(431)
);
PPM_474:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(445)
);
PPM_475:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(458)
);
PPM_476:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(471)
);
PPM_477:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(483)
);
PPM_478:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(495)
);
PPM_479:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(506)
);
PPM_480:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(517)
);
PPM_481:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(527)
);
PPM_482:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(537)
);
PPM_483:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(546)
);
PPM_484:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(555)
);
PPM_485:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(563)
);
PPM_486:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(571)
);
PPM_487:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(578)
);
PPM_488:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(585)
);
PPM_489:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(591)
);
PPM_490:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(597)
);
PPM_491:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(602)
);
PPM_492:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(607)
);
PPM_493:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(611)
);
PPM_494:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(614)
);
SUMMAND(615) <= LOGIC_ONE;
PPH_14:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(618)
);
-- Begin partial product 15
-- Begin decoder block 16
DEC_15:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(29),INB => OPB(30),INC => OPB(31),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63)
);
-- End decoder block 16
-- Begin partial product 16
PPL_15:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(270)
);
RGATE_15:R_GATE
port map
(
INA => OPB(29),INB => OPB(30),INC => OPB(31),
PPBIT => SUMMAND(271)
);
PPM_495:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(287)
);
PPM_496:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(303)
);
PPM_497:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(321)
);
PPM_498:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(339)
);
PPM_499:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(356)
);
PPM_500:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(372)
);
PPM_501:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(388)
);
PPM_502:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(403)
);
PPM_503:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(418)
);
PPM_504:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(432)
);
PPM_505:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(446)
);
PPM_506:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(459)
);
PPM_507:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(472)
);
PPM_508:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(484)
);
PPM_509:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(496)
);
PPM_510:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(507)
);
PPM_511:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(518)
);
PPM_512:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(528)
);
PPM_513:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(538)
);
PPM_514:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(547)
);
PPM_515:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(556)
);
PPM_516:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(564)
);
PPM_517:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(572)
);
PPM_518:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(579)
);
PPM_519:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(586)
);
PPM_520:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(592)
);
PPM_521:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(598)
);
PPM_522:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(603)
);
PPM_523:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(608)
);
PPM_524:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(612)
);
PPM_525:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(616)
);
PPM_526:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(619)
);
PPM_527:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(621)
);
SUMMAND(622) <= LOGIC_ONE;
PPH_15:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(624)
);
-- Begin partial product 16
-- Begin decoder block 17
DEC_16:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(31),INB => OPB(32),INC => OPB(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67)
);
-- End decoder block 17
-- Begin partial product 17
PPL_16:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(304)
);
RGATE_16:R_GATE
port map
(
INA => OPB(31),INB => OPB(32),INC => OPB(33),
PPBIT => SUMMAND(305)
);
PPM_528:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(322)
);
PPM_529:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(340)
);
PPM_530:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(357)
);
PPM_531:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(373)
);
PPM_532:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(389)
);
PPM_533:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(404)
);
PPM_534:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(419)
);
PPM_535:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(433)
);
PPM_536:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(447)
);
PPM_537:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(460)
);
PPM_538:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(473)
);
PPM_539:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(485)
);
PPM_540:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(497)
);
PPM_541:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(508)
);
PPM_542:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(519)
);
PPM_543:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(529)
);
PPM_544:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(539)
);
PPM_545:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(548)
);
PPM_546:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(557)
);
PPM_547:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(565)
);
PPM_548:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(573)
);
PPM_549:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(580)
);
PPM_550:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(587)
);
PPM_551:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(593)
);
PPM_552:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(599)
);
PPM_553:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(604)
);
PPM_554:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(609)
);
PPM_555:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(613)
);
PPM_556:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(617)
);
PPM_557:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(620)
);
PPM_558:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(623)
);
PPM_559:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(625)
);
PPM_560:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(626)
);
SUMMAND(627) <= LOGIC_ONE;
PPH_16:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(628)
);
-- Begin partial product 17
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the Wallace-tree
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
architecture WALLACE of WALLACE_34_34 is
-- Components used in the netlist
component FULL_ADDER
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component HALF_ADDER
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 486);
signal INT_SUM: std_logic_vector(0 to 620);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin NO stage
INT_SUM(76) <= SUMMAND(108); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(77) <= SUMMAND(109); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(78), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49),
SAVE => INT_SUM(79), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin NO stage
INT_SUM(80) <= INT_CARRY(50); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(81) <= INT_CARRY(51); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80),
SAVE => INT_SUM(82), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53),
SAVE => INT_SUM(83), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(84), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End HA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112),
SAVE => INT_SUM(85), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115),
SAVE => INT_SUM(86), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118),
SAVE => INT_SUM(87), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin NO stage
INT_SUM(88) <= SUMMAND(119); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(91) <= INT_CARRY(58); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91),
SAVE => INT_SUM(92), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60),
SAVE => INT_SUM(93), CARRY => INT_CARRY(70)
);
---- End HA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(94), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(62); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End FA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125),
SAVE => INT_SUM(97), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(98), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(99), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98),
SAVE => INT_SUM(100), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65),
SAVE => INT_SUM(101), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin NO stage
INT_SUM(102) <= INT_CARRY(66); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102),
SAVE => INT_SUM(103), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68),
SAVE => INT_SUM(104), CARRY => INT_CARRY(79)
);
---- End HA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69),
SAVE => INT_SUM(105), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin NO stage
INT_SUM(106) <= INT_CARRY(70); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134),
SAVE => INT_SUM(107), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(108), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140),
SAVE => INT_SUM(109), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(110) <= SUMMAND(141); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(111) <= SUMMAND(142); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109),
SAVE => INT_SUM(112), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(113), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(114), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114),
SAVE => INT_SUM(115), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77),
SAVE => INT_SUM(116), CARRY => INT_CARRY(88)
);
---- End HA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(117), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(118) <= INT_CARRY(79); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145),
SAVE => INT_SUM(119), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148),
SAVE => INT_SUM(120), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151),
SAVE => INT_SUM(121), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154),
SAVE => INT_SUM(122), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= SUMMAND(155); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121),
SAVE => INT_SUM(124), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81),
SAVE => INT_SUM(125), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83),
SAVE => INT_SUM(126), CARRY => INT_CARRY(96)
);
---- End HA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126),
SAVE => INT_SUM(127), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86),
SAVE => INT_SUM(128), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(129), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin NO stage
INT_SUM(130) <= INT_CARRY(88); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158),
SAVE => INT_SUM(131), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161),
SAVE => INT_SUM(132), CARRY => INT_CARRY(101)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164),
SAVE => INT_SUM(133), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(134), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133),
SAVE => INT_SUM(135), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91),
SAVE => INT_SUM(136), CARRY => INT_CARRY(105)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93),
SAVE => INT_SUM(137), CARRY => INT_CARRY(106)
);
---- End HA stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137),
SAVE => INT_SUM(138), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(139), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97),
SAVE => INT_SUM(140), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin NO stage
INT_SUM(141) <= INT_CARRY(98); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170),
SAVE => INT_SUM(142), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173),
SAVE => INT_SUM(143), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(144), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(145), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(180), DATA_B => SUMMAND(181),
SAVE => INT_SUM(146), CARRY => INT_CARRY(114)
);
---- End HA stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144),
SAVE => INT_SUM(147), CARRY => INT_CARRY(115)
);
---- End FA stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(148), CARRY => INT_CARRY(116)
);
---- End FA stage
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103),
SAVE => INT_SUM(149), CARRY => INT_CARRY(117)
);
---- End FA stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149),
SAVE => INT_SUM(150), CARRY => INT_CARRY(118)
);
---- End FA stage
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106),
SAVE => INT_SUM(151), CARRY => INT_CARRY(119)
);
---- End FA stage
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107),
SAVE => INT_SUM(152), CARRY => INT_CARRY(120)
);
---- End FA stage
---- Begin NO stage
INT_SUM(153) <= INT_CARRY(108); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_121:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_122:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184),
SAVE => INT_SUM(154), CARRY => INT_CARRY(121)
);
---- End FA stage
---- Begin FA stage
FA_123:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187),
SAVE => INT_SUM(155), CARRY => INT_CARRY(122)
);
---- End FA stage
---- Begin FA stage
FA_124:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190),
SAVE => INT_SUM(156), CARRY => INT_CARRY(123)
);
---- End FA stage
---- Begin FA stage
FA_125:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193),
SAVE => INT_SUM(157), CARRY => INT_CARRY(124)
);
---- End FA stage
---- Begin NO stage
INT_SUM(158) <= SUMMAND(194); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_126:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156),
SAVE => INT_SUM(159), CARRY => INT_CARRY(125)
);
---- End FA stage
---- Begin FA stage
FA_127:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110),
SAVE => INT_SUM(160), CARRY => INT_CARRY(126)
);
---- End FA stage
---- Begin FA stage
FA_128:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113),
SAVE => INT_SUM(161), CARRY => INT_CARRY(127)
);
---- End FA stage
---- Begin NO stage
INT_SUM(162) <= INT_CARRY(114); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_129:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161),
SAVE => INT_SUM(163), CARRY => INT_CARRY(128)
);
---- End FA stage
---- Begin FA stage
FA_130:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116),
SAVE => INT_SUM(164), CARRY => INT_CARRY(129)
);
---- End FA stage
---- Begin NO stage
INT_SUM(165) <= INT_CARRY(117); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_131:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165),
SAVE => INT_SUM(166), CARRY => INT_CARRY(130)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119),
SAVE => INT_SUM(167), CARRY => INT_CARRY(131)
);
---- End HA stage
---- Begin FA stage
FA_132:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End FA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_133:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197),
SAVE => INT_SUM(168), CARRY => INT_CARRY(132)
);
---- End FA stage
---- Begin FA stage
FA_134:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200),
SAVE => INT_SUM(169), CARRY => INT_CARRY(133)
);
---- End FA stage
---- Begin FA stage
FA_135:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203),
SAVE => INT_SUM(170), CARRY => INT_CARRY(134)
);
---- End FA stage
---- Begin FA stage
FA_136:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206),
SAVE => INT_SUM(171), CARRY => INT_CARRY(135)
);
---- End FA stage
---- Begin FA stage
FA_137:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209),
SAVE => INT_SUM(172), CARRY => INT_CARRY(136)
);
---- End FA stage
---- Begin FA stage
FA_138:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170),
SAVE => INT_SUM(173), CARRY => INT_CARRY(137)
);
---- End FA stage
---- Begin FA stage
FA_139:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121),
SAVE => INT_SUM(174), CARRY => INT_CARRY(138)
);
---- End FA stage
---- Begin FA stage
FA_140:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124),
SAVE => INT_SUM(175), CARRY => INT_CARRY(139)
);
---- End FA stage
---- Begin FA stage
FA_141:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175),
SAVE => INT_SUM(176), CARRY => INT_CARRY(140)
);
---- End FA stage
---- Begin FA stage
FA_142:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127),
SAVE => INT_SUM(177), CARRY => INT_CARRY(141)
);
---- End FA stage
---- Begin FA stage
FA_143:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128),
SAVE => INT_SUM(178), CARRY => INT_CARRY(142)
);
---- End FA stage
---- Begin NO stage
INT_SUM(179) <= INT_CARRY(129); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_144:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130),
SAVE => INT_SUM(180), CARRY => INT_CARRY(143)
);
---- End FA stage
---- Begin NO stage
INT_SUM(181) <= INT_CARRY(131); -- At Level 5
---- End NO stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(180), DATA_B => INT_SUM(181),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_145:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212),
SAVE => INT_SUM(182), CARRY => INT_CARRY(144)
);
---- End FA stage
---- Begin FA stage
FA_146:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215),
SAVE => INT_SUM(183), CARRY => INT_CARRY(145)
);
---- End FA stage
---- Begin FA stage
FA_147:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218),
SAVE => INT_SUM(184), CARRY => INT_CARRY(146)
);
---- End FA stage
---- Begin FA stage
FA_148:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221),
SAVE => INT_SUM(185), CARRY => INT_CARRY(147)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(222), DATA_B => SUMMAND(223),
SAVE => INT_SUM(186), CARRY => INT_CARRY(148)
);
---- End HA stage
---- Begin FA stage
FA_149:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184),
SAVE => INT_SUM(187), CARRY => INT_CARRY(149)
);
---- End FA stage
---- Begin FA stage
FA_150:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132),
SAVE => INT_SUM(188), CARRY => INT_CARRY(150)
);
---- End FA stage
---- Begin FA stage
FA_151:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135),
SAVE => INT_SUM(189), CARRY => INT_CARRY(151)
);
---- End FA stage
---- Begin NO stage
INT_SUM(190) <= INT_CARRY(136); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_152:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189),
SAVE => INT_SUM(191), CARRY => INT_CARRY(152)
);
---- End FA stage
---- Begin FA stage
FA_153:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138),
SAVE => INT_SUM(192), CARRY => INT_CARRY(153)
);
---- End FA stage
---- Begin NO stage
INT_SUM(193) <= INT_CARRY(139); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_154:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193),
SAVE => INT_SUM(194), CARRY => INT_CARRY(154)
);
---- End FA stage
---- Begin NO stage
INT_SUM(195) <= INT_CARRY(140); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(196) <= INT_CARRY(141); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_155:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196),
SAVE => INT_SUM(197), CARRY => INT_CARRY(155)
);
---- End FA stage
---- Begin NO stage
INT_SUM(198) <= INT_CARRY(142); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_156:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End FA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_157:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226),
SAVE => INT_SUM(199), CARRY => INT_CARRY(156)
);
---- End FA stage
---- Begin FA stage
FA_158:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229),
SAVE => INT_SUM(200), CARRY => INT_CARRY(157)
);
---- End FA stage
---- Begin FA stage
FA_159:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232),
SAVE => INT_SUM(201), CARRY => INT_CARRY(158)
);
---- End FA stage
---- Begin FA stage
FA_160:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235),
SAVE => INT_SUM(202), CARRY => INT_CARRY(159)
);
---- End FA stage
---- Begin FA stage
FA_161:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238),
SAVE => INT_SUM(203), CARRY => INT_CARRY(160)
);
---- End FA stage
---- Begin NO stage
INT_SUM(204) <= SUMMAND(239); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_162:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201),
SAVE => INT_SUM(205), CARRY => INT_CARRY(161)
);
---- End FA stage
---- Begin FA stage
FA_163:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204),
SAVE => INT_SUM(206), CARRY => INT_CARRY(162)
);
---- End FA stage
---- Begin FA stage
FA_164:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146),
SAVE => INT_SUM(207), CARRY => INT_CARRY(163)
);
---- End FA stage
---- Begin NO stage
INT_SUM(208) <= INT_CARRY(147); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(209) <= INT_CARRY(148); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_165:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207),
SAVE => INT_SUM(210), CARRY => INT_CARRY(164)
);
---- End FA stage
---- Begin FA stage
FA_166:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149),
SAVE => INT_SUM(211), CARRY => INT_CARRY(165)
);
---- End FA stage
---- Begin NO stage
INT_SUM(212) <= INT_CARRY(150); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(213) <= INT_CARRY(151); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_167:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212),
SAVE => INT_SUM(214), CARRY => INT_CARRY(166)
);
---- End FA stage
---- Begin FA stage
FA_168:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153),
SAVE => INT_SUM(215), CARRY => INT_CARRY(167)
);
---- End FA stage
---- Begin FA stage
FA_169:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154),
SAVE => INT_SUM(216), CARRY => INT_CARRY(168)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_170:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242),
SAVE => INT_SUM(217), CARRY => INT_CARRY(169)
);
---- End FA stage
---- Begin FA stage
FA_171:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245),
SAVE => INT_SUM(218), CARRY => INT_CARRY(170)
);
---- End FA stage
---- Begin FA stage
FA_172:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248),
SAVE => INT_SUM(219), CARRY => INT_CARRY(171)
);
---- End FA stage
---- Begin FA stage
FA_173:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251),
SAVE => INT_SUM(220), CARRY => INT_CARRY(172)
);
---- End FA stage
---- Begin FA stage
FA_174:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254),
SAVE => INT_SUM(221), CARRY => INT_CARRY(173)
);
---- End FA stage
---- Begin FA stage
FA_175:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219),
SAVE => INT_SUM(222), CARRY => INT_CARRY(174)
);
---- End FA stage
---- Begin FA stage
FA_176:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156),
SAVE => INT_SUM(223), CARRY => INT_CARRY(175)
);
---- End FA stage
---- Begin FA stage
FA_177:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159),
SAVE => INT_SUM(224), CARRY => INT_CARRY(176)
);
---- End FA stage
---- Begin NO stage
INT_SUM(225) <= INT_CARRY(160); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_178:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224),
SAVE => INT_SUM(226), CARRY => INT_CARRY(177)
);
---- End FA stage
---- Begin FA stage
FA_179:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162),
SAVE => INT_SUM(227), CARRY => INT_CARRY(178)
);
---- End FA stage
---- Begin NO stage
INT_SUM(228) <= INT_CARRY(163); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_180:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228),
SAVE => INT_SUM(229), CARRY => INT_CARRY(179)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165),
SAVE => INT_SUM(230), CARRY => INT_CARRY(180)
);
---- End HA stage
---- Begin FA stage
FA_181:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166),
SAVE => INT_SUM(231), CARRY => INT_CARRY(181)
);
---- End FA stage
---- Begin NO stage
INT_SUM(232) <= INT_CARRY(167); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_182:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_183:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257),
SAVE => INT_SUM(233), CARRY => INT_CARRY(182)
);
---- End FA stage
---- Begin FA stage
FA_184:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260),
SAVE => INT_SUM(234), CARRY => INT_CARRY(183)
);
---- End FA stage
---- Begin FA stage
FA_185:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263),
SAVE => INT_SUM(235), CARRY => INT_CARRY(184)
);
---- End FA stage
---- Begin FA stage
FA_186:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266),
SAVE => INT_SUM(236), CARRY => INT_CARRY(185)
);
---- End FA stage
---- Begin FA stage
FA_187:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269),
SAVE => INT_SUM(237), CARRY => INT_CARRY(186)
);
---- End FA stage
---- Begin NO stage
INT_SUM(238) <= SUMMAND(270); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(239) <= SUMMAND(271); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_188:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235),
SAVE => INT_SUM(240), CARRY => INT_CARRY(187)
);
---- End FA stage
---- Begin FA stage
FA_189:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238),
SAVE => INT_SUM(241), CARRY => INT_CARRY(188)
);
---- End FA stage
---- Begin FA stage
FA_190:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170),
SAVE => INT_SUM(242), CARRY => INT_CARRY(189)
);
---- End FA stage
---- Begin FA stage
FA_191:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173),
SAVE => INT_SUM(243), CARRY => INT_CARRY(190)
);
---- End FA stage
---- Begin FA stage
FA_192:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242),
SAVE => INT_SUM(244), CARRY => INT_CARRY(191)
);
---- End FA stage
---- Begin FA stage
FA_193:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175),
SAVE => INT_SUM(245), CARRY => INT_CARRY(192)
);
---- End FA stage
---- Begin NO stage
INT_SUM(246) <= INT_CARRY(176); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_194:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246),
SAVE => INT_SUM(247), CARRY => INT_CARRY(193)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178),
SAVE => INT_SUM(248), CARRY => INT_CARRY(194)
);
---- End HA stage
---- Begin FA stage
FA_195:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179),
SAVE => INT_SUM(249), CARRY => INT_CARRY(195)
);
---- End FA stage
---- Begin NO stage
INT_SUM(250) <= INT_CARRY(180); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_196:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_197:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274),
SAVE => INT_SUM(251), CARRY => INT_CARRY(196)
);
---- End FA stage
---- Begin FA stage
FA_198:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277),
SAVE => INT_SUM(252), CARRY => INT_CARRY(197)
);
---- End FA stage
---- Begin FA stage
FA_199:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280),
SAVE => INT_SUM(253), CARRY => INT_CARRY(198)
);
---- End FA stage
---- Begin FA stage
FA_200:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283),
SAVE => INT_SUM(254), CARRY => INT_CARRY(199)
);
---- End FA stage
---- Begin FA stage
FA_201:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286),
SAVE => INT_SUM(255), CARRY => INT_CARRY(200)
);
---- End FA stage
---- Begin NO stage
INT_SUM(256) <= SUMMAND(287); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_202:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253),
SAVE => INT_SUM(257), CARRY => INT_CARRY(201)
);
---- End FA stage
---- Begin FA stage
FA_203:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256),
SAVE => INT_SUM(258), CARRY => INT_CARRY(202)
);
---- End FA stage
---- Begin FA stage
FA_204:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184),
SAVE => INT_SUM(259), CARRY => INT_CARRY(203)
);
---- End FA stage
---- Begin NO stage
INT_SUM(260) <= INT_CARRY(185); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(261) <= INT_CARRY(186); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_205:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259),
SAVE => INT_SUM(262), CARRY => INT_CARRY(204)
);
---- End FA stage
---- Begin FA stage
FA_206:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187),
SAVE => INT_SUM(263), CARRY => INT_CARRY(205)
);
---- End FA stage
---- Begin FA stage
FA_207:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190),
SAVE => INT_SUM(264), CARRY => INT_CARRY(206)
);
---- End FA stage
---- Begin FA stage
FA_208:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264),
SAVE => INT_SUM(265), CARRY => INT_CARRY(207)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192),
SAVE => INT_SUM(266), CARRY => INT_CARRY(208)
);
---- End HA stage
---- Begin FA stage
FA_209:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193),
SAVE => INT_SUM(267), CARRY => INT_CARRY(209)
);
---- End FA stage
---- Begin NO stage
INT_SUM(268) <= INT_CARRY(194); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_210:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End FA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_211:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290),
SAVE => INT_SUM(269), CARRY => INT_CARRY(210)
);
---- End FA stage
---- Begin FA stage
FA_212:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293),
SAVE => INT_SUM(270), CARRY => INT_CARRY(211)
);
---- End FA stage
---- Begin FA stage
FA_213:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296),
SAVE => INT_SUM(271), CARRY => INT_CARRY(212)
);
---- End FA stage
---- Begin FA stage
FA_214:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299),
SAVE => INT_SUM(272), CARRY => INT_CARRY(213)
);
---- End FA stage
---- Begin FA stage
FA_215:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302),
SAVE => INT_SUM(273), CARRY => INT_CARRY(214)
);
---- End FA stage
---- Begin FA stage
FA_216:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305),
SAVE => INT_SUM(274), CARRY => INT_CARRY(215)
);
---- End FA stage
---- Begin FA stage
FA_217:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271),
SAVE => INT_SUM(275), CARRY => INT_CARRY(216)
);
---- End FA stage
---- Begin FA stage
FA_218:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274),
SAVE => INT_SUM(276), CARRY => INT_CARRY(217)
);
---- End FA stage
---- Begin FA stage
FA_219:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198),
SAVE => INT_SUM(277), CARRY => INT_CARRY(218)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200),
SAVE => INT_SUM(278), CARRY => INT_CARRY(219)
);
---- End HA stage
---- Begin FA stage
FA_220:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277),
SAVE => INT_SUM(279), CARRY => INT_CARRY(220)
);
---- End FA stage
---- Begin FA stage
FA_221:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202),
SAVE => INT_SUM(280), CARRY => INT_CARRY(221)
);
---- End FA stage
---- Begin NO stage
INT_SUM(281) <= INT_CARRY(203); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_222:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281),
SAVE => INT_SUM(282), CARRY => INT_CARRY(222)
);
---- End FA stage
---- Begin FA stage
FA_223:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206),
SAVE => INT_SUM(283), CARRY => INT_CARRY(223)
);
---- End FA stage
---- Begin FA stage
FA_224:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207),
SAVE => INT_SUM(284), CARRY => INT_CARRY(224)
);
---- End FA stage
---- Begin NO stage
INT_SUM(285) <= INT_CARRY(208); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_225:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_226:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308),
SAVE => INT_SUM(286), CARRY => INT_CARRY(225)
);
---- End FA stage
---- Begin FA stage
FA_227:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311),
SAVE => INT_SUM(287), CARRY => INT_CARRY(226)
);
---- End FA stage
---- Begin FA stage
FA_228:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314),
SAVE => INT_SUM(288), CARRY => INT_CARRY(227)
);
---- End FA stage
---- Begin FA stage
FA_229:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317),
SAVE => INT_SUM(289), CARRY => INT_CARRY(228)
);
---- End FA stage
---- Begin FA stage
FA_230:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320),
SAVE => INT_SUM(290), CARRY => INT_CARRY(229)
);
---- End FA stage
---- Begin NO stage
INT_SUM(291) <= SUMMAND(321); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(292) <= SUMMAND(322); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_231:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288),
SAVE => INT_SUM(293), CARRY => INT_CARRY(230)
);
---- End FA stage
---- Begin FA stage
FA_232:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291),
SAVE => INT_SUM(294), CARRY => INT_CARRY(231)
);
---- End FA stage
---- Begin FA stage
FA_233:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211),
SAVE => INT_SUM(295), CARRY => INT_CARRY(232)
);
---- End FA stage
---- Begin FA stage
FA_234:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214),
SAVE => INT_SUM(296), CARRY => INT_CARRY(233)
);
---- End FA stage
---- Begin NO stage
INT_SUM(297) <= INT_CARRY(215); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_235:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295),
SAVE => INT_SUM(298), CARRY => INT_CARRY(234)
);
---- End FA stage
---- Begin FA stage
FA_236:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216),
SAVE => INT_SUM(299), CARRY => INT_CARRY(235)
);
---- End FA stage
---- Begin FA stage
FA_237:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219),
SAVE => INT_SUM(300), CARRY => INT_CARRY(236)
);
---- End FA stage
---- Begin FA stage
FA_238:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300),
SAVE => INT_SUM(301), CARRY => INT_CARRY(237)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221),
SAVE => INT_SUM(302), CARRY => INT_CARRY(238)
);
---- End HA stage
---- Begin FA stage
FA_239:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222),
SAVE => INT_SUM(303), CARRY => INT_CARRY(239)
);
---- End FA stage
---- Begin NO stage
INT_SUM(304) <= INT_CARRY(223); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_240:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End FA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_241:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325),
SAVE => INT_SUM(305), CARRY => INT_CARRY(240)
);
---- End FA stage
---- Begin FA stage
FA_242:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328),
SAVE => INT_SUM(306), CARRY => INT_CARRY(241)
);
---- End FA stage
---- Begin FA stage
FA_243:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331),
SAVE => INT_SUM(307), CARRY => INT_CARRY(242)
);
---- End FA stage
---- Begin FA stage
FA_244:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334),
SAVE => INT_SUM(308), CARRY => INT_CARRY(243)
);
---- End FA stage
---- Begin FA stage
FA_245:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337),
SAVE => INT_SUM(309), CARRY => INT_CARRY(244)
);
---- End FA stage
---- Begin FA stage
FA_246:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340),
SAVE => INT_SUM(310), CARRY => INT_CARRY(245)
);
---- End FA stage
---- Begin FA stage
FA_247:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307),
SAVE => INT_SUM(311), CARRY => INT_CARRY(246)
);
---- End FA stage
---- Begin FA stage
FA_248:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310),
SAVE => INT_SUM(312), CARRY => INT_CARRY(247)
);
---- End FA stage
---- Begin FA stage
FA_249:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227),
SAVE => INT_SUM(313), CARRY => INT_CARRY(248)
);
---- End FA stage
---- Begin NO stage
INT_SUM(314) <= INT_CARRY(228); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(315) <= INT_CARRY(229); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_250:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313),
SAVE => INT_SUM(316), CARRY => INT_CARRY(249)
);
---- End FA stage
---- Begin FA stage
FA_251:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230),
SAVE => INT_SUM(317), CARRY => INT_CARRY(250)
);
---- End FA stage
---- Begin FA stage
FA_252:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233),
SAVE => INT_SUM(318), CARRY => INT_CARRY(251)
);
---- End FA stage
---- Begin FA stage
FA_253:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318),
SAVE => INT_SUM(319), CARRY => INT_CARRY(252)
);
---- End FA stage
---- Begin FA stage
FA_254:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236),
SAVE => INT_SUM(320), CARRY => INT_CARRY(253)
);
---- End FA stage
---- Begin FA stage
FA_255:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237),
SAVE => INT_SUM(321), CARRY => INT_CARRY(254)
);
---- End FA stage
---- Begin NO stage
INT_SUM(322) <= INT_CARRY(238); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_256:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_257:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343),
SAVE => INT_SUM(323), CARRY => INT_CARRY(255)
);
---- End FA stage
---- Begin FA stage
FA_258:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346),
SAVE => INT_SUM(324), CARRY => INT_CARRY(256)
);
---- End FA stage
---- Begin FA stage
FA_259:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349),
SAVE => INT_SUM(325), CARRY => INT_CARRY(257)
);
---- End FA stage
---- Begin FA stage
FA_260:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352),
SAVE => INT_SUM(326), CARRY => INT_CARRY(258)
);
---- End FA stage
---- Begin FA stage
FA_261:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355),
SAVE => INT_SUM(327), CARRY => INT_CARRY(259)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(356), DATA_B => SUMMAND(357),
SAVE => INT_SUM(328), CARRY => INT_CARRY(260)
);
---- End HA stage
---- Begin FA stage
FA_262:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325),
SAVE => INT_SUM(329), CARRY => INT_CARRY(261)
);
---- End FA stage
---- Begin FA stage
FA_263:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328),
SAVE => INT_SUM(330), CARRY => INT_CARRY(262)
);
---- End FA stage
---- Begin FA stage
FA_264:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242),
SAVE => INT_SUM(331), CARRY => INT_CARRY(263)
);
---- End FA stage
---- Begin FA stage
FA_265:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245),
SAVE => INT_SUM(332), CARRY => INT_CARRY(264)
);
---- End FA stage
---- Begin FA stage
FA_266:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331),
SAVE => INT_SUM(333), CARRY => INT_CARRY(265)
);
---- End FA stage
---- Begin FA stage
FA_267:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247),
SAVE => INT_SUM(334), CARRY => INT_CARRY(266)
);
---- End FA stage
---- Begin NO stage
INT_SUM(335) <= INT_CARRY(248); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_268:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335),
SAVE => INT_SUM(336), CARRY => INT_CARRY(267)
);
---- End FA stage
---- Begin FA stage
FA_269:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251),
SAVE => INT_SUM(337), CARRY => INT_CARRY(268)
);
---- End FA stage
---- Begin FA stage
FA_270:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252),
SAVE => INT_SUM(338), CARRY => INT_CARRY(269)
);
---- End FA stage
---- Begin NO stage
INT_SUM(339) <= INT_CARRY(253); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_271:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End FA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_272:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360),
SAVE => INT_SUM(340), CARRY => INT_CARRY(270)
);
---- End FA stage
---- Begin FA stage
FA_273:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363),
SAVE => INT_SUM(341), CARRY => INT_CARRY(271)
);
---- End FA stage
---- Begin FA stage
FA_274:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366),
SAVE => INT_SUM(342), CARRY => INT_CARRY(272)
);
---- End FA stage
---- Begin FA stage
FA_275:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369),
SAVE => INT_SUM(343), CARRY => INT_CARRY(273)
);
---- End FA stage
---- Begin FA stage
FA_276:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372),
SAVE => INT_SUM(344), CARRY => INT_CARRY(274)
);
---- End FA stage
---- Begin NO stage
INT_SUM(345) <= SUMMAND(373); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_277:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342),
SAVE => INT_SUM(346), CARRY => INT_CARRY(275)
);
---- End FA stage
---- Begin FA stage
FA_278:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345),
SAVE => INT_SUM(347), CARRY => INT_CARRY(276)
);
---- End FA stage
---- Begin FA stage
FA_279:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257),
SAVE => INT_SUM(348), CARRY => INT_CARRY(277)
);
---- End FA stage
---- Begin FA stage
FA_280:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260),
SAVE => INT_SUM(349), CARRY => INT_CARRY(278)
);
---- End FA stage
---- Begin FA stage
FA_281:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348),
SAVE => INT_SUM(350), CARRY => INT_CARRY(279)
);
---- End FA stage
---- Begin FA stage
FA_282:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262),
SAVE => INT_SUM(351), CARRY => INT_CARRY(280)
);
---- End FA stage
---- Begin NO stage
INT_SUM(352) <= INT_CARRY(263); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(353) <= INT_CARRY(264); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_283:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352),
SAVE => INT_SUM(354), CARRY => INT_CARRY(281)
);
---- End FA stage
---- Begin FA stage
FA_284:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266),
SAVE => INT_SUM(355), CARRY => INT_CARRY(282)
);
---- End FA stage
---- Begin FA stage
FA_285:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267),
SAVE => INT_SUM(356), CARRY => INT_CARRY(283)
);
---- End FA stage
---- Begin NO stage
INT_SUM(357) <= INT_CARRY(268); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_286:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_287:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376),
SAVE => INT_SUM(358), CARRY => INT_CARRY(284)
);
---- End FA stage
---- Begin FA stage
FA_288:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379),
SAVE => INT_SUM(359), CARRY => INT_CARRY(285)
);
---- End FA stage
---- Begin FA stage
FA_289:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382),
SAVE => INT_SUM(360), CARRY => INT_CARRY(286)
);
---- End FA stage
---- Begin FA stage
FA_290:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385),
SAVE => INT_SUM(361), CARRY => INT_CARRY(287)
);
---- End FA stage
---- Begin FA stage
FA_291:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388),
SAVE => INT_SUM(362), CARRY => INT_CARRY(288)
);
---- End FA stage
---- Begin NO stage
INT_SUM(363) <= SUMMAND(389); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_292:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360),
SAVE => INT_SUM(364), CARRY => INT_CARRY(289)
);
---- End FA stage
---- Begin FA stage
FA_293:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363),
SAVE => INT_SUM(365), CARRY => INT_CARRY(290)
);
---- End FA stage
---- Begin FA stage
FA_294:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272),
SAVE => INT_SUM(366), CARRY => INT_CARRY(291)
);
---- End FA stage
---- Begin NO stage
INT_SUM(367) <= INT_CARRY(273); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(368) <= INT_CARRY(274); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_295:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366),
SAVE => INT_SUM(369), CARRY => INT_CARRY(292)
);
---- End FA stage
---- Begin FA stage
FA_296:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275),
SAVE => INT_SUM(370), CARRY => INT_CARRY(293)
);
---- End FA stage
---- Begin FA stage
FA_297:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278),
SAVE => INT_SUM(371), CARRY => INT_CARRY(294)
);
---- End FA stage
---- Begin FA stage
FA_298:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371),
SAVE => INT_SUM(372), CARRY => INT_CARRY(295)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280),
SAVE => INT_SUM(373), CARRY => INT_CARRY(296)
);
---- End HA stage
---- Begin FA stage
FA_299:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281),
SAVE => INT_SUM(374), CARRY => INT_CARRY(297)
);
---- End FA stage
---- Begin NO stage
INT_SUM(375) <= INT_CARRY(282); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_300:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End FA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_301:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392),
SAVE => INT_SUM(376), CARRY => INT_CARRY(298)
);
---- End FA stage
---- Begin FA stage
FA_302:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395),
SAVE => INT_SUM(377), CARRY => INT_CARRY(299)
);
---- End FA stage
---- Begin FA stage
FA_303:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398),
SAVE => INT_SUM(378), CARRY => INT_CARRY(300)
);
---- End FA stage
---- Begin FA stage
FA_304:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401),
SAVE => INT_SUM(379), CARRY => INT_CARRY(301)
);
---- End FA stage
---- Begin FA stage
FA_305:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404),
SAVE => INT_SUM(380), CARRY => INT_CARRY(302)
);
---- End FA stage
---- Begin FA stage
FA_306:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378),
SAVE => INT_SUM(381), CARRY => INT_CARRY(303)
);
---- End FA stage
---- Begin FA stage
FA_307:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284),
SAVE => INT_SUM(382), CARRY => INT_CARRY(304)
);
---- End FA stage
---- Begin FA stage
FA_308:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287),
SAVE => INT_SUM(383), CARRY => INT_CARRY(305)
);
---- End FA stage
---- Begin NO stage
INT_SUM(384) <= INT_CARRY(288); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_309:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383),
SAVE => INT_SUM(385), CARRY => INT_CARRY(306)
);
---- End FA stage
---- Begin FA stage
FA_310:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290),
SAVE => INT_SUM(386), CARRY => INT_CARRY(307)
);
---- End FA stage
---- Begin NO stage
INT_SUM(387) <= INT_CARRY(291); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_311:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387),
SAVE => INT_SUM(388), CARRY => INT_CARRY(308)
);
---- End FA stage
---- Begin FA stage
FA_312:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294),
SAVE => INT_SUM(389), CARRY => INT_CARRY(309)
);
---- End FA stage
---- Begin FA stage
FA_313:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295),
SAVE => INT_SUM(390), CARRY => INT_CARRY(310)
);
---- End FA stage
---- Begin NO stage
INT_SUM(391) <= INT_CARRY(296); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_314:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_315:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407),
SAVE => INT_SUM(392), CARRY => INT_CARRY(311)
);
---- End FA stage
---- Begin FA stage
FA_316:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410),
SAVE => INT_SUM(393), CARRY => INT_CARRY(312)
);
---- End FA stage
---- Begin FA stage
FA_317:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413),
SAVE => INT_SUM(394), CARRY => INT_CARRY(313)
);
---- End FA stage
---- Begin FA stage
FA_318:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416),
SAVE => INT_SUM(395), CARRY => INT_CARRY(314)
);
---- End FA stage
---- Begin FA stage
FA_319:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419),
SAVE => INT_SUM(396), CARRY => INT_CARRY(315)
);
---- End FA stage
---- Begin FA stage
FA_320:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394),
SAVE => INT_SUM(397), CARRY => INT_CARRY(316)
);
---- End FA stage
---- Begin FA stage
FA_321:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298),
SAVE => INT_SUM(398), CARRY => INT_CARRY(317)
);
---- End FA stage
---- Begin FA stage
FA_322:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301),
SAVE => INT_SUM(399), CARRY => INT_CARRY(318)
);
---- End FA stage
---- Begin NO stage
INT_SUM(400) <= INT_CARRY(302); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_323:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399),
SAVE => INT_SUM(401), CARRY => INT_CARRY(319)
);
---- End FA stage
---- Begin FA stage
FA_324:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304),
SAVE => INT_SUM(402), CARRY => INT_CARRY(320)
);
---- End FA stage
---- Begin NO stage
INT_SUM(403) <= INT_CARRY(305); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_325:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403),
SAVE => INT_SUM(404), CARRY => INT_CARRY(321)
);
---- End FA stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307),
SAVE => INT_SUM(405), CARRY => INT_CARRY(322)
);
---- End HA stage
---- Begin FA stage
FA_326:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308),
SAVE => INT_SUM(406), CARRY => INT_CARRY(323)
);
---- End FA stage
---- Begin NO stage
INT_SUM(407) <= INT_CARRY(309); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_327:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End FA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin FA stage
FA_328:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422),
SAVE => INT_SUM(408), CARRY => INT_CARRY(324)
);
---- End FA stage
---- Begin FA stage
FA_329:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425),
SAVE => INT_SUM(409), CARRY => INT_CARRY(325)
);
---- End FA stage
---- Begin FA stage
FA_330:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428),
SAVE => INT_SUM(410), CARRY => INT_CARRY(326)
);
---- End FA stage
---- Begin FA stage
FA_331:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431),
SAVE => INT_SUM(411), CARRY => INT_CARRY(327)
);
---- End FA stage
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(432), DATA_B => SUMMAND(433),
SAVE => INT_SUM(412), CARRY => INT_CARRY(328)
);
---- End HA stage
---- Begin FA stage
FA_332:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410),
SAVE => INT_SUM(413), CARRY => INT_CARRY(329)
);
---- End FA stage
---- Begin FA stage
FA_333:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311),
SAVE => INT_SUM(414), CARRY => INT_CARRY(330)
);
---- End FA stage
---- Begin FA stage
FA_334:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314),
SAVE => INT_SUM(415), CARRY => INT_CARRY(331)
);
---- End FA stage
---- Begin NO stage
INT_SUM(416) <= INT_CARRY(315); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_335:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415),
SAVE => INT_SUM(417), CARRY => INT_CARRY(332)
);
---- End FA stage
---- Begin FA stage
FA_336:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317),
SAVE => INT_SUM(418), CARRY => INT_CARRY(333)
);
---- End FA stage
---- Begin NO stage
INT_SUM(419) <= INT_CARRY(318); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_337:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419),
SAVE => INT_SUM(420), CARRY => INT_CARRY(334)
);
---- End FA stage
---- Begin HA stage
HA_36:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320),
SAVE => INT_SUM(421), CARRY => INT_CARRY(335)
);
---- End HA stage
---- Begin FA stage
FA_338:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321),
SAVE => INT_SUM(422), CARRY => INT_CARRY(336)
);
---- End FA stage
---- Begin NO stage
INT_SUM(423) <= INT_CARRY(322); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_339:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin FA stage
FA_340:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436),
SAVE => INT_SUM(424), CARRY => INT_CARRY(337)
);
---- End FA stage
---- Begin FA stage
FA_341:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439),
SAVE => INT_SUM(425), CARRY => INT_CARRY(338)
);
---- End FA stage
---- Begin FA stage
FA_342:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442),
SAVE => INT_SUM(426), CARRY => INT_CARRY(339)
);
---- End FA stage
---- Begin FA stage
FA_343:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445),
SAVE => INT_SUM(427), CARRY => INT_CARRY(340)
);
---- End FA stage
---- Begin HA stage
HA_37:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(446), DATA_B => SUMMAND(447),
SAVE => INT_SUM(428), CARRY => INT_CARRY(341)
);
---- End HA stage
---- Begin FA stage
FA_344:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426),
SAVE => INT_SUM(429), CARRY => INT_CARRY(342)
);
---- End FA stage
---- Begin FA stage
FA_345:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324),
SAVE => INT_SUM(430), CARRY => INT_CARRY(343)
);
---- End FA stage
---- Begin FA stage
FA_346:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327),
SAVE => INT_SUM(431), CARRY => INT_CARRY(344)
);
---- End FA stage
---- Begin NO stage
INT_SUM(432) <= INT_CARRY(328); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_347:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431),
SAVE => INT_SUM(433), CARRY => INT_CARRY(345)
);
---- End FA stage
---- Begin FA stage
FA_348:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330),
SAVE => INT_SUM(434), CARRY => INT_CARRY(346)
);
---- End FA stage
---- Begin NO stage
INT_SUM(435) <= INT_CARRY(331); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_349:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435),
SAVE => INT_SUM(436), CARRY => INT_CARRY(347)
);
---- End FA stage
---- Begin HA stage
HA_38:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333),
SAVE => INT_SUM(437), CARRY => INT_CARRY(348)
);
---- End HA stage
---- Begin FA stage
FA_350:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334),
SAVE => INT_SUM(438), CARRY => INT_CARRY(349)
);
---- End FA stage
---- Begin NO stage
INT_SUM(439) <= INT_CARRY(335); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_351:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End FA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin FA stage
FA_352:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450),
SAVE => INT_SUM(440), CARRY => INT_CARRY(350)
);
---- End FA stage
---- Begin FA stage
FA_353:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453),
SAVE => INT_SUM(441), CARRY => INT_CARRY(351)
);
---- End FA stage
---- Begin FA stage
FA_354:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456),
SAVE => INT_SUM(442), CARRY => INT_CARRY(352)
);
---- End FA stage
---- Begin FA stage
FA_355:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459),
SAVE => INT_SUM(443), CARRY => INT_CARRY(353)
);
---- End FA stage
---- Begin NO stage
INT_SUM(444) <= SUMMAND(460); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_356:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442),
SAVE => INT_SUM(445), CARRY => INT_CARRY(354)
);
---- End FA stage
---- Begin FA stage
FA_357:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337),
SAVE => INT_SUM(446), CARRY => INT_CARRY(355)
);
---- End FA stage
---- Begin FA stage
FA_358:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340),
SAVE => INT_SUM(447), CARRY => INT_CARRY(356)
);
---- End FA stage
---- Begin NO stage
INT_SUM(448) <= INT_CARRY(341); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_359:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447),
SAVE => INT_SUM(449), CARRY => INT_CARRY(357)
);
---- End FA stage
---- Begin FA stage
FA_360:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343),
SAVE => INT_SUM(450), CARRY => INT_CARRY(358)
);
---- End FA stage
---- Begin NO stage
INT_SUM(451) <= INT_CARRY(344); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_361:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451),
SAVE => INT_SUM(452), CARRY => INT_CARRY(359)
);
---- End FA stage
---- Begin HA stage
HA_39:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346),
SAVE => INT_SUM(453), CARRY => INT_CARRY(360)
);
---- End HA stage
---- Begin FA stage
FA_362:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347),
SAVE => INT_SUM(454), CARRY => INT_CARRY(361)
);
---- End FA stage
---- Begin NO stage
INT_SUM(455) <= INT_CARRY(348); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_363:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349),
SAVE => SUM(42), CARRY => CARRY(42)
);
---- End FA stage
-- End WT-branch 43
-- Begin WT-branch 44
---- Begin FA stage
FA_364:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463),
SAVE => INT_SUM(456), CARRY => INT_CARRY(362)
);
---- End FA stage
---- Begin FA stage
FA_365:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466),
SAVE => INT_SUM(457), CARRY => INT_CARRY(363)
);
---- End FA stage
---- Begin FA stage
FA_366:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469),
SAVE => INT_SUM(458), CARRY => INT_CARRY(364)
);
---- End FA stage
---- Begin FA stage
FA_367:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472),
SAVE => INT_SUM(459), CARRY => INT_CARRY(365)
);
---- End FA stage
---- Begin FA stage
FA_368:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351),
SAVE => INT_SUM(460), CARRY => INT_CARRY(366)
);
---- End FA stage
---- Begin NO stage
INT_SUM(461) <= INT_CARRY(352); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(462) <= INT_CARRY(353); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_369:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458),
SAVE => INT_SUM(463), CARRY => INT_CARRY(367)
);
---- End FA stage
---- Begin FA stage
FA_370:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461),
SAVE => INT_SUM(464), CARRY => INT_CARRY(368)
);
---- End FA stage
---- Begin FA stage
FA_371:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355),
SAVE => INT_SUM(465), CARRY => INT_CARRY(369)
);
---- End FA stage
---- Begin NO stage
INT_SUM(466) <= INT_CARRY(356); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_372:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465),
SAVE => INT_SUM(467), CARRY => INT_CARRY(370)
);
---- End FA stage
---- Begin FA stage
FA_373:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358),
SAVE => INT_SUM(468), CARRY => INT_CARRY(371)
);
---- End FA stage
---- Begin FA stage
FA_374:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359),
SAVE => INT_SUM(469), CARRY => INT_CARRY(372)
);
---- End FA stage
---- Begin NO stage
INT_SUM(470) <= INT_CARRY(360); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_375:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361),
SAVE => SUM(43), CARRY => CARRY(43)
);
---- End FA stage
-- End WT-branch 44
-- Begin WT-branch 45
---- Begin FA stage
FA_376:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476),
SAVE => INT_SUM(471), CARRY => INT_CARRY(373)
);
---- End FA stage
---- Begin FA stage
FA_377:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479),
SAVE => INT_SUM(472), CARRY => INT_CARRY(374)
);
---- End FA stage
---- Begin FA stage
FA_378:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482),
SAVE => INT_SUM(473), CARRY => INT_CARRY(375)
);
---- End FA stage
---- Begin FA stage
FA_379:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485),
SAVE => INT_SUM(474), CARRY => INT_CARRY(376)
);
---- End FA stage
---- Begin FA stage
FA_380:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473),
SAVE => INT_SUM(475), CARRY => INT_CARRY(377)
);
---- End FA stage
---- Begin FA stage
FA_381:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363),
SAVE => INT_SUM(476), CARRY => INT_CARRY(378)
);
---- End FA stage
---- Begin FA stage
FA_382:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366),
SAVE => INT_SUM(477), CARRY => INT_CARRY(379)
);
---- End FA stage
---- Begin FA stage
FA_383:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477),
SAVE => INT_SUM(478), CARRY => INT_CARRY(380)
);
---- End FA stage
---- Begin FA stage
FA_384:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369),
SAVE => INT_SUM(479), CARRY => INT_CARRY(381)
);
---- End FA stage
---- Begin FA stage
FA_385:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370),
SAVE => INT_SUM(480), CARRY => INT_CARRY(382)
);
---- End FA stage
---- Begin NO stage
INT_SUM(481) <= INT_CARRY(371); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_386:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372),
SAVE => SUM(44), CARRY => CARRY(44)
);
---- End FA stage
-- End WT-branch 45
-- Begin WT-branch 46
---- Begin FA stage
FA_387:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488),
SAVE => INT_SUM(482), CARRY => INT_CARRY(383)
);
---- End FA stage
---- Begin FA stage
FA_388:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491),
SAVE => INT_SUM(483), CARRY => INT_CARRY(384)
);
---- End FA stage
---- Begin FA stage
FA_389:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494),
SAVE => INT_SUM(484), CARRY => INT_CARRY(385)
);
---- End FA stage
---- Begin FA stage
FA_390:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497),
SAVE => INT_SUM(485), CARRY => INT_CARRY(386)
);
---- End FA stage
---- Begin FA stage
FA_391:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484),
SAVE => INT_SUM(486), CARRY => INT_CARRY(387)
);
---- End FA stage
---- Begin FA stage
FA_392:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374),
SAVE => INT_SUM(487), CARRY => INT_CARRY(388)
);
---- End FA stage
---- Begin HA stage
HA_40:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376),
SAVE => INT_SUM(488), CARRY => INT_CARRY(389)
);
---- End HA stage
---- Begin FA stage
FA_393:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488),
SAVE => INT_SUM(489), CARRY => INT_CARRY(390)
);
---- End FA stage
---- Begin FA stage
FA_394:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379),
SAVE => INT_SUM(490), CARRY => INT_CARRY(391)
);
---- End FA stage
---- Begin FA stage
FA_395:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380),
SAVE => INT_SUM(491), CARRY => INT_CARRY(392)
);
---- End FA stage
---- Begin NO stage
INT_SUM(492) <= INT_CARRY(381); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_396:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382),
SAVE => SUM(45), CARRY => CARRY(45)
);
---- End FA stage
-- End WT-branch 46
-- Begin WT-branch 47
---- Begin FA stage
FA_397:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500),
SAVE => INT_SUM(493), CARRY => INT_CARRY(393)
);
---- End FA stage
---- Begin FA stage
FA_398:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503),
SAVE => INT_SUM(494), CARRY => INT_CARRY(394)
);
---- End FA stage
---- Begin FA stage
FA_399:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506),
SAVE => INT_SUM(495), CARRY => INT_CARRY(395)
);
---- End FA stage
---- Begin NO stage
INT_SUM(496) <= SUMMAND(507); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(497) <= SUMMAND(508); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_400:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495),
SAVE => INT_SUM(498), CARRY => INT_CARRY(396)
);
---- End FA stage
---- Begin FA stage
FA_401:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383),
SAVE => INT_SUM(499), CARRY => INT_CARRY(397)
);
---- End FA stage
---- Begin FA stage
FA_402:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386),
SAVE => INT_SUM(500), CARRY => INT_CARRY(398)
);
---- End FA stage
---- Begin FA stage
FA_403:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500),
SAVE => INT_SUM(501), CARRY => INT_CARRY(399)
);
---- End FA stage
---- Begin FA stage
FA_404:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389),
SAVE => INT_SUM(502), CARRY => INT_CARRY(400)
);
---- End FA stage
---- Begin FA stage
FA_405:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390),
SAVE => INT_SUM(503), CARRY => INT_CARRY(401)
);
---- End FA stage
---- Begin NO stage
INT_SUM(504) <= INT_CARRY(391); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_406:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392),
SAVE => SUM(46), CARRY => CARRY(46)
);
---- End FA stage
-- End WT-branch 47
-- Begin WT-branch 48
---- Begin FA stage
FA_407:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511),
SAVE => INT_SUM(505), CARRY => INT_CARRY(402)
);
---- End FA stage
---- Begin FA stage
FA_408:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514),
SAVE => INT_SUM(506), CARRY => INT_CARRY(403)
);
---- End FA stage
---- Begin FA stage
FA_409:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517),
SAVE => INT_SUM(507), CARRY => INT_CARRY(404)
);
---- End FA stage
---- Begin HA stage
HA_41:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(518), DATA_B => SUMMAND(519),
SAVE => INT_SUM(508), CARRY => INT_CARRY(405)
);
---- End HA stage
---- Begin FA stage
FA_410:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507),
SAVE => INT_SUM(509), CARRY => INT_CARRY(406)
);
---- End FA stage
---- Begin FA stage
FA_411:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394),
SAVE => INT_SUM(510), CARRY => INT_CARRY(407)
);
---- End FA stage
---- Begin NO stage
INT_SUM(511) <= INT_CARRY(395); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_412:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511),
SAVE => INT_SUM(512), CARRY => INT_CARRY(408)
);
---- End FA stage
---- Begin FA stage
FA_413:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398),
SAVE => INT_SUM(513), CARRY => INT_CARRY(409)
);
---- End FA stage
---- Begin FA stage
FA_414:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399),
SAVE => INT_SUM(514), CARRY => INT_CARRY(410)
);
---- End FA stage
---- Begin NO stage
INT_SUM(515) <= INT_CARRY(400); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_415:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401),
SAVE => SUM(47), CARRY => CARRY(47)
);
---- End FA stage
-- End WT-branch 48
-- Begin WT-branch 49
---- Begin FA stage
FA_416:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522),
SAVE => INT_SUM(516), CARRY => INT_CARRY(411)
);
---- End FA stage
---- Begin FA stage
FA_417:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525),
SAVE => INT_SUM(517), CARRY => INT_CARRY(412)
);
---- End FA stage
---- Begin FA stage
FA_418:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528),
SAVE => INT_SUM(518), CARRY => INT_CARRY(413)
);
---- End FA stage
---- Begin NO stage
INT_SUM(519) <= SUMMAND(529); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_419:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518),
SAVE => INT_SUM(520), CARRY => INT_CARRY(414)
);
---- End FA stage
---- Begin FA stage
FA_420:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403),
SAVE => INT_SUM(521), CARRY => INT_CARRY(415)
);
---- End FA stage
---- Begin NO stage
INT_SUM(522) <= INT_CARRY(404); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(523) <= INT_CARRY(405); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_421:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522),
SAVE => INT_SUM(524), CARRY => INT_CARRY(416)
);
---- End FA stage
---- Begin FA stage
FA_422:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407),
SAVE => INT_SUM(525), CARRY => INT_CARRY(417)
);
---- End FA stage
---- Begin FA stage
FA_423:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408),
SAVE => INT_SUM(526), CARRY => INT_CARRY(418)
);
---- End FA stage
---- Begin NO stage
INT_SUM(527) <= INT_CARRY(409); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_424:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410),
SAVE => SUM(48), CARRY => CARRY(48)
);
---- End FA stage
-- End WT-branch 49
-- Begin WT-branch 50
---- Begin FA stage
FA_425:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532),
SAVE => INT_SUM(528), CARRY => INT_CARRY(419)
);
---- End FA stage
---- Begin FA stage
FA_426:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535),
SAVE => INT_SUM(529), CARRY => INT_CARRY(420)
);
---- End FA stage
---- Begin FA stage
FA_427:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538),
SAVE => INT_SUM(530), CARRY => INT_CARRY(421)
);
---- End FA stage
---- Begin NO stage
INT_SUM(531) <= SUMMAND(539); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_428:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530),
SAVE => INT_SUM(532), CARRY => INT_CARRY(422)
);
---- End FA stage
---- Begin FA stage
FA_429:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412),
SAVE => INT_SUM(533), CARRY => INT_CARRY(423)
);
---- End FA stage
---- Begin NO stage
INT_SUM(534) <= INT_CARRY(413); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_430:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534),
SAVE => INT_SUM(535), CARRY => INT_CARRY(424)
);
---- End FA stage
---- Begin HA stage
HA_42:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415),
SAVE => INT_SUM(536), CARRY => INT_CARRY(425)
);
---- End HA stage
---- Begin FA stage
FA_431:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416),
SAVE => INT_SUM(537), CARRY => INT_CARRY(426)
);
---- End FA stage
---- Begin NO stage
INT_SUM(538) <= INT_CARRY(417); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_432:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418),
SAVE => SUM(49), CARRY => CARRY(49)
);
---- End FA stage
-- End WT-branch 50
-- Begin WT-branch 51
---- Begin FA stage
FA_433:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542),
SAVE => INT_SUM(539), CARRY => INT_CARRY(427)
);
---- End FA stage
---- Begin FA stage
FA_434:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545),
SAVE => INT_SUM(540), CARRY => INT_CARRY(428)
);
---- End FA stage
---- Begin FA stage
FA_435:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548),
SAVE => INT_SUM(541), CARRY => INT_CARRY(429)
);
---- End FA stage
---- Begin FA stage
FA_436:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541),
SAVE => INT_SUM(542), CARRY => INT_CARRY(430)
);
---- End FA stage
---- Begin FA stage
FA_437:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421),
SAVE => INT_SUM(543), CARRY => INT_CARRY(431)
);
---- End FA stage
---- Begin FA stage
FA_438:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422),
SAVE => INT_SUM(544), CARRY => INT_CARRY(432)
);
---- End FA stage
---- Begin NO stage
INT_SUM(545) <= INT_CARRY(423); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_439:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424),
SAVE => INT_SUM(546), CARRY => INT_CARRY(433)
);
---- End FA stage
---- Begin NO stage
INT_SUM(547) <= INT_CARRY(425); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_440:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426),
SAVE => SUM(50), CARRY => CARRY(50)
);
---- End FA stage
-- End WT-branch 51
-- Begin WT-branch 52
---- Begin FA stage
FA_441:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551),
SAVE => INT_SUM(548), CARRY => INT_CARRY(434)
);
---- End FA stage
---- Begin FA stage
FA_442:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554),
SAVE => INT_SUM(549), CARRY => INT_CARRY(435)
);
---- End FA stage
---- Begin FA stage
FA_443:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557),
SAVE => INT_SUM(550), CARRY => INT_CARRY(436)
);
---- End FA stage
---- Begin FA stage
FA_444:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550),
SAVE => INT_SUM(551), CARRY => INT_CARRY(437)
);
---- End FA stage
---- Begin FA stage
FA_445:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429),
SAVE => INT_SUM(552), CARRY => INT_CARRY(438)
);
---- End FA stage
---- Begin FA stage
FA_446:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430),
SAVE => INT_SUM(553), CARRY => INT_CARRY(439)
);
---- End FA stage
---- Begin NO stage
INT_SUM(554) <= INT_CARRY(431); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_447:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432),
SAVE => INT_SUM(555), CARRY => INT_CARRY(440)
);
---- End FA stage
---- Begin HA stage
HA_43:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433),
SAVE => SUM(51), CARRY => CARRY(51)
);
---- End HA stage
-- End WT-branch 52
-- Begin WT-branch 53
---- Begin FA stage
FA_448:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560),
SAVE => INT_SUM(556), CARRY => INT_CARRY(441)
);
---- End FA stage
---- Begin FA stage
FA_449:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563),
SAVE => INT_SUM(557), CARRY => INT_CARRY(442)
);
---- End FA stage
---- Begin FA stage
FA_450:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434),
SAVE => INT_SUM(558), CARRY => INT_CARRY(443)
);
---- End FA stage
---- Begin HA stage
HA_44:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436),
SAVE => INT_SUM(559), CARRY => INT_CARRY(444)
);
---- End HA stage
---- Begin FA stage
FA_451:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558),
SAVE => INT_SUM(560), CARRY => INT_CARRY(445)
);
---- End FA stage
---- Begin FA stage
FA_452:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438),
SAVE => INT_SUM(561), CARRY => INT_CARRY(446)
);
---- End FA stage
---- Begin FA stage
FA_453:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439),
SAVE => INT_SUM(562), CARRY => INT_CARRY(447)
);
---- End FA stage
---- Begin HA stage
HA_45:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440),
SAVE => SUM(52), CARRY => CARRY(52)
);
---- End HA stage
-- End WT-branch 53
-- Begin WT-branch 54
---- Begin FA stage
FA_454:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568),
SAVE => INT_SUM(563), CARRY => INT_CARRY(448)
);
---- End FA stage
---- Begin FA stage
FA_455:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571),
SAVE => INT_SUM(564), CARRY => INT_CARRY(449)
);
---- End FA stage
---- Begin NO stage
INT_SUM(565) <= SUMMAND(572); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(566) <= SUMMAND(573); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_456:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565),
SAVE => INT_SUM(567), CARRY => INT_CARRY(450)
);
---- End FA stage
---- Begin NO stage
INT_SUM(568) <= INT_SUM(566); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_457:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441),
SAVE => INT_SUM(569), CARRY => INT_CARRY(451)
);
---- End FA stage
---- Begin FA stage
FA_458:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444),
SAVE => INT_SUM(570), CARRY => INT_CARRY(452)
);
---- End FA stage
---- Begin FA stage
FA_459:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445),
SAVE => INT_SUM(571), CARRY => INT_CARRY(453)
);
---- End FA stage
---- Begin NO stage
INT_SUM(572) <= INT_CARRY(446); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_460:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447),
SAVE => SUM(53), CARRY => CARRY(53)
);
---- End FA stage
-- End WT-branch 54
-- Begin WT-branch 55
---- Begin FA stage
FA_461:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576),
SAVE => INT_SUM(573), CARRY => INT_CARRY(454)
);
---- End FA stage
---- Begin FA stage
FA_462:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579),
SAVE => INT_SUM(574), CARRY => INT_CARRY(455)
);
---- End FA stage
---- Begin FA stage
FA_463:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449),
SAVE => INT_SUM(575), CARRY => INT_CARRY(456)
);
---- End FA stage
---- Begin FA stage
FA_464:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575),
SAVE => INT_SUM(576), CARRY => INT_CARRY(457)
);
---- End FA stage
---- Begin NO stage
INT_SUM(577) <= INT_CARRY(450); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_465:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451),
SAVE => INT_SUM(578), CARRY => INT_CARRY(458)
);
---- End FA stage
---- Begin NO stage
INT_SUM(579) <= INT_CARRY(452); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_466:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453),
SAVE => SUM(54), CARRY => CARRY(54)
);
---- End FA stage
-- End WT-branch 55
-- Begin WT-branch 56
---- Begin FA stage
FA_467:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583),
SAVE => INT_SUM(580), CARRY => INT_CARRY(459)
);
---- End FA stage
---- Begin FA stage
FA_468:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586),
SAVE => INT_SUM(581), CARRY => INT_CARRY(460)
);
---- End FA stage
---- Begin NO stage
INT_SUM(582) <= SUMMAND(587); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_469:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582),
SAVE => INT_SUM(583), CARRY => INT_CARRY(461)
);
---- End FA stage
---- Begin FA stage
FA_470:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456),
SAVE => INT_SUM(584), CARRY => INT_CARRY(462)
);
---- End FA stage
---- Begin FA stage
FA_471:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457),
SAVE => INT_SUM(585), CARRY => INT_CARRY(463)
);
---- End FA stage
---- Begin HA stage
HA_46:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458),
SAVE => SUM(55), CARRY => CARRY(55)
);
---- End HA stage
-- End WT-branch 56
-- Begin WT-branch 57
---- Begin FA stage
FA_472:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590),
SAVE => INT_SUM(586), CARRY => INT_CARRY(464)
);
---- End FA stage
---- Begin FA stage
FA_473:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593),
SAVE => INT_SUM(587), CARRY => INT_CARRY(465)
);
---- End FA stage
---- Begin FA stage
FA_474:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459),
SAVE => INT_SUM(588), CARRY => INT_CARRY(466)
);
---- End FA stage
---- Begin NO stage
INT_SUM(589) <= INT_CARRY(460); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_475:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461),
SAVE => INT_SUM(590), CARRY => INT_CARRY(467)
);
---- End FA stage
---- Begin NO stage
INT_SUM(591) <= INT_CARRY(462); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_476:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463),
SAVE => SUM(56), CARRY => CARRY(56)
);
---- End FA stage
-- End WT-branch 57
-- Begin WT-branch 58
---- Begin FA stage
FA_477:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596),
SAVE => INT_SUM(592), CARRY => INT_CARRY(468)
);
---- End FA stage
---- Begin FA stage
FA_478:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599),
SAVE => INT_SUM(593), CARRY => INT_CARRY(469)
);
---- End FA stage
---- Begin FA stage
FA_479:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464),
SAVE => INT_SUM(594), CARRY => INT_CARRY(470)
);
---- End FA stage
---- Begin NO stage
INT_SUM(595) <= INT_CARRY(465); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_480:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466),
SAVE => INT_SUM(596), CARRY => INT_CARRY(471)
);
---- End FA stage
---- Begin HA stage
HA_47:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467),
SAVE => SUM(57), CARRY => CARRY(57)
);
---- End HA stage
-- End WT-branch 58
-- Begin WT-branch 59
---- Begin FA stage
FA_481:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602),
SAVE => INT_SUM(597), CARRY => INT_CARRY(472)
);
---- End FA stage
---- Begin HA stage
HA_48:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(603), DATA_B => SUMMAND(604),
SAVE => INT_SUM(598), CARRY => INT_CARRY(473)
);
---- End HA stage
---- Begin FA stage
FA_482:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468),
SAVE => INT_SUM(599), CARRY => INT_CARRY(474)
);
---- End FA stage
---- Begin NO stage
INT_SUM(600) <= INT_CARRY(469); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_483:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470),
SAVE => INT_SUM(601), CARRY => INT_CARRY(475)
);
---- End FA stage
---- Begin HA stage
HA_49:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471),
SAVE => SUM(58), CARRY => CARRY(58)
);
---- End HA stage
-- End WT-branch 59
-- Begin WT-branch 60
---- Begin FA stage
FA_484:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607),
SAVE => INT_SUM(602), CARRY => INT_CARRY(476)
);
---- End FA stage
---- Begin HA stage
HA_50:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(608), DATA_B => SUMMAND(609),
SAVE => INT_SUM(603), CARRY => INT_CARRY(477)
);
---- End HA stage
---- Begin FA stage
FA_485:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472),
SAVE => INT_SUM(604), CARRY => INT_CARRY(478)
);
---- End FA stage
---- Begin NO stage
INT_SUM(605) <= INT_CARRY(473); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_486:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474),
SAVE => INT_SUM(606), CARRY => INT_CARRY(479)
);
---- End FA stage
---- Begin HA stage
HA_51:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475),
SAVE => SUM(59), CARRY => CARRY(59)
);
---- End HA stage
-- End WT-branch 60
-- Begin WT-branch 61
---- Begin FA stage
FA_487:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612),
SAVE => INT_SUM(607), CARRY => INT_CARRY(480)
);
---- End FA stage
---- Begin FA stage
FA_488:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477),
SAVE => INT_SUM(608), CARRY => INT_CARRY(481)
);
---- End FA stage
---- Begin FA stage
FA_489:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478),
SAVE => INT_SUM(609), CARRY => INT_CARRY(482)
);
---- End FA stage
---- Begin HA stage
HA_52:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479),
SAVE => SUM(60), CARRY => CARRY(60)
);
---- End HA stage
-- End WT-branch 61
-- Begin WT-branch 62
---- Begin FA stage
FA_490:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616),
SAVE => INT_SUM(610), CARRY => INT_CARRY(483)
);
---- End FA stage
---- Begin NO stage
INT_SUM(611) <= SUMMAND(617); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_491:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480),
SAVE => INT_SUM(612), CARRY => INT_CARRY(484)
);
---- End FA stage
---- Begin NO stage
INT_SUM(613) <= INT_CARRY(481); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_492:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482),
SAVE => SUM(61), CARRY => CARRY(61)
);
---- End FA stage
-- End WT-branch 62
-- Begin WT-branch 63
---- Begin FA stage
FA_493:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620),
SAVE => INT_SUM(614), CARRY => INT_CARRY(485)
);
---- End FA stage
---- Begin NO stage
INT_SUM(615) <= INT_SUM(614); -- At Level 5
---- End NO stage
---- Begin NO stage
INT_SUM(616) <= INT_CARRY(483); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_494:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484),
SAVE => SUM(62), CARRY => CARRY(62)
);
---- End FA stage
-- End WT-branch 63
-- Begin WT-branch 64
---- Begin FA stage
FA_495:FULL_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623),
SAVE => INT_SUM(617), CARRY => INT_CARRY(486)
);
---- End FA stage
---- Begin NO stage
INT_SUM(618) <= INT_CARRY(485); -- At Level 5
---- End NO stage
---- Begin HA stage
HA_53:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(617), DATA_B => INT_SUM(618),
SAVE => SUM(63), CARRY => CARRY(63)
);
---- End HA stage
-- End WT-branch 64
-- Begin WT-branch 65
---- Begin NO stage
INT_SUM(619) <= SUMMAND(624); -- At Level 5
---- End NO stage
---- Begin NO stage
INT_SUM(620) <= SUMMAND(625); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_496:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486),
SAVE => SUM(64), CARRY => CARRY(64)
);
---- End FA stage
-- End WT-branch 65
-- Begin WT-branch 66
---- Begin HA stage
HA_54:HALF_ADDER -- At Level 6
port map
(
DATA_A => SUMMAND(626), DATA_B => SUMMAND(627),
SAVE => SUM(65), CARRY => CARRY(65)
);
---- End HA stage
-- End WT-branch 66
-- Begin WT-branch 67
---- Begin NO stage
SUM(66) <= SUMMAND(628); -- At Level 6
---- End NO stage
-- End WT-branch 67
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture RTL of MULTIPLIER_34_34 is
component BOOTHCODER_34_34
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 33);
SUMMAND: out std_logic_vector(0 to 628)
);
end component;
component WALLACE_34_34
port
(
SUMMAND: in std_logic_vector(0 to 628);
CARRY: out std_logic_vector(0 to 65);
SUM: out std_logic_vector(0 to 66)
);
end component;
component DBLCADDER_128_128
port
(
OPA:in std_logic_vector(0 to 127);
OPB:in std_logic_vector(0 to 127);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 127)
);
end component;
signal PPBIT:std_logic_vector(0 to 628);
signal INT_CARRY: std_logic_vector(0 to 128);
signal INT_SUM: std_logic_vector(0 to 127);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_34
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 33) => MULTIPLIER(0 to 33),
SUMMAND(0 to 628) => PPBIT(0 to 628)
);
W:WALLACE_34_34
port map
(
SUMMAND(0 to 628) => PPBIT(0 to 628),
CARRY(0 to 65) => INT_CARRY(1 to 66),
SUM(0 to 66) => INT_SUM(0 to 66)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(67) <= LOGIC_ZERO;
INT_CARRY(68) <= LOGIC_ZERO;
INT_CARRY(69) <= LOGIC_ZERO;
INT_CARRY(70) <= LOGIC_ZERO;
INT_CARRY(71) <= LOGIC_ZERO;
INT_CARRY(72) <= LOGIC_ZERO;
INT_CARRY(73) <= LOGIC_ZERO;
INT_CARRY(74) <= LOGIC_ZERO;
INT_CARRY(75) <= LOGIC_ZERO;
INT_CARRY(76) <= LOGIC_ZERO;
INT_CARRY(77) <= LOGIC_ZERO;
INT_CARRY(78) <= LOGIC_ZERO;
INT_CARRY(79) <= LOGIC_ZERO;
INT_CARRY(80) <= LOGIC_ZERO;
INT_CARRY(81) <= LOGIC_ZERO;
INT_CARRY(82) <= LOGIC_ZERO;
INT_CARRY(83) <= LOGIC_ZERO;
INT_CARRY(84) <= LOGIC_ZERO;
INT_CARRY(85) <= LOGIC_ZERO;
INT_CARRY(86) <= LOGIC_ZERO;
INT_CARRY(87) <= LOGIC_ZERO;
INT_CARRY(88) <= LOGIC_ZERO;
INT_CARRY(89) <= LOGIC_ZERO;
INT_CARRY(90) <= LOGIC_ZERO;
INT_CARRY(91) <= LOGIC_ZERO;
INT_CARRY(92) <= LOGIC_ZERO;
INT_CARRY(93) <= LOGIC_ZERO;
INT_CARRY(94) <= LOGIC_ZERO;
INT_CARRY(95) <= LOGIC_ZERO;
INT_CARRY(96) <= LOGIC_ZERO;
INT_CARRY(97) <= LOGIC_ZERO;
INT_CARRY(98) <= LOGIC_ZERO;
INT_CARRY(99) <= LOGIC_ZERO;
INT_CARRY(100) <= LOGIC_ZERO;
INT_CARRY(101) <= LOGIC_ZERO;
INT_CARRY(102) <= LOGIC_ZERO;
INT_CARRY(103) <= LOGIC_ZERO;
INT_CARRY(104) <= LOGIC_ZERO;
INT_CARRY(105) <= LOGIC_ZERO;
INT_CARRY(106) <= LOGIC_ZERO;
INT_CARRY(107) <= LOGIC_ZERO;
INT_CARRY(108) <= LOGIC_ZERO;
INT_CARRY(109) <= LOGIC_ZERO;
INT_CARRY(110) <= LOGIC_ZERO;
INT_CARRY(111) <= LOGIC_ZERO;
INT_CARRY(112) <= LOGIC_ZERO;
INT_CARRY(113) <= LOGIC_ZERO;
INT_CARRY(114) <= LOGIC_ZERO;
INT_CARRY(115) <= LOGIC_ZERO;
INT_CARRY(116) <= LOGIC_ZERO;
INT_CARRY(117) <= LOGIC_ZERO;
INT_CARRY(118) <= LOGIC_ZERO;
INT_CARRY(119) <= LOGIC_ZERO;
INT_CARRY(120) <= LOGIC_ZERO;
INT_CARRY(121) <= LOGIC_ZERO;
INT_CARRY(122) <= LOGIC_ZERO;
INT_CARRY(123) <= LOGIC_ZERO;
INT_CARRY(124) <= LOGIC_ZERO;
INT_CARRY(125) <= LOGIC_ZERO;
INT_CARRY(126) <= LOGIC_ZERO;
INT_CARRY(127) <= LOGIC_ZERO;
INT_SUM(67) <= LOGIC_ZERO;
INT_SUM(68) <= LOGIC_ZERO;
INT_SUM(69) <= LOGIC_ZERO;
INT_SUM(70) <= LOGIC_ZERO;
INT_SUM(71) <= LOGIC_ZERO;
INT_SUM(72) <= LOGIC_ZERO;
INT_SUM(73) <= LOGIC_ZERO;
INT_SUM(74) <= LOGIC_ZERO;
INT_SUM(75) <= LOGIC_ZERO;
INT_SUM(76) <= LOGIC_ZERO;
INT_SUM(77) <= LOGIC_ZERO;
INT_SUM(78) <= LOGIC_ZERO;
INT_SUM(79) <= LOGIC_ZERO;
INT_SUM(80) <= LOGIC_ZERO;
INT_SUM(81) <= LOGIC_ZERO;
INT_SUM(82) <= LOGIC_ZERO;
INT_SUM(83) <= LOGIC_ZERO;
INT_SUM(84) <= LOGIC_ZERO;
INT_SUM(85) <= LOGIC_ZERO;
INT_SUM(86) <= LOGIC_ZERO;
INT_SUM(87) <= LOGIC_ZERO;
INT_SUM(88) <= LOGIC_ZERO;
INT_SUM(89) <= LOGIC_ZERO;
INT_SUM(90) <= LOGIC_ZERO;
INT_SUM(91) <= LOGIC_ZERO;
INT_SUM(92) <= LOGIC_ZERO;
INT_SUM(93) <= LOGIC_ZERO;
INT_SUM(94) <= LOGIC_ZERO;
INT_SUM(95) <= LOGIC_ZERO;
INT_SUM(96) <= LOGIC_ZERO;
INT_SUM(97) <= LOGIC_ZERO;
INT_SUM(98) <= LOGIC_ZERO;
INT_SUM(99) <= LOGIC_ZERO;
INT_SUM(100) <= LOGIC_ZERO;
INT_SUM(101) <= LOGIC_ZERO;
INT_SUM(102) <= LOGIC_ZERO;
INT_SUM(103) <= LOGIC_ZERO;
INT_SUM(104) <= LOGIC_ZERO;
INT_SUM(105) <= LOGIC_ZERO;
INT_SUM(106) <= LOGIC_ZERO;
INT_SUM(107) <= LOGIC_ZERO;
INT_SUM(108) <= LOGIC_ZERO;
INT_SUM(109) <= LOGIC_ZERO;
INT_SUM(110) <= LOGIC_ZERO;
INT_SUM(111) <= LOGIC_ZERO;
INT_SUM(112) <= LOGIC_ZERO;
INT_SUM(113) <= LOGIC_ZERO;
INT_SUM(114) <= LOGIC_ZERO;
INT_SUM(115) <= LOGIC_ZERO;
INT_SUM(116) <= LOGIC_ZERO;
INT_SUM(117) <= LOGIC_ZERO;
INT_SUM(118) <= LOGIC_ZERO;
INT_SUM(119) <= LOGIC_ZERO;
INT_SUM(120) <= LOGIC_ZERO;
INT_SUM(121) <= LOGIC_ZERO;
INT_SUM(122) <= LOGIC_ZERO;
INT_SUM(123) <= LOGIC_ZERO;
INT_SUM(124) <= LOGIC_ZERO;
INT_SUM(125) <= LOGIC_ZERO;
INT_SUM(126) <= LOGIC_ZERO;
INT_SUM(127) <= LOGIC_ZERO;
D:DBLCADDER_128_128
port map
(
OPA(0 to 127) => INT_SUM(0 to 127),
OPB(0 to 127) => INT_CARRY(0 to 127),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 127) => RESULT(0 to 127)
);
end RTL;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ADD32 is
port(X: in std_logic_vector(31 downto 0);
Y: in std_logic_vector(31 downto 0);
CI: in std_logic;
S: out std_logic_vector(31 downto 0);
CO: out std_logic);
end ADD32;
library ieee;
use ieee.std_logic_1164.all;
architecture A of ADD32 is
component DBLCADDER_32_32
port(OPA: in std_logic_vector(0 to 31);
OPB: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic);
end component;
signal A,B,Q: std_logic_vector(0 to 31);
signal CLK: std_logic;
begin
U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
B(0) <= Y(0);
A(1) <= X(1);
B(1) <= Y(1);
A(2) <= X(2);
B(2) <= Y(2);
A(3) <= X(3);
B(3) <= Y(3);
A(4) <= X(4);
B(4) <= Y(4);
A(5) <= X(5);
B(5) <= Y(5);
A(6) <= X(6);
B(6) <= Y(6);
A(7) <= X(7);
B(7) <= Y(7);
A(8) <= X(8);
B(8) <= Y(8);
A(9) <= X(9);
B(9) <= Y(9);
A(10) <= X(10);
B(10) <= Y(10);
A(11) <= X(11);
B(11) <= Y(11);
A(12) <= X(12);
B(12) <= Y(12);
A(13) <= X(13);
B(13) <= Y(13);
A(14) <= X(14);
B(14) <= Y(14);
A(15) <= X(15);
B(15) <= Y(15);
A(16) <= X(16);
B(16) <= Y(16);
A(17) <= X(17);
B(17) <= Y(17);
A(18) <= X(18);
B(18) <= Y(18);
A(19) <= X(19);
B(19) <= Y(19);
A(20) <= X(20);
B(20) <= Y(20);
A(21) <= X(21);
B(21) <= Y(21);
A(22) <= X(22);
B(22) <= Y(22);
A(23) <= X(23);
B(23) <= Y(23);
A(24) <= X(24);
B(24) <= Y(24);
A(25) <= X(25);
B(25) <= Y(25);
A(26) <= X(26);
B(26) <= Y(26);
A(27) <= X(27);
B(27) <= Y(27);
A(28) <= X(28);
B(28) <= Y(28);
A(29) <= X(29);
B(29) <= Y(29);
A(30) <= X(30);
B(30) <= Y(30);
A(31) <= X(31);
B(31) <= Y(31);
S(0) <= Q(0);
S(1) <= Q(1);
S(2) <= Q(2);
S(3) <= Q(3);
S(4) <= Q(4);
S(5) <= Q(5);
S(6) <= Q(6);
S(7) <= Q(7);
S(8) <= Q(8);
S(9) <= Q(9);
S(10) <= Q(10);
S(11) <= Q(11);
S(12) <= Q(12);
S(13) <= Q(13);
S(14) <= Q(14);
S(15) <= Q(15);
S(16) <= Q(16);
S(17) <= Q(17);
S(18) <= Q(18);
S(19) <= Q(19);
S(20) <= Q(20);
S(21) <= Q(21);
S(22) <= Q(22);
S(23) <= Q(23);
S(24) <= Q(24);
S(25) <= Q(25);
S(26) <= Q(26);
S(27) <= Q(27);
S(28) <= Q(28);
S(29) <= Q(29);
S(30) <= Q(30);
S(31) <= Q(31);
end A;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.data_type.all;
-- Decode from byte stream to Rq polynomaial. Does not shift elements by q!
entity decode_Rq is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
input : in std_logic_vector(7 downto 0);
input_valid : in std_logic;
input_ack : out std_logic;
rounded_decode : in std_logic;
output : out std_logic_vector(q_num_bits - 1 downto 0);
output_valid : out std_logic;
done : out std_logic
);
end entity decode_Rq;
architecture RTL of decode_Rq is
type state_type is (idle, loop_input, loop_input_one, loop_input_two, loop_input_two_r, next_recursion, loop_finalize, recursion_end_wait,
recursion_end, recursion_end_2, recursion_end_3, begin_recusion, loop_one_d, loop_if_prep, loop_if_case,
loop_if_one_S0,
loop_if_one_S1, loop_if_two, loop_if_three, next_loop, loop_two_prep, loop_two_case, loop_two_wait,
loop_two_fma, loop_two_divmod, loop_two_store, loop_two_d_end, loop_two_d_end_write, loop_two_flush,
output_loop, output_loop_wait, output_loop_fma, output_loop_divmod, output_loop_end, output_loop_end_2,
output_end_write, output_flush_pipe, decode_done
);
signal state_decode : state_type;
signal i : integer range 0 to p;
signal reg_length : integer range 0 to p;
constant max_depth : integer := p_num_bits;
signal depth_counter : integer range 0 to max_depth;
signal reg_S0 : std_logic_vector(7 downto 0);
signal reg_S1 : std_logic_vector(7 downto 0);
signal reg_m : unsigned(31 downto 0);
signal reg_m2 : unsigned(31 downto 0);
signal reg_r : unsigned(31 downto 0);
signal reg_r0 : unsigned(15 downto 0);
signal reg_r1 : unsigned(15 downto 0);
signal reg_Mi0 : unsigned(15 downto 0);
--signal reg_Mi1 : unsigned(15 downto 0);
signal address_offset : integer range 0 to 2**p_num_bits;
signal address_offset_next : integer range 0 to 2**p_num_bits;
signal pop_stack : std_logic;
signal push_stack : std_logic;
signal stack_input : integer range 0 to 2**p_num_bits;
signal stack_output : integer range 0 to 2**p_num_bits;
signal output_reg_r0 : std_logic;
signal output_reg_r1 : std_logic;
signal output_reg_r0_only : std_logic;
signal dividend : std_logic_vector(31 downto 0);
signal divisor_index : std_logic_vector(6 downto 0);
signal divisor_index_mod : std_logic_vector(6 downto 0);
signal remainder_mod : std_logic_vector(15 downto 0);
signal decode_command_pipe_in : std_logic;
signal decode_command_pipe_out : std_logic;
signal bram_R2_address_pipe_in : std_logic_vector(p_num_bits - 1 downto 0);
signal bram_R2_address_pipe_out : std_logic_vector(p_num_bits - 1 downto 0);
signal store_cmd_pipe_in : divmod_cmd;
signal store_cmd_pipe_out : divmod_cmd;
signal remainder_pipe_delay_out : std_logic_vector(15 downto 0);
signal pipe_flush_counter : integer range 0 to 66;
signal decode_command : std_logic;
signal reg_store_both : std_logic;
signal reg_store_address : std_logic_vector(p_num_bits - 1 downto 0);
signal reg_remainder_mod : std_logic_vector(15 downto 0);
signal bram_R2_address_a : std_logic_vector(p_num_bits - 1 downto 0);
signal bram_R2_write_a : std_logic;
signal bram_R2_data_in_a : std_logic_vector(15 downto 0);
signal bram_R2_data_out_a : std_logic_vector(15 downto 0);
signal bram_R2_address_b : std_logic_vector(p_num_bits - 1 downto 0);
signal bram_R2_write_b : std_logic;
signal bram_R2_data_in_b : std_logic_vector(15 downto 0);
--signal bram_R2_data_out_b : std_logic_vector(15 downto 0);
signal bram_br_address_a : std_logic_vector(p_num_bits - 1 downto 0);
signal bram_br_write_a : std_logic;
signal bram_br_data_in_a : std_logic_vector(15 downto 0);
signal bram_br_data_out_a : std_logic_vector(15 downto 0);
signal bram_br_address_b : std_logic_vector(p_num_bits - 1 downto 0);
signal bram_br_write_b : std_logic;
signal bram_br_data_in_b : std_logic_vector(15 downto 0);
--signal bram_br_data_out_b : std_logic_vector(15 downto 0);
signal rounded_index_offset : integer range 0 to 21;
begin
fsm_process : process(clock, reset) is
variable i_2_before_end : integer := 0;
begin
if reset = '1' then
state_decode <= idle;
decode_command_pipe_in <= '0';
bram_R2_write_a <= '0';
--bram_R2_write_b <= '0';
bram_br_write_a <= '0';
bram_br_write_b <= '0';
push_stack <= '0';
pop_stack <= '0';
done <= '0';
elsif rising_edge(clock) then
case state_decode is
when idle =>
if start = '1' then
state_decode <= loop_input;
end if;
i <= 0;
depth_counter <= 0;
address_offset <= 0;
address_offset_next <= 0;
reg_length <= p;
bram_R2_write_a <= '0';
--bram_R2_write_b <= '0';
bram_br_write_a <= '0';
bram_br_write_b <= '0';
push_stack <= '0';
pop_stack <= '0';
done <= '0';
decode_command_pipe_in <= '0';
bram_R2_address_pipe_in <= (others => '0');
when loop_input =>
if i < reg_length - 1 then
if input_valid = '1' then
state_decode <= loop_input_one;
reg_S0 <= input;
end if;
else
state_decode <= next_recursion;
end if;
bram_br_write_a <= '0';
when loop_input_one =>
if rounded_decode = '1' then
state_decode <= loop_input_two_r;
else
if input_valid = '1' then
state_decode <= loop_input_two;
end if;
reg_S1 <= input;
end if;
when loop_input_two =>
state_decode <= loop_input;
bram_br_data_in_a <= std_logic_vector(unsigned(reg_S0) + shift_left(resize(unsigned(reg_S1), 16), 8));
bram_br_address_a <= std_logic_vector(to_unsigned(i / 2, p_num_bits));
bram_br_write_a <= '1';
i <= i + 2;
when loop_input_two_r =>
state_decode <= loop_input;
bram_br_data_in_a <= std_logic_vector(resize(unsigned(reg_S0), 16));
bram_br_address_a <= std_logic_vector(to_unsigned(i / 2, p_num_bits));
bram_br_write_a <= '1';
i <= i + 2;
when next_recursion =>
state_decode <= begin_recusion;
depth_counter <= depth_counter + 1;
address_offset <= address_offset_next;
address_offset_next <= address_offset_next + (reg_length + 1) / 2;
reg_length <= (reg_length + 1) / 2;
i <= 0;
stack_input <= reg_length;
push_stack <= '1';
when begin_recusion =>
if reg_length = 1 then
state_decode <= recursion_end_wait;
else
state_decode <= loop_one_d;
end if;
push_stack <= '0';
when recursion_end_wait =>
state_decode <= recursion_end;
when recursion_end =>
if M_array(depth_counter + rounded_index_offset) = 1 then -- TODO This never happens at the moment
state_decode <= loop_two_flush; --loop_two_case;
dividend <= std_logic_vector(to_unsigned(q, 32));
divisor_index <= std_logic_vector(to_unsigned(0, 7));
divisor_index_mod <= std_logic_vector(to_unsigned(0, 7));
decode_command_pipe_in <= '1';
bram_R2_address_pipe_in <= std_logic_vector(to_unsigned(address_offset, p_num_bits));
store_cmd_pipe_in <= cmd_store_remainder;
else
if input_valid = '1' then
reg_S0 <= input;
state_decode <= recursion_end_2;
end if;
reg_Mi0 <= to_unsigned(M_array(depth_counter + rounded_index_offset), 16);
end if;
pipe_flush_counter <= 0;
when recursion_end_2 =>
if reg_Mi0 <= to_unsigned(256, 16) then
state_decode <= loop_two_flush; --loop_two_case;
dividend <= std_logic_vector(resize(unsigned(reg_S0), 32));
divisor_index <= std_logic_vector(to_unsigned(depth_counter + rounded_index_offset, 7));
divisor_index_mod <= std_logic_vector(to_unsigned(depth_counter + rounded_index_offset, 7));
decode_command_pipe_in <= '1';
bram_R2_address_pipe_in <= std_logic_vector(to_unsigned(address_offset, p_num_bits));
store_cmd_pipe_in <= cmd_store_remainder;
else
if input_valid = '1' then
reg_S1 <= input;
state_decode <= recursion_end_3;
end if;
end if;
when recursion_end_3 =>
state_decode <= loop_two_flush; --loop_two_prep;
dividend <= std_logic_vector(resize(unsigned(reg_S1) & unsigned(reg_S0), 32));
divisor_index <= std_logic_vector(to_unsigned(depth_counter + rounded_index_offset, 7));
divisor_index_mod <= std_logic_vector(to_unsigned(depth_counter + rounded_index_offset, 7));
decode_command_pipe_in <= '1';
bram_R2_address_pipe_in <= std_logic_vector(to_unsigned(address_offset, p_num_bits));
store_cmd_pipe_in <= cmd_store_remainder;
when loop_one_d =>
if i < reg_length - 1 then
state_decode <= loop_if_prep;
else
if i = reg_length - 1 then
state_decode <= loop_finalize;
else
state_decode <= next_recursion;
end if;
end if;
bram_br_write_a <= '0';
when loop_finalize =>
state_decode <= next_recursion;
when loop_if_prep =>
state_decode <= loop_if_case;
if i = reg_length - 2 then
i_2_before_end := 1;
else
i_2_before_end := 0;
end if;
reg_m <= to_unsigned(M_array_squared_256_16384(depth_counter * 2 + rounded_index_offset + i_2_before_end), 32);
reg_m2 <= to_unsigned(M_array_squared(depth_counter * 2 + rounded_index_offset + i_2_before_end), 32);
when loop_if_case =>
if reg_m = 2 then
if input_valid = '1' then
state_decode <= loop_if_one_S0;
reg_S0 <= input;
end if;
elsif reg_m = 1 then
if input_valid = '1' then
state_decode <= loop_if_two;
reg_S0 <= input;
end if;
else
state_decode <= loop_if_three;
end if;
when loop_if_one_S0 =>
if input_valid = '1' then
state_decode <= loop_if_one_S1;
reg_S1 <= input;
end if;
when loop_if_one_S1 =>
state_decode <= loop_one_d;
i <= i + 2;
bram_br_data_in_a <= std_logic_vector(unsigned(reg_S0) + shift_left(resize(unsigned(reg_S1), 16), 8));
bram_br_address_a <= std_logic_vector(to_unsigned(address_offset_next + i / 2, p_num_bits));
bram_br_write_a <= '1';
when loop_if_two =>
state_decode <= next_loop;
bram_br_data_in_a <= std_logic_vector(resize(unsigned(reg_S0), 16));
bram_br_address_a <= std_logic_vector(to_unsigned(address_offset_next + i / 2, p_num_bits));
bram_br_write_a <= '1';
when loop_if_three =>
state_decode <= next_loop;
bram_br_data_in_a <= (others => '0');
bram_br_address_a <= std_logic_vector(to_unsigned(address_offset_next + i / 2, p_num_bits));
bram_br_write_a <= '1';
when next_loop =>
state_decode <= loop_one_d;
i <= i + 2;
bram_br_write_a <= '0';
when loop_two_prep =>
if depth_counter = 1 then
state_decode <= output_loop;
else
state_decode <= loop_two_case;
end if;
depth_counter <= depth_counter - 1;
bram_R2_write_a <= '0';
if depth_counter /= 1 then
address_offset <= address_offset - stack_output;
else
address_offset <= 0;
end if;
address_offset_next <= address_offset;
reg_length <= stack_output;
pop_stack <= '1';
i <= 0;
bram_R2_write_a <= '0';
decode_command_pipe_in <= '0';
when loop_two_case =>
if i < reg_length - 1 then
state_decode <= loop_two_wait;
else
state_decode <= loop_two_d_end;
end if;
bram_br_address_a <= std_logic_vector(to_unsigned(address_offset_next + i / 2, p_num_bits));
bram_R2_address_a <= std_logic_vector(to_unsigned(address_offset_next + i / 2, p_num_bits));
pop_stack <= '0';
bram_R2_write_a <= '0';
--bram_R2_write_b <= '0';
decode_command_pipe_in <= '0';
when loop_two_wait =>
state_decode <= loop_two_fma;
when loop_two_fma =>
state_decode <= loop_two_divmod;
if i = reg_length - 2 then
i_2_before_end := 1;
else
i_2_before_end := 0;
end if;
if to_unsigned(bottomt_array(depth_counter * 2 + rounded_index_offset + i_2_before_end), 2) = 0 then
reg_r <= resize(unsigned(bram_br_data_out_a) + unsigned(bram_R2_data_out_a), 32);
elsif to_unsigned(bottomt_array(depth_counter * 2 + rounded_index_offset + i_2_before_end), 2) = 1 then
reg_r <= unsigned(bram_br_data_out_a) + shift_left(resize(unsigned(bram_R2_data_out_a), 32), 8);
else
reg_r <= unsigned(bram_br_data_out_a) + shift_left(resize(unsigned(bram_R2_data_out_a), 32), 16);
end if;
reg_Mi0 <= to_unsigned(M_array(depth_counter + rounded_index_offset), 16);
when loop_two_divmod =>
state_decode <= loop_two_store;
dividend <= std_logic_vector(reg_r);
divisor_index <= std_logic_vector(to_unsigned(depth_counter + rounded_index_offset, 7));
if i = reg_length - 2 then
divisor_index_mod <= std_logic_vector(to_unsigned(depth_counter + 11 + rounded_index_offset, 7));
else
divisor_index_mod <= std_logic_vector(to_unsigned(depth_counter + rounded_index_offset, 7));
end if;
decode_command_pipe_in <= '1';
bram_R2_address_pipe_in <= std_logic_vector(to_unsigned(address_offset + i, p_num_bits));
store_cmd_pipe_in <= cmd_store_both;
when loop_two_store =>
state_decode <= loop_two_case;
decode_command_pipe_in <= '0';
i <= i + 2;
when loop_two_d_end =>
if i = reg_length - 1 then
state_decode <= loop_two_d_end_write;
else
state_decode <= loop_two_flush;
end if;
pipe_flush_counter <= 0;
when loop_two_d_end_write =>
state_decode <= loop_two_flush;
bram_R2_data_in_a <= bram_R2_data_out_a;
bram_R2_address_a <= std_logic_vector(to_unsigned(address_offset + i, p_num_bits));
bram_R2_write_a <= '1';
when loop_two_flush =>
if pipe_flush_counter = 16 then --TODO this might work with 15
state_decode <= loop_two_prep;
end if;
pipe_flush_counter <= pipe_flush_counter + 1;
bram_R2_write_a <= '0';
decode_command_pipe_in <= '0';
when output_loop =>
if i < reg_length - 1 then
state_decode <= output_loop_wait;
else
state_decode <= output_loop_end;
end if;
pop_stack <= '0';
decode_command_pipe_in <= '0';
bram_br_address_a <= std_logic_vector(to_unsigned(i / 2, p_num_bits));
bram_R2_address_a <= std_logic_vector(to_unsigned(i / 2, p_num_bits));
when output_loop_wait =>
state_decode <= output_loop_fma;
when output_loop_fma =>
state_decode <= output_loop_divmod;
if i = reg_length - 2 then
i_2_before_end := 1;
else
i_2_before_end := 0;
end if;
if to_unsigned(bottomt_array(depth_counter * 2 + rounded_index_offset + i_2_before_end), 2) = 0 then
reg_r <= resize(unsigned(bram_br_data_out_a) + unsigned(bram_R2_data_out_a), 32);
elsif to_unsigned(bottomt_array(depth_counter * 2 + rounded_index_offset + i_2_before_end), 2) = 1 then
reg_r <= unsigned(bram_br_data_out_a) + shift_left(resize(unsigned(bram_R2_data_out_a), 32), 8);
else
reg_r <= unsigned(bram_br_data_out_a) + shift_left(resize(unsigned(bram_R2_data_out_a), 32), 16);
end if;
when output_loop_divmod =>
state_decode <= output_loop;
dividend <= std_logic_vector(reg_r);
divisor_index <= std_logic_vector(to_unsigned(0 + rounded_index_offset, 7));
divisor_index_mod <= std_logic_vector(to_unsigned(0 + rounded_index_offset, 7));
store_cmd_pipe_in <= cmd_output_both;
decode_command_pipe_in <= '1';
i <= i + 2;
when output_loop_end =>
state_decode <= output_loop_end_2;
when output_loop_end_2 =>
state_decode <= output_end_write;
when output_end_write =>
state_decode <= output_flush_pipe;
if i = reg_length - 1 then
dividend <= std_logic_vector(resize(unsigned(bram_R2_data_out_a), 32));
divisor_index <= std_logic_vector(to_unsigned(0 + rounded_index_offset, 7));
divisor_index_mod <= std_logic_vector(to_unsigned(0 + rounded_index_offset, 7));
store_cmd_pipe_in <= cmd_output_r0_only;
decode_command_pipe_in <= '1';
end if;
pipe_flush_counter <= 0;
when output_flush_pipe =>
if pipe_flush_counter = 16 then --TODO this might work with 15
state_decode <= decode_done;
end if;
decode_command_pipe_in <= '0';
pipe_flush_counter <= pipe_flush_counter + 1;
when decode_done =>
state_decode <= idle;
done <= '1';
end case;
end if;
end process fsm_process;
output_reg : process(clock, reset) is
begin
if reset = '1' then
output_valid <= '0';
output_reg_r1 <= '0';
elsif rising_edge(clock) then
output_valid <= '0';
if output_reg_r0 = '1' then
output <= std_logic_vector(reg_r0(q_num_bits - 1 downto 0));
if output_reg_r0_only = '0' then
output_reg_r1 <= '1';
end if;
output_valid <= '1';
end if;
if output_reg_r1 = '1' then
output <= std_logic_vector(reg_r1(q_num_bits - 1 downto 0));
output_reg_r1 <= '0';
output_valid <= '1';
end if;
end if;
end process output_reg;
input_ack <= '0' when state_decode = idle
else '1' when state_decode = loop_input and i < reg_length - 1 and input_valid = '1'
else '1' when state_decode = loop_input_one and input_valid = '1' and rounded_decode = '0'
else '1' when state_decode = recursion_end and input_valid = '1' and M_array(depth_counter + rounded_index_offset) /= 1
else '1' when state_decode = recursion_end_2 and input_valid = '1' and reg_Mi0 > to_unsigned(256, 16)
else '1' when state_decode = loop_if_case and input_valid = '1' and reg_m >= 1
else '1' when state_decode = loop_if_one_S0 and input_valid = '1'
else '0';
rounded_index_offset <= 0 when rounded_decode = '0' else 21;
stack_memory_inst : entity work.stack_memory
generic map(
DEPTH => max_depth
)
port map(
clock => clock,
reset => reset,
push_stack => push_stack,
pop_stack => pop_stack,
stack_input => stack_input,
stack_output => stack_output
);
div_mod_pipeline_inst : entity work.div_mod_pipeline(RTL)
port map(
clock => clock,
reset => reset,
dividend => dividend,
divisor_index => divisor_index,
divisor_index_mod => divisor_index_mod,
decode_command_pipe_in => decode_command_pipe_in,
bram_R2_address_pipe_in => bram_R2_address_pipe_in,
store_cmd_pipe_in => store_cmd_pipe_in,
decode_command_pipe_out => decode_command_pipe_out,
bram_R2_address_pipe_out => bram_R2_address_pipe_out,
store_cmd_pipe_out => store_cmd_pipe_out,
remainder_mod => remainder_mod,
remainder_pipe_delay_out => remainder_pipe_delay_out
);
decode_command <= decode_command_pipe_out;
store_div_result : process(clock, reset) is
begin
if reset = '1' then
reg_store_both <= '0';
bram_R2_write_b <= '0';
output_reg_r0 <= '0';
output_reg_r0_only <= '0';
elsif rising_edge(clock) then
output_reg_r0 <= '0';
output_reg_r0_only <= '0';
bram_R2_write_b <= '0';
if decode_command = '1' and reg_store_both = '0' then
if store_cmd_pipe_out = cmd_output_both then
reg_r0 <= unsigned(remainder_pipe_delay_out);
reg_r1 <= unsigned(remainder_mod);
output_reg_r0 <= '1';
elsif store_cmd_pipe_out = cmd_output_r0_only then
reg_r0 <= unsigned(remainder_pipe_delay_out);
output_reg_r0 <= '1';
output_reg_r0_only <= '1';
else
bram_R2_address_b <= bram_R2_address_pipe_out;
bram_R2_data_in_b <= remainder_pipe_delay_out;
bram_R2_write_b <= '1';
if store_cmd_pipe_out = cmd_store_both then
reg_store_address <= bram_R2_address_pipe_out;
reg_store_both <= '1';
reg_remainder_mod <= remainder_mod;
end if;
end if;
elsif reg_store_both = '1' then
bram_R2_address_b <= std_logic_vector(unsigned(reg_store_address) + 1);
bram_R2_data_in_b <= reg_remainder_mod;
bram_R2_write_b <= '1';
reg_store_both <= '0';
end if;
end if;
end process store_div_result;
block_ram_R2 : entity work.block_ram
generic map(
ADDRESS_WIDTH => p_num_bits,
DATA_WIDTH => 16
)
port map(
clock => clock,
address_a => bram_R2_address_a,
write_a => bram_R2_write_a,
data_in_a => bram_R2_data_in_a,
data_out_a => bram_R2_data_out_a,
address_b => bram_R2_address_b,
write_b => bram_R2_write_b,
data_in_b => bram_R2_data_in_b,
data_out_b => open
);
block_ram_bottomr : entity work.block_ram
generic map(
ADDRESS_WIDTH => p_num_bits,
DATA_WIDTH => 16
)
port map(
clock => clock,
address_a => bram_br_address_a,
write_a => bram_br_write_a,
data_in_a => bram_br_data_in_a,
data_out_a => bram_br_data_out_a,
address_b => bram_br_address_b,
write_b => bram_br_write_b,
data_in_b => bram_br_data_in_b,
data_out_b => open
);
bram_br_address_b <= (others => '0');
bram_br_data_in_b <= (others => '0');
end architecture RTL;
|
<gh_stars>1-10
----------------------------------------------------------------------------
-- btn_debounce.vhd -- Button Debouncer
----------------------------------------------------------------------------
-- Author: <NAME>
-- Copyright 2011 Digilent, Inc.
-- Modified: Added toggle output
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component is used to debounce signals generated by external push
-- buttons. It is designed to independently debounce a Push button signal.
-- Debouncing is done by only registering a change in a button state if
-- it remains constant for the specified number of clock cycles.
--
-- Port Descriptions:
--
-- clk - The input clock
-- input - The input button signal
-- output - The debounced button output signal
-- toggle - The debounced toggle output signal
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011 (SamB): Created using Xilinx Tools 13.2
-- 10/06/2013 (CU): Converted to one button and added toggle output
-- 05/19/2019 (Mike): Refactored/optimized from https://github.com/rauenzi/VHDL-Communications/blob/522ccea95e7f1ec41ed0b26fa6a8897a4768de74/btn_debounce_toggle.vhd
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- TODO: reset logic
entity btn_debounce is
GENERIC (
CONSTANT delay : integer := 65535); -- the number of clock cycles to wait before asserting stable input (also the required delay between presses in order for it to register as a new press)
Port ( clk : in STD_LOGIC; -- the input clock
input : in STD_LOGIC; -- the input button signal
output : out STD_LOGIC; -- the debounced button output signal
toggle : inout STD_LOGIC := '0'); -- the debounced toggle output signal
end btn_debounce;
architecture Behavioral of btn_debounce is
signal counter : integer range 0 to delay := 0;
signal debounced : std_logic := '0';
signal sync : std_logic_vector(1 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
-- counter for how many clocks the button state has remained unchanged after a change in input
if (counter = delay or (not ((debounced = '1') xor (input = '1')))) then
counter <= 0;
else
counter <= counter + 1;
end if;
-- debounce
if (counter = delay) then
debounced <= not(debounced);
end if;
-- toggle
sync(0) <= debounced;
sync(1) <= sync(0);
if (not sync(1) and sync(0)) = '1' then
toggle <= not toggle;
end if;
end process;
output <= debounced;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
entity top is
port(
clk : in std_logic;
reset : in std_logic;
KEY0 : in std_logic;
KEY1 : in std_logic;
KEY2 : in std_logic;
KEY3 : in std_logic;
SW0 : in std_logic;
SW1 : in std_logic;
notes_OUT : out std_logic_vector(4 downto 0)
);
end top;
|
<reponame>paulino/minsdhcspi-host
--------------------------------------------------------------------------------
-- This file is part of the 'Minimalistic SDHC Host Reader'
-- Copyright (C) 2016 <NAME> <<EMAIL>>
-- Licensed under the Apache License 2.0, you may obtain a copy of
-- the License at https://www.apache.org/licenses/LICENSE-2.0
--
-- You can get more info at https://github.com/paulino/minsdhcspi-host
--------------------------------------------------------------------------------
-- Date: 28-07-2017
-- Version: 1.1
--*--------------------------------- End auto header, don't touch this line -*--
library ieee;
use ieee.std_logic_1164.all;
package sdspihost_pk is
-- Commands for entity sdspihost
constant SDHOST_INIT : std_logic_vector (3 downto 0) := X"0"; -- Init SD
constant SDHOST_READFIRST : std_logic_vector (3 downto 0) := X"1"; -- Read first byte, data_in <= blockno
constant SDHOST_READNEXT : std_logic_vector (3 downto 0) := X"2"; -- Read next byte
-- Address of SD CMD commands in ROM
constant CMD0_ROMADDR : std_logic_vector(7 downto 0) := X"00";
constant CMD8_ROMADDR : std_logic_vector(7 downto 0) := X"06";
constant CMD55_ROMADDR : std_logic_vector(7 downto 0) := X"0C";
constant ACMD41_ROMADDR : std_logic_vector(7 downto 0) := X"12";
constant CMD12_ROMADDR : std_logic_vector(7 downto 0) := X"18";
-- Components
component sdspihost
port(
clk : in std_logic;
reset : in std_logic;
busy : out std_logic;
err : out std_logic;
r_block : in std_logic;
r_byte : in std_logic;
block_addr : in std_logic_vector(31 downto 0); -- 512 sd block address
data_out : out std_logic_vector (7 downto 0);
miso : in std_logic; -- sd card pin
mosi : out std_logic; -- sd card pin
sclk : out std_logic; -- sd card pin
ss : out std_logic -- sd card pin
);
end component;
component generic_counter
generic ( width : integer );
port(
clk : in std_logic;
reset : in std_logic;
up : in std_logic;
dout : out std_logic_vector(width-1 downto 0)
);
end component;
component generic_paracont
generic ( width : integer );
port(
clk : in std_logic;
reset : in std_logic;
up : in std_logic;
load : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0)
);
end component;
component generic_ioreg is
generic ( width : integer );
port(
clk : in std_logic;
w : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0)
);
end component;
component spi
Port (
clk : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
w_data : in std_logic; -- 0: read / 1: write
w_conf : in std_logic; -- 1: write_config, 0: write data
ss_in : in std_logic; -- SPI SS
busy : out std_logic; -- Data ready when not busy
miso : in std_logic; -- SPI external connections
mosi : out std_logic;
sclk : out std_logic;
ss : out std_logic);
end component;
component sdcmd_rom
port(
addr : IN std_logic_vector(4 downto 0);
data_out : OUT std_logic_vector(7 downto 0)
);
end component;
end sdspihost_pk;
package body sdspihost_pk is
end sdspihost_pk;
|
<gh_stars>1-10
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library knnCluster;
use knnCluster.knnCluster_Pkg.all;
entity singlePortMemory is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(TEST_DEPTH - 1 downto 0);
dina : in std_logic_vector(DATA_WIDTH - 1 downto 0);
douta : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end singlePortMemory;
architecture Behavioral of singlePortMemory is
-- declare type of memory
type mem_type is array (0 to (2 ** TEST_DEPTH) - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
-- initialize memory with zeros (only for simulation purposes)
shared variable ram : mem_type := (others => (others => '0'));
begin
-- port a
process (clka)
begin
-- all events have to be synchronous and ram protocol is write first
if clka'event and clka = '1' then
-- if write is enabled
if wea(0) = '1' then
-- write input to selected address
ram(conv_integer(addra)) := dina;
end if;
-- otherwise just read
douta <= ram(conv_integer(addra));
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: <NAME>
-- Create Date: 26.08.2019
-- Module Name: Player - Behavioral
-- Project Name: Pacman
-- Target Devices: BASYS 3
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity player is
Port(
p_Clock : in std_logic;
p_Reset : in std_logic;
p_Move : in std_logic;
p_Direction : in std_logic_vector(3 downto 0);
p_HPos : in integer range 0 to 65535;
p_VPos : in integer range 0 to 65535;
o_Draw : out std_logic
);
end player;
architecture Behavioral of player is
COMPONENT player_rom
Port(
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
);
END COMPONENT;
constant c_BITMAP_WIDTH : integer := 40;
signal s_BitmapAddr : std_logic_vector(5 downto 0);
signal s_BitmapRow : std_logic_vector(39 downto 0);
signal s_Draw : std_logic;
signal s_HOffset : integer range 0 to 65535;
signal s_VOffset : integer range 0 to 65535;
signal s_PlayerH : integer;
signal s_PlayerV : integer;
begin
c_BITMAP : player_rom
Port MAP(
clka => p_Clock,
addra => s_BitmapAddr,
douta => s_BitmapRow
);
process(p_Clock, p_Reset)
begin
if (p_Reset = '1') then
s_PlayerH <= 281;
s_PlayerV <= 91;
elsif (rising_edge(p_Clock)) then
if p_Direction(0) = '1' and p_Move = '1' then
if (s_PlayerV < 80 and s_PlayerV > 40) then
if (s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 140 and s_PlayerV > 80) then
if (s_PlayerH - 1 > 120 and s_PlayerH < 160) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH - 1 > 280 and s_PlayerH < 320) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH - 1 > 440 and s_PlayerH < 480) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 180) then
if (s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 220 and s_PlayerV > 180) then
if ((s_PlayerH < 160 and s_PlayerH - 1 > 120) or (s_PlayerH < 240 and s_PlayerH - 1 > 200) or (s_PlayerH < 400 and s_PlayerH - 1 > 360) or (s_PlayerH < 480 and s_PlayerH - 1 > 440)) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 260 and s_PlayerV > 220) then
if (s_PlayerH < 160 and s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 280 and s_PlayerH - 1 > 200) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 400 and s_PlayerH - 1 > 320) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 480 and s_PlayerH - 1 > 440) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 300) then
if (s_PlayerH < 160 and s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 240 and s_PlayerH - 1 > 200) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 400 and s_PlayerH - 1 > 360) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 480 and s_PlayerH - 1 > 440) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 340) then
if (s_PlayerH < 240 and s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 480 and s_PlayerH - 1 > 360) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 380) then
if (s_PlayerH < 160 and s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 400 and s_PlayerH - 1 > 200) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 480 and s_PlayerH - 1 > 440) then
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 390) then
if (s_PlayerH < 160 and s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 240 and s_PlayerH - 1 > 200) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 400 and s_PlayerH - 1 > 320) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 480 and s_PlayerH - 1 > 440) then
s_PlayerH <= s_PlayerH - 1;
else
s_PlayerH <= s_PlayerH - 1;
end if;
elsif (s_PlayerV < 430) then
if (s_PlayerH < 240 and s_PlayerH - 1 > 120) then
s_PlayerH <= s_PlayerH - 1;
elsif (s_PlayerH < 480 and s_PlayerH - 1 > 360) then
s_PlayerH <= s_PlayerH - 1;
end if;
else
s_PlayerH <= s_PlayerH - 1;
end if;
elsif p_Direction(1) = '1' and p_Move = '1' then
if (s_PlayerV < 80 and s_PlayerV > 40) then
if (s_PlayerH + 31 < 480) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 140 and s_PlayerV > 80) then
if (s_PlayerH + 31 < 160 and s_PlayerH > 120) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 320 and s_PlayerH > 280) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 480 and s_PlayerH > 440) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 180 and s_PlayerV > 140) then
if (s_PlayerH + 31 < 480) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 220 and s_PlayerV > 180) then
if ((s_PlayerH + 31 < 160 and s_PlayerH > 120) or (s_PlayerH + 31 < 240 and s_PlayerH > 200) or (s_PlayerH + 31 < 400 and s_PlayerH > 360) or (s_PlayerH + 31 < 480 and s_PlayerH > 440)) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 260 and s_PlayerV > 220) then
if (s_PlayerH + 31 < 160 and s_PlayerH > 120) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 280 and s_PlayerH > 200) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 400 and s_PlayerH > 320) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 480 and s_PlayerH > 440) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 300) then
if (s_PlayerH + 31 < 160 and s_PlayerH > 120) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 240 and s_PlayerH > 200) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 400 and s_PlayerH > 360) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 480 and s_PlayerH > 440) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 340) then
if (s_PlayerH + 31 < 240 and s_PlayerH > 120) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 480 and s_PlayerH > 360) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 380) then
if (s_PlayerH + 31 < 160 and s_PlayerH > 120) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 400 and s_PlayerH > 200) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 480 and s_PlayerH > 440) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 390) then
if (s_PlayerH + 31 < 160 and s_PlayerH > 120) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 240 and s_PlayerH > 200) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 400 and s_PlayerH > 320) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 480 and s_PlayerH > 440) then
s_PlayerH <= s_PlayerH + 1;
end if;
elsif (s_PlayerV < 430) then
if (s_PlayerH + 31 < 240 and s_PlayerH > 120) then
s_PlayerH <= s_PlayerH + 1;
elsif (s_PlayerH + 31 < 480 and s_PlayerH > 360) then
s_PlayerH <= s_PlayerH + 1;
end if;
else
s_PlayerH <= s_PlayerH + 1;
end if;
elsif p_Direction(2) = '1' and p_Move = '1' then
if (s_PlayerH < 240 and s_PlayerV > 200) or (s_PlayerV < 400 and s_PlayerV > 360) then
if (s_PlayerV + 31 < 440) then
s_PlayerV <= s_PlayerV + 1;
end if;
elsif (s_PlayerH < 160 and s_PlayerH > 120) then
if (s_PlayerV + 31 < 440) then
s_PlayerV <= s_PlayerV + 1;
end if;
elsif (s_PlayerH < 200 and s_PlayerH > 160) then
if (s_PlayerV + 31 < 80) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 180 and s_PlayerV > 140) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 340 and s_PlayerV > 300) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 440 and s_PlayerV > 400) then
s_PlayerV <= s_PlayerV + 1;
end if;
elsif (s_PlayerH < 280 and s_PlayerH > 240) then
if (s_PlayerV + 31 < 80) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 180 and s_PlayerV > 140) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 260 and s_PlayerV > 220) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 380 and s_PlayerV > 340) then
s_PlayerV <= s_PlayerV + 1;
end if;
elsif (s_PlayerH < 320 and s_PlayerH > 280) then -- Middle
if (s_PlayerV + 31 < 180) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 380 and s_PlayerV > 340) then
s_PlayerV <= s_PlayerV + 1;
end if;
elsif (s_PlayerH < 360 and s_PlayerH > 320) then
if (s_PlayerV + 31 < 80) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 180 and s_PlayerV > 140) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 260 and s_PlayerV > 220) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 380 and s_PlayerV > 340) then
s_PlayerV <= s_PlayerV + 1;
end if;
elsif (s_PlayerH < 440 and s_PlayerH > 400) then
if (s_PlayerV + 31 < 80) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 180 and s_PlayerV > 140) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 340 and s_PlayerV > 300) then
s_PlayerV <= s_PlayerV + 1;
elsif (s_PlayerV + 31 < 440 and s_PlayerV > 400) then
s_PlayerV <= s_PlayerV + 1;
end if;
elsif (s_PlayerH < 480 and s_PlayerH > 400) then
if (s_PlayerV + 31 < 440) then
s_PlayerV <= s_PlayerV + 1;
end if;
else
s_PlayerV <= s_PlayerV + 1;
end if;
elsif p_Direction(3) = '1' and p_Move = '1' then
if (s_PlayerH < 240 and s_PlayerV > 200) or (s_PlayerV < 400 and s_PlayerV > 360) then
if (s_PlayerV - 1 > 40) then
s_PlayerV <= s_PlayerV - 1;
end if;
elsif (s_PlayerH < 160 and s_PlayerH > 120) then
if (s_PlayerV - 1 > 40) then
s_PlayerV <= s_PlayerV - 1;
end if;
elsif (s_PlayerH < 200 and s_PlayerH > 160) then
if (s_PlayerV - 1 > 40) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 140 and s_PlayerV < 180) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 300 and s_PlayerV < 340) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 400 and s_PlayerV < 440) then
s_PlayerV <= s_PlayerV - 1;
end if;
elsif (s_PlayerH < 280 and s_PlayerH > 240) then
if (s_PlayerV - 1 < 40) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 140 and s_PlayerV < 180) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 260 and s_PlayerV < 220) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 380 and s_PlayerV < 340) then
s_PlayerV <= s_PlayerV - 1;
end if;
elsif (s_PlayerH < 320 and s_PlayerH > 280) then -- Middle
if (s_PlayerV - 1 > 40) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 340 and s_PlayerV > 380) then
s_PlayerV <= s_PlayerV - 1;
end if;
elsif (s_PlayerH < 360 and s_PlayerH > 320) then
if (s_PlayerV - 1 > 40) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 140 and s_PlayerV < 180) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 220 and s_PlayerV < 260) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 340 and s_PlayerV < 380) then
s_PlayerV <= s_PlayerV - 1;
end if;
elsif (s_PlayerH < 440 and s_PlayerH > 400) then
if (s_PlayerV - 1 > 40) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 180 and s_PlayerV < 140) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 340 and s_PlayerV < 300) then
s_PlayerV <= s_PlayerV - 1;
elsif (s_PlayerV - 1 > 440 and s_PlayerV < 400) then
s_PlayerV <= s_PlayerV - 1;
end if;
elsif (s_PlayerH < 480 and s_PlayerH > 400) then
if (s_PlayerV - 1 > 40) then
s_PlayerV <= s_PlayerV - 1;
end if;
else
s_PlayerV <= s_PlayerV - 1;
end if;
end if;
end if;
end process;
draw : process(p_Clock, p_Reset)
begin
if (p_Reset = '1') then
s_Draw <= '0';
s_BitmapAddr <= (others => '0');
s_HOffset <= 0;
s_VOffset <= 0;
elsif (rising_edge(p_Clock)) then
s_HOffset <= p_HPos - s_PlayerH;
s_VOffset <= p_VPos - s_PlayerV;
if (s_HOffset >= 0 and s_HOffset < c_BITMAP_WIDTH and s_VOffset >= 0 and s_VOffset < c_BITMAP_WIDTH) then
s_BitmapAddr <= std_logic_vector(to_unsigned(s_VOffset, s_BitmapAddr'length));
s_Draw <= s_BitmapRow(s_HOffset);
else
s_Draw <= '0';
end if;
end if;
end process;
o_Draw <= s_Draw;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: FSM that patches the silicon's issue of increments > 8
-- https://forums.xilinx.com/t5/Versal-and-UltraScale/IDELAY-ODELAY-Usage/td-p/812362
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library surf;
use surf.StdRtlPkg.all;
library unisim;
use unisim.vcomponents.all;
entity Delaye3PatchFsm is
generic (
TPD_G : time := 1 ns;
DELAY_TYPE : string := "FIXED"; -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
DELAY_VALUE : integer := 0; -- Input delay value setting
IS_CLK_INVERTED : bit := '0'; -- Optional inversion for CLK
IS_RST_INVERTED : bit := '0'); -- Optional inversion for RST
port (
-- Inputs
CLK : in sl; -- 1-bit input: Clock input
RST : in sl; -- 1-bit input: Asynchronous Reset to the DELAY_VALUE
LOAD : in sl; -- 1-bit input: Load DELAY_VALUE input
CNTVALUEIN : in slv(8 downto 0); -- 9-bit input: Counter value input
CNTVALUEOUT : in slv(8 downto 0); -- 9-bit output: Counter value output
-- outputs
patchLoad : out sl;
patchCntValue : out slv(8 downto 0);
busy : out sl); -- 1-bit output: Patch module is busy
end Delaye3PatchFsm;
architecture rtl of Delaye3PatchFsm is
type StateType is (
IDLE_S,
LOAD_S,
WAIT_S);
type RegType is record
Load : sl;
dlyValue : slv(8 downto 0);
dlyTarget : slv(8 downto 0);
waitCnt : slv(2 downto 0);
state : StateType;
end record RegType;
constant REG_INIT_C : RegType := (
Load => '0',
dlyValue => toSlv(DELAY_VALUE, 9),
dlyTarget => toSlv(DELAY_VALUE, 9),
waitCnt => (others => '0'),
state => IDLE_S);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
begin
GEN_PATCH : if (DELAY_TYPE = "VAR_LOAD") generate
comb : process (CNTVALUEIN, CNTVALUEOUT, LOAD, r) is
variable v : RegType;
begin
-- Latch the current value
v := r;
-- Reset strobes
v.Load := '0';
-- Check for load request
if (LOAD = '1') then
-- Update the target delay value
v.dlyTarget := CNTVALUEIN;
end if;
-- Main state machine
case r.state is
----------------------------------------------------------------------
when IDLE_S =>
-- Check if load target different from current output
if (v.dlyTarget /= CNTVALUEOUT) then
-- Check if we should increment the value
if (v.dlyTarget > CNTVALUEOUT) then
v.dlyValue := CNTVALUEOUT + 1;
-- Else decrement the value
else
v.dlyValue := CNTVALUEOUT - 1;
end if;
-- Next state
v.state := LOAD_S;
end if;
----------------------------------------------------------------------
when LOAD_S =>
-- "Wait at least one clock cycle after applying a new value on the
-- CNTVALUEIN bus before applying the LOAD signal." UG571 (v1.12, page172)
v.Load := '1';
-- Next state
v.state := WAIT_S;
----------------------------------------------------------------------
when WAIT_S =>
-- Increment the counter
v.waitCnt := r.waitCnt + 1;
-- "Option for multiple updates: Wait 5 clock cycles." UG571 (v1.12, page181)
if (r.waitCnt = 4) then
-- Reset the counter
v.waitCnt := (others => '0');
-- Next state
v.state := IDLE_S;
end if;
----------------------------------------------------------------------
end case;
-- Outputs
patchLoad <= r.Load;
patchCntValue <= r.dlyValue;
if (v.dlyTarget /= CNTVALUEOUT) or (r.state /= IDLE_S) then
busy <= '1';
else
busy <= '0';
end if;
-- Register the variable for next clock cycle
rin <= v;
end process comb;
seq : process (CLK, RST) is
begin
-- Check for non-inverted clock
if (IS_CLK_INVERTED = '0') then
if (rising_edge(CLK)) then
r <= rin after TPD_G;
end if;
-- Else inverted clock
else
if (falling_edge(CLK)) then
r <= rin after TPD_G;
end if;
end if;
-- Asynchronous Reset to the DELAY_VALUE
if ((RST = '1') and (IS_RST_INVERTED = '0')) or ((RST = '0') and (IS_RST_INVERTED = '1')) then
r <= REG_INIT_C after TPD_G;
end if;
end process seq;
end generate;
BYP_PATCH : if (DELAY_TYPE /= "VAR_LOAD") generate
patchLoad <= LOAD;
patchCntValue <= CNTVALUEIN;
busy <= '0';
end generate;
end rtl;
|
<gh_stars>0
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity testbench is
end testbench;
architecture tb of testbench is
component alu is
port(
a, b : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(2 downto 0);
res : out std_logic_vector(3 downto 0)
);
end component;
signal a_i, b_i, res_o : std_logic_vector(3 downto 0);
signal sel_line : std_logic_vector(2 downto 0);
begin
DUT: alu port map(a_i, b_i, sel_line, res_o);
process
begin
a_i <= "0111";
b_i <= "0001";
sel_line <= "000";
wait for 10ps;
assert(res_o="1000") report "Fail 0/0" severity error;
sel_line <= "001";
wait for 10ps;
assert(res_o="0110") report "Fail 0/0" severity error;
-- sel_line <= "010";
-- wait for 10ps;
-- assert(res_o="1110") report "Fail 0/0" severity error;
sel_line <= "011";
wait for 10ps;
assert(res_o="0001") report "Fail 0/0" severity error;
sel_line <= "100";
wait for 10ps;
assert(res_o="0111") report "Fail 0/0" severity error;
sel_line <= "101";
wait for 10ps;
assert(res_o="1000") report "Fail 0/0" severity error;
sel_line <= "110";
wait for 10ps;
assert(res_o="1110") report "Fail 0/0" severity error;
sel_line <= "111";
wait for 10ps;
assert(res_o="1000") report "Fail 0/0" severity error;
a_i <= "0000";
b_i <= "0000";
sel_line <= "000";
assert false report "Test done." severity note;
wait;
end process;
end tb;
|
<filename>lvin_Verification_Axi4LiteVIP_v1_0/tb/Axi4LiteVIP_tb.vhd
--------------------------------------------------------------------------------
-- Project Name : IpLibrary
-- Design Name : Axi4LitePassThroughAdaptor
-- File Name : Axi4LitePassThroughAdaptor.vhd
--------------------------------------------------------------------------------
-- Author : <NAME>
-- Description:
--
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- LIBRARIES
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library lvin_Verification_Axi4LiteIntf_v1_0;
use lvin_Verification_Axi4LiteIntf_v1_0.Axi4LiteIntf_pkg.all;
library lvin_Verification_Axi4LiteTransactor_v1_0;
use lvin_Verification_Axi4LiteTransactor_v1_0.Axi4LiteTransactor_pkg.all;
library lvin_Axi4Lite_Regbank_v1_0;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Axi4LiteVIP_tb is
end entity Axi4LiteVIP_tb;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture rtl of Axi4LiteVIP_tb is
constant AddrWidth : natural := 32;
signal AClk : std_logic;
signal AResetn : std_logic;
signal Master_ARValid, Slave_ARValid : std_logic;
signal Master_ARReady, Slave_ARReady : std_logic;
signal Master_ARAddr , Slave_ARAddr : std_logic_vector(AddrWidth-1 downto 0);
signal Master_ARProt , Slave_ARProt : std_logic_vector(2 downto 0);
signal Master_RValid , Slave_RValid : std_logic;
signal Master_RReady , Slave_RReady : std_logic;
signal Master_RData , Slave_RData : std_logic_vector(31 downto 0);
signal Master_RResp , Slave_RResp : std_logic_vector(1 downto 0);
signal Master_AWValid, Slave_AWValid : std_logic;
signal Master_AWReady, Slave_AWReady : std_logic;
signal Master_AWAddr , Slave_AWAddr : std_logic_vector(AddrWidth-1 downto 0);
signal Master_AWProt , Slave_AWProt : std_logic_vector(2 downto 0);
signal Master_WValid , Slave_WValid : std_logic;
signal Master_WReady , Slave_WReady : std_logic;
signal Master_WData , Slave_WData : std_logic_vector(31 downto 0);
signal Master_WStrb , Slave_WStrb : std_logic_vector(3 downto 0);
signal Master_BValid , Slave_BValid : std_logic;
signal Master_BReady , Slave_BReady : std_logic;
signal Master_BResp , Slave_BResp : std_logic_vector(1 downto 0);
constant c_PeriodAClk : time := 5 ns;
signal ClockEnable : boolean := False;
alias Ctrl0 : t_Axi4LiteIntf is lvin_Verification_Axi4LiteIntf_v1_0.Axi4LiteIntf_pkg.Axi4LiteIntfArray(0);
alias Ctrl1 : t_Axi4LiteIntf is lvin_Verification_Axi4LiteIntf_v1_0.Axi4LiteIntf_pkg.Axi4LiteIntfArray(1);
begin
-----------------------------------------------------------------------------
-- CLOCK
-----------------------------------------------------------------------------
p_AClk : process
begin
AClk <= '0';
wait until ClockEnable = True;
while ClockEnable loop
AClk <= not AClk;
wait for c_PeriodAClk/2;
end loop;
wait;
end process;
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
Master : entity work.Axi4LiteVIP
Generic map(
IntfIndex => 0,
AddrWidth => AddrWidth,
Mode => "Master"
)
Port map(
-- Clock and Reset
AClk => AClk,
AResetn => AResetn,
-- Axi4Stream Master Interface
Master_ARValid => Slave_ARValid,
Master_ARReady => Slave_ARReady,
Master_ARAddr => Slave_ARAddr,
Master_ARProt => Slave_ARProt,
Master_RValid => Slave_RValid,
Master_RReady => Slave_RReady,
Master_RData => Slave_RData,
Master_RResp => Slave_RResp,
Master_AWValid => Slave_AWValid,
Master_AWReady => Slave_AWReady,
Master_AWAddr => Slave_AWAddr,
Master_AWProt => Slave_AWProt,
Master_WValid => Slave_WValid,
Master_WReady => Slave_WReady,
Master_WData => Slave_WData,
Master_WStrb => Slave_WStrb,
Master_BValid => Slave_BValid,
Master_BReady => Slave_BReady,
Master_BResp => Slave_BResp
);
Passthrough : entity work.Axi4LiteVIP
Generic map(
IntfIndex => 1,
AddrWidth => AddrWidth,
Mode => "Passthrough"
)
Port map(
-- Clock and Reset
AClk => AClk,
AResetn => AResetn,
-- Axi4Stream Slave Interface
Slave_ARValid => Slave_ARValid,
Slave_ARReady => Slave_ARReady,
Slave_ARAddr => Slave_ARAddr,
Slave_ARProt => Slave_ARProt,
Slave_RValid => Slave_RValid,
Slave_RReady => Slave_RReady,
Slave_RData => Slave_RData,
Slave_RResp => Slave_RResp,
Slave_AWValid => Slave_AWValid,
Slave_AWReady => Slave_AWReady,
Slave_AWAddr => Slave_AWAddr,
Slave_AWProt => Slave_AWProt,
Slave_WValid => Slave_WValid,
Slave_WReady => Slave_WReady,
Slave_WData => Slave_WData,
Slave_WStrb => Slave_WStrb,
Slave_BValid => Slave_BValid,
Slave_BReady => Slave_BReady,
Slave_BResp => Slave_BResp,
-- Axi4Stream Master Interface
Master_ARValid => Master_ARValid,
Master_ARReady => Master_ARReady,
Master_ARAddr => Master_ARAddr,
Master_ARProt => Master_ARProt,
Master_RValid => Master_RValid,
Master_RReady => Master_RReady,
Master_RData => Master_RData,
Master_RResp => Master_RResp,
Master_AWValid => Master_AWValid,
Master_AWReady => Master_AWReady,
Master_AWAddr => Master_AWAddr,
Master_AWProt => Master_AWProt,
Master_WValid => Master_WValid,
Master_WReady => Master_WReady,
Master_WData => Master_WData,
Master_WStrb => Master_WStrb,
Master_BValid => Master_BValid,
Master_BReady => Master_BReady,
Master_BResp => Master_BResp
);
i_Regbank : entity lvin_Axi4Lite_Regbank_v1_0.Regbank
Port map(
AClk => AClk ,
AResetn => AResetn ,
Ctrl_ARValid => Master_ARValid,
Ctrl_ARReady => Master_ARReady,
Ctrl_ARAddr => Master_ARAddr ,
Ctrl_RValid => Master_RValid ,
Ctrl_RReady => Master_RReady ,
Ctrl_RData => Master_RData ,
Ctrl_RResp => Master_RResp ,
Ctrl_AWValid => Master_AWValid,
Ctrl_AWReady => Master_AWReady,
Ctrl_AWAddr => Master_AWAddr ,
Ctrl_WValid => Master_WValid ,
Ctrl_WReady => Master_WReady ,
Ctrl_WData => Master_WData ,
Ctrl_WStrb => Master_WStrb ,
Ctrl_BValid => Master_BValid ,
Ctrl_BReady => Master_BReady ,
Ctrl_BResp => Master_BResp
);
-----------------------------------------------------------------------------
-- MAIN CTRL
-----------------------------------------------------------------------------
process
variable data : std_logic_vector(31 downto 0);
begin
AResetn <= '0';
InitAxi(Ctrl0);
InitAxi(Ctrl1);
wait for 20*c_PeriodAClk;
ClockEnable <= True;
Idle(Ctrl0, 20);
AResetn <= '1';
Idle(Ctrl0, 20);
--------------------------------------------------------------------------
ReadAxi(Ctrl0, x"00", data);
ReadAxi(Ctrl0, x"04", data);
ReadAxi(Ctrl0, x"08", data);
ReadAxi(Ctrl0, x"0C", data);
WriteAxi(Ctrl0, x"00", x"BEEF0000");
WriteAxi(Ctrl0, x"04", x"BEEF0001");
WriteAxi(Ctrl0, x"08", x"BEEF0002");
WriteAxi(Ctrl0, x"0C", x"BEEF0003");
ReadAxi(Ctrl1, x"10", data);
ReadAxi(Ctrl1, x"14", data);
ReadAxi(Ctrl1, x"18", data);
ReadAxi(Ctrl1, x"1C", data);
WriteAxi(Ctrl1, x"10", x"BEEF0000");
WriteAxi(Ctrl1, x"14", x"BEEF0001");
WriteAxi(Ctrl1, x"18", x"BEEF0002");
WriteAxi(Ctrl1, x"1C", x"BEEF0003");
WriteAxi(Ctrl0, x"00", x"BEEFDEAD");
WriteAxi(Ctrl1, x"10", x"deadbeef");
WriteAxi(Ctrl0, x"00", x"BEEFDEAD");
WriteAxi(Ctrl1, x"10", x"deadbeef");
ReadAxi(Ctrl0, x"00", data);
ReadAxi(Ctrl1, x"10", data);
ReadAxi(Ctrl0, x"00", data);
ReadAxi(Ctrl1, x"10", data);
WriteAxi(Ctrl0, x"00", x"BEEFDEAD");
ReadAxi(Ctrl0, x"00", data);
WriteAxi(Ctrl1, x"10", x"deadbeef");
ReadAxi(Ctrl1, x"10", data);
WriteAxi(Ctrl1, x"10", x"deadbeef");
ReadAxi(Ctrl0, x"00", data);
WriteAxi(Ctrl0, x"00", x"BEEFDEAD");
ReadAxi(Ctrl1, x"10", data);
--------------------------------------------------------------------------
Idle(Ctrl0, 20);
AResetn <= '0';
Idle(Ctrl0, 20);
ClockEnable <= False;
wait for 20*c_PeriodAClk;
report "Simulation Finished" severity failure;
end process;
end architecture rtl;
|
<filename>components/modelsim_fli/transport_udp/firmware/sim/ipbus_sim_udp.vhd
---------------------------------------------------------------------------------
--
-- Copyright 2017 - <NAME> Laboratory and University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ipbus.web.cern.ch/ipbus
--
---------------------------------------------------------------------------------
-- Uses the FLI mechanism to send / receive uHAL UDP packets.
--
-- There are two modes of operation:
--
-- If MULTI_PACKET = false, there is a 'one-in, one-out' assumption, i.e.
-- multiple packets cannot be processed simultaneously. This allows the
-- simulator to be paused while waiting for a new packet, reducing the
-- number of cycles to be simulated. A timeout applies in case the firmware
-- decides not to reply to a packet.
--
-- If MULTI_PACKET = true, the simulator runs continuously, can receive
-- and transmit simultaneously, and can queue multiple input packets. This
-- will cause a large number of cycles to be simulated.
--
-- <NAME>, April 2019
--
-- $Id$
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ipbus_trans_decl.all;
entity ipbus_sim_udp is
generic(
MULTI_PACKET: boolean := false
);
port(
clk_ipb: in std_logic;
rst_ipb: in std_logic;
trans_out: out ipbus_trans_in;
trans_in: in ipbus_trans_out
);
end ipbus_sim_udp;
architecture behavioural of ipbus_sim_udp is
attribute FOREIGN: string;
procedure get_pkt_data(
variable del_return: in integer;
variable data, valid, last: out integer) is
begin
report "ERROR: get_pkt_data can't get here";
end;
attribute FOREIGN of get_pkt_data : procedure is "get_pkt_data sim_udp_fli.so";
procedure store_pkt_data(
variable mac_data_in: in integer) is
begin
report "ERROR: store_pkt_data can't get here";
end;
attribute FOREIGN of store_pkt_data : procedure is "store_pkt_data sim_udp_fli.so";
procedure send_pkt is
begin
report "ERROR: send_pkt can't get here";
end;
attribute FOREIGN of send_pkt : procedure is "send_pkt sim_udp_fli.so";
constant TIMEOUT_VAL: integer := 32768;
signal rxbuf_addr, txbuf_addr, rx_addr, tx_addr: std_logic_vector(9 downto 0);
signal tx_len: std_logic_vector(9 downto 0) := (others => '0');
signal rxbuf_data, txbuf_data: std_logic_vector(31 downto 0);
signal timer: integer;
signal rx_valid, rx_last, tx_done, timeout: std_logic;
type state_type is (ST_IDLE, ST_WAIT_PKT, ST_RXPKT, ST_RXDEL, ST_WAIT, ST_TXDEL, ST_TXPKT);
signal state: state_type;
begin
-- Buffers
rxbuf: entity work.ipbus_udp_ram_buf
port map(
clk => clk_ipb,
addr => rxbuf_addr,
rd => trans_out.rdata,
wd => rxbuf_data,
wen => rx_valid
);
txbuf: entity work.ipbus_udp_ram_buf
port map(
clk => clk_ipb,
addr => txbuf_addr,
rd => txbuf_data,
wd => trans_in.wdata,
wen => trans_in.we
);
-- Address lines
rxbuf_addr <= trans_in.raddr(9 downto 0) when state = ST_WAIT or state = ST_RXDEL else rx_addr;
txbuf_addr <= trans_in.waddr(9 downto 0) when state = ST_WAIT else tx_addr;
process(clk_ipb)
begin
if rising_edge(clk_ipb) then
if state = ST_IDLE then
rx_addr <= (others => '0');
tx_addr <= (others => '0');
else
if rx_valid = '1' then
rx_addr <= std_logic_vector(unsigned(rx_addr) + 1);
end if;
if state = ST_TXPKT or state = ST_TXDEL then
tx_addr <= std_logic_vector(unsigned(tx_addr) + 1);
end if;
end if;
end if;
end process;
-- State machine
process(clk_ipb)
begin
if rising_edge(clk_ipb) then
if rst_ipb = '1' then
state <= ST_IDLE;
else
case state is
-- Starting state
when ST_IDLE =>
state <= ST_WAIT_PKT;
-- Waiting for packet
when ST_WAIT_PKT =>
if rx_valid = '1' then
state <= ST_RXPKT;
end if;
-- Receiving packet
when ST_RXPKT =>
if rx_last = '1' then
state <= ST_RXDEL;
end if;
-- Wait for RAM
when ST_RXDEL =>
state <= ST_WAIT;
-- Waiting for transactor
when ST_WAIT =>
if timeout = '1' then
state <= ST_IDLE;
elsif trans_in.pkt_done = '1' then
state <= ST_TXDEL;
end if;
-- Wait for RAM
when ST_TXDEL =>
state <= ST_TXPKT;
-- Transmitting packet
when ST_TXPKT =>
if tx_done = '1' then
state <= ST_IDLE;
end if;
end case;
end if;
end if;
end process;
-- Handshaking
trans_out.pkt_rdy <= '1' when state = ST_WAIT else '0';
trans_out.busy <= '0';
-- Packet rx
packet_rx: process(clk_ipb)
variable del, data, valid, last: integer;
begin
if MULTI_PACKET then
del := 0;
else
del := 1;
end if;
if rising_edge(clk_ipb) then
if state = ST_WAIT_PKT or (state = ST_RXPKT and rx_last = '0') then
get_pkt_data(del_return => del, data => data, valid => valid, last => last);
rxbuf_data <= std_logic_vector(to_signed(data, 32));
if valid = 1 then
rx_valid <= '1';
else
rx_valid <= '0';
end if;
if last = 1 then
rx_last <= '1';
else
rx_last <= '0';
end if;
else
rx_valid <= '0';
rx_last <= '0';
end if;
end if;
end process;
-- Packet tx
packet_tx: process(clk_ipb)
variable data: integer;
begin
if rising_edge(clk_ipb) then
if trans_in.waddr = (trans_in.waddr'range => '0') and trans_in.we = '1' then
tx_len <= std_logic_vector(unsigned(trans_in.wdata(25 downto 16)) + unsigned(trans_in.wdata(9 downto 0)) + 1);
end if;
if state = ST_TXPKT then
data := to_integer(signed(txbuf_data));
store_pkt_data(mac_data_in => data);
if tx_done = '1' then
send_pkt;
end if;
end if;
end if;
end process;
tx_done <= '1' when tx_addr = tx_len else '0';
-- Timeout
process(clk_ipb)
begin
if rising_edge(clk_ipb) then
if state /= ST_WAIT then
timer <= 0;
timeout <= '0';
elsif timeout = '0' then
timer <= timer + 1;
if timer = TIMEOUT_VAL then
timeout <= '1';
end if;
end if;
end if;
end process;
end behavioural;
|
<gh_stars>1-10
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal ll_in : electrical;
terminal ll_out : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => ll_out,
output => servo_out
);
XCMP22 : entity work.lead_lag_e(simple)
generic map(
f2 => 2000.0,
f1 => 5.0,
k => 400.0
)
port map(
input => ll_in,
output => ll_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : <NAME>
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang'above(ang_max) use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang'above(ang_min) use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
entity amp_lim is
port (terminal ps : electrical; -- positive supply terminal
terminal input, output : electrical);
end entity amp_lim;
architecture simple of amp_lim is
quantity v_pwr across i_pwr through ps to electrical_ref;
quantity vin across iin through input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity v_amplified : voltage ;
constant gain : real := 1.0;
begin
v_amplified == gain*vin;
if v_amplified > v_pwr use
vout == v_pwr;
else
vout == v_amplified;
end use;
-- ignore loading effects
i_pwr == 0.0;
iin == 0.0;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library ieee;
use ieee.math_real.all;
package pwl_full_functions is
function next_increment(x : in real; xdata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
return real;
end package pwl_full_functions;
package body pwl_full_functions is
function next_increment(x : in real; xdata : in real_vector)
return real is
variable i : integer;
begin
i := 0;
while i <= xdata'right loop
if x >= xdata(i) - 6.0e-15 then -- The value 6.0e-15 envelopes round-off error
-- of real-to-time conversion in calling model
i := i + 1;
else
return xdata(i) - xdata(i - 1);
end if;
end loop;
return 1.0; -- Returns a "large number" relative to expected High-Speed time scale
end function next_increment;
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
-- Created a new pwl_dim1_flat function that returns a constant
-- value of ydata(0) if x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right)
function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x >= xdata(xdata'right) then
yvalue := ydata(ydata'right);
return yvalue;
end if;
if x <= xdata(0) then
yvalue := ydata(0);
return yvalue;
end if;
start:=0;
fin:=xdata'right;
-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
-- so fin==n-1 in C terms (where n is the size of the array).
while start <=fin loop
mid:=(start+fin)/2;
if xdata(mid) < x
then start:=mid+1;
else fin:=mid-1;
end if;
end loop;
if xdata(mid) > x
then mid:=mid-1;
end if;
yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
return yvalue;
end function pwl_dim1_flat;
end package body pwl_full_functions;
-- Not sure the sync_tdata process is necessary. Requires the tdata set contain
-- a larger value than the actual simulation time.
-- Piece-wise linear voltage source model
library IEEE;
use IEEE.std_logic_1164.all;
Library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use work.pwl_full_functions.all;
entity v_pwl_full is
generic (
vdata : real_vector; -- v-pulse data
tdata : real_vector -- time-data for v-pulse
);
port (
terminal pos, neg : electrical
);
end entity v_pwl_full;
architecture ideal of v_pwl_full is
QUANTITY v across i through pos TO neg;
signal tick : std_logic := '0'; -- Sync signal for tdata "tracking"
begin
sync_tdata: process is
variable next_tick_delay : real := 0.0; -- Time increment to the next time-point in tdata
begin
wait until domain = time_domain;
loop
next_tick_delay := next_increment(NOW,tdata);
tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs);
wait on tick;
end loop;
end process sync_tdata;
break on tick; -- Forces analog solution point at all tdata time-points
v == pwl_dim1_flat(NOW, tdata, vdata);
end architecture ideal;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity tb_CS5_Amp_Lim is
end tb_CS5_Amp_Lim;
architecture TB_CS5_Amp_Lim of tb_CS5_Amp_Lim is
-- Component declarations
-- Signal declarations
terminal amp_in : electrical;
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal mot_out : rotational_v;
terminal pos_fb_v : electrical;
terminal power : electrical;
terminal rudder_in : rotational;
terminal src_in : electrical;
terminal XSIG010068 : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => amp_in,
servo_in => src_in,
pos_fb => pos_fb_v
);
gear3 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => mot_out,
rot2 => gear_out
);
r2v : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pos_fb_v,
input => gear_out
);
r2t : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
t2r : entity work.horn_t2r(bhv)
port map(
theta => rudder_in,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
j => 168.0e-9,
d => 5.63e-6,
l => 2.03e-3,
kt => 3.43e-3,
r_wind => 2.2
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => mot_out
);
stop1 : entity work.stop_r(ideal)
generic map(
ang_min => -1.05,
ang_max => 1.05,
k_stop => 1.0e6,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
XCMP35 : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP36 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder_in
);
R2w : entity work.resistor(ideal)
generic map(
res => 1000.0
)
port map(
p1 => XSIG010068,
p2 => ELECTRICAL_REF
);
XCMP55 : entity work.amp_lim(simple)
port map(
input => amp_in,
output => mot_in,
ps => power
);
v9 : entity work.v_pulse(ideal)
generic map(
initial => 0.0,
pulse => 4.8,
ti2p => 300ms,
tp2i => 300ms,
delay => 100ms,
width => 5ms,
period => 605ms
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
XCMP57 : entity work.v_pwl_full(ideal)
generic map(
tdata => (0.0,100.0e-3,400.0e-3,900.0e-3,1300.0e-3,1800.0e-3,2300.0e-3,2600.0e-3, 2900.0e-3),
vdata => (0.0,0.0,2.4,2.4,4.7,4.7,1.0,1.0,0.0)
)
port map(
pos => XSIG010068,
neg => ELECTRICAL_REF
);
XCMP60 : entity work.v_pwl_full(ideal)
generic map(
vdata => (4.8,4.8,4.4,4.4,4.0,4.0,3.6,3.6,3.2,3.2),
tdata => (0.0,705.0e-3,706.0e-3,1310.0e-3,1320.0e-3,1915.0e-3,1925.0e-3,2520.0e-3,2530.0e-3,3125.0e-3)
)
port map(
pos => power,
neg => ELECTRICAL_REF
);
end TB_CS5_Amp_Lim;
--
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:45:29 04/19/2020
-- Design Name:
-- Module Name: C:/ISE/Project_PWM/Encoder_to_time_TB.vhd
-- Project Name: Project_PWM
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Encoder_to_time
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Encoder_to_time_TB IS
END Encoder_to_time_TB;
ARCHITECTURE behavior OF Encoder_to_time_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Encoder_to_time
PORT(
enc_in_A_B : IN std_logic_vector(1 downto 0);
srst_n_i : IN std_logic;
number_o : OUT unsigned(7-1 downto 0)
);
END COMPONENT;
--Inputs
signal enc_in_A_B : std_logic_vector(1 downto 0) := (others => '0');
signal srst_n_i : std_logic := '0';
--Outputs
signal number_o : unsigned(7-1 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Encoder_to_time PORT MAP (
enc_in_A_B => enc_in_A_B,
srst_n_i => srst_n_i,
number_o => number_o
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
srst_n_i <= '1';
wait for clk_period;
enc_in_A_B <= "01";
wait for clk_period;
enc_in_A_B <= "11";
wait for clk_period;
enc_in_A_B <= "10";
wait for clk_period;
enc_in_A_B <= "00";
wait;
end process;
END;
|
<reponame>dsd-g05/lab4
-- Descp. Determines which LED should be lit up on the 7-segment display.
--
-- entity name: g05_7_segment_decoder
--
-- Version 1.0
-- Author: <NAME>; <EMAIL> & <NAME>; <EMAIL>
-- Date: October 29, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_7_segment_decoder is
port (
code : in std_logic_vector(3 downto 0);
RippleBlank_In : in std_logic;
RippleBlank_Out : out std_logic;
segments : out std_logic_vector(6 downto 0)
);
end g05_7_segment_decoder;
architecture behavior of g05_7_segment_decoder is
-- input is the concatenation of RippleBlank_In and code
signal input : std_logic_vector(4 downto 0);
-- output is the concatenation of RippleBlank_Out and segments
signal output : std_logic_vector(7 downto 0);
begin
input <= RippleBlank_In & code;
with input select output <=
"01000000" when "00000", --display 0
"01111001" when "00001", --display 1
"00100100" when "00010", --display 2
"00110000" when "00011", --display 3
"00011001" when "00100", --display 4
"00010010" when "00101", --display 5
"00000010" when "00110", --display 6
"01111000" when "00111", --display 7
"00000000" when "01000", --display 8
"00011000" when "01001", --display 9
"00000011" when "01010", --display b (blue)
"00101111" when "01011", --display r (red)
"00101011" when "01100", --display n (black)
"01110001" when "01101", --display j (yellow)
"01100011" when "01110", --display v (green)
"00100111" when "01111", --display c (white)
"01111001" when "10001", --display 1
"00100100" when "10010", --display 2
"00110000" when "10011", --display 3
"00011001" when "10100", --display 4
"00010010" when "10101", --display 5
"00000010" when "10110", --display 6
"01111000" when "10111", --display 7
"00000000" when "11000", --display 8
"00011000" when "11001", --display 9
"00000011" when "11010", --display b (blue)
"00101111" when "11011", --display r (red)
"00101011" when "11100", --display n (black)
"01110001" when "11101", --display j (yellow)
"01100011" when "11110", --display v (green)
"00100111" when "11111", --display c (white)
"11111111" when others;
RippleBlank_Out <= output(7);
segments <= output(6 downto 0);
end behavior;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : pcie_7x_0_pcie_pipe_lane.vhd
-- Version : 3.3
--
-- Description: PIPE per lane module for 7-Series PCIe Block
--
--
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_7x_0_pcie_pipe_lane is
generic
(
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port
(
pipe_rx_char_is_k_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Rx Char Is K
pipe_rx_data_o : out std_logic_vector(15 downto 0); -- Pipelined PIPE Rx Data
pipe_rx_valid_o : out std_logic; -- Pipelined PIPE Rx Data Valid
pipe_rx_chanisaligned_o : out std_logic; -- Pipelined PIPE Rx Chan Is Aligned
pipe_rx_status_o : out std_logic_vector( 2 downto 0); -- Pipelined PIPE Rx Status
pipe_rx_phy_status_o : out std_logic; -- Pipelined PIPE Rx Phy Status
pipe_rx_elec_idle_o : out std_logic; -- Pipelined PIPE Rx Electrical Idle
pipe_rx_polarity_i : in std_logic; -- PIPE Rx Polarity
pipe_tx_compliance_i : in std_logic; -- PIPE Tx Compliance
pipe_tx_char_is_k_i : in std_logic_vector( 1 downto 0); -- PIPE Tx Char Is K
pipe_tx_data_i : in std_logic_vector(15 downto 0); -- PIPE Tx Data
pipe_tx_elec_idle_i : in std_logic; -- PIPE Tx Electrical Idle
pipe_tx_powerdown_i : in std_logic_vector( 1 downto 0); -- PIPE Tx Powerdown
pipe_rx_char_is_k_i : in std_logic_vector( 1 downto 0); -- PIPE Rx Char Is K
pipe_rx_data_i : in std_logic_vector(15 downto 0); -- PIPE Rx Data
pipe_rx_valid_i : in std_logic; -- PIPE Rx Data Valid
pipe_rx_chanisaligned_i : in std_logic; -- PIPE Rx Chan Is Aligned
pipe_rx_status_i : in std_logic_vector( 2 downto 0); -- PIPE Rx Status
pipe_rx_phy_status_i : in std_logic; -- PIPE Rx Phy Status
pipe_rx_elec_idle_i : in std_logic; -- PIPE Rx Electrical Idle
pipe_rx_polarity_o : out std_logic; -- Pipelined PIPE Rx Polarity
pipe_tx_compliance_o : out std_logic; -- Pipelined PIPE Tx Compliance
pipe_tx_char_is_k_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Tx Char Is K
pipe_tx_data_o : out std_logic_vector(15 downto 0); -- Pipelined PIPE Tx Data
pipe_tx_elec_idle_o : out std_logic; -- Pipelined PIPE Tx Electrical
pipe_tx_powerdown_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Tx Powerdown
pipe_clk : in std_logic; -- PIPE Clock
rst_n : in std_logic -- Reset
);
end pcie_7x_0_pcie_pipe_lane;
architecture rtl of pcie_7x_0_pcie_pipe_lane is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
--******************************************************************--
-- Reality check. --
--******************************************************************--
constant TCQ : integer := 1;
signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx_data_q : std_logic_vector(15 downto 0);
signal pipe_rx_valid_q : std_logic;
signal pipe_rx_chanisaligned_q : std_logic;
signal pipe_rx_status_q : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_q : std_logic;
signal pipe_rx_elec_idle_q : std_logic;
signal pipe_rx_polarity_q : std_logic;
signal pipe_tx_compliance_q : std_logic;
signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_tx_data_q : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_q : std_logic;
signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0);
signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_rx_data_qq : std_logic_vector(15 downto 0);
signal pipe_rx_valid_qq : std_logic;
signal pipe_rx_chanisaligned_qq : std_logic;
signal pipe_rx_status_qq : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_qq : std_logic;
signal pipe_rx_elec_idle_qq : std_logic;
signal pipe_rx_polarity_qq : std_logic;
signal pipe_tx_compliance_qq : std_logic;
signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_tx_data_qq : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_qq : std_logic;
signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0);
begin -- rtl
pipe_stages_0 : if (PIPE_PIPELINE_STAGES = 0) generate
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
pipe_rx_data_o <= pipe_rx_data_i;
pipe_rx_valid_o <= pipe_rx_valid_i;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
pipe_rx_status_o <= pipe_rx_status_i;
pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
pipe_rx_polarity_o <= pipe_rx_polarity_i;
pipe_tx_compliance_o <= pipe_tx_compliance_i;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
pipe_tx_data_o <= pipe_tx_data_i;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
end generate; -- pipe_stages_0
pipe_stages_1 : if (PIPE_PIPELINE_STAGES = 1) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
pipe_rx_data_o <= pipe_rx_data_q;
pipe_rx_valid_o <= pipe_rx_valid_q;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
pipe_rx_status_o <= pipe_rx_status_q;
pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
pipe_rx_polarity_o <= pipe_rx_polarity_q;
pipe_tx_compliance_o <= pipe_tx_compliance_q;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
pipe_tx_data_o <= pipe_tx_data_q;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
end generate; -- pipe_stages_1
pipe_stages_2 : if (PIPE_PIPELINE_STAGES = 2) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_rx_data_qq <= (others => '0') after (TCQ)*1 ps;
pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_tx_data_qq <= (others => '0') after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
pipe_rx_data_o <= pipe_rx_data_qq;
pipe_rx_valid_o <= pipe_rx_valid_qq;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
pipe_rx_status_o <= pipe_rx_status_qq;
pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
pipe_rx_polarity_o <= pipe_rx_polarity_qq;
pipe_tx_compliance_o <= pipe_tx_compliance_qq;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
pipe_tx_data_o <= pipe_tx_data_qq;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
end generate; -- pipe_stages_2
end rtl;
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- Company: DHBW
-- Engineer: <NAME>
--
-- Create Date: 05/16/2021 08:17:06 PM
-- Design Name: AXI4_lite_master
-- Module Name: AXI4_lite_master - rtl
-- Project Name: EDRICO
-- Target Devices: Arty Z7
-- Tool Versions:
-- Description:
-- This is the top module of the AXI4 master interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library AXI4M_lib;
use AXI4M_lib.AXI4_lite_master_pkg.ALL;
----------------------------------------------------------------------------------
--ENTITY
----------------------------------------------------------------------------------
entity AXI4_lite_master is
port (
------------------------------------------------------------------------------
--AXI channels
------------------------------------------------------------------------------
--clock and reset
M_AXI_ACLK : in STD_LOGIC;
M_AXI_ARSTN : in STD_LOGIC;
--read address channel
M_AXI_ARADDR : out STD_LOGIC_VECTOR (31 downto 0);
M_AXI_ARCACHE : out STD_LOGIC_VECTOR (3 downto 0);
M_AXI_ARPROT : out STD_LOGIC_VECTOR (2 downto 0);
M_AXI_ARVALID : out STD_LOGIC;
M_AXI_ARREADY : in STD_LOGIC;
--read data channel
M_AXI_RDATA : in STD_LOGIC_VECTOR (31 downto 0);
M_AXI_RRESP : in STD_LOGIC_VECTOR (1 downto 0);
M_AXI_RVALID : in STD_LOGIC;
M_AXI_RREADY : out STD_LOGIC;
--write address channel
M_AXI_AWADDR : out STD_LOGIC_VECTOR (31 downto 0);
M_AXI_AWCACHE : out STD_LOGIC_VECTOR (3 downto 0);
M_AXI_AWPROT : out STD_LOGIC_VECTOR (2 downto 0);
M_AXI_AWVALID : out STD_LOGIC;
M_AXI_AWREADY : in STD_LOGIC;
--write data channel
M_AXI_WDATA : out STD_LOGIC_VECTOR (31 downto 0);
M_AXI_WSTRB : out STD_LOGIC_VECTOR (3 downto 0);
M_AXI_WVALID : out STD_LOGIC;
M_AXI_WREADY : in STD_LOGIC;
--write response channel
M_AXI_BRESP : in STD_LOGIC_VECTOR (1 downto 0);
M_AXI_BVALID : in STD_LOGIC;
M_AXI_BREADY : out STD_LOGIC;
------------------------------------------------------------------------------
--input signals
------------------------------------------------------------------------------
--control signals
enable : in STD_LOGIC;
readWrite : in STD_LOGIC;
instruction : in STD_LOGIC;
size : in STD_LOGIC_VECTOR (1 downto 0);
--halt core signal
halt_core : in STD_LOGIC;
--clock and reset
reset : in STD_LOGIC;
--address and data input
address_in : in STD_LOGIC_VECTOR (31 downto 0);
data_in : in STD_LOGIC_VECTOR (31 downto 0);
------------------------------------------------------------------------------
--output signals
------------------------------------------------------------------------------
--system control
memOp_finished : out STD_LOGIC;
store_systemData : out STD_LOGIC;
--exception flags
instruction_afe_AXI : out STD_LOGIC;
storeAMO_afe_AXI : out STD_LOGIC;
load_afe_AXI : out STD_LOGIC;
--data output
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end AXI4_lite_master;
----------------------------------------------------------------------------------
--ARCHITECTURE
----------------------------------------------------------------------------------
architecture rtl of AXI4_lite_master is
----------------------------------------------------------------------------------
--signals
----------------------------------------------------------------------------------
signal reset_local : std_logic;
signal load_address : std_logic;
signal load_data : std_logic;
signal address_register : std_logic_vector(31 downto 0);
signal data_register : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------------------
--AXI4 lite master control unit
----------------------------------------------------------------------------------
AXI4_LM_CU: AXI4_lite_master_control_unit
port map(
------------------------------------------------------------------------------
--AXI channels
------------------------------------------------------------------------------
--clock and reset
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARSTN => M_AXI_ARSTN,
--read address channel
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
--read data channel
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
--write address channel
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
--write data channel
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
--write response channel
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
------------------------------------------------------------------------------
--input signals
------------------------------------------------------------------------------
--controll signals
enable => enable,
readWrite => readWrite,
instruction => instruction,
size => size,
--halt core
halt_core => halt_core,
--clock and reset
reset => reset,
------------------------------------------------------------------------------
--output signals
------------------------------------------------------------------------------
--system control
memOp_finished => memOp_finished,
store_systemData => store_systemData,
--exception flags
load_afe_AXI => load_afe_AXI,
storeAMO_afe_AXI => storeAMO_afe_AXI,
instruction_afe_AXI => instruction_afe_AXI,
--register control
load_address => load_address,
load_data => load_data
);
----------------------------------------------------------------------------------
--address register
----------------------------------------------------------------------------------
addr_reg: process(M_AXI_ACLK, reset, M_AXI_ARSTN, reset_local)
begin
if(reset = '1' or M_AXI_ARSTN = '0') then
address_register <= (others => '0');
elsif(M_AXI_ACLK'event and M_AXI_ACLK = '1') then
if(reset_local = '1') then
address_register <= (others => '0');
elsif(load_address = '1') then
address_register <= address_in;
end if;
end if;
end process;
----------------------------------------------------------------------------------
--data register
----------------------------------------------------------------------------------
data_reg: process(M_AXI_ACLK, reset, M_AXI_ARSTN, reset_local)
begin
if(reset = '1' or M_AXI_ARSTN = '0') then
data_register <= (others => '0');
elsif(M_AXI_ACLK'event and M_AXI_ACLK = '1') then
if(reset_local = '1') then
data_register <= (others => '1');
elsif(load_data = '1') then
data_register <= data_in;
end if;
end if;
end process;
----------------------------------------------------------------------------------
--address and data assignements
----------------------------------------------------------------------------------
M_AXI_AWADDR <= address_register;
M_AXI_ARADDR <= address_register;
M_AXI_WDATA <= data_register;
data_out <= M_AXI_RDATA;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xorshift16 is
port(
clk : in std_logic;
rst_n : in std_logic;
kick_n : in std_logic;
d_en_n : out std_logic;
data : out std_logic_vector(3 downto 0)
);
end xorshift16;
architecture RTL of xorshift16 is
signal y: std_logic_vector(15 downto 0) := X"8ca2";
signal state: std_logic_vector(3 downto 0) := "0000";
begin
process(clk)
begin
if clk'event and clk = '1' then
if rst_n = '0' then
d_en_n <= '1';
state <= "0000";
else
case state is
when "0000" =>
if kick_n = '0' then
y <= y xor
(y((15 - 2) downto 0) & "00");
state <= "0001";
end if;
when "0001" =>
y <= y xor
("00000" & y(15 downto 5));
state <= "0011";
when "0011" =>
y <= y xor
(y((15 - 8) downto 0) & "00000000");
state <= "0010";
when "0010" =>
state <= "0110";
d_en_n <= '0';
data <= y(3 downto 0);
when "0110" =>
state <= "0111";
data <= y(7 downto 4);
when "0111" =>
state <= "0101";
data <= y(11 downto 8);
when "0101" =>
state <= "0100";
data <= y(15 downto 12);
when "0100" =>
d_en_n <= '1';
state <= "0000";
when others =>
null;
end case;
end if;
end if;
end process;
end RTL;
|
<reponame>JRRitter/Digital-electronics-1<gh_stars>1-10
------------------------------------------------------------------------
-- Library declaration
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------------
-- Entity declaration for commander
------------------------------------------------------------------------
entity commander is
generic(
g_command1: unsigned(8-1 downto 0) := "01000000";
g_command2: unsigned(8-1 downto 0) := "11000000";
g_command3: unsigned(8-1 downto 0) := "10001101"
);
port(
-- Inputs
clk_i : in std_logic; -- Clock 10 kHz
srst_n_i: in std_logic; -- Synchronous reset (active low)
current_time_i: in unsigned(12-1 downto 0);
-- Outputs
CLK_o : out std_logic := '1';
DIO_o : out std_logic := '1'
);
end entity commander;
------------------------------------------------------------------------
-- Architecture declaration for commander
------------------------------------------------------------------------
architecture Behavioral of commander is
-- signal with the last
signal s_last_time : unsigned(12-1 downto 0) := x"000";
-- signal representing output CLK_o
signal s_CLK : std_logic := '1';
-- signal representing output DIO_o
signal s_DIO : std_logic := '1';
-- activate command sequence
signal s_activated : std_logic := '0';
-- counter for the whole command sequence
signal s_counter : unsigned(8-1 downto 0) := x"00";
-- counter for inner segments of command sequence
signal s_cnt_inner : unsigned(5-1 downto 0) := "00000";
-- Numbers that are supposed to be displayed on corresponding grids
signal s_num1 : unsigned(12-1 downto 0) := x"000";
signal s_num2 : unsigned(12-1 downto 0) := x"000";
signal s_num3 : unsigned(12-1 downto 0) := x"000";
signal s_num4 : unsigned(12-1 downto 0) := x"000";
-- 7 segment display data with decimal point for corresponding grids
signal s_grid1 : unsigned(8-1 downto 0) := x"00";
signal s_grid2 : unsigned(8-1 downto 0) := x"00";
signal s_grid3 : unsigned(8-1 downto 0) := x"00";
signal s_grid4 : unsigned(8-1 downto 0) := x"00";
begin
------------------------------------------------------------------------
-- p_activate_command:
-- Compares last value of time (s_last_time) with current time of input
-- current_time_i. If they differ, set s_activate_command to '1', thus
-- starting the command creation and stopping the comparison of input.
------------------------------------------------------------------------
p_activate_command: process (clk_i)
begin
if rising_edge(clk_i) then --and s_activated = '0' then -- Rising clock edge
if srst_n_i = '0' then -- Synchronous reset
s_last_time <= x"000";
s_activated <= '0';
s_counter <= x"00";
s_num1 <= x"000";
s_num2 <= x"000";
s_num3 <= x"000";
s_num4 <= x"000";
s_grid1 <= x"00";
s_grid2 <= x"00";
s_grid3 <= x"00";
s_grid4 <= x"00";
elsif s_activated = '0' then
if (s_last_time = current_time_i) then
else -- s_last_time is not current_time_i
s_activated <= '1';
-- time mod 10 = # of seconds
s_num1 <= current_time_i mod x"00A";
-- ((time mod 60) - # of seconds) / 10 = # of tens of seconds
s_num2 <= (current_time_i mod x"03C" - current_time_i mod x"00A")/x"00A";
-- ((time mod 600) - (time mod 60)) / 60 = # of minutes
s_num3 <= (current_time_i mod x"258" - current_time_i mod x"03C")/x"03C";
-- (time - (time mod 600)) / 600 = # of tens of minutes
s_num4 <= (current_time_i - current_time_i mod x"258")/x"258";
end if;
s_last_time <= current_time_i;
------------------------------------------------------------------------
-- command_counter:
-- after activation increments s_counter till the end of
-- the sequence (x"CB"); after that it sets s_activated to zero
-- and resets the counter
-- the counter directly dictates the sequences of DIO_o and CLK_o
------------------------------------------------------------------------
elsif s_activated = '1' then
if s_counter >= x"CB" then
s_counter <= x"00";
s_activated <= '0';
elsif s_counter = x"00" then
s_grid1 <= "11000000" when (s_num1 = x"000") else
"11111001" when (s_num1 = x"001") else
"10100100" when (s_num1 = x"002") else
"10110000" when (s_num1 = x"003") else
"10011001" when (s_num1 = x"004") else
"10010010" when (s_num1 = x"005") else
"10000010" when (s_num1 = x"006") else
"11111000" when (s_num1 = x"007") else
"10000000" when (s_num1 = x"008") else
"10010000";
s_grid2 <= "11000000" when (s_num2 = x"000") else
"11111001" when (s_num2 = x"001") else
"10100100" when (s_num2 = x"002") else
"10110000" when (s_num2 = x"003") else
"10011001" when (s_num2 = x"004") else
"10010010" when (s_num2 = x"005") else
"10000010" when (s_num2 = x"006") else
"11111000" when (s_num2 = x"007") else
"10000000" when (s_num2 = x"008") else
"10010000";
s_grid3 <= "11000000" when (s_num3 = x"000") else
"11111001" when (s_num3 = x"001") else
"10100100" when (s_num3 = x"002") else
"10110000" when (s_num3 = x"003") else
"10011001" when (s_num3 = x"004") else
"10010010" when (s_num3 = x"005") else
"10000010" when (s_num3 = x"006") else
"11111000" when (s_num3 = x"007") else
"10000000" when (s_num3 = x"008") else
"10010000";
s_grid4 <= "11000000" when (s_num4 = x"000") else
"11111001" when (s_num4 = x"001") else
"10100100" when (s_num4 = x"002") else
"10110000" when (s_num4 = x"003") else
"10011001" when (s_num4 = x"004") else
"10010010" when (s_num4 = x"005") else
"10000010" when (s_num4 = x"006") else
"11111000" when (s_num4 = x"007") else
"10000000" when (s_num4 = x"008") else
"10010000";
s_counter <= s_counter + x"01";
else
s_counter <= s_counter + x"01";
end if;
end if;
end if;
end process p_activate_command;
------------------------------------------------------------------------
-- p_create-clk:
-- Creates sequence of output CLK
-- The overall sequence is:
-- START - COMMAND 1 - END - START - COMMAND 2 - DATA 1~4 - END -
-- START - COMMAND 3 - END
-- for commands and data it creates a square wave with duty cycle 1/3
------------------------------------------------------------------------
p_create_clk : process (clk_i)
begin
if rising_edge(clk_i) and s_activated = '1' then -- Rising clock edge
if srst_n_i = '0' then -- Synchronous reset
s_CLK <= '1';
s_cnt_inner <= "00000";
else
if (s_counter >= x"01") and (s_counter < x"1F") then
-- starting one clock earlier due to mod
-- vytváří 001001001001... spravne
if (s_cnt_inner mod "00011") = "00000" then -- mod 3 = 0
s_CLK <= '0';
s_cnt_inner <= s_cnt_inner + "00001";
elsif (s_cnt_inner mod "00011") = "00001" then -- mod 3 = 1
s_CLK <= '0';
s_cnt_inner <= s_cnt_inner + "00001";
else -- (s_cnt_inner mod 3) = 2
s_CLK <= '1';
s_cnt_inner <= s_cnt_inner + "00001";
end if;
if s_cnt_inner = "11101" then -- (30) reset inner counter on end of sequence
s_cnt_inner <= "00000";
end if;
elsif (s_counter = x"1F") then
s_CLK <= '1';
elsif (s_counter >= x"21") and (s_counter < x"AB") then
-- vytváří 001001001001... spravne
if (s_cnt_inner mod "00011") = "00000" then -- mod 3 = 0
s_CLK <= '0';
s_cnt_inner <= s_cnt_inner + "00001";
elsif (s_cnt_inner mod "00011") = "00001" then -- mod 3 = 1
s_CLK <= '0';
s_cnt_inner <= s_cnt_inner + "00001";
else -- (s_cnt_inner mod 3) = 2
s_CLK <= '1';
s_cnt_inner <= s_cnt_inner + "00001";
end if;
if s_cnt_inner = "11110" then
s_cnt_inner <= "00001";
end if;
if s_counter = x"AA" then -- (27) reset inner counter on end of sequence
s_cnt_inner <= "00000";
end if;
elsif (s_counter = x"AB") then
s_CLK <= '1';
elsif (s_counter >= x"AD") and (s_counter < x"CB") then
if (s_cnt_inner mod "00011") = "00000" then -- mod 3 = 0
s_CLK <= '0';
s_cnt_inner <= s_cnt_inner + "00001";
elsif (s_cnt_inner mod "00011") = "00001" then -- mod 3 = 1
s_CLK <= '0';
s_cnt_inner <= s_cnt_inner + "00001";
else -- (s_cnt_inner mod 3) = 2
s_CLK <= '1';
s_cnt_inner <= s_cnt_inner + "00001";
end if;
if s_cnt_inner = "11101" then -- (30) reset inner counter on end of sequence
s_cnt_inner <= "00000";
end if;
else -- s_counter = CB
s_CLK <= '1';
end if;
end if;
end if;
end process p_create_clk;
------------------------------------------------------------------------
-- p_create-command:
-- Creates sequence of output DIO
-- The overall sequence is:
-- START - COMMAND 1 - END - START - COMMAND 2 - DATA 1~4 - END -
-- START - COMMAND 3 - END
-- command 1 sets the TM1637 into auto adress increment mode
-- command 2 sets starter adress
-- data 1~4 are the values from s_grid1~4
-- command 3 sets the display to on with set pulsewidth 12/16
------------------------------------------------------------------------
p_create_command : process (clk_i)
begin
if rising_edge(clk_i) and s_activated = '1' then -- Rising clock edge
if srst_n_i = '0' then -- Synchronous reset
s_DIO <= '0';
else
if s_counter = x"00" then
-- START
s_DIO <= '0';
elsif (s_counter >= x"01") and (s_counter < x"1F") then
-- COMMAND 1
case s_counter is
when x"01"+x"01" => s_DIO <= g_command1(0);
when x"01"+x"04" => s_DIO <= g_command1(1);
when x"01"+x"07" => s_DIO <= g_command1(2);
when x"01"+x"0A" => s_DIO <= g_command1(3);
when x"01"+x"0D" => s_DIO <= g_command1(4);
when x"01"+x"10" => s_DIO <= g_command1(5);
when x"01"+x"13" => s_DIO <= g_command1(6);
when x"01"+x"16" => s_DIO <= g_command1(7);
when x"01"+x"19" => s_DIO <= '0';
when others =>
end case;
elsif (s_counter = x"1F") then
-- END
s_DIO <= '1';
elsif (s_counter = x"20") then
-- START
s_DIO <= '0';
elsif (s_counter >= x"21") and (s_counter < x"AB") then
-- COMMAND 2
case s_counter is
when x"21"+x"01" => s_DIO <= g_command2(0);
when x"21"+x"04" => s_DIO <= g_command2(1);
when x"21"+x"07" => s_DIO <= g_command2(2);
when x"21"+x"0A" => s_DIO <= g_command2(3);
when x"21"+x"0D" => s_DIO <= g_command2(4);
when x"21"+x"10" => s_DIO <= g_command2(5);
when x"21"+x"13" => s_DIO <= g_command2(6);
when x"21"+x"16" => s_DIO <= g_command2(7);
when x"21"+x"19" => s_DIO <= '0';
when others =>
end case;
-- DATA 1
case s_counter is
when x"3C"+x"01" => s_DIO <= s_grid1(0);
when x"3C"+x"04" => s_DIO <= s_grid1(1);
when x"3C"+x"07" => s_DIO <= s_grid1(2);
when x"3C"+x"0A" => s_DIO <= s_grid1(3);
when x"3C"+x"0D" => s_DIO <= s_grid1(4);
when x"3C"+x"10" => s_DIO <= s_grid1(5);
when x"3C"+x"13" => s_DIO <= s_grid1(6);
when x"3C"+x"16" => s_DIO <= s_grid1(7);
when x"3C"+x"19" => s_DIO <= '0';
when others =>
end case;
-- DATA 2
case s_counter is
when x"57"+x"01" => s_DIO <= s_grid2(0);
when x"57"+x"04" => s_DIO <= s_grid2(1);
when x"57"+x"07" => s_DIO <= s_grid2(2);
when x"57"+x"0A" => s_DIO <= s_grid2(3);
when x"57"+x"0D" => s_DIO <= s_grid2(4);
when x"57"+x"10" => s_DIO <= s_grid2(5);
when x"57"+x"13" => s_DIO <= s_grid2(6);
when x"57"+x"16" => s_DIO <= s_grid2(7);
when x"57"+x"19" => s_DIO <= '0';
when others =>
end case;
-- DATA 3
case s_counter is
when x"72"+x"01" => s_DIO <= s_grid3(0);
when x"72"+x"04" => s_DIO <= s_grid3(1);
when x"72"+x"07" => s_DIO <= s_grid3(2);
when x"72"+x"0A" => s_DIO <= s_grid3(3);
when x"72"+x"0D" => s_DIO <= s_grid3(4);
when x"72"+x"10" => s_DIO <= s_grid3(5);
when x"72"+x"13" => s_DIO <= s_grid3(6);
when x"72"+x"16" => s_DIO <= s_grid3(7);
when x"72"+x"19" => s_DIO <= '0';
when others =>
end case;
-- DATA 4
case s_counter is
when x"8D"+x"01" => s_DIO <= s_grid4(0);
when x"8D"+x"04" => s_DIO <= s_grid4(1);
when x"8D"+x"07" => s_DIO <= s_grid4(2);
when x"8D"+x"0A" => s_DIO <= s_grid4(3);
when x"8D"+x"0D" => s_DIO <= s_grid4(4);
when x"8D"+x"10" => s_DIO <= s_grid4(5);
when x"8D"+x"13" => s_DIO <= s_grid4(6);
when x"8D"+x"16" => s_DIO <= s_grid4(7);
when x"8D"+x"19" => s_DIO <= '0';
when others =>
end case;
elsif (s_counter = x"AB") then
-- END
s_DIO <= '1';
elsif (s_counter = x"AC") then
-- START
s_DIO <= '0';
elsif (s_counter >= x"AD") and (s_counter < x"CB") then
-- COMMAND 3
case s_counter is
when x"AD"+x"01" => s_DIO <= g_command3(0);
when x"AD"+x"04" => s_DIO <= g_command3(1);
when x"AD"+x"07" => s_DIO <= g_command3(2);
when x"AD"+x"0A" => s_DIO <= g_command3(3);
when x"AD"+x"0D" => s_DIO <= g_command3(4);
when x"AD"+x"10" => s_DIO <= g_command3(5);
when x"AD"+x"13" => s_DIO <= g_command3(6);
when x"AD"+x"16" => s_DIO <= g_command3(7);
when x"AD"+x"19" => s_DIO <= '0';
when others =>
end case;
else -- s_counter = CB aka length of sequence - 1
-- END
s_DIO <= '1';
end if;
end if;
end if;
end process p_create_command;
--------------------------------------------------------------------------
-- p_update:
-- Assigns the value of current time (s_cur_time) to output current_time_o
-- (this warrants a delay of 1 clock cycle from input to output)
--------------------------------------------------------------------------
p_update : process (clk_i)
begin
if rising_edge(clk_i) then -- Rising clock edge
if srst_n_i = '0' then
CLK_o <= '1';
DIO_o <= '1';
else
CLK_o <= s_CLK;
DIO_o <= s_DIO;
end if;
end if;
end process p_update;
end architecture Behavioral;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPRND.VHD ***
--*** ***
--*** Function: FP Exponent Output Block - ***
--*** Rounded ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_exprnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END fp_exprnd;
ARCHITECTURE rtl OF fp_exprnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal rangeerrorff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
rangeerrorff <= '0';
overflowff <= "00";
underflowff <= "00";
manoverflowbitff <= '0';
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
rangeerrorff <= rangeerror;
overflowff(1) <= overflownode;
overflowff(2) <= overflowff(1);
underflowff(1) <= underflownode;
underflowff(2) <= underflowff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1));
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaexp(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- '1' if infinity
-- zero if exponent == 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth+1) OR rangeerrorff;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= overflowff(2);
underflowout <= underflowff(2);
END rtl;
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-05-31 14:53:37-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.10 2007-05-31 14:53:37-04 l435385 Exp $
--
-- Created for VHDL-200X par, <NAME> (<EMAIL>)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREADnew [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREADnew [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREADnew [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREADnew [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREADnew;
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREADnew;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREADnew (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREADnew;
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREADnew (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREADnew;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
<reponame>slaclab/cryo-wib-firmware
-- pdts_tstamp
--
-- Maintains the timestamp and event counters
--
-- <NAME>, March 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.pdts_defs.all;
entity pdts_tstamp is
port(
clk: in std_logic;
rst: in std_logic;
d: in std_logic_vector(7 downto 0);
s_valid: in std_logic;
s_first: in std_logic;
tstamp: out std_logic_vector(8 * TSTAMP_WDS - 1 downto 0);
evtctr: out std_logic_vector(8 * EVTCTR_WDS - 1 downto 0);
rdy: out std_logic
);
end pdts_tstamp;
architecture rtl of pdts_tstamp is
signal sr: std_logic_vector(8 * (TSTAMP_WDS + EVTCTR_WDS) - 1 downto 0);
signal tstamp_i: unsigned(8 * TSTAMP_WDS - 1 downto 0);
signal evtctr_i: unsigned(8 * EVTCTR_WDS - 1 downto 0);
signal ctr: unsigned(7 downto 0);
signal lock, init, pkt_end, pkt_end_d: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
ctr <= (others => '0');
elsif (s_valid = '1' and s_first = '1' and d(SCMD_W - 1 downto 0) = std_logic_vector(to_unsigned(SCMD_SYNC, SCMD_W))) or ctr /= to_unsigned(0, ctr'length) then
ctr <= ctr + 1;
if ctr < (TSTAMP_WDS + EVTCTR_WDS + 1) * (10 / SCLK_RATIO) and s_valid = '1' then
sr <= d & sr(8 * (TSTAMP_WDS + EVTCTR_WDS) - 1 downto 8);
end if;
end if;
pkt_end <= and_reduce(std_logic_vector(ctr));
pkt_end_d <= pkt_end;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
tstamp_i <= (others => '0');
evtctr_i <= (others => '0');
lock <= '0';
init <= '0';
else
if pkt_end = '1' then
evtctr_i <= unsigned(sr(8 * (TSTAMP_WDS + EVTCTR_WDS) - 1 downto 8 * TSTAMP_WDS));
elsif s_valid = '1' and EVTCTR_MASK(to_integer(unsigned(d(3 downto 0)))) = '1' then
evtctr_i <= evtctr_i + 1;
end if;
if lock = '0' and init = '0' then
if pkt_end = '1' then
tstamp_i <= unsigned(sr(8 * TSTAMP_WDS - 1 downto 9) & '1' & X"01");
lock <= '1';
init <= '1';
end if;
else
tstamp_i <= tstamp_i + 1;
if pkt_end_d = '1' and tstamp_i /= unsigned(sr(8 * TSTAMP_WDS - 1 downto 9) & '1' & X"01") then
lock <= '0';
end if;
end if;
end if;
end if;
end process;
tstamp <= std_logic_vector(tstamp_i);
evtctr <= std_logic_vector(evtctr_i);
rdy <= lock;
end rtl;
|
<reponame>navrajkambo/De1-SoC-Verilog-Audio-Loopback
component AudioPLL is
port (
ref_clk_clk : in std_logic := 'X'; -- clk
ref_reset_reset : in std_logic := 'X'; -- reset
audio_clk_clk : out std_logic; -- clk
reset_source_reset : out std_logic -- reset
);
end component AudioPLL;
u0 : component AudioPLL
port map (
ref_clk_clk => CONNECTED_TO_ref_clk_clk, -- ref_clk.clk
ref_reset_reset => CONNECTED_TO_ref_reset_reset, -- ref_reset.reset
audio_clk_clk => CONNECTED_TO_audio_clk_clk, -- audio_clk.clk
reset_source_reset => CONNECTED_TO_reset_source_reset -- reset_source.reset
);
|
<gh_stars>1-10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity Nexys4 is
port (
-- les switchs
swt : in std_logic_vector (8 downto 0);
-- le reset
btnC : std_logic;
-- les anodes pour sélectionner l'afficheur 7 segments
an : out std_logic_vector (7 downto 0);
-- afficheur 7 segments (point décimal compris, segment 7)
ssg : out std_logic_vector (7 downto 0);
-- horloge
mclk : in std_logic
);
end Nexys4;
architecture synthesis of Nexys4 is
-- rappel du (des) composant(s)
component all7segments
port(
clk : in std_logic;
reset : in std_logic;
e0 : in std_logic_vector(3 downto 0);
e1 : in std_logic_vector(3 downto 0);
e2 : in std_logic_vector(3 downto 0);
e3 : in std_logic_vector(3 downto 0);
e4 : in std_logic_vector(3 downto 0);
e5 : in std_logic_vector(3 downto 0);
e6 : in std_logic_vector(3 downto 0);
e7 : in std_logic_vector(3 downto 0);
an : out std_logic_vector(7 downto 0);
ssg : out std_logic_vector(7 downto 0)
);
end component;
component additionneur4bits
port(
input1 : in std_logic_vector(3 downto 0);
input2 : in std_logic_vector(3 downto 0);
carry_in : in std_logic;
sum : out std_logic_vector(3 downto 0);
carry_out : out std_logic
);
end component;
signal carry_in, carry_out : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(3 downto 0);
signal carry : std_logic;
signal reset : std_logic;
begin
-- valeurs des sorties (à modifier)
carry_in <= "000"&swt(8);
carry_out <= "000"&carry;
reset <= not btnC;
-- connexion du (des) composant(s) avec les ports de la carte
Inst_All7Segments: All7Segments port map(
clk => mclk,
reset => reset,
e0 => swt(3 downto 0),
e1 => swt(7 downto 4),
e2 => carry_in,
e3 => "0000",
e4 => sum,
e5 => carry_out,
e6 => "0000",
e7 => "0000",
an => an,
ssg => ssg
);
Inst_additionneur4bits: additionneur4bits PORT MAP(
input1 => swt(3 downto 0),
input2 => swt(7 downto 4),
carry_in => swt(8),
sum => sum,
carry_out => carry
);
end synthesis;
|
<reponame>Klagarge/ELN_CURSOR_JCHE_THJCT
library Common;
use Common.CommonLib.all;
ARCHITECTURE RTL OF lcdSerializer IS
------------------------------------------------------------------------------
-- The clock-pulse rate of the SCL line can be up to 20 MHz @3.3V
-- The clock frequency is divided by generic value "baudRateDivide"
-- The corresponding "sclEn" is further divided by 2 to generate SCL
--
signal sclCounter: unsigned(requiredBitNb(baudRateDivide-1)-1 downto 0);
signal sclEn: std_ulogic;
signal scl_int: std_ulogic;
------------------------------------------------------------------------------
-- The minimal reset pulse width is 1 us
-- "sclEn" at 40 MHz has to be divided by 40 to generate the 1 us delay
--
constant resetCount : natural := 40;
signal resetCounter: unsigned(requiredBitNb(2*resetCount-1)-1 downto 0);
signal resetDone: std_ulogic;
------------------------------------------------------------------------------
-- Serial data bits have to be stable at the rising edge of SCL
-- Data bits will be updated at the falling edge of SCL
--
-- Data in comprises 9 bits: A0 (as MSB) and 8 row pixels or command bits
-- A0 selects between command data (A0 = 0) and pixel data (A0 = 1)
--
constant pixelsPerColumn : positive := data'length-1;
signal dataSampled : std_ulogic_vector(data'range);
signal chipSelect : std_ulogic;
signal updateData: std_ulogic;
signal dataCounter: unsigned(requiredBitNb(pixelsPerColumn+1)-1 downto 0);
BEGIN
------------------------------------------------------------------------------
-- clock divider for SCL
divideClock: process(reset, clock)
begin
if reset='1' then
scl_int <= '0';
sclCounter <= (others => '0');
elsif rising_edge(clock) then
if sclEn = '1' then
sclCounter <= (others => '0');
scl_int <= not scl_int;
else
sclCounter <= sclCounter + 1;
end if;
end if;
end process divideClock;
sclEn <= '1' when sclCounter = baudRateDivide-1
else '0';
------------------------------------------------------------------------------
-- LCD reset
process(clock,reset)
variable i : natural;
begin
if reset = '1' then
resetCounter <= (others => '0');
elsif rising_edge(clock) then
if sclEn = '1' then
if resetDone = '0' then
resetCounter <= resetCounter + 1;
end if;
end if;
end if;
end process;
resetDone <= '1' when resetCounter >= 2*resetCount-1
else '0';
RST_n <= '1' when resetCounter >= resetCount-1
else '0';
------------------------------------------------------------------------------
-- sample input data
process (reset, clock)
begin
if reset = '1' then
dataSampled <= (others => '0');
elsif rising_edge(clock) then
if send = '1' then
dataSampled <= data;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- A0
A0 <= dataSampled(data'high);
------------------------------------------------------------------------------
-- serialize data
updateData <= sclEn and scl_int;
process (reset, clock)
begin
if reset = '1' then
dataCounter <= (others => '0');
elsif rising_edge(clock) then
if resetDone = '1' then
if dataCounter = 0 then
if send = '1' then
dataCounter <= to_unsigned(pixelsPerColumn+1, dataCounter'length);
end if;
else
if updateData = '1' then
dataCounter <= dataCounter - 1;
end if;
end if;
end if;
end if;
end process;
busy <= '1' when (resetDone = '0') or (dataCounter > 0)
else '0';
chipSelect <= '1' when (dataCounter > 0) and (dataCounter < pixelsPerColumn+1)
else '0';
sampleData: process (reset, clock)
begin
if reset = '1' then
CS_n <= '1';
SCL <= '1';
SI <= '1';
elsif rising_edge(clock) then
if chipSelect = '1' then
CS_n <= '0';
SCL <= scl_int or not(chipSelect);
SI <= dataSampled(to_integer(dataCounter-1));
else
CS_n <= '1';
SCL <= '1';
SI <= '1';
end if;
end if;
end process sampleData;
END ARCHITECTURE RTL;
|
<reponame>lsst-camera-daq/surf
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: This module measures the trigger rate of a trigger
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library surf;
use surf.StdRtlPkg.all;
entity SyncTrigRate is
generic (
TPD_G : time := 1 ns; -- Simulation FF output delay
COMMON_CLK_G : boolean := false; -- true if locClk & refClk are the same clock
ONE_SHOT_G : boolean := false;
IN_POLARITY_G : sl := '1'; -- 0 for active LOW, 1 for active HIGH
COUNT_EDGES_G : boolean := false; -- Count edges or high time
REF_CLK_FREQ_G : real := 200.0E+6; -- units of Hz
REFRESH_RATE_G : real := 1.0E+0; -- units of Hz
CNT_WIDTH_G : positive := 32); -- Counters' width
port (
-- Trigger Input (locClk domain)
trigIn : in sl;
-- Trigger Rate Output (locClk domain)
trigRateUpdated : out sl;
trigRateOut : out slv(CNT_WIDTH_G-1 downto 0); -- units of REFRESH_RATE_G
trigRateOutMax : out slv(CNT_WIDTH_G-1 downto 0); -- units of REFRESH_RATE_G
trigRateOutMin : out slv(CNT_WIDTH_G-1 downto 0); -- units of REFRESH_RATE_G
-- Clocks
locClkEn : in sl := '1';
locClk : in sl;
locRst : in sl := '0';
refClk : in sl;
refRst : in sl := '0');
end SyncTrigRate;
architecture rtl of SyncTrigRate is
constant TIMEOUT_C : natural := getTimeRatio(REF_CLK_FREQ_G, REFRESH_RATE_G)-1;
type RegType is record
updated : sl;
timer : natural range 0 to TIMEOUT_C;
trigCntDly : slv(CNT_WIDTH_G-1 downto 0);
rate : slv(CNT_WIDTH_G-1 downto 0);
end record;
constant REG_INIT_C : RegType := (
updated => '0',
timer => 0,
trigCntDly => (others => '0'),
rate => (others => '0'));
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal trig : sl := not(IN_POLARITY_G);
signal trigLast : sl := not IN_POLARITY_G;
signal updated : sl := '0';
signal trigCnt : slv(CNT_WIDTH_G-1 downto 0) := (others => '0');
signal trigCntSync : slv(CNT_WIDTH_G-1 downto 0) := (others => '0');
signal rstStat : sl;
begin
BYPASS_ONE_SHOT : if (ONE_SHOT_G = false) generate
trig <= trigIn;
end generate;
GEN_ONE_SHOT : if (ONE_SHOT_G = true) generate
U_OneShot : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G,
IN_POLARITY_G => IN_POLARITY_G,
OUT_POLARITY_G => IN_POLARITY_G)
port map (
clk => locClk,
dataIn => trigIn,
dataOut => trig);
end generate;
process (locClk) is
begin
if rising_edge(locClk) then
-- Check the clock enable
if (locClkEn = '1') or (ONE_SHOT_G = true) then
trigLast <= trig after TPD_G;
-- Check for a trigger
if (COUNT_EDGES_G = false and trig = IN_POLARITY_G) or
(COUNT_EDGES_G and trig = IN_POLARITY_G and trigLast = not (IN_POLARITY_G)) then
-- Increment the counter
trigCnt <= trigCnt + 1 after TPD_G;
end if;
end if;
end if;
end process;
SyncIn_trigCnt : entity surf.SynchronizerFifo
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => COMMON_CLK_G,
DATA_WIDTH_G => CNT_WIDTH_G)
port map (
wr_clk => locClk,
din => trigCnt,
rd_clk => refClk,
dout => trigCntSync);
comb : process (r, trigCntSync) is
variable v : RegType;
begin
-- Latch the current value
v := r;
-- Reset strobing signals
v.updated := '0';
-- Check for timeout
if r.timer = TIMEOUT_C then
-- Reset the timer
v.timer := 0;
-- Update the rate measurement
v.updated := '1';
v.rate := trigCntSync - r.trigCntDly;
-- Keep a delayed copy of trigCntSync
v.trigCntDly := trigCntSync;
else
-- Increment the timer
v.timer := r.timer + 1;
end if;
-- Register the variable for next clock cycle
rin <= v;
end process comb;
seq : process (refClk) is
begin
if rising_edge(refClk) then
r <= rin after TPD_G;
end if;
end process seq;
rstStat <= refRst or locRst;
U_Sync : entity surf.SyncMinMax
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => COMMON_CLK_G,
WIDTH_G => CNT_WIDTH_G)
port map (
-- ASYNC statistics reset
rstStat => rstStat,
-- Write Interface (wrClk domain)
wrClk => refClk,
wrEn => r.updated,
dataIn => r.rate,
-- Read Interface (rdClk domain)
rdClk => locClk,
updated => trigRateUpdated,
dataOut => trigRateOut,
dataMin => trigRateOutMin,
dataMax => trigRateOutMax);
end rtl;
|
--------------------------------------------------------------------------------------------------
-- Interpolator
--------------------------------------------------------------------------------------------------
-- <NAME> - <EMAIL>
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package interpolator_pkg is
component interpolator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_low : in sig;
sig_high : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.muxer_pkg.all;
use work.multichannel_fir_filter_pkg.all;
entity interpolator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_low : in sig;
sig_high : out sig);
end interpolator;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of interpolator is
constant H0 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 1, 1);
constant H1 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 2, 1);
signal filtered1 : fir_sig;
signal filtered2 : fir_sig;
signal combined : fir_sig;
begin
--Low pass the input signal using the multichannel approach
low_pass : multichannel_fir_filter
generic map(h0 => H0,
h1 => H1,
INIT_SEL => b"10")
port map( clk => clk_low,
clk_2x => clk_high,
rst => rst,
x1 => sig_low,
x2 => sig_low,
y1 => filtered1,
y2 => filtered2);
--Mux the poly-phase filter results into one signal
--NOTE: If this design were to ever support interpolation factor > 2, the mux would need to
--select the input signals in descending order
mux_sigs : muxer
generic map(INIT_SEL => std_logic_vector(rotate_left(unsigned'(b"01"), h'length)))
port map(clk => clk_low,
clk_2x => clk_high,
rst => rst,
sig1 => std_logic_vector(filtered1),
sig2 => std_logic_vector(filtered2),
fir_sig(sigs) => combined);
sig_high <= combined(30 downto 15);
end behave;
|
component adc is
port (
adc_pll_clock_clk : in std_logic := 'X'; -- clk
adc_pll_locked_export : in std_logic := 'X'; -- export
clock_clk : in std_logic := 'X'; -- clk
command_valid : in std_logic := 'X'; -- valid
command_channel : in std_logic_vector(4 downto 0) := (others => 'X'); -- channel
command_startofpacket : in std_logic := 'X'; -- startofpacket
command_endofpacket : in std_logic := 'X'; -- endofpacket
command_ready : out std_logic; -- ready
reset_sink_reset_n : in std_logic := 'X'; -- reset_n
response_valid : out std_logic; -- valid
response_channel : out std_logic_vector(4 downto 0); -- channel
response_data : out std_logic_vector(11 downto 0); -- data
response_startofpacket : out std_logic; -- startofpacket
response_endofpacket : out std_logic -- endofpacket
);
end component adc;
u0 : component adc
port map (
adc_pll_clock_clk => CONNECTED_TO_adc_pll_clock_clk, -- adc_pll_clock.clk
adc_pll_locked_export => CONNECTED_TO_adc_pll_locked_export, -- adc_pll_locked.export
clock_clk => CONNECTED_TO_clock_clk, -- clock.clk
command_valid => CONNECTED_TO_command_valid, -- command.valid
command_channel => CONNECTED_TO_command_channel, -- .channel
command_startofpacket => CONNECTED_TO_command_startofpacket, -- .startofpacket
command_endofpacket => CONNECTED_TO_command_endofpacket, -- .endofpacket
command_ready => CONNECTED_TO_command_ready, -- .ready
reset_sink_reset_n => CONNECTED_TO_reset_sink_reset_n, -- reset_sink.reset_n
response_valid => CONNECTED_TO_response_valid, -- response.valid
response_channel => CONNECTED_TO_response_channel, -- .channel
response_data => CONNECTED_TO_response_data, -- .data
response_startofpacket => CONNECTED_TO_response_startofpacket, -- .startofpacket
response_endofpacket => CONNECTED_TO_response_endofpacket -- .endofpacket
);
|
<gh_stars>1-10
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
-- Date : Fri Jun 25 18:49:31 2021
-- Host : DESKTOP-BJG36E9 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xilinx_transfer_function_1_mult_gen_v12_0_i1_sim_netlist.vhdl
-- Design : xilinx_transfer_function_1_mult_gen_v12_0_i1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
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<KEY>
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
A : in STD_LOGIC_VECTOR ( 63 downto 0 );
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
P : out STD_LOGIC_VECTOR ( 95 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "xilinx_transfer_function_1_mult_gen_v12_0_i1,mult_gen_v12_0_17,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_17,Vivado 2021.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 64;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 32;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 1;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of U0 : label is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 95;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of U0 : label is "soft";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of U0 : label is "true";
attribute x_interface_info : string;
attribute x_interface_info of A : signal is "xilinx.com:signal:data:1.0 a_intf DATA";
attribute x_interface_parameter : string;
attribute x_interface_parameter of A : signal is "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
attribute x_interface_info of B : signal is "xilinx.com:signal:data:1.0 b_intf DATA";
attribute x_interface_parameter of B : signal is "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef";
attribute x_interface_info of P : signal is "xilinx.com:signal:data:1.0 p_intf DATA";
attribute x_interface_parameter of P : signal is "XIL_INTERFACENAME p_intf, LAYERED_METADATA undef";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_17
port map (
A(63 downto 0) => A(63 downto 0),
B(31 downto 0) => B(31 downto 0),
CE => '1',
CLK => '1',
P(95 downto 0) => P(95 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- PandA Motion Project - 2016
-- Diamond Light Source, Oxford, UK
-- SOLEIL Synchrotron, GIF-sur-YVETTE, France
--
-- Author : Dr. <NAME> (<EMAIL>)
--------------------------------------------------------------------------------
--
-- Description : Long table based position generation module.
-- 32-bit data in and out interface.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.support.all;
entity pgen is
generic (
AXI_BURST_LEN : integer := 256;
DW : natural := 32 -- Output Data Width
);
port (
-- Clock and Reset
clk_i : in std_logic;
-- Block Input and Outputs
enable_i : in std_logic;
trig_i : in std_logic;
out_o : out std_logic_vector(DW-1 downto 0);
-- Block Parameters
REPEATS : in std_logic_vector(31 downto 0);
ACTIVE_o : out std_logic;
TABLE_ADDRESS : in std_logic_vector(31 downto 0);
TABLE_ADDRESS_WSTB : in std_logic;
TABLE_LENGTH : in std_logic_vector(31 downto 0);
TABLE_LENGTH_WSTB : in std_logic;
health : out std_logic_vector(31 downto 0) := (others => '0');
-- DMA Engine Interface
dma_req_o : out std_logic;
dma_ack_i : in std_logic;
dma_done_i : in std_logic;
dma_addr_o : out std_logic_vector(31 downto 0);
dma_len_o : out std_logic_vector(7 downto 0);
dma_data_i : in std_logic_vector(31 downto 0);
dma_valid_i : in std_logic
);
end pgen;
architecture rtl of pgen is
component fifo_1K32
port (
clk : in std_logic;
srst : in std_logic;
din : in std_logic_vector(31 DOWNTO 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 DOWNTO 0);
full : out std_logic;
empty : out std_logic;
data_count : out std_logic_vector(9 downto 0)
);
end component;
type state_t is (IDLE, WAIT_FIFO, DMA_REQ, DMA_READ, IS_FINISHED, FINISHED);
signal pgen_fsm : state_t;
signal reset : std_logic;
signal TABLE_WORDS : unsigned(31 downto 0);
signal table_cycle : unsigned(31 downto 0);
signal table_ready : std_logic := '0';
signal fifo_reset : std_logic;
signal fifo_rd_en : std_logic;
signal fifo_dout : std_logic_vector(DW-1 downto 0);
signal fifo_count : integer range 0 to 1023;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_data_count : std_logic_vector(9 downto 0);
signal fifo_available : std_logic;
signal trig : std_logic;
signal enable : std_logic;
signal trig_pulse : std_logic;
signal enable_fall : std_logic;
signal count : unsigned(31 downto 0);
signal dma_len : unsigned(8 downto 0);
signal dma_addr : unsigned(31 downto 0);
signal dma_underrun : std_logic;
signal table_end : std_logic;
signal active : std_logic := '0';
begin
-- Assign outputs
dma_len_o <= std_logic_vector(dma_len(7 downto 0));
dma_addr_o <= std_logic_vector(dma_addr);
out_o <= fifo_dout;
-- Reset for state machine
reset <= not table_ready or enable_fall;
--
-- 32bit FIFO with 1K sample depth
--
dma_fifo_inst : fifo_1K32
port map (
srst => fifo_reset,
clk => clk_i,
din => dma_data_i,
wr_en => dma_valid_i,
rd_en => fifo_rd_en,
dout => fifo_dout,
full => fifo_full,
empty => fifo_empty,
data_count => fifo_data_count
);
fifo_reset <= reset;
fifo_rd_en <= trig_pulse;
fifo_count <= to_integer(unsigned(fifo_data_count));
-- There is space (>256 words) in the fifo, so perform data read from
-- host memory.
fifo_available <= '1' when (fifo_count < 768) else '0';
--
-- Input registers
--
process(clk_i) begin
if rising_edge(clk_i) then
trig <= trig_i;
enable <= enable_i;
end if;
end process;
-- Trigger pulse pops data from fifo and tick data counter when block
-- is enabled and table is ready.
trig_pulse <= (trig_i and not trig) and active and table_ready;
enable_fall <= not enable_i and enable;
--
-- Table ready controls state machine reset. The table is un-validated once
-- LENGTH=0 written.
--
TABLE_WORDS <= unsigned(TABLE_LENGTH) srl 2; -- Byte -> Dword
process(clk_i) begin
if rising_edge(clk_i) then
if (TABLE_LENGTH_WSTB = '1') then
if (TABLE_WORDS = 0) then
table_ready <= '0';
elsif (TABLE_WORDS /= 0) then
table_ready <= '1';
end if;
end if;
end if;
end process;
process(clk_i) begin
if rising_edge(clk_i) then
if (reset = '1') then
dma_req_o <= '0';
count <= (others => '0');
dma_addr <= (others => '0');
dma_len <= (others => '0');
table_cycle <= (others => '0');
pgen_fsm <= IDLE;
else
case pgen_fsm is
when IDLE =>
-- Wait following fifo reset by monitoring full flag.
if (fifo_full = '0') then
table_cycle <= table_cycle + 1;
count <= TABLE_WORDS;
dma_addr <= unsigned(TABLE_ADDRESS);
pgen_fsm <= WAIT_FIFO;
end if;
-- Wait until enough space available in the fifo.
when WAIT_FIFO =>
if (fifo_available = '1') then
dma_req_o <= '1';
pgen_fsm <= DMA_REQ;
-- Determine dma length in samples.
if (count < AXI_BURST_LEN) then
dma_len <= count(8 downto 0);
else
dma_len <= to_unsigned(AXI_BURST_LEN, dma_len'length);
end if;
end if;
when DMA_REQ =>
if (dma_ack_i = '1') then
dma_req_o <= '0';
pgen_fsm <= DMA_READ;
end if;
when DMA_READ =>
-- Wait until DMA completes, and keep track of total count.
if (dma_done_i = '1') then
count <= count - dma_len;
dma_addr <= dma_addr + dma_len * 4;
pgen_fsm <= IS_FINISHED;
end if;
when IS_FINISHED =>
-- Is table finished?
if (count = 0) then
-- Are there more table REPEATS?
if (table_cycle = unsigned(REPEATS)) then
pgen_fsm <= FINISHED;
else
count <= TABLE_WORDS;
dma_addr <= unsigned(TABLE_ADDRESS);
pgen_fsm <= WAIT_FIFO;
table_cycle <= table_cycle + 1;
end if;
else
pgen_fsm <= WAIT_FIFO;
end if;
-- Wait for re-enable to start over.
when FINISHED =>
dma_req_o <= '0';
count <= (others => '0');
dma_addr <= (others => '0');
dma_len <= (others => '0');
end case;
end if;
end if;
end process;
--
-- Error detection, and reporting.
--
process(clk_i) begin
if rising_edge(clk_i) then
if (reset = '1') then
dma_underrun <= '0';
table_end <= '0';
health <= (others => '0');
else
-- Detect Table End reached once in operation.
if (pgen_fsm = FINISHED and fifo_empty = '1' and trig_pulse = '1') then
table_end <= '1';
end if;
-- Detect DMA underrun, and stop operation.
if (trig_pulse = '1' and fifo_empty = '1') then
dma_underrun <= '1';
end if;
-- Assign HEALTH output as Enum.
if (table_ready = '0') then
health(1 downto 0) <= TO_SVECTOR(1,2);
elsif (dma_underrun = '1') then
health(1 downto 0) <= TO_SVECTOR(3,2);
else
health(1 downto 0) <= (others => '0');
end if;
end if;
end if;
end process;
active <= enable and not fifo_empty;
ACTIVE_o <= active;
end rtl;
|
<filename>lab3/src/Task2/TestBench/rs_latch_param_TB.vhd<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
entity rs_latch_param_tb is
end rs_latch_param_tb;
architecture TB_ARCHITECTURE of rs_latch_param_tb is
component rs_latch_param
port(
R : in STD_LOGIC;
S : in STD_LOGIC;
Q : out STD_LOGIC;
nQ : out STD_LOGIC );
end component;
signal R : STD_LOGIC;
signal S : STD_LOGIC;
signal Q_struct : STD_LOGIC;
signal nQ_struct : STD_LOGIC;
signal Q_beh : STD_LOGIC;
signal nQ_beh : STD_LOGIC;
signal Q2_struct : STD_LOGIC;
signal nQ2_struct : STD_LOGIC;
signal Q2_beh : STD_LOGIC;
signal nQ2_beh : STD_LOGIC;
begin
UUT : entity rs_latch_param(Struct)
port map (
R => R,
S => S,
Q => Q_struct,
nQ => nQ_struct
);
UUT2 : entity rs_latch(beh)
port map (
R => R,
S => S,
Q => Q_beh,
nQ => nQ_beh
);
UUT3 : entity rs_latch(Struct)
port map (
R => R,
S => S,
Q => Q2_struct,
nQ => nQ2_struct
);
UUT4 : entity rs_latch(beh)
port map (
R => R,
S => S,
Q => Q2_beh,
nQ => nQ2_beh
);
Simulate: process
begin
R <= '0';
S <= '0';
wait for 10 ns;
R <= '1';
S <= '0';
wait for 10 ns;
R <= '0';
S <= '0';
wait for 10 ns;
R <= '0';
S <= '1';
wait for 10 ns;
R <= '0';
S <= '0';
wait for 10 ns;
R <= '1';
S <= '1';
wait for 10 ns;
R <= '0';
S <= '0';
wait for 10 ns;
end process;
end TB_ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
package if_pkg is
-- The CPU will vector to this address
-- when an IRQ is asserted and the pipeline
-- is in a safe place to do so.
constant IRQ_VECTOR_ADDRESS : word := X"00000200";
-- inputs to Instruction Fetch stage
type if_in is record
insn : word;
load_pc : std_logic;
next_pc : word;
stall : std_logic;
irq : std_logic;
end record if_in;
-- outputs from Instruction Fetch stage
type if_out is record
fetch_addr : word;
pc : word;
end record if_out;
end package if_pkg;
|
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity System_tb is
end;
architecture bench of System_tb is
component System
generic (
CLK_FREQUENCY : integer := 100000000;
BAUD_RATE : integer := 9600;
CENTERING : integer := 16
);
port (
input : in std_logic_vector (0 to 7);
write : in std_logic;
data_trasmitted: out std_logic;
clk, rst : in std_logic;
data_out : out std_logic_vector (15 downto 0);
crc_ok : out std_logic;
new_data : out std_logic:='0';
oe, pe, fe, rda : out std_logic
);
end component;
signal input: std_logic_vector (0 to 7);
signal write: std_logic;
signal data_trasmitted: std_logic;
signal clk:std_logic;
signal rst: std_logic:='0';
signal data_out: std_logic_vector (15 downto 0);
signal crc_ok: std_logic;
signal new_data: std_logic:='0';
signal oe, pe, fe, rda: std_logic ;
constant CLK_FREQUENCY : integer := 100000000;
constant BAUD_RATE : integer := 9600;
constant CENTERING : integer := 16;
constant clk_period : time := 10 ns;
begin
-- Insert values for generic parameters !!
uut: System generic map ( CLK_FREQUENCY => CLK_FREQUENCY,
BAUD_RATE => BAUD_RATE,
CENTERING => CENTERING )
port map ( input => input,
write => write,
data_trasmitted => data_trasmitted,
clk => clk,
rst => rst,
data_out => data_out,
crc_ok => crc_ok,
new_data => new_data,
oe => oe,
pe => pe,
fe => fe,
rda => rda );
stimulus: process
begin
input <= "10100100";
wait for clk_period;
write <= '1';
wait;
end process;
CLK_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
end;
|
<filename>firmware/targets/XilinxZcu102/shared/tb/SmaTxClkoutTb.vhd<gh_stars>0
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: Simulation Testbed for testing the SmaTxClkout module
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
entity SmaTxClkoutTb is end SmaTxClkoutTb;
architecture testbed of SmaTxClkoutTb is
constant CLK_PERIOD_G : time := 6.4 ns; -- 6.4 = 1/156.25 MHz
constant TPD_G : time := CLK_PERIOD_G/4;
signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C;
signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C;
signal axilClk : sl := '0';
signal axilRst : sl := '1';
signal clk160MHz : sl := '0';
signal rst160MHz : sl := '1';
signal smaTxP : sl := '0';
signal smaTxN : sl := '1';
signal smaRxP : sl := '0';
signal smaRxN : sl := '1';
begin
--------------------
-- Clocks and Resets
--------------------
U_axilClk : entity surf.ClkRst
generic map (
CLK_PERIOD_G => CLK_PERIOD_G,
RST_START_DELAY_G => 0 ns,
RST_HOLD_TIME_G => 1000 ns)
port map (
clkP => axilClk,
rst => axilRst);
U_clk160MHz : entity surf.ClkRst
generic map (
CLK_PERIOD_G => 6.25 ns, -- 6.25 ns = 1/160 MHz
RST_START_DELAY_G => 0 ns,
RST_HOLD_TIME_G => 1000 ns)
port map (
clkP => clk160MHz,
rst => rst160MHz);
-----------------------
-- Module to be tested
-----------------------
U_SmaTxClkout : entity work.SmaTxClkout
generic map (
TPD_G => TPD_G)
port map (
-- AXI-Lite Interface (axilClk domain)
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => axilReadMaster,
axilReadSlave => axilReadSlave,
axilWriteMaster => axilWriteMaster,
axilWriteSlave => axilWriteSlave,
-- Clocks and Resets
gtRefClk => clk160MHz,
drpClk => clk160MHz,
drpRst => rst160MHz,
-- Broadcast External Timing Clock
smaTxP => smaTxP,
smaTxN => smaTxN,
smaRxP => smaRxP,
smaRxN => smaRxN);
end testbed;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity fir_filter_tb is
end entity fir_filter_tb;
architecture testbench of fir_filter_tb is
component fir_filter_symmetric_round is
generic (
N_INPUT : integer := 16;
N_COEF : integer := 16;
N_TRUNC : integer := 18;
N_OUTPUT : integer := 18+3;
M : integer := 6
);
port (
i_clk : in std_logic;
i_rst : in std_logic;
i_slave_axis_tdata : in std_logic_vector(N_INPUT-1 downto 0);
i_slave_axis_tvalid : in std_logic;
o_slave_axis_tready : out std_logic;
o_master_axis_tdata : out std_logic_vector(N_OUTPUT-1 downto 0);
o_master_axis_tvalid : out std_logic;
i_master_axis_tready : in std_logic
);
end component;
-- absolute paths
constant in_file : string := "/home/mbrignone/MAESTRIA/MSE/dsp/tp1_dsp_mse/ejercicio_4/vhdl/data/data_in_fny_0p8.txt";
constant out_file : string := "/home/mbrignone/MAESTRIA/MSE/dsp/tp1_dsp_mse/ejercicio_4/vhdl/data/data_out_fny_0p8_symmetric_round.txt";
constant values_to_save : integer := 200;
-- pointers for the files
file r_fptr, w_fptr : text;
constant N_INPUT : integer := 16;
constant N_COEF : integer := 16;
constant N_TRUNC : integer := 18;
constant N_OUTPUT : integer := N_TRUNC+3;
signal i_clk : std_logic;
signal i_rst : std_logic;
signal i_slave_axis_tdata : std_logic_vector(N_INPUT-1 downto 0);
signal i_slave_axis_tvalid : std_logic;
signal o_slave_axis_tready : std_logic;
signal o_master_axis_tdata : std_logic_vector(N_OUTPUT-1 downto 0);
signal o_master_axis_tvalid : std_logic;
signal i_master_axis_tready : std_logic;
constant C_CLK_PERIOD : real := 10.0e-9; -- nanoseconds
-- procedure to generate delays of M clock cycl
procedure generate_delay (
signal i_clk : in std_logic;
constant M_CYCLE : in integer
) is
begin
wait_ncycle : for i in 0 to M_CYCLE-1 loop
wait until rising_edge(i_clk);
end loop;
end procedure generate_delay;
begin
-----------------------------------------------------------
-- Clocks and Reset
-----------------------------------------------------------
CLK_GEN : process
begin
i_clk <= '1';
wait for C_CLK_PERIOD / 2.0 * (1 SEC);
i_clk <= '0';
wait for C_CLK_PERIOD / 2.0 * (1 SEC);
end process CLK_GEN;
RESET_GEN : process
begin
i_rst <= '1',
'0' after 20.0*C_CLK_PERIOD * (1 SEC);
wait;
end process RESET_GEN;
-----------------------------------------------------------
-- Testbench Stimulus
-----------------------------------------------------------
generate_stimulus : process is
variable fstatus : file_open_status;
variable file_line : line;
variable input_val : integer;
begin
file_open(fstatus, r_fptr, in_file, read_mode);
-- just accept all the data
i_master_axis_tready <= '1';
-- reset vaues for the input signals
i_slave_axis_tdata <= (others => '0');
i_slave_axis_tvalid <= '0';
wait until i_rst = '1';
generate_delay(i_clk, 10);
loop_file : while not endfile(r_fptr) loop
readline(r_fptr, file_line);
read(file_line, input_val);
report "Input value read from file: " & integer'image(input_val);
i_slave_axis_tdata <= std_logic_vector(to_signed(input_val, N_INPUT));
i_slave_axis_tvalid <= '1';
wait until (rising_edge(i_clk) and o_slave_axis_tready = '1');
i_slave_axis_tvalid <= '0';
generate_delay(i_clk, 20);
end loop;
report "Done reading input file";
file_close(r_fptr);
wait;
end process; -- generate_stimulus
p_write_file : process is
variable fstatus : file_open_status;
variable file_line : line;
variable v_int : integer;
variable v_std_lv : std_logic_vector((o_master_axis_tdata'LENGTH - 1) downto 0);
begin
file_open(fstatus, w_fptr, out_file, write_mode);
wait until (i_rst = '1');
write_file : for i in 0 to values_to_save loop
wait until (o_master_axis_tvalid = '1');
v_int := to_integer(signed(o_master_axis_tdata));
v_std_lv := o_master_axis_tdata;
write(file_line, v_int);
write(file_line, v_std_lv, right, 40);
writeline(w_fptr, file_line);
report "Written value: " & integer'image(v_int);
end loop;
report "Done writing output file";
file_close(w_fptr);
wait;
end process;
-----------------------------------------------------------
-- Entity Under Test
-----------------------------------------------------------
DUT : fir_filter_symmetric_round
generic map (
N_INPUT => N_INPUT,
N_COEF => N_COEF,
N_TRUNC => N_TRUNC,
N_OUTPUT => N_OUTPUT,
M => 6
)
port map (
i_clk => i_clk,
i_rst => i_rst,
i_slave_axis_tdata => i_slave_axis_tdata,
i_slave_axis_tvalid => i_slave_axis_tvalid,
o_slave_axis_tready => o_slave_axis_tready,
o_master_axis_tdata => o_master_axis_tdata,
o_master_axis_tvalid => o_master_axis_tvalid,
i_master_axis_tready => i_master_axis_tready
);
end architecture testbench;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity icache is
generic (
ADDRESS_HIGH: integer := 31
);
port (
syscon: in wb_syscon_type;
valid: out std_logic;
data: out std_logic_vector(31 downto 0);
address: in std_logic_vector(31 downto 0);
strobe: in std_logic;
enable: in std_logic;
seq: in std_logic;
stall: out std_logic;
flush: in std_logic;
abort: in std_logic;
tag: in std_logic_vector(31 downto 0);
tagen: in std_logic;
-- Master wishbone interface
mwbo: out wb_mosi_type;
mwbi: in wb_miso_type
);
end icache;
architecture behave of icache is
constant ADDRESS_LOW: integer := 0;
constant CACHE_MAX_BITS: integer := 13; -- 8 Kb
constant CACHE_LINE_SIZE_BITS: integer := 6; -- 64 bytes
constant CACHE_LINE_SIZE: integer := 2**CACHE_LINE_SIZE_BITS;
constant CACHE_LINE_ID_BITS: integer := CACHE_MAX_BITS-CACHE_LINE_SIZE_BITS;
-- memory max width: 19 bits (18 downto 0)
-- cache line size: 64 bytes
-- cache lines: 128
alias line: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0)
is address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
alias line_offset: std_logic_vector(CACHE_LINE_SIZE_BITS-1 downto 2)
is address(CACHE_LINE_SIZE_BITS-1 downto 2);
signal ctag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+1 downto 0);
signal miss: std_logic;
signal ack: std_logic;
type state_type is (
flushing,
running,
filling,
--waitwrite,
ending
);
constant offcnt_zero: unsigned(line_offset'HIGH downto 2) := (others => '0');
signal tag_match: std_logic;
signal cache_addr_read,cache_addr_write: std_logic_vector(CACHE_MAX_BITS-1 downto 2);
signal access_i: std_logic;
signal stall_i, valid_i: std_logic;
signal hit: std_logic;
signal tag_mem_enable: std_logic;
signal cache_mem_enable: std_logic;
signal exttag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
signal tag_mem_data: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+1 downto 0);
signal tag_mem_addr: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
constant dignore: std_logic_vector(ctag'RANGE) := (others => DontCareValue);
constant dignore32: std_logic_vector(31 downto 0) := (others => DontCareValue);
signal valid_while_filling: std_logic;
type icache_regs_type is record
cyc, stb: std_logic;
busy: std_logic;
state: state_type;
fill_success: std_logic;
flushcnt: unsigned(line'RANGE);
tag_mem_wen: std_logic;
wbaddr: std_logic_vector(31 downto CACHE_MAX_BITS);
offcnt: unsigned(line_offset'HIGH downto 2);
offcnt_write: unsigned(line_offset'HIGH downto 2);
stbcount: unsigned(line_offset'HIGH downto 2);
access_q: std_logic;
queued_address: std_logic;
save_addr: std_logic_vector(address'RANGE);
line_save: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
tag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
enable_q: std_logic;
iwfready: std_logic;
fault: std_logic;
flush: std_logic;
end record;
signal r: icache_regs_type;
alias tag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0)
is r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
alias address_tag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0)
is r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
signal ctag_address: std_logic_vector(address_tag'RANGE);
signal wrcachea: std_logic;
signal cmem_enable: std_logic;
signal cmem_wren: std_logic;
signal access_to_same_line: std_logic;
begin
ctag_address<=ctag(address_tag'HIGH downto address_tag'LOW);
tagmem: entity work.generic_dp_ram_1r1w
generic map (
address_bits => CACHE_LINE_ID_BITS,
data_bits => ADDRESS_HIGH-CACHE_MAX_BITS+2
)
port map (
clka => syscon.clk,
ena => tag_mem_enable,
addra => cache_addr_read(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS),--line,
doa => ctag,
clkb => syscon.clk,
enb => '1',
web => r.tag_mem_wen,
addrb => tag_mem_addr,
dib => tag_mem_data,
dob => open
);
cachemem: entity work.generic_dp_ram_1r1w
generic map (
address_bits => cache_addr_read'LENGTH,
data_bits => 32
)
port map (
clka => syscon.clk,
ena => cache_mem_enable,
addra => cache_addr_read,
doa => data,
clkb => syscon.clk,
enb => cmem_enable,
web => cmem_wren,
addrb => cache_addr_write,
dib => mwbi.dat,
dob => open
);
cmem_enable <= '1';
cmem_wren <= mwbi.ack;
valid_i <= ctag(ctag'HIGH);
process(r.state, r.flushcnt, tagen, exttag_save)
variable wrtag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
begin
if tagen='1' then
wrtag := exttag_save;
else
wrtag := tag_save;
end if;
if r.state=flushing then
tag_mem_data <= '0' & wrtag;
tag_mem_addr <= std_logic_vector(r.flushcnt);
else
tag_mem_data <= '1' & wrtag;
tag_mem_addr <= r.line_save;
end if;
end process;
process(ctag_address, address_tag, tag, tagen)
begin
if tagen='0' then
if ctag_address=address_tag then
tag_match<='1';
else
tag_match<='0';
end if;
else
if ctag_address=tag(ADDRESS_HIGH downto CACHE_MAX_BITS) then
tag_match<='1';
else
tag_match<='0';
end if;
end if;
end process;
cache_addr_write <= r.line_save & mwbi.tag(CACHE_LINE_SIZE_BITS-3 downto 0);
access_to_same_line<='1' when r.line_save = r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS) and
r.tag_save = r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS) else '0';
process(r,strobe,enable,miss,syscon,line,line_offset,hit,flush,mwbi,valid_while_filling,abort)
variable ett: std_logic_vector(exttag_save'RANGE);
variable w: icache_regs_type;
variable data_valid: std_logic;
variable stall_input: std_logic;
begin
w:=r;
w.busy := '0';
w.cyc := '0';
-- w.stb := 'X';
w.tag_mem_wen := '0';
w.fill_success :='0';
w.flushcnt := (others => 'X');
data_valid := '0';
tag_mem_enable <= enable and strobe;
cache_mem_enable <= enable and strobe;
cache_addr_read <= line & line_offset;
case r.state is
when flushing =>
w.busy := '1';
w.flushcnt := r.flushcnt - 1;
w.tag_mem_wen := '1';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.iwfready := '0';
stall_input := '1';
if r.flushcnt=0 then
w.tag_mem_wen:='0';
--w.state := running;
if r.queued_address='1' and r.fault='1' then
w.state := filling;
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.state := filling;
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.cyc := '1';
w.stb := '1';
w.busy := '1';
w.queued_address:='0';
w.line_save := r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
else
w.state := running;
end if;
end if;
when running =>
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.iwfready:='0';
stall_input := '0';
data_valid := hit;
w.stb := 'X';
if r.access_q='1' then
-- We had a cache access in last clock cycle.
if r.enable_q='1' then
if miss='1' and abort='0' then -- And it was a miss...
stall_input := '1';
data_valid := '0';
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.state := filling;
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.cyc := '1';
w.stb := '1';
w.busy := '1';
else
data_valid := '1';
end if;
end if;
end if;
if flush='1' then
w.state := flushing;
w.flushcnt := (others => '1');
w.tag_mem_wen := '1';
-- TODO: check if this is correct...
stall_input:='1';
end if;
w.queued_address := '0';
if r.access_q='1' and data_valid='0' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
w.fault := '0';
when filling =>
stall_input := '1';
w.busy:= '1';
w.cyc := '1';
tag_mem_enable <= '1';
cache_mem_enable <= enable and strobe;
if mwbi.ack='1' then
w.iwfready := enable;
w.offcnt_write := r.offcnt_write - 1;
-- This will go to 0, but we check before and switch state
if r.offcnt_write=offcnt_zero then
w.tag_mem_wen := '1';
w.state := ending;
end if;
end if;
if mwbi.stall='0' then
w.offcnt := r.offcnt + 1;
-- this needed ??
if r.stbcount/=offcnt_zero then
w.stbcount := w.stbcount - 1;
else
w.stb := '0';
end if;
end if;
if true then
if r.iwfready='0' then
cache_addr_read <= r.save_addr(CACHE_MAX_BITS-1 downto 2);
end if;
if enable='1' then
stall_input := not r.iwfready;
data_valid := r.iwfready;
if r.iwfready='1' and strobe='1' then
w.iwfready:='0';
end if;
if seq='0' and strobe='1' and stall_input='0' then
--stall_input := '1';
data_valid:='0';
w.fault :='1';
end if;
if r.access_q='1' and access_to_same_line='0' then
data_valid:='0';
stall_input:='1';
w.fault := '1';
end if;
end if;
if r.fault='1' then
stall_input:='1';
data_valid:='0';
end if;
if stall_input='0' then
if enable='1' and strobe='1' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
end if;
if flush='1' then
w.fault:='1';
data_valid:='0';
stall_input:='1';
w.flush:='1';
end if;
if stall_input='0' then
if enable='1' and strobe='1' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
end if;
if abort='1' then
w.fault:='1';
end if;
end if; -- IWF
when ending =>
w.busy :='0';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.stbcount := (others => 'X');
w.line_save:= (others => 'X');
w.tag_save:= (others => 'X');
w.iwfready:='0';
tag_mem_enable <= '1';
cache_mem_enable <='1';
cache_addr_read <= r.save_addr(CACHE_MAX_BITS-1 downto 2);
stall_input := '1';
w.fault:='0';
if enable='1' then
w.fill_success := '1';
end if;
if r.queued_address='1' then--and r.fault='1' then
w.state := filling;
w.cyc := '1';
w.stb := '1';
w.busy := '1';
w.queued_address:='0';
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.line_save := r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
else
w.state := running;
end if;
w.flush:='0';
if r.flush='1' then
w.state := flushing;
w.flushcnt := (others => '1');
w.tag_mem_wen := '1';
w.cyc :='0';
end if;
end case;
if strobe='1' and enable='1' then
if stall_input='0' then
w.save_addr := address;
w.access_q := '1';
if r.state=running then
w.line_save := address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := address(ADDRESS_HIGH downto CACHE_MAX_BITS);
end if;
end if;
else
if stall_input='0' then
w.access_q := '0';
end if;
end if;
if abort='1' then
w.access_q:='0';
w.queued_address:='0';
end if;
w.enable_q := enable;
valid <= data_valid;
stall <= stall_input;
if syscon.rst='1' then
w.state := flushing;
w.busy := '1';
w.fill_success :='0';
w.flushcnt := (others => '1');
w.tag_mem_wen := '1'; -- this needed ??
w.cyc := '0';
w.stb := 'X';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.access_q := '0';
w.enable_q := '0';
w.queued_address:='0';
w.iwfready:='0';
w.flush := '0';
w.fault := '0';
w.stbcount := (others => 'X');
w.line_save:= (others => 'X');
w.tag_save:= (others => 'X');
end if;
if rising_edge(syscon.clk) then
r <= w;
end if;
end process;
hit <= '1' when tag_match='1' and valid_i='1' else '0';
miss <= not hit;
mwbo.cyc <= r.cyc;
mwbo.stb <= r.stb;
mwbo.we <= '0';
mwbo.dat <= (others => 'X');
mwbo.bte <= BTE_BURST_16BEATWRAP;
mwbo.cti <= CTI_CYCLE_INCRADDR; -- BUg: we need to signal eof
mwbo.adr(31 downto CACHE_MAX_BITS) <= r.wbaddr(31 downto CACHE_MAX_BITS);
mwbo.adr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS) <= r.line_save;
mwbo.adr(CACHE_LINE_SIZE_BITS-1 downto 2) <= std_logic_vector(r.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2));
mwbo.tag(CACHE_LINE_SIZE_BITS-3 downto 0) <= std_logic_vector(r.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2));
mwbo.adr(1 downto 0) <= "00";
end behave;
|
------------------------------------------------------------------------------------------------
-- Author: <NAME>
-- Name: RTL_REG.vhd
-- Date of creation: 29/11/2018
-- Date of modification: 07/12/2018
-- Description: Implementation of a Register
------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library AESLibrary;
use AESLibrary.state_definition_package.all;
library source;
entity RTL_REG is
port (
clockREG_i : in std_logic;
resetbREG_i : in std_logic;
enableREG_i : in std_logic;
D_i : in bit128;
Q_o : out bit128
);
end entity RTL_REG;
architecture RTL_REG_arch of RTL_REG is
signal Q_os : bit128;
signal inter_s : bit128;
begin
seq_0 : process(clockREG_i, resetbREG_i, inter_s)
begin
if resetbREG_i = '0' then
Q_os <= (others => '0');
elsif clockREG_i'event and clockREG_i = '1' then
Q_os <= inter_s;
else
Q_os <= Q_os;
end if;
end process seq_0;
seq_1 : process(Q_os, D_i, enableREG_i)
begin
if enableREG_i = '1' then
inter_s <= D_i;
else
inter_s <= Q_os;
end if;
end process seq_1;
Q_o <= Q_os;
end architecture RTL_REG_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
-- This block implements VERA mode 0, i.e. 16 colour text mode.
-- Furthermore, it is hardcoded that:
-- * MAPW = 2, which means 128 tiles wide
-- * MAPH = 1, which means 64 tiles high
-- * TILEW = 0, which means 8 pixels wide
-- * TILEH = 0, which means 8 pixels high
--
-- In this mode, the map data consists of 64 rows of 128 values, where
-- each value is two bytes. The first byte indicates the tile index,
-- the second value indicates the colour index.
-- In the colour index, bits 7-4 is the background colour, while
-- bits 3-0 is the foreground colour.
--
-- On input it has the free-running pixel counters, as well as the base
-- addresses for the MAP and TILE areas.
-- On output it has colour of the corresponding pixel.
-- Because there are several pipeline stages in this block, the output must
-- also include the pixel counters delayed accordingly.
--
-- This block needs to read the Video RAM three times for each tile:
-- 1. To get the tile index at the corresponding pixel (using mapbase_i).
-- 2. To get the colour index at the corresponding pixel (using mapbase_i).
-- 3. To get the tile data for this character (using tilebase_i).
-- Additionally, it needs to read the colour from the palette RAM at every pixel.
--
-- Since each tile is 8 pixels wide (and hence eight clock cycles),
-- the reads from Video RAM are staged.
entity mode0 is
port (
clk_i : in std_logic;
-- Input pixel counters
pix_x_i : in std_logic_vector( 9 downto 0);
pix_y_i : in std_logic_vector( 9 downto 0);
-- Interface to Video RAM
vram_addr_o : out std_logic_vector(16 downto 0);
vram_rd_data_i : in std_logic_vector( 7 downto 0);
-- Interface to Palette RAM
pal_addr_o : out std_logic_vector( 7 downto 0);
pal_rd_data_i : in std_logic_vector(11 downto 0);
-- From Layer settings
mapbase_i : in std_logic_vector(16 downto 0);
tilebase_i : in std_logic_vector(16 downto 0);
-- Output colour
col_o : out std_logic_vector(11 downto 0);
delay_o : out std_logic_vector( 9 downto 0) -- Length of pipeline
);
end mode0;
architecture rtl of mode0 is
-- Stage 0
signal pix_x_0r : std_logic_vector( 9 downto 0);
signal pix_y_0r : std_logic_vector( 9 downto 0);
-- Stage 1
signal pix_x_1r : std_logic_vector( 9 downto 0);
signal pix_y_1r : std_logic_vector( 9 downto 0);
-- Stage 2
signal pix_x_2r : std_logic_vector( 9 downto 0);
signal pix_y_2r : std_logic_vector( 9 downto 0);
-- Stage 3
signal pix_x_3r : std_logic_vector( 9 downto 0);
signal pix_y_3r : std_logic_vector( 9 downto 0);
signal colour_value_3r : std_logic_vector( 7 downto 0);
-- Stage 4
signal pix_x_4r : std_logic_vector( 9 downto 0);
signal pix_y_4r : std_logic_vector( 9 downto 0);
signal colour_value_4r : std_logic_vector( 7 downto 0);
signal tile_value_4r : std_logic_vector( 7 downto 0);
-- Stage 5
signal pix_x_5r : std_logic_vector( 9 downto 0);
signal pix_y_5r : std_logic_vector( 9 downto 0);
begin
---------------------------------------
-- Perform staged reads from Video RAM
-- 1. To get the tile index at the corresponding pixel (using mapbase_i).
-- 2. To get the colour index at the corresponding pixel (using mapbase_i).
-- 3. To get the tile data for this character (using tilebase_i).
---------------------------------------
p_stages : process (clk_i)
variable map_row_v : std_logic_vector( 5 downto 0); -- 64 tiles high
variable map_column_v : std_logic_vector( 6 downto 0); -- 128 tiles wide
variable map_offset_v : std_logic_vector(16 downto 0);
variable map_value_v : std_logic_vector( 7 downto 0); -- Tile index
variable tile_row_v : std_logic_vector( 2 downto 0); -- 8 pixels high
variable tile_column_v : std_logic_vector( 2 downto 0); -- 8 pixels wide
variable tile_offset_v : std_logic_vector(16 downto 0);
begin
if rising_edge(clk_i) then
pix_x_0r <= pix_x_i;
pix_y_0r <= pix_y_i;
pix_x_1r <= pix_x_0r;
pix_y_1r <= pix_y_0r;
pix_x_2r <= pix_x_1r;
pix_y_2r <= pix_y_1r;
pix_x_3r <= pix_x_2r;
pix_y_3r <= pix_y_2r;
pix_x_4r <= pix_x_3r;
pix_y_4r <= pix_y_3r;
-- Stage 0. Read tile index from Video RAM. Ready in stage 2.
if pix_x_i(2 downto 0) = 0 then
map_row_v := pix_y_i(8 downto 3);
map_column_v := pix_x_i(9 downto 3);
map_offset_v := "000" & map_row_v & map_column_v & "0";
vram_addr_o <= mapbase_i + map_offset_v;
end if;
-- Stage 1. Read colour index from Video RAM. Ready in stage 3.
if pix_x_i(2 downto 0) = 1 then
map_row_v := pix_y_i(8 downto 3);
map_column_v := pix_x_i(9 downto 3);
map_offset_v := "000" & map_row_v & map_column_v & "1";
vram_addr_o <= mapbase_i + map_offset_v;
end if;
-- Stage 2. Read tile data from Video RAM. Ready in stage 4.
if pix_x_i(2 downto 0) = 2 then
map_value_v := vram_rd_data_i; -- Store tile index for this tile.
tile_row_v := pix_y_i(2 downto 0);
tile_offset_v := "000000" & map_value_v & tile_row_v;
vram_addr_o <= tilebase_i + tile_offset_v;
end if;
-- Stage 3. Store colour value.
if pix_x_i(2 downto 0) = 3 then
colour_value_3r <= vram_rd_data_i; -- Store colour index for this tile.
end if;
-- Stage 4. Store tile value.
if pix_x_i(2 downto 0) = 4 then
colour_value_4r <= colour_value_3r; -- Make sure colour and tile values
-- are properly synchronized.
tile_value_4r <= vram_rd_data_i; -- Store data for this tile.
end if;
end if;
end process p_stages;
-------------------------
-- Read from palette RAM
-------------------------
p_colour : process (clk_i)
variable tile_column_v : integer range 0 to 7; -- 8 pixels wide
variable pixel_v : std_logic;
variable tile_offset_v : std_logic_vector(16 downto 0);
begin
if rising_edge(clk_i) then
tile_column_v := 7-to_integer(pix_x_4r(2 downto 0)); -- Subtract from 7, because the MSB of the tile data
-- corresponds to the lowest pixel coordinate.
pixel_v := tile_value_4r(tile_column_v); -- Get value of this particular pixel.
-- Read pixel colour from palette RAM.
if pixel_v = '0' then
pal_addr_o <= "0000" & colour_value_4r(7 downto 4); -- background
else
pal_addr_o <= "0000" & colour_value_4r(3 downto 0); -- foreground
end if;
end if;
end process p_colour;
--------------------
-- Output registers
--------------------
p_output : process (clk_i)
begin
if rising_edge(clk_i) then
col_o <= pal_rd_data_i;
delay_o <= "0000001000";
end if;
end process p_output;
end architecture rtl;
|
--
-- Written by <NAME>
--
library ieee;
use ieee.std_logic_1164.ALL;
entity led_button is
port ( buttons : in std_logic_vector (4 downto 0); -- 5 buttons
leds : out std_logic_vector (7 downto 0)); -- 8 LEDs
end led_button;
architecture behavioral of led_button is
begin
-- First 5 LEDs are directly mapped to each of the 5 buttons
leds(7 downto 3) <= buttons(4 downto 0);
-- Illuminate the other 3 LEDs using boolean logic
leds(0) <= buttons(0) and buttons(1);
leds(1) <= buttons(2) and buttons(3);
leds(2) <= buttons(4) and buttons(0);
end behavioral;
|
<filename>bitvis_vip_axi/tb/maintenance_tb/axi_vvc_tb.vhd
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_axi;
context bitvis_vip_axi.vvc_context;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
--hdlunit:tb
-- Test case entity
entity axi_vvc_tb is
generic (
GC_TESTCASE : string := "UVVM"
);
end entity axi_vvc_tb;
-- Test case architecture
architecture sim of axi_vvc_tb is
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant C_ADDR_WIDTH_1 : natural := 32;
constant C_DATA_WIDTH_1 : natural := 32;
constant C_ID_WIDTH_1 : natural := 8;
constant C_USER_WIDTH_1 : natural := 8;
constant C_ADDR_WIDTH_2 : natural := 32;
constant C_DATA_WIDTH_2 : natural := 32;
constant C_ID_WIDTH_2 : natural := 0;
constant C_USER_WIDTH_2 : natural := 0;
signal clk : std_logic := '0';
signal areset : std_logic := '0';
signal clock_ena : boolean := false;
begin
-----------------------------
-- Instantiate Test harness
-----------------------------
i_axi_th : entity work.axi_th
generic map (
GC_ADDR_WIDTH_1 => C_ADDR_WIDTH_1,
GC_DATA_WIDTH_1 => C_DATA_WIDTH_1,
GC_ID_WIDTH_1 => C_ID_WIDTH_1,
GC_USER_WIDTH_1 => C_USER_WIDTH_1,
GC_ADDR_WIDTH_2 => C_ADDR_WIDTH_2,
GC_DATA_WIDTH_2 => C_DATA_WIDTH_2,
GC_ID_WIDTH_2 => C_ID_WIDTH_2,
GC_USER_WIDTH_2 => C_USER_WIDTH_2
);
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
variable v_cmd_idx : integer;
variable v_result : t_vvc_result;
variable v_expected_result : t_vvc_result := C_EMPTY_VVC_RESULT;
variable v_write_data : t_slv_array(0 to 3)(31 downto 0) := (x"12345678", x"33333333", x"55555555", x"AAAAAAAA");
variable v_max_write_data : t_slv_array(0 to 255)(31 downto 0) := (others=>(others=>'0'));
variable v_write_data_narrow : t_slv_array(0 to 1)(7 downto 0) := (x"12", x"34");
variable v_wstrb_narrow : t_slv_array(0 to 1)(0 downto 0) := ("1", "1");
variable v_wuser_narrow : t_slv_array(0 to 1)(0 downto 0) := ("1", "1");
variable v_ruser_narrow : t_slv_array(0 to 1)(0 downto 0) := ("0", "0");
variable v_write_data_wide : t_slv_array(0 to 1)(39 downto 0) := (x"0087654321", x"009ABCDEF0");
variable v_wstrb_wide : t_slv_array(0 to 1)(7 downto 0) := (x"0F", x"0F");
variable v_wuser_wide : t_slv_array(0 to 1)(15 downto 0) := (x"0001", x"0001");
variable v_ruser_wide : t_slv_array(0 to 1)(15 downto 0) := (x"0000", x"0000");
variable v_wstrb_single_byte : t_slv_array(0 to 3)(3 downto 0) := (x"1", x"1", x"1", x"1");
variable v_timestamp : time;
variable v_measured_time : time;
begin
-- To avoid that log files from different test cases (run in separate
-- simulations) overwrite each other.
set_log_file_name(GC_TESTCASE & "_Log.txt");
set_alert_file_name(GC_TESTCASE & "_Alert.txt");
await_uvvm_initialization(VOID);
disable_log_msg(ID_POS_ACK);
disable_log_msg(ID_UVVM_SEND_CMD);
disable_log_msg(ID_UVVM_CMD_ACK);
disable_log_msg(ID_UVVM_CMD_RESULT);
disable_log_msg(ID_AWAIT_COMPLETION_WAIT);
disable_log_msg(ID_AWAIT_COMPLETION_END);
disable_log_msg(AXI_VVCT, 1, ID_POS_ACK);
disable_log_msg(AXI_VVCT, 1, ID_CMD_INTERPRETER);
disable_log_msg(AXI_VVCT, 1, ID_CMD_INTERPRETER_WAIT);
disable_log_msg(AXI_VVCT, 1, ID_CMD_EXECUTOR_WAIT);
disable_log_msg(AXI_VVCT, 2, ID_POS_ACK);
disable_log_msg(AXI_VVCT, 2, ID_CMD_INTERPRETER);
disable_log_msg(AXI_VVCT, 2, ID_CMD_INTERPRETER_WAIT);
disable_log_msg(AXI_VVCT, 2, ID_CMD_EXECUTOR_WAIT);
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
wait for 40 ns; -- Waiting until reset is done
--------------------------------------------------------------------------------------------------------------------
-- Testing write/read/check procedures
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing write/read/check procedures");
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000000",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000000",
arlen => x"03",
arsize => 4,
rdata_exp => t_slv_array'(x"12345678", x"33333333", x"55555555", x"AAAAAAAA"),
msg => "Testing AXI check"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000000",
arlen => x"03",
arsize => 4,
data_routing => TO_BUFFER,
msg => "Testing AXI read"
);
v_cmd_idx := get_last_received_cmd_idx(AXI_VVCT,1); -- Retrieve the command index
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
fetch_result(AXI_VVCT, 1, v_cmd_idx, v_result, "Fetching read result");
check_value(v_result.rid, x"00", "Checking RID", C_SCOPE);
for i in 0 to 3 loop
check_value(v_result.rdata(i), v_write_data(i), "Checking RDATA, index " & to_string(i), C_SCOPE);
check_value(v_result.ruser(i), x"00", "Checking RUSER, index " & to_string(i), C_SCOPE);
end loop;
--------------------------------------------------------------------------------------------------------------------
-- Testing scoreboard
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing scoreboard");
v_expected_result.len := 1;
v_expected_result.rid(7 downto 0) := x"12";
v_expected_result.rdata(0)(31 downto 0) := x"33333333";
v_expected_result.rdata(1)(31 downto 0) := x"55555555";
v_expected_result.ruser(0)(7 downto 0) := x"00";
v_expected_result.ruser(1)(7 downto 0) := x"00";
AXI_VVC_SB.add_expected(1, v_expected_result);
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => x"12",
araddr => x"00000004",
arlen => x"01",
arsize => 4,
data_routing => TO_SB,
msg => "Testing AXI read"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
--------------------------------------------------------------------------------------------------------------------
-- Testing out-of-order write responses
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing out-of-order write responses");
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awid => x"00",
awaddr => x"00000010",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awid => x"01",
awaddr => x"00000020",
awlen => x"03",
awsize => 4,
wdata => t_slv_array'(x"BBBBBBBB", x"CCCCCCCC", x"DDDDDDDD", x"EEEEEEEE"),
msg => "Testing AXI write"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
--------------------------------------------------------------------------------------------------------------------
-- Testing read data response coming out of order
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing read data response coming out of order");
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awid => x"00",
awaddr => x"00000030",
awlen => x"08",
awsize => 4,
wdata => t_slv_array'(x"77777777", x"88888888", x"99999999", x"AAAAAAAA", x"BBBBBBBB", x"CCCCCCCC", x"DDDDDDDD", x"EEEEEEEE", x"FFFFFFFF"),
msg => "Testing AXI write"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => x"01",
araddr => x"00000030",
arlen => x"02",
arsize => 4,
rdata_exp => t_slv_array'(x"77777777", x"88888888", x"99999999"),
msg => "Testing AXI check"
);
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => x"02",
araddr => x"0000003C",
arlen => x"02",
arsize => 4,
rdata_exp => t_slv_array'(x"AAAAAAAA", x"BBBBBBBB", x"CCCCCCCC"),
msg => "Testing AXI check"
);
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => x"03",
araddr => x"00000048",
arlen => x"02",
arsize => 4,
rdata_exp => t_slv_array'(x"DDDDDDDD", x"EEEEEEEE", x"FFFFFFFF"),
msg => "Testing AXI check"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
--------------------------------------------------------------------------------------------------------------------
-- Testing minimum burst length
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing minimum burst length");
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000060",
awlen => x"00",
awsize => 4,
wdata => v_write_data(0 to 0),
msg => "Writing with a minimum burst length"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
-- Checking that only this word has been written
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000060",
arlen => x"00",
arsize => 4,
rdata_exp => v_write_data(0 to 0),
msg => "Reading with a minumum burst length"
);
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000064",
arlen => x"00",
arsize => 4,
rdata_exp => t_slv_array'(x"00000000", x"00000000"),
msg => "Reading from the next address to see that it hasn't been written to"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
--------------------------------------------------------------------------------------------------------------------
-- Testing maximum burst length
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing maximum burst length");
-- Filling the write data variable
for i in 0 to 255 loop
v_max_write_data(i) := random(32);
end loop;
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000070",
awlen => x"FF",
awsize => 4,
wdata => v_max_write_data,
msg => "Writing with a maximum burst length"
);
await_completion(AXI_VVCT, 1, 10 us, "Waiting for commands to finish");
-- Checking that the data has been written correctly
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000070",
arlen => x"FF",
arsize => 4,
data_routing => TO_BUFFER,
msg => "Testing AXI read"
);
v_cmd_idx := get_last_received_cmd_idx(AXI_VVCT,1); -- Retrieve the command index
await_completion(AXI_VVCT, 1, 10 us, "Waiting for commands to finish");
fetch_result(AXI_VVCT, 1, v_cmd_idx, v_result, "Fetching read result");
for i in 0 to 255 loop
check_value(v_result.rdata(i), v_max_write_data(i), "Checking RDATA, index " & to_string(i), C_SCOPE);
-- check_value(v_result.ruser(i), x"00", "Checking RUSER, index " & to_string(i), C_SCOPE);
end loop;
--------------------------------------------------------------------------------------------------------------------
-- Testing that unconstrained command parameters are normalized correctly
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing that unconstrained command parameters are normalized correctly");
-- Testing smaller parameter widths on all unconstrained inputs
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awid => "1",
awaddr => x"500",
awlen => x"01",
awsize => 4,
awuser => "1",
wdata => v_write_data_narrow,
wstrb => v_wstrb_narrow,
wuser => v_wuser_narrow,
buser_exp => "0",
msg => "Testing smaller parameter widths on all unconstrained inputs"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
-- Checking that the data was written correctly
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000500",
arlen => x"01",
arsize => 4,
rdata_exp => t_slv_array'(x"00000012", x"00000034"),
msg => "Checking that the data was written correctly"
);
-- Testing smaller parameter widths on axi_check
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => "1",
araddr => x"500",
arlen => x"01",
arsize => 4,
aruser => "1",
rdata_exp => v_write_data_narrow,
ruser_exp => v_ruser_narrow,
msg => "Testing smaller parameter widths on axi_check"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
-- Testing smaller parameter widths on axi_read
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => "1",
araddr => x"500",
arlen => x"01",
arsize => 4,
aruser => "1",
data_routing => TO_BUFFER,
msg => "Testing smaller parameter widths on axi_read"
);
v_cmd_idx := get_last_received_cmd_idx(AXI_VVCT,1); -- Retrieve the command index
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
fetch_result(AXI_VVCT, 1, v_cmd_idx, v_result, "Fetching read result");
check_value(v_result.rid, x"01", "Checking RID", C_SCOPE);
for i in 0 to 1 loop
check_value(v_result.rdata(i), v_write_data_narrow(i), "Checking RDATA, index " & to_string(i), C_SCOPE);
check_value(v_result.ruser(i), x"00", "Checking RUSER, index " & to_string(i), C_SCOPE);
end loop;
-- Testing larger parameter widths on all unconstrained inputs
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awid => x"001",
awaddr => x"000000510",
awlen => x"01",
awsize => 4,
awuser => x"001",
wdata => v_write_data_wide,
wstrb => v_wstrb_wide,
wuser => v_wuser_wide,
buser_exp => x"000",
msg => "Testing larger parameter widths on all unconstrained inputs"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
-- Checking that the data was written correctly
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000510",
arlen => x"01",
arsize => 4,
rdata_exp => t_slv_array'(x"87654321", x"9ABCDEF0"),
msg => "Checking that the data was written correctly"
);
-- Testing larger parameter widths on axi_check
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => x"001",
araddr => x"0000000510",
arlen => x"01",
arsize => 4,
aruser => x"001",
rdata_exp => v_write_data_wide,
ruser_exp => v_ruser_wide,
msg => "Testing larger parameter widths on axi_check"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
-- Testing larger parameter widths on axi_read
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
arid => x"001",
araddr => x"0000000510",
arlen => x"01",
arsize => 4,
aruser => x"001",
data_routing => TO_BUFFER,
msg => "Testing smaller parameter widths on axi_read"
);
v_cmd_idx := get_last_received_cmd_idx(AXI_VVCT,1); -- Retrieve the command index
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
fetch_result(AXI_VVCT, 1, v_cmd_idx, v_result, "Fetching read result");
check_value(v_result.rid, x"01", "Checking RID", C_SCOPE);
for i in 0 to 1 loop
check_value(v_result.rdata(i), v_write_data_wide(i), "Checking RDATA, index " & to_string(i), C_SCOPE);
check_value(v_result.ruser(i), x"00", "Checking RUSER, index " & to_string(i), C_SCOPE);
end loop;
--------------------------------------------------------------------------------------------------------------------
-- Testing that ID and user of size 0 is allowed
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing that ID and user of size 0 is allowed");
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 2,
awaddr => x"00000000",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
await_completion(AXI_VVCT, 2, 1 us, "Waiting for commands to finish");
axi_check(
VVCT => AXI_VVCT,
vvc_instance_idx => 2,
araddr => x"00000000",
arlen => x"03",
arsize => 4,
rdata_exp => t_slv_array'(x"12345678", x"33333333", x"55555555", x"AAAAAAAA"),
msg => "Testing AXI check"
);
await_completion(AXI_VVCT, 2, 1 us, "Waiting for commands to finish");
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 2,
araddr => x"00000000",
arlen => x"03",
arsize => 4,
data_routing => TO_BUFFER,
msg => "Testing AXI read"
);
v_cmd_idx := get_last_received_cmd_idx(AXI_VVCT,2); -- Retrieve the command index
await_completion(AXI_VVCT, 2, 1 us, "Waiting for commands to finish");
fetch_result(AXI_VVCT, 2, v_cmd_idx, v_result, "Fetching read result");
-- check_value(v_result.rid, x"00", "Checking RID", C_SCOPE);
for i in 0 to 3 loop
check_value(v_result.rdata(i), v_write_data(i), "Checking RDATA, index " & to_string(i), C_SCOPE);
-- check_value(v_result.ruser(i), x"00", "Checking RUSER, index " & to_string(i), C_SCOPE);
end loop;
--------------------------------------------------------------------------------------------------------------------
-- Testing inter bfm delay
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing TIME_START2START");
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000000",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
await_completion(AXI_VVCT, 1, 1 us, "Waiting for commands to finish");
v_timestamp := now;
shared_axi_vvc_config(1).inter_bfm_delay.delay_type := TIME_START2START;
shared_axi_vvc_config(1).inter_bfm_delay.delay_in_time := 10 us;
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000000",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
await_completion(AXI_VVCT, 1, 100 us, "Waiting for commands to finish");
check_value(now - v_timestamp, 10 us, ERROR, "Checking that inter-bfm delay was upheld");
log(ID_LOG_HDR, "Testing TIME_FINISH2START");
increment_expected_alerts(TB_WARNING,1, "Expecting warning because TIME_FINISH2START is not supported", C_SCOPE);
v_timestamp := now;
shared_axi_vvc_config(1).inter_bfm_delay.delay_type := TIME_FINISH2START;
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000000",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
await_completion(AXI_VVCT, 1, 100 us, "Waiting for commands to finish");
shared_axi_vvc_config(1).inter_bfm_delay.delay_type := NO_DELAY;
shared_axi_vvc_config(1).inter_bfm_delay.delay_in_time := 0 ns;
--------------------------------------------------------------------------------------------------------------------
-- Testing to force single pending transactions
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing to force single pending transactions");
-- First we measure the time it takes to perform a read and write simultaneously
v_timestamp := now;
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000000",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000004",
arlen => x"03",
arsize => 4,
data_routing => TO_BUFFER,
msg => "Testing AXI read"
);
await_completion(AXI_VVCT, 1, 100 us, "Waiting for commands to finish");
v_measured_time := now - v_timestamp;
-- Then, we turn on the force_single_penging_transaction setting, and see that it takes about twice as long
shared_axi_vvc_config(1).force_single_pending_transaction := true;
v_timestamp := now;
axi_write(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
awaddr => x"00000000",
awlen => x"03",
awsize => 4,
wdata => v_write_data,
msg => "Testing AXI write"
);
axi_read(
VVCT => AXI_VVCT,
vvc_instance_idx => 1,
araddr => x"00000004",
arlen => x"03",
arsize => 4,
data_routing => TO_BUFFER,
msg => "Testing AXI read"
);
await_completion(AXI_VVCT, 1, 100 us, "Waiting for commands to finish");
-- Checking that it takes twice as long (+- 20 %)
check_value_in_range(now - v_timestamp, v_measured_time*1.8, v_measured_time*2.2, ERROR, "Checking that it takes longer time to force a single pending transaction");
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end architecture sim;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2019.1
-- Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ShiftRows is
port (
ap_ready : OUT STD_LOGIC;
state_0_1_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_0_2_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_0_3_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_1_1_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_1_2_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_1_3_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_2_1_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_2_2_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_2_3_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_3_1_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_3_2_read : IN STD_LOGIC_VECTOR (7 downto 0);
state_3_3_read : IN STD_LOGIC_VECTOR (7 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_4 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_5 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_6 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_7 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_8 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_9 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_10 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_11 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end;
architecture behav of ShiftRows is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
begin
ap_ready <= ap_const_logic_1;
ap_return_0 <= state_1_1_read;
ap_return_1 <= state_2_2_read;
ap_return_10 <= state_1_2_read;
ap_return_11 <= state_2_3_read;
ap_return_2 <= state_3_3_read;
ap_return_3 <= state_2_1_read;
ap_return_4 <= state_3_2_read;
ap_return_5 <= state_0_3_read;
ap_return_6 <= state_3_1_read;
ap_return_7 <= state_0_2_read;
ap_return_8 <= state_1_3_read;
ap_return_9 <= state_0_1_read;
end behav;
|
library Common;
use Common.CommonLib.all;
architecture RTL of serialPortTransmitter is
signal dividerCounter: unsigned(requiredBitNb(baudRateDivide)-1 downto 0);
signal dividerCounterReset: std_uLogic;
signal txData: std_ulogic_vector(dataBitNb-1 downto 0);
signal send1: std_uLogic;
signal txShiftEnable: std_uLogic;
signal txShiftReg: std_ulogic_vector(dataBitNb+1 downto 0);
signal txSendingByte: std_uLogic;
signal txSendingByteAndStop: std_uLogic;
begin
divide: process(reset, clock)
begin
if reset = '1' then
dividerCounter <= (others => '0');
elsif rising_edge(clock) then
if dividerCounterReset = '1' then
dividerCounter <= to_unsigned(1, dividerCounter'length);
else
dividerCounter <= dividerCounter + 1;
end if;
end if;
end process divide;
endOfCount: process(dividerCounter, send1)
begin
if dividerCounter = baudRateDivide then
dividerCounterReset <= '1';
elsif send1 = '1' then
dividerCounterReset <= '1';
else
dividerCounterReset <= '0';
end if;
end process endOfCount;
txShiftEnable <= dividerCounterReset;
storeData: process(reset, clock)
begin
if reset = '1' then
txData <= (others => '1');
elsif rising_edge(clock) then
if send = '1' then
txData <= dataIn;
end if;
end if;
end process storeData;
delaySend: process(reset, clock)
begin
if reset = '1' then
send1 <= '0';
elsif rising_edge(clock) then
send1 <= send;
end if;
end process delaySend;
shiftReg: process(reset, clock)
begin
if reset = '1' then
txShiftReg <= (others => '1');
elsif rising_edge(clock) then
if txShiftEnable = '1' then
if send1 = '1' then
txShiftReg <= '0' & txData & '0';
else
txShiftReg(txShiftReg'high-1 downto 0) <= txShiftReg(txShiftReg'high downto 1);
txShiftReg(txShiftReg'high) <= '1';
end if;
end if;
end if;
end process shiftReg;
txSendingByte <= '1' when (txShiftReg(txShiftReg'high downto 1) /= (txShiftReg'high downto 1 => '1'))
else '0';
txSendingByteAndStop <= '1' when txShiftReg /= (txShiftReg'high downto 0 => '1')
else '0';
TxD <= txShiftReg(0) when txSendingByte = '1' else '1';
busy <= txSendingByteAndStop or send1 or send;
end RTL;
|
<reponame>Chair-for-Security-Engineering/FrodoKEM<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity read_S is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
done : out std_logic;
addr_sk : out std_logic_vector(13 downto 0);
dout_sk : in std_logic_vector(15 downto 0);
we_out : out std_logic;
addr_out : out std_logic_vector(9 downto 0);
din_out : out std_logic_vector(15 downto 0)
);
end entity read_S;
architecture behave of read_S is
type states is (s_reset, s_read, s_done);
signal state : states := s_reset;
signal i, in_index, out_index, outputs_done, offset : integer := 0;
begin
process (clk) is
begin
if (rising_edge(clk)) then
done <= '0';
we_out <= '0';
if (reset = '1') then
state <= s_reset;
elsif (enable = '1') then
if (state = s_reset) then
state <= s_read;
i <= 0;
in_index <= 0;
out_index <= 0;
outputs_done <= 0;
offset <= 0;
elsif (state = s_read) then
state <= s_read;
i <= i + 1;
in_index <= in_index + 640;
if (in_index >= 4480) then
in_index <= 0;
offset <= offset + 1;
end if;
addr_sk <= std_logic_vector(to_unsigned(in_index+4816+offset, 14));
if (i >= 2) then
out_index <= out_index + 1;
outputs_done <= outputs_done + 1;
we_out <= '1';
addr_out <= std_logic_vector(to_unsigned(out_index, 10));
din_out <= dout_sk(7 downto 0) & dout_sk(15 downto 8);
if (out_index = 7) then
out_index <= 0;
end if;
if (outputs_done = 5119) then
state <= s_done;
end if;
end if;
elsif (state = s_done) then
done <= '1';
state <= s_reset;
end if;
end if;
end if;
end process;
end behave;
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:01:32 06/10/2013
-- Design Name:
-- Module Name: teste_display_e_botao - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity teste_display_e_botao is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
botao : in STD_LOGIC;
saida_8segmentos : out STD_LOGIC_VECTOR (7 downto 0);
disp_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC);
end teste_display_e_botao;
architecture Behavioral of teste_display_e_botao is
signal entrada_disp, display_s : STD_LOGIC_VECTOR (15 downto 0);
signal clk1s, botao_DB : std_logic :='0';
signal cnt : integer range 0 to 9999;
begin
meu_proj : entity work.meu_projeto
Port map ( clock => clock,
reset => reset,
botao => botao_DB,
saida => entrada_disp,
led => led) ;
debouce_n1 :entity work.debounce
port map ( clock => clock,
entrada => botao,
saida_DB => botao_DB
);
display : entity work.modulo_display
Port map( clock => clock,
reset => reset,
entrada_s => entrada_disp,
saida_8segmentos => saida_8segmentos,
disp_sel_o => disp_sel_o
);
end Behavioral;
|
-- Converted from mpsoc_wb_uart_regs.v
-- by verilog2vhdl - QueenField
--//////////////////////////////////////////////////////////////////////////////
-- __ _ _ _ //
-- / _(_) | | | | //
-- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | //
-- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | //
-- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | //
-- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| //
-- | | //
-- |_| //
-- //
-- //
-- MPSoC-RISCV CPU //
-- Universal Asynchronous Receiver-Transmitter //
-- Wishbone Bus Interface //
-- //
--//////////////////////////////////////////////////////////////////////////////
-- Copyright (c) 2018-2019 by the author(s)
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a copy
-- * of this software and associated documentation files (the "Software"), to deal
-- * in the Software without restriction, including without limitation the rights
-- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- * copies of the Software, and to permit persons to whom the Software is
-- * furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- * THE SOFTWARE.
-- *
-- * =============================================================================
-- * Author(s):
-- * <NAME> <<EMAIL>>
-- * <NAME> <<EMAIL>>
-- */
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mpsoc_uart_wb_pkg.all;
entity mpsoc_wb_uart_regs is
generic (
SIM : integer := 0
);
port (
clk : in std_logic;
wb_rst_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_re_i : in std_logic;
stx_pad_o : out std_logic;
srx_pad_i : in std_logic;
modem_inputs : in std_logic_vector(3 downto 0);
rts_pad_o : out std_logic;
dtr_pad_o : out std_logic;
int_o : out std_logic;
baud_o : out std_logic
);
end mpsoc_wb_uart_regs;
architecture RTL of mpsoc_wb_uart_regs is
component mpsoc_wb_uart_transmitter
generic (
SIM : integer := 0
);
port (
clk : in std_logic;
wb_rst_i : in std_logic;
lcr : in std_logic_vector(7 downto 0);
tf_push : in std_logic;
wb_dat_i : in std_logic_vector(7 downto 0);
enable : in std_logic;
tx_reset : in std_logic;
lsr_mask : in std_logic; --reset of fifo
stx_pad_o : out std_logic;
tstate : out std_logic_vector(2 downto 0);
tf_count : out std_logic_vector(UART_FIFO_COUNTER_W-1 downto 0)
);
end component;
component mpsoc_wb_uart_sync_flops
generic (
WIDTH : integer := 1;
INIT_VALUE : std_logic := '0'
);
port (
rst_i : in std_logic; -- reset input
clk_i : in std_logic; -- clock input
stage1_rst_i : in std_logic; -- synchronous reset for stage 1 FF
stage1_clk_en_i : in std_logic; -- synchronous clock enable for stage 1 FF
async_dat_i : in std_logic_vector(WIDTH-1 downto 0); -- asynchronous data input
sync_dat_o : out std_logic_vector(WIDTH-1 downto 0) -- synchronous data output
);
end component;
component mpsoc_wb_uart_receiver
port (
clk : in std_logic;
wb_rst_i : in std_logic;
lcr : in std_logic_vector(7 downto 0);
rf_pop : in std_logic;
srx_pad_i : in std_logic;
enable : in std_logic;
rx_reset : in std_logic;
lsr_mask : in std_logic;
counter_t : out std_logic_vector(9 downto 0);
rf_count : out std_logic_vector(UART_FIFO_COUNTER_W-1 downto 0);
rf_data_out : out std_logic_vector(UART_FIFO_REC_WIDTH-1 downto 0);
rf_overrun : out std_logic;
rf_error_bit : out std_logic;
rstate : out std_logic_vector(3 downto 0);
rf_push_pulse : out std_logic
);
end component;
--////////////////////////////////////////////////////////////////
--
-- Constants
--
constant PRESCALER_PRESET_HARD : std_logic := '1';
constant PRESCALER_HIGH_PRESET : std_logic_vector(7 downto 0) := X"00";
constant PRESCALER_LOW_PRESET : std_logic_vector(7 downto 0) := X"00";
--////////////////////////////////////////////////////////////////
--
-- Variables
--
signal enable : std_logic;
signal srx_pad : std_logic_vector(0 downto 0);
signal srx_pad_o : std_logic_vector(0 downto 0);
signal ier : std_logic_vector(3 downto 0);
signal iir : std_logic_vector(3 downto 0);
signal fcr : std_logic_vector(1 downto 0); -- bits 7 and 6 of fcr. Other bits are ignored
signal mcr : std_logic_vector(4 downto 0);
signal lcr : std_logic_vector(7 downto 0);
signal msr : std_logic_vector(7 downto 0);
signal dl : std_logic_vector(15 downto 0); -- 32-bit divisor latch
signal scratch : std_logic_vector(7 downto 0); -- UART scratch register
signal start_dlc : std_logic; -- activate dlc on writing to UART_DL1
signal lsr_mask_d : std_logic; -- delay for lsr_mask condition
signal msi_reset : std_logic; -- reset MSR 4 lower bits indicator
signal dlc : std_logic_vector(15 downto 0); -- 32-bit divisor latch counter
signal trigger_level : std_logic_vector(3 downto 0); -- trigger level of the receiver FIFO
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal dlab : std_logic; -- divisor latch access bit
signal loopback : std_logic; -- loopback bit (MCR bit 4)
signal cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i : std_logic; -- modem status bits
signal cts, dsr, ri, dcd : std_logic; -- effective signals
signal cts_c, dsr_c, ri_c, dcd_c : std_logic; -- Complement effective signals (considering loopback)
-- LSR bits wires and regs
signal lsr : std_logic_vector(7 downto 0);
signal lsr_mask : std_logic; -- lsr_mask
signal lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7 : std_logic;
signal lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r : std_logic;
-- Interrupt signals
signal rls_int : std_logic; -- receiver line status interrupt
signal rda_int : std_logic; -- receiver data available interrupt
signal ti_int : std_logic; -- timeout indicator interrupt
signal thre_int : std_logic; -- transmitter holding register empty interrupt
signal ms_int : std_logic; -- modem status interrupt
-- FIFO signals
signal tf_push : std_logic;
signal rf_pop : std_logic;
signal rf_data_out : std_logic_vector(UART_FIFO_REC_WIDTH-1 downto 0);
signal rf_error_bit : std_logic; -- an error (parity or framing) is inside the fifo
signal rf_overrun : std_logic;
signal rf_push_pulse : std_logic;
signal rf_count : std_logic_vector(UART_FIFO_COUNTER_W-1 downto 0);
signal tf_count : std_logic_vector(UART_FIFO_COUNTER_W-1 downto 0);
signal tstate : std_logic_vector(2 downto 0);
signal rstate : std_logic_vector(3 downto 0);
signal counter_t : std_logic_vector(9 downto 0);
signal thre_set_en : std_logic; -- THRE status is delayed one character time when a character is written to fifo.
signal block_cnt : std_logic_vector(7 downto 0); -- While counter counts, THRE status is blocked (delayed one character cycle)
signal block_value : std_logic_vector(7 downto 0); -- One character length minus stop bit
-- Transmitter Instance
signal serial_out : std_logic;
-- handle loopback
signal serial_in : std_logic;
signal lsr_mask_condition : std_logic;
signal iir_read : std_logic;
signal msr_read : std_logic;
signal fifo_read : std_logic;
signal fifo_write : std_logic;
-- STATUS REGISTERS
-- Modem Status Register
signal delayed_modem_signals : std_logic_vector(3 downto 0);
-- lsr bit0 (receiver data available)
signal lsr0_d : std_logic;
-- lsr bit 1 (receiver overrun)
signal lsr1_d : std_logic; -- delayed
-- lsr bit 2 (parity error)
signal lsr2_d : std_logic; -- delayed
-- lsr bit 3 (framing error)
signal lsr3_d : std_logic; -- delayed
-- lsr bit 4 (break indicator)
signal lsr4_d : std_logic; -- delayed
-- lsr bit 5 (transmitter fifo is empty)
signal lsr5_d : std_logic;
-- lsr bit 6 (transmitter empty indicator)
signal lsr6_d : std_logic;
-- lsr bit 7 (error in fifo)
signal lsr7_d : std_logic;
signal rls_int_d : std_logic;
signal thre_int_d : std_logic;
signal ms_int_d : std_logic;
signal ti_int_d : std_logic;
signal rda_int_d : std_logic;
-- rise detection signals
signal rls_int_rise : std_logic;
signal thre_int_rise : std_logic;
signal ms_int_rise : std_logic;
signal ti_int_rise : std_logic;
signal rda_int_rise : std_logic;
-- interrupt pending flags
signal rls_int_pnd : std_logic;
signal rda_int_pnd : std_logic;
signal thre_int_pnd : std_logic;
signal ms_int_pnd : std_logic;
signal ti_int_pnd : std_logic;
begin
--////////////////////////////////////////////////////////////////
--
-- Module Body
--
baud_o <= enable; -- baud_o is actually the enable signal
lsr(7 downto 0) <= (lsr7r & lsr6r & lsr5r & lsr4r & lsr3r & lsr2r & lsr1r & lsr0r);
cts_pad_i <= modem_inputs(3);
dsr_pad_i <= modem_inputs(2);
dsr_pad_i <= modem_inputs(1);
dcd_pad_i <= modem_inputs(0);
cts <= not cts_pad_i;
dsr <= not dsr_pad_i;
ri <= not ri_pad_i;
dcd <= not dcd_pad_i;
cts_c <= mcr(UART_MC_RTS) when loopback = '1' else cts_pad_i;
dsr_c <= mcr(UART_MC_DTR) when loopback = '1' else dsr_pad_i;
ri_c <= mcr(UART_MC_OUT1) when loopback = '1' else ri_pad_i;
dcd_c <= mcr(UART_MC_OUT2) when loopback = '1' else dcd_pad_i;
dlab <= lcr(UART_LC_DL);
loopback <= mcr(4);
-- assign modem outputs
rts_pad_o <= mcr(UART_MC_RTS);
dtr_pad_o <= mcr(UART_MC_DTR);
transmitter : mpsoc_wb_uart_transmitter
generic map (
SIM => SIM
)
port map (
clk => clk,
wb_rst_i => wb_rst_i,
lcr => lcr,
tf_push => tf_push,
wb_dat_i => wb_dat_i,
enable => enable,
stx_pad_o => serial_out,
tstate => tstate,
tf_count => tf_count,
tx_reset => tx_reset,
lsr_mask => lsr_mask
);
-- Synchronizing and sampling serial RX input
i_uart_sync_flops : mpsoc_wb_uart_sync_flops
generic map (
WIDTH => 1,
INIT_VALUE => '0'
)
port map (
rst_i => wb_rst_i,
clk_i => clk,
stage1_rst_i => '0',
stage1_clk_en_i => '1',
async_dat_i => srx_pad_o,
sync_dat_o => srx_pad
);
srx_pad_o(0) <= srx_pad_i;
serial_in <= serial_out when loopback = '1' else srx_pad(0);
stx_pad_o <= '1' when loopback = '1' else serial_out;
-- Receiver Instance
receiver : mpsoc_wb_uart_receiver
port map (
clk => clk,
wb_rst_i => wb_rst_i,
lcr => lcr,
rf_pop => rf_pop,
srx_pad_i => serial_in,
enable => enable,
counter_t => counter_t,
rf_count => rf_count,
rf_data_out => rf_data_out,
rf_error_bit => rf_error_bit,
rf_overrun => rf_overrun,
rx_reset => rx_reset,
lsr_mask => lsr_mask,
rstate => rstate,
rf_push_pulse => rf_push_pulse
);
-- Asynchronous reading here because the outputs are sampled in uart_wb.v file
processing_0 : process (dl, dlab, ier, iir, scratch, lcr, lsr, msr, rf_data_out, wb_addr_i, wb_re_i)
begin
-- asynchrounous reading
case ((wb_addr_i)) is
when UART_REG_RB =>
if (dlab = '1') then
wb_dat_o <= dl(7 downto 0);
else
wb_dat_o <= rf_data_out(10 downto 3);
end if;
when UART_REG_IE =>
if (dlab = '1') then
wb_dat_o <= dl(15 downto 8);
else
wb_dat_o <= ("0000" & ier);
end if;
when UART_REG_II =>
wb_dat_o <= ("1100" & iir);
when UART_REG_LC =>
wb_dat_o <= lcr;
when UART_REG_LS =>
wb_dat_o <= lsr;
when UART_REG_MS =>
wb_dat_o <= msr;
when UART_REG_SR =>
wb_dat_o <= scratch;
when others =>
wb_dat_o <= (others => '0');
end case;
end process;
-- rf_pop signal handling
processing_1 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
rf_pop <= '0';
elsif (rising_edge(clk)) then
if (rf_pop = '1') then -- restore the signal to 0 after one clock cycle
rf_pop <= '0';
elsif (wb_re_i = '1' and wb_addr_i = UART_REG_RB and dlab = '0') then
rf_pop <= '1'; -- advance read pointer
end if;
end if;
end process;
lsr_mask_condition <= (wb_re_i and to_stdlogic(wb_addr_i = UART_REG_LS) and not dlab);
iir_read <= (wb_re_i and to_stdlogic(wb_addr_i = UART_REG_II) and not dlab);
msr_read <= (wb_re_i and to_stdlogic(wb_addr_i = UART_REG_MS) and not dlab);
fifo_read <= (wb_re_i and to_stdlogic(wb_addr_i = UART_REG_RB) and not dlab);
fifo_write <= (wb_we_i and to_stdlogic(wb_addr_i = UART_REG_TR) and not dlab);
-- lsr_mask_d delayed signal handling
processing_2 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr_mask_d <= '0';
elsif (rising_edge(clk)) then
-- reset bits in the Line Status Register
lsr_mask_d <= lsr_mask_condition;
end if;
end process;
-- lsr_mask is rise detected
lsr_mask <= lsr_mask_condition and not lsr_mask_d;
-- msi_reset signal handling
processing_3 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
msi_reset <= '1';
elsif (rising_edge(clk)) then
if (msi_reset = '1') then
msi_reset <= '0';
elsif (msr_read = '1') then
msi_reset <= '1'; -- reset bits in Modem Status Register
end if;
end if;
end process;
-- WRITES AND RESETS
-- Line Control Register
processing_4 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lcr <= "00000011"; -- 8n1 setting
elsif (rising_edge(clk)) then
if (wb_we_i = '1' and wb_addr_i = UART_REG_LC) then
lcr <= wb_dat_i;
end if;
end if;
end process;
-- Interrupt Enable Register or UART_DL2
processing_5 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
ier <= "0000"; -- no interrupts after reset
if (PRESCALER_PRESET_HARD = '1') then
dl(15 downto 8) <= PRESCALER_HIGH_PRESET;
elsif (PRESCALER_PRESET_HARD = '0') then
dl(15 downto 8) <= (others => '0');
end if;
elsif (rising_edge(clk)) then
if (wb_we_i = '1' and wb_addr_i = UART_REG_IE) then
if (dlab = '1') then
if (PRESCALER_PRESET_HARD = '0') then
dl(15 downto 8) <= wb_dat_i;
end if;
else -- ier uses only 4 lsb
ier <= wb_dat_i(3 downto 0);
end if;
end if;
end if;
end process;
-- FIFO Control Register and rx_reset, tx_reset signals
processing_6 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
fcr <= "11";
rx_reset <= '0';
tx_reset <= '0';
elsif (rising_edge(clk)) then
if (wb_we_i = '1' and wb_addr_i = UART_REG_FC) then
fcr <= wb_dat_i(7 downto 6);
rx_reset <= wb_dat_i(1);
tx_reset <= wb_dat_i(2);
else
rx_reset <= '0';
tx_reset <= '0';
end if;
end if;
end process;
-- Modem Control Register
processing_7 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
mcr <= (others => '0');
elsif (rising_edge(clk)) then
if (wb_we_i = '1' and wb_addr_i = UART_REG_MC) then
mcr <= wb_dat_i(4 downto 0);
end if;
end if;
end process;
-- Scratch register
-- Line Control Register
processing_8 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
scratch <= (others => '0'); -- 8n1 setting
elsif (rising_edge(clk)) then
if (wb_we_i = '1' and wb_addr_i = UART_REG_SR) then
scratch <= wb_dat_i;
end if;
end if;
end process;
-- TX_FIFO or UART_DL1
processing_9 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
if (PRESCALER_PRESET_HARD = '1') then
dl(7 downto 0) <= PRESCALER_LOW_PRESET;
elsif (PRESCALER_PRESET_HARD = '0') then
dl(7 downto 0) <= (others => '0');
end if;
tf_push <= '0';
start_dlc <= '0';
elsif (rising_edge(clk)) then
if (wb_we_i = '1' and wb_addr_i = UART_REG_TR) then
if (dlab = '1') then
if (PRESCALER_PRESET_HARD = '0') then
dl(7 downto 0) <= wb_dat_i;
end if;
start_dlc <= '1'; -- enable DL counter
tf_push <= '0';
else
tf_push <= '1';
start_dlc <= '0';
end if;
else -- else: !if(dlab)
start_dlc <= '0';
tf_push <= '0';
end if;
end if;
end process;
-- Receiver FIFO trigger level selection logic (asynchronous mux)
processing_10 : process (fcr)
begin
case (fcr(1 downto 0)) is
when "00" =>
trigger_level <= std_logic_vector(to_unsigned(1, 4));
when "01" =>
trigger_level <= std_logic_vector(to_unsigned(4, 4));
when "10" =>
trigger_level <= std_logic_vector(to_unsigned(8, 4));
when "11" =>
trigger_level <= std_logic_vector(to_unsigned(14, 4));
when others =>
null;
end case;
end process;
processing_11 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
msr <= (others => '0');
delayed_modem_signals(3 downto 0) <= (others => '0');
elsif (rising_edge(clk)) then
if (msi_reset = '1') then
msr(UART_MS_DDCD downto UART_MS_DCTS) <= (others => '0');
else
msr(UART_MS_DDCD downto UART_MS_DCTS) <= msr(UART_MS_DDCD downto UART_MS_DCTS) or ((dcd & ri & dsr & cts) xor delayed_modem_signals(3 downto 0));
end if;
msr(UART_MS_CDCD downto UART_MS_CCTS) <= (dcd_c & ri_c & dsr_c & cts_c);
delayed_modem_signals(3 downto 0) <= (dcd & ri & dsr & cts);
end if;
end process;
-- Line Status Register
-- activation conditions
lsr0 <= to_stdlogic(unsigned(tf_count) = to_unsigned(0, UART_FIFO_COUNTER_W)) and rf_push_pulse; -- data in receiver fifo available set condition
lsr1 <= rf_overrun; -- Receiver overrun error
lsr2 <= rf_data_out(1); -- parity error bit
lsr3 <= rf_data_out(0); -- framing error bit
lsr4 <= rf_data_out(2); -- break error in the character
lsr5 <= to_stdlogic(unsigned(tf_count) = to_unsigned(0, UART_FIFO_COUNTER_W)) and thre_set_en; -- transmitter fifo is empty
lsr6 <= to_stdlogic(unsigned(tf_count) = to_unsigned(0, UART_FIFO_COUNTER_W)) and thre_set_en and to_stdlogic(tstate = "000"); -- transmitter empty
lsr7 <= rf_error_bit or rf_overrun;
processing_12 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr0_d <= '0';
elsif (rising_edge(clk)) then
lsr0_d <= lsr0;
end if;
end process;
processing_13 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr0r <= '0';
elsif (rising_edge(clk)) then
-- deassert condition
if ((rf_count = std_logic_vector(to_unsigned(1, UART_FIFO_COUNTER_W)) and rf_pop = '1' and rf_push_pulse = '0') or rx_reset = '1') then
lsr0r <= '0';
else
lsr0r <= lsr0r or (lsr0 and not lsr0_d); -- set on rise of lsr0 and keep asserted until deasserted
end if;
end if;
end process;
processing_14 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr1_d <= '0';
elsif (rising_edge(clk)) then
lsr1_d <= lsr1;
end if;
end process;
processing_15 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr1r <= '0';
elsif (rising_edge(clk)) then
if (lsr_mask = '1') then
lsr1r <= '0';
else
lsr1r <= lsr1r or (lsr1 and not lsr1_d); -- set on rise
end if;
end if;
end process;
processing_16 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr2_d <= '0';
elsif (rising_edge(clk)) then
lsr2_d <= lsr2;
end if;
end process;
processing_17 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr2r <= '0';
elsif (rising_edge(clk)) then
if (lsr_mask = '1') then
lsr2r <= '0';
else
lsr2r <= lsr2r or (lsr1 and not lsr2_d); -- set on rise
end if;
end if;
end process;
processing_18 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr3_d <= '0';
elsif (rising_edge(clk)) then
lsr3_d <= lsr3;
end if;
end process;
processing_19 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr3r <= '0';
elsif (rising_edge(clk)) then
if (lsr_mask = '1') then
lsr3r <= '0';
else
lsr3r <= lsr3r or (lsr3 and not lsr3_d); -- set on rise
end if;
end if;
end process;
processing_20 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr4_d <= '0';
elsif (rising_edge(clk)) then
lsr4_d <= lsr4;
end if;
end process;
processing_21 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr4r <= '0';
elsif (rising_edge(clk)) then
if (lsr_mask = '1') then
lsr4r <= '0';
else
lsr4r <= lsr4r or (lsr4 and not lsr4_d);
end if;
end if;
end process;
processing_22 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr5_d <= '1';
elsif (rising_edge(clk)) then
lsr5_d <= lsr5;
end if;
end process;
processing_23 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr5r <= '1';
elsif (rising_edge(clk)) then
if (fifo_write = '1') then
lsr5r <= '0';
else
lsr5r <= lsr5r or (lsr5 and not lsr5_d);
end if;
end if;
end process;
processing_24 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr6_d <= '1';
elsif (rising_edge(clk)) then
lsr6_d <= lsr6;
end if;
end process;
processing_25 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr6r <= '1';
elsif (rising_edge(clk)) then
if (fifo_write = '1') then
lsr6r <= '0';
else
lsr6r <= lsr6r or (lsr6 and not lsr6_d);
end if;
end if;
end process;
processing_26 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr7_d <= '0';
elsif (rising_edge(clk)) then
lsr7_d <= lsr7;
end if;
end process;
processing_27 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
lsr7r <= '0';
elsif (rising_edge(clk)) then
if (lsr_mask = '1') then
lsr7r <= '0';
else
lsr7r <= lsr7r or (lsr7 and not lsr7_d);
end if;
end if;
end process;
-- Frequency divider
processing_28 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
dlc <= (others => '0');
elsif (rising_edge(clk)) then
if (start_dlc = '1' or reduce_or(dlc) = '0') then
dlc <= std_logic_vector(unsigned(dl)-X"0001"); -- preset counter
else -- decrement counter
dlc <= std_logic_vector(unsigned(dlc)-X"0001");
end if;
end if;
end process;
-- Enable signal generation logic
processing_29 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
enable <= '0';
elsif (rising_edge(clk)) then
if (reduce_or(dl) = '1' and reduce_or(dlc) = '0') then -- dl>0 & dlc==0
enable <= '1';
else
enable <= '0';
end if;
end if;
end process;
-- Delaying THRE status for one character cycle after a character is written to an empty fifo.
processing_30 : process (lcr)
begin
case ((lcr(3 downto 0))) is
when "0000" =>
-- 6 bits
block_value <= std_logic_vector(to_unsigned(95, 8));
when "0100" =>
-- 6.5 bits
block_value <= std_logic_vector(to_unsigned(103, 8));
when "0001" =>
when "1000" =>
-- 7 bits
block_value <= std_logic_vector(to_unsigned(111, 8));
when "1100" =>
-- 7.5 bits
block_value <= std_logic_vector(to_unsigned(119, 8));
when "0010" =>
when "0101" =>
when "1001" =>
-- 8 bits
block_value <= std_logic_vector(to_unsigned(127, 8));
when "0011" =>
when "0110" =>
when "1010" =>
when "1101" =>
-- 9 bits
block_value <= std_logic_vector(to_unsigned(143, 8));
when "0111" =>
when "1011" =>
when "1110" =>
-- 10 bits
block_value <= std_logic_vector(to_unsigned(159, 8));
when "1111" =>
-- 11 bits
block_value <= std_logic_vector(to_unsigned(175, 8));
when others =>
null;
end case;
end process;
-- Counting time of one character minus stop bit
processing_31 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
block_cnt <= X"00";
elsif (rising_edge(clk)) then
if (lsr5r = '1' and fifo_write = '1') then -- THRE bit set & write to fifo occured
if (SIM = 1) then
block_cnt <= X"01";
else
block_cnt <= block_value;
end if;
elsif (enable = '1' and block_cnt /= X"00") then -- only work on enable times
block_cnt <= std_logic_vector(unsigned(block_cnt)-X"01"); -- decrement break counter
end if;
end if;
end process;
-- always of break condition detection
-- Generating THRE status enable signal
thre_set_en <= not reduce_or(block_cnt);
-- INTERRUPT LOGIC
rls_int <= ier(UART_IE_RLS) and (lsr(UART_LS_OE) or lsr(UART_LS_PE) or lsr(UART_LS_FE) or lsr(UART_LS_BI));
rda_int <= ier(UART_IE_RDA) and to_stdlogic(rf_count >= '0' & trigger_level);
thre_int <= ier(UART_IE_THRE) and lsr(UART_LS_TFE);
ms_int <= ier(UART_IE_MS) and (reduce_or(msr(3 downto 0)));
ti_int <= ier(UART_IE_RDA) and to_stdlogic(counter_t = "0000000000") and reduce_or(rf_count);
-- delay lines
processing_32 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
rls_int_d <= '0';
elsif (rising_edge(clk)) then
rls_int_d <= rls_int;
end if;
end process;
processing_33 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
rda_int_d <= '0';
elsif (rising_edge(clk)) then
rda_int_d <= rda_int;
end if;
end process;
processing_34 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
thre_int_d <= '0';
elsif (rising_edge(clk)) then
thre_int_d <= thre_int;
end if;
end process;
processing_35 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
ms_int_d <= '0';
elsif (rising_edge(clk)) then
ms_int_d <= ms_int;
end if;
end process;
processing_36 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
ti_int_d <= '0';
elsif (rising_edge(clk)) then
ti_int_d <= ti_int;
end if;
end process;
rda_int_rise <= rda_int and not rda_int_d;
rls_int_rise <= rls_int and not rls_int_d;
thre_int_rise <= thre_int and not thre_int_d;
ms_int_rise <= ms_int and not ms_int_d;
ti_int_rise <= ti_int and not ti_int_d;
-- interrupt pending flags assignments
processing_37 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
rls_int_pnd <= '0';
elsif (rising_edge(clk)) then
if (lsr_mask = '1') then
rls_int_pnd <= '0'; -- reset condition
elsif (rls_int_rise = '1') then
rls_int_pnd <= '1'; -- latch condition
else
rls_int_pnd <= rls_int_pnd and ier(UART_IE_RLS); -- default operation: remove if masked
end if;
end if;
end process;
processing_38 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
rda_int_pnd <= '0';
elsif (rising_edge(clk)) then
if ((rf_count = ('0' & trigger_level)) and fifo_read = '1') then
rda_int_pnd <= '0'; -- reset condition
elsif (rda_int_rise = '1') then
rda_int_pnd <= '1'; -- latch condition
else
rda_int_pnd <= rda_int_pnd and ier(UART_IE_RDA); -- default operation: remove if masked
end if;
end if;
end process;
processing_39 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
thre_int_pnd <= '0';
elsif (rising_edge(clk)) then
if (iir_read = '1' and iir(UART_II_IP) = '0' and iir(3 downto 1) = UART_II_THRE) then
thre_int_pnd <= fifo_write or '0';
elsif (thre_int_rise = '1') then
thre_int_pnd <= '1';
else
thre_int_pnd <= thre_int_pnd and ier(UART_IE_THRE);
end if;
end if;
end process;
processing_40 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
ms_int_pnd <= '0';
elsif (rising_edge(clk)) then
if (msr_read = '1') then
ms_int_pnd <= '0';
elsif (ms_int_rise = '1') then
ms_int_pnd <= '1';
else
ms_int_pnd <= ms_int_pnd and ier(UART_IE_MS);
end if;
end if;
end process;
processing_41 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
ti_int_pnd <= '0';
elsif (rising_edge(clk)) then
if (fifo_read = '1') then
ti_int_pnd <= '0';
elsif (ti_int_rise = '1') then
ti_int_pnd <= '1';
else
ti_int_pnd <= ti_int_pnd and ier(UART_IE_RDA);
end if;
end if;
end process;
-- end of pending flags
-- INT_O logic
processing_42 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
int_o <= '0';
elsif (rising_edge(clk)) then
if (rls_int_pnd = '1') then
int_o <= not lsr_mask;
elsif (rda_int_pnd = '1') then
int_o <= '1';
elsif (ti_int_pnd = '1') then
int_o <= not fifo_read;
elsif (thre_int_pnd = '1') then
int_o <= not (fifo_write and iir_read);
elsif (ms_int_pnd = '1') then -- if no interrupt are pending
int_o <= not msr_read;
else
int_o <= '0'; -- if no interrupt are pending
end if;
end if;
end process;
-- Interrupt Identification register
processing_43 : process (clk, wb_rst_i)
begin
if (wb_rst_i = '1') then
iir <= X"1";
elsif (rising_edge(clk)) then
if (rls_int_pnd = '1') then -- interrupt is pending
iir(3 downto 1) <= UART_II_RLS; -- set identification register to correct value
iir(UART_II_IP) <= '0'; -- and clear the IIR bit 0 (interrupt pending)
-- the sequence of conditions determines priority of interrupt identification
elsif (rda_int = '1') then
iir(3 downto 1) <= UART_II_RDA;
iir(UART_II_IP) <= '0';
elsif (ti_int_pnd = '1') then
iir(3 downto 1) <= UART_II_TI;
iir(UART_II_IP) <= '0';
elsif (thre_int_pnd = '1') then
iir(3 downto 1) <= UART_II_THRE;
iir(UART_II_IP) <= '0';
elsif (ms_int_pnd = '1') then
iir(3 downto 1) <= UART_II_MS;
iir(UART_II_IP) <= '0';
else -- no interrupt is pending
iir(3 downto 1) <= (others => '0');
iir(UART_II_IP) <= '1';
end if;
end if;
end process;
end RTL;
|
<reponame>lsst-camera-daq/surf<gh_stars>100-1000
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: Uses the ICAP primitive to internally
-- toggle the PROG_B via IPROG command
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library surf;
use surf.StdRtlPkg.all;
library unisim;
use unisim.vcomponents.all;
entity Iprog7Series is
generic (
TPD_G : time := 1 ns;
USE_SLOWCLK_G : boolean := false;
BUFR_CLK_DIV_G : string := "8");
port (
clk : in sl;
rst : in sl;
slowClk : in sl := '0';
start : in sl; -- Should be asserted and held until reboot
bootAddress : in slv(31 downto 0) := X"00000000");
end Iprog7Series;
architecture rtl of Iprog7Series is
signal icapClk : sl;
signal icapClkRst : sl;
signal icapCsl : sl;
signal icapRnw : sl;
signal icapI : slv(31 downto 0);
begin
SLOWCLK_GEN : if (USE_SLOWCLK_G) generate
icapClk <= slowClk;
end generate SLOWCLK_GEN;
DIVCLK_GEN : if (not USE_SLOWCLK_G) generate
BUFR_ICPAPE2 : BUFR
generic map (
BUFR_DIVIDE => BUFR_CLK_DIV_G)
port map (
CE => '1',
CLR => '0',
I => clk,
O => icapClk);
end generate DIVCLK_GEN;
-- Synchronize reset to icapClk
RstSync_Inst : entity surf.RstSync
generic map (
TPD_G => TPD_G,
OUT_REG_RST_G => false)
port map (
clk => icapClk,
asyncRst => rst,
syncRst => icapClkRst);
-- IPROG logic
Iprog7SeriesCore_1 : entity surf.Iprog7SeriesCore
generic map (
TPD_G => TPD_G,
SYNC_RELOAD_G => true)
port map (
reload => start,
reloadAddr => bootAddress,
icapClk => icapClk,
icapClkRst => icapClkRst,
icapReq => open,
icapGrant => '1', -- Dedicated ICAP so always grant
icapCsl => icapCsl,
icapRnw => icapRnw,
icapI => icapI);
-- ICAP Primative
ICAPE2_Inst : ICAPE2
generic map (
DEVICE_ID => x"03651093", -- Specifies the pre-programmed Device ID value to be used for simulation purposes
ICAP_WIDTH => "X32", -- Specifies the input and output data width to be used with the ICAPE2 Possible values: (X8,X16 or X32)
SIM_CFG_FILE_NAME => "NONE") -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation model
port map (
O => open, -- 32-bit output: Configuration data output bus
CLK => icapClk, -- 1-bit input: Clock Input
CSIB => icapCsl, -- 1-bit input: Active-Low ICAP Enable
I => icapI, -- 32-bit input: Configuration data input bus
RDWRB => icapRnw); -- 1-bit input: Read/Write Select input
end rtl;
|
--! @file halfround_2.vhd
--! @brief Xtea halfround 2
--! @author <NAME>, <EMAIL>
--! @date 2016-12-08
-------------------------------------------------------------------------------
-- Libraries
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity halfround_2 is
port (
key_i : in std_logic_vector(127 downto 0);
sum_i : in std_logic_vector(31 downto 0);
sum_o : out std_logic_vector(31 downto 0);
mode_i : in std_logic;
mode_o : out std_logic;
data_i : in std_logic_vector(63 downto 0);
data_o : out std_logic_vector(63 downto 0)
);
end halfround_2;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture halfround_2 of halfround_2 is
-----------------------------------
-- Types
-----------------------------------
-----------------------------------
-- Constants
-----------------------------------
-----------------------------------
-- Signal Declarations
-----------------------------------
signal key_sel : std_logic_vector(31 downto 0);
signal subkey : std_logic_vector(31 downto 0);
signal sftmix_1 : std_logic_vector(31 downto 0);
signal sftmix_2 : std_logic_vector(31 downto 0);
signal sftmix_3 : std_logic_vector(31 downto 0);
signal sftmix : std_logic_vector(31 downto 0);
signal v0 : std_logic_vector(31 downto 0);
signal v1 : std_logic_vector(31 downto 0);
signal xor_result : std_logic_vector(31 downto 0);
begin
-----------------------------------
-- Port Mappings
-----------------------------------
-----------------------------------
-- Asynchronous Assignments
-----------------------------------
v0 <= data_i(63 downto 32);
v1 <= data_i(31 downto 0);
-- keygen step
key_sel <= key_i(127 downto 96) when ((sum_i(12 downto 11) = "00" and mode_i = '0') or (sum_i(1 downto 0) = "00" and mode_i = '1')) else
key_i(95 downto 64) when ((sum_i(12 downto 11) = "01" and mode_i = '0') or (sum_i(1 downto 0) = "01" and mode_i = '1')) else
key_i(63 downto 32) when ((sum_i(12 downto 11) = "10" and mode_i = '0') or (sum_i(1 downto 0) = "10" and mode_i = '1')) else
key_i(31 downto 0);
subkey <= sum_i + key_sel;
-- f step
sftmix_1 <= v0(27 downto 0) & "0000";
sftmix_2 <= "00000" & v0(31 downto 5);
sftmix_3 <= sftmix_1 xor sftmix_2;
sftmix <= sftmix_3 + v0;
xor_result <= sftmix xor subkey;
data_o(63 downto 32) <= v0;
data_o(31 downto 0) <= (v1 + xor_result) when mode_i = '0' else (v1 - xor_result);
sum_o <= sum_i;
mode_o <= mode_i;
-----------------------------------
-- Processes
-----------------------------------
end halfround_2;
|
-- file: input/clock_divider.vhd
-- authors: <NAME> and <NAME>
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Divides 27MHz clock into adequate clock value
library ieee ;
use ieee.std_logic_1164.all ;
entity clock_divider is
generic (
RATE : natural := 270000
) ;
port (
clk_in : in std_logic ;
clk_out : out std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end clock_divider ;
architecture behavior of clock_divider is
signal count: integer range 0 to RATE - 1;
begin
-- Counter for rate
process(clk_in, reset)
begin
if reset = '1' then
count <= 0 ;
elsif rising_edge(clk_in) and enable = '1' then
if count = RATE - 1 then
count <= 0 ;
else
count <= count + 1 ;
end if ;
end if ;
end process ;
-- Sets clk_out
clk_out <= '1' when count = (RATE - 1) else '0' ;
end behavior ;
|
<reponame>2manyretries/util-hdl
-- cswapa
-- Conditionally Swap the pair of inputs to an ordered pair of outputs.
--
-- The comparison is done over a subrange (up to the full range) of the data
-- width, which allows for the sort-key to be combined with other data.
-- (For example an index of which element in the stream.)
-- Data outside the sort-key is considered a black box and passed around
-- untouched with it.
--
-- We also admit less-than (best is smallest) or greater-or-equal (best is
-- largest comparisons).
--
-- (c) GIves (2manyretries) 2016
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cswap is
generic (
width : positive; -- datum width
msb : natural; -- msbit to compare
lsb : natural; -- lsbit to compare
lt : boolean -- whether to compare less-than (best is smallest)
);
port (
ina : in std_logic_vector(width-1 downto 0);
inb : in std_logic_vector(width-1 downto 0);
outa : out std_logic_vector(width-1 downto 0);
outb : out std_logic_vector(width-1 downto 0)
);
end entity cswap;
architecture rtl of cswap is
begin
p_cswap : process (ina,inb) is
begin
outa <= ina;
outb <= inb;
if lt = ( unsigned(ina(msb downto lsb)) < unsigned(inb(msb downto lsb)) ) then
outa <= inb;
outb <= ina;
end if;
end process p_cswap;
end architecture rtl;
|
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: cri.nz:user:DDS_AXI_PERIPH_wrapper:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY SP_OV_DDS_AXI_PERIPH_wrapp_0_0 IS
PORT (
CH_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DEBUG : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DEBUG2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DONE : OUT STD_LOGIC;
MCLK_464_063 : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
aux_0_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_0_arready : OUT STD_LOGIC;
aux_0_arvalid : IN STD_LOGIC;
aux_0_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_0_awready : OUT STD_LOGIC;
aux_0_awvalid : IN STD_LOGIC;
aux_0_bready : IN STD_LOGIC;
aux_0_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_0_bvalid : OUT STD_LOGIC;
aux_0_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_0_rready : IN STD_LOGIC;
aux_0_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_0_rvalid : OUT STD_LOGIC;
aux_0_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_0_wready : OUT STD_LOGIC;
aux_0_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_0_wvalid : IN STD_LOGIC;
aux_1_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_1_arready : OUT STD_LOGIC;
aux_1_arvalid : IN STD_LOGIC;
aux_1_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_1_awready : OUT STD_LOGIC;
aux_1_awvalid : IN STD_LOGIC;
aux_1_bready : IN STD_LOGIC;
aux_1_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_1_bvalid : OUT STD_LOGIC;
aux_1_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_1_rready : IN STD_LOGIC;
aux_1_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_1_rvalid : OUT STD_LOGIC;
aux_1_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_1_wready : OUT STD_LOGIC;
aux_1_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_1_wvalid : IN STD_LOGIC;
aux_2_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_2_arready : OUT STD_LOGIC;
aux_2_arvalid : IN STD_LOGIC;
aux_2_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_2_awready : OUT STD_LOGIC;
aux_2_awvalid : IN STD_LOGIC;
aux_2_bready : IN STD_LOGIC;
aux_2_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_2_bvalid : OUT STD_LOGIC;
aux_2_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_2_rready : IN STD_LOGIC;
aux_2_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_2_rvalid : OUT STD_LOGIC;
aux_2_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_2_wready : OUT STD_LOGIC;
aux_2_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_2_wvalid : IN STD_LOGIC;
aux_3_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_3_arready : OUT STD_LOGIC;
aux_3_arvalid : IN STD_LOGIC;
aux_3_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_3_awready : OUT STD_LOGIC;
aux_3_awvalid : IN STD_LOGIC;
aux_3_bready : IN STD_LOGIC;
aux_3_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_3_bvalid : OUT STD_LOGIC;
aux_3_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_3_rready : IN STD_LOGIC;
aux_3_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_3_rvalid : OUT STD_LOGIC;
aux_3_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_3_wready : OUT STD_LOGIC;
aux_3_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_3_wvalid : IN STD_LOGIC;
ph_0_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_0_arready : OUT STD_LOGIC;
ph_0_arvalid : IN STD_LOGIC;
ph_0_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_0_awready : OUT STD_LOGIC;
ph_0_awvalid : IN STD_LOGIC;
ph_0_bready : IN STD_LOGIC;
ph_0_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_0_bvalid : OUT STD_LOGIC;
ph_0_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_0_rready : IN STD_LOGIC;
ph_0_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_0_rvalid : OUT STD_LOGIC;
ph_0_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_0_wready : OUT STD_LOGIC;
ph_0_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_0_wvalid : IN STD_LOGIC;
ph_1_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_1_arready : OUT STD_LOGIC;
ph_1_arvalid : IN STD_LOGIC;
ph_1_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_1_awready : OUT STD_LOGIC;
ph_1_awvalid : IN STD_LOGIC;
ph_1_bready : IN STD_LOGIC;
ph_1_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_1_bvalid : OUT STD_LOGIC;
ph_1_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_1_rready : IN STD_LOGIC;
ph_1_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_1_rvalid : OUT STD_LOGIC;
ph_1_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_1_wready : OUT STD_LOGIC;
ph_1_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_1_wvalid : IN STD_LOGIC;
ph_2_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_2_arready : OUT STD_LOGIC;
ph_2_arvalid : IN STD_LOGIC;
ph_2_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_2_awready : OUT STD_LOGIC;
ph_2_awvalid : IN STD_LOGIC;
ph_2_bready : IN STD_LOGIC;
ph_2_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_2_bvalid : OUT STD_LOGIC;
ph_2_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_2_rready : IN STD_LOGIC;
ph_2_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_2_rvalid : OUT STD_LOGIC;
ph_2_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_2_wready : OUT STD_LOGIC;
ph_2_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_2_wvalid : IN STD_LOGIC;
ph_3_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_3_arready : OUT STD_LOGIC;
ph_3_arvalid : IN STD_LOGIC;
ph_3_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_3_awready : OUT STD_LOGIC;
ph_3_awvalid : IN STD_LOGIC;
ph_3_bready : IN STD_LOGIC;
ph_3_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_3_bvalid : OUT STD_LOGIC;
ph_3_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_3_rready : IN STD_LOGIC;
ph_3_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_3_rvalid : OUT STD_LOGIC;
ph_3_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_3_wready : OUT STD_LOGIC;
ph_3_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_3_wvalid : IN STD_LOGIC;
util_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
util_arready : OUT STD_LOGIC;
util_arvalid : IN STD_LOGIC;
util_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
util_awready : OUT STD_LOGIC;
util_awvalid : IN STD_LOGIC;
util_bready : IN STD_LOGIC;
util_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
util_bvalid : OUT STD_LOGIC;
util_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
util_rready : IN STD_LOGIC;
util_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
util_rvalid : OUT STD_LOGIC;
util_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
util_wready : OUT STD_LOGIC;
util_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
util_wvalid : IN STD_LOGIC
);
END SP_OV_DDS_AXI_PERIPH_wrapp_0_0;
ARCHITECTURE SP_OV_DDS_AXI_PERIPH_wrapp_0_0_arch OF SP_OV_DDS_AXI_PERIPH_wrapp_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SP_OV_DDS_AXI_PERIPH_wrapp_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT DDS_AXI_PERIPH_wrapper IS
PORT (
CH_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DEBUG : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DEBUG2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DONE : OUT STD_LOGIC;
MCLK_464_063 : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
aux_0_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_0_arready : OUT STD_LOGIC;
aux_0_arvalid : IN STD_LOGIC;
aux_0_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_0_awready : OUT STD_LOGIC;
aux_0_awvalid : IN STD_LOGIC;
aux_0_bready : IN STD_LOGIC;
aux_0_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_0_bvalid : OUT STD_LOGIC;
aux_0_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_0_rready : IN STD_LOGIC;
aux_0_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_0_rvalid : OUT STD_LOGIC;
aux_0_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_0_wready : OUT STD_LOGIC;
aux_0_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_0_wvalid : IN STD_LOGIC;
aux_1_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_1_arready : OUT STD_LOGIC;
aux_1_arvalid : IN STD_LOGIC;
aux_1_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_1_awready : OUT STD_LOGIC;
aux_1_awvalid : IN STD_LOGIC;
aux_1_bready : IN STD_LOGIC;
aux_1_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_1_bvalid : OUT STD_LOGIC;
aux_1_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_1_rready : IN STD_LOGIC;
aux_1_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_1_rvalid : OUT STD_LOGIC;
aux_1_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_1_wready : OUT STD_LOGIC;
aux_1_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_1_wvalid : IN STD_LOGIC;
aux_2_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_2_arready : OUT STD_LOGIC;
aux_2_arvalid : IN STD_LOGIC;
aux_2_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_2_awready : OUT STD_LOGIC;
aux_2_awvalid : IN STD_LOGIC;
aux_2_bready : IN STD_LOGIC;
aux_2_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_2_bvalid : OUT STD_LOGIC;
aux_2_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_2_rready : IN STD_LOGIC;
aux_2_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_2_rvalid : OUT STD_LOGIC;
aux_2_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_2_wready : OUT STD_LOGIC;
aux_2_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_2_wvalid : IN STD_LOGIC;
aux_3_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_3_arready : OUT STD_LOGIC;
aux_3_arvalid : IN STD_LOGIC;
aux_3_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
aux_3_awready : OUT STD_LOGIC;
aux_3_awvalid : IN STD_LOGIC;
aux_3_bready : IN STD_LOGIC;
aux_3_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_3_bvalid : OUT STD_LOGIC;
aux_3_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_3_rready : IN STD_LOGIC;
aux_3_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
aux_3_rvalid : OUT STD_LOGIC;
aux_3_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
aux_3_wready : OUT STD_LOGIC;
aux_3_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aux_3_wvalid : IN STD_LOGIC;
ph_0_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_0_arready : OUT STD_LOGIC;
ph_0_arvalid : IN STD_LOGIC;
ph_0_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_0_awready : OUT STD_LOGIC;
ph_0_awvalid : IN STD_LOGIC;
ph_0_bready : IN STD_LOGIC;
ph_0_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_0_bvalid : OUT STD_LOGIC;
ph_0_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_0_rready : IN STD_LOGIC;
ph_0_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_0_rvalid : OUT STD_LOGIC;
ph_0_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_0_wready : OUT STD_LOGIC;
ph_0_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_0_wvalid : IN STD_LOGIC;
ph_1_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_1_arready : OUT STD_LOGIC;
ph_1_arvalid : IN STD_LOGIC;
ph_1_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_1_awready : OUT STD_LOGIC;
ph_1_awvalid : IN STD_LOGIC;
ph_1_bready : IN STD_LOGIC;
ph_1_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_1_bvalid : OUT STD_LOGIC;
ph_1_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_1_rready : IN STD_LOGIC;
ph_1_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_1_rvalid : OUT STD_LOGIC;
ph_1_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_1_wready : OUT STD_LOGIC;
ph_1_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_1_wvalid : IN STD_LOGIC;
ph_2_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_2_arready : OUT STD_LOGIC;
ph_2_arvalid : IN STD_LOGIC;
ph_2_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_2_awready : OUT STD_LOGIC;
ph_2_awvalid : IN STD_LOGIC;
ph_2_bready : IN STD_LOGIC;
ph_2_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_2_bvalid : OUT STD_LOGIC;
ph_2_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_2_rready : IN STD_LOGIC;
ph_2_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_2_rvalid : OUT STD_LOGIC;
ph_2_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_2_wready : OUT STD_LOGIC;
ph_2_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_2_wvalid : IN STD_LOGIC;
ph_3_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_3_arready : OUT STD_LOGIC;
ph_3_arvalid : IN STD_LOGIC;
ph_3_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ph_3_awready : OUT STD_LOGIC;
ph_3_awvalid : IN STD_LOGIC;
ph_3_bready : IN STD_LOGIC;
ph_3_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_3_bvalid : OUT STD_LOGIC;
ph_3_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_3_rready : IN STD_LOGIC;
ph_3_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ph_3_rvalid : OUT STD_LOGIC;
ph_3_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ph_3_wready : OUT STD_LOGIC;
ph_3_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ph_3_wvalid : IN STD_LOGIC;
util_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
util_arready : OUT STD_LOGIC;
util_arvalid : IN STD_LOGIC;
util_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
util_awready : OUT STD_LOGIC;
util_awvalid : IN STD_LOGIC;
util_bready : IN STD_LOGIC;
util_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
util_bvalid : OUT STD_LOGIC;
util_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
util_rready : IN STD_LOGIC;
util_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
util_rvalid : OUT STD_LOGIC;
util_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
util_wready : OUT STD_LOGIC;
util_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
util_wvalid : IN STD_LOGIC
);
END COMPONENT DDS_AXI_PERIPH_wrapper;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SP_OV_DDS_AXI_PERIPH_wrapp_0_0_arch: ARCHITECTURE IS "DDS_AXI_PERIPH_wrapper,Vivado 2019.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SP_OV_DDS_AXI_PERIPH_wrapp_0_0_arch : ARCHITECTURE IS "SP_OV_DDS_AXI_PERIPH_wrapp_0_0,DDS_AXI_PERIPH_wrapper,{}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF SP_OV_DDS_AXI_PERIPH_wrapp_0_0_arch: ARCHITECTURE IS "package_project";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF util_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 util WVALID";
ATTRIBUTE X_INTERFACE_INFO OF util_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 util WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF util_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 util WREADY";
ATTRIBUTE X_INTERFACE_INFO OF util_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 util WDATA";
ATTRIBUTE X_INTERFACE_INFO OF util_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 util RVALID";
ATTRIBUTE X_INTERFACE_INFO OF util_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 util RRESP";
ATTRIBUTE X_INTERFACE_INFO OF util_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 util RREADY";
ATTRIBUTE X_INTERFACE_INFO OF util_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 util RDATA";
ATTRIBUTE X_INTERFACE_INFO OF util_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 util BVALID";
ATTRIBUTE X_INTERFACE_INFO OF util_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 util BRESP";
ATTRIBUTE X_INTERFACE_INFO OF util_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 util BREADY";
ATTRIBUTE X_INTERFACE_INFO OF util_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 util AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF util_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 util AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF util_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 util AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF util_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 util ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF util_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 util ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF util_araddr: SIGNAL IS "XIL_INTERFACENAME util, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF util_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 util ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF ph_3_araddr: SIGNAL IS "XIL_INTERFACENAME ph_3, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ph_3_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_3 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF ph_2_araddr: SIGNAL IS "XIL_INTERFACENAME ph_2, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ph_2_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_2 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF ph_1_araddr: SIGNAL IS "XIL_INTERFACENAME ph_1, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ph_1_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_1 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF ph_0_araddr: SIGNAL IS "XIL_INTERFACENAME ph_0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ph_0_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ph_0 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_3_araddr: SIGNAL IS "XIL_INTERFACENAME aux_3, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aux_3_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_3 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_2_araddr: SIGNAL IS "XIL_INTERFACENAME aux_2, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aux_2_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_2 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_1_araddr: SIGNAL IS "XIL_INTERFACENAME aux_1, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aux_1_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_1 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 ARREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_0_araddr: SIGNAL IS "XIL_INTERFACENAME aux_0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1," &
" NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aux_0_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 aux_0 ARADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF aux_0:aux_1:aux_2:aux_3:ph_0:ph_1:ph_2:ph_3:util, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN SP_OV_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
BEGIN
U0 : DDS_AXI_PERIPH_wrapper
PORT MAP (
CH_OUT => CH_OUT,
DEBUG => DEBUG,
DEBUG2 => DEBUG2,
DONE => DONE,
MCLK_464_063 => MCLK_464_063,
aclk => aclk,
aresetn => aresetn,
aux_0_araddr => aux_0_araddr,
aux_0_arready => aux_0_arready,
aux_0_arvalid => aux_0_arvalid,
aux_0_awaddr => aux_0_awaddr,
aux_0_awready => aux_0_awready,
aux_0_awvalid => aux_0_awvalid,
aux_0_bready => aux_0_bready,
aux_0_bresp => aux_0_bresp,
aux_0_bvalid => aux_0_bvalid,
aux_0_rdata => aux_0_rdata,
aux_0_rready => aux_0_rready,
aux_0_rresp => aux_0_rresp,
aux_0_rvalid => aux_0_rvalid,
aux_0_wdata => aux_0_wdata,
aux_0_wready => aux_0_wready,
aux_0_wstrb => aux_0_wstrb,
aux_0_wvalid => aux_0_wvalid,
aux_1_araddr => aux_1_araddr,
aux_1_arready => aux_1_arready,
aux_1_arvalid => aux_1_arvalid,
aux_1_awaddr => aux_1_awaddr,
aux_1_awready => aux_1_awready,
aux_1_awvalid => aux_1_awvalid,
aux_1_bready => aux_1_bready,
aux_1_bresp => aux_1_bresp,
aux_1_bvalid => aux_1_bvalid,
aux_1_rdata => aux_1_rdata,
aux_1_rready => aux_1_rready,
aux_1_rresp => aux_1_rresp,
aux_1_rvalid => aux_1_rvalid,
aux_1_wdata => aux_1_wdata,
aux_1_wready => aux_1_wready,
aux_1_wstrb => aux_1_wstrb,
aux_1_wvalid => aux_1_wvalid,
aux_2_araddr => aux_2_araddr,
aux_2_arready => aux_2_arready,
aux_2_arvalid => aux_2_arvalid,
aux_2_awaddr => aux_2_awaddr,
aux_2_awready => aux_2_awready,
aux_2_awvalid => aux_2_awvalid,
aux_2_bready => aux_2_bready,
aux_2_bresp => aux_2_bresp,
aux_2_bvalid => aux_2_bvalid,
aux_2_rdata => aux_2_rdata,
aux_2_rready => aux_2_rready,
aux_2_rresp => aux_2_rresp,
aux_2_rvalid => aux_2_rvalid,
aux_2_wdata => aux_2_wdata,
aux_2_wready => aux_2_wready,
aux_2_wstrb => aux_2_wstrb,
aux_2_wvalid => aux_2_wvalid,
aux_3_araddr => aux_3_araddr,
aux_3_arready => aux_3_arready,
aux_3_arvalid => aux_3_arvalid,
aux_3_awaddr => aux_3_awaddr,
aux_3_awready => aux_3_awready,
aux_3_awvalid => aux_3_awvalid,
aux_3_bready => aux_3_bready,
aux_3_bresp => aux_3_bresp,
aux_3_bvalid => aux_3_bvalid,
aux_3_rdata => aux_3_rdata,
aux_3_rready => aux_3_rready,
aux_3_rresp => aux_3_rresp,
aux_3_rvalid => aux_3_rvalid,
aux_3_wdata => aux_3_wdata,
aux_3_wready => aux_3_wready,
aux_3_wstrb => aux_3_wstrb,
aux_3_wvalid => aux_3_wvalid,
ph_0_araddr => ph_0_araddr,
ph_0_arready => ph_0_arready,
ph_0_arvalid => ph_0_arvalid,
ph_0_awaddr => ph_0_awaddr,
ph_0_awready => ph_0_awready,
ph_0_awvalid => ph_0_awvalid,
ph_0_bready => ph_0_bready,
ph_0_bresp => ph_0_bresp,
ph_0_bvalid => ph_0_bvalid,
ph_0_rdata => ph_0_rdata,
ph_0_rready => ph_0_rready,
ph_0_rresp => ph_0_rresp,
ph_0_rvalid => ph_0_rvalid,
ph_0_wdata => ph_0_wdata,
ph_0_wready => ph_0_wready,
ph_0_wstrb => ph_0_wstrb,
ph_0_wvalid => ph_0_wvalid,
ph_1_araddr => ph_1_araddr,
ph_1_arready => ph_1_arready,
ph_1_arvalid => ph_1_arvalid,
ph_1_awaddr => ph_1_awaddr,
ph_1_awready => ph_1_awready,
ph_1_awvalid => ph_1_awvalid,
ph_1_bready => ph_1_bready,
ph_1_bresp => ph_1_bresp,
ph_1_bvalid => ph_1_bvalid,
ph_1_rdata => ph_1_rdata,
ph_1_rready => ph_1_rready,
ph_1_rresp => ph_1_rresp,
ph_1_rvalid => ph_1_rvalid,
ph_1_wdata => ph_1_wdata,
ph_1_wready => ph_1_wready,
ph_1_wstrb => ph_1_wstrb,
ph_1_wvalid => ph_1_wvalid,
ph_2_araddr => ph_2_araddr,
ph_2_arready => ph_2_arready,
ph_2_arvalid => ph_2_arvalid,
ph_2_awaddr => ph_2_awaddr,
ph_2_awready => ph_2_awready,
ph_2_awvalid => ph_2_awvalid,
ph_2_bready => ph_2_bready,
ph_2_bresp => ph_2_bresp,
ph_2_bvalid => ph_2_bvalid,
ph_2_rdata => ph_2_rdata,
ph_2_rready => ph_2_rready,
ph_2_rresp => ph_2_rresp,
ph_2_rvalid => ph_2_rvalid,
ph_2_wdata => ph_2_wdata,
ph_2_wready => ph_2_wready,
ph_2_wstrb => ph_2_wstrb,
ph_2_wvalid => ph_2_wvalid,
ph_3_araddr => ph_3_araddr,
ph_3_arready => ph_3_arready,
ph_3_arvalid => ph_3_arvalid,
ph_3_awaddr => ph_3_awaddr,
ph_3_awready => ph_3_awready,
ph_3_awvalid => ph_3_awvalid,
ph_3_bready => ph_3_bready,
ph_3_bresp => ph_3_bresp,
ph_3_bvalid => ph_3_bvalid,
ph_3_rdata => ph_3_rdata,
ph_3_rready => ph_3_rready,
ph_3_rresp => ph_3_rresp,
ph_3_rvalid => ph_3_rvalid,
ph_3_wdata => ph_3_wdata,
ph_3_wready => ph_3_wready,
ph_3_wstrb => ph_3_wstrb,
ph_3_wvalid => ph_3_wvalid,
util_araddr => util_araddr,
util_arready => util_arready,
util_arvalid => util_arvalid,
util_awaddr => util_awaddr,
util_awready => util_awready,
util_awvalid => util_awvalid,
util_bready => util_bready,
util_bresp => util_bresp,
util_bvalid => util_bvalid,
util_rdata => util_rdata,
util_rready => util_rready,
util_rresp => util_rresp,
util_rvalid => util_rvalid,
util_wdata => util_wdata,
util_wready => util_wready,
util_wstrb => util_wstrb,
util_wvalid => util_wvalid
);
END SP_OV_DDS_AXI_PERIPH_wrapp_0_0_arch;
|
<reponame>HenningHolmDE/adventofcode-2021
-- Solution for Advent of Code 2021, day 9
entity day_09 is
end entity;
use std.textio.all;
architecture simulation of day_09 is
type heightmap_t is array (natural range <>, natural range <>) of natural;
constant EXAMPLE_HEIGHTMAP : heightmap_t :=
(
(2, 1, 9, 9, 9, 4, 3, 2, 1, 0),
(3, 9, 8, 7, 8, 9, 4, 9, 2, 1),
(9, 8, 5, 6, 7, 8, 9, 8, 9, 2),
(8, 7, 6, 7, 8, 9, 6, 7, 8, 9),
(9, 8, 9, 9, 9, 6, 5, 6, 7, 8)
);
-- Check if given location is a low point
function is_low_point(
heightmap : heightmap_t;
row : natural;
col : natural
) return boolean is
variable height : natural;
begin
height := heightmap(row, col);
-- Check adjacent points
if row > 0 and heightmap(row - 1, col) <= height then
-- Not a low point as up is at least as low
return false;
elsif col > 0 and heightmap(row, col - 1) <= height then
-- Not a low point as left is at least as low
return false;
elsif col < heightmap'length(2) - 1 and heightmap(row, col + 1) <= height then
-- Not a low point as right is at least as low
return false;
elsif row < heightmap'length(1) - 1 and heightmap(row + 1, col) <= height then
-- Not a low point as down is at least as low
return false;
end if;
-- Low point as all adjacent points are higher.
return true;
end function;
-- Part One: Calculate sum of low point's risk levels for given heightmap
function calculate_risk_level_sum(
heightmap : heightmap_t
) return natural is
variable risk_level : natural;
variable result : natural;
begin
result := 0;
for ROW in heightmap'range(1) loop
for COL in heightmap'range(2) loop
if is_low_point(heightmap, ROW, COL) then
-- Add risk level of low point to resulting sum
risk_level := 1 + heightmap(ROW, COL);
result := result + risk_level;
end if;
end loop;
end loop;
return result;
end function;
-- Types used by flooding algorithm
type flooding_map_t is array(natural range <>, natural range <>) of boolean;
type flooding_state_t is record
flooding_map : flooding_map_t;
flooding_size : natural;
end record;
-- Recursive flooding algorithm
function perform_flooding(
heightmap : heightmap_t;
flooding_state : flooding_state_t;
row : natural;
col : natural
) return flooding_state_t is
variable new_state : flooding_state_t(
flooding_map(heightmap'range(1), heightmap'range(2))
);
begin
new_state := flooding_state;
-- Flood current position
new_state.flooding_map(row, col) := true;
new_state.flooding_size := new_state.flooding_size + 1;
-- Check and flood adjacent positions
if row > 0 then
-- Check UP
if not new_state.flooding_map(row - 1, col) and heightmap(row - 1, col) /= 9 then
-- Continue flooding as position is not yet flooded and does not contain a 9
new_state := perform_flooding(heightmap, new_state, row - 1, col);
end if;
end if;
if col > 0 then
-- Check LEFT
if not new_state.flooding_map(row, col - 1) and heightmap(row, col - 1) /= 9 then
-- Continue flooding as position is not yet flooded and does not contain a 9
new_state := perform_flooding(heightmap, new_state, row, col - 1);
end if;
end if;
if col < heightmap'length(2) - 1 then
-- Check RIGHT
if not new_state.flooding_map(row, col + 1) and heightmap(row, col + 1) /= 9 then
-- Continue flooding as position is not yet flooded and does not contain a 9
new_state := perform_flooding(heightmap, new_state, row, col + 1);
end if;
end if;
if row < heightmap'length(1) - 1 then
-- Check DOWN
if not new_state.flooding_map(row + 1, col) and heightmap(row + 1, col) /= 9 then
-- Continue flooding as position is not yet flooded and does not contain a 9
new_state := perform_flooding(heightmap, new_state, row + 1, col);
end if;
end if;
return new_state;
end function;
-- Calculate size of basin around given low point
function calculate_basin_size(
heightmap : heightmap_t;
row : natural;
col : natural
) return natural is
variable flooding_state : flooding_state_t(
flooding_map(heightmap'range(1), heightmap'range(2))
);
begin
-- Run flooding algorithm on low point and return resulting flooding size
flooding_state := perform_flooding(heightmap, flooding_state, row, col);
return flooding_state.flooding_size;
end function;
-- Part Two: Calculate product of the sizes of the three largest basins
function calculate_basin_size_product(
heightmap : heightmap_t
) return natural is
variable basin_size : natural;
variable largest_basins : integer_vector(0 to 2);
variable smallest_index : natural;
begin
for ROW in heightmap'range(1) loop
for COL in heightmap'range(2) loop
if is_low_point(heightmap, ROW, COL) then
-- Determine basin size for this low point
basin_size := calculate_basin_size(heightmap, ROW, COL);
-- Find index of smallest basin in vector
smallest_index := 0;
for I in largest_basins'range loop
if largest_basins(I) < largest_basins(smallest_index) then
smallest_index := I;
end if;
end loop;
-- Update value in vector if basin is larger
if basin_size > largest_basins(smallest_index) then
largest_basins(smallest_index) := basin_size;
end if;
end if;
end loop;
end loop;
-- Return product of largest three basins
return largest_basins(0) * largest_basins(1) * largest_basins(2);
end function;
begin
process
type heightmap_ptr_t is access heightmap_t;
variable heightmap_ptr : heightmap_ptr_t;
file i_file : text;
variable i_line : line;
variable value : natural;
variable char : character;
variable row : natural;
variable result : natural;
begin
report (
"Size of heightmap in example input: " &
integer'image(EXAMPLE_HEIGHTMAP'length(1)) & "x" &
integer'image(EXAMPLE_HEIGHTMAP'length(2))
);
-- Load heightmap from input file
file_open(i_file, "inputs/day_09.txt", read_mode);
row := 0;
while not endfile(i_file) loop
readline(i_file, i_line);
if heightmap_ptr = null then
-- Assume square heightmap
heightmap_ptr := new heightmap_t(0 to i_line'length - 1, 0 to i_line'length - 1);
end if;
-- Load row of digits from line
for COL in 0 to i_line'length - 1 loop
read(i_line, char);
heightmap_ptr(row, COL) := character'pos(char) - character'pos('0');
end loop;
row := row + 1;
end loop;
file_close(i_file);
report (
"Size of heightmap in input file: " &
integer'image(heightmap_ptr'length(1)) & "x" &
integer'image(heightmap_ptr'length(2))
);
report "*** Part One ***";
result := calculate_risk_level_sum(EXAMPLE_HEIGHTMAP);
report "Risk level of example input: " & integer'image(result);
assert result = 15;
result := calculate_risk_level_sum(heightmap_ptr.all);
report "Risk level of input file: " & integer'image(result);
assert result = 423;
report "*** Part Two ***";
result := calculate_basin_size_product(EXAMPLE_HEIGHTMAP);
report "Basin size product of example input: " & integer'image(result);
assert result = 1134;
result := calculate_basin_size_product(heightmap_ptr.all);
report "Basin size product of input file: " & integer'image(result);
assert result = 1198704;
deallocate(heightmap_ptr);
wait;
end process;
end architecture;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- http://cseweb.ucsd.edu/~hepeng/cse143-w08/labs/VHDLReference/05.pdf
ENTITY proc IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
o1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Tri_out : INOUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE maxpld OF proc IS
PROCEDURE op_example (SIGNAL A : INTEGER;
SIGNAL B : INTEGER;
SIGNAL C : INTEGER;
SIGNAL bool : BOOLEAN;
SIGNAL a1 : STD_LOGIC_VECTOR(0 TO 3);
SIGNAL a2 : STD_LOGIC_VECTOR(0 TO 3))
IS
VARIABLE res : integer;
VARIABLE L : BOOLEAN;
VARIABLE M : BOOLEAN;
VARIABLE N : BOOLEAN;
VARIABLE O : BOOLEAN;
VARIABLE P : BOOLEAN;
VARIABLE V0 : BIT_VECTOR(3 DOWNTO 0);
VARIABLE B0 : BIT;
VARIABLE B1 : BIT;
VARIABLE temp : STD_LOGIC_VECTOR(0 TO 4);
VARIABLE X : STD_LOGIC_VECTOR(0 TO 4);
VARIABLE Y : STD_LOGIC_VECTOR(0 TO 4);
VARIABLE Z : STD_LOGIC_VECTOR(0 TO 4);
BEGIN
temp := std_logic_vector(unsigned(a1(0) & a1) + unsigned(a2(0) & a2));
res := A + B * C;
res := A + B * C;
res := (A + B) * C;
L := NOT BOOL AND A = 4;
L := NOT BOOL AND A = 4;
L := NOT (BOOL AND A = 4);
L := (M XOR N) AND (O XOR P);
L := M XOR (N AND (O XOR P));
L := M XOR (N AND O) XOR P;
L := (M NAND N) NAND (O NAND P);
L := (M NAND (N NAND O)) NAND P;
L := M NAND ((N NAND O) NAND P);
L := M AND (N OR O);
L := (M AND N) OR O;
V0 := NOT B0 & NOT B1;
V0 := NOT B0 & NOT B1;
V0 := NOT (B0 & NOT B1);
res := -A;
res := -(-A);
res := +A;
res := +(+A);
res := -A + B * C;
res := A + (-B) * C;
res := A + (-B) * C;
res := -(A + B * C);
res := A * 4;
res := A / 4;
res := A MOD 4;
res := A REM 4;
res := ABS(A);
res := 2 ** A;
temp := std_logic_vector(NOT (unsigned(X)) & unsigned(Y) XOR unsigned(Z) ROL 1);
temp := std_logic_vector(NOT (unsigned(X)) & unsigned(Y) XOR unsigned(Z) ROL 1);
END PROCEDURE;
FUNCTION FUNC (SIGNAL A : INTEGER;
SIGNAL B : INTEGER;
SIGNAL C : INTEGER) RETURN BIT
IS
BEGIN
END FUNCTION;
SIGNAL X : std_logic;
SIGNAL X0 : std_logic_vector(0 TO 7);
SIGNAL X1 : std_logic_vector(0 TO 7);
BEGIN
X <= A AND NOT (B OR C) AND (D(1) XOR D(2));
Tri_out <= A WHEN (B = '0') ELSE 'Z';
o1 <= "00" WHEN (D = "1000") ELSE
"01" WHEN (D = "0100") ELSE
"10" WHEN (D = "0010") ELSE
"11" WHEN (D = "0001");
X0(0 TO 3) <= X1(4 TO 7);
X0(4 TO 7) <= X1(0 TO 3);
PROCESS
VARIABLE res : bit;
BEGIN
res := FUNC(1, 2, 3);
res := FUNC(B => 2, A => 1, C => 7 MOD 4);
res := FUNC(1, 2, C => -3 + 6);
res := -(3 + 6);
WAIT;
END PROCESS;
PROCESS
BEGIN
REPORT "-5 mod (-3) : " & integer'image(-(5 MOD (-3)));
REPORT "-(5 mod (-3)) : " & integer'image(-(5 MOD (-3)));
REPORT "(-5) mod (-3) : " & integer'image((-5) MOD (-3));
REPORT "-16 ** 2 : " & integer'image(-(16 ** 2));
REPORT "-(16 ** 2) : " & integer'image(-(16 ** 2));
REPORT "(-16) ** 2 : " & integer'image((-16) ** 2);
WAIT;
END PROCESS;
END ARCHITECTURE;
|
<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
ENTITY bcdtestbench IS
END bcdtestbench;
ARCHITECTURE timing OF bcdtestbench IS
SIGNAL A: std_logic_vector (3 downto 0):="0000";
SIGNAL B: std_logic_vector (6 downto 0);
BEGIN
UUT1:ENTITY WORK.bcd (behave) PORT MAP(A);
A<=A+1 AFTER 20 us WHEN NOW<= 1000 us else"0000";
END ARCHITECTURE timing;
|
<gh_stars>1-10
-------------------------------------------------------------------------------
-- Title : Flag insertion block
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : flag_ins.vhd
-- Author : <NAME> (<EMAIL>)
-- Organization: OpenIPCore Project
-- Created :2001/01/11
-- Last update: 2001/01/26
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description: Transmit and insert flag and idle patterns
-------------------------------------------------------------------------------
-- Copyright (c) 2000 <NAME>
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 11 Jan 2001
-- Modifier : <NAME> (<EMAIL>)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity flag_ins_ent is
port (
TXclk : in std_logic; -- TX clock
rst_n : in std_logic; -- system reset
TX : out std_logic; -- TX data
TXEN : in std_logic; -- TX enable
TXD : in std_logic; -- TX input data
AbortFrame : in std_logic; -- Abort Current Frame
Frame : in std_logic); -- Valid Frame
end flag_ins_ent;
architecture flag_ins_beh of flag_ins_ent is
begin -- flag_ins_beh
-- purpose: Tranmit process
-- type : sequential
-- inputs : TXclk, rst_n
-- outputs:
process (TXclk, rst_n)
variable transmit_reg : std_logic_vector(7 downto 0); -- Transmit Register
variable state : std_logic; -- Internal state
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
transmit_reg := (others => '1');
state := '0';
TX <= '1';
elsif TXclk'event and TXclk = '1' then -- rising clock edge
if TXEN = '1' then
case state is
-- idle state
when '0' =>
TX <= transmit_reg(0);
transmit_reg(7 downto 0) := '1' & transmit_reg(7 downto 1);
if Frame = '1' and AbortFrame = '0' then
state := '1';
transmit_reg := "01111110";
end if;
-- Normal operation
when '1' =>
TX <= transmit_reg(0);
transmit_reg(7 downto 0) := TXD & transmit_reg(7 downto 1);
if AbortFrame = '1' then
transmit_reg := "11111110";
state := '0';
elsif Frame = '0' then
transmit_reg := "01111110";
state := '0';
end if;
when others => null;
end case;
else
TX <= '1';
end if; -- end TXEN
end if; -- end TXclk
end process;
end flag_ins_beh;
|
<filename>haskell/cl3sh/vhdl/MAC/mac_testinput.vhdl
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.mac_types.all;
entity mac_testinput is
port(-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
result : out mac_types.tup2);
end;
architecture structural of mac_testinput is
begin
mac_stimuligenerator_sstimuligenerator_result : entity mac_stimuligenerator_sstimuligenerator
port map
(result => result
,system1000 => system1000
,system1000_rstn => system1000_rstn);
end;
|
-- 50 MHz PS to 40 MHz PL
-- 50 *
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity SysPLL_zynq is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_zynq;
architecture xilinx of SysPLL_zynq is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "SysPLL_zynq,clk_wiz_v3_6,{component_name=SysPLL_k7,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 20.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 25.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 20.000)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => CLK_IN,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_MIPS_mux IS
END tb_MIPS_mux;
ARCHITECTURE behavior OF tb_MIPS_mux IS
constant N : integer := 32;
--Inputs
signal tb_mux_inp0 : std_logic_vector(N-1 downto 0) := (others => '0');
signal tb_mux_inp1 : std_logic_vector(N-1 downto 0) := (others => '0');
signal tb_mux_sel : std_logic := '0';
--Outputs
signal tb_mux_out : std_logic_vector(N-1 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
U1_Test: entity work.MIPS_mux(Behavioral)
generic map ( N=> 32)
PORT MAP (
mux_inp0 => tb_mux_inp0,
mux_inp1 => tb_mux_inp1,
mux_sel => tb_mux_sel,
mux_out => tb_mux_out
);
-- Stimulus process
stim_proc: process
begin -- 32 bit 2:1 mux for the MIPS
tb_mux_inp0 <= x"ABAB1010";
tb_mux_inp1 <= x"1010AAAA";
tb_mux_sel <= '0';
wait for 100ns;
tb_mux_sel <= '1';
wait for 100ns;
tb_mux_sel <= '0';
wait for 100ns;
tb_mux_sel <= '1';
wait for 100ns;
-- 6 bit 2:1 mux
-- tb_mux_inp0 <= "101010";
-- tb_mux_inp1 <= "111111";
--
-- tb_mux_sel <= '0';
-- wait for 100ns;
--
-- tb_mux_sel <= '1';
-- wait for 100ns;
--
-- tb_mux_sel <= '0';
-- wait for 100ns;
--
-- tb_mux_sel <= '1';
-- wait for 100ns;
--
assert false
report "End"
severity failure;
end process;
END;
|
<reponame>jburrell7/ReuPlus
----------------------------------------------------------------------------------
-- Creation Date: 21:12:48 05/06/2010
-- Module Name: RS232/UART Interface - Behavioral
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity timingGen is
port (
rst_n : in std_logic;
clk100 : in std_logic;
dotClk : in std_logic;
phi2 : in std_logic;
cpuWr_n : in std_logic;
phi2Sync : out std_logic;
clk16M : out std_logic;
dlyCpuWr : out std_logic;
dlyCpuRd : out std_logic;
phi2PosEdge : out std_logic;
phi2NegEdge : out std_logic;
davPos : out std_logic;
davNeg : out std_logic
);
end timingGen;
architecture Behavioral of timingGen is
component clk16MDrv
PORT
(
inclk : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
end component;
signal clk8Sync : std_logic_vector(1 downto 0);
signal clkPhiSync : std_logic_vector(3 downto 0);
signal stateCtr : integer range 0 to 15;
signal stateCtr2 : integer range 0 to 7;
signal waitCtr : integer range 0 to 63;
signal stateCtr3 : integer range 0 to 7;
signal waitCtr1 : integer range 0 to 63;
signal clk16MNode : std_logic;
begin
u1:clk16MDrv
PORT map(
inclk => clk16MNode,
outclk => clk16M
);
process(rst_n, clk100, dotClk, phi2)
begin
if (rst_n = '0') then
clk8Sync <= "00";
phi2Sync <= '0';
elsif rising_edge(clk100) then
clk8Sync <= clk8Sync(0) & dotClk;
phi2Sync <= phi2;
end if;
if (rst_n = '0') then
clkPhiSync <= "0000";
elsif rising_edge(clk100) then
clkPhiSync <= clkPhiSync(2 downto 0) & phi2;
end if;
if (rst_n = '0') then
stateCtr <= 0;
clk16MNode <= '0';
elsif rising_edge(clk100) then
case stateCtr is
when 0 =>
clk16MNode <= '0';
if (clk8Sync(1) = '1') then
clk16MNode <= '1';
stateCtr <= 1;
else
stateCtr <= 0;
end if;
when 1 =>
clk16MNode <= '1';
stateCtr <= 2;
when 2 =>
clk16MNode <= '1';
stateCtr <= 3;
when 3 =>
clk16MNode <= '0';
stateCtr <= 4;
when 4 =>
clk16MNode <= '0';
stateCtr <= 5;
when 5 =>
clk16MNode <= '0';
stateCtr <= 6;
when 6 =>
clk16MNode <= '1';
stateCtr <= 7;
when 7 =>
clk16MNode <= '1';
stateCtr <= 8;
when 8 =>
clk16MNode <= '1';
stateCtr <= 9;
when others =>
clk16MNode <= '0';
stateCtr <= 0;
end case;
end if;
if (rst_n = '0') then
stateCtr2 <= 0;
dlyCpuWr <= '0';
dlyCpuRd <= '0';
waitCtr <= 0;
elsif rising_edge(clk100) then
dlyCpuWr <= '0';
dlyCpuRd <= '0';
case stateCtr2 is
when 0 =>
if (clkPhiSync(2 downto 1) = "01") then
stateCtr2 <= 1;
else
stateCtr2 <= 0;
end if;
waitCtr <= 0;
when 1 =>
waitCtr <= waitCtr + 1;
if (waitCtr = 10) then
stateCtr2 <= 2;
else
stateCtr2 <= 1;
end if;
when 2 =>
waitCtr <= 0;
stateCtr2 <= 3;
when 3 =>
dlyCpuWr <= not cpuWr_n;
dlyCpuRd <= cpuWr_n;
waitCtr <= waitCtr + 1;
if (waitCtr = 10) then
stateCtr2 <= 4;
else
stateCtr2 <= 3;
end if;
when 4 =>
if (clkPhiSync(2 downto 1) = "10") then
stateCtr2 <= 0;
else
stateCtr2 <= 4;
end if;
when others =>
stateCtr2 <= 0;
waitCtr <= 0;
end case;
end if;
if (rst_n = '0') then
stateCtr3 <= 0;
waitCtr1 <= 0;
phi2PosEdge <= '0';
phi2NegEdge <= '0';
davPos <= '0';
davNeg <= '0';
elsif rising_edge(clk100) then
phi2PosEdge <= '0';
phi2NegEdge <= '0';
davPos <= '0';
davNeg <= '0';
case stateCtr3 is
when 0 =>
phi2PosEdge <= '0';
phi2NegEdge <= '0';
waitCtr1 <= 0;
if (clkPhiSync(1 downto 1) = "01") then
stateCtr3 <= 1;
else
stateCtr3 <= 0;
end if;
when 1 =>
waitCtr1 <= waitCtr1 + 1;
if (waitCtr1 = 40) then
stateCtr3 <= 2;
else
stateCtr3 <= 1;
end if;
if (waitCtr1 > 30) then
davPos <= '1';
end if;
if (waitCtr1 < 11) then
phi2PosEdge <= '1';
end if;
when 2 =>
waitCtr1 <= 0;
if (clkPhiSync(2 downto 1) = "10") then
stateCtr3 <= 3;
else
stateCtr3 <= 2;
end if;
when 3 =>
waitCtr1 <= waitCtr1 + 1;
if (waitCtr1 = 40) then
stateCtr3 <= 0;
else
stateCtr3 <= 3;
end if;
if (waitCtr1 > 30) then
davNeg <= '1';
end if;
if (waitCtr1 < 10) then
phi2NegEdge <= '1';
end if;
when others =>
stateCtr3 <= 0;
end case;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity simple_dualport_ram_testbench is
end simple_dualport_ram_testbench;
architecture behavior of simple_dualport_ram_testbench is
constant ADDRESS_WIDTH : integer := 5;
constant DATA_WIDTH : integer := 5;
-- Inputs
signal clk_write : std_logic := '0';
signal write_enable : std_logic := '0';
signal write_address : std_logic_vector (address_width-1 downto 0) := (others => '0');
signal write_data : std_logic_vector(data_width-1 downto 0) := (others => '0');
signal clk_read : std_logic := '0';
signal read_enable : std_logic := '0';
signal read_address : std_logic_vector (address_width-1 downto 0) := (others => '0');
-- Outputs
signal read_data : std_logic_vector (data_width-1 downto 0) := (others => '0');
signal bStartRead : std_logic := '0';
-- Clock period definition
constant clk_period : time := 5 ns;
constant clk_period2 : time := 7 ns;
begin
-- Unit under test
simple_dualport_ram_inst : entity work.simple_dualport_ram
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH
)
port map (
-- write port
clk_write => clk_write,
write_enable => write_enable,
write_address => write_address,
write_data => write_data,
-- read port
clk_read => clk_read,
read_enable => read_enable,
read_address => read_address,
read_data => read_data
);
-- Clock process definition for "clk_write"
process
begin
clk_write <= '0';
wait for clk_period/2;
clk_write <= '1';
wait for clk_period/2;
end process;
-- Clock process definition for "clk_read"
process
begin
clk_read <= '0';
wait for clk_period2/2;
clk_read <= '1';
wait for clk_period2/2;
end process;
-- read and write address processes:
process (clk_write)
begin
if rising_edge(clk_write) then
write_enable <= '1';
write_data <= std_logic_vector(shift_left(unsigned(write_address) + 1, 1));
write_address <= std_logic_vector(unsigned(write_address) + 1);
end if;
end process;
process (clk_read)
begin
if rising_edge(clk_read) then
if bStartRead = '1' then
read_enable <= '1';
read_address <= std_logic_vector(unsigned(read_address) + 1);
end if;
end if;
end process;
-- Stimulus process
process
begin
-- wait for a few data points to be written before starting the read
wait for clk_period*10;
wait until rising_edge(clk_write);
bStartRead <= '1';
wait;
end process;
end;
|
<reponame>gabrielgauthier/liboqs-test
--********************************************************************************************
--* VHDL-SIKE: a speed optimized hardware implementation of the
--* Supersingular Isogeny Key Encapsulation scheme
--*
--* Copyright (c) <NAME> and <NAME>
--*
--*********************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PE_final is
port( clk : in std_logic;
rst : in std_logic;
si_i : in std_logic_vector(1 downto 0);
ci_i : in std_logic_vector(16 downto 0); --k+1 bits
sip1_o : out std_logic_vector(15 downto 0);
cip1_o : out std_logic_vector(1 downto 0)); --k+1 bits
end PE_final;
architecture Behavioral of PE_final is
signal s_in_exp : std_logic_vector(17 downto 0);
signal c_in_exp : std_logic_vector(17 downto 0);
signal res : std_logic_vector(17 downto 0); --18 bits
begin
s_in_exp(17 downto 2) <= (others => '0');
s_in_exp(1 downto 0) <= si_i;
c_in_exp(17 downto 17) <= (others => '0');
c_in_exp(16 downto 0) <= ci_i;
res <= std_logic_vector(unsigned(s_in_exp) + unsigned(c_in_exp));
i_output_regs : process(clk) --synchronous reset
begin
if rising_edge(clk) then
if rst = '1' then
cip1_o <= (others => '0');
sip1_o <= (others => '0');
else
cip1_o(1 downto 0) <= res(17 downto 16);
sip1_o <= res(15 downto 0);
end if;
end if;
end process;
end Behavioral;
|
<filename>MRstd.vhd
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Implementa��o em hardware sintetiz�vel de uma organiza��o monociclo
-- do processador MIPS. Apenas 9 das instru��es do MIPS s�o aceitas
-- por esta organiza��o:
-- ADDU, SUBU, AAND, OOR, XXOR, NNOR, LW, SW e ORI
--
-- Vers�o Inicial - Moraes 20/setembro/2006
-- Revis�o - Ney 07/maio/2008
-- Revis�o - Ney 09/maio/2008 - removido bug do ORI
-- ORI opera agora com extens�o de 0 e n�o extens�o de sinal
-- Revisado - Ney 24/outubro/2008 - Altera��o para eliminar
-- o registrador IR e tornar a MIPS_V0 realmente
-- monociclo.
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- IMPLEMENTAR O MULTIPLEXADOR NA ENTRADA NA SAIDA DA ULA PARA APONTAR
-- ENDERE�O NA MEM�RIA (POP), ANTES DE DECREMENTAR O VALOR DE $rs
-- IMPLEMENTAR DUPLA ENTRADA NO BANCO DE REGISTRADORES PARA INSTRU��O POP
-- PERGUNTAR SE EST� CERTO wregA EM CONTROL_UNIT (SP -> LW)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- package com tipos b�sicos
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
package p_MI0 is
subtype reg32 is std_logic_vector(31 downto 0);
-- tipo para os barramentos de 32 bits
--enum com os tipos de instrucao
type inst_type is (ADDU, SUBU, AAND, OOR, XXOR, NNOR, LW, LRW, PUSH, POP, SW,
ORI, invalid_instruction);
type microinstruction is record
ce: std_logic; -- ce e rw s�o os controles da mem�ria
rw: std_logic;
i: inst_type;
wregA: std_logic; -- wregA diz se o banco de registradores deve ou n�o ser escrito
wregB: std_logic; -- wregB diz se o banco de registradores deve escrever o valor da ALU (POP)
end record;
end p_MI0;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Registrador gen�rico sens�vel � borda de subida do clock
-- com possibilidade de inicializa��o de valor
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_MI0.all;
entity reg32_ce is
generic( INIT_VALUE : reg32 := (others=>'0') );
port( ck, rst, ce : in std_logic;
D : in reg32;
Q : out reg32
);
end reg32_ce;
architecture reg32_ce of reg32_ce is
begin
process(ck, rst)
begin
if rst = '1' then
Q <= INIT_VALUE(31 downto 0);
elsif ck'event and ck = '1' then
if ce = '1' then
Q <= D;
end if;
end if;
end process;
end reg32_ce;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Banco de registradores - 31 registradores de uso geral - reg(0): cte 0
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use work.p_MI0.all;
entity reg_bank is
port( ck, rst, wregA, wregB : in std_logic;
AdRs, AdRt, adRD, adRD_2 : in std_logic_vector( 4 downto 0);
RD, RD_2 : in reg32;
R1, R2: out reg32
);
end reg_bank;
architecture reg_bank of reg_bank is
type bank is array(0 to 31) of reg32;
signal reg : bank ;
signal wen, RF : reg32 ;
begin
g1: for i in 0 to 31 generate
wen(i) <= '1' when i/=0 and ((adRD=i and wregA='1') or (adRD_2=i and wregB='1')) else '0';
RF <= RD_2 when(adRD_2=i and wregB='1') else RD;
rx: entity work.reg32_ce port map
(ck=>ck, rst=>rst, ce=>wen(i), D=>RF, Q=>reg(i));
end generate g1;
R1 <= reg(CONV_INTEGER(AdRs)); -- sele��o do fonte 1
R2 <= reg(CONV_INTEGER(AdRt)); -- sele��o do fonte 2
end reg_bank;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ALU - a opera��o depende somente da instru��o corrente que �
-- decodificada na Unidade de Controle
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.p_MI0.all;
entity alu is
port( op1, op2 : in reg32;
outalu : out reg32;
zero : out std_logic;
op_alu : in inst_type
);
end alu;
architecture alu of alu is
signal int_alu : reg32;
begin
outalu <= int_alu;
int_alu <=
op1 - op2 when op_alu=SUBU or op_alu=PUSH else
op1 and op2 when op_alu=AAND else
op1 or op2 when op_alu=OOR or op_alu=ORI else
op1 xor op2 when op_alu=XXOR else
op1 nor op2 when op_alu=NNOR else
op1 + op2; --- default � a soma
zero <= '1' when int_alu=x"00000000" else '0';
end alu;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Descri��o do Bloco de Dados (Datapath)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_signed.all;
use work.p_MI0.all;
entity datapath is
port( ck, rst : in std_logic;
i_address : out reg32;
instruction : in reg32;
d_address : out reg32;
data : inout reg32;
uins : in microinstruction;
IR_OUT : out reg32
);
end datapath;
architecture datapath of datapath is
signal incpc, ent_pc, pc_mais_offset, pc, result, R1, R2, ext32, op2, reg_destA, reg_destB : reg32;
signal adD, adD_2 : std_logic_vector(4 downto 0) ;
signal tipoR, tipoI, zero : std_logic ;
begin
tipoR <= '1' when uins.i=ADDU or uins.i=SUBU or
uins.i=AAND or uins.i=OOR or uins.i=XXOR or uins.i=NNOR or
uins.i=LRW or uins.i=PUSH or uins.i=POP else '0';
tipoI <= '1' when uins.i=LW or uins.i=ORI or uins.i=SW else '0';
--====== Hardware para a busca de instru��es =============================================
incpc <= pc + 4; --Avanca para a proxima instrucao
rpc: entity work.reg32_ce
generic map(INIT_VALUE=>x"00400000") -- ATEN��O a este VALOR!!
-- Ele depende do simulador!!
-- Para o SPIM --> use x"00400020"
-- Para o MARS --> use x"00400000"
port map(ck=>ck, rst=>rst, ce=>'1',
D=>incpc, Q=>pc);
IR_OUT <= instruction ;
-- IR_OUT � o sinal de sa�da do Bloco de Dados, que cont�m
-- o c�digo da instru��o em execu��o no momento. � passado
-- ao Bloco de Controle
i_address <= pc;
--======== hardware do banco de registradores e extens�o de sinal ou de 0 ================
adD <= instruction(15 downto 11) when tipoR='1' and not (uins.i=PUSH or uins.i=POP) else
instruction(20 downto 16) ;
-- TOMAR CUIDADO COM others=>'Z' OU colocar '0'
-- Se for zero n�o escreve no banco de registradores
adD_2 <= instruction(15 downto 11) when uins.i=POP else (others=>'Z');
REGS: entity work.reg_bank port map
(ck=>ck, rst=>rst, wregA=>uins.wregA, wregB=>uins.wregB, AdRs=>instruction(25 downto 21),
AdRt=>instruction(20 downto 16), adRD=>adD, adRD_2=>adD_2, RD=>reg_destA, RD_2=>reg_destB, R1=>R1, R2=>R2);
-- Extens�o de 0 ou extens�o de sinal
ext32 <= x"FFFF" & instruction(15 downto 0) when (instruction(15)='1'
and (uins.i=LW or uins.i=SW)) else
-- LW and SW use signal extension, ORI uses 0-extension
x"0000" & instruction(15 downto 0);
-- other instructions do not use this information,
-- thus anything is good 0 or sign extension
--========= hardware da ALU e em volta dela ==========================================
-- <NAME> POR CAUSA DA COMPARA��O
-- (SUPOSI��O -> AVALIA SE A INSTRU��O � DO TIPO PUSH OU POP ANTES DE tipoR)
op2 <= x"00000004" when uins.i=PUSH or uins.i=POP else
R2 when tipoR='1' and not (uins.i=PUSH or uins.i=POP) else ext32;
inst_alu: entity work.alu port map (op1=>R1, op2=>op2,
outalu=>result, zero=>zero, op_alu=>uins.i);
-- operacao com a mem�ria de dados
d_address <= R1 when uins.i=POP else result;
data <= R2 when uins.ce='1' and uins.rw='0' else (others=>'Z');
reg_destA <= data when uins.i=LW or uins.i=LRW or uins.i=POP else result;
reg_destB <= result;
end datapath;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Unidade de Controle - decodifica a instru��o e gera os sinais de controle
-- nesta implementa��o � um bloco puramente combinacional
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_MI0.all;
entity control_unit is
port(ck, rst: in std_logic; -- estes sinais s�o in�teis nesta vers�o da
-- Unidade de Controle, pois ela � combinacional
uins : out microinstruction;
ir : in reg32
);
end control_unit;
architecture control_unit of control_unit is
signal i : inst_type;
begin
uins.i <= i;
i <= ADDU when ir(31 downto 26)="000000" and ir(10 downto 0)="00000100001" else
SUBU when ir(31 downto 26)="000000" and ir(10 downto 0)="00000100011" else
AAND when ir(31 downto 26)="000000" and ir(10 downto 0)="00000100100" else
OOR when ir(31 downto 26)="000000" and ir(10 downto 0)="00000100101" else
XXOR when ir(31 downto 26)="000000" and ir(10 downto 0)="00000100110" else
NNOR when ir(31 downto 26)="000000" and ir(10 downto 0)="00000100111" else
LRW when ir(31 downto 26)="000000" and ir(10 downto 0)="00000101000" else
PUSH when ir(31 downto 26)="000000" and ir(10 downto 0)="00000101001" else
POP when ir(31 downto 26)="000000" and ir(10 downto 0)="00000101010" else
ORI when ir(31 downto 26)="001101" else
LW when ir(31 downto 26)="100011" else
SW when ir(31 downto 26)="101011" else
invalid_instruction ; -- IMPORTANTE: condi��o "default" � invalid instruction;
assert i /= invalid_instruction
report "******************* INVALID INSTRUCTION *************"
severity error;
uins.ce <= '1' when i=SW or i=LW or i=LRW or i=PUSH or i=POP else '0';
uins.rw <= '0' when i=SW or i=PUSH else '1';
uins.wregA <= '0' when i=SW else '1';
uins.wregB <= '1' when i=POP else '0';
end control_unit;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Topo da Hierarquia do Processador - instancia��o dos Blocos de
-- Dados e de Controle
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_MI0.all;
entity MRstd is
port( clock, reset: in std_logic;
ce, rw, bw: out std_logic;
i_address, d_address: out reg32;
instruction: in reg32;
data: inout reg32);
end MRstd;
architecture MRstd of MRstd is
signal IR: reg32;
signal uins: microinstruction;
begin
dp: entity work.datapath
port map( ck=>clock, rst=>reset, IR_OUT=>IR, uins=>uins, i_address=>i_address,
instruction=>instruction, d_address=>d_address, data=>data);
ct: entity work.control_unit port map( ck=>clock, rst=>reset, IR=>IR, uins=>uins);
ce <= uins.ce;
rw <= uins.rw;
bw <= '1'; -- Esta vers�o trabalha apenas em modo word (32 bits).
-- Logo, este sinal � in�til aqui
end MRstd;
|
--------------------------------------------------------------------------------
-- __ _ _ _ --
-- / _(_) | | | | --
-- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | --
-- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | --
-- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | --
-- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| --
-- | | --
-- |_| --
-- --
-- --
-- Peripheral-NTM for MPSoC --
-- Neural Turing Machine for MPSoC --
-- --
--------------------------------------------------------------------------------
-- Copyright (c) 2020-2021 by the author(s)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ntm_math_pkg.all;
package ntm_core_pkg is
-----------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- READ HEADS
-----------------------------------------------------------------------
component ntm_reading is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
M_IN_ENABLE : in std_logic;
R_OUT_ENABLE : out std_logic;
-- DATA
SIZE_N_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
M_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
R_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
-----------------------------------------------------------------------
-- WRITE HEADS
-----------------------------------------------------------------------
component ntm_writing is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
M_IN_ENABLE : in std_logic;
A_IN_ENABLE : in std_logic;
M_OUT_ENABLE : in std_logic;
-- DATA
SIZE_N_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
M_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
A_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
M_OUT : in std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component ntm_erasing is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
M_IN_ENABLE : in std_logic;
E_IN_ENABLE : in std_logic;
M_OUT_ENABLE : in std_logic;
-- DATA
SIZE_N_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
M_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
E_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
M_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
-----------------------------------------------------------------------
-- MEMORY
-----------------------------------------------------------------------
component ntm_content_based_addressing is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
K_IN_ENABLE : in std_logic; -- for j in 0 to J-1
M_IN_I_ENABLE : in std_logic; -- for i in 0 to I-1
M_IN_J_ENABLE : in std_logic; -- for j in 0 to J-1
C_OUT_ENABLE : out std_logic; -- for i in 0 to I-1
-- DATA
SIZE_I_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_J_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
K_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
M_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
BETA_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
C_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component ntm_addressing is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
K_IN_ENABLE : in std_logic; -- for k in 0 to W-1
S_IN_ENABLE : in std_logic; -- for k in 0 to W-1
M_IN_J_ENABLE : in std_logic; -- for j in 0 to N-1
M_IN_K_ENABLE : in std_logic; -- for k in 0 to W-1
W_IN_ENABLE : in std_logic; -- for j in 0 to N-1
W_OUT_ENABLE : out std_logic; -- for j in 0 to N-1
-- DATA
SIZE_N_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
K_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
BETA_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
G_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
S_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
GAMMA_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
M_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
W_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
-----------------------------------------------------------------------
-- TOP
-----------------------------------------------------------------------
component ntm_top is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
W_IN_L_ENABLE : in std_logic; -- for l in 0 to L-1
W_IN_X_ENABLE : in std_logic; -- for x in 0 to X-1
K_IN_I_ENABLE : in std_logic; -- for i in 0 to R-1 (read heads flow)
K_IN_L_ENABLE : in std_logic; -- for l in 0 to L-1
K_IN_K_ENABLE : in std_logic; -- for k in 0 to W-1
B_IN_ENABLE : in std_logic; -- for l in 0 to L-1
X_IN_ENABLE : in std_logic; -- for x in 0 to X-1
Y_OUT_ENABLE : out std_logic; -- for y in 0 to Y-1
-- DATA
SIZE_X_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_Y_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_N_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_L_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_R_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
K_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
B_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
X_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
Y_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component ntm_interface_vector is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
-- Key Vector
WK_IN_L_ENABLE : in std_logic; -- for l in 0 to L-1
WK_IN_K_ENABLE : in std_logic; -- for k in 0 to W-1
K_OUT_ENABLE : out std_logic; -- for k in 0 to W-1
-- Key Strength
WBETA_IN_ENABLE : in std_logic; -- for l in 0 to L-1
-- Interpolation Gate
WG_IN_ENABLE : in std_logic; -- for l in 0 to L-1
-- Shift Weighting
WS_IN_L_ENABLE : in std_logic; -- for l in 0 to L-1
WS_IN_J_ENABLE : in std_logic; -- for j in 0 to N-1
S_OUT_ENABLE : out std_logic; -- for j in 0 to N-1
-- Sharpening
WGAMMA_IN_ENABLE : in std_logic; -- for l in 0 to L-1
-- Hidden State
H_IN_ENABLE : in std_logic; -- for l in 0 to L-1
-- DATA
SIZE_N_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_L_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
WK_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
WBETA_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
WG_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
WS_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
WGAMMA_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
H_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
K_OUT : out std_logic_vector(DATA_SIZE-1 downto 0);
BETA_OUT : out std_logic_vector(DATA_SIZE-1 downto 0);
G_OUT : out std_logic_vector(DATA_SIZE-1 downto 0);
S_OUT : out std_logic_vector(DATA_SIZE-1 downto 0);
GAMMA_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component ntm_output_vector is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
K_IN_I_ENABLE : in std_logic; -- for i in 0 to R-1
K_IN_Y_ENABLE : in std_logic; -- for y in 0 to Y-1
K_IN_K_ENABLE : in std_logic; -- for k in 0 to W-1
R_IN_I_ENABLE : in std_logic; -- for i in 0 to R-1
R_IN_K_ENABLE : in std_logic; -- for j in 0 to W-1
NU_IN_ENABLE : in std_logic; -- for y in 0 to Y-1
Y_OUT_ENABLE : in std_logic; -- for y in 0 to Y-1
-- DATA
SIZE_Y_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_L_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_R_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
K_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
R_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
NU_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
Y_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component ntm_controller_output_vector is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
U_IN_Y_ENABLE : in std_logic; -- for y in 0 to Y-1
U_IN_L_ENABLE : in std_logic; -- for l in 0 to L-1
H_IN_ENABLE : in std_logic; -- for l in 0 to L-1
NU_ENABLE_OUT : out std_logic; -- for j in 0 to Y-1
-- DATA
SIZE_Y_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_L_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
U_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
H_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
NU_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
end ntm_core_pkg;
|
<reponame>KanaHayama/MyPianoPro
library verilog;
use verilog.vl_types.all;
entity FreqChange is
port(
clk_in : in vl_logic;
clk_out : out vl_logic
);
end FreqChange;
|
<reponame>sonibla/FPGA-automatic-gate
----------------------------------------------------------------------------------
-- Company: ENSEA
-- Engineer: <NAME>, <NAME>, <NAME>
--
-- Create Date: 25.02.2019 08:14:23
-- Design Name:
-- Module Name: TICK_1ms - Behavioral
-- Project Name: Portail
-- Target Devices:
-- Tool Versions:
-- Description: envoie un signal de une période d'horloge toutes les millisecondes.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TICK_1ms is
Port (
CLK : in STD_LOGIC;--Horloge
Tick : out STD_LOGIC --Signal de sortie
);
end TICK_1ms;
architecture Behavioral of TICK_1ms is
constant div : integer := 99999; --Nombre de fronts d'horloge que l'on doit compter
signal count : integer range 0 to div := 0; --Compteur
begin
process(CLK) begin
if rising_edge(CLK) then
if count = div then --on a fini de compter
count <= 0;
else
count <= count+1;
end if;
end if;
end process;
Tick <= '1' when count = 0 else '0';
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity num is
Port ( CLK,Reset,CU_D,PL: in std_logic;
cnt : out std_logic_vector(3 downto 0);
load_in: in std_logic_vector(3 downto 0));
end num;
architecture Numarator of num is
begin
process (Reset,CLK,CU_D,PL)
begin
if reset='1' then
cnt <="0000";
elsif (clk'event and clk ='1') then
if CU_D ='0' then
cnt <= cnt+1;
else
cnt <= cnt-1;
end if;
end if;
if(PL= '1') then cnt <= load_in;
end if;
end process;
end Numarator;
|
<filename>fpga/simsrc/tb_dp_dclk_ram_wr_rdwr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.etherlink_pkg.all;
entity tb_dp_dclk_ram_wr_rdwr is
end entity ; -- tb_dp_dclk_ram_wr_rdwr
architecture behav of tb_dp_dclk_ram_wr_rdwr is
constant MEM_ADDR_W : natural := 8; -- buffer address width
constant MEM_DATA_W : natural := 32; -- buffer data width
constant M2_SUPPORT_WRITE : boolean := true; -- whether port 2 is read-write (when true) or read-only (when false)
constant M2_READ_DELAY : natural := 2; -- read delay: 2=insert register at inputs
-- Port 1: write-only
signal clk1 : std_logic;
signal m1_addr : std_logic_vector(MEM_ADDR_W-1 downto 0); -- buffer address, granularity 32b words
signal m1_wdt : std_logic_vector(MEM_DATA_W-1 downto 0); -- buffer write data
signal m1_wstrobe : std_logic; -- strobe to write data into the buffer
-- Port 2: read/write
signal clk2 : std_logic;
signal m2_addr : std_logic_vector(MEM_ADDR_W-1 downto 0); -- buffer address, granularity 32b words
signal m2_wdt : std_logic_vector(MEM_DATA_W-1 downto 0); -- buffer write data
signal m2_wstrobe : std_logic; -- strobe to write data into the buffer
signal m2_rstrobe : std_logic; -- strobe to write data into the buffer
signal m2_rdt : std_logic_vector(MEM_DATA_W-1 downto 0); -- buffer write data
signal eos : boolean := false;
begin
dut: dp_dclk_ram_wr_rdwr
generic map (
MEM_ADDR_W, -- : natural := 9; -- buffer address width
MEM_DATA_W, -- : natural := 32; -- buffer data width
M2_SUPPORT_WRITE, -- : boolean := true; -- whether port 2 is read-write (when true) or read-only (when false)
M2_READ_DELAY -- : natural := 2 -- read delay: 2=insert register at inputs
)
port map (
-- Port 1: write-only
clk1, -- : in std_logic;
m1_addr, -- : in std_logic_vector(MEM_ADDR_W-1 downto 0); -- buffer address, granularity 32b words
m1_wdt, -- : in std_logic_vector(MEM_DATA_W-1 downto 0); -- buffer write data
m1_wstrobe, -- : in std_logic; -- strobe to write data into the buffer
-- Port 2: read/write
clk2, -- : in std_logic;
m2_addr, -- : in std_logic_vector(MEM_ADDR_W-1 downto 0); -- buffer address, granularity 32b words
m2_wdt, -- : in std_logic_vector(MEM_DATA_W-1 downto 0); -- buffer write data
m2_wstrobe, -- : in std_logic; -- strobe to write data into the buffer
m2_rstrobe, -- : in std_logic; -- strobe to write data into the buffer
m2_rdt -- : out std_logic_vector(MEM_DATA_W-1 downto 0) -- buffer write data
) ;
clkgen1: process
begin
if eos then wait; end if;
clk1 <= '0';
wait for 5 ns;
clk1 <= '1';
wait for 5 ns;
end process;
clk2 <= clk1;
-- clkgen2: process
-- begin
-- if eos then wait; end if;
-- clk2 <= '0';
-- wait for 5 ns;
-- clk2 <= '1';
-- wait for 5 ns;
-- end process;
tb: process
begin
m1_addr <= (others => '0');
m1_wdt <= (others => '0');
m1_wstrobe <= '0';
m2_addr <= (others => '0');
m2_wdt <= (others => '0');
m2_wstrobe <= '0';
m2_rstrobe <= '0';
wait for 10 ns;
m1_wdt <= X"000000A1";
m1_wstrobe <= '1';
wait for 10 ns;
m1_wstrobe <= '0';
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
m2_rstrobe <= '1';
wait for 10 ns;
m2_rstrobe <= '0';
wait for 100 ns;
eos <= true;
wait;
end process;
end architecture ; -- behav
|
library IEEE;
use IEEE.std_logic_1164.all;
-- MODULE SPECIFIC TO STM BAROMETER SENSOR, LPS25H WHICH GENERATES THE WRITE REGISTER COMMANDS
ENTITY LPS25H_baro_RDWR IS
PORT(
BARO_OUT,SER_CLK, RST_L : IN STD_LOGIC;
ADD : IN STD_LOGIC_VECTOR(8 downto 0);
DIN : IN STD_LOGIC_VECTOR(7 downto 0);
--__bidir_name, __bidir_name : INOUT STD_LOGIC;
BARO_SER_CLK, FIN ,CS_L : OUT STD_LOGIC;
spi_data : OUT STD_LOGIC_VECTOR(7 downto 0);
BARO_DIN : OUT STD_LOGIC);
END LPS25H_baro_RDWR;
architecture SPI_SM of LPS25h_baro_RDWR is
type state_TYPE is (S0, S1 ,S2 ,S3 ,Y0 ,Y1 ,Y2 ,Y3 ,Y4 ,Y5 ,Y6 ,Y7,
Y8 ,Y9 ,Y10 ,Y11 ,Y12 ,Y13 ,Y14 ,Y15 ,Y16 ,Y17 ,Y18);
CONSTANT ICR2 : std_logic_vector(8 downto 0) := O"077";
CONSTANT RSCNF : std_logic_vector(8 downto 0) := O"020";
CONSTANT CR1 : std_logic_vector(8 downto 0) := O"040";
CONSTANT CR2 : std_logic_vector(8 downto 0) := O"041";
CONSTANT CR3 : std_logic_vector(8 downto 0) := O"042";
CONSTANT CR4 : std_logic_vector(8 downto 0) := O"043";
CONSTANT ICNFG : std_logic_vector(8 downto 0) := O"044";
CONSTANT FFCTL : std_logic_vector(8 downto 0) := O"056";
CONSTANT PRSH : std_logic_vector(8 downto 0) := O"252";
CONSTANT PRSL : std_logic_vector(8 downto 0) := O"251";
CONSTANT PRSXL : std_logic_vector(8 downto 0) := O"250";
CONSTANT TMPH : std_logic_vector(8 downto 0) := O"254";
CONSTANT TMPL : std_logic_vector(8 downto 0) := O"253";
CONSTANT RPRSH : std_logic_vector(8 downto 0) := O"212";
CONSTANT RPRSL : std_logic_vector(8 downto 0) := O"211";
CONSTANT RPRSXL : std_logic_vector(8 downto 0) := O"210";
-- CONSTANT TBD : std_logic_vector(8 downto 0) := "00100100";
SIGNAL RD :std_logic_vector(7 downto 0);
signal pres_state, next_state :state_TYPE;
signal CS :std_logic;
SIGNAL A7:BOOLEAN;
BEGIN
SYNC: PROCESS(RST_L,SER_CLK)
begin
if (RST_L = '0') THEN
PRES_STATE <= S0;
ELSE
IF(ser_CLK='1'and ser_clk'event)THEN
PRES_STATE <= NEXT_STATE;
END IF;
END IF;
END PROCESS SYNC;
COMB: PROCESS(pres_state,add)
BEGIN
CASE PRES_STATE IS
WHEN S0 =>
case add is
when ICR2 => next_state <= s1;
when RSCNF => next_state <= s1;
when CR1 => next_state <= s1;
when CR2 => next_state <= s1;
when CR3 => next_state <= s1;
when CR4 => next_state <= s1;
when ICNFG => next_state <= s1;
when FFCTL => next_state <= s1;
when PRSH => next_state <= s1;
when PRSL => next_state <= s1;
when PRSXL => next_state <= s1;
when TMPH => next_state <= s1;
when TMPL => next_state <= s1;
when RPRSH => next_state <= s1;
when RPRSL => next_state <= s1;
when RPRSXL => next_state <= s1;
--when padch => next_state <= s1;
--when padcl => next_state <= s1;
--when tadch => next_state <= s1;
--when tadcl => next_state <= s1;
when others => next_state <= S0;
end case;
WHEN S1 => NEXT_STATE <= S2;
WHEN S2 => NEXT_STATE <= S3;
WHEN S3 => NEXT_STATE <= Y0;
WHEN Y0 => NEXT_STATE <= Y1;
WHEN Y1 => NEXT_STATE <= Y2;
WHEN Y2 => NEXT_STATE <= Y3;
WHEN Y3 => NEXT_STATE <= Y4;
WHEN Y4 => NEXT_STATE <= Y5;
WHEN Y5 => NEXT_STATE <= Y6;
WHEN Y6 => NEXT_STATE <= Y7;
WHEN Y7 => NEXT_STATE <= Y8;
WHEN Y8 => NEXT_STATE <= Y9;
WHEN Y9 => NEXT_STATE <= Y10;
WHEN Y10 => NEXT_STATE <= Y11;
WHEN Y11 => NEXT_STATE <= Y12;
WHEN Y12 => NEXT_STATE <= Y13;
WHEN Y13 => NEXT_STATE <= Y14;
WHEN Y14 => NEXT_STATE <= Y15;
WHEN Y15 => NEXT_STATE <= Y16;
WHEN Y16 => NEXT_STATE <= Y17;
WHEN Y17 => NEXT_STATE <= Y18;
WHEN Y18 => NEXT_STATE <= S0;
END CASE;
END PROCESS COMB;
latchs: PROCESS(pres_state,ser_clk,ADD(7),rd, BARO_OUT, A7, RD)
begin
IF ADD(7) = '1' THEN A7 <= TRUE;
ELSE A7 <= FALSE;
END IF;
if (ser_CLK = '0' and ser_clk'event) THEN
if ((PRES_STATE = Y8) AND A7) then
RD(7) <= BARO_OUT;
end if;
if ((PRES_STATE = Y9) AND A7) then
RD(6) <= BARO_OUT;
end if;
if ((PRES_STATE = Y10) AND A7) then
RD(5) <= BARO_OUT;
end if;
if ((PRES_STATE = Y11) AND A7) then
RD(4) <= BARO_OUT;
end if;
if ((PRES_STATE = Y12) AND A7) then
RD(3) <= BARO_OUT;
end if;
if ((PRES_STATE = Y13) AND A7) then
RD(2) <= BARO_OUT;
end if;
if ((PRES_STATE = Y14) AND A7) then
RD(1) <= BARO_OUT;
end if;
if ((PRES_STATE = Y15) AND A7) then
RD(0) <= BARO_OUT;
end if;
end if;
spi_data <= RD;
END PROCESS LATCHS;
outputs: process (pres_state,cs,add,ser_clk,din)
VARIABLE BARODIN :std_logic;
VARIABLE clken :std_logic;
VARIABLE FN :std_logic;
begin
state_driven_outputs: case pres_state is
when S0 => BARODIN :='0';clken := '0'; FN := '0';baro_ser_clk <= '1';FIN <= '0';BARO_DIN <= '0'; cs <= '1';CS_L <= cs;
when S1 => BARODIN :='0';clken := '0'; FN := '0';baro_ser_clk <= '1';FIN <= '0';BARO_DIN <= barodin; cs <= '1';CS_L <= cs;
when S2 => BARODIN :='0';clken := '0'; FN := '0';baro_ser_clk <= '1';FIN <= '0';BARO_DIN <= barodin; cs <= '1';CS_L <= cs;
when S3 => BARODIN :='0';clken := '0'; FN := '0';baro_ser_clk <= '1';FIN <= '0';BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y0 => BARODIN := ADD(7);clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y1 => BARODIN := '0';clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y2 => BARODIN := ADD(5);clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y3 => BARODIN := ADD(4);clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y4 => BARODIN := ADD(3);clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y5 => BARODIN := ADD(2);clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y6 => BARODIN := ADD(1);clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y7 => BARODIN := ADD(0);clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y8 => BARODIN := (DIN(7) and not ADD(7)); clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y9 => BARODIN := (DIN(6) and not ADD(7));clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y10 => BARODIN := (DIN(5) and not ADD(7));clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y11 => BARODIN := (DIN(4) and not ADD(7)); clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y12 => BARODIN := (DIN(3) and not ADD(7));clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y13 => BARODIN := (DIN(2) and not ADD(7));clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y14 => BARODIN := (DIN(1) and not ADD(7));clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y15 => BARODIN := (DIN(0) and not ADD(7)); clken := '1'; FN := '0';baro_ser_clk <= not ser_clk and clken;FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
When Y16 => BARODIN :='0'; clken := '0'; FN := '0';baro_ser_clk <= '1';FIN <= FN;BARO_DIN <= barodin; cs <= '0';CS_L <= cs;
when Y17 => BARODIN :='0'; clken := '0'; FN := '1';baro_ser_clk <= '1'; FIN <= FN;BARO_DIN <= '0'; cs <= '1';CS_L <= cs;
when Y18 => BARODIN :='0';clken := '0'; FN := '1';baro_ser_clk <= '1'; FIN <= FN;BARO_DIN <= '0'; cs <= '1';CS_L <= cs;
WHEN OTHERS=> clken := '0'; FN := '0';baro_ser_clk <= '1'; FIN <= '0';BARO_DIN <= '0'; cs <= '1';CS_L <= cs;
BARODIN :='0'; -- todo check this value. Added to avoid possible latch
end case state_driven_outputs;
--BARO_DIN <= barodin; --baro_ser_clk <= not ser_clk and clken;
--if (not ser_clk and clken) = "1" then baro_ser_clk <= '1' else baro_ser_clk ,='0';
--FIN <= FN;
end process OUTPUTS;
END SPI_SM;
|
-- *******************************************************************************
-- * Copyright 2016 -- 2021 IBM Corporation
-- *
-- * Licensed under the Apache License, Version 2.0 (the "License");
-- * you may not use this file except in compliance with the License.
-- * You may obtain a copy of the License at
-- *
-- * http://www.apache.org/licenses/LICENSE-2.0
-- *
-- * Unless required by applicable law or agreed to in writing, software
-- * distributed under the License is distributed on an "AS IS" BASIS,
-- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- * See the License for the specific language governing permissions and
-- * limitations under the License.
-- *******************************************************************************
-- ******************************************************************************
-- *
-- * cloudFPGA
-- *
-- *-----------------------------------------------------------------------------
-- *
-- * Title : Basic implementation of the PSoC external memory interface.
-- * File : psocEmif.vhd
-- *
-- * Created : Sep. 2017
-- * Authors : <NAME> <<EMAIL>>
-- * <NAME>
-- *
-- * Devices : xcku060-ffva1156-2-i
-- * Tools : Vivado v2016.4 (64-bit)
-- * Depends : None
-- *
-- * Description : Simplified version of the EMIF interface between the PSoC and
-- * the FPGA of the FMKU2595 module.
-- *
-- * Generics: This design instantiates a register file with a total of
-- * 2^gAddrWidth times gDataWidth bits. By default, gAddrWidth=gDataWidth=8
-- * which implements a register file of 256 registers times 8 bits.
-- *
-- *-----------------------------------------------------------------------------
-- *
-- * Note: The EMIF I/F of the PSOC is expected to be configured as follows:
-- * - External Memory Type : Synchronous
-- * - Address Width : 8 bits
-- * - Data Width : 8 bits
-- * - External Memory Speed : 30 ns
-- * - Bus Clock Frequency : 24 MHz
-- * - Write cycle Length : 166.7 ns (4 cycles)
-- * - Read cycle Length : 166.7 ns (4 cycles)
-- * - WriteEn Pulse Width : 41.7 ns (1 cycle)
-- * - OutputEn Pulse Width : 125 ns (3 cycles)
-- *
-- ******************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;sBus_
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
--*************************************************************************
--** ENTITY
--*************************************************************************
entity PsocExtMemItf is
generic (
gAddrWidth : integer := 7;
gDataWidth : integer := 8;
gDefRegVal : std_logic_vector
);
port (
-- Global Resets input -----------------------
piRst : in std_logic;
-- CPU/DMA Bus Interface ---------------------
piBus_Clk : in std_logic;
piBus_Cs_n : in std_logic;
piBus_We_n : in std_logic;
piBus_Addr : in std_logic_vector(gAddrWidth - 1 downto 0);
piBus_Data : in std_logic_vector(gDataWidth - 1 downto 0);
poBus_Data : out std_logic_vector(gDataWidth - 1 downto 0);
-- Internal FPGA Fabric Interface
piFab_Clk : in std_logic;
piFab_Data : in std_logic_vector(gDataWidth * (2**gAddrWidth) - 1 downto 0);
poFab_Data : out std_logic_vector(gDataWidth * (2**gAddrWidth) - 1 downto 0)
);
end PsocExtMemItf;
--*************************************************************************
--** ARCHITECTURE
--*************************************************************************
architecture Behavioral of PsocExtMemItf is
constant cTREG : time := 2 ns;
constant cDEPTH : integer := gDataWidth * (2**gAddrWidth);
signal sBus_ClkMts : std_logic;
signal sBus_ClkReg : std_logic;
signal sBus_ClkRegReg : std_logic;
-- Emif Bus Interface
signal sBus_Cs_n : std_logic;
signal sBus_We_n : std_logic;
signal sBus_Addr : std_logic_vector(gAddrWidth - 1 downto 0);
signal sBus_Data : std_logic_vector(gDataWidth - 1 downto 0);
signal sEmifReg : std_logic_vector(cDEPTH - 1 downto 0);
-- Fpga Fabric Interface
signal sFab_Data : std_logic_vector(cDEPTH - 1 downto 0);
begin -- architecture rtl
-----------------------------------------------------------------
-- SREG: Source Synchronous Registering of the Input Bus Signals
-----------------------------------------------------------------
pInpBusReg: process (piBus_Clk, piRst) is
begin
if rising_edge(piBus_Clk) then
sBus_Cs_n <= piBus_Cs_n after cTREG;
sBus_We_n <= piBus_We_n after cTREG;
sBus_Data <= piBus_Data after cTREG;
sBus_Addr <= piBus_Addr after cTREG;
end if;
end process pInpBusReg;
---------------------------------------------------------------
-- REG: Clock domain crossing for the incoming bus clock pulse
---------------------------------------------------------------
pBusClkToFabClkReg: process (piFab_Clk) is
begin
if rising_edge(piFab_Clk) then
-- Synchronizer to avaoid metastability (Mts)
sBus_ClkMts <= piBus_Clk after cTREG;
sBus_ClkReg <= sBus_ClkMts after cTREG;
end if;
end process pBusClkToFabClkReg;
----------------------------------------------------------
-- REG: MMIO Write Cycle
----------------------------------------------------------
pMmioWrReg : process (piFab_Clk, piRst) is
variable vAddr : integer := 0;
begin
if (piRst = '1') then
sEmifReg <= gDefRegVal;
elsif rising_edge(piFab_Clk) then
sBus_ClkRegReg <= sBus_ClkReg after cTREG;
-- On rising edge of the Bus clcok
if (sBus_ClkRegReg = '1' and sBus_ClkReg = '0') then
if (sBus_Cs_n = '0' and sBus_We_n = '0') then
-- Write cycle accesss
vAddr := to_integer(unsigned(sBus_Addr));
vAddr := vAddr * gDataWidth;
sEmifReg(vAddr + 7 downto vAddr) <= sBus_Data;
end if;
end if;
end if;
end process pMmioWrReg;
----------------------------------------------------------
-- COMB: MMIO Read Cycle
----------------------------------------------------------
pMmioRdComb: process (sFab_Data, sBus_Addr) is
variable vAddr : integer := 0;
begin
vAddr := to_integer(unsigned(sBus_Addr));
vAddr := vAddr * gDataWidth;
poBus_Data <= sFab_Data(vAddr + 7 downto vAddr);
end process pMmioRdComb;
----------------------------------------------------------
-- REG: Register data signals from the fabric
----------------------------------------------------------
pFabInpReg: process (piFab_Clk) is
begin
if rising_edge(piFab_Clk) then
sFab_Data <= piFab_Data after cTREG;
end if;
end process pFabInpReg;
----------------------------------------------------------
-- Output Ports Assignment
----------------------------------------------------------
poFab_Data <= sEmifReg;
end Behavioral;
|
library IEEE;use
IEEE.STD_LOGIC_1164.ALL;use
IEEE.STD_LOGIC_ARITH.ALL;use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Stack_Pointer is
Port (RST : in std_logic;
LD : in std_logic;
INCR : in std_logic;
DECR : in std_logic;
CLK :in std_logic;
DATA : in std_logic_vector (7 downto 0);
SP_OUT : out std_logic_vector (7 downto 0));
end Stack_Pointer;
architecture Behavioral of Stack_Pointer is
signal count : std_logic_vector (7 downto 0) := x"00";
begin
Process(CLK,RST,INCR,DECR)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
count <= x"00";
else
if(LD = '1') then
count <= DATA;
end if;
if(INCR = '1') then
count <= count + 1;
end if;
if(DECR = '1') then
count <= count - 1;
end if;
end if;
end if;
end process;
SP_OUT <= count;
end Behavioral;
|
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