KlaraHDL/hardware_code_and_sec_small · Datasets at Hugging Face

content stringlengths 0 376M
<reponame>oddek/CacheController_DDV3101 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 09/30/2020 09:53:55 AM -- Design Name: -- Module Name: OneToFourDemux - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity OneToFourDemux is Port ( i0 : in STD_LOGIC_VECTOR (31 downto 0); sel : in STD_LOGIC_VECTOR (1 downto 0); en : in STD_LOGIC; Y0 : out STD_LOGIC_VECTOR (31 downto 0); Y1 : out STD_LOGIC_VECTOR (31 downto 0); Y2 : out STD_LOGIC_VECTOR (31 downto 0); Y3 : out STD_LOGIC_VECTOR (31 downto 0)); end OneToFourDemux; architecture Behavioral of OneToFourDemux is begin process(i0, sel) is begin case sel is when "00" => Y0 <= i0; when "01" => Y1 <= i0; when "10" => Y2 <= i0; when others => Y3 <= i0; end case; end process; end Behavioral;
<filename>Exercise3/Multiplication/output_files/package.vhd ----- Libraries ----- LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -----Package---- package easy is constant iBits : integer; end easy; package body easy is constant iBits : integer := 8; end package body easy;
<reponame>ChibiKev/Single-Cycle-CPU library verilog; use verilog.vl_types.all; entity Chen_Kevin_Single_Cycle_CPU_Board is port( Chen_Kevin_Segment_A0: out vl_logic; Chen_Kevin_Clock: in vl_logic; Chen_Keivn_Reset: in vl_logic; Chen_Kevin_Segment_B0: out vl_logic; Chen_Kevin_Segment_C0: out vl_logic; Chen_Kevin_Segment_D0: out vl_logic; Chen_Kevin_Segment_E0: out vl_logic; Chen_Kevin_Segment_F0: out vl_logic; Chen_Kevin_Segment_G0: out vl_logic; Chen_Kevin_Segment_A1: out vl_logic; Chen_Kevin_Segment_B1: out vl_logic; Chen_Kevin_Segment_C1: out vl_logic; Chen_Kevin_Segment_D1: out vl_logic; Chen_Kevin_Segment_E1: out vl_logic; Chen_Kevin_Segment_F1: out vl_logic; Chen_Kevin_Segment_G1: out vl_logic; Chen_Kevin_Segment_A2: out vl_logic; Chen_Kevin_Segment_B2: out vl_logic; Chen_Kevin_Segment_C2: out vl_logic; Chen_Kevin_Segment_D2: out vl_logic; Chen_Kevin_Segment_E2: out vl_logic; Chen_Kevin_Segment_F2: out vl_logic; Chen_Kevin_Segment_G2: out vl_logic; Chen_Kevin_Segment_A3: out vl_logic; Chen_Kevin_Segment_B3: out vl_logic; Chen_Kevin_Segment_C3: out vl_logic; Chen_Kevin_Segment_D3: out vl_logic; Chen_Kevin_Segment_E3: out vl_logic; Chen_Kevin_Segment_F3: out vl_logic; Chen_Kevin_Segment_G3: out vl_logic; Chen_Kevin_Segment_A4: out vl_logic; Chen_Kevin_Segment_B4: out vl_logic; Chen_Kevin_Segment_C4: out vl_logic; Chen_Kevin_Segment_D4: out vl_logic; Chen_Kevin_Segment_E4: out vl_logic; Chen_Kevin_Segment_F4: out vl_logic; Chen_Kevin_Segment_G4: out vl_logic; Chen_Kevin_Segment_A5: out vl_logic; Chen_Kevin_Segment_B5: out vl_logic; Chen_Kevin_Segment_C5: out vl_logic; Chen_Kevin_Segment_D5: out vl_logic; Chen_Kevin_Segment_E5: out vl_logic; Chen_Kevin_Segment_F5: out vl_logic; Chen_Kevin_Segment_G5: out vl_logic; Chen_Kevin_Segment_A6: out vl_logic; Chen_Kevin_Segment_B6: out vl_logic; Chen_Kevin_Segment_C6: out vl_logic; Chen_Kevin_Segment_D6: out vl_logic; Chen_Kevin_Segment_E6: out vl_logic; Chen_Kevin_Segment_F6: out vl_logic; Chen_Kevin_Segment_G6: out vl_logic; Chen_Kevin_Segment_A7: out vl_logic; Chen_Kevin_Segment_B7: out vl_logic; Chen_Kevin_Segment_C7: out vl_logic; Chen_Kevin_Segment_D7: out vl_logic; Chen_Kevin_Segment_E7: out vl_logic; Chen_Kevin_Segment_F7: out vl_logic; Chen_Kevin_Segment_G7: out vl_logic; Chen_Kevin_Op : out vl_logic_vector(3 downto 0) ); end Chen_Kevin_Single_Cycle_CPU_Board;
-------------------------------------------------------------------------------- -- __ _ _ _ -- -- / _(_) \| \| \| \| -- -- __ _ _ _ ___ ___ _ __ \| \|_ _ ___\| \| __\| \| -- -- / _` \| \| \| \|/ _ \/ _ \ '_ \\| _\| \|/ _ \ \|/ _` \| -- -- \| (_\| \| \|_\| \| __/ __/ \| \| \| \| \| \| __/ \| (_\| \| -- -- \__, \|\__,_\|\___\|\___\|_\| \|_\|_\| \|_\|\___\|_\|\__,_\| -- -- \| \| -- -- \|_\| -- -- -- -- -- -- Peripheral-NTM for MPSoC -- -- Neural Turing Machine for MPSoC -- -- -- -------------------------------------------------------------------------------- -- Copyright (c) 2020-2021 by the author(s) -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.ntm_state_pkg.all; use work.ntm_state_top_pkg.all; entity ntm_state_top_testbench is generic ( -- SYSTEM-SIZE DATA_SIZE : integer := 32; CONTROL_SIZE : integer := 64; X : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- x in 0 to X-1 Y : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- y in 0 to Y-1 N : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- j in 0 to N-1 W : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- k in 0 to W-1 L : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- l in 0 to L-1 R : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- i in 0 to R-1 -- FUNCTIONALITY ENABLE_NTM_STATE_TOP_TEST : boolean := false; ENABLE_NTM_STATE_TOP_CASE_0 : boolean := false; ENABLE_NTM_STATE_TOP_CASE_1 : boolean := false ); end ntm_state_top_testbench; architecture ntm_state_top_testbench_architecture of ntm_state_top_testbench is ----------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------- -- GLOBAL signal CLK : std_logic; signal RST : std_logic; -- TOP -- CONTROL signal start_top : std_logic; signal ready_top : std_logic; signal data_a_i_in_enable_state_top : std_logic; signal data_a_j_in_enable_state_top : std_logic; signal data_b_i_in_enable_state_top : std_logic; signal data_b_j_in_enable_state_top : std_logic; signal data_c_i_in_enable_state_top : std_logic; signal data_c_j_in_enable_state_top : std_logic; signal data_d_i_in_enable_state_top : std_logic; signal data_d_j_in_enable_state_top : std_logic; signal data_k_in_i_enable_state_top : std_logic; signal data_k_in_j_enable_state_top : std_logic; signal data_k_i_enable_state_top : std_logic; signal data_k_j_enable_state_top : std_logic; signal data_x_out_enable_state_top : std_logic; signal data_y_out_enable_state_top : std_logic; -- DATA signal size_a_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_a_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_b_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_b_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_c_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_c_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_d_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_d_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal data_a_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_b_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_c_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_d_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_k_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_x_out_state_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_y_out_state_top : std_logic_vector(DATA_SIZE-1 downto 0); begin ----------------------------------------------------------------------- -- Body ----------------------------------------------------------------------- -- STIMULUS state_top_stimulus : ntm_state_top_stimulus generic map ( -- SYSTEM-SIZE DATA_SIZE => DATA_SIZE, CONTROL_SIZE => CONTROL_SIZE, X => X, Y => Y, N => N, W => W, L => L, R => R ) port map ( -- GLOBAL CLK => CLK, RST => RST, -- CONTROL NTM_STATE_TOP_START => start_top, NTM_STATE_TOP_READY => ready_top, NTM_STATE_TOP_DATA_A_IN_I_ENABLE => data_a_i_in_enable_state_top, NTM_STATE_TOP_DATA_A_IN_J_ENABLE => data_a_j_in_enable_state_top, NTM_STATE_TOP_DATA_B_IN_I_ENABLE => data_b_i_in_enable_state_top, NTM_STATE_TOP_DATA_B_IN_J_ENABLE => data_b_j_in_enable_state_top, NTM_STATE_TOP_DATA_C_IN_I_ENABLE => data_c_i_in_enable_state_top, NTM_STATE_TOP_DATA_C_IN_J_ENABLE => data_c_j_in_enable_state_top, NTM_STATE_TOP_DATA_D_IN_I_ENABLE => data_d_i_in_enable_state_top, NTM_STATE_TOP_DATA_D_IN_J_ENABLE => data_d_j_in_enable_state_top, NTM_STATE_TOP_DATA_K_IN_I_ENABLE => data_k_in_i_enable_state_top, NTM_STATE_TOP_DATA_K_IN_J_ENABLE => data_k_in_j_enable_state_top, NTM_STATE_TOP_DATA_K_I_ENABLE => data_k_i_enable_state_top, NTM_STATE_TOP_DATA_K_J_ENABLE => data_k_j_enable_state_top, NTM_STATE_TOP_DATA_X_OUT_ENABLE => data_x_out_enable_state_top, NTM_STATE_TOP_DATA_Y_OUT_ENABLE => data_y_out_enable_state_top, -- DATA NTM_STATE_TOP_SIZE_A_I_IN => size_a_i_in_top, NTM_STATE_TOP_SIZE_A_J_IN => size_a_j_in_top, NTM_STATE_TOP_SIZE_B_I_IN => size_b_i_in_top, NTM_STATE_TOP_SIZE_B_J_IN => size_b_j_in_top, NTM_STATE_TOP_SIZE_C_I_IN => size_c_i_in_top, NTM_STATE_TOP_SIZE_C_J_IN => size_c_j_in_top, NTM_STATE_TOP_SIZE_D_I_IN => size_d_i_in_top, NTM_STATE_TOP_SIZE_D_J_IN => size_d_j_in_top, NTM_STATE_TOP_DATA_A_IN => data_a_in_top, NTM_STATE_TOP_DATA_B_IN => data_b_in_top, NTM_STATE_TOP_DATA_C_IN => data_c_in_top, NTM_STATE_TOP_DATA_D_IN => data_d_in_top, NTM_STATE_TOP_DATA_K_IN => data_k_in_top, NTM_STATE_TOP_DATA_X_OUT => data_x_out_state_top, NTM_STATE_TOP_DATA_Y_OUT => data_y_out_state_top ); -- TOP ntm_state_top_test : if (ENABLE_NTM_STATE_TOP_TEST) generate state_top : ntm_state_top generic map ( DATA_SIZE => DATA_SIZE, CONTROL_SIZE => CONTROL_SIZE ) port map ( -- GLOBAL CLK => CLK, RST => RST, -- CONTROL START => start_top, READY => ready_top, DATA_A_IN_I_ENABLE => data_a_i_in_enable_state_top, DATA_A_IN_J_ENABLE => data_a_j_in_enable_state_top, DATA_B_IN_I_ENABLE => data_b_i_in_enable_state_top, DATA_B_IN_J_ENABLE => data_b_j_in_enable_state_top, DATA_C_IN_I_ENABLE => data_c_i_in_enable_state_top, DATA_C_IN_J_ENABLE => data_c_j_in_enable_state_top, DATA_D_IN_I_ENABLE => data_d_i_in_enable_state_top, DATA_D_IN_J_ENABLE => data_d_j_in_enable_state_top, DATA_K_IN_I_ENABLE => data_k_in_i_enable_state_top, DATA_K_IN_J_ENABLE => data_k_in_j_enable_state_top, DATA_K_I_ENABLE => data_k_i_enable_state_top, DATA_K_J_ENABLE => data_k_j_enable_state_top, DATA_X_OUT_ENABLE => data_x_out_enable_state_top, DATA_Y_OUT_ENABLE => data_y_out_enable_state_top, -- DATA SIZE_A_I_IN => size_a_i_in_top, SIZE_A_J_IN => size_a_j_in_top, SIZE_B_I_IN => size_b_i_in_top, SIZE_B_J_IN => size_b_j_in_top, SIZE_C_I_IN => size_c_i_in_top, SIZE_C_J_IN => size_c_j_in_top, SIZE_D_I_IN => size_d_i_in_top, SIZE_D_J_IN => size_d_j_in_top, DATA_A_IN => data_a_in_top, DATA_B_IN => data_b_in_top, DATA_C_IN => data_c_in_top, DATA_D_IN => data_d_in_top, DATA_K_IN => data_k_in_top, DATA_X_OUT => data_x_out_state_top, DATA_Y_OUT => data_y_out_state_top ); end generate ntm_state_top_test; end ntm_state_top_testbench_architecture;
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-- USN VHDL 101 course -- template for test bench development -- author \| date library ieee; use ieee.std_logic_1164.all; entity tb_module_name is end tb_module_name; architecture tb of tb_module_name is component module_name port (clk, reset : in std_logic; ... : in std_logic; ... : in std_logic_vector(M downto 0); ... : out std_logic; ... : out std_logic_vector(N downto 0) ); end component; signal clk, reset : std_logic; signal ... : std_logic; -- module inputs signal ... : std_logic_vector(M downto 0); -- module inputs signal ... : std_logic; -- module outputs signal ... : std_logic_vector(N downto 0); -- module outputs constant clk_period : time := 10 ns; begin uut : module_name port map (clk => clk, reset => reset, ... => ..., ... => ..., ... => ..., ... => ...); clk_process: process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimuli process stim_proc: process begin ... <= '0'; reset <= '1'; wait for clk_period2; reset <= '0'; ... <= '1'; ... wait for clk_period...; ... end process ; end tb;
library IEEE; use IEEE.STD_LOGIC_1164.all; use work.all; entity EX_MEM_DIV is port ( --INPUTS clock, clear : in std_logic; --MEM control signals data_format_in : in std_logic_vector(2 downto 0); datamem_write_in : in std_logic; jump_flag_in : in std_logic; --WB control signals mux0_sel_in : in std_logic_vector(1 downto 0); reg_file_write_in : in std_logic; reg_file_write_address_in : in std_logic_vector(4 downto 0); --Data ALU_output_in : in std_logic_vector(31 downto 0); register_file_output_1_in : in std_logic_vector(31 downto 0); ALU_branch_response_in : in std_logic; instruction_address_in : in std_logic_vector(31 downto 0); --OUTPUTS --MEM control signals data_format_out : out std_logic_vector(2 downto 0); datamem_write_out : out std_logic; jump_flag_out : out std_logic; --WB control signals mux0_sel_out : out std_logic_vector(1 downto 0); reg_file_write_out : out std_logic; reg_file_write_address_out : out std_logic_vector(4 downto 0); --Data ALU_output_out : out std_logic_vector(31 downto 0); register_file_output_1_out : out std_logic_vector(31 downto 0); ALU_branch_response_out : out std_logic; instruction_address_out : out std_logic_vector(31 downto 0) ); end EX_MEM_DIV; architecture behavioral of EX_MEM_DIV is --INTERNAL SIGNALS --MEM control signals signal data_format_input_signal : std_logic_vector(2 downto 0); signal datamem_write_input_signal : std_logic; signal jump_flag_input_signal : std_logic; --WB control signals signal mux0_sel_input_signal : std_logic_vector(1 downto 0); signal reg_file_write_input_signal : std_logic; signal reg_file_write_address_input_signal : std_logic_vector(4 downto 0); --Data signal ALU_output_input_signal : std_logic_vector(31 downto 0); signal register_file_output_1_input_signal : std_logic_vector(31 downto 0); signal ALU_branch_response_input_signal : std_logic; signal instruction_address_input_signal : std_logic_vector(31 downto 0); --MEM control signals signal data_format_output_signal : std_logic_vector(2 downto 0); signal datamem_write_output_signal : std_logic; signal jump_flag_output_signal : std_logic; --WB control signals signal mux0_sel_output_signal : std_logic_vector(1 downto 0); signal reg_file_write_output_signal : std_logic; signal reg_file_write_address_output_signal : std_logic_vector(4 downto 0); --Data signal ALU_output_output_signal : std_logic_vector(31 downto 0); signal register_file_output_1_output_signal : std_logic_vector(31 downto 0); signal ALU_branch_response_output_signal : std_logic; signal instruction_address_output_signal : std_logic_vector(31 downto 0); begin --INTERNAL REGISTERS --MEM control signals data_format_reg : reg3b port map(data_format_input_signal, '1', clock, clear, data_format_output_signal); datamem_write_reg : reg1b port map(datamem_write_input_signal, '1', clock, clear, datamem_write_output_signal); jump_flag_reg : reg1b port map(jump_flag_input_signal, '1', clock, clear, jump_flag_output_signal); --WB control signals mux0_sel_reg : reg2b port map(mux0_sel_input_signal, '1', clock, clear, mux0_sel_output_signal); reg_file_write_reg : reg1b port map(reg_file_write_input_signal, '1', clock, clear, reg_file_write_output_signal); reg_file_write_address_reg : reg5b port map(reg_file_write_address_input_signal, '1', clock, clear, reg_file_write_address_output_signal); --Data ALU_output_reg : reg32b port map(ALU_output_input_signal, '1', clock, clear, ALU_output_output_signal); register_file_output_1_reg : reg32b port map(register_file_output_1_input_signal, '1', clock, clear, register_file_output_1_output_signal); ALU_branch_respose_reg : reg1b port map(ALU_branch_response_input_signal, '1', clock, clear, ALU_branch_response_output_signal); instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal); --WIRING INPUT PORTS --MEM control signals data_format_input_signal <= data_format_in; datamem_write_input_signal <= datamem_write_in; jump_flag_input_signal <= jump_flag_in; --WB control signals mux0_sel_input_signal <= mux0_sel_in; reg_file_write_input_signal <= reg_file_write_in; reg_file_write_address_input_signal <= reg_file_write_address_in; --Data ALU_output_input_signal <= ALU_output_in; register_file_output_1_input_signal <= register_file_output_1_in; ALU_branch_response_input_signal <= ALU_branch_response_in; instruction_address_input_signal <= instruction_address_in; --WIRING OUTPUT PORTS --MEM control signals data_format_out <= data_format_output_signal; datamem_write_out <= datamem_write_output_signal; jump_flag_out <= jump_flag_output_signal; --WB control signals mux0_sel_out <= mux0_sel_output_signal; reg_file_write_out <= reg_file_write_output_signal; reg_file_write_address_out <= reg_file_write_address_output_signal; --Data ALU_output_out <= ALU_output_output_signal; register_file_output_1_out <= register_file_output_1_output_signal; ALU_branch_response_out <= ALU_branch_response_output_signal; instruction_address_out <= instruction_address_output_signal; end behavioral;
<gh_stars>1-10 library ieee; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity content_final_work_v2 is PORT(clk : IN STD_LOGIC; SEG_LED : OUT STD_LOGIC_VECTOR(6 downto 0); SEG_NCS : OUT STD_LOGIC_VECTOR(5 downto 0); segdot : OUT STD_LOGIC; key1 : IN STD_LOGIC; --keyTimeSet-按键1-进入时间设置模式 key2 : IN STD_LOGIC; --keyClockSet-按键2-进入闹钟设置模式 key5 : IN STD_LOGIC; --keyQuitClock-按键5-停止闹钟 key6 : IN STD_LOGIC; --keyNumAdd-按键6-选中的数字增加1 key7 : IN STD_LOGIC --keyLeftMove-按键7-左移选中数字 ); END content_final_work_v2; ARCHITECTURE behav OF content_final_work_v2 IS SIGNAL bcd_led : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others=>'0'); SIGNAL clkcnt : STD_LOGIC_VECTOR(30 DOWNTO 0) := (others =>'0'); SIGNAL bcddata_Time : STD_LOGIC_VECTOR(23 downto 0) := (others=>'0'); --当前时间的bcddata SIGNAL bcddata_TimeSet : STD_LOGIC_VECTOR(23 downto 0):=(others=>'0'); --设置时间的bcddata SIGNAL bcddata_ClockSet : STD_LOGIC_VECTOR(23 downto 0):=(others=>'0'); --设置闹钟的bcddata SIGNAL a: integer range 0 to 249999999 :=0; SIGNAL clk_1Hz,q : STD_LOGIC :='0'; SIGNAL clk_1Hz_4vectors : STD_LOGIC_VECTOR(3 DOWNTO 0) :="0000"; SIGNAL keyTimeSetfilt : STD_LOGIC := '0'; --按键1的脉冲信号 SIGNAL TimeSetting : STD_LOGIC := '1'; SIGNAL keyClockSetfilt : STD_LOGIC := '0'; --按键2的脉冲信号 SIGNAL ClockSetting : STD_LOGIC := '1'; SIGNAL keyClockQuitfilt : STD_LOGIC := '0'; --按键5的脉冲信号 SIGNAL ClockTwinkling : STD_LOGIC := '0'; SIGNAL keyNumAddfilt : STD_LOGIC := '0'; --按键6的脉冲信号 SIGNAL keyLeftMovefilt : STD_LOGIC := '0'; --按键7的脉冲信号 SIGNAL LeftMoving : BIT_VECTOR(4 DOWNTO 0) :="11110"; --选中的数字 SHARED VARIABLE displayMode : integer := 0; --数码管的显示模式：若为0则是当前时间，若为1则是设置时间，若为2则是闹钟时间 component keyfilt is port (clk : IN STD_LOGIC; keyTimeSet : IN STD_LOGIC; keyTimeSetfilt : OUT STD_LOGIC; keyClockSet : IN STD_LOGIC; keyClockSetfilt : OUT STD_LOGIC; keyClockQuit : IN STD_LOGIC; keyClockQuitfilt : OUT STD_LOGIC; keyNumAdd : IN STD_LOGIC; keyNumAddfilt : OUT STD_LOGIC; keyLeftMove : IN STD_LOGIC; keyLeftMovefilt : OUT STD_LOGIC ); end component keyfilt; BEGIN akeyfilt: keyfilt port map ( clk =>clk, keyTimeSet => key1, keyTimeSetfilt =>keyTimeSetfilt, keyClockSet => key2, keyClockSetfilt =>keyClockSetfilt, keyClockQuit => key5, keyClockQuitfilt =>keyClockQuitfilt, keyNumAdd => key6, keyNumAddfilt => keyNumAddfilt, keyLeftMove => key7, keyLeftMovefilt => keyLeftMovefilt ); process(clk,clkcnt) begin if(rising_edge(clk))then clkcnt<= clkcnt + 1; end if; end process; process(clk) --产生1Hz时钟脉冲 begin if(clk'event and clk='1') then if a=24999999 then a<=0; q<= not q; clk_1Hz_4vectors <= NOT clk_1Hz_4vectors; else a<=a+1; end if; end if; clk_1Hz <= q; end process; process(clk, clk_1Hz) begin if clk = '1' then if keyClockQuitfilt = '1' then --若按键5按下，则退出闹钟闪烁 ClockTwinkling <= '0'; elsif keyTimeSetfilt = '1' then --若按键1按下，则进入时间设置 bcddata_Time <= bcddata_TimeSet; elsif clk_1Hz'event and clk_1Hz='1' then --当前时间的计数 if bcddata_Time(3 downto 0)=x"9" then bcddata_Time(3 downto 0)<=x"0"; else bcddata_Time(3 downto 0)<=bcddata_Time(3 downto 0)+1; end if; if bcddata_Time(7 downto 0)=x"59" then bcddata_Time(7 downto 0)<=x"00"; elsif bcddata_Time(3 downto 0)=x"9" then bcddata_Time(7 downto 4)<=bcddata_Time(7 downto 4)+1; end if; if bcddata_Time(11 downto 0)=x"959" then bcddata_Time(11 downto 0)<=x"000"; elsif bcddata_Time(7 downto 0)=x"59" then bcddata_Time(11 downto 8)<=bcddata_Time(11 downto 8)+1; end if; if bcddata_Time(15 downto 0)=x"5959" then bcddata_Time(15 downto 0)<=x"0000"; elsif bcddata_Time(11 downto 0) =x"959" then bcddata_Time(15 downto 12)<=bcddata_Time(15 downto 12)+1; end if; if bcddata_Time(19 downto 0)=x"95959" then bcddata_Time(19 downto 0)<=x"00000"; elsif bcddata_Time(15 downto 0) =x"5959" then bcddata_Time(19 downto 16)<=bcddata_Time(19 downto 16)+1; end if; if bcddata_Time(23 downto 0)=x"235959" then bcddata_Time(23 downto 0)<=x"000000"; elsif bcddata_Time(19 downto 0) =x"95959" then bcddata_Time(23 downto 20)<=bcddata_Time(23 downto 20)+1; end if; if (bcddata_Time = bcddata_ClockSet OR ClockTwinkling = '1') then --若当前时间的bcddata与闹钟时间的bcddata相等，则进入闹钟闪烁 ClockTwinkling <= '1'; end if; end if; end if; end process; process(keyNumAddfilt) begin if ((keyNumAddfilt'event AND keyNumAddfilt='1') AND TimeSetting = '0') OR ((keyNumAddfilt'event AND keyNumAddfilt='1') AND ClockSetting = '0')then if displayMode = 1 then --如果是显示模式1（即时间设置模式），则对时间设置模式的bcddata进行操作 case leftMoving is when "11110" => bcddata_TimeSet(3 downto 0)<=bcddata_TimeSet(3 downto 0)+1; --设置秒针个位数 when "11101" => bcddata_TimeSet(7 downto 4)<=bcddata_TimeSet(7 downto 4)+1; --设置秒针十位数 when "11011" => bcddata_TimeSet(11 downto 8)<=bcddata_TimeSet(11 downto 8)+1; --设置分针个位数 when "10111" => bcddata_TimeSet(15 downto 12)<=bcddata_TimeSet(15 downto 12)+1; --设置分针十位数 when "01111" => bcddata_TimeSet(19 downto 16)<=bcddata_TimeSet(19 downto 16)+1; --设置时针 when others => NULL; end case; if bcddata_TimeSet(3 downto 0)=x"9" then bcddata_TimeSet(3 downto 0)<=x"0"; end if; if bcddata_TimeSet(7 downto 4)=x"5" then bcddata_TimeSet(7 downto 4)<=x"0"; end if; if bcddata_TimeSet(11 downto 8)=x"9" then bcddata_TimeSet(11 downto 8)<=x"0"; end if; if bcddata_TimeSet(15 downto 12)=x"5" then bcddata_TimeSet(15 downto 12)<=x"0"; end if; if bcddata_TimeSet(19 downto 16)=x"9" then bcddata_TimeSet(19 downto 16)<=x"0"; bcddata_TimeSet(23 downto 20)<=bcddata_TimeSet(23 downto 20)+1; end if; if bcddata_TimeSet(23 downto 16)=x"23" then bcddata_TimeSet(23 downto 16)<=x"00"; elsif bcddata_TimeSet(19 downto 16) =x"9" then bcddata_TimeSet(23 downto 20)<=bcddata_TimeSet(23 downto 20)+1; end if; elsif displayMode = 2 then --如果是显示模式2（即闹钟设置模式），则对闹钟设置模式的bcddata进行操作 case leftMoving is when "11110" => bcddata_ClockSet(3 downto 0)<=bcddata_ClockSet(3 downto 0)+1; --设置秒针个位数 when "11101" => bcddata_ClockSet(7 downto 4)<=bcddata_ClockSet(7 downto 4)+1; --设置秒针十位数 when "11011" => bcddata_ClockSet(11 downto 8)<=bcddata_ClockSet(11 downto 8)+1; --设置分针个位数 when "10111" => bcddata_ClockSet(15 downto 12)<=bcddata_ClockSet(15 downto 12)+1; --设置分针十位数 when "01111" => bcddata_ClockSet(19 downto 16)<=bcddata_ClockSet(19 downto 16)+1; --设置时针 when others => NULL; end case; if bcddata_ClockSet(3 downto 0)=x"9" then bcddata_ClockSet(3 downto 0)<=x"0"; end if; if bcddata_ClockSet(7 downto 4)=x"5" then bcddata_ClockSet(7 downto 4)<=x"0"; end if; if bcddata_ClockSet(11 downto 8)=x"9" then bcddata_ClockSet(11 downto 8)<=x"0"; end if; if bcddata_ClockSet(15 downto 12)=x"5" then bcddata_ClockSet(15 downto 12)<=x"0"; end if; if bcddata_ClockSet(19 downto 16)=x"9" then bcddata_ClockSet(19 downto 16)<=x"0"; bcddata_ClockSet(23 downto 20)<=bcddata_ClockSet(23 downto 20)+1; end if; if bcddata_ClockSet(23 downto 16)=x"23" then bcddata_ClockSet(23 downto 16)<=x"00"; elsif bcddata_ClockSet(19 downto 16) =x"9" then bcddata_ClockSet(23 downto 20)<=bcddata_ClockSet(23 downto 20)+1; end if; end if; end if; end process; process(clkcnt(17 downto 15)) begin if displayMode = 0 then case clkcnt(17 downto 15) is when "000" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(3 downto 0) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(3 downto 0); end if; SEG_NCS <= "011111"; segdot <= '1'; when "001" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(7 downto 4) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(7 downto 4); end if; SEG_NCS <= "101111"; segdot <= '1'; when "010" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(11 downto 8) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(11 downto 8); end if; SEG_NCS <= "110111"; segdot <= clk_1Hz; when "011" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(15 downto 12) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(15 downto 12); end if; SEG_NCS <= "111011"; segdot <= '1'; when "100" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(19 downto 16) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(19 downto 16); end if; SEG_NCS <= "111101"; segdot<= clk_1Hz; when "101" => if ClockTwinkling = '1' then bcd_led <= bcddata_ClockSet(23 downto 20) OR clk_1Hz_4vectors; else bcd_led <= bcddata_Time(23 downto 20); end if; SEG_NCS <= "111110"; segdot <= '1'; when "110" => SEG_NCS <= "111111"; when "111" => SEG_NCS <= "111111"; when others => NULL; end case; elsif displayMode = 1 then case clkcnt(17 downto 15) is when "000" => if LeftMoving = "11110" then bcd_led <= bcddata_TimeSet(3 downto 0) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(3 downto 0); end if; SEG_NCS <= "011111"; segdot <= '1'; when "001" => if LeftMoving = "11101" then bcd_led <= bcddata_TimeSet(7 downto 4) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(7 downto 4); end if; SEG_NCS <= "101111"; segdot <= '1'; when "010" => if LeftMoving = "11011" then bcd_led <= bcddata_TimeSet(11 downto 8) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(11 downto 8); end if; SEG_NCS <= "110111"; segdot <= clk_1Hz; when "011" => if LeftMoving = "10111" then bcd_led <= bcddata_TimeSet(15 downto 12) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(15 downto 12); end if; SEG_NCS <= "111011"; segdot<='1'; when "100" => if LeftMoving = "01111" then bcd_led<=bcddata_TimeSet(19 downto 16) OR clk_1Hz_4vectors; else bcd_led<=bcddata_TimeSet(19 downto 16); end if; SEG_NCS <= "111101"; segdot<= clk_1Hz; when "101" => bcd_led<=bcddata_TimeSet(23 downto 20); SEG_NCS <= "111110"; segdot <= '1'; when "110" => SEG_NCS <= "111111"; when "111" => SEG_NCS <= "111111"; when others => NULL; end case; elsif displayMode = 2 then case clkcnt(17 downto 15) is when "000" => if LeftMoving = "11110" then bcd_led <= bcddata_ClockSet(3 downto 0) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(3 downto 0); end if; SEG_NCS <= "011111"; segdot <= '1'; when "001" => if LeftMoving = "11101" then bcd_led <= bcddata_ClockSet(7 downto 4) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(7 downto 4); end if; SEG_NCS <= "101111"; segdot <= '1'; when "010" => if LeftMoving = "11011" then bcd_led <= bcddata_ClockSet(11 downto 8) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(11 downto 8); end if; SEG_NCS <= "110111"; segdot <= clk_1Hz; when "011" => if LeftMoving = "10111" then bcd_led <= bcddata_ClockSet(15 downto 12) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(15 downto 12); end if; SEG_NCS <= "111011"; segdot<='1'; when "100" => if LeftMoving = "01111" then bcd_led<=bcddata_ClockSet(19 downto 16) OR clk_1Hz_4vectors; else bcd_led<=bcddata_ClockSet(19 downto 16); end if; SEG_NCS <= "111101"; segdot<= clk_1Hz; when "101" => bcd_led<=bcddata_ClockSet(23 downto 20); SEG_NCS <= "111110"; segdot <= '1'; when "110" => SEG_NCS <= "111111"; when "111" => SEG_NCS <= "111111"; when others => NULL; end case; end if; end process; process(bcd_led) begin case bcd_led is WHEN "0000"=>SEG_LED<="0000001"; WHEN "0001"=>SEG_LED<="1001111"; WHEN "0010"=>SEG_LED<="0010010"; WHEN "0011"=>SEG_LED<="0000110"; WHEN "0100"=>SEG_LED<="1001100"; WHEN "0101"=>SEG_LED<="0100100"; WHEN "0110"=>SEG_LED<="0100000"; WHEN "0111"=>SEG_LED<="0001111"; WHEN "1000"=>SEG_LED<="0000000"; WHEN "1001"=>SEG_LED<="0000100"; WHEN OTHERS=>SEG_LED<="1111111"; end case; end process; -------------------------------------------------------- process(clk) begin if(rising_edge(clk))then if keyTimeSetfilt = '1' then TimeSetting <= not TimeSetting; if TimeSetting = '1' then displayMode := 1; elsif TimeSetting = '0' then displayMode := 0; end if; end if; if keyClockSetfilt = '1' then ClockSetting <= not ClockSetting; if ClockSetting = '1' then displayMode := 2; elsif ClockSetting = '0' then displayMode := 0; end if; end if; if keyLeftMovefilt = '1' then LeftMoving <= LeftMoving ROL 1; end if; end if; end process; end behav;
-- Criado por <NAME> -- Processador RISC-V Uniciclo em VHDL -- Em 22/05/2021 -- Universidade de Brasília, Matriculas 180053922 e 180023631 library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity riscV is port( clock : in std_logic ); end entity riscV; architecture arc_riscV of riscV is component bloco_pc is port( clock : in std_logic; pcin : in std_logic_vector(31 downto 0); pcout : out std_logic_vector(31 downto 0) ); end component; component bloco_rom is port( address : in std_logic_vector; dataout : out std_logic_vector ); end component; component bloco_ram is port ( clock : in std_logic; writeEnable : in std_logic; address : in std_logic_vector; datain : in std_logic_vector; dataout : out std_logic_vector ); end component; component bloco_ctrlgeral is port( opcode : in std_logic_vector(6 downto 0); branch : out std_logic; memRead : out std_logic; memToReg : out std_logic; ulaOP : out std_logic_vector(2 downto 0); memWrite : out std_logic; ulaSource : out std_logic; regWrite : out std_logic; isLUI : out std_logic; isAUIPC : out std_logic; isJALX : out std_logic; isJALR : out std_logic ); end component; component bloco_breg is port( writeData : in std_logic_vector(31 downto 0); writeEnable : in std_logic; select1 : in std_logic_vector(4 downto 0); select2 : in std_logic_vector(4 downto 0); selectWrite : in std_logic_vector(4 downto 0); clock : in std_logic; register1 : out std_logic_vector(31 downto 0); register2 : out std_logic_vector(31 downto 0) ); end component; component bloco_gimediato is port( instruc : in std_logic_vector(31 downto 0); imediato : out std_logic_vector(31 downto 0) ); end component; component bloco_ctrlula is port ( ulaOP: in std_logic_vector(2 downto 0); func3: in std_logic_vector(2 downto 0); bitfunc7: in std_logic; ulaCode: out std_logic_vector(3 downto 0) ); end component; component bloco_ula is port( opcode : in std_logic_vector(3 downto 0); A, B : in std_logic_vector(31 downto 0); Z : out std_logic_vector(31 downto 0); zero : out std_logic ); end component; component bloco_mux32 is port( selec : in std_logic; A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); Z : out std_logic_vector(31 downto 0) ); end component; component bloco_mux5 is port( selec : in std_logic; A : in std_logic_vector(4 downto 0); B : in std_logic_vector(4 downto 0); Z : out std_logic_vector(4 downto 0) ); end component; component bloco_and is port( A : in std_logic; B : in std_logic; Z : out std_logic ); end component; component bloco_somador is port( A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); Z : out std_logic_vector(31 downto 0) ); end component; signal fake_clock : std_logic; signal sig_pcin : std_logic_vector(31 downto 0); signal sig_pcout : std_logic_vector(31 downto 0); signal instruction : std_logic_vector(31 downto 0); signal sig_branch : std_logic; signal sig_memRead : std_logic; signal sig_memToReg : std_logic; signal sig_ulaOP : std_logic_vector(2 downto 0); signal sig_memWrite : std_logic; signal sig_ulaSource : std_logic; signal sig_regWrite : std_logic; signal sig_isLUI : std_logic; signal sig_isAUIPC : std_logic; signal sig_isJALX : std_logic; signal sig_isJALR : std_logic; signal sig_writeData : std_logic_vector(31 downto 0); signal sig_register1 : std_logic_vector(31 downto 0); signal sig_register2 : std_logic_vector(31 downto 0); signal sig_imediato : std_logic_vector(31 downto 0); signal sig_ulaCode : std_logic_vector(3 downto 0); signal sig_ulaB : std_logic_vector(31 downto 0); signal sig_ulaZ : std_logic_vector(31 downto 0); signal sig_ulaZero : std_logic; alias sig_addressRom : std_logic_vector(9 downto 0) is sig_pcout(11 downto 2); --n�o s�o necess�rios todos os bits de endere�o alias sig_addressRam : std_logic_vector(9 downto 0) is sig_ulaZ(11 downto 2); signal sig_dataOutRam : std_logic_vector(31 downto 0); alias sig_opcode : std_logic_vector(6 downto 0) is instruction(6 downto 0); alias sig_select1 : std_logic_vector(4 downto 0) is instruction(19 downto 15); alias sig_select2 : std_logic_vector(4 downto 0) is instruction(24 downto 20); alias sig_selectWrite : std_logic_vector(4 downto 0) is instruction(11 downto 7); alias sig_func3 : std_logic_vector(2 downto 0) is instruction(14 downto 12); alias sig_bitfunc7 : std_logic is instruction(30); signal sig_soma_pcimediato : std_logic_vector(31 downto 0); signal sig_soma_pc4 : std_logic_vector(31 downto 0); signal sig_and_branchzero : std_logic; signal sig_mux_somasdepc : std_logic_vector(31 downto 0); signal sig_mux_select1lui: std_logic_vector(4 downto 0); --Mux RAM signal sig_mux_ramulaz : std_logic_vector(31 downto 0); --Mux AUIPC signal sig_mux_auipc : std_logic_vector(31 downto 0); begin pc: bloco_pc port map( clock => fake_clock, pcin => sig_pcin, pcout => sig_pcout ); memoria_de_instrucoes: bloco_rom port map( address => sig_addressRom, dataout => instruction ); bloco_de_controle_geral : bloco_ctrlgeral port map( opcode => sig_opcode, branch => sig_branch, memRead => sig_memRead, memToReg => sig_memToReg, ulaOP => sig_ulaOP, memWrite => sig_memWrite, ulaSource => sig_ulaSource, regWrite => sig_regWrite, isLUI => sig_isLUI, isAUIPC => sig_isAUIPC, isJALX => sig_isJALX, isJALR => sig_isJALR ); breg: bloco_breg port map( writeData => sig_writeData, writeEnable => sig_regWrite, select1 => sig_mux_select1lui, select2 => sig_select2, selectWrite => sig_selectWrite, clock => fake_clock, register1 => sig_register1, register2 => sig_register2 ); gerador_de_imediato: bloco_gimediato port map( instruc => instruction, imediato => sig_imediato ); controle_da_ula: bloco_ctrlula port map( ulaOP => sig_ulaOP, func3 => sig_func3, bitfunc7 => sig_bitfunc7, ulaCode => sig_ulaCode ); mux32_breg_imm: bloco_mux32 port map( selec => sig_ulaSource, A => sig_register2, B => sig_imediato, Z => sig_ulaB ); ula: bloco_ula port map( opcode => sig_ulaCode, A => sig_register1, B => sig_ulaB, Z => sig_ulaZ, zero => sig_ulaZero ); memoria_de_dados: bloco_ram port map( clock => fake_clock, writeEnable => sig_memWrite, address => sig_addressRam, datain => sig_register2, dataout => sig_dataOutRam ); mux32_memdados_ula: bloco_mux32 port map( selec => sig_memToReg, A => sig_ulaZ, B => sig_dataOutRam, Z => sig_mux_ramulaz ); somador_pc_imm: bloco_somador port map( A => sig_pcout, B => sig_imediato, Z => sig_soma_pcimediato ); somador_pc_4: bloco_somador port map( A => sig_pcout, B => "00000000000000000000000000000100", Z => sig_soma_pc4 ); and_branch: bloco_and port map( A => sig_branch, B => sig_ulaZero, Z => sig_and_branchzero ); mux32_pc4_pcimediato: bloco_mux32 port map( selec => sig_and_branchzero, A => sig_soma_pc4, B => sig_soma_pcimediato, Z => sig_mux_somasdepc ); mux_lui: bloco_mux5 port map( selec => sig_isLUI, A => sig_select1, B => "00000", Z => sig_mux_select1lui ); mux_auipc: bloco_mux32 port map( selec => sig_isAUIPC, A => sig_mux_ramulaz, B => sig_soma_pcimediato, Z => sig_mux_auipc ); mux_jalx: bloco_mux32 port map( selec => sig_isJALX, A => sig_mux_auipc, B => sig_soma_pc4, Z => sig_writeData ); mux_jalr: bloco_mux32 port map( selec => sig_isJALR, A => sig_mux_somasdepc, B => sig_ulaZ, Z => sig_pcin ); process begin --fake_clock <= clock fake_clock <= '0'; --comentar daqui pra baixo para utilizar a entrada de clock wait for 1 ns; fake_clock <= '1'; wait for 1 ns; end process; end arc_riscV;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity cmp is Generic(N : natural := 8); Port ( rs1 : in STD_LOGIC_VECTOR (N-1 downto 0); rs2 : in STD_LOGIC_VECTOR (N-1 downto 0); uns : in STD_LOGIC; lt : out STD_LOGIC; eq : out STD_LOGIC); end cmp; architecture Behavioral of cmp is signal rs1_i: unsigned(N-1 downto 0); signal rs2_i: unsigned(N-1 downto 0); begin rs1_i(N-2 downto 0) <= unsigned(rs1(N-2 downto 0)); rs2_i(N-2 downto 0) <= unsigned(rs2(N-2 downto 0)); rs1_i(N-1) <= rs1(N-1) when uns = '1' else rs2(N-1); rs2_i(N-1) <= rs2(N-1) when uns = '1' else rs1(N-1); lt <= '1' when rs1_i < rs2_i else '0'; eq <= '1' when rs1 = rs2 else '0'; end Behavioral;
library ieee; use ieee.std_logic_1164.all; entity OrGate is port ( x1:in std_logic; x2:in std_logic; x3:out std_logic ); end OrGate; architecture beh of OrGate is begin x3 <= x1 or x2; end beh;
library IEEE; use IEEE.std_logic_1164.all; ENTITY reg8 IS PORT ( i_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; i_RESETN, i_CLOCK: IN STD_LOGIC ; o_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE arch_reg8 OF reg8 IS BEGIN PROCESS ( i_RESETN, i_CLOCK ) BEGIN IF i_RESETN = '0' THEN o_DATA <= "00000000" ; ELSIF i_CLOCK'EVENT AND i_CLOCK = '1' THEN o_DATA <= i_DATA ; END IF ; END PROCESS ; END arch_reg8 ;
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<KEY> `protect end_protected
library verilog; use verilog.vl_types.all; entity tb_top_key_beep is generic( T : integer := 20 ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of T : constant is 1; end tb_top_key_beep;
component pr_region_default_SpatialIP_0 is port ( clock : in std_logic := 'X'; -- clk io_M_AXI_0_AWID : out std_logic_vector(5 downto 0); -- awid io_M_AXI_0_AWUSER : out std_logic_vector(31 downto 0); -- awuser io_M_AXI_0_AWADDR : out std_logic_vector(31 downto 0); -- awaddr io_M_AXI_0_AWLEN : out std_logic_vector(7 downto 0); -- awlen io_M_AXI_0_AWSIZE : out std_logic_vector(2 downto 0); -- awsize io_M_AXI_0_AWBURST : out std_logic_vector(1 downto 0); -- awburst io_M_AXI_0_AWLOCK : out std_logic; -- awlock io_M_AXI_0_AWCACHE : out std_logic_vector(3 downto 0); -- awcache io_M_AXI_0_AWPROT : out std_logic_vector(2 downto 0); -- awprot io_M_AXI_0_AWQOS : out std_logic_vector(3 downto 0); -- awqos io_M_AXI_0_AWVALID : out std_logic; -- awvalid io_M_AXI_0_AWREADY : in std_logic := 'X'; -- awready io_M_AXI_0_ARID : out std_logic_vector(5 downto 0); -- arid io_M_AXI_0_ARUSER : out std_logic_vector(31 downto 0); -- aruser io_M_AXI_0_ARADDR : out std_logic_vector(31 downto 0); -- araddr io_M_AXI_0_ARLEN : out std_logic_vector(7 downto 0); -- arlen io_M_AXI_0_ARSIZE : out std_logic_vector(2 downto 0); -- arsize io_M_AXI_0_ARBURST : out std_logic_vector(1 downto 0); -- arburst io_M_AXI_0_ARLOCK : out std_logic; -- arlock io_M_AXI_0_ARCACHE : out std_logic_vector(3 downto 0); -- arcache io_M_AXI_0_ARPROT : out std_logic_vector(2 downto 0); -- arprot io_M_AXI_0_ARQOS : out std_logic_vector(3 downto 0); -- arqos io_M_AXI_0_ARVALID : out std_logic; -- arvalid io_M_AXI_0_ARREADY : in std_logic := 'X'; -- arready io_M_AXI_0_WDATA : out std_logic_vector(511 downto 0); -- wdata io_M_AXI_0_WSTRB : out std_logic_vector(63 downto 0); -- wstrb io_M_AXI_0_WLAST : out std_logic; -- wlast io_M_AXI_0_WVALID : out std_logic; -- wvalid io_M_AXI_0_WREADY : in std_logic := 'X'; -- wready io_M_AXI_0_RID : in std_logic_vector(5 downto 0) := (others => 'X'); -- rid io_M_AXI_0_RUSER : in std_logic_vector(31 downto 0) := (others => 'X'); -- ruser io_M_AXI_0_RDATA : in std_logic_vector(511 downto 0) := (others => 'X'); -- rdata io_M_AXI_0_RRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp io_M_AXI_0_RLAST : in std_logic := 'X'; -- rlast io_M_AXI_0_RVALID : in std_logic := 'X'; -- rvalid io_M_AXI_0_RREADY : out std_logic; -- rready io_M_AXI_0_BID : in std_logic_vector(5 downto 0) := (others => 'X'); -- bid io_M_AXI_0_BUSER : in std_logic_vector(31 downto 0) := (others => 'X'); -- buser io_M_AXI_0_BRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp io_M_AXI_0_BVALID : in std_logic := 'X'; -- bvalid io_M_AXI_0_BREADY : out std_logic; -- bready io_S_AVALON_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address io_S_AVALON_readdata : out std_logic_vector(31 downto 0); -- readdata io_S_AVALON_chipselect : in std_logic := 'X'; -- chipselect io_S_AVALON_write : in std_logic := 'X'; -- write io_S_AVALON_read : in std_logic := 'X'; -- read io_S_AVALON_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata reset : in std_logic := 'X' -- reset ); end component pr_region_default_SpatialIP_0; u0 : component pr_region_default_SpatialIP_0 port map ( clock => CONNECTED_TO_clock, -- clock.clk io_M_AXI_0_AWID => CONNECTED_TO_io_M_AXI_0_AWID, -- io_M_AXI_0.awid io_M_AXI_0_AWUSER => CONNECTED_TO_io_M_AXI_0_AWUSER, -- .awuser io_M_AXI_0_AWADDR => CONNECTED_TO_io_M_AXI_0_AWADDR, -- .awaddr io_M_AXI_0_AWLEN => CONNECTED_TO_io_M_AXI_0_AWLEN, -- .awlen io_M_AXI_0_AWSIZE => CONNECTED_TO_io_M_AXI_0_AWSIZE, -- .awsize io_M_AXI_0_AWBURST => CONNECTED_TO_io_M_AXI_0_AWBURST, -- .awburst io_M_AXI_0_AWLOCK => CONNECTED_TO_io_M_AXI_0_AWLOCK, -- .awlock io_M_AXI_0_AWCACHE => CONNECTED_TO_io_M_AXI_0_AWCACHE, -- .awcache io_M_AXI_0_AWPROT => CONNECTED_TO_io_M_AXI_0_AWPROT, -- .awprot io_M_AXI_0_AWQOS => CONNECTED_TO_io_M_AXI_0_AWQOS, -- .awqos io_M_AXI_0_AWVALID => CONNECTED_TO_io_M_AXI_0_AWVALID, -- .awvalid io_M_AXI_0_AWREADY => CONNECTED_TO_io_M_AXI_0_AWREADY, -- .awready io_M_AXI_0_ARID => CONNECTED_TO_io_M_AXI_0_ARID, -- .arid io_M_AXI_0_ARUSER => CONNECTED_TO_io_M_AXI_0_ARUSER, -- .aruser io_M_AXI_0_ARADDR => CONNECTED_TO_io_M_AXI_0_ARADDR, -- .araddr io_M_AXI_0_ARLEN => CONNECTED_TO_io_M_AXI_0_ARLEN, -- .arlen io_M_AXI_0_ARSIZE => CONNECTED_TO_io_M_AXI_0_ARSIZE, -- .arsize io_M_AXI_0_ARBURST => CONNECTED_TO_io_M_AXI_0_ARBURST, -- .arburst io_M_AXI_0_ARLOCK => CONNECTED_TO_io_M_AXI_0_ARLOCK, -- .arlock io_M_AXI_0_ARCACHE => CONNECTED_TO_io_M_AXI_0_ARCACHE, -- .arcache io_M_AXI_0_ARPROT => CONNECTED_TO_io_M_AXI_0_ARPROT, -- .arprot io_M_AXI_0_ARQOS => CONNECTED_TO_io_M_AXI_0_ARQOS, -- .arqos io_M_AXI_0_ARVALID => CONNECTED_TO_io_M_AXI_0_ARVALID, -- .arvalid io_M_AXI_0_ARREADY => CONNECTED_TO_io_M_AXI_0_ARREADY, -- .arready io_M_AXI_0_WDATA => CONNECTED_TO_io_M_AXI_0_WDATA, -- .wdata io_M_AXI_0_WSTRB => CONNECTED_TO_io_M_AXI_0_WSTRB, -- .wstrb io_M_AXI_0_WLAST => CONNECTED_TO_io_M_AXI_0_WLAST, -- .wlast io_M_AXI_0_WVALID => CONNECTED_TO_io_M_AXI_0_WVALID, -- .wvalid io_M_AXI_0_WREADY => CONNECTED_TO_io_M_AXI_0_WREADY, -- .wready io_M_AXI_0_RID => CONNECTED_TO_io_M_AXI_0_RID, -- .rid io_M_AXI_0_RUSER => CONNECTED_TO_io_M_AXI_0_RUSER, -- .ruser io_M_AXI_0_RDATA => CONNECTED_TO_io_M_AXI_0_RDATA, -- .rdata io_M_AXI_0_RRESP => CONNECTED_TO_io_M_AXI_0_RRESP, -- .rresp io_M_AXI_0_RLAST => CONNECTED_TO_io_M_AXI_0_RLAST, -- .rlast io_M_AXI_0_RVALID => CONNECTED_TO_io_M_AXI_0_RVALID, -- .rvalid io_M_AXI_0_RREADY => CONNECTED_TO_io_M_AXI_0_RREADY, -- .rready io_M_AXI_0_BID => CONNECTED_TO_io_M_AXI_0_BID, -- .bid io_M_AXI_0_BUSER => CONNECTED_TO_io_M_AXI_0_BUSER, -- .buser io_M_AXI_0_BRESP => CONNECTED_TO_io_M_AXI_0_BRESP, -- .bresp io_M_AXI_0_BVALID => CONNECTED_TO_io_M_AXI_0_BVALID, -- .bvalid io_M_AXI_0_BREADY => CONNECTED_TO_io_M_AXI_0_BREADY, -- .bready io_S_AVALON_address => CONNECTED_TO_io_S_AVALON_address, -- io_S_AVALON.address io_S_AVALON_readdata => CONNECTED_TO_io_S_AVALON_readdata, -- .readdata io_S_AVALON_chipselect => CONNECTED_TO_io_S_AVALON_chipselect, -- .chipselect io_S_AVALON_write => CONNECTED_TO_io_S_AVALON_write, -- .write io_S_AVALON_read => CONNECTED_TO_io_S_AVALON_read, -- .read io_S_AVALON_writedata => CONNECTED_TO_io_S_AVALON_writedata, -- .writedata reset => CONNECTED_TO_reset -- reset.reset );
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; use tip.all; entity ALU is port(CLK : in STD_LOGIC; COMMAND_IN:in std_logic_vector(3 downto 0); SELECT_IN:in std_logic_vector(3 downto 0); CONST_IN :in std_logic_vector(7 downto 0); OUT_ALU: out std_logic_vector(7 downto 0); Zero: inout std_logic:='0'; Carry: inout std_logic:='0'); end; architecture UAL of ALU is component Semi_sumator port(EN: in std_logic; A,B: in std_logic_vector(7 downto 0); SUM: out std_logic_vector(7 downto 0); CF,ZF:out std_logic); end component; component Sumator_complet port(EN: in std_logic; A,B: in std_logic_VECTOR(7 downto 0); SUM: out std_logic_VECTOR(7 downto 0); CF: inout std_logic; ZF: out std_logic); end component; component Scazator port(EN: in std_logic; A,B: in STD_LOGIC_VECTOR(7 downto 0); DIF: out STD_LOGIC_VECTOR(7 downto 0); CF,ZF: out STD_LOGIC); end component; component Scazator_complet port(EN: in std_logic; A,B: in std_logic_VECTOR(7 downto 0); DIF: out std_logic_VECTOR(7 downto 0); CF:inout std_logic; ZF: out std_logic); end component; component Poarta_SI port(EN: in std_logic; A,B: in std_logic_VECTOR(7 downto 0); Y: out std_logic_VECTOR(7 downto 0); CF,ZF: out std_logic); end component; component XOR_8 port(EN: in std_logic; A,B:in std_logic_vector(7 downto 0); X:out std_logic_vector(7 downto 0); CARRY,ZERO:out std_logic); end component; component OR_8 port(EN: in std_logic; A,B:in std_logic_vector(7 downto 0); O:out std_logic_vector(7 downto 0); CARRY,ZERO: out std_logic); end component; component SHIFT PORT(EN: in std_logic; REG_IN:in std_logic_vector(7 downto 0); --input SEL:in std_logic_vector(3 downto 0); --selectia de shift (SEE XAPP213.PDF) CARRY: inout std_logic; REG_OUT: out std_logic_vector(7 downto 0); ZERO: out std_logic); end component; component Mux2la1 port (I0,I1: in std_logic_vector(7 downto 0); SEL2_1: in std_logic; O: out std_logic_vector(7 downto 0)); end component; component Mux16la1 port ( --EN: in std_logic; MUX_IN: in M168; EN: in STD_LOGIC; SEL: in STD_LOGIC_VECTOR(3 downto 0); MUX_OUT: out STD_LOGIC_VECTOR(7 downto 0) ); end component; component REGISTRII port(CLK_R : in STD_LOGIC; CLK_W : in STD_LOGIC; IN_REG: in STD_LOGIC_VECTOR(7 downto 0); S_IO_A : in STD_LOGIC_VECTOR(3 downto 0); S_O_B : in STD_LOGIC_VECTOR(3 downto 0); OUT_A : out STD_LOGIC_VECTOR(7 downto 0); OUT_B : out STD_LOGIC_VECTOR(7 downto 0)); end component; component LOAD port(EN: in std_logic; LOAD_IN : in std_logic_vector(7 downto 0); LOAD_OUT: out std_logic_vector(7 downto 0); CF,ZF: out std_logic); end component; signal INPUT_REG: std_logic_vector(7 downto 0):="00000000"; signal sX,sY : std_logic_vector(3 downto 0); signal MUX_SELECT: std_logic_vector(3 downto 0); signal shift_command: std_logic_vector(3 downto 0); signal REG_A,REG_B: std_logic_vector(7 downto 0):="00000000"; signal A,B: std_logic_vector(7 downto 0):="00000000"; signal REZULTATE : M168; signal EN : std_logic; signal EN_VEC : std_logic_vector(15 downto 0):=(others => '0'); signal WRITE_REG : std_logic; begin process(COMMAND_IN,SELECT_IN,CONST_IN,CLK) variable EN_AUX: std_logic_vector(15 downto 0):="0000000000000000"; variable EN_GENERAL: std_logic; begin --EN_AUX:=(others => '0'); case COMMAND_IN is when "0001" \| "0010" \| "0011" \| "0100" \| "0101" \| "0110" \| "0111" \| "0000" => MUX_SELECT<= COMMAND_IN; sX <= SELECT_IN; sY <= "ZZZZ"; if(CLK = '1' and CLK'EVENT) then EN_GENERAL := '0'; end if; if(CLK = '0' and CLK'EVENT) then EN_GENERAL:= '1'; end if; EN_AUX(to_integer(unsigned(COMMAND_IN))):=not EN_GENERAL; when "1100" => MUX_SELECT<=CONST_IN(3 downto 0); sX <= SELECT_IN; sY <= CONST_IN(7 downto 4); if(CLK = '1' and CLK'EVENT) then EN_GENERAL := '0'; end if; if(CLK = '0' and CLK'EVENT) then EN_GENERAL:= '1'; end if; EN_AUX(to_integer(unsigned(CONST_IN))):=not EN_GENERAL; when "1101" => MUX_SELECT<=COMMAND_IN; sX<= SELECT_IN; shift_command<= CONST_IN(3 downto 0); if(CLK = '1' and CLK'EVENT) then EN_GENERAL := '0'; end if; if(CLK = '0' and CLK'EVENT) then EN_GENERAL:= '1'; end if; EN_AUX(to_integer(unsigned(COMMAND_IN))):= EN_GENERAL; when others => NULL; end case; if(EN_GENERAL = '1') then WRITE_REG<='0'; end if; if(EN_GENERAL = '0') then WRITE_REG<='1'; end if; EN_VEC<=EN_AUX; EN<= EN_GENERAL; end process; ATR: B<=REG_B when COMMAND_IN = "1100" else CONST_IN; REG : REGISTRII port map(EN,WRITE_REG,INPUT_REG,sX,sY,REG_A,REG_B); LOADD : LOAD port map(EN_VEC(0),B,REZULTATE(0),Carry,Zero); --0000 ANDD : Poarta_SI port map(EN_VEC(1),REG_A,B,REZULTATE(1),Carry,Zero); --0001 ORR : OR_8 port map(EN_VEC(2),REG_A,B,REZULTATE(2),Carry,Zero); --0010 XORR : XOR_8 port map(EN_VEC(3),REG_A,B,REZULTATE(3),Carry,Zero); --0011 ADD : Semi_sumator port map(EN_VEC(4),REG_A,B,REZULTATE(4),Carry,Zero); --0100 ADDCY : Sumator_complet port map(EN_VEC(5),REG_A,B,REZULTATE(5),Carry,Zero); --0101 SUB : Scazator port map(EN_VEC(6),REG_A,B,REZULTATE(6),Carry,Zero); --0110 SUBCY : Scazator_complet port map(EN_VEC(7),REG_A,B,REZULTATE(7),Carry,Zero); --0111 SHIFT1 : SHIFT port map(EN_VEC(13),REG_A,shift_command,Carry,REZULTATE(13),Zero);--1101 MUX_OUT: MUX16la1 port map(REZULTATE,'1',MUX_SELECT,INPUT_REG); REZULTATE(12 downto 8) <= (others =>"ZZZZZZZZ"); REZULTATE(15 downto 14) <= (others =>"ZZZZZZZZ"); OUT_ALU<= INPUT_REG; end;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:59:48 05/23/2011 -- Design Name: -- Module Name: /home/silva/Documents/Dropbox/IST/PSD_TEMP/debug/sudoku_mem/tb_circuito.vhd -- Project Name: sudoku_mem -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: circuito3 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_circuito IS END tb_circuito; ARCHITECTURE behavior OF tb_circuito IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT circuito3 PORT( CLK : IN std_logic; RST : IN std_logic; clks : OUT std_logic; memout : OUT std_logic_vector(31 downto 0); canSTART : IN std_logic; execDONE : OUT std_logic; CNTbyte2 : IN std_logic_vector(11 downto 0) ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '0'; signal canSTART : std_logic := '0'; signal CNTbyte2 : std_logic_vector(11 downto 0) := (others => '0'); --Outputs signal clks : std_logic; signal memout : std_logic_vector(31 downto 0); signal execDONE : std_logic; -- Clock period definitions constant CLK_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: circuito3 PORT MAP ( CLK => CLK, RST => RST, clks => clks, memout => memout, canSTART => canSTART, execDONE => execDONE, CNTbyte2 => CNTbyte2 ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. rst <= '1', '0' after 50 ns; canstart <= '0', '1' after 100 ns; -- insert stimulus here wait; end process; END;
-- The MIT License (MIT) -- -- Copyright (c) <NAME> <EMAIL> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity camera_unit is generic( BUF_AW : integer := 8; BUF_DW : integer := 16 ); port( clk : in std_logic; reset : in std_logic; addr : in std_logic_vector(15 downto 0); strobe : in std_logic; cycle : in std_logic; c_sel : in std_logic; wr : in std_logic; ack : out std_logic; --filter : in std_logic; ack_tick : out std_logic; dout : out std_logic_vector(15 downto 0); cfinish : out std_logic; resend : in std_logic ; frame_irq : out std_logic; --- CAMERA PINS GOES HERE OV7670_VSYNC : in std_logic; OV7670_HREF : in std_logic; OV7670_PCLK : in std_logic; OV7670_D : in std_logic_vector(7 downto 0); OV7670_SIOC : out STD_LOGIC; OV7670_SIOD : inout STD_LOGIC; OV7670_RESET : out STD_LOGIC; OV7670_PWDN : out STD_LOGIC; OV7670_XCLK : out STD_LOGIC ); end entity; architecture arch of camera_unit is -- signals declaration here constant ID: natural := 1; constant VGA_ADDR: std_logic_vector(18 downto 0 ) := "1001010111111111111"; constant QVGA_ADDR: std_logic_vector(18 downto 0) := "0010010101111111111"; constant QQVGA_ADDR : std_logic_vector(18 downto 0) := "0000100101011111111"; constant OFFSET: unsigned(15 downto 0) := X"0008"; signal mem_addr : std_logic_vector(15 downto 0); signal wr_op, px_wr, ack_db, state : std_logic := '0'; --signal fr_din, fr_din_next: std_logic_vector(BUF_DW-1 downto 0); signal cam_dout: std_logic_vector(15 downto 0) ; signal buffer_out,filter_out, filter_out_next : std_logic_vector(15 downto 0); signal clk_45: std_logic; signal fr_addr: std_logic_vector(18 downto 0) ; signal fr_addr_map, fr_addr_map_next: std_logic_vector(18 downto 0) ; -- select the filter or not signal R8,R8_next,G8, G8_next,B8,B8_next : std_logic_vector(7 downto 0); signal pixon: std_logic; signal d1, d2: std_logic_vector(7 downto 0) ; signal filter_ready: std_logic; signal rez_160x120,rez_320x240: std_logic; signal rez_in: std_logic_vector(1 downto 0) ; begin ack <= strobe and cycle and c_sel; state <= (ack_db or state) and (strobe and cycle and c_sel); ack_tick <= ack_db; write_proc : process( clk,reset ) begin if(reset = '1') then rez_320x240 <= '0'; rez_160x120 <= '0'; elsif rising_edge(clk) then if((strobe and cycle and wr and c_sel) = '1' ) then if rez_in = "01" then rez_160x120 <= '1'; rez_320x240 <= '0'; elsif rez_in = "10" then rez_160x120 <= '0'; rez_320x240 <= '1'; else rez_160x120 <= '0'; rez_320x240 <= '0'; end if; else rez_320x240 <= rez_320x240; rez_160x120 <= rez_160x120; end if; end if; end process ; sync_proc:process(clk, reset) begin if reset = '1' then ack_db <= '0'; --fr_din <= (others=>'0'); filter_out <= (others=>'0'); R8 <= (others=>'0'); G8 <= (others=>'0'); B8 <= (others=>'0'); fr_addr_map <= (others=>'0'); elsif rising_edge(clk) then --fr_din <= fr_din_next; filter_out<= filter_out_next; ack_db <= strobe and cycle and c_sel and (not ack_db) and (not state); R8 <= R8_next; G8 <= G8_next; B8 <= B8_next; fr_addr_map <= fr_addr_map_next; end if; end process; mem_addr <=std_logic_vector(unsigned(addr) - OFFSET) when (strobe and cycle and c_sel) = '1' else (others=>'0'); rez_in <= mem_addr(2 downto 1); -- clock unit clkgen_unit:entity work.clock_gen port map ( clk_in => clk, clk_45 => clk_45, clk_24 => OV7670_XCLK ) ; -- controller unit cam_ctrl: entity work.ov7670_controller port map( clk45 => clk_45, resend => resend, -- to host config_finished => cfinish, -- to led sioc => OV7670_SIOC, -- to camera siod => OV7670_SIOD, -- to camera reset => OV7670_RESET,-- to camera pwdn => OV7670_PWDN -- to camera ); capture_unit: entity work.ov7670_capture port map( pclk => OV7670_PCLK, vsync => OV7670_VSYNC, -- from camera rez_160x120 => rez_160x120, rez_320x240 => rez_320x240, href => OV7670_HREF, -- from camera d => OV7670_D, -- from camera addr => fr_addr, -- to buffer address dout => cam_dout, -- to buffer out we => px_wr ); frame_irq <= '1' when ((rez_320x240 = '1' and fr_addr_map = QVGA_ADDR) OR (rez_160x120 = '1' and fr_addr_map = QQVGA_ADDR) OR (rez_160x120 = '0' and rez_320x240 = '0' and fr_addr_map = VGA_ADDR)) else '0'; -- add the filter R8_next <= cam_dout(15 downto 11) & "000" when px_wr='1' else R8; G8_next <= cam_dout(10 downto 5) & "00" when px_wr='1' else G8; B8_next <= cam_dout(4 downto 0) & "000" when px_wr='1' else B8; filter_unit: entity work.hsvfilter port map( clk => clk, reset => reset, R_in => R8_next, G_in => G8_next, B_in => B8_next, start => px_wr, pixon => pixon, available => filter_ready ); wr_op <= '1' when fr_addr_map(3 downto 0) = "1111" and filter_ready = '1' else '0';-- when filter = '1' else px_wr; filter_out_next <= pixon&filter_out(15 downto 1) when filter_ready = '1' else filter_out; --buffer_in <= cam_dout when filter = '0' else filter_out_next; --fr_din_next <= cam_dout&fr_din(7 downto 0) when wr_op = '1' else -- fr_din(15 downto 8)&cam_dout when -- (px_wr = '1') else fr_din; fr_addr_map_next <=fr_addr when px_wr='1' else fr_addr_map;--when filter = '1' else fr_addr; -- end process; frame_ent: entity work.dual_port_dual_clock generic map( ADDR_WIDTH => BUF_AW, DATA_WIDTH => BUF_DW ) port map( clka => clk,-- a bit dagerous OV7670_PCLK, clkb => clk, we => wr_op, addr_a => fr_addr_map(18 downto 4),--fr_addr_map, addr_b => mem_addr(BUF_AW downto 1), -- requested by host din_a => filter_out_next,--buffer_in,--fr_din_next, -- stacked data from camera dout_a => open, dout_b => buffer_out -- to host ); --d1 <= (others=>'1') when buffer_out(0) = '1' else (others=>'0'); --d2 <= (others=>'1') when buffer_out(1) = '1' else (others=>'0'); dout <= buffer_out; end architecture;
library ieee; use ieee.std_logic_1164.all; entity adderSubtractor is port( mode : in std_logic; A : in std_logic_vector(2 downto 0); B : in std_logic_vector(2 downto 0); S : out std_logic_vector(2 downto 0); Cout, V : out std_logic ); end adderSubtractor; architecture struct of adderSubtractor is component full_adder is port( A, B, C : IN std_logic; Sum, Carry : OUT std_logic ); end component; signal C1, C2, C3: std_logic; signal xor0, xor1, xor2: std_logic; begin xor0 <= B(0) XOR mode; xor1 <= B(1) XOR mode; xor2 <= B(2) XOR mode; FA0: full_adder port map(A(0), xor0, mode, S(0), C1); FA1: full_adder port map(A(1), xor1, C1, S(1), C2); FA2: full_adder port map(A(2), xor2, C2, S(2), C3); V <= C2 XOR C3; Cout <= C3; end struct;
<reponame>danielvcorreia/cr -------------------------------------------- -- Module Name: tutorial -------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; Entity tutorial Is port ( sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(7 downto 0) ); end tutorial; Architecture behavior of tutorial Is Signal led_int : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; begin led <= led_int; led_int(0) <= not(sw(0)); led_int(1) <= sw(1) and not(sw(2)); led_int(3) <= sw(2) and sw(3); led_int(2) <= led_int(1) or led_int(3); led_int(7 downto 4) <= sw(7 downto 4); end behavior;
<gh_stars>1-10 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; --This entity counts the number of leading '1' terms entity sixteenbitcounter is port ( CLK : in std_logic; Y : out std_logic_vector(15 downto 0) := ('0', others=>'0') -- output only ); end entity; architecture counter16_falling of sixteenbitcounter is begin process is variable x : natural := 0; begin wait until CLK = '0'; x := x + 1; Y <= CONV_STD_LOGIC_VECTOR(x, 16); end process; end counter16_falling; architecture counter16_rising of sixteenbitcounter is begin process (CLK) is variable x : natural := 0; begin if (CLK'event and CLK = '1') then x := x + 1; Y <= CONV_STD_LOGIC_VECTOR(x, 16); end if; end process; end counter16_rising; architecture counter16_rising_v2 of sixteenbitcounter is begin process (CLK) is variable x : natural := 0; begin if rising_edge(CLK) then x := x + 1; Y <= CONV_STD_LOGIC_VECTOR(x, 16); end if; end process; end counter16_rising_v2;
<gh_stars>1-10 -- ******************************************************************/ -- Actel Corporation Proprietary and Confidential -- Copyright 2010 Actel Corporation. All rights reserved. -- -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED -- IN ADVANCE IN WRITING. -- -- Description: -- -- Revision Information: -- Date Description -- ---- ----------------------------------------- -- 04AUG10 Production Release Version 1.0 -- -- SVN Revision Information: -- SVN $Revision: $ -- SVN $Date: $ -- -- Resolved SARs -- SAR Date Who Description -- -- Notes: -- -- *****************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; ENTITY CoreAHBLtoAXI_AXIAccessControlHX IS GENERIC ( ----------------------------------------------------- -- Global parameters ----------------------------------------------------- AHB_AWIDTH : integer := 32; AHB_DWIDTH : integer := 32; AXI_AWIDTH : integer := 32; AXI_DWIDTH : integer := 64; CLOCKS_ASYNC : integer := 1; UNDEF_BURST : integer := 0); -- if '0' then single transter else INCR16 PORT ( ----------------------------------------------------- -- Input-Output Ports ----------------------------------------------------- -- Inputs on the AHBL interface HSEL : IN std_logic; HADDR : IN std_logic_vector(AHB_AWIDTH - 1 DOWNTO 0); HWRITE : IN std_logic; HREADY : IN std_logic; HTRANS : IN std_logic_vector(1 DOWNTO 0); HSIZE : IN std_logic_vector(2 DOWNTO 0); HBURST : IN std_logic_vector(2 DOWNTO 0); HMASTLOCK : IN std_logic; latch_ahb_sig_sync : IN std_logic; ahb_wr_done_sync : IN std_logic; ahb_rd_req_sync : IN std_logic; burst_count_valid_sync : IN std_logic; burst_count_r : IN std_logic_vector(3 DOWNTO 0); rdch_fifo_full : IN std_logic; wrch_fifo_empty : IN std_logic; -- Inputs on AXI Interface ACLK : IN std_logic; ARESETn : IN std_logic; axi_wr_data : IN std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); -- Outputs on AXI Interface AWID : OUT std_logic_vector(3 DOWNTO 0); AWADDR : OUT std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0); AWLEN : OUT std_logic_vector(3 DOWNTO 0); AWSIZE : OUT std_logic_vector(2 DOWNTO 0); AWBURST : OUT std_logic_vector(1 DOWNTO 0); AWLOCK : OUT std_logic_vector(1 DOWNTO 0); AWVALID : OUT std_logic; AWREADY : IN std_logic; WID : OUT std_logic_vector(3 DOWNTO 0); WDATA : OUT std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); WSTRB : OUT std_logic_vector((AXI_DWIDTH / 8) - 1 DOWNTO 0); WLAST : OUT std_logic; WVALID : OUT std_logic; WREADY : IN std_logic; BREADY : OUT std_logic; BID : IN std_logic_vector(3 DOWNTO 0); BRESP : IN std_logic_vector(1 DOWNTO 0); BVALID : IN std_logic; ARID : OUT std_logic_vector(3 DOWNTO 0); ARADDR : OUT std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0); ARLEN : OUT std_logic_vector(3 DOWNTO 0); ARSIZE : OUT std_logic_vector(2 DOWNTO 0); ARBURST : OUT std_logic_vector(1 DOWNTO 0); ARLOCK : OUT std_logic_vector(1 DOWNTO 0); ARVALID : OUT std_logic; ARREADY : IN std_logic; RREADY : OUT std_logic; RID : IN std_logic_vector(3 DOWNTO 0); RDATA : IN std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); RRESP : IN std_logic_vector(1 DOWNTO 0); RLAST : IN std_logic; RVALID : IN std_logic; WRCH_fifo_rd_en : OUT std_logic; BRESP_sync : OUT std_logic_vector(1 DOWNTO 0); rdch_fifo_wr_en_r : OUT std_logic; rdch_fifo_wr_data : OUT std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0); axi_read_rlast : OUT std_logic); END ENTITY CoreAHBLtoAXI_AXIAccessControlHX; ARCHITECTURE translated OF CoreAHBLtoAXI_AXIAccessControlHX IS CONSTANT AXI_WRSTB : integer := AXI_DWIDTH / 8; CONSTANT WRITE_C : std_logic := '1'; -- write constant CONSTANT READ_C : std_logic := '0'; -- read constant CONSTANT RESPOK_C : std_logic_vector(1 DOWNTO 0) := "00"; -- response OKAY from AXI CONSTANT RESPERR_C : std_logic_vector(1 DOWNTO 0) := "01"; -- response ERROR from AXI -- State machine variables CONSTANT IDLE : std_logic_vector(2 DOWNTO 0) := "000"; CONSTANT SEND_WR_ADDR : std_logic_vector(2 DOWNTO 0) := "001"; CONSTANT SEND_WR_DATA : std_logic_vector(2 DOWNTO 0) := "010"; CONSTANT READ_WR_RESP : std_logic_vector(2 DOWNTO 0) := "011"; CONSTANT SEND_RD_ADDR : std_logic_vector(2 DOWNTO 0) := "100"; CONSTANT READ_RD_DATA : std_logic_vector(2 DOWNTO 0) := "101"; CONSTANT SHIFT_DATA_BYTE : std_logic_vector(7 DOWNTO 0) := "00000001"; CONSTANT SHIFT_DATA_HW : std_logic_vector(7 DOWNTO 0) := "00000011"; CONSTANT SHIFT_DATA_WORD : std_logic_vector(7 DOWNTO 0) := "00001111"; FUNCTION to_integer ( val : std_logic_vector) RETURN integer IS CONSTANT vec : std_logic_vector(val'high-val'low DOWNTO 0) := val; VARIABLE rtn : integer := 0; BEGIN FOR index IN vec'RANGE LOOP IF (vec(index) = '1') THEN rtn := rtn + (2index); END IF; END LOOP; RETURN(rtn); END to_integer; FUNCTION ShiftRight ( val : std_logic_vector; shft : integer) RETURN std_logic_vector IS VARIABLE int : std_logic_vector(val'LENGTH+shft-1 DOWNTO 0); VARIABLE rtn : std_logic_vector(val'RANGE); VARIABLE fill : std_logic_vector(shft-1 DOWNTO 0) := (others => '0'); BEGIN int := fill & val; rtn := int(val'LENGTH+shft-1 DOWNTO shft); RETURN(rtn); END ShiftRight; FUNCTION ShiftLeft(s1:std_logic_vector;nn:integer) return std_logic_vector is -- shift left by nn bits, add nn 0s to LSBs -- Example s1 = 11111101, nn = 3, return = 11101000 --It is in effect unsigned multiplication by 2^nn --variable rr : std_logic_vector(s1'high downto s1'low); variable rr : std_logic_vector(7 downto 0); begin if(nn < 0) then assert false report "shln: shift index nn is negative,can't shift" severity error; end if; if(nn = 0) then rr := s1; else rr := (others => '0'); --for ii in s1'high downto s1'low+1 loop for ii in 7 downto 0 loop rr(ii) := s1(ii-nn); if(ii = nn) then exit; end if; end loop; end if; return rr; end ShiftLeft; FUNCTION to_stdlogic ( val : IN boolean) RETURN std_logic IS BEGIN IF (val) THEN RETURN('1'); ELSE RETURN('0'); END IF; END to_stdlogic; FUNCTION conv_std_logic ( val : IN boolean) RETURN std_logic IS BEGIN RETURN(to_stdlogic(val)); END conv_std_logic; ------------------------------------------------------------------------------- -- Register Declarations ------------------------------------------------------------------------------- SIGNAL wvalid_reg : std_logic; SIGNAL axi_current_state : std_logic_vector(2 DOWNTO 0); SIGNAL axi_next_state : std_logic_vector(2 DOWNTO 0); SIGNAL HSEL_sync : std_logic; SIGNAL HADDR_sync : std_logic_vector(AHB_AWIDTH - 1 DOWNTO 0) ; SIGNAL HWRITE_sync : std_logic; SIGNAL HREADY_sync : std_logic; SIGNAL HTRANS_sync : std_logic_vector(1 DOWNTO 0); SIGNAL HSIZE_sync : std_logic_vector(2 DOWNTO 0); SIGNAL HBURST_sync : std_logic_vector(2 DOWNTO 0); SIGNAL HMASTLOCK_sync : std_logic; SIGNAL awaddr_awvalid_set : std_logic; SIGNAL wvalid_set : std_logic; SIGNAL wvalid_clr : std_logic; SIGNAL bready_set : std_logic; SIGNAL burstcount_load : std_logic; SIGNAL burstcount_dec : std_logic; SIGNAL burstcount_dec_r : std_logic; SIGNAL latch_wr_resp : std_logic_vector(1 DOWNTO 0); SIGNAL latch_wr_resp_set : std_logic; SIGNAL axiwr_burst_length : std_logic_vector(3 DOWNTO 0); SIGNAL axird_burst_length : std_logic_vector(3 DOWNTO 0); SIGNAL axi_burst_type : std_logic_vector(1 DOWNTO 0); SIGNAL awaddr_awvalid_clr : std_logic; SIGNAL burstcount_reg : std_logic_vector(4 DOWNTO 0); SIGNAL burstcount_reg_r : std_logic_vector(4 DOWNTO 0); SIGNAL burst_count_r_sync : std_logic_vector(3 DOWNTO 0); SIGNAL rdch_write_data_r : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL rd_data_c : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0) ; SIGNAL axi_read_data : std_logic; SIGNAL rready_set : std_logic; SIGNAL axi_read_resp : std_logic_vector(1 DOWNTO 0); SIGNAL ahb_rd_req_sync_d : std_logic; SIGNAL latch_ahb_sig_sync_d : std_logic; SIGNAL axi_wstrb : std_logic_vector((AXI_DWIDTH / 8) - 1 DOWNTO 0); SIGNAL swap_rd_data_byte : std_logic_vector(3 DOWNTO 0); SIGNAL axi_wrdata : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL wrstb_count : std_logic_vector(1 DOWNTO 0); SIGNAL AWADDR_incr : std_logic_vector(2 DOWNTO 0); SIGNAL axi_wr_data_d : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL awaddr_awvalid_clr_d : std_logic; SIGNAL araddr_arvalid_clr_d : std_logic; SIGNAL araddr_arvalid_set : std_logic; SIGNAL araddr_arvalid_clr : std_logic; SIGNAL WREADY_reg : std_logic; SIGNAL BVALID_reg : std_logic; SIGNAL wvalid_reg_r : std_logic; SIGNAL wvalid_set_r : std_logic; SIGNAL wvalid_set_r1 : std_logic; SIGNAL wvalid_clr_t : std_logic; SIGNAL wvalid_clr_r : std_logic; SIGNAL axi_wr_data_lat : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; ------------------------------------------------------------------------------- -- Wire Declarations ------------------------------------------------------------------------------- SIGNAL rd_haddr : std_logic_vector(AHB_AWIDTH - 1 DOWNTO 0) ; SIGNAL axi_rd_start : std_logic; SIGNAL store_ahb_sig : std_logic; SIGNAL undef_wr_burst_size_32 : std_logic_vector(3 DOWNTO 0); SIGNAL undef_rd_burst_size_32 : std_logic_vector(3 DOWNTO 0); SIGNAL undef_wr_burst_size_64 : std_logic_vector(3 DOWNTO 0); SIGNAL undef_rd_burst_size_64 : std_logic_vector(3 DOWNTO 0); SIGNAL temp_xhdl28 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl29 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl30 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl31 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl32 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl33 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl34 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl35 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl36 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl37 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl38 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl39 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl40 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl41 : std_logic_vector(7 DOWNTO 0); SIGNAL temp_xhdl42 : std_logic; SIGNAL temp_xhdl43 : std_logic_vector(3 DOWNTO 0); SIGNAL temp_xhdl45 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl46 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl47 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl48 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl49 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl50 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl51 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl52 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl53 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl54 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl70 : std_logic; SIGNAL AWID_xhdl1 : std_logic_vector(3 DOWNTO 0); SIGNAL AWADDR_xhdl2 : std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0) ; SIGNAL AWLEN_xhdl3 : std_logic_vector(3 DOWNTO 0); SIGNAL AWSIZE_xhdl4 : std_logic_vector(2 DOWNTO 0); SIGNAL AWBURST_xhdl5 : std_logic_vector(1 DOWNTO 0); SIGNAL AWVALID_xhdl6 : std_logic; SIGNAL AWVALID_xhdl6_int : std_logic; SIGNAL WID_xhdl7 : std_logic_vector(3 DOWNTO 0); SIGNAL WDATA_xhdl8 : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL WSTRB_xhdl9 : std_logic_vector(AXI_WRSTB - 1 DOWNTO 0); SIGNAL WLAST_xhdl10 : std_logic; SIGNAL WVALID_xhdl11 : std_logic; SIGNAL BREADY_xhdl12 : std_logic; SIGNAL ARID_xhdl13 : std_logic_vector(3 DOWNTO 0); SIGNAL ARADDR_xhdl14 : std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0) ; SIGNAL ARLEN_xhdl15 : std_logic_vector(3 DOWNTO 0); SIGNAL ARSIZE_xhdl16 : std_logic_vector(2 DOWNTO 0); SIGNAL ARBURST_xhdl17 : std_logic_vector(1 DOWNTO 0); SIGNAL ARLOCK_xhdl18 : std_logic_vector(1 DOWNTO 0); SIGNAL ARVALID_xhdl19 : std_logic; SIGNAL ARVALID_xhdl19_int : std_logic; SIGNAL RREADY_xhdl20 : std_logic; SIGNAL AWLOCK_xhdl21 : std_logic_vector(1 DOWNTO 0); SIGNAL WRCH_fifo_rd_en_xhdl22 : std_logic; SIGNAL BRESP_sync_xhdl23 : std_logic_vector(1 DOWNTO 0); SIGNAL rdch_fifo_wr_en_r_xhdl24 : std_logic; SIGNAL rdch_fifo_wr_data_xhdl25 : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0) ; SIGNAL axi_read_rlast_xhdl26 : std_logic; SIGNAL axi_burst_length_ahb32 : std_logic; SIGNAL axi_burst_length_ahb64 : std_logic; SIGNAL axiwr_burst_length_ahb32 : std_logic; SIGNAL axiwr_burst_length_ahb64 : std_logic; BEGIN AWID <= AWID_xhdl1; AWADDR <= AWADDR_xhdl2; AWLEN <= AWLEN_xhdl3; AWSIZE <= AWSIZE_xhdl4; AWBURST <= AWBURST_xhdl5; AWVALID <= AWVALID_xhdl6; WID <= WID_xhdl7; WDATA <= WDATA_xhdl8; WSTRB <= WSTRB_xhdl9; WLAST <= WLAST_xhdl10; WVALID <= WVALID_xhdl11; BREADY <= BREADY_xhdl12; ARID <= ARID_xhdl13; ARADDR <= ARADDR_xhdl14; ARLEN <= ARLEN_xhdl15; ARSIZE <= ARSIZE_xhdl16; ARBURST <= ARBURST_xhdl17; ARLOCK <= ARLOCK_xhdl18; ARVALID <= ARVALID_xhdl19; RREADY <= RREADY_xhdl20; AWLOCK <= AWLOCK_xhdl21; WRCH_fifo_rd_en <= WRCH_fifo_rd_en_xhdl22; BRESP_sync <= BRESP_sync_xhdl23; rdch_fifo_wr_en_r <= rdch_fifo_wr_en_r_xhdl24; rdch_fifo_wr_data <= rdch_fifo_wr_data_xhdl25; axi_read_rlast <= axi_read_rlast_xhdl26; temp_xhdl28 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data(63 DOWNTO 32) & axi_wr_data(31 DOWNTO 0); temp_xhdl29 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl30 <= "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000"; temp_xhdl31 <= axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0); temp_xhdl32 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl33 <= "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(47 DOWNTO 32); temp_xhdl34 <= "00000000000000000000000000000000" & axi_wr_data(31 DOWNTO 16) & axi_wr_data(15 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0); temp_xhdl35 <= axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data(63 DOWNTO 48) & axi_wr_data(47 DOWNTO 32) & "00000000000000000000000000000000"; temp_xhdl36 <= axi_wr_data(31 DOWNTO 16) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000"; temp_xhdl37 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(31 DOWNTO 0) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl38 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl39 <= axi_wr_data(31 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data_d(63 DOWNTO 32) & "00000000000000000000000000000000"; temp_xhdl40 <= "00000000000000000000000000000000" & axi_wr_data(31 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data_d(63 DOWNTO 32); --///////////////////////////////////////////////////////////////////////////// -- Start-of-code // --///////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------------------------- -- Generate the write data to be sent to the AXI interface -- This is the 64-bit data read from the WRCHANNEL fifo and sent on the Write -- data channel on the AXI bus ------------------------------------------------------------------------------- PROCESS (AWADDR_incr, HSIZE_sync, HBURST_sync, axi_wr_data, HADDR_sync, temp_xhdl28, temp_xhdl29, temp_xhdl30, temp_xhdl31, temp_xhdl32, temp_xhdl33, temp_xhdl34,temp_xhdl35, temp_xhdl36, temp_xhdl37, temp_xhdl38, temp_xhdl39, temp_xhdl40 ) VARIABLE axi_wrdata_xhdl27 : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); BEGIN CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "11" => axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); WHEN "10" => IF (HBURST_sync(2 DOWNTO 0) = "000") THEN axi_wrdata_xhdl27 := temp_xhdl28; ELSE IF (HBURST_sync(2 DOWNTO 0) = "001") THEN axi_wrdata_xhdl27 := temp_xhdl29; ELSE -- For all bursts IF (HBURST_sync(0) = '1') THEN -- For incr bursts IF (HADDR_sync(2) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; ELSE -- For wrap bursts IF (HADDR_sync(2) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; END IF; END IF; END IF; WHEN "01" => IF (HBURST_sync(2 DOWNTO 0) = "000") THEN -- For Single IF (HADDR_sync(2 DOWNTO 1) = "00") THEN axi_wrdata_xhdl27 := temp_xhdl30; ELSE IF (HADDR_sync(2 DOWNTO 1) = "10") THEN axi_wrdata_xhdl27 := temp_xhdl31; ELSE IF (HADDR_sync(2 DOWNTO 1) = "11") THEN axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 16) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000"; ELSE axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); END IF; END IF; END IF; ELSE IF (HBURST_sync(2 DOWNTO 0) = "001") THEN axi_wrdata_xhdl27 := temp_xhdl32; ELSE -- For Bursts IF (AWADDR_incr(2 DOWNTO 1) = "00") THEN axi_wrdata_xhdl27 := temp_xhdl33; ELSE IF (AWADDR_incr(2 DOWNTO 1) = "01") THEN axi_wrdata_xhdl27 := temp_xhdl34; ELSE IF (AWADDR_incr(2 DOWNTO 1) = "10") THEN axi_wrdata_xhdl27 := temp_xhdl35; ELSE axi_wrdata_xhdl27 := temp_xhdl36; END IF; END IF; END IF; END IF; END IF; WHEN "00" => IF (HBURST_sync(2 DOWNTO 0) = "000") THEN axi_wrdata_xhdl27 := temp_xhdl37; ELSE IF (HBURST_sync(2 DOWNTO 0) = "001") THEN axi_wrdata_xhdl27 := temp_xhdl38; ELSE IF (HBURST_sync(0) = '1') THEN -- For incr bursts IF (AWADDR_incr(2) = '1') THEN axi_wrdata_xhdl27 := temp_xhdl39; ELSE axi_wrdata_xhdl27 := temp_xhdl40; END IF; ELSE -- For wrap bursts IF (HADDR_sync(2) = '0') THEN -- Address less than 4 - lower range IF (AWADDR_incr(2 DOWNTO 0) < "100") THEN IF (AWADDR_incr(0) = '1') THEN axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); ELSE axi_wrdata_xhdl27 := axi_wr_data; END IF; ELSE IF (AWADDR_incr(0) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); ELSE axi_wrdata_xhdl27 := axi_wr_data; END IF; END IF; ELSE -- Address falling in upper range IF (AWADDR_incr(2 DOWNTO 0) >= "100") THEN IF (AWADDR_incr(0) = '1') THEN axi_wrdata_xhdl27 := axi_wr_data; ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; ELSE IF (AWADDR_incr(0) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data; ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; END IF; END IF; END IF; -- else: !if(HBURST_sync[0] == 1'b1) END IF; END IF; -- else: !if(HBURST_sync[2:0] == 3'b001) WHEN -- case: 2'b00 OTHERS => axi_wrdata_xhdl27 := (OTHERS => '0'); END CASE; axi_wrdata <= axi_wrdata_xhdl27; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN burstcount_dec_r <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN burstcount_dec_r <= burstcount_dec; END IF; END PROCESS; temp_xhdl41 <= "00001111" WHEN (AWADDR_incr(2 DOWNTO 0) = "000") ELSE "11110000"; ------------------------------------------------------------------------------- -- Generate the write strobe to be sent to the AXI interface ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN axi_wstrb <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "11" => axi_wstrb <= '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1'; WHEN "10" => IF ((HBURST_sync(2 DOWNTO 0) = "000") OR ((HBURST_sync(2 DOWNTO 0) = "001") AND (UNDEF_BURST = 0))) THEN -- For Single/Undef IF (HADDR_sync(2 DOWNTO 0) = "000") THEN axi_wstrb <= "00001111"; ELSE IF (HADDR_sync(2 DOWNTO 0) = "100") THEN axi_wstrb <= "11110000"; END IF; END IF; ELSE -- For all bursts IF (HBURST_sync(0) = '1') THEN -- For incr bursts IF (HADDR_sync(2) = '1') THEN -- 30/01/13 - check whether start addr = '4 IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN --axi_wstrb <= ShiftLeft("00001111", to_integer(HADDR_sync(2 DOWNTO 0))) ; IF ((HADDR_sync(2)) = '1') THEN axi_wstrb <= "11110000"; ELSE axi_wstrb <= "00001111"; END IF; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF (axi_wstrb = "11110000") THEN axi_wstrb <= "00001111"; ELSE --axi_wstrb <= ShiftLeft(axi_wstrb, 4); axi_wstrb <= axi_wstrb(3 DOWNTO 0) & "0000"; END IF; END IF; END IF; -- if (HADDR_sync[2] == 1'b1) ELSE axi_wstrb <= '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1'; END IF; ELSE -- For wrap bursts IF (burstcount_reg = "00000") THEN axi_wstrb <= axi_wstrb; ELSE IF (((WVALID_xhdl11 AND WREADY) AND CONV_STD_LOGIC(axi_wstrb = "11110000")) = '1') THEN axi_wstrb <= "00001111"; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN --axi_wstrb <= ShiftLeft(axi_wstrb, 4); axi_wstrb <= axi_wstrb(3 DOWNTO 0) & "0000"; ELSE IF (wvalid_set_r = '1') THEN axi_wstrb <= temp_xhdl41; END IF; END IF; END IF; END IF; END IF; END IF; WHEN "01" => IF ((HBURST_sync(2 DOWNTO 0) = "000") OR ((HBURST_sync(2 DOWNTO 0) = "001") AND (UNDEF_BURST = 0))) THEN --axi_wstrb <= ShiftLeft("00000011", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 1)) = "00") THEN axi_wstrb <= "00000011"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "01") THEN axi_wstrb <= "00001100"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "10") THEN axi_wstrb <= "00110000"; ELSE axi_wstrb <= "11000000"; END IF; ELSE -- For all bursts IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN --axi_wstrb <= ShiftLeft("00000011", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 1)) = "00") THEN axi_wstrb <= "00000011"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "01") THEN axi_wstrb <= "00001100"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "10") THEN axi_wstrb <= "00110000"; ELSE axi_wstrb <= "11000000"; END IF; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF (axi_wstrb = "11000000") THEN axi_wstrb <= "00000011"; ELSE --axi_wstrb <= ShiftLeft(axi_wstrb, 2); axi_wstrb <= axi_wstrb(5 DOWNTO 0) & "00"; END IF; END IF; END IF; END IF; WHEN "00" => IF ((HBURST_sync(2 DOWNTO 0) = "000") OR ((HBURST_sync(2 DOWNTO 0) = "001") AND (UNDEF_BURST = 0))) THEN --axi_wstrb <= ShiftLeft("00000001", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 0)) = "111") THEN axi_wstrb <= "10000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "110") THEN axi_wstrb <= "01000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "101") THEN axi_wstrb <= "00100000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "100") THEN axi_wstrb <= "00010000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "011") THEN axi_wstrb <= "00001000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "010") THEN axi_wstrb <= "00000100"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "001") THEN axi_wstrb <= "00000010"; ELSE axi_wstrb <= "00000001"; END IF; ELSE -- For all bursts IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN --axi_wstrb <= ShiftLeft("00000001", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 0)) = "111") THEN axi_wstrb <= "10000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "110") THEN axi_wstrb <= "01000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "101") THEN axi_wstrb <= "00100000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "100") THEN axi_wstrb <= "00010000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "011") THEN axi_wstrb <= "00001000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "010") THEN axi_wstrb <= "00000100"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "001") THEN axi_wstrb <= "00000010"; ELSE axi_wstrb <= "00000001"; END IF; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF (axi_wstrb = "10000000") THEN axi_wstrb <= "00000001"; ELSE --axi_wstrb <= ShiftLeft(axi_wstrb, 1); axi_wstrb <= axi_wstrb(6 DOWNTO 0) & '0'; END IF; END IF; END IF; END IF; -- For Single/Undef WHEN OTHERS => axi_wstrb <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0'; END CASE; END IF; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN wrstb_count <= "00"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (WLAST_xhdl10 = '1') THEN wrstb_count <= "00"; ELSE IF ((wvalid_reg = '1') AND (axi_next_state = SEND_WR_DATA)) THEN wrstb_count <= wrstb_count + "01"; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Generate the address increment logic on AXI -- This is write data generation on the AXI interface ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN latch_ahb_sig_sync_d <= '0'; axi_wr_data_d <= (OTHERS => '0'); AWADDR_incr <= "000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN latch_ahb_sig_sync_d <= latch_ahb_sig_sync; axi_wr_data_d <= axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN AWADDR_incr <= AWADDR_xhdl2(2 DOWNTO 0); ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF ((HSIZE_sync(1 DOWNTO 0)) = "00") THEN AWADDR_incr <= AWADDR_incr + "001"; ELSIF ((HSIZE_sync(1 DOWNTO 0)) = "01") THEN AWADDR_incr <= AWADDR_incr + "010"; ELSE AWADDR_incr <= AWADDR_incr + "100"; END IF; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Create a sync pulse to trigger the AXI state machine when there is valid -- AHB command ------------------------------------------------------------------------------- store_ahb_sig <= latch_ahb_sig_sync AND (NOT latch_ahb_sig_sync_d) ; ------------------------------------------------------------------------------- -- Synchronize the AHB signals to AXI clock on store_ahb_sig signal ------------------------------------------------------------------------------- ahb_to_axi_latch_logic : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN HSEL_sync <= '0'; HADDR_sync <= (OTHERS => '0'); HWRITE_sync <= '0'; HREADY_sync <= '0'; HTRANS_sync <= "00"; HSIZE_sync <= "000"; HBURST_sync <= "000"; HMASTLOCK_sync <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (store_ahb_sig = '1') THEN HSEL_sync <= HSEL; HADDR_sync <= HADDR; HWRITE_sync <= HWRITE; HREADY_sync <= HREADY; HTRANS_sync <= HTRANS; HSIZE_sync <= HSIZE; HBURST_sync <= HBURST; HMASTLOCK_sync <= HMASTLOCK; END IF; END IF; END PROCESS ahb_to_axi_latch_logic; L0: IF (UNDEF_BURST = 1) GENERATE undef_wr_burst_size_32 <= "0111" ; undef_wr_burst_size_64 <= "1111" ; undef_rd_burst_size_32 <= "1111" ; undef_rd_burst_size_64 <= "1111" ; END GENERATE L0; L1: IF (NOT(UNDEF_BURST = 1)) GENERATE undef_wr_burst_size_32 <= "0000" ; undef_wr_burst_size_64 <= "0000" ; undef_rd_burst_size_32 <= "0000" ; undef_rd_burst_size_64 <= "0000" ; END GENERATE L1; L2: IF (AHB_DWIDTH = 32) GENERATE ------------------------------------------------------------------------------- -- Generate AXI Write channel Burst Length from HBURST and HSYNC ------------------------------------------------------------------------------- PROCESS ( HSIZE_sync, HADDR_sync, undef_wr_burst_size_32, HBURST_sync) BEGIN IF (HSIZE_sync(1 DOWNTO 0) = "00") THEN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) -- if (HSIZE_sync[1:0] == 2'b00) ELSE IF (HSIZE_sync(1 DOWNTO 0) = "01") THEN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) -- if (HSIZE_sync[1:0] == 2'b01) ELSE IF (HADDR_sync(2) = '0') THEN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0001"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0011"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "0111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) -- if (HSIZE_sync[1:0] == 2'b01) ELSE CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) END IF; END IF; END IF; -- else: !if(HSIZE_sync[1:0] == 2'b10) END PROCESS; END GENERATE L2; L3: IF (NOT(AHB_DWIDTH = 32)) GENERATE -- always @ () -- block: axiwr_burst_length_ahb32 PROCESS (undef_wr_burst_size_64, HBURST_sync) BEGIN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_64; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) END PROCESS; END GENERATE L3; L4: IF (AHB_DWIDTH = 32) GENERATE ------------------------------------------------------------------------------- -- Generate AXI Read channel Burst Length from HBURST and HSYNC ------------------------------------------------------------------------------- PROCESS (undef_rd_burst_size_32, HBURST_sync) BEGIN -- orig CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axird_burst_length <= "0000"; WHEN "001" => axird_burst_length <= undef_rd_burst_size_32; WHEN "010" => axird_burst_length <= "0011"; WHEN "011" => axird_burst_length <= "0011"; WHEN "100" => axird_burst_length <= "0111"; WHEN "101" => axird_burst_length <= "0111"; WHEN "110" => axird_burst_length <= "1111"; WHEN "111" => axird_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; END PROCESS; END GENERATE L4; L5: IF (NOT(AHB_DWIDTH = 32)) GENERATE -- always @ () PROCESS (undef_rd_burst_size_64, HBURST_sync) BEGIN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axird_burst_length <= "0000"; WHEN "001" => axird_burst_length <= undef_rd_burst_size_64; WHEN "010" => axird_burst_length <= "0011"; WHEN "011" => axird_burst_length <= "0011"; WHEN "100" => axird_burst_length <= "0111"; WHEN "101" => axird_burst_length <= "0111"; WHEN "110" => axird_burst_length <= "1111"; WHEN "111" => axird_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; END PROCESS; END GENERATE L5; ------------------------------------------------------------------------------- -- Extract AXI Burst type from HBURST ------------------------------------------------------------------------------- PROCESS (HBURST_sync) BEGIN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axi_burst_type <= "01"; WHEN "001" => axi_burst_type <= "01"; WHEN "010" => axi_burst_type <= "10"; WHEN "011" => axi_burst_type <= "01"; WHEN "100" => axi_burst_type <= "10"; WHEN "101" => axi_burst_type <= "01"; WHEN "110" => axi_burst_type <= "10"; WHEN "111" => axi_burst_type <= "01"; WHEN OTHERS => NULL; END CASE; END PROCESS; ------------------------------------------------------------------------------- -- Synchronize burst count value received from the AHB Access Control logic -- This is used for for loading the initial value in burstcount_reg signal ------------------------------------------------------------------------------- sync_ahb_2_axi : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN burst_count_r_sync <= "0000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (burst_count_valid_sync = '1') THEN burst_count_r_sync <= burst_count_r(3 DOWNTO 0); END IF; END IF; END PROCESS sync_ahb_2_axi; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN awaddr_awvalid_clr_d <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN awaddr_awvalid_clr_d <= awaddr_awvalid_clr; END IF; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN araddr_arvalid_clr_d <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN araddr_arvalid_clr_d <= araddr_arvalid_clr; END IF; END PROCESS; --***************************************************************// -- Write Data Channel // --*************************************************************// ------------------------------------------------------------------------------- -- Latch AHB signals into AXI domain on synchronised control signal ------------------------------------------------------------------------------- WDATA_xhdl8 <= axi_wrdata(AXI_DWIDTH - 1 DOWNTO 0) ; WSTRB_xhdl9 <= axi_wstrb ; WID_xhdl7 <= "0000" ; WLAST_xhdl10 <= wvalid_clr ; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN WREADY_reg <= '0'; wvalid_reg_r <= '0'; wvalid_clr_r <= '0'; axi_wr_data_lat <= (OTHERS => '0'); ELSIF (ACLK'EVENT AND ACLK = '1') THEN WREADY_reg <= WREADY; wvalid_reg_r <= wvalid_reg; wvalid_clr_r <= wvalid_clr; axi_wr_data_lat <= axi_wrdata; END IF; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN wvalid_set_r <= '0'; wvalid_set_r1 <= '0'; burstcount_reg_r <= "00000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN wvalid_set_r <= wvalid_set AND NOT wvalid_reg; wvalid_set_r1 <= wvalid_set_r; burstcount_reg_r <= burstcount_reg; END IF; END PROCESS; ------------------------------------------------------------------------------- -- The logic is used to de-assert the WVALID ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN wvalid_clr_t <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (axi_current_state = SEND_WR_DATA AND wvalid_clr = '1') THEN wvalid_clr_t <= '1'; ELSE wvalid_clr_t <= '0'; END IF; END IF; END PROCESS; temp_xhdl42 <= ((NOT wvalid_clr AND wvalid_reg) AND CONV_STD_LOGIC(axi_next_state = SEND_WR_DATA)) WHEN WREADY = '1' ELSE wvalid_reg; ------------------------------------------------------------------------------- -- Generation of WVALID signal -- wvalid_set asserts the WVALID and wvalid_clr signal de-asserts it. ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN WVALID_xhdl11 <= '0'; wvalid_reg <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (wvalid_clr = '1' AND WREADY = '1') THEN wvalid_reg <= '0'; ELSE IF (wvalid_set = '1' AND wvalid_clr_t = '0') THEN wvalid_reg <= '1'; END IF; END IF; WVALID_xhdl11 <= temp_xhdl42; END IF; END PROCESS; --*************************************************************// -- Write Address Channel // --*************************************************************// ------------------------------------------------------------------------------- -- Write address channel generation ------------------------------------------------------------------------------- AWVALID_xhdl6 <= '0' WHEN awaddr_awvalid_clr_d = '1' ELSE AWVALID_xhdl6_int; AWVALID_xhdl6_int <= '1' WHEN awaddr_awvalid_set = '1' ELSE '0'; PROCESS (HADDR_sync, axiwr_burst_length(3 DOWNTO 0), axi_burst_type(1 DOWNTO 0), HMASTLOCK_sync, HBURST_sync(2 DOWNTO 0), HSIZE_sync(2 DOWNTO 0)) BEGIN AWADDR_xhdl2 <= HADDR_sync(AXI_AWIDTH - 1 DOWNTO 0); AWID_xhdl1 <= "0000"; AWLEN_xhdl3 <= axiwr_burst_length(3 DOWNTO 0); AWBURST_xhdl5 <= axi_burst_type(1 DOWNTO 0); AWLOCK_xhdl21 <= HMASTLOCK_sync & '0'; IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN AWSIZE_xhdl4 <= HSIZE_sync(2 DOWNTO 0); ELSE -- For all bursts IF (HBURST_sync(0) = '1') THEN -- For incr IF (HADDR_sync(2) = '0') THEN -- 30/01/13 added to check whether address starts from '4 CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "00" => AWSIZE_xhdl4 <= "000"; -- 1 bytes in one transfer WHEN "01" => AWSIZE_xhdl4 <= "001"; -- 2 bytes in one transfer WHEN "10" => AWSIZE_xhdl4 <= "011"; -- 8 bytes in one transfer WHEN "11" => AWSIZE_xhdl4 <= "011"; WHEN OTHERS => AWSIZE_xhdl4 <= "011"; END CASE; -- case (HSIZE_sync[1:0]) ELSE CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "00" => AWSIZE_xhdl4 <= "000"; -- 1 bytes in one transfer WHEN "01" => AWSIZE_xhdl4 <= "001"; -- 2 bytes in one transfer WHEN "10" => AWSIZE_xhdl4 <= "010"; -- 4 bytes in one transfer WHEN "11" => AWSIZE_xhdl4 <= "011"; WHEN OTHERS => AWSIZE_xhdl4 <= "011"; END CASE; -- case (HSIZE_sync[1:0]) END IF; ELSE -- For wrap CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "00" => AWSIZE_xhdl4 <= "000"; -- 1 bytes in one transfer WHEN "01" => AWSIZE_xhdl4 <= "001"; -- 2 bytes in one transfer WHEN "10" => AWSIZE_xhdl4 <= "010"; -- 4 bytes in one transfer WHEN "11" => AWSIZE_xhdl4 <= "011"; WHEN OTHERS => AWSIZE_xhdl4 <= "011"; END CASE; -- case (HSIZE_sync[1:0]) END IF; END IF; END PROCESS; temp_xhdl43 <= ShiftRight(burst_count_r_sync(3 DOWNTO 0), 1) WHEN (HADDR_sync(2) = '0') ELSE burst_count_r_sync(3 DOWNTO 0); ------------------------------------------------------------------------------- -- burstcount_reg holds the burst count value -- The count value is decremented on the burstcount_dec assertion ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN burstcount_reg <= "00000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN -- Load the burst count value IF (burstcount_load = '1') THEN IF ((HSIZE_sync(1 DOWNTO 0) = "00" AND HBURST_sync /= "000") AND HBURST_sync /= "001") THEN -- Byte bursts IF (HBURST_sync(0) = '1') THEN -- incr burstcount_reg <= "00001" + (burst_count_r_sync(3 DOWNTO 0)); ELSE -- wrap burstcount_reg <= "0" & burst_count_r_sync(3 DOWNTO 0); END IF; ELSE IF ((HSIZE_sync(1 DOWNTO 0) = "01" AND HBURST_sync /= "000") AND HBURST_sync /= "001") THEN -- HW bursts burstcount_reg <= "00001" + (burst_count_r_sync(3 DOWNTO 0)); ELSE IF ((HSIZE_sync(1 DOWNTO 0) = "10" AND HBURST_sync /= "000") AND HBURST_sync /= "001") THEN -- Word bursts IF (HBURST_sync(0) = '1') THEN burstcount_reg <= "00001" + (temp_xhdl43); ELSE -- wrap burstcount_reg <= "0" & burst_count_r_sync(3 DOWNTO 0); END IF; ELSE IF (HSIZE_sync(1 DOWNTO 0) = "10" AND HBURST_sync = "001") THEN -- Word undef burstcount_reg <= "00001" + ShiftRight(burst_count_r_sync(3 DOWNTO 0), 1); ELSE -- Single burstcount_reg <= "00001" + ShiftRight(burst_count_r_sync(3 DOWNTO 0), 1); END IF; END IF; END IF; END IF; ELSE IF (burstcount_dec = '1') THEN burstcount_reg <= burstcount_reg - "00001"; END IF; END IF; END IF; END PROCESS; --*************************************************************// -- Write Response Channel // --*************************************************************// ------------------------------------------------------------------------------- -- Generation of BREADY write response ready signal -- BREADY is always asserted ------------------------------------------------------------------------------- BREADY_xhdl12 <= '1' ; BRESP_sync_xhdl23 <= latch_wr_resp(1 DOWNTO 0) ; ------------------------------------------------------------------------------- -- Latch the write response received on the response channel ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN latch_wr_resp <= "00"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN -- write response IF (latch_wr_resp_set = '1') THEN latch_wr_resp(1 DOWNTO 0) <= BRESP(1 DOWNTO 0); END IF; END IF; -- else: !if(ARESETn == 1'b0) END PROCESS; -- always @ (posedge ACLK or negedge ARESETn) PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN BVALID_reg <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN BVALID_reg <= BVALID; END IF; END PROCESS; --*************************************************************// -- Read Address Channel // --*************************************************************// ------------------------------------------------------------------------------- -- AXI Read Address channel generation ------------------------------------------------------------------------------- ARVALID_xhdl19 <= '0' WHEN araddr_arvalid_clr_d = '1' ELSE ARVALID_xhdl19_int; ARVALID_xhdl19_int <= '1' WHEN araddr_arvalid_set = '1' ELSE '0'; PROCESS (HADDR_sync, axird_burst_length(3 DOWNTO 0), HSIZE_sync(2 DOWNTO 0), axi_burst_type(1 DOWNTO 0), HMASTLOCK_sync) BEGIN ARADDR_xhdl14 <= HADDR_sync(AXI_AWIDTH - 1 DOWNTO 0); ARID_xhdl13 <= "0000"; ARLEN_xhdl15 <= axird_burst_length(3 DOWNTO 0); ARSIZE_xhdl16 <= HSIZE_sync(2 DOWNTO 0); ARBURST_xhdl17 <= axi_burst_type(1 DOWNTO 0); ARLOCK_xhdl18 <= HMASTLOCK_sync & '0'; END PROCESS; ------------------------------------------------------------------------------- -- Generation of write enable to RDCHANNEL fifo ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN ahb_rd_req_sync_d <= '0'; rdch_fifo_wr_en_r_xhdl24 <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN ahb_rd_req_sync_d <= ahb_rd_req_sync; rdch_fifo_wr_en_r_xhdl24 <= axi_read_data; END IF; END PROCESS; --*************************************************************// -- Read Data Channel // --***************************************************************// ------------------------------------------------------------------------------- -- Generation of RREADY ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN RREADY_xhdl20 <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (rready_set = '1') THEN RREADY_xhdl20 <= '1'; ELSE RREADY_xhdl20 <= '0'; END IF; END IF; END PROCESS; rd_haddr <= HADDR_sync ; ------------------------------------------------------------------------------- -- Latch the incoming read data from the AXI Read data channel ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN rdch_write_data_r <= (OTHERS => '0'); ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (axi_read_data = '1') THEN rdch_write_data_r(AXI_DWIDTH - 1 DOWNTO 0) <= RDATA(AXI_DWIDTH - 1 DOWNTO 0); END IF; END IF; END PROCESS; temp_xhdl45 <= rdch_write_data_r(31 DOWNTO 0) WHEN (swap_rd_data_byte(0) = '1') ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl46 <= rdch_write_data_r(63 DOWNTO 32) WHEN (swap_rd_data_byte(0) = '1') ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl47 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "01") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl48 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "11") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl49 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "01") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl50 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "11") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl51 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(2 DOWNTO 0) = "001") OR (swap_rd_data_byte(2 DOWNTO 0) = "010") OR (swap_rd_data_byte(2 DOWNTO 0) = "011") OR (swap_rd_data_byte(2 DOWNTO 0) = "000")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl52 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(2 DOWNTO 0) = "101") OR (swap_rd_data_byte(2 DOWNTO 0) = "110") OR (swap_rd_data_byte(2 DOWNTO 0) = "111") OR (swap_rd_data_byte(2 DOWNTO 0) = "100")) ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl53 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(3 DOWNTO 0) = "0001") OR (swap_rd_data_byte(3 DOWNTO 0) = "0010") OR (swap_rd_data_byte(3 DOWNTO 0) = "1001") OR (swap_rd_data_byte(3 DOWNTO 0) = "1010") OR (swap_rd_data_byte(3 DOWNTO 0) = "1011") OR (swap_rd_data_byte(3 DOWNTO 0) = "1100") OR (swap_rd_data_byte(3 DOWNTO 0) = "0011") OR (swap_rd_data_byte(3 DOWNTO 0) = "0100")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl54 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(3 DOWNTO 0) = "1000") OR (swap_rd_data_byte(3 DOWNTO 0) = "0101") OR (swap_rd_data_byte(3 DOWNTO 0) = "1101") OR (swap_rd_data_byte(3 DOWNTO 0) = "1110") OR (swap_rd_data_byte(3 DOWNTO 0) = "1111") OR (swap_rd_data_byte(3 DOWNTO 0) = "0000") OR (swap_rd_data_byte(3 DOWNTO 0) = "0110") OR (swap_rd_data_byte(3 DOWNTO 0) = "0111")) ELSE rdch_write_data_r(31 DOWNTO 0) ; PROCESS (rdch_write_data_r, HSIZE_sync, HBURST_sync, temp_xhdl45, rd_haddr, temp_xhdl46, temp_xhdl47, temp_xhdl48, temp_xhdl49, temp_xhdl50, temp_xhdl51, temp_xhdl52, temp_xhdl53,temp_xhdl54 ) VARIABLE rd_data_c_xhdl44 : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0); BEGIN CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "11" => rd_data_c_xhdl44 := rdch_write_data_r(AXI_DWIDTH - 1 DOWNTO 0) (31 DOWNTO 0); WHEN "10" => IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN -- For Single/undef IF (rd_haddr(2 DOWNTO 0) = "000") THEN rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(31 DOWNTO 0); ELSE rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(63 DOWNTO 32); END IF; ELSE -- For all other burst types IF (rd_haddr(2 DOWNTO 0) = "000") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl45; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl46; END IF; END IF; -- else: !if(HBURST_sync[2:0] == 3'b000) WHEN "01" => IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN -- For Single/undef IF (rd_haddr(2 DOWNTO 0) < "100") THEN IF (rd_haddr(1 DOWNTO 0) = "00" OR rd_haddr(1 DOWNTO 0) = "10") THEN rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(31 DOWNTO 0); ELSE rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(63 DOWNTO 32); END IF; ELSE IF (rd_haddr(1 DOWNTO 0) = "00" OR rd_haddr(1 DOWNTO 0) = "10") THEN rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(63 DOWNTO 32); ELSE rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(31 DOWNTO 0); END IF; END IF; -- else: !if(rd_haddr[2:0] < 3'b100) ELSE -- For all other burst types IF (rd_haddr(2 DOWNTO 0) < "100") THEN IF (rd_haddr(1 DOWNTO 0) = "00") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl47; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl48; END IF; ELSE IF (rd_haddr(1 DOWNTO 0) = "00") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl49; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl50; END IF; END IF; -- else: !if(rd_haddr[2:0] < 3'b100) END IF; -- else: !if(HBURST_sync[2:0] == 3'b000) WHEN "00" => IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN -- For Single/undef IF (rd_haddr(2 DOWNTO 0) < "100") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl51; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl52; END IF; ELSE -- For all other burst types IF (rd_haddr(2 DOWNTO 0) < "100") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl53; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl54; END IF; END IF; WHEN OTHERS => rd_data_c_xhdl44 := (OTHERS => '0'); END CASE; rd_data_c <= rd_data_c_xhdl44; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN swap_rd_data_byte <= "0000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN swap_rd_data_byte <= '0' & HADDR_sync(2 DOWNTO 0); ELSE IF ((ARREADY AND ARVALID_xhdl19) = '1') THEN swap_rd_data_byte <= '0' & ARADDR_xhdl14(2 DOWNTO 0); ELSE IF ((RREADY_xhdl20 AND RVALID) = '1') THEN swap_rd_data_byte <= swap_rd_data_byte + "0001"; END IF; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Write data to RDCHANNEL fifo -- The data is the Read data from AXI Read data channel ------------------------------------------------------------------------------- rdch_fifo_wr_data_xhdl25 <= rd_data_c ; ------------------------------------------------------------------------------- -- Generate start signal for read channel fifo to enable read from AHB side ------------------------------------------------------------------------------- gen_start_for_rdch_read : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN axi_read_rlast_xhdl26 <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN axi_read_rlast_xhdl26 <= (RLAST AND RVALID) AND RREADY_xhdl20; END IF; END PROCESS gen_start_for_rdch_read; ------------------------------------------------------------------------------- -- Invokes the AXI State machine on ahb_rd_req coming from the AHB Access Ctrl ------------------------------------------------------------------------------- axi_rd_start <= NOT ahb_rd_req_sync AND ahb_rd_req_sync_d ; ------------------------------------------------------------------------------- -- Sequential block for State Machine ------------------------------------------------------------------------------- axi_state_machine_seq_logic : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN axi_current_state <= IDLE; ELSIF (ACLK'EVENT AND ACLK = '1') THEN axi_current_state <= axi_next_state; END IF; END PROCESS axi_state_machine_seq_logic; temp_xhdl70 <= burstcount_reg(0) WHEN (HSIZE_sync(1 DOWNTO 0) = "00") ELSE '1'; ------------------------------------------------------------------------------- -- Combinational block for State Machine ------------------------------------------------------------------------------- axi_state_machine_combo_logic : PROCESS (axi_current_state, HSIZE_sync, RVALID, ahb_wr_done_sync, RREADY_xhdl20, HADDR_sync, AWREADY, RLAST, wvalid_reg_r, axi_next_state, ARREADY, BREADY_xhdl12, BVALID_reg, wvalid_set_r, HWRITE_sync, HBURST_sync, WREADY, burstcount_reg, RRESP, wvalid_set_r1, temp_xhdl70, wvalid_reg, axi_rd_start) VARIABLE axi_next_state_xhdl55 : std_logic_vector(2 DOWNTO 0); VARIABLE awaddr_awvalid_set_xhdl56 : std_logic; VARIABLE araddr_arvalid_set_xhdl57 : std_logic; VARIABLE awaddr_awvalid_clr_xhdl58 : std_logic; VARIABLE araddr_arvalid_clr_xhdl59 : std_logic; VARIABLE wvalid_set_xhdl60 : std_logic; VARIABLE wvalid_clr_xhdl61 : std_logic; VARIABLE bready_set_xhdl62 : std_logic; VARIABLE burstcount_load_xhdl63 : std_logic; VARIABLE burstcount_dec_xhdl64 : std_logic; VARIABLE WRCH_fifo_rd_en_xhdl22_xhdl65 : std_logic; VARIABLE latch_wr_resp_set_xhdl66 : std_logic; VARIABLE axi_read_resp_xhdl67 : std_logic_vector(1 DOWNTO 0); VARIABLE axi_read_data_xhdl68 : std_logic; VARIABLE rready_set_xhdl69 : std_logic; BEGIN axi_next_state_xhdl55 := axi_current_state; awaddr_awvalid_set_xhdl56 := '0'; araddr_arvalid_set_xhdl57 := '0'; awaddr_awvalid_clr_xhdl58 := '0'; araddr_arvalid_clr_xhdl59 := '0'; wvalid_set_xhdl60 := '0'; wvalid_clr_xhdl61 := '0'; bready_set_xhdl62 := '0'; burstcount_load_xhdl63 := '0'; burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; latch_wr_resp_set_xhdl66 := '0'; axi_read_resp_xhdl67(1 DOWNTO 0) := "00"; axi_read_data_xhdl68 := '0'; rready_set_xhdl69 := '0'; CASE axi_current_state IS ----------------------------------------- -- IDLE STATE ----------------------------------------- WHEN IDLE => IF (ahb_wr_done_sync = '1') THEN axi_next_state_xhdl55 := SEND_WR_ADDR; ELSE IF (axi_rd_start = '1') THEN axi_next_state_xhdl55 := SEND_RD_ADDR; END IF; END IF; --------------------------------------------- -- SEND WRITE ADDRESS AND CONTROL ON AXI BUS --------------------------------------------- WHEN SEND_WR_ADDR => awaddr_awvalid_set_xhdl56 := '1'; burstcount_load_xhdl63 := '1'; IF (AWREADY = '1') THEN awaddr_awvalid_clr_xhdl58 := '1'; CASE HWRITE_sync IS WHEN WRITE_C => axi_next_state_xhdl55 := SEND_WR_DATA; WHEN READ_C => axi_next_state_xhdl55 := READ_RD_DATA; WHEN OTHERS => NULL; END CASE; ELSE awaddr_awvalid_clr_xhdl58 := '0'; END IF; WHEN SEND_WR_DATA => burstcount_load_xhdl63 := '0'; bready_set_xhdl62 := '1'; wvalid_set_xhdl60 := '1'; IF (HBURST_sync = "000") THEN -- All Single --IF (wvalid_reg_r = '1' AND WREADY = '1') THEN IF (wvalid_reg_r = '1' AND wvalid_reg = '1') THEN --SAR#57250 - WREADY condition added wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (burstcount_reg = "00000") THEN -- Last burst count axi_next_state_xhdl55 := READ_WR_RESP; ELSE -- Not a last burst count IF (wvalid_reg = '1' AND wvalid_set_r = '1') THEN WRCH_fifo_rd_en_xhdl22_xhdl65 := temp_xhdl70; ELSE WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; IF (wvalid_reg_r = '1' AND WREADY = '1') THEN --SAR#57250 - WREADY condition added burstcount_dec_xhdl64 := '1'; ELSE burstcount_dec_xhdl64 := '0'; END IF; END IF; -- For word undef ELSE IF (HBURST_sync = "001" AND HSIZE_sync(1 DOWNTO 0) = "10") THEN IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; -- For Halfword undef ELSE IF (HBURST_sync = "001" AND HSIZE_sync(1 DOWNTO 0) = "01") THEN IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; -- For Byte undef ELSE IF (HBURST_sync = "001" AND HSIZE_sync(1 DOWNTO 0) = "00") THEN IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; ELSE -- All Bursts IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF (HBURST_sync(0) = '1') THEN -- incr bursts IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; IF (HSIZE_sync(1 DOWNTO 0) = "00" OR HSIZE_sync(1 DOWNTO 0) = "01") THEN -- 30/01/13 - check whether start addr = '4 WRCH_fifo_rd_en_xhdl22_xhdl65 := NOT burstcount_reg(0); ELSE IF (HSIZE_sync(1 DOWNTO 0) = "10" AND HADDR_sync(2) = '1') THEN -- 30/01/13 - check whether start addr = '4 WRCH_fifo_rd_en_xhdl22_xhdl65 := NOT burstcount_reg(0); -- else if (HADDR_sync[2] == 1'b0 && HSIZE_sync[1:0] == 2'b10) begin // 30/01/13 - check whether start addr = '4 ELSE -- 30/01/13 - check whether start addr = '4 WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; END IF; END IF; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; ELSE -- wrap bursts IF (((WREADY AND wvalid_reg) AND NOT wvalid_set_r1) = '1') THEN burstcount_dec_xhdl64 := '1'; ELSE burstcount_dec_xhdl64 := '0'; END IF; IF ((wvalid_set_r OR ((NOT burstcount_reg(0) AND WREADY) AND NOT wvalid_set_r1)) = '1') THEN -- wrap WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; -- else: !if(HBURST_sync[0] == 1'b1) END IF; END IF; END IF; END IF; END IF; --------------------------------------------- -- GET WRITE RESPONSE FROM AXI SLAVE --------------------------------------------- WHEN READ_WR_RESP => IF ((BVALID_reg = '1') AND (BREADY_xhdl12 = '1')) THEN latch_wr_resp_set_xhdl66 := '1'; axi_next_state_xhdl55 := IDLE; ELSE latch_wr_resp_set_xhdl66 := '0'; END IF; --------------------------------------------- -- SEND READ ADDRESS AND CONTROL ON AXI BUS --------------------------------------------- WHEN SEND_RD_ADDR => araddr_arvalid_set_xhdl57 := '1'; burstcount_load_xhdl63 := '1'; rready_set_xhdl69 := '1'; IF (ARREADY = '1') THEN araddr_arvalid_clr_xhdl59 := '1'; CASE HWRITE_sync IS WHEN WRITE_C => axi_next_state_xhdl55 := SEND_WR_DATA; WHEN READ_C => axi_next_state_xhdl55 := READ_RD_DATA; WHEN OTHERS => NULL; END CASE; ELSE araddr_arvalid_clr_xhdl59 := '0'; END IF; -- Error respnose WHEN READ_RD_DATA => burstcount_load_xhdl63 := '0'; rready_set_xhdl69 := '1'; axi_read_data_xhdl68 := '0'; IF (RLAST = '1') THEN -- Last burst transfer IF (RVALID = '1') THEN axi_read_data_xhdl68 := '1'; IF (RRESP = RESPOK_C) THEN axi_read_resp_xhdl67(1 DOWNTO 0) := RESPOK_C; ELSE axi_read_resp_xhdl67(1 DOWNTO 0) := RESPERR_C; END IF; axi_next_state_xhdl55 := IDLE; rready_set_xhdl69 := '0'; ELSE END IF; ELSE IF ((RVALID = '1') AND (RREADY_xhdl20 = '1')) THEN axi_read_data_xhdl68 := '1'; IF (RRESP = RESPOK_C) THEN axi_read_resp_xhdl67(1 DOWNTO 0) := RESPOK_C; ELSE axi_read_resp_xhdl67(1 DOWNTO 0) := RESPERR_C; END IF; ELSE END IF; END IF; -- OKAY response WHEN OTHERS => axi_next_state_xhdl55 := axi_current_state; END CASE; axi_next_state <= axi_next_state_xhdl55; awaddr_awvalid_set <= awaddr_awvalid_set_xhdl56; araddr_arvalid_set <= araddr_arvalid_set_xhdl57; awaddr_awvalid_clr <= awaddr_awvalid_clr_xhdl58; araddr_arvalid_clr <= araddr_arvalid_clr_xhdl59; wvalid_set <= wvalid_set_xhdl60; wvalid_clr <= wvalid_clr_xhdl61; bready_set <= bready_set_xhdl62; burstcount_load <= burstcount_load_xhdl63; burstcount_dec <= burstcount_dec_xhdl64; WRCH_fifo_rd_en_xhdl22 <= WRCH_fifo_rd_en_xhdl22_xhdl65; latch_wr_resp_set <= latch_wr_resp_set_xhdl66; axi_read_resp <= axi_read_resp_xhdl67; axi_read_data <= axi_read_data_xhdl68; rready_set <= rready_set_xhdl69; END PROCESS axi_state_machine_combo_logic; END ARCHITECTURE translated;
<filename>ip/MIPI_D_PHY_RX/tb/tb_DPHY_LaneSFEN.vhd ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/04/2016 05:12:32 PM -- Design Name: -- Module Name: tb_DPHY_LaneSFEN - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.math_real.all; use IEEE.std_logic_textio.all; -- I/O for logic types library STD; use STD.textio.all; -- basic I/O -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tb_DPHY_LaneSFEN is -- Port ( ); end tb_DPHY_LaneSFEN; architecture Behavioral of tb_DPHY_LaneSFEN is component DPHY_LaneSFEN is Generic ( kCtlClkFreqHz : natural := 100_000_000 ); Port ( aLP : in STD_LOGIC_VECTOR (1 downto 0); aHS : in STD_LOGIC; CtlClk : in STD_LOGIC; SerClkHS : in STD_LOGIC; DivClk : in STD_LOGIC; RxByteClkHS : out std_logic; rbRxDataHS : out std_logic_vector(7 downto 0); rbRxValidHS : out std_logic; rbRxActiveHS : out std_logic; rbRxSyncHS : out std_logic; rbErrSotHS : out std_logic; rbErrSotSyncHS : out std_logic; aEnable : in std_logic; --Enable Lane Module. DivClk&SerClkHS must be stable aForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state aStopstate : out std_logic --Lane is in Stop state. ); end component DPHY_LaneSFEN; function max(l : time; r : time) return time is begin if (l > r) then return l; else return r; end if; end function max; constant kSerClkPeriod : time := 2 ns; constant kCtlClkPeriod : time := 10 ns; constant kUI : time := kSerClkPeriod / 2; constant kT_LPX : time := 50 ns; constant kT_HS_PREPARE : time := 40 ns + 4kUI; constant kT_HS_ZERO : time := 100 ns + 6kUI; constant kT_HS_TRAIL : time := max(18kUI, 60 ns + 14kUI); constant kT_HS_EXIT : time := 100 ns; constant kTInit : time := 100 us; constant kSyncSeq : std_logic_vector(7 downto 0) := "10111000"; --least significant bit signal SerClkHS, DivClkHS, CtlClk, cHSClkLocked : std_logic := '1'; signal HS : std_logic; signal LP : std_logic_vector(1 downto 0); signal rbRxDataHS : std_logic_vector(7 downto 0); signal rbRxValidHS, rbRxActiveHS, rbRxSyncHS, rbErrSotHS, rbErrSotSyncHS, aDataStopstate : std_logic; signal RxByteClkHS : std_logic; begin DUT: DPHY_LaneSFEN Port map ( aLP => LP, aHS => HS, CtlClk => CtlClk, SerClkHS => SerClkHS, DivClk => DivClkHS, --PPI RxByteClkHS => RxByteClkHS, rbRxDataHS => rbRxDataHS, rbRxValidHS => rbRxValidHS, rbRxActiveHS => rbRxActiveHS, rbRxSyncHS => rbRxSyncHS, rbErrSotHS => rbErrSotHS, rbErrSotSyncHS => rbErrSotSyncHS, aEnable => '1', aStopstate => aDataStopstate, aForceRxmode => '0' ); --Clocks SerClkHS <= not SerClkHS after kSerClkPeriod / 2; DivClkHS <= not DivClkHS after kSerClkPeriod / 2 * 4; CtlClk <= not CtlClk after kCtlClkPeriod / 2; Stimulus: process procedure Stopstate(dur : in time) is begin LP <= "11"; HS <= 'X'; wait for dur; end procedure; procedure HS_Rqst is begin LP <= "01"; wait for kT_LPX; end procedure; procedure HS_Prepare is begin LP <= "00"; wait for kT_HS_PREPARE; end procedure; procedure HS_Zero is begin HS <= '0'; wait for kT_HS_ZERO; end procedure; procedure HS_Send0(nbits : in natural) is begin for i in 0 to nbits-1 loop HS <= '0'; wait until SerClkHS'event; end loop; end procedure; procedure HS_Send(byte : in std_logic_vector(7 downto 0)) is begin for i in 0 to 7 loop wait for kUI / 2; --90deg phase difference between data and clock HS <= byte(i); wait until SerClkHS'event; end loop; end procedure; procedure HS_Trail is begin wait for kUI / 2; HS <= not HS; wait for kT_HS_TRAIL; end procedure; variable seed1, seed2: positive; -- seed values for random generator variable rand: real; -- random real-number value in range 0 to 1.0 variable range_of_rand : real := 10.0; -- the range of random values created will be 0 to +1000. variable to_send : natural; begin Stopstate(kTInit + 1 us); for i in 0 to 7 loop HS_Rqst; HS_Prepare; wait for kUI; -- this will test different word alignments HS_Zero; wait until Falling_Edge(SerClkHS); HS_Send(kSyncSeq); uniform(seed1, seed2, rand); -- generate random number for j in 0 to integer(rand*range_of_rand) loop case (j) is when 0 => HS_Send(x"DE"); when 1 => HS_Send(x"AD"); when 2 => HS_Send(x"BE"); when 3 => HS_Send(x"EF"); when others => HS_Send(std_logic_vector(to_unsigned(j-4,8))); end case; end loop; HS_Trail; Stopstate(kT_HS_EXIT); end loop; wait; end process Stimulus; Verification: process (LP, RxByteClkHS) variable cnt_hs : natural := 0; variable cnt_byte : natural := 0; variable bit_last : std_logic := '1'; variable f_err_hold, f_err_temp, f_intrail : boolean := true; impure function check_data(data : std_logic_vector(7 downto 0); i : natural) return boolean is begin if (not f_intrail) then if (data = (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last)) then f_intrail := true; else bit_last := data(7); --least-significant first end if; else if (data /= (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last)) then f_intrail := false; bit_last := data(7); --least-significant first end if; end if; case (i) is when 0 => f_err_temp := (data = x"DE"); when 1 => f_err_temp := (data = x"AD"); when 2 => f_err_temp := (data = x"BE"); when 3 => f_err_temp := (data = x"EF"); when others => f_err_temp := (data = std_logic_vector(to_unsigned(i-4, 8))); end case; -- Keep the error in mind for later, we might not be in trail after all if (f_intrail) then f_err_hold := f_err_hold and f_err_temp; return true; else return f_err_hold and f_err_temp; end if; end check_data; variable my_line : line; -- type 'line' comes from textio begin if LP'event and LP = "00" then cnt_hs := cnt_hs + 1; cnt_byte := 0; f_intrail := false; f_err_hold := true; bit_last := '1'; --sync sequence last bit end if; if LP = "00" and Rising_Edge(RxByteClkHS) then if rbRxValidHS = '1' then if not check_data(rbRxDataHS, cnt_byte) then write(my_line, string'("Error at byte ")); write(my_line, cnt_byte); write(my_line, string'(", data: ")); hwrite(my_line, rbRxDataHS); write(my_line, string'(", time: ")); write(my_line, now); writeline(output, my_line); end if; cnt_byte := cnt_byte + 1; end if; end if; end process; end Behavioral;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:20:04 05/18/2010 -- Design Name: -- Module Name: /home/silva/Documents/Dropbox/IST/4 Ano/2º Semestre/AAC/Projecto/Parte II/Codigo/17.Maio/4/tadam/teste_flags.vhd -- Project Name: tadam -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Flag_Test -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY teste_flags IS END teste_flags; ARCHITECTURE behavior OF teste_flags IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Flag_Test PORT( NEG : IN std_logic; ZERO : IN std_logic; OVERFLOW : IN std_logic; CARRY : IN std_logic; COND : IN std_logic_vector(3 downto 0); OP : IN std_logic_vector(1 downto 0); UNJUMP : IN std_logic; ENABLE : IN std_logic; SEL : IN std_logic; Z : OUT std_logic ); END COMPONENT; --Inputs signal NEG : std_logic := '0'; signal ZERO : std_logic := '0'; signal OVERFLOW : std_logic := '0'; signal CARRY : std_logic := '0'; signal COND : std_logic_vector(3 downto 0) := (others => '0'); signal OP : std_logic_vector(1 downto 0) := (others => '0'); signal UNJUMP : std_logic := '0'; signal ENABLE : std_logic := '0'; signal SEL : std_logic := '0'; --Outputs signal Z : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Flag_Test PORT MAP ( NEG => NEG, ZERO => ZERO, OVERFLOW => OVERFLOW, CARRY => CARRY, COND => COND, OP => OP, UNJUMP => UNJUMP, ENABLE => ENABLE, SEL => SEL, Z => Z ); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name -- Stimulus process stim_proc: process begin -- insert stimulus here -- 04FD NEG <= '0'; ZERO <= '1','0' after 500 ns; COND <= "0101"; OP <= "00"; ENABLE <= '1'; wait; end process; END;
<filename>FPGA/DSPB_Simulink_Model/DSPB_MMSE/rtl/DSPB_MMSE/DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_atb.vhd<gh_stars>0 -- ------------------------------------------------------------------------- -- High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #625) -- Quartus Prime development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2018 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly -- subject to the terms and conditions of the Intel FPGA Software License -- Agreement, Intel MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by Intel -- and sold by Intel or its authorized distributors. Please refer to the -- applicable agreement for further details. -- --------------------------------------------------------------------------- -- VHDL created from DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror -- VHDL created on Mon Aug 16 17:44:01 2021 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use work.dspba_sim_library_package.all; entity DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_atb is end; architecture normal of DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_atb is component DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror is port ( in_1_valid : in std_logic_vector(0 downto 0); -- ufix1 in_2_input_spectrum : in std_logic_vector(31 downto 0); -- float32_m23 out_1_valid_x : out std_logic_vector(0 downto 0); -- ufix1 out_2_output_spectrum : out std_logic_vector(31 downto 0); -- float32_m23 clk : in std_logic; areset : in std_logic ); end component; component DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_stm is port ( in_1_valid_stm : out std_logic_vector(0 downto 0); in_2_input_spectrum_stm : out std_logic_vector(31 downto 0); out_1_valid_x_stm : out std_logic_vector(0 downto 0); out_2_output_spectrum_stm : out std_logic_vector(31 downto 0); clk : out std_logic; areset : out std_logic ); end component; signal in_1_valid_stm : STD_LOGIC_VECTOR (0 downto 0); signal in_2_input_spectrum_stm : STD_LOGIC_VECTOR (31 downto 0); signal out_1_valid_x_stm : STD_LOGIC_VECTOR (0 downto 0); signal out_2_output_spectrum_stm : STD_LOGIC_VECTOR (31 downto 0); signal in_1_valid_dut : STD_LOGIC_VECTOR (0 downto 0); signal in_2_input_spectrum_dut : STD_LOGIC_VECTOR (31 downto 0); signal out_1_valid_x_dut : STD_LOGIC_VECTOR (0 downto 0); signal out_2_output_spectrum_dut : STD_LOGIC_VECTOR (31 downto 0); signal clk : std_logic; signal areset : std_logic; begin -- General Purpose data in real output checkGPIn : process (clk, areset, in_1_valid_dut, in_1_valid_stm, in_2_input_spectrum_dut, in_2_input_spectrum_stm) variable in_2_input_spectrum_real : REAL := 0.0; variable in_2_input_spectrum_stm_real : REAL := 0.0; begin in_2_input_spectrum_real := vIEEE_2_real(in_2_input_spectrum_dut, 8, 23, false); in_2_input_spectrum_stm_real := vIEEE_2_real(in_2_input_spectrum_stm, 8, 23, false); END PROCESS; -- General Purpose data out check checkGPOut : process (clk, areset) variable mismatch_out_1_valid_x : BOOLEAN := FALSE; variable mismatch_out_2_output_spectrum : BOOLEAN := FALSE; variable out_2_output_spectrum_real : REAL := 0.0; variable out_2_output_spectrum_stm_real : REAL := 0.0; variable ok : BOOLEAN := TRUE; begin IF (areset = '1') THEN -- do nothing during reset ELSIF (clk'EVENT AND clk = '0') THEN -- falling clock edge to avoid transitions ok := TRUE; mismatch_out_1_valid_x := FALSE; mismatch_out_2_output_spectrum := FALSE; out_2_output_spectrum_real := vIEEE_2_real(out_2_output_spectrum_dut, 8, 23, false); out_2_output_spectrum_stm_real := vIEEE_2_real(out_2_output_spectrum_stm, 8, 23, false); IF ( (out_1_valid_x_dut /= out_1_valid_x_stm)) THEN mismatch_out_1_valid_x := TRUE; report "Mismatch on device output pin out_1_valid_x" severity Warning; END IF; IF ( not vIEEEisEqual(out_2_output_spectrum_dut, out_2_output_spectrum_stm, 8, 23, 0.000000e+00, 0.000000e+00)) THEN mismatch_out_2_output_spectrum := TRUE; report "Mismatch on device output pin out_2_output_spectrum" severity Warning; END IF; IF (mismatch_out_1_valid_x or mismatch_out_2_output_spectrum) THEN ok := FALSE; END IF; assert (ok) report "mismatch in general purpose signal. Check the status of any associated valid signals." severity Warning; END IF; END PROCESS; dut : DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror port map ( in_1_valid_stm, in_2_input_spectrum_stm, out_1_valid_x_dut, out_2_output_spectrum_dut, clk, areset ); sim : DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_stm port map ( in_1_valid_stm, in_2_input_spectrum_stm, out_1_valid_x_stm, out_2_output_spectrum_stm, clk, areset ); end normal;
<filename>Labs/05-counter/counter/counter.srcs/sources_1/new/m7_driver.vhd ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/10/2021 03:21:51 PM -- Design Name: -- Module Name: m7_driver - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity m7_driver is Generic ( g_MAX : natural := 100000 -- update each segment every 1ms ); Port ( CLK100MHZ : in std_logic; num_in : in std_logic_vector(32 - 1 downto 0); s_mask : in std_logic_vector(8 - 1 downto 0); reset : in std_logic; t_seg_o : out std_logic_vector(7 - 1 downto 0); AN : out std_logic_vector(8 - 1 downto 0) ); end m7_driver; architecture Behavioral of m7_driver is signal switch_segment : std_logic; signal local_disply_num : std_logic_vector(4-1 downto 0); signal local_cnt : natural; begin -------------------------------------------------------------------- -- segment switching signal clk_en_16b : entity work.clock_enable generic map( g_MAX => g_MAX ) port map( clk => CLK100MHZ, reset => reset, -- no reset needed ce_o => switch_segment ); hex2seg : entity work.hex_7seg port map( hex_i => local_disply_num, seg_o(6) => t_seg_o(6), seg_o(5) => t_seg_o(5), seg_o(4) => t_seg_o(4), seg_o(3) => t_seg_o(3), seg_o(2) => t_seg_o(2), seg_o(1) => t_seg_o(1), seg_o(0) => t_seg_o(0) ); segment_switcher : process(CLK100MHZ) begin if rising_edge(CLK100MHZ) then if (reset = '1') then local_cnt <= 0; elsif (switch_segment = '1') then AN(local_cnt-1) <= '1'; -- reset previous segment if (s_mask(local_cnt) = '1') then -- check mask AN(local_cnt) <= '0'; -- activate current segment end if; -- calculate segment numbers local_disply_num <= num_in((local_cnt4)+3 downto (local_cnt4)); -- if last segment go to beginning if (local_cnt < 8) then local_cnt <= local_cnt + 1; else local_cnt <= 0; end if; end if; end if; end process segment_switcher; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01:29:15 01/07/2018 -- Design Name: -- Module Name: top_fpga - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top_fpga is Port ( sys_clk : in STD_LOGIC; sys_rst_n : in STD_LOGIC; DAC_IN1,DAC_IN2,DAC_IN3 : in STD_LOGIC_VECTOR (35 downto 0); DAC_OUT13,DAC_OUT14,DAC_OUT15 : out STD_LOGIC_VECTOR (35 downto 0)); end top_fpga; architecture Behavioral of top_fpga is signal sys_rst : std_logic; COMPONENT MASH_HDL PORT( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic; In1 : IN std_logic_vector(35 DOWNTO 0); -- sfix36_En22 ce_out : OUT std_logic; Modulator_output : OUT std_logic_vector(35 DOWNTO 0) -- sfix36_En22 ); END COMPONENT; COMPONENT DSM_MOD8_HDL PORT ( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic; In1 : IN std_logic_vector(45 DOWNTO 0); -- sfix36_En32 ce_out : OUT std_logic; Out1 : OUT std_logic_vector(1 DOWNTO 0) -- sfix2 ); END COMPONENT; COMPONENT Eight_order_delta_sigma_modulator PORT ( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic; Baseband_signal : IN std_logic_vector(35 DOWNTO 0); -- sfix36_En32 ce_out : OUT std_logic; Modulator_output : OUT std_logic_vector(35 DOWNTO 0) -- sfix36_En32 ); END COMPONENT; begin sys_rst <= not sys_rst_n; U1 : Eight_order_delta_sigma_modulator PORT MAP( clk => sys_clk, reset => sys_rst, clk_enable => '1', Baseband_signal => DAC_IN1, ce_out => open, Modulator_output => DAC_OUT13 ); -- U2 : DSM_MOD8_LTE_HDL -- PORT MAP( -- clk => sys_clk, -- reset => sys_rst, -- clk_enable => '1', -- In1 => DAC_IN2, -- ce_out => open, -- Out1 => DAC_OUT14 -- ); -- -- U3 : MASH_HDL -- PORT MAP( -- clk => sys_clk, -- reset => sys_rst, -- clk_enable => '1', -- In1 => DAC_IN3, -- ce_out => open, -- Modulator_output => DAC_OUT15 -- ); end Behavioral;
<filename>lib/memory_tech_lib/tests/memory_tb.vhd<gh_stars>10-100 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.test_pkg.all; use work.memory_pack.all; use work.mem_test_pack.all; entity memory_tb is end memory_tb; architecture tb of memory_tb is signal select_mem : mem_type; signal clk : std_logic := '0'; signal rst : std_logic := '1'; constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; signal p0 : mem_port := MEM_PORT_NOP; signal p1 : mem_port := MEM_PORT_NOP; signal dr0 : data_array_t := (others => (others => '0')); signal dr1 : data_array_t := (others => (others => '0')); procedure tick(signal clk : inout std_logic) is begin wait for 10 ns; clk <= '1'; wait for 10 ns; clk <= '0'; end procedure; function to_bit(b : boolean) return std_logic is begin if b then return '1'; else return '0'; end if; end function; for mems : memories use configuration work.memories_inferred; begin mems: memories generic map ( FOR_SYNTHESIS => false) port map ( rst0 => rst, clk0 => clk, rst1 => rst, clk1 => clk, select_mem => select_mem, p0 => p0, p1 => p1, dr0 => dr0, dr1 => dr1); process begin test_plan(75, "memory_tb"); -- Memories do synchronous reads and writes at the rising clock edge. Setup -- read/write requests at the negative edge and check the results at the -- following negative edge. tick(clk); rst <= '0'; tick(clk); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; -- TODO: How to test ROM? Need to support initializnig it first test_comment("RAM_GEN_32x2048_1R"); select_mem <= ROM_GEN_32x2048_1R; tick(clk); --for m in one_port_rams'left to one_port_rams'right loop --select_mem <= one_port_rams(m); --end loop; test_comment("RAM_GEN_2x8x256_1RW"); select_mem <= RAM_GEN_2x8x256_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(3, x"0000FFFF", "01"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 1 byte write"); p0 <= writemem(3, x"00000000", "00"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 0 byte write"); p0 <= writemem(3, x"00000000", "10"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"000000FF", "read after 1 byte write"); p0 <= writemem(3, x"0000abcd", "11"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read after 2 byte write"); p0 <= MEM_PORT_NOP; test_comment("RAM_FIXED_2x8x256_1RW"); select_mem <= RAM_FIXED_2x8x256_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(3, x"0000FFFF", "01"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 1 byte write"); p0 <= writemem(3, x"00000000", "00"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 0 byte write"); p0 <= writemem(3, x"00000000", "10"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"000000FF", "read after 1 byte write"); p0 <= writemem(3, x"0000abcd", "11"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read after 2 byte write"); p0 <= MEM_PORT_NOP; test_comment("RAM_GEN_18x2048_1RW"); select_mem <= RAM_GEN_18x2048_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0003FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= MEM_PORT_NOP; test_comment("RAM_FIXED_18x2048_1RW"); select_mem <= RAM_FIXED_18x2048_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0003FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= MEM_PORT_NOP; test_comment("RAM_GEN_2x8x2048_2RW"); select_mem <= RAM_GEN_2x8x2048_2RW; p0 <= writemem(3, x"0000abcd"); p1 <= MEM_PORT_NOP; tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "p0 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= readmem(3); tick(clk); test_equal(dr1(select_mem), x"0000abcd", "p1 read back write to 3"); p0 <= readmem(3); p1 <= readmem(3); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "p0 & p1 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(5, x"00001256"); p1 <= writemem(6, x"00007834"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after simultaneous writes"); p0 <= writemem(5, x"0000FFFF", x"00000000"); p1 <= writemem(6, x"00000000", x"00000000"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after writes with we=0"); p0 <= writemem(5, x"0000FFFF", x"00000001"); p1 <= writemem(6, x"00000000", x"00000002"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "reads latched during partial writes"); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"00000034000012FF", "read after writes with we=10 and we=01"); test_comment("RAM_FIXED_2x8x2048_2RW"); select_mem <= RAM_FIXED_2x8x2048_2RW; p0 <= writemem(3, x"0000abcd"); p1 <= MEM_PORT_NOP; tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "p0 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= readmem(3); tick(clk); test_equal(dr1(select_mem), x"0000abcd", "p1 read back write to 3"); p0 <= readmem(3); p1 <= readmem(3); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "p0 & p1 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(5, x"00001256"); p1 <= writemem(6, x"00007834"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after simultaneous writes"); p0 <= writemem(5, x"0000FFFF", x"00000000"); p1 <= writemem(6, x"00000000", x"00000000"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after writes with we=0"); p0 <= writemem(5, x"0000FFFF", x"00000001"); p1 <= writemem(6, x"00000000", x"00000002"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "reads latched during partial writes"); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"00000034000012FF", "read after writes with we=10 and we=01"); test_comment("RAM_GEN_32x1x512_2RW"); select_mem <= RAM_GEN_32x1x512_2RW; p0 <= writemem(3, x"1234abcd"); p1 <= MEM_PORT_NOP; tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"1234abcd", "p0 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= readmem(3); tick(clk); test_equal(dr1(select_mem), x"1234abcd", "p1 read back write to 3"); p0 <= readmem(3); p1 <= readmem(3); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "p0 & p1 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"1234abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"FFFFFFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"1234abcd", "rereread back write to 3"); p0 <= writemem(5, x"12345678"); p1 <= writemem(6, x"abcdefcb"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"abcdefcb12345678", "read after simultaneous writes"); p0 <= writemem(5, x"0000FFFF", x"00000000"); p1 <= writemem(6, x"00000000", x"00000000"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"abcdefcb12345678", "read after writes with we=0"); p0 <= writemem(5, x"FFFF0000", x"11111111"); p1 <= writemem(6, x"00000000", x"12345678"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"abcdefcb12345678", "reads latched during partial writes"); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"a9c9a98313354668", "read after writes with mixed we"); wait; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.lib.all; -- Entity entity system is port ( clk : in std_logic; -- Declare Outputs environment_time_out : out signed(31 downto 0); membrane_v_out : out signed(31 downto 0); membrane_r_out : out signed(31 downto 0); membrane_t_out : out signed(31 downto 0); membrane_f_out : out signed(31 downto 0); membrane_dv_dt_out : out signed(31 downto 0); membrane_istimc_out : out signed(31 downto 0); fast_sodium_current_i_na_out : out signed(31 downto 0); fast_sodium_current_e_na_out : out signed(31 downto 0); fast_sodium_current_time_private_out : out signed(31 downto 0); fast_sodium_current_v_private_out : out signed(31 downto 0); fast_sodium_current_m_gate_m_out : out signed(31 downto 0); fast_sodium_current_h_gate_h_out : out signed(31 downto 0); fast_sodium_current_j_gate_j_out : out signed(31 downto 0); l_type_ca_channel_i_ca_l_out : out signed(31 downto 0); l_type_ca_channel_i_caca_out : out signed(31 downto 0); l_type_ca_channel_i_cak_out : out signed(31 downto 0); l_type_ca_channel_i_cana_out : out signed(31 downto 0); l_type_ca_channel_gamma_nai_out : out signed(31 downto 0); l_type_ca_channel_gamma_nao_out : out signed(31 downto 0); l_type_ca_channel_gamma_ki_out : out signed(31 downto 0); l_type_ca_channel_gamma_ko_out : out signed(31 downto 0); l_type_ca_channel_time_private_out : out signed(31 downto 0); l_type_ca_channel_v_private_out : out signed(31 downto 0); l_type_ca_channel_cai_private_out : out signed(31 downto 0); l_type_ca_channel_d_gate_d_out : out signed(31 downto 0); l_type_ca_channel_f_gate_f_out : out signed(31 downto 0); l_type_ca_channel_f_ca_gate_f_ca_out : out signed(31 downto 0); time_dependent_potassium_current_i_k_out : out signed(31 downto 0); time_dependent_potassium_current_time_private_out : out signed(31 downto 0); time_dependent_potassium_current_v_private_out : out signed(31 downto 0); time_dependent_potassium_current_x_gate_x_out : out signed(31 downto 0); time_dependent_potassium_current_xi_gate_xi_out : out signed(31 downto 0); time_independent_potassium_current_i_k1_out : out signed(31 downto 0); time_independent_potassium_current_e_k1_out : out signed(31 downto 0); time_independent_potassium_current_time_private_out : out signed(31 downto 0); time_independent_potassium_current_v_private_out : out signed(31 downto 0); time_independent_potassium_current_k1_gate_k1_infinity_out : out signed(31 downto 0); plateau_potassium_current_i_kp_out : out signed(31 downto 0); sarcolemmal_calcium_pump_i_p_ca_out : out signed(31 downto 0); sodium_background_current_i_na_b_out : out signed(31 downto 0); calcium_background_current_i_ca_b_out : out signed(31 downto 0); sodium_potassium_pump_i_nak_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_ca_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_na_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_k_out : out signed(31 downto 0); na_ca_exchanger_i_naca_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_rel_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_up_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_leak_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_tr_out : out signed(31 downto 0); ionic_concentrations_nai_out : out signed(31 downto 0); ionic_concentrations_nao_out : out signed(31 downto 0); ionic_concentrations_cai_out : out signed(31 downto 0); ionic_concentrations_cao_out : out signed(31 downto 0); ionic_concentrations_ki_out : out signed(31 downto 0); ionic_concentrations_ko_out : out signed(31 downto 0); ionic_concentrations_ca_jsr_out : out signed(31 downto 0); ionic_concentrations_ca_nsr_out : out signed(31 downto 0) ); end; -- Architecture architecture behavior of system is -- Declare all internal signals signal luo_rudy_1994_environment_time : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_v : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_r : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_t : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_f : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_dv_dt : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_istimc : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_i_na : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_e_na : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_m_gate_m : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_h_gate_h : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_j_gate_j : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_ca_l : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_caca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_cak : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_cana : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_nai : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_nao : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_ki : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_ko : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_cai_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_d_gate_d : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_f_gate_f : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_f_ca_gate_f_ca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_i_k : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_x_gate_x : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_xi_gate_xi : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_i_k1 : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_e_k1 : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_k1_gate_k1_infinity : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_plateau_potassium_current_i_kp : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_sarcolemmal_calcium_pump_i_p_ca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_sodium_background_current_i_na_b : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_background_current_i_ca_b : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_sodium_potassium_pump_i_nak : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_non_specific_calcium_activated_current_i_ns_ca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_non_specific_calcium_activated_current_i_ns_na : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_non_specific_calcium_activated_current_i_ns_k : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_na_ca_exchanger_i_naca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_rel : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_up : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_leak : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_tr : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_nai : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_nao : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_cai : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_cao : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ki : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ko : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ca_jsr : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ca_nsr : signed(31 downto 0) := CREATE_FP(0.0); -- Declare base component component LuoRudy1994 is port( clk : in std_logic; environment_time_out : out signed(31 downto 0); membrane_v_out : out signed(31 downto 0); membrane_r_out : out signed(31 downto 0); membrane_t_out : out signed(31 downto 0); membrane_f_out : out signed(31 downto 0); membrane_dv_dt_out : out signed(31 downto 0); membrane_istimc_out : out signed(31 downto 0); fast_sodium_current_i_na_out : out signed(31 downto 0); fast_sodium_current_e_na_out : out signed(31 downto 0); fast_sodium_current_time_private_out : out signed(31 downto 0); fast_sodium_current_v_private_out : out signed(31 downto 0); fast_sodium_current_m_gate_m_out : out signed(31 downto 0); fast_sodium_current_h_gate_h_out : out signed(31 downto 0); fast_sodium_current_j_gate_j_out : out signed(31 downto 0); l_type_ca_channel_i_ca_l_out : out signed(31 downto 0); l_type_ca_channel_i_caca_out : out signed(31 downto 0); l_type_ca_channel_i_cak_out : out signed(31 downto 0); l_type_ca_channel_i_cana_out : out signed(31 downto 0); l_type_ca_channel_gamma_nai_out : out signed(31 downto 0); l_type_ca_channel_gamma_nao_out : out signed(31 downto 0); l_type_ca_channel_gamma_ki_out : out signed(31 downto 0); l_type_ca_channel_gamma_ko_out : out signed(31 downto 0); l_type_ca_channel_time_private_out : out signed(31 downto 0); l_type_ca_channel_v_private_out : out signed(31 downto 0); l_type_ca_channel_cai_private_out : out signed(31 downto 0); l_type_ca_channel_d_gate_d_out : out signed(31 downto 0); l_type_ca_channel_f_gate_f_out : out signed(31 downto 0); l_type_ca_channel_f_ca_gate_f_ca_out : out signed(31 downto 0); time_dependent_potassium_current_i_k_out : out signed(31 downto 0); time_dependent_potassium_current_time_private_out : out signed(31 downto 0); time_dependent_potassium_current_v_private_out : out signed(31 downto 0); time_dependent_potassium_current_x_gate_x_out : out signed(31 downto 0); time_dependent_potassium_current_xi_gate_xi_out : out signed(31 downto 0); time_independent_potassium_current_i_k1_out : out signed(31 downto 0); time_independent_potassium_current_e_k1_out : out signed(31 downto 0); time_independent_potassium_current_time_private_out : out signed(31 downto 0); time_independent_potassium_current_v_private_out : out signed(31 downto 0); time_independent_potassium_current_k1_gate_k1_infinity_out : out signed(31 downto 0); plateau_potassium_current_i_kp_out : out signed(31 downto 0); sarcolemmal_calcium_pump_i_p_ca_out : out signed(31 downto 0); sodium_background_current_i_na_b_out : out signed(31 downto 0); calcium_background_current_i_ca_b_out : out signed(31 downto 0); sodium_potassium_pump_i_nak_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_ca_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_na_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_k_out : out signed(31 downto 0); na_ca_exchanger_i_naca_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_rel_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_up_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_leak_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_tr_out : out signed(31 downto 0); ionic_concentrations_nai_out : out signed(31 downto 0); ionic_concentrations_nao_out : out signed(31 downto 0); ionic_concentrations_cai_out : out signed(31 downto 0); ionic_concentrations_cao_out : out signed(31 downto 0); ionic_concentrations_ki_out : out signed(31 downto 0); ionic_concentrations_ko_out : out signed(31 downto 0); ionic_concentrations_ca_jsr_out : out signed(31 downto 0); ionic_concentrations_ca_nsr_out : out signed(31 downto 0) ); end component LuoRudy1994; begin -- Create base instance luo_rudy_1994_inst : component LuoRudy1994 port map( clk => clk, environment_time_out => luo_rudy_1994_environment_time, membrane_v_out => luo_rudy_1994_membrane_v, membrane_r_out => luo_rudy_1994_membrane_r, membrane_t_out => luo_rudy_1994_membrane_t, membrane_f_out => luo_rudy_1994_membrane_f, membrane_dv_dt_out => luo_rudy_1994_membrane_dv_dt, membrane_istimc_out => luo_rudy_1994_membrane_istimc, fast_sodium_current_i_na_out => luo_rudy_1994_fast_sodium_current_i_na, fast_sodium_current_e_na_out => luo_rudy_1994_fast_sodium_current_e_na, fast_sodium_current_time_private_out => luo_rudy_1994_fast_sodium_current_time_private, fast_sodium_current_v_private_out => luo_rudy_1994_fast_sodium_current_v_private, fast_sodium_current_m_gate_m_out => luo_rudy_1994_fast_sodium_current_m_gate_m, fast_sodium_current_h_gate_h_out => luo_rudy_1994_fast_sodium_current_h_gate_h, fast_sodium_current_j_gate_j_out => luo_rudy_1994_fast_sodium_current_j_gate_j, l_type_ca_channel_i_ca_l_out => luo_rudy_1994_l_type_ca_channel_i_ca_l, l_type_ca_channel_i_caca_out => luo_rudy_1994_l_type_ca_channel_i_caca, l_type_ca_channel_i_cak_out => luo_rudy_1994_l_type_ca_channel_i_cak, l_type_ca_channel_i_cana_out => luo_rudy_1994_l_type_ca_channel_i_cana, l_type_ca_channel_gamma_nai_out => luo_rudy_1994_l_type_ca_channel_gamma_nai, l_type_ca_channel_gamma_nao_out => luo_rudy_1994_l_type_ca_channel_gamma_nao, l_type_ca_channel_gamma_ki_out => luo_rudy_1994_l_type_ca_channel_gamma_ki, l_type_ca_channel_gamma_ko_out => luo_rudy_1994_l_type_ca_channel_gamma_ko, l_type_ca_channel_time_private_out => luo_rudy_1994_l_type_ca_channel_time_private, l_type_ca_channel_v_private_out => luo_rudy_1994_l_type_ca_channel_v_private, l_type_ca_channel_cai_private_out => luo_rudy_1994_l_type_ca_channel_cai_private, l_type_ca_channel_d_gate_d_out => luo_rudy_1994_l_type_ca_channel_d_gate_d, l_type_ca_channel_f_gate_f_out => luo_rudy_1994_l_type_ca_channel_f_gate_f, l_type_ca_channel_f_ca_gate_f_ca_out => luo_rudy_1994_l_type_ca_channel_f_ca_gate_f_ca, time_dependent_potassium_current_i_k_out => luo_rudy_1994_time_dependent_potassium_current_i_k, time_dependent_potassium_current_time_private_out => luo_rudy_1994_time_dependent_potassium_current_time_private, time_dependent_potassium_current_v_private_out => luo_rudy_1994_time_dependent_potassium_current_v_private, time_dependent_potassium_current_x_gate_x_out => luo_rudy_1994_time_dependent_potassium_current_x_gate_x, time_dependent_potassium_current_xi_gate_xi_out => luo_rudy_1994_time_dependent_potassium_current_xi_gate_xi, time_independent_potassium_current_i_k1_out => luo_rudy_1994_time_independent_potassium_current_i_k1, time_independent_potassium_current_e_k1_out => luo_rudy_1994_time_independent_potassium_current_e_k1, time_independent_potassium_current_time_private_out => luo_rudy_1994_time_independent_potassium_current_time_private, time_independent_potassium_current_v_private_out => luo_rudy_1994_time_independent_potassium_current_v_private, time_independent_potassium_current_k1_gate_k1_infinity_out => luo_rudy_1994_time_independent_potassium_current_k1_gate_k1_infinity, plateau_potassium_current_i_kp_out => luo_rudy_1994_plateau_potassium_current_i_kp, sarcolemmal_calcium_pump_i_p_ca_out => luo_rudy_1994_sarcolemmal_calcium_pump_i_p_ca, sodium_background_current_i_na_b_out => luo_rudy_1994_sodium_background_current_i_na_b, calcium_background_current_i_ca_b_out => luo_rudy_1994_calcium_background_current_i_ca_b, sodium_potassium_pump_i_nak_out => luo_rudy_1994_sodium_potassium_pump_i_nak, non_specific_calcium_activated_current_i_ns_ca_out => luo_rudy_1994_non_specific_calcium_activated_current_i_ns_ca, non_specific_calcium_activated_current_i_ns_na_out => luo_rudy_1994_non_specific_calcium_activated_current_i_ns_na, non_specific_calcium_activated_current_i_ns_k_out => luo_rudy_1994_non_specific_calcium_activated_current_i_ns_k, na_ca_exchanger_i_naca_out => luo_rudy_1994_na_ca_exchanger_i_naca, calcium_fluxes_in_the_sr_i_rel_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_rel, calcium_fluxes_in_the_sr_i_up_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_up, calcium_fluxes_in_the_sr_i_leak_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_leak, calcium_fluxes_in_the_sr_i_tr_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_tr, ionic_concentrations_nai_out => luo_rudy_1994_ionic_concentrations_nai, ionic_concentrations_nao_out => luo_rudy_1994_ionic_concentrations_nao, ionic_concentrations_cai_out => luo_rudy_1994_ionic_concentrations_cai, ionic_concentrations_cao_out => luo_rudy_1994_ionic_concentrations_cao, ionic_concentrations_ki_out => luo_rudy_1994_ionic_concentrations_ki, ionic_concentrations_ko_out => luo_rudy_1994_ionic_concentrations_ko, ionic_concentrations_ca_jsr_out => luo_rudy_1994_ionic_concentrations_ca_jsr, ionic_concentrations_ca_nsr_out => luo_rudy_1994_ionic_concentrations_ca_nsr ); -- Perform Mapping environment_time_out <= luo_rudy_1994_environment_time; membrane_v_out <= luo_rudy_1994_membrane_v; membrane_r_out <= luo_rudy_1994_membrane_r; membrane_t_out <= luo_rudy_1994_membrane_t; membrane_f_out <= luo_rudy_1994_membrane_f; membrane_dv_dt_out <= luo_rudy_1994_membrane_dv_dt; membrane_istimc_out <= luo_rudy_1994_membrane_istimc; fast_sodium_current_i_na_out <= luo_rudy_1994_fast_sodium_current_i_na; fast_sodium_current_e_na_out <= luo_rudy_1994_fast_sodium_current_e_na; fast_sodium_current_time_private_out <= luo_rudy_1994_fast_sodium_current_time_private; fast_sodium_current_v_private_out <= luo_rudy_1994_fast_sodium_current_v_private; fast_sodium_current_m_gate_m_out <= luo_rudy_1994_fast_sodium_current_m_gate_m; fast_sodium_current_h_gate_h_out <= luo_rudy_1994_fast_sodium_current_h_gate_h; fast_sodium_current_j_gate_j_out <= luo_rudy_1994_fast_sodium_current_j_gate_j; l_type_ca_channel_i_ca_l_out <= luo_rudy_1994_l_type_ca_channel_i_ca_l; l_type_ca_channel_i_caca_out <= luo_rudy_1994_l_type_ca_channel_i_caca; l_type_ca_channel_i_cak_out <= luo_rudy_1994_l_type_ca_channel_i_cak; l_type_ca_channel_i_cana_out <= luo_rudy_1994_l_type_ca_channel_i_cana; l_type_ca_channel_gamma_nai_out <= luo_rudy_1994_l_type_ca_channel_gamma_nai; l_type_ca_channel_gamma_nao_out <= luo_rudy_1994_l_type_ca_channel_gamma_nao; l_type_ca_channel_gamma_ki_out <= luo_rudy_1994_l_type_ca_channel_gamma_ki; l_type_ca_channel_gamma_ko_out <= luo_rudy_1994_l_type_ca_channel_gamma_ko; l_type_ca_channel_time_private_out <= luo_rudy_1994_l_type_ca_channel_time_private; l_type_ca_channel_v_private_out <= luo_rudy_1994_l_type_ca_channel_v_private; l_type_ca_channel_cai_private_out <= luo_rudy_1994_l_type_ca_channel_cai_private; l_type_ca_channel_d_gate_d_out <= luo_rudy_1994_l_type_ca_channel_d_gate_d; l_type_ca_channel_f_gate_f_out <= luo_rudy_1994_l_type_ca_channel_f_gate_f; l_type_ca_channel_f_ca_gate_f_ca_out <= luo_rudy_1994_l_type_ca_channel_f_ca_gate_f_ca; time_dependent_potassium_current_i_k_out <= luo_rudy_1994_time_dependent_potassium_current_i_k; time_dependent_potassium_current_time_private_out <= luo_rudy_1994_time_dependent_potassium_current_time_private; time_dependent_potassium_current_v_private_out <= luo_rudy_1994_time_dependent_potassium_current_v_private; time_dependent_potassium_current_x_gate_x_out <= luo_rudy_1994_time_dependent_potassium_current_x_gate_x; time_dependent_potassium_current_xi_gate_xi_out <= luo_rudy_1994_time_dependent_potassium_current_xi_gate_xi; time_independent_potassium_current_i_k1_out <= luo_rudy_1994_time_independent_potassium_current_i_k1; time_independent_potassium_current_e_k1_out <= luo_rudy_1994_time_independent_potassium_current_e_k1; time_independent_potassium_current_time_private_out <= luo_rudy_1994_time_independent_potassium_current_time_private; time_independent_potassium_current_v_private_out <= luo_rudy_1994_time_independent_potassium_current_v_private; time_independent_potassium_current_k1_gate_k1_infinity_out <= luo_rudy_1994_time_independent_potassium_current_k1_gate_k1_infinity; plateau_potassium_current_i_kp_out <= luo_rudy_1994_plateau_potassium_current_i_kp; sarcolemmal_calcium_pump_i_p_ca_out <= luo_rudy_1994_sarcolemmal_calcium_pump_i_p_ca; sodium_background_current_i_na_b_out <= luo_rudy_1994_sodium_background_current_i_na_b; calcium_background_current_i_ca_b_out <= luo_rudy_1994_calcium_background_current_i_ca_b; sodium_potassium_pump_i_nak_out <= luo_rudy_1994_sodium_potassium_pump_i_nak; non_specific_calcium_activated_current_i_ns_ca_out <= luo_rudy_1994_non_specific_calcium_activated_current_i_ns_ca; non_specific_calcium_activated_current_i_ns_na_out <= luo_rudy_1994_non_specific_calcium_activated_current_i_ns_na; non_specific_calcium_activated_current_i_ns_k_out <= luo_rudy_1994_non_specific_calcium_activated_current_i_ns_k; na_ca_exchanger_i_naca_out <= luo_rudy_1994_na_ca_exchanger_i_naca; calcium_fluxes_in_the_sr_i_rel_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_rel; calcium_fluxes_in_the_sr_i_up_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_up; calcium_fluxes_in_the_sr_i_leak_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_leak; calcium_fluxes_in_the_sr_i_tr_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_tr; ionic_concentrations_nai_out <= luo_rudy_1994_ionic_concentrations_nai; ionic_concentrations_nao_out <= luo_rudy_1994_ionic_concentrations_nao; ionic_concentrations_cai_out <= luo_rudy_1994_ionic_concentrations_cai; ionic_concentrations_cao_out <= luo_rudy_1994_ionic_concentrations_cao; ionic_concentrations_ki_out <= luo_rudy_1994_ionic_concentrations_ki; ionic_concentrations_ko_out <= luo_rudy_1994_ionic_concentrations_ko; ionic_concentrations_ca_jsr_out <= luo_rudy_1994_ionic_concentrations_ca_jsr; ionic_concentrations_ca_nsr_out <= luo_rudy_1994_ionic_concentrations_ca_nsr; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library common; use common.all; library altera_mf; use altera_mf.all; -- writes take two cycles -- read data appears after 4 ticks -- 1 to process the start request -- 1 to get it from the SRAM -- 2 in the syncronizer entity sram is port (i_clk: in std_ulogic; -- max clk 100MHz i_reset: in std_ulogic; -- inputs i_addr: in unsigned(17 downto 0); i_wdata: in std_ulogic_vector(15 downto 0); i_rnw: in std_ulogic; i_start: in std_ulogic; -- outputs o_rdata: out std_ulogic_vector(15 downto 0); -- status o_busy: out std_ulogic; o_rdata_valid: out std_ulogic; -- bus ports io_data: inout std_ulogic_vector(15 downto 0); o_addr: out std_ulogic_vector(17 downto 0); o_nCE: out std_ulogic; o_nOE: out std_ulogic; o_nWE: out std_ulogic; o_nLB: out std_ulogic; o_nUB: out std_ulogic); end entity sram; architecture synth of sram is component delay is generic (DELAY: natural; WIDTH: natural); port (clk: in std_ulogic; rst: in std_ulogic; input: in std_ulogic_vector((WIDTH - 1) downto 0); output: out std_ulogic_vector((WIDTH - 1) downto 0)); end component delay; component altera_std_synchronizer_bundle is generic (DEPTH : integer := 3; -- must be >= 2 WIDTH : integer := 1); port (clk : in std_logic; reset_n : in std_logic; din : in std_logic_vector(width-1 downto 0); dout : out std_logic_vector(width-1 downto 0)); end component altera_std_synchronizer_bundle; signal busy: std_ulogic; begin -- syncronize the input data rdata_sync: altera_std_synchronizer_bundle generic map (DEPTH => 2, WIDTH => 16) port map (clk => i_clk, reset_n => not i_reset, din => std_logic_vector(io_data), std_ulogic_vector(dout) => o_rdata); process (i_clk, i_reset) begin if (i_reset = '1') then o_nCE <= '1'; o_nOE <= '1'; o_nWE <= '1'; o_nLB <= '1'; o_nUB <= '1'; io_data <= (others => 'Z'); busy <= '0'; elsif (rising_edge(i_clk)) then if (busy = '0') then -- not doing anything -- wait for read or write request if (i_start) then -- we have a request o_addr <= std_ulogic_vector(i_addr); if (i_rnw = '1') then -- read io_data <= (others => 'Z'); o_nOE <= '0'; o_nWE <= '1'; else -- write io_data <= i_wdata; o_nOE <= '1'; o_nWE <= '0'; -- we take more than one cycle for writes -- so have to say we're busy busy <= '1'; end if; o_nCE <= '0'; o_nUB <= '0'; o_nLB <= '0'; else -- not busy and not starting anything new -- so disable everything o_nCE <= '1'; o_nOE <= '1'; o_nWE <= '1'; o_nLB <= '1'; o_nUB <= '1'; io_data <= (others => 'Z'); end if; else -- busy -> writing -- finish off the write by releasing everything o_nCE <= '1'; o_nOE <= '1'; o_nWE <= '1'; o_nLB <= '1'; o_nUB <= '1'; io_data <= (others => 'Z'); busy <= '0'; end if; end if; end process; o_busy <= busy; -- when both i_start and i_rnw are asserted -- then the read data becomes available 4 ticks later dly: delay generic map (DELAY => 4, WIDTH => 1) port map (clk => i_clk, rst => i_reset, input(0) => i_start and i_rnw, output(0) => o_rdata_valid); end architecture synth;
<reponame>amnesia13/prince-vhdl library ieee; use ieee.std_logic_1164.all; -- The cipher without the key whitening layer entity prince_core is port(data_in: in std_logic_vector(63 downto 0); key: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end prince_core; architecture structural of prince_core is type round_constants is array(0 to 11) of std_logic_vector(63 downto 0); type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0); -- Round constants for each round constant rcs: round_constants := (x"0000000000000000", x"13198A2E03707344", x"A4093822299F31D0", x"082EFA98EC4E6C89", x"452821E638D01377", x"BE5466CF34E90C6C", x"7EF84F78FD955CB1", x"85840851F1AC43AA", x"C882D32F25323C54", x"64A51195E0E3610D", x"D3B5A399CA0C2399", x"C0AC29B7C97C50DD"); -- Signals for transporting the data between rounds signal ims: intermediate_signals; signal middle1, middle2: std_logic_vector(63 downto 0); -- Required component declarations component sbox port(data_in: in std_logic_vector(3 downto 0); data_out: out std_logic_vector(3 downto 0) ); end component; component sbox_inv port(data_in: in std_logic_vector(3 downto 0); data_out: out std_logic_vector(3 downto 0) ); end component; component linear_m port(data_in: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end component; component linear_m_inv port(data_in: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end component; component linear_mprime port(data_in: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end component; begin -- Round 0 ims(0) <= data_in xor key xor rcs(0); -- Round 1 to 5 FIRST_HALF: for i in 1 to 5 generate signal sb_out, m_out: std_logic_vector(63 downto 0); begin SB_FH: for j in 0 to 15 generate SX_FH: sbox port map( data_in => ims(i - 1)(63 - 4j downto 63 - 4j - 3), data_out => sb_out(63 - 4j downto 63 - 4j - 3) ); end generate; LIN_M: linear_m port map( data_in => sb_out, data_out => m_out ); ims(i) <= m_out xor rcs(i) xor key; end generate; -- Middle layer SB_MID: for i in 0 to 15 generate SX_M1: sbox port map( data_in => ims(5)(63 - 4i downto 63 - 4i - 3), data_out => middle1(63 - 4i downto 63 - 4i - 3) ); end generate; MP_MID: linear_mprime port map( data_in => middle1, data_out => middle2 ); SB_MID_INV: for i in 0 to 15 generate SX_M2: sbox_inv port map( data_in => middle2(63 - 4i downto 63 - 4i - 3), data_out => ims(6)(63 - 4i downto 63 - 4i - 3) ); end generate; -- Round 6 to 10 SECOND_HALF: for i in 6 to 10 generate signal m_in, sb_in: std_logic_vector(63 downto 0); begin m_in <= ims(i) xor key xor rcs(i); LIN_M_INV: linear_m_inv port map( data_in => m_in, data_out => sb_in ); SB_SH: for j in 0 to 15 generate SX_SH: sbox_inv port map( data_in => sb_in(63 - 4j downto 63 - 4j - 3), data_out => ims(i + 1)(63 - 4j downto 63 - 4j - 3) ); end generate; end generate; -- Round 11 data_out <= ims(11) xor rcs(11) xor key; end architecture;
------------------------------------------------------------------------------- -- Title : Accelerator Adapter -- Project : ------------------------------------------------------------------------------- -- File : xd_sync_module.vhd -- Author : rmg/jn -- Company : Xilinx, Inc. -- Created : 2012-09-05 -- Last update: 2013-01-22 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- (c) Copyright 2012 Xilinx, Inc. All rights reserved. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2012-09-05 1.0 rmg/jn Created -- 2013-07-12 2.0 pankajk Added new ports iscalar_rqt_enable & -- iscalar_rqt_enable to qualify with -- iscalar_start & oscalar_start ------------------------------------------------------------------------------- -- ************************************************************************** -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************** ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library axis_accelerator_adapter_v2_1_6; use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all; use axis_accelerator_adapter_v2_1_6.async_fifo_dist_wt; use axis_accelerator_adapter_v2_1_6.sync_ap_status; use axis_accelerator_adapter_v2_1_6.cdc_sync; entity xd_sync_module is generic ( -- System generics: C_FAMILY : string; -- Xilinx FPGA family C_MAX_N_IARGS : integer; C_MAX_N_OARGS : integer; C_N_INPUT_ARGS : integer; C_N_OUTPUT_ARGS : integer; C_PRMRY_IS_ACLK_ASYNC : integer; C_MTBF_STAGES : integer; C_MAX_N_ISCALARS : integer; C_N_INPUT_SCALARS : integer; C_MAX_N_OSCALARS : integer; C_N_INOUT_SCALARS : integer; C_MAX_N_IOSCALARS : integer; C_N_OUTPUT_SCALARS : integer; C_NONE : integer := 2); port ( -- SLAVE AXI LITE: S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; -- Host command input port host_cmd_data : in std_logic_vector(31 downto 0); host_cmd_we : in std_logic; host_cmd_rdy : out std_logic; host_complete_re : in std_logic; host_cmd_error : out std_logic; --- iarg_rqt_enable : in std_logic_vector(C_MAX_N_IARGS-1 downto 0); oarg_rqt_enable : in std_logic_vector(C_MAX_N_OARGS-1 downto 0); --- status_ap_start : out std_logic; status_ap_done : out std_logic; status_ap_idle : out std_logic; status_ap_ready : out std_logic; status_ap_start_clr : in std_logic; status_ap_done_clr : in std_logic; status_ap_idle_clr : in std_logic; status_ap_ready_clr : in std_logic; --- status_iarg_rqt : out std_logic_vector(C_MAX_N_IARGS-1 downto 0); status_iarg_ack : out std_logic_vector(C_MAX_N_IARGS-1 downto 0); status_oarg_rqt : out std_logic_vector(C_MAX_N_OARGS-1 downto 0); status_oarg_ack : out std_logic_vector(C_MAX_N_OARGS-1 downto 0); --- ap_clk : in std_logic; soft_rst : in std_logic; ap_rst : in std_logic; --- Control and status signals for multibuffers mb_iarg_rdy : in std_logic_vector(C_MAX_N_IARGS-1 downto 0); mb_iarg_done : out std_logic_vector(C_MAX_N_IARGS-1 downto 0); mb_oarg_rdy : in std_logic_vector(C_MAX_N_OARGS-1 downto 0); mb_oarg_done : out std_logic_vector(C_MAX_N_OARGS-1 downto 0); -- AP control handshaking ap_start : out std_logic; ap_ready : in std_logic; ap_done : in std_logic; ap_continue : out std_logic; ap_idle : in std_logic; ap_start_one_shot : out std_logic; --- iscalar_rqt_enable : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); oscalar_rqt_enable : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0); --- ap_iscalar_rdy : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); ap_iscalar_done : out std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); --- ap_oscalar_vld : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0); ap_oscalar_rdy : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0)); end entity; architecture rtl of xd_sync_module is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes"; type state_type is ( idle, apply_input_mask, wait_start, wait_done, stop); signal state : state_type; signal ap_start_i : std_logic; --------------------------------------- constant OPCODE_WIDTH : integer := 4; constant ARG_MASK_LSB : integer := 0; constant ARG_MASK_MSB : integer := 7; constant SCALAR_MASK_LSB : integer := 8; constant SCALAR_MASK_MSB : integer := 15; constant OPCODE_LSB : integer := 16; constant OPCODE_MSB : integer := OPCODE_LSB+OPCODE_WIDTH-1; constant ISCALAR_MASK_LSB: integer := OPCODE_MSB+1; constant ISCALAR_MASK_MSB: integer := ISCALAR_MASK_LSB+7; -- input commands constant UPDATE_INPUT : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0000"; constant UPDATE_OUTPUT : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0001"; constant EXECUTE_STEP : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0010"; constant EXECUTE_RESUME : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0100"; constant EXECUTE_STOP : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0101"; -- constant EXECUTE : std_logic_vector(1 downto 0) := "10"; constant IARG_UM_LSB : integer := 0; constant OARG_UM_LSB : integer := 8; constant ISCALAR_UM_LSB : integer := 16; constant OSCALAR_UM_LSB : integer := 24; -- pragma translate_off type dbg_opcode_type is ( op_update_input, op_update_output, op_exec_step, op_exec_resume, op_exec_stop, op_invalid); signal dbg_opcode : dbg_opcode_type; -- pragma translate_on signal command_full : std_logic; signal command : std_logic_vector(31 downto 0); signal command_vld : std_logic; signal command_rdy : std_logic; -- signal arg_mask : std_logic_vector(7 downto 0); signal scalar_mask : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); signal opcode : std_logic_vector(OPCODE_WIDTH-1 downto 0); -- signal input_mask_we : std_logic; signal input_mask_clr : std_logic; signal output_mask_we : std_logic; signal output_mask_clr : std_logic; -- signal iarg_mask : std_logic_vector(C_MAX_N_IARGS-1 downto 0); signal oarg_mask : std_logic_vector(C_MAX_N_OARGS-1 downto 0); signal iscalar_mask : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); signal oscalar_mask : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0); -- signal iarg_start : std_logic; signal iarg_start_sync : std_logic; signal oarg_start : std_logic; signal oarg_start_sync : std_logic; signal iscalar_start : std_logic; signal iscalar_start_sync: std_logic; signal oscalar_start : std_logic; signal oscalar_start_sync : std_logic; signal global_start : std_logic; -- signal mb_iarg_done_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0); signal mb_oarg_done_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0); -- -- Core ap_start delayed version. signal core_ap_start : std_logic; signal set_ap_start : std_logic; signal set_ap_start_r : std_logic; signal clr_ap_start : std_logic; signal run_continous : std_logic; signal ap_cmd_error : std_logic; signal host_cmd_error_i : std_logic; signal axi_rst : std_logic; --- Syncrhonizer signals signal iarg_rqt_enable_sync : std_logic_vector(C_MAX_N_IARGS-1 downto 0); signal oarg_rqt_enable_sync : std_logic_vector(C_MAX_N_OARGS-1 downto 0); signal ap_start_i_sync : std_logic; signal ap_done_sync : std_logic; signal ap_idle_sync : std_logic; signal ap_ready_sync : std_logic; signal ap_cmd_error_sync : std_logic; signal ap_rstn : std_logic; signal ap_rst_vec : std_logic_vector(0 downto 0); signal ap_rst_axi_sync : std_logic; signal ap_rst_sync : std_logic_vector(0 downto 0); signal axin_rst : std_logic; constant C_EXTRA_SYNCS : integer := 1; ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF axi_rst : SIGNAL IS "true"; begin -- Active low ap_rst ap_rstn <= not ap_rst; ---------------------- --- Reset Synchronizer ---------------------- -- EN_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate -- begin -- -- -- XD_IARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync -- generic map ( -- C_CDC_TYPE => 1, -- C_RESET_STATE => 0, -- C_SINGLE_BIT => 0, -- C_FLOP_INPUT => 1, -- C_VECTOR_WIDTH => C_MAX_N_IARGS, -- C_MTBF_STAGES => C_MTBF_STAGES -- ) -- port map ( -- prmry_aclk => S_AXI_ACLK, -- prmry_resetn => S_AXI_ARESETN, -- prmry_in => '0', -- prmry_vect_in => iarg_rqt_enable, -- -- scndry_aclk => ap_clk, -- scndry_resetn => ap_rstn, -- scndry_out => open, -- scndry_vect_out => iarg_rqt_enable_sync -- ); -- -- -- XD_OARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync -- generic map ( -- C_CDC_TYPE => 1, -- C_RESET_STATE => 0, -- C_SINGLE_BIT => 0, -- C_FLOP_INPUT => 0, -- C_VECTOR_WIDTH => C_MAX_N_OARGS, -- C_MTBF_STAGES => C_MTBF_STAGES -- ) -- port map ( -- prmry_aclk => S_AXI_ACLK, -- prmry_resetn => S_AXI_ARESETN, -- prmry_in => '0', -- prmry_vect_in => oarg_rqt_enable, -- -- scndry_aclk => ap_clk, -- scndry_resetn => ap_rstn, -- scndry_out => open, -- scndry_vect_out => oarg_rqt_enable_sync -- ); -- -- end generate EN_SYNC_GEN; -- -- NO_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate -- begin iarg_rqt_enable_sync <= iarg_rqt_enable; oarg_rqt_enable_sync <= oarg_rqt_enable; -- end generate NO_SYNC_GEN; ---------------------- --- Reset Synchronizer ---------------------- EN_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate begin AP_START_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_start_i, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_start_i_sync, scndry_vect_out => open ); AP_DONE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_done, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_done_sync, scndry_vect_out => open ); AP_IDLE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_idle, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_idle_sync, scndry_vect_out => open ); AP_READY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_ready, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_ready_sync, scndry_vect_out => open ); AP_CMDERR_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_cmd_error, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_cmd_error_sync, scndry_vect_out => open ); end generate EN_APCLK_LITE_SYNC_GEN; NO_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate begin -- -- ap_start_i_sync <= ap_start_i; -- ap_done_sync <= ap_done; -- ap_idle_sync <= ap_idle; -- ap_ready_sync <= ap_ready; -- ap_cmd_error_sync <= ap_cmd_error; -- AP_START_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_start_i, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_start_i_sync, scndry_vect_out => open ); AP_DONE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_done, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_done_sync, scndry_vect_out => open ); AP_IDLE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_idle, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_idle_sync, scndry_vect_out => open ); AP_READY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_ready, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_ready_sync, scndry_vect_out => open ); AP_CMDERR_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_cmd_error, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_cmd_error_sync, scndry_vect_out => open ); end generate NO_APCLK_LITE_SYNC_GEN; ---------------------- --- Reset Synchronizer ---------------------- mb_iarg_done <= mb_iarg_done_i; mb_oarg_done <= mb_oarg_done_i; axin_rst <= not(S_AXI_ARESETN); -- axi_rst <= not(S_AXI_ARESETN) or ap_rst; -- ap_rst_vec(0) <= ap_rst; -- -- rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff -- GENERIC MAP ( -- C_HAS_RST => 1, -- C_WIDTH => 1 -- ) -- PORT MAP ( -- RST => S_AXI_ARESETN, -- CLK => S_AXI_ACLK, -- D => ap_rst_vec, -- Q => ap_rst_sync -- ); -- process(S_AXI_ACLK) -- begin -- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then -- ap_rst_vec(0) <= ap_rst; -- ap_rst_sync(0) <= ap_rst_vec(0); -- end if; -- end process; -- process(S_AXI_ACLK, S_AXI_ARESETN) -- begin -- if(S_AXI_ARESETN='0') then -- axi_rst <= '1'; -- elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then -- axi_rst <= ap_rst_axi_sync; -- end if; -- end process; ap_rst_axi_sync1 : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => 1, C_MTBF_STAGES => 2 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => ap_rst, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => axi_rst, scndry_vect_out => open ); --------------------------------------- COMMAND_FIFO_NEW : entity axis_accelerator_adapter_v2_1_6.async_fifo_dist_inst generic map ( C_FAMILY => C_FAMILY, DEPTH => 32, WIDTH => 32) port map ( din => host_cmd_data, din_vld => host_cmd_we, din_rdy => host_cmd_rdy, wr_clk => S_AXI_ACLK, wr_rst => axi_rst, dout => command, dout_vld => command_vld, dout_rdy => command_rdy, rd_clk => ap_clk, rd_rst => ap_rst); arg_mask <= command(ARG_MASK_MSB downto ARG_MASK_LSB); scalar_mask <= command(ISCALAR_MASK_MSB downto ISCALAR_MASK_LSB) & command(SCALAR_MASK_MSB downto SCALAR_MASK_LSB); --scalar_mask <= command(SCALAR_MASK_MSB downto SCALAR_MASK_LSB); opcode <= command(OPCODE_MSB downto OPCODE_LSB); process(ap_clk) begin if(ap_clk'event and ap_clk = '1') then if(ap_rst = '1' or input_mask_clr = '1') then iarg_mask <= (others => '0'); iscalar_mask <= (others => '0'); elsif(input_mask_we = '1') then iarg_mask <= iarg_mask or arg_mask; iscalar_mask <= iscalar_mask or scalar_mask; end if; end if; end process; process(ap_clk) begin if(ap_clk'event and ap_clk = '1') then if(ap_rst = '1' or output_mask_clr = '1') then oarg_mask <= (others => '0'); oscalar_mask <= (others => '0'); elsif(output_mask_we = '1') then oarg_mask <= oarg_mask or arg_mask; oscalar_mask <= oscalar_mask or scalar_mask(15 downto 0); end if; end if; end process; ---------------------------------------- USE_INPUT_ARGS_GEN : if (C_N_INPUT_ARGS > 0) generate begin iarg_start <= and_reduce(mb_iarg_rdy(C_N_INPUT_ARGS-1 downto 0) or not(iarg_rqt_enable_sync(C_N_INPUT_ARGS-1 downto 0))); end generate USE_INPUT_ARGS_GEN; NO_INPUT_ARGS_GEN : if (C_N_INPUT_ARGS = 0) generate begin iarg_start <= '1'; end generate NO_INPUT_ARGS_GEN; USE_OUTPUT_ARGS_GEN : if (C_N_OUTPUT_ARGS > 0) generate begin oarg_start <= and_reduce(mb_oarg_rdy(C_N_OUTPUT_ARGS-1 downto 0) or not(oarg_rqt_enable_sync(C_N_OUTPUT_ARGS-1 downto 0))); end generate USE_OUTPUT_ARGS_GEN; NO_OUTPUT_ARGS_GEN : if (C_N_OUTPUT_ARGS = 0) generate begin oarg_start <= '1'; end generate NO_OUTPUT_ARGS_GEN; USE_INPUT_SCALAR_GEN1 : if (C_N_INPUT_SCALARS+C_N_INOUT_SCALARS > 0 ) generate begin iscalar_start <= and_reduce((ap_iscalar_rdy(C_MAX_N_ISCALARS-1 downto 0)) or not(iscalar_rqt_enable(C_MAX_N_ISCALARS-1 downto 0))); --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0) or not(iscalar_rqt_enable(C_N_INPUT_SCALARS-1 downto 0))) and and_reduce(ap_iscalar_rdy(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) or not(iscalar_rqt_enable(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS))); end generate USE_INPUT_SCALAR_GEN1; -- USE_INPUT_SCALAR_GEN2 : if (C_N_INPUT_SCALARS > 0 and C_N_INOUT_SCALARS = 0) generate -- begin -- --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0)); -- iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0) or not(iscalar_rqt_enable(C_N_INPUT_SCALARS-1 downto 0))); -- end generate USE_INPUT_SCALAR_GEN2; -- -- USE_INPUT_SCALAR_GEN3 : if (C_N_INPUT_SCALARS = 0 and C_N_INOUT_SCALARS > 0) generate -- begin -- --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0)); -- iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS) or not(iscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS))); -- end generate USE_INPUT_SCALAR_GEN3; NO_INPUT_SCALAR_GEN : if (C_N_INPUT_SCALARS = 0 and C_N_INOUT_SCALARS = 0) generate begin iscalar_start <= '1'; end generate NO_INPUT_SCALAR_GEN; USE_OUTPUT_SCALAR_GEN1 : if (C_N_OUTPUT_SCALARS+C_N_INOUT_SCALARS > 0 ) generate begin oscalar_start <= and_reduce((ap_oscalar_rdy(C_MAX_N_OSCALARS-1 downto 0)) or not(oscalar_rqt_enable(C_MAX_N_OSCALARS-1 downto 0))); --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0) or not(oscalar_rqt_enable(C_N_OUTPUT_SCALARS-1 downto 0))); end generate USE_OUTPUT_SCALAR_GEN1; -- USE_OUTPUT_SCALAR_GEN2 : if (C_N_OUTPUT_SCALARS > 0 and C_N_INOUT_SCALARS > 0) generate -- begin -- --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0)); -- oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) or not(oscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS))) and and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0) or not(oscalar_rqt_enable(C_N_OUTPUT_SCALARS-1 downto 0))); -- end generate USE_OUTPUT_SCALAR_GEN2; -- -- USE_OUTPUT_SCALAR_GEN3 : if (C_N_OUTPUT_SCALARS = 0 and C_N_INOUT_SCALARS > 0) generate -- begin -- --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0)); -- oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) or not(oscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS))); -- end generate USE_OUTPUT_SCALAR_GEN3; NO_OUTPUT_SCALAR_GEN : if (C_N_OUTPUT_SCALARS = 0 and C_N_INOUT_SCALARS = 0) generate begin oscalar_start <= '1'; end generate NO_OUTPUT_SCALAR_GEN; -- pragma translate_off process(opcode) begin dbg_opcode <= op_invalid; case opcode is when UPDATE_INPUT => dbg_opcode <= op_update_input; when UPDATE_OUTPUT => dbg_opcode <= op_update_output; when EXECUTE_STEP => dbg_opcode <= op_exec_step; when EXECUTE_RESUME => dbg_opcode <= op_exec_resume; when EXECUTE_STOP => dbg_opcode <= op_exec_stop; when others => null; end case; end process; -- pragma translate_on EXISTING : if (C_EXTRA_SYNCS = 0) generate begin global_start <= iarg_start and oarg_start and iscalar_start and oscalar_start; end generate EXISTING; NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate begin AP_IARGSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rst, prmry_in => iarg_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => iarg_start_sync, scndry_vect_out => open ); AP_OARGSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => S_AXI_ACLK, prmry_resetn => S_AXI_ARESETN, prmry_in => oarg_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => oarg_start_sync, scndry_vect_out => open ); AP_ISCALARSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => S_AXI_ACLK, prmry_resetn => S_AXI_ARESETN, prmry_in => iscalar_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => iscalar_start_sync, scndry_vect_out => open ); AP_OSCALARSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => S_AXI_ACLK, prmry_resetn => S_AXI_ARESETN, prmry_in => oscalar_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => oscalar_start_sync, scndry_vect_out => open ); global_start <= iarg_start_sync and oarg_start_sync and iscalar_start_sync and oscalar_start_sync; end generate NEW_INTRO; process(ap_clk, ap_rst) begin if(ap_rst = '1') then state <= idle; ap_start_i <= '0'; ap_start_one_shot <= '0'; run_continous <= '0'; elsif(ap_clk'event and ap_clk = '1') then ap_start_i <= '0'; ap_start_one_shot <= '0'; case state is when idle => -- Wait until there is a command available if (command_vld = '1') then case opcode is when EXECUTE_STEP => state <= wait_start; when EXECUTE_RESUME => run_continous <= '1'; state <= wait_start; when others => end case; end if; when apply_input_mask => -- In this state we apply the command. For input arguments and -- scalars we give a "done" of the elements. state <= wait_start; when wait_start => if (run_continous = '0') then -- accelerator start is given when: -- 1.- all input arguments have data valid to process. -- 2.- all ouput arguments have free memory where to wite the -- processed data. if (global_start = '1') then state <= wait_done; ap_start_i <= '1'; ap_start_one_shot <= '1'; end if; else if (command_vld = '1') then case opcode is when EXECUTE_STOP => run_continous <= '0'; state <= idle; when others => state <= stop; end case; elsif (global_start = '1') then state <= wait_done; ap_start_i <= '1'; ap_start_one_shot <= '1'; end if; end if; when wait_done => if(ap_done = '1') then if (run_continous = '0') then state <= idle; else state <= apply_input_mask; end if; end if; when others => end case; end if; end process; ap_start <= core_ap_start; process(state, global_start, run_continous, command_vld, opcode, iarg_mask, iscalar_mask, arg_mask, scalar_mask, ap_done, oarg_mask, oscalar_mask) begin command_rdy <= '0'; input_mask_we <= '0'; output_mask_we <= '0'; input_mask_clr <= '0'; output_mask_clr <= '0'; mb_iarg_done_i <= (others => '0'); ap_iscalar_done <= (others => '0'); mb_oarg_done_i <= (others => '0'); ap_oscalar_vld <= (others => '0'); set_ap_start <= '0'; ap_cmd_error <= '0'; case state is when idle => command_rdy <= command_vld; if(command_vld = '1') then case opcode is when UPDATE_INPUT => input_mask_we <= '1'; mb_iarg_done_i <= arg_mask; ap_iscalar_done <= scalar_mask; when UPDATE_OUTPUT => output_mask_we <= '1'; when EXECUTE_STEP => when EXECUTE_RESUME => when EXECUTE_STOP => when others => end case; end if; when apply_input_mask => mb_iarg_done_i <= iarg_mask; ap_iscalar_done <= iscalar_mask; when wait_start => if (run_continous = '0') then set_ap_start <= global_start; else if (command_vld = '1') then command_rdy <= '1'; if (opcode = EXECUTE_STOP) then input_mask_clr <= '1'; output_mask_clr <= '1'; else ap_cmd_error <= '1'; end if; else set_ap_start <= global_start; end if; end if; when wait_done => if(ap_done = '1') then -- Toggle the output argument multibuffer (if enabled) if (C_N_OUTPUT_ARGS > 0) then mb_oarg_done_i(C_N_OUTPUT_ARGS-1 downto 0) <= oarg_mask(C_N_OUTPUT_ARGS-1 downto 0); end if; -- Write values in output FIFOs (if enabled) if (C_N_OUTPUT_SCALARS+C_N_INOUT_SCALARS > 0) then ap_oscalar_vld(C_MAX_N_OSCALARS-1 downto 0) <= oscalar_mask(C_MAX_N_OSCALARS-1 downto 0); end if; -- if (C_N_INOUT_SCALARS > 0) then -- ap_oscalar_vld(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= oscalar_mask(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS); -- end if; -- clear input/output masks before we start a new iteration input_mask_clr <= not(run_continous); output_mask_clr <= not(run_continous); end if; when others => end case; end process; clr_ap_start <= ap_ready; process(ap_clk, ap_rst) begin if(ap_rst = '1') then set_ap_start_r <= '0'; elsif(ap_clk'event and ap_clk = '1') then set_ap_start_r <= set_ap_start; end if; end process; process(ap_clk, ap_rst) begin if(ap_rst = '1') then core_ap_start <= '0'; elsif(ap_clk'event and ap_clk = '1') then -- Core ap_start delayed version. if(core_ap_start = '0') then core_ap_start <= set_ap_start_r; else core_ap_start <= not(clr_ap_start); end if; end if; end process; --------------------------- SYNC_AP_START_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_start_i_sync, axi_clk => S_AXI_ACLK, flag => status_ap_start, flag_clr => status_ap_start_clr); SYNC_AP_DONE_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_done_sync, axi_clk => S_AXI_ACLK, flag => status_ap_done, flag_clr => status_ap_done_clr); STATUS_AP_IDLE_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_idle_sync, axi_clk => S_AXI_ACLK, flag => status_ap_idle, flag_clr => status_ap_idle_clr); STATUS_AP_READY_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_ready_sync, axi_clk => S_AXI_ACLK, flag => status_ap_ready, flag_clr => status_ap_ready_clr); SYNC_AP_CMD_ERROR_I : entity work.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_cmd_error_sync, axi_clk => S_AXI_ACLK, flag => host_cmd_error_i, flag_clr => host_cmd_error_i); host_cmd_error <= host_cmd_error_i; -- TODO: status_iarg_rqt <= (others => '0'); status_iarg_ack <= (others => '0'); status_oarg_rqt <= (others => '0'); status_oarg_ack <= (others => '0'); ap_continue <= ap_done; end rtl;
<filename>bin_Erosion_Operation/ip/Erosion/fp_delbit.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_DELBIT.VHD * --* * --* Function: Generic Bit Delay * --* * --* 01/12/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY fp_delbit IS GENERIC ( pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); END fp_delbit; ARCHITECTURE rtl OF fp_delbit IS component fp_delbit_one IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; component fp_delbit_var IS GENERIC ( pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; BEGIN genone: IF (pipes = 1) GENERATE delone: fp_delbit_one PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; genvar: IF (pipes > 1) GENERATE delvar: fp_delbit_var GENERIC MAP (pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; END rtl;
<reponame>MohammadNiknam17/VHDL-12BIT-Counter-to-7segment-output library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- common cathode 7Segment entity Binary_To_7S_HEX is port (Binary: in std_logic_vector (3 downto 0); a,b,c,d,e,f,g: out std_logic); end Binary_To_7S_HEX; architecture Behavioral of Binary_To_7S_HEX is signal TMP: std_logic_vector(6 downto 0); begin process(Binary) begin case Binary is when "0000" => TMP <= "1111110" ; -- 0 HEX when "0001" => TMP <= "0110000" ; -- 1 HEX when "0010" => TMP <= "1101101" ; -- 2 HEX when "0011" => TMP <= "1111001" ; -- 3 HEX when "0100" => TMP <= "0110011" ; -- 4 HEX when "0101" => TMP <= "1011011" ; -- 5 HEX when "0110" => TMP <= "1011111" ; -- 6 HEX when "0111" => TMP <= "1110001" ; -- 7 HEX when "1000" => TMP <= "1111111" ; -- 8 HEX when "1001" => TMP <= "1110011" ; -- 9 HEX when "1010" => TMP <= "1110111" ; -- A HEX when "1011" => TMP <= "0011111" ; -- B HEX when "1100" => TMP <= "1001110" ; -- C HEX when "1101" => TMP <= "0111101" ; -- D HEX when "1110" => TMP <= "1001111" ; -- E HEX when "1111" => TMP <= "1000111" ; -- F HEX when others => TMP <= "0000000" ; end case; end process; a <= TMP(6); b <= TMP(5); c <= TMP(4); d <= TMP(3); e <= TMP(2); f <= TMP(1); g <= TMP(0); end Behavioral;
----------------------------------------------------------------------- -- int mul wrapper ----------------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.customTypes.all; entity mul_op is Generic ( INPUTS: integer; OUTPUTS: integer; DATA_SIZE_IN: integer; DATA_SIZE_OUT: integer ); port ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; pValidArray : IN std_logic_vector(1 downto 0); nReadyArray : in std_logic_vector(0 downto 0); validArray : out std_logic_vector(0 downto 0); readyArray : OUT std_logic_vector(1 downto 0); dataInArray : in data_array (1 downto 0)(DATA_SIZE_IN-1 downto 0); dataOutArray : out data_array (0 downto 0)(DATA_SIZE_OUT-1 downto 0)); end entity; architecture arch of mul_op is signal join_valid : STD_LOGIC; -- multiplier latency (4 or 8) constant LATENCY : integer := 4; --constant LATENCY : integer := 8; begin join: entity work.join(arch) generic map(2) port map( pValidArray, nReadyArray(0), join_valid, readyArray); -- instantiated multiplier (work.mul_4_stage or work.mul_8_stage) multiply_unit: entity work.mul_4_stage(behav) --multiply_unit: entity work.mul_8_stage(behav) port map ( clk => clk, ce => nReadyArray(0), a => dataInArray(0), b => dataInArray(1), p => dataOutArray(0)); buff: entity work.delay_buffer(arch) generic map(LATENCY) port map(clk, rst, join_valid, nReadyArray(0), validArray(0)); end architecture;
<reponame>Scheams/vhdl-calculator -------------------------------------------------------------------------------- -- Author: <NAME> -- -- Created: 01.12.2019 -- -- Unit: IO Control Unit (Testbench) -- -- Version: -- -) Version 1.0.0 -- -- Changelog: -- -) Version 1.0.0 (01.12.2019) -- First implementation of IO Control Unit testbench. -- -- Description: -- Check if the IO Control Unit debounces the buttons and switches with a -- lower frequency than the system clock. Furthermore, check if the LED -- signals are looped through. Change the signals on the the digits and -- verfiy that the unit hops through all the digts with the select line. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity tb_io_ctrl is end tb_io_ctrl; architecture sim of tb_io_ctrl is component io_ctrl port ( clk_i : in std_logic; reset_i : in std_logic; dig0_i : in std_logic_vector ( 7 downto 0); dig1_i : in std_logic_vector ( 7 downto 0); dig2_i : in std_logic_vector ( 7 downto 0); dig3_i : in std_logic_vector ( 7 downto 0); led_i : in std_logic_vector (15 downto 0); sw_i : in std_logic_vector (15 downto 0); pb_i : in std_logic_vector ( 3 downto 0); ss_o : out std_logic_vector( 7 downto 0); ss_sel_o : out std_logic_vector( 3 downto 0); led_o : out std_logic_vector(15 downto 0); swsync_o : out std_logic_vector(15 downto 0); pbsync_o : out std_logic_vector( 3 downto 0) ); end component; signal s_clk_i : std_logic; signal s_reset_i : std_logic; signal s_dig0_i : std_logic_vector ( 7 downto 0); signal s_dig1_i : std_logic_vector ( 7 downto 0); signal s_dig2_i : std_logic_vector ( 7 downto 0); signal s_dig3_i : std_logic_vector ( 7 downto 0); signal s_led_i : std_logic_vector (15 downto 0); signal s_sw_i : std_logic_vector (15 downto 0); signal s_pb_i : std_logic_vector ( 3 downto 0); signal s_ss_o : std_logic_vector( 7 downto 0); signal s_ss_sel_o : std_logic_vector( 3 downto 0); signal s_led_o : std_logic_vector(15 downto 0); signal s_swsync_o : std_logic_vector(15 downto 0); signal s_pbsync_o : std_logic_vector( 3 downto 0); begin u_sim: io_ctrl port map ( clk_i => s_clk_i, reset_i => s_reset_i, dig0_i => s_dig0_i, dig1_i => s_dig1_i, dig2_i => s_dig2_i, dig3_i => s_dig3_i, led_i => s_led_i, sw_i => s_sw_i, pb_i => s_pb_i, ss_o => s_ss_o, ss_sel_o => s_ss_sel_o, led_o => s_led_o, swsync_o => s_swsync_o, pbsync_o => s_pbsync_o ); ---------------------------------------------------------------------------- -- Create a reset pulse ---------------------------------------------------------------------------- p_reset: process begin s_reset_i <= '1'; wait for 500 us; s_reset_i <= '0'; wait; end process p_reset; ---------------------------------------------------------------------------- -- Create a 100MHz clock ---------------------------------------------------------------------------- p_clk: process begin s_clk_i <= '1'; wait for 5 ns; s_clk_i <= '0'; wait for 5 ns; end process p_clk; ---------------------------------------------------------------------------- -- Simulate push buttons and check if they are debounced ---------------------------------------------------------------------------- p_pb: process begin s_pb_i <= "0000"; wait for 1 ms; s_pb_i <= "0001"; wait for 3 ms; s_pb_i <= "0010"; wait for 3 ms; s_pb_i <= "0100"; wait for 3 ms; s_pb_i <= "1000"; wait for 1 ms; s_pb_i <= "0000"; wait for 1 ms; s_pb_i <= "1000"; wait; end process p_pb; ---------------------------------------------------------------------------- -- Simulate switches and check if they are debounced ---------------------------------------------------------------------------- p_sw: process begin s_sw_i <= X"0000"; wait for 1 ms; s_sw_i <= X"0F00"; wait for 3 ms; s_sw_i <= X"00F0"; wait for 3 ms; s_sw_i <= X"0000"; wait for 3 ms; s_sw_i <= X"5555"; wait for 1 ms; s_sw_i <= X"AAA5"; wait; end process p_sw; ---------------------------------------------------------------------------- -- Simulate LEDs turn on or off ---------------------------------------------------------------------------- p_led: process begin s_led_i <= X"0000"; wait for 1 ms; s_led_i <= X"5555"; wait for 6 ms; s_led_i <= X"AAAA"; wait for 3 ms; s_led_i <= X"0000"; wait; end process p_led; ---------------------------------------------------------------------------- -- Simulate raw values on the digits and check if they are displayed -- one after another. ---------------------------------------------------------------------------- p_dig: process begin s_dig0_i <= "11111111"; s_dig1_i <= "11111111"; s_dig2_i <= "11111111"; s_dig3_i <= "11111111"; wait for 1 ms; s_dig0_i <= "00111111"; s_dig1_i <= "11001111"; s_dig2_i <= "11110011"; s_dig3_i <= "11111100"; wait for 3 ms; s_dig0_i <= "00000000"; s_dig1_i <= "00111100"; s_dig2_i <= "11111111"; s_dig3_i <= "11000011"; wait for 3 ms; s_dig0_i <= "01010101"; s_dig1_i <= "10101010"; s_dig2_i <= "11110000"; s_dig3_i <= "00001111"; wait for 3 ms; s_dig0_i <= "10000000"; s_dig1_i <= "00100000"; s_dig2_i <= "00001000"; s_dig3_i <= "00000010"; wait; end process p_dig; end sim;
<filename>VHDL/dual_port_vram/ram.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RAM is port ( clock : in std_logic; -- Port a has read and write a_addr : in std_logic_vector(9 downto 0); a_write : in std_logic; a_din : in std_logic_vector(7 downto 0); a_dout : out std_logic_vector(7 downto 0); -- Port b is read only b_addr : in std_logic_vector(9 downto 0); b_dout : out std_logic_vector(7 downto 0) ); end entity RAM; architecture behavioural of RAM is type memory is array(0 to 1023) of std_logic_vector(7 downto 0); signal storage : memory := (others => (others => '0')); begin process(clock) begin if rising_edge(clock) then a_dout <= storage(to_integer(unsigned(a_addr))); b_dout <= storage(to_integer(unsigned(b_addr))); if a_write = '1' then storage(to_integer(unsigned(a_addr))) <= a_din; end if; end if; end process; end behavioural;
--******************************************************************** -- Copyright 2011-2012 by XESS Corp <http://www.xess.com>. -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. --****************************************************************** ---------------------------------------------------------------------------------- -- Modules for passing bits back and forth from the host PC -- to FPGA application logic through the JTAG port. ---------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.CommonPckg.all; package HostIoPckg is -- FPGA device type that's used to select the appropriate BSCAN primitive. type FpgaDevice_t is (SPARTAN3A, SPARTAN6); -- Use one of these to select which USER opcode enables the I/O to the host through the JTAG port. type TapUserInstr_t is (USER0, USER1, USER2, USER3, USER4); -- Use one of these to select the memory operation to perform via the JTAG port. constant NOP_OPCODE_C : std_logic_vector(1 downto 0) := "00"; constant SIZE_OPCODE_C : std_logic_vector(1 downto 0) := "01"; constant WRITE_OPCODE_C : std_logic_vector(1 downto 0) := "10"; constant READ_OPCODE_C : std_logic_vector(1 downto 0) := "11"; component BscanToHostIo is generic ( FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1 -- USER instruction this module responds to. ); port ( -- Interface to HostIoHdrScanner. inShiftDr_o : out std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_o : out std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_o : out std_logic; -- Bit from the host to the FPGA application logic. tdo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoa_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdob_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoc_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdod_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoe_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdof_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdog_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoh_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoi_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoj_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdok_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdol_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdom_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdon_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdop_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoq_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdor_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdos_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdot_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdou_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdov_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdow_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdox_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoy_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoz_i : in std_logic := LO -- Bit from the FPGA application logic to the host. ); end component; component HostIoHdrScanner is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32 -- Length of payload bit counter. ); port ( -- Interface to BscanHostIo. inShiftDr_i : in std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic; -- Bit from the host to the FPGA application logic. -- Interface to FPGA application logic. pyldCntr_o : out std_logic_vector(PYLD_CNTR_LENGTH_G-1 downto 0); -- This counts down the number of payload bits still to be received. active_o : out std_logic -- Tell the external circuitry it has been activated. ); end component; component RamCtrlSync is port ( drck_i : in std_logic; -- Clock from JTAG domain. clk_i : in std_logic; -- Clock from RAM domain. ctrlIn_i : in std_logic; -- Control signal from JTAG domain. ctrlOut_o : out std_logic; -- Control signal to RAM domain. opBegun_i : in std_logic := HI; -- R/W operation begun signal from RAM domain. doneIn_i : in std_logic := HI; -- R/W operation done signal from RAM domain. doneOut_o : out std_logic -- R/W operation done signal to the JTAG domain. ); end component; component HostIoToRamCore is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1 -- Add to address after each memory R/W operation. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the FPGA application logic. tdo_o : out std_logic; -- Bit from the FPGA application logic to the host. -- Interface to the memory. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. rwDone_i : in std_logic := HI -- True when memory read/write operation is done. ); end component; component HostIoToRam is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1; -- Add to address after each memory R/W operation. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false; -- If true, include BscanToHostIo module in this module. SYNC_G : boolean := true -- If true, sync this module with the memory clock domain. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the memory. tdo_o : out std_logic; -- Bit from the memory to the host. -- Interface to the memory. clk_i : in std_logic := LO; -- Clock from FPGA application logic. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. opBegun_i : in std_logic := HI; -- High when memory read/write operation has begun. done_i : in std_logic := HI -- High when memory read/write operation is done. ); end component; component HostIoToDut is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false -- If true, include BscanToHostIo module in this module. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the DUT. tdo_o : out std_logic; -- Bit from the DUT to the host. -- Interface to DUT. clkToDut_o : out std_logic; -- Rising edge clock signals arrival of vector to DUT. vectorFromDut_i : in std_logic_vector; -- Gather inputs to send back to host thru this bus. vectorToDut_o : out std_logic_vector -- Output test vector from the host to DUT thru this bus. ); end component; end package; --********************************************************************************************** -- This module connects the BSCAN primitive to a HostIo module. --********************************************************************************************** library IEEE, UNISIM; use IEEE.STD_LOGIC_1164.all; use UNISIM.VComponents.all; use work.CommonPckg.all; use work.HostIoPckg.all; entity BscanToHostIo is generic ( FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1 -- USER instruction this module responds to. ); port ( -- Interface to HostIoHdrScanner. inShiftDr_o : out std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_o : out std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_o : out std_logic; -- Bit from the host to the FPGA application logic. tdo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoa_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdob_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoc_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdod_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoe_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdof_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdog_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoh_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoi_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoj_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdok_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdol_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdom_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdon_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdop_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoq_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdor_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdos_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdot_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdou_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdov_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdow_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdox_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoy_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoz_i : in std_logic := LO -- Bit from the FPGA application logic to the host. ); end entity; architecture arch of BscanToHostIo is -- Signals from BSCAN primitive. signal bscanReset_s : std_logic; signal bscanShift_s : std_logic; signal bscanDrck1_s : std_logic; signal bscanDrck2_s : std_logic; signal bscanSel1_s : std_logic; signal bscanSel2_s : std_logic; signal bscanSel_s : std_logic; signal tdo_s : std_logic; begin spartan3a_bscan : if FPGA_DEVICE_G = SPARTAN3A generate -- Boundary-scan interface to FPGA JTAG port. UBscanUser : BSCAN_SPARTAN3A port map( DRCK1 => bscanDrck1_s, -- data clock after USER1 instruction received. DRCK2 => bscanDrck2_s, -- data clock after USER2 instruction received. RESET => bscanReset_s, -- JTAG TAP FSM reset. SEL1 => bscanSel1_s, -- USER1 instruction enables user-I/O. SEL2 => bscanSel2_s, -- USER2 instruction enables user-I/O. SHIFT => bscanShift_s, -- True when JTAG TAP FSM is in the SHIFT-DR state. TDI => tdi_o, -- Data bits from the host arrive through here. TDO1 => tdo_s, -- Bits from the FPGA app. logic go to the TDO pin and back to the host. TDO2 => tdo_s -- Bits from the FPGA app. logic go to the TDO pin and back to the host. ); -- All the bits from the application logic are OR'ed together since only one HostIo module -- will be active and the others will pull their TDO outputs to logic 0. tdo_s <= tdo_i or tdoa_i or tdob_i or tdoc_i or tdod_i or tdoe_i or tdof_i or tdog_i or tdoh_i or tdoi_i or tdoj_i or tdok_i or tdol_i or tdom_i or tdon_i or tdoo_i or tdop_i or tdoq_i or tdor_i or tdos_i or tdot_i or tdou_i or tdov_i or tdow_i or tdox_i or tdoy_i or tdoz_i; -- Select the appropriate sel signal based upon which USER instruction this module responds to. bscanSel_s <= bscanSel1_s when TAP_USER_INSTR_G = USER1 else bscanSel2_s; -- Detect when a USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. inShiftDr_o <= YES when bscanReset_s = LO and bscanShift_s = HI and bscanSel_s = HI else NO; -- Output the appropriate drck signal to the HostIo module. drck_o <= bscanDrck1_s when TAP_USER_INSTR_G = USER1 else bscanDrck2_s; end generate; spartan6_bscan : if FPGA_DEVICE_G = SPARTAN6 generate -- Boundary-scan interface to FPGA JTAG port. UBscanUser : BSCAN_SPARTAN6 generic map( JTAG_CHAIN => TapUserInstr_t'pos(TAP_USER_INSTR_G) ) port map( DRCK => drck_o, -- Data clock after USER instruction received. RESET => bscanReset_s, -- JTAG TAP FSM reset. SEL => bscanSel_s, -- True when USER instruction enters IR. SHIFT => bscanShift_s, -- True when JTAG TAP FSM is in the SHIFT-DR state. TDI => tdi_o, -- Data bits from the host arrive through here. TDO => tdo_s -- Bits from the FPGA app. logic go to the TDO pin and back to the host. ); -- All the bits from the application logic are OR'ed together since only one HostIo module -- will be active and the others will pull their TDO outputs to logic 0. tdo_s <= tdo_i or tdoa_i or tdob_i or tdoc_i or tdod_i or tdoe_i or tdof_i or tdog_i or tdoh_i or tdoi_i or tdoj_i or tdok_i or tdol_i or tdom_i or tdon_i or tdoo_i or tdop_i or tdoq_i or tdor_i or tdos_i or tdot_i or tdou_i or tdov_i or tdow_i or tdox_i or tdoy_i or tdoz_i; -- Detect when a USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. inShiftDr_o <= YES when bscanReset_s = LO and bscanShift_s = HI and bscanSel_s = HI else NO; end generate; end architecture; --********************************************************************************************** -- This module accepts a bitstream from a BscanHostIo module and extracts an ID and -- the number of payload bits that follow. It triggers an attached module if the received -- ID matches the ID passed in by the generic parameter. The attached module accepts the -- bitstream until all the payload bits are processed. The attached module can also return -- results that it has produced (usually from an operation initiated by a previous instruction). -- After the payload bit counter decrements to zero, this module is reset and it -- repeats the entire process for the next instruction. -- -- If the received ID does not match, the attached module is not triggered. The bitstream -- continues downstream to look for a possible match with another module. -- -- \| Complete Instruction \| -- \| Header reception \| Payload reception \| -- TDI: \| ID \| # of payload bits \| Payload bits from host \| -- TDO: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| Result bits from FPGA \| -- Bit counter \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| N-1 N-2 ...... 2 1 0 \| --********************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.CommonPckg.all; entity HostIoHdrScanner is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32 -- Length of payload bit counter. ); port ( -- Interface to BscanHostIo. inShiftDr_i : in std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic; -- Bit from the host to the FPGA application logic. -- Interface to FPGA application logic. pyldCntr_o : out std_logic_vector(PYLD_CNTR_LENGTH_G-1 downto 0); -- This counts down the number of payload bits still to be received. active_o : out std_logic -- Tell the external circuitry it has been activated. ); end entity; architecture arch of HostIoHdrScanner is -- The header register consists of the ID field and a field with the # of payload bits that follow. signal id_r : std_logic_vector(ID_G'high downto ID_G'low); signal pyldCntr_r : std_logic_vector(pyldCntr_o'range); signal hdrRcvd_r : std_logic; -- High after an ID and # of payload bits have been shifted in. begin -- Scan in the header and any following payload bits. process(drck_i) begin if rising_edge(drck_i) then -- Reset the header register if BSCAN drops out of USER SHIFT-DR state or if the current instruction is done. -- Detect when an instruction is done, i.e. has received all its payload bits. -- Detection uses payload counter value of 1 (not 0) because the last bit has entered at that point. if inShiftDr_i = NO or (hdrRcvd_r = YES and pyldCntr_r = 1) then -- Clear the header register and set MSbit of payload bit counter. A header has -- been received when this bit has been shifted all the way through the counter and ID -- registers and into the header received flag. id_r <= (others => ZERO); pyldCntr_r <= (others => ZERO); pyldCntr_r(pyldCntr_r'high) <= YES; hdrRcvd_r <= NO; else -- Otherwise, shift in header bits on the rising edge of DRCK. if hdrRcvd_r = NO then -- Shift bits into the header register until a complete header is received. pyldCntr_r <= tdi_i & pyldCntr_r(pyldCntr_r'high downto 1); id_r <= pyldCntr_r(0) & id_r(id_r'high downto 1); hdrRcvd_r <= id_r(0); else -- After a header has been received, count down the number of payload bits following the header. pyldCntr_r <= pyldCntr_r - 1; end if; end if; end if; end process; -- The attached module is activated if it matches the ID in the header. active_o <= HI when (id_r(id_r'high downto 0) = ID_G(0 to ID_G'high)) and (hdrRcvd_r = HI) else LO; -- Output the number of payload bits still to be received. pyldCntr_o <= pyldCntr_r; end architecture; --********************************************************************************************** -- This module interfaces with BscanToHostIo to perform read/write operations to memory devices. -- -- Write operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a write operation is activated by the opcode in the first two bits in the payload. -- This module then extracts a starting address from the payload bitstream. -- Then this module extracts data words from the payload bitstream and writes them to -- the memory device at sequentially increasing addresses beginning from that address. -- -- \| Header reception \| Payload bits \| -- TDI: \| ID \| # of payload bits \| Opcode \| Starting address \| Data1 \| ..... \| DataN \| -- TDO: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| -- Addr: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| Addr1 \| ..... \| AddrN \| -- Data: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| Data1 \| ..... \| DataN \| -- -- Read operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a read operation is activated by the opcode in the first two bits in the payload. -- This module then extracts a starting address from the payload bitstream. -- Then this module reads data from the memory device at sequentially increasing addresses -- starting from that address, and it shifts them serially back to the host. -- (Valid data on TDO starts after the first read of the memory completes.) -- -- \| Header reception \| Payload bits \| RAM data goes back to host \| -- TDI: \| ID \| # of payload bits \| Opcode \| Starting address \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| -- TDO: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| Data1 \| ... \| DataN-1 \| -- Addr: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| Addr1 \| Addr2 \| ... \| AddrN \| -- Data: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| Data1 \| Data2 \| ... \| DataN \| -- -- Parameter query operation: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a parameter query operation is activated by the opcode in the first two bits in the payload. -- This module then places the width of the memory address and data buses into a register -- and shifts it serially back to the host. -- -- \| Header reception \| Payload bits \| Parameter data goes back to host \| -- TDI: \| ID \| # of payload bits \| Opcode \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| -- TDO: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| Address width \| Data width \| -- Addr: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| -- Data: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| --********************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.CommonPckg.all; use work.HostIoPckg.all; entity HostIoToRamCore is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1 -- Add to address after each memory R/W operation. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the FPGA application logic. tdo_o : out std_logic; -- Bit from the FPGA application logic to the host. -- Interface to the memory. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. rwDone_i : in std_logic := HI -- True when memory read/write operation is done. ); end entity; architecture arch of HostIoToRamCore is signal pyldCntr_s : std_logic_vector(PYLD_CNTR_LENGTH_G-1 downto 0); signal active_s : std_logic; signal opcode_r : std_logic_vector(NOP_OPCODE_C'range) := NOP_OPCODE_C; signal opcodeRcvd_r : std_logic := NO; signal addrFromHost_r : std_logic_vector(addr_o'high downto 0) := (others => ZERO); signal addrFromHostRcvd_r : std_logic := NO; constant PARAM_SIZE_C : natural := 16; constant SHIFT_REG_SIZE_C : natural := IntMax(PARAM_SIZE_C, dataFromHost_o'length); signal shiftReg_r : std_logic_vector(SHIFT_REG_SIZE_C-1 downto 0) := (others => ZERO); signal bitCntr_r : natural range 0 to SHIFT_REG_SIZE_C := 0; signal wrToMemory_r : std_logic := NO; signal rdFromMemory_r : std_logic := NO; signal dataFromMemory_r : std_logic_vector(dataToHost_i'high downto 0); begin -- Scan the bits from the host looking for an instruction header. UHdrScannner : HostIoHdrScanner generic map ( ID_G => ID_G, PYLD_CNTR_LENGTH_G => PYLD_CNTR_LENGTH_G ) port map ( -- Interface to BSCAN primitive. inShiftDr_i => inShiftDr_i, drck_i => drck_i, tdi_i => tdi_i, -- Interface to FPGA application logic. pyldCntr_o => pyldCntr_s, active_o => active_s ); -- Process the instruction bits as they arrive from the host. process(drck_i) begin if rising_edge(drck_i) then -- Keep processing as long as this module is activated or writing to memory. if (active_s = YES or wrToMemory_r = HI) and (reset_i = LO) then -- First, get the opcode from the host. if opcodeRcvd_r = NO then opcode_r <= tdi_i & opcode_r(opcode_r'high downto 1); opcodeRcvd_r <= opcode_r(0); -- Opcode complete once LSB is set. -- Next, process the received opcode. else case opcode_r is when SIZE_OPCODE_C => -- Return memory address and data bus parameters. if bitCntr_r = 0 then -- Load the memory parameters into the host shift register. shiftReg_r(PARAM_SIZE_C-1 downto 0) <= CONV_STD_LOGIC_VECTOR(dataFromHost_o'length, PARAM_SIZE_C/2) & CONV_STD_LOGIC_VECTOR(addr_o'length, PARAM_SIZE_C/2); bitCntr_r <= PARAM_SIZE_C; -- Set the number of data bits to send. else -- Shift next bit of memory parameters to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. end if; when WRITE_OPCODE_C => -- Perform write to memory. if addrFromHostRcvd_r = NO then -- Receiving the memory write address from the host. addrFromHost_r <= tdi_i & addrFromHost_r(addrFromHost_r'high downto 1); addrFromHostRcvd_r <= addrFromHost_r(0); -- Address complete once LSB is set. wrToMemory_r <= NO; shiftReg_r <= (others => ZERO); shiftReg_r(dataFromHost_o'high) <= ONE; else -- Now get data to write to memory from the host. if wrToMemory_r = YES and rwDone_i = YES then -- Write to memory is done. wrToMemory_r <= NO; -- Stop any further writes till another complete data word arrives from host. addrFromHost_r <= addrFromHost_r + ADDR_INC; -- Point to next memory location to be written (if needed). end if; if shiftReg_r(0) = LO then -- Shifting in data from host before writing it to memory. shiftReg_r(dataFromHost_o'range) <= tdi_i & shiftReg_r(dataFromHost_o'high downto 1); else -- Data from host received, now write it into the memory. dataFromHost_o <= tdi_i & shiftReg_r(dataFromHost_o'high downto 1); -- Store host data so it doesn't change if more bits arrive from host. -- Clear shift register so it can receive more data from the host. shiftReg_r <= (others => ZERO); shiftReg_r(dataFromHost_o'high) <= HI; wrToMemory_r <= YES; -- Initiate write of host data to memory. end if; end if; -- Perform read of memory. when READ_OPCODE_C => if addrFromHostRcvd_r = NO then -- Receiving the memory read address from the host. addrFromHost_r <= tdi_i & addrFromHost_r(addrFromHost_r'high downto 1); addrFromHostRcvd_r <= addrFromHost_r(0); -- Address complete once LSB is set. rdFromMemory_r <= addrFromHost_r(0); -- Initiate read as soon as address is received. bitCntr_r <= dataFromMemory_r'length - 1; -- Output garbage word until 1st read has a chance to complete. else if rdFromMemory_r = YES and rwDone_i = YES then -- Receive a complete data word from the host. rdFromMemory_r <= NO; -- OK, data is here so stop the reading the memory. dataFromMemory_r <= dataToHost_i; -- Store the memory data until it can be loaded into the host shift reg. end if; if bitCntr_r = 0 then -- Shift register is empty. shiftReg_r(dataFromMemory_r'range) <= dataFromMemory_r; -- Reload it with new data from memory. bitCntr_r <= dataFromMemory_r'length-1; -- Reload the bit counter. if pyldCntr_s >= shiftReg_r'length then -- Is more data expected by the host? addrFromHost_r <= addrFromHost_r + ADDR_INC; -- Point to next memory location to read from. rdFromMemory_r <= YES; -- Initiate the read operation. end if; else -- Shift register is shifting its contents to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. end if; end if; -- Default case is NOP. when others => null; end case; end if; else -- Reset everything when this module is not selected or is reset. opcode_r <= (others => ZERO); opcode_r(opcode_r'high) <= ONE; opcodeRcvd_r <= NO; addrFromHost_r <= (others => ZERO); addrFromHost_r(addrFromHost_r'high) <= ONE; addrFromHostRcvd_r <= NO; shiftReg_r <= (others => ZERO); shiftReg_r(dataFromHost_o'high) <= ONE; bitCntr_r <= 0; wrToMemory_r <= NO; rdFromMemory_r <= NO; end if; end if; end process; -- Force output low if this module has not been selected. -- This allows the bit outputs of multiple modules to be OR'ed together -- and sent to the TDO input of the BSCAN primitive. tdo_o <= shiftReg_r(0) when active_s = YES else LO; -- Attach this module to a memory. addr_o <= addrFromHost_r; wr_o <= wrToMemory_r; rd_o <= rdFromMemory_r; end architecture; --********************************************************************************************** -- This module synchronizes a HostIoToRamCore read or write control signal to the clock domain -- of the memory device. --********************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use work.CommonPckg.all; use work.SyncToClockPckg.all; entity RamCtrlSync is port ( drck_i : in std_logic; -- Clock from JTAG domain. clk_i : in std_logic; -- Clock from RAM domain. ctrlIn_i : in std_logic; -- Control signal from JTAG domain. ctrlOut_o : out std_logic; -- Control signal to RAM domain. opBegun_i : in std_logic := HI; -- R/W operation begun signal from RAM domain. doneIn_i : in std_logic := HI; -- R/W operation done signal from RAM domain. doneOut_o : out std_logic -- R/W operation done signal to the JTAG domain. ); end entity; architecture arch of RamCtrlSync is signal ctrlIn_s : std_logic; -- JTAG domain control signal sync'ed to RAM domain. begin -- Sync the RAM control signal from the JTAG clock domain to the RAM domain. UCtrlSync : SyncToClock port map (clk_i => clk_i, unsynced_i => ctrlIn_i, synced_o => ctrlIn_s); -- Now raise-and-hold the output control signal to the RAM upon a rising edge of the input control signal. -- Lower the output control signal if the input control signal goes low or if the RAM signals that the -- operation has begun or has finished. process(clk_i) variable prevCtrlIn_v : std_logic := HI; -- Previous value of the input control signal. begin if rising_edge(clk_i) then if ctrlIn_s = LO then -- Lower the RAM control signal if the input signal has been deactivated. ctrlOut_o <= LO; elsif prevCtrlIn_v = LO then -- Raise the RAM control signal upon a rising edge of the input control signal. ctrlOut_o <= HI; elsif opBegun_i = HI or doneIn_i = HI then -- Lower the RAM control signal once the RAM has begun or completed the R/W operation. ctrlOut_o <= LO; end if; prevCtrlIn_v := CtrlIn_s; -- Store the previous value of the input control signal. end if; end process; -- Inform the HostIoToRamCore when the memory operation is done. Latch the done signal -- from the RAM until the HostIoToRamCore sees it and lowers its control signal. -- Once the control signal is lowered, the RAM will eventually lower its done signal. process(clk_i) begin if rising_edge(clk_i) then if ctrlIn_s = LO then doneOut_o <= LO; elsif doneIn_i = HI then doneOut_o <= HI; end if; end if; end process; end architecture; --********************************************************************************************** -- This module combines the HostIoToRamCore with two RamCtrlSync modules for the R/W control -- signals to form a complete interface between the JTAG port and a memory device. --********************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use work.CommonPckg.all; use work.SyncToClockPckg.all; use work.HostIoPckg.all; entity HostIoToRam is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1; -- Add to address after each memory R/W operation. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false; -- If true, include BscanToHostIo module in this module. SYNC_G : boolean := true -- If true, sync this module with the memory clock domain. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the memory. tdo_o : out std_logic; -- Bit from the memory to the host. -- Interface to the memory. clk_i : in std_logic := LO; -- Clock from FPGA application logic. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. opBegun_i : in std_logic := HI; -- High when memory read/write operation has begun. done_i : in std_logic := HI -- High when memory read/write operation is done. ); end entity; architecture arch of HostIoToRam is -- Internal memory signals. signal wr_s : std_logic; signal rd_s : std_logic; signal wrDone_s : std_logic; signal rdDone_s : std_logic; signal rwDone_s : std_logic; -- Internal JTAG signals. signal inShiftDr_s : std_logic; signal drck_s : std_logic; signal tdi_s : std_logic; signal tdo_s : std_logic; begin -- If you're only interfacing the JTAG port to a single module, then the -- SIMPLE_G parameter lets you build the JTAG interface right into this interface -- and connect it to the internal JTAG signals. USimple : if SIMPLE_G = true generate begin UBscanHostIo : BscanToHostIo generic map( FPGA_DEVICE_G => FPGA_DEVICE_G, TAP_USER_INSTR_G => TAP_USER_INSTR_G ) port map( inShiftDr_o => inShiftDr_s, drck_o => drck_s, tdi_o => tdi_s, tdo_i => tdo_s ); end generate; -- If you're interfacing several modules to the JTAG port, then you'll be using -- an external JTAG module. So just connect the I/O ports to the internal -- JTAG signals. UComplex : if SIMPLE_G = false generate begin inShiftDr_s <= inShiftDr_i; drck_s <= drck_i; tdi_s <= tdi_i; tdo_o <= tdo_s; end generate; -- Connect the HostIoToRamCore to the internal JTAG and memory signals. UHostIoToRamCore : HostIoToRamCore generic map ( ID_G => ID_G, PYLD_CNTR_LENGTH_G => PYLD_CNTR_LENGTH_G, ADDR_INC => ADDR_INC ) port map( reset_i => reset_i, inShiftDr_i => inShiftDr_s, drck_i => drck_s, tdi_i => tdi_s, tdo_o => tdo_s, addr_o => addr_o, wr_o => wr_s, dataFromHost_o => dataFromHost_o, rd_o => rd_s, dataToHost_i => dataToHost_i, rwDone_i => rwDone_s ); -- Synchronize the JTAG interface to the memory clock domain. USync : if SYNC_G = true generate begin UWrRamCtrlSync : RamCtrlSync port map ( drck_i => drck_s, clk_i => clk_i, ctrlIn_i => wr_s, ctrlOut_o => wr_o, opBegun_i => opBegun_i, doneIn_i => done_i, doneOut_o => wrDone_s ); URdRamCtrlSync : RamCtrlSync port map ( drck_i => drck_s, clk_i => clk_i, ctrlIn_i => rd_s, ctrlOut_o => rd_o, opBegun_i => opBegun_i, doneIn_i => done_i, doneOut_o => rdDone_s ); -- Only one read or write memory operation can be in-process at a time, -- so OR their done signals together to create a unified -- "memory operation done" signal. rwDone_s <= rdDone_s or wrDone_s; end generate; -- Don't synchronize the JTAG interface to the memory clock domain. UUnsync : if SYNC_G = false generate begin rwDone_s <= done_i; rd_o <= rd_s; wr_o <= wr_s; end generate; end architecture; --********************************************************************************************** -- This module interfaces with BscanToHostIo to send/receive test vectors to/from a device-under-test (DUT). -- -- Write operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a write operation is activated by the opcode in the first two bits in the payload. -- This module then captures N bits serially from TDI and outputs them in parallel -- onto the inputs of the DUT. A clock pulse is also generated which can be used to clock -- the DUT if desired. -- -- \| Header reception \| Payload bits \| One clock cycle \| -- TDI: \| ID \| # of payload bits \| Opcode \| b1 b2 b3 b4 b5 ... bN \| -- TDO: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| -- DUT INP: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| b1b2b3b4...bN \| -- DUT clk: \|____________________________________________________________________\|^^^^^^^^\|____ -- -- Read operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a read operation is activated by the opcode in the first two bits in the payload. -- This module captures all the outputs from the DUT in parallel and then shifts them -- back to the host on TDO. -- -- \| Header reception \| Payload bits \| One clock cycle \| DUT output bits \| -- TDI: \| ID \| # of payload bits \| Opcode \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| -- TDO: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| b1 b2 b3 b4 ... bN \| -- DUT OUTP: \| b1b2b3b4...bN \| -- -- Parameter query operation: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a parameter query operation is activated by the opcode in the first two bits in the payload. -- This module then places the number of DUT inputs and outputs into a register and shifts it -- serially back to the host. -- -- \| Header reception \| Payload bits \| Parameter data goes back to host \| -- TDI: \| ID \| # of payload bits \| Opcode \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| -- TDO: \|xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\| # DUT inputs \| # DUT outputs \| --************************************************************************************************ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.CommonPckg.all; use work.HostIoPckg.all; entity HostIoToDut is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false -- If true, include BscanToHostIo module in this module. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the DUT. tdo_o : out std_logic; -- Bit from the DUT to the host. -- Interface to DUT. clkToDut_o : out std_logic; -- Rising edge clock signals arrival of vector to DUT. vectorFromDut_i : in std_logic_vector; -- Gather inputs to send back to host thru this bus. vectorToDut_o : out std_logic_vector -- Output test vector from the host to DUT thru this bus. ); end entity; architecture arch of HostIoToDut is signal active_s : std_logic; -- True when the module is activated by a matching ID. signal opcode_r : std_logic_vector(NOP_OPCODE_C'range); -- Stores opcode received via JTAG. signal opcodeRcvd_r : std_logic; -- True once opcode is received. constant PARAM_SIZE_C : natural := 16; constant SHIFT_REG_SIZE_C : natural := IntMax(IntMax(PARAM_SIZE_C, vectorFromDut_i'length), vectorToDut_o'length); signal shiftReg_r : std_logic_vector(SHIFT_REG_SIZE_C-1 downto 0); -- Stores DUT input & output bits. signal bitCntr_r : natural range 0 to SHIFT_REG_SIZE_C; signal activateClk_r : std_logic; -- Internal JTAG signals. signal inShiftDr_s : std_logic; signal drck_s : std_logic; signal tdi_s : std_logic; signal tdo_s : std_logic; begin -- If you're only interfacing the JTAG port to a single module, then the -- SIMPLE_G parameter lets you build the JTAG interface right into this interface -- and connect it to the internal JTAG signals. USimple : if SIMPLE_G = true generate begin UBscanHostIo : BscanToHostIo generic map( FPGA_DEVICE_G => FPGA_DEVICE_G, TAP_USER_INSTR_G => TAP_USER_INSTR_G ) port map( inShiftDr_o => inShiftDr_s, drck_o => drck_s, tdi_o => tdi_s, tdo_i => tdo_s ); end generate; -- If you're interfacing several modules to the JTAG port, then you'll be using -- an external JTAG module. So just connect the I/O ports to the internal -- JTAG signals. UComplex : if SIMPLE_G = false generate begin inShiftDr_s <= inShiftDr_i; drck_s <= drck_i; tdi_s <= tdi_i; tdo_o <= tdo_s; end generate; -- Scan the bits from the host looking for an instruction header. UHdrScanner : HostIoHdrScanner generic map ( ID_G => ID_G, PYLD_CNTR_LENGTH_G => PYLD_CNTR_LENGTH_G ) port map ( -- Interface to BSCAN primitive. inShiftDr_i => inShiftDr_s, drck_i => drck_s, tdi_i => tdi_s, -- Interface to DUT. active_o => active_s ); -- Process the instruction bits as they arrive from the host. process(drck_s) begin if rising_edge(drck_s) then activateClk_r <= LO; -- By default, keep clock to DUT inactive. -- Keep processing as long as this module is activated. if active_s = YES and reset_i = LO then -- First, get the opcode from the host. if opcodeRcvd_r = NO then opcode_r <= tdi_s & opcode_r(opcode_r'high downto 1); opcodeRcvd_r <= opcode_r(0); -- Opcode complete once LSB is set. -- Next, process the received opcode. else case opcode_r is when SIZE_OPCODE_C => -- Return DUT input and output-width parameters. if bitCntr_r = 0 then -- Load the I/O parameters into the host shift register. shiftReg_r(PARAM_SIZE_C-1 downto 0) <= CONV_STD_LOGIC_VECTOR(vectorFromDut_i'length, PARAM_SIZE_C/2) & CONV_STD_LOGIC_VECTOR(vectorToDut_o'length, PARAM_SIZE_C/2); bitCntr_r <= PARAM_SIZE_C; -- Set the number of bits to send. else -- Shift next bit of I/O parameters to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. end if; when WRITE_OPCODE_C => -- Output a test vector to the DUT. case vectorToDut_o'length is when 0 => -- No inputs to the DUT, so just pulse the clock. activateClk_r <= HI; when 1 => -- Only one input to DUT, so drive it directly from the TDI pin. vectorToDut_o(vectorToDut_o'low) <= tdi_s; activateClk_r <= HI; when others => if shiftReg_r(0) = NO then -- Shifting in data from host before applying it to the DUT. shiftReg_r(vectorToDut_o'length-1 downto 0) <= tdi_s & shiftReg_r(vectorToDut_o'length-1 downto 1); else -- Vector from host received, now apply it to the DUT. vectorToDut_o <= tdi_s & shiftReg_r(vectorToDut_o'length-1 downto 1); -- Output test vector to DUT. activateClk_r <= HI; -- Pulse vector clock for one cycle after vector is received. -- Clear shift register so it can receive another vector from the host. shiftReg_r <= (others => ZERO); -- Clear all shift register bits and ... shiftReg_r(vectorToDut_o'length-1) <= HI; -- ... set MSbit so we can tell when all bits are received. end if; end case; when READ_OPCODE_C => -- Get results of a test vector from the DUT. if bitCntr_r /= 0 then -- Shifting DUT outputs to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. else -- Load the DUT output bits into the shift register. shiftReg_r(vectorFromDut_i'length-1 downto 0) <= vectorFromDut_i; -- Load the DUT outputs into the host shift register. bitCntr_r <= vectorFromDut_i'length - 1; -- Set the number of bits to send. end if; -- Default case is NOP. when others => null; end case; end if; else -- Reset everything when this module is not selected or is reset. opcode_r <= (others => ZERO); -- Clear all opcode shift register bits and ... opcode_r(opcode_r'high) <= ONE; -- ... set MSbit so we can tell when a complete opcode is received. opcodeRcvd_r <= NO; shiftReg_r <= (others => ZERO); -- Clear all shift register bits and ... if vectorToDut_o'length > 0 then shiftReg_r(vectorToDut_o'length-1) <= ONE; -- ... set MSbit so we can tell when all bits are received. end if; bitCntr_r <= 0; end if; end if; end process; -- The inputs to the DUT are changed and the clock-enable signal is set on the rising edge of the DRCK. -- The following statement generates a rising clock edge to the DUT when DRCK goes low. This gives -- the inputs to the DUT time to settle. clkToDut_o <= not drck_s when activateClk_r = HI else LO; -- Force output low if this module has not been selected. -- This allows the bit outputs of multiple modules to be OR'ed together -- and sent to the TDO input of the BSCAN primitive. tdo_s <= shiftReg_r(0) when active_s = YES else LO; end architecture;
<reponame>chandanpalai/VHDL-example-codes library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.abc.all; entity tri is port ( I : in std_logic_vector(m-1 downto 0); -- input En : in std_logic; -- input Y : out std_logic_vector(m-1 downto 0)); -- output end entity tri; architecture tri_arc of tri is begin -- architecture tri_arc Y<= I when En='0' else (others=>'Z'); end architecture tri_arc;
<gh_stars>0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY HA_DF IS PORT ( a, b : IN std_logic; sum, cout : OUT std_logic); END ENTITY; ARCHITECTURE dataflow OF HA_DF IS BEGIN sum <= a XOR b; cout <= a AND b; END ARCHITECTURE;
<reponame>Elthra/patmos --------------------------------------------------------------------- ---- ---- ---- FPU ---- ---- Floating Point Unit (Double precision) ---- ---- ---- ---- Author: <NAME> ---- ---- <EMAIL> ---- ---- ---- --------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2009 <NAME> ---- ---- <EMAIL> ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer.---- ---- ---- ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ---- POSSIBILITY OF SUCH DAMAGE. ---- ---- ---- --------------------------------------------------------------------- library ieee; use work.fpupack.all; use work.comppack.all; use ieee.std_logic_misc.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; entity fpu_double_tb is end fpu_double_tb; architecture TB_ARCHITECTURE of fpu_double_tb is component fpu_double port( clk : in std_logic; rst : in std_logic; enable : in std_logic; rmode : in std_logic_vector(1 downto 0); fpu_op : in std_logic_vector(2 downto 0); opa : in std_logic_vector(63 downto 0); opb : in std_logic_vector(63 downto 0); out_fp : out std_logic_vector(63 downto 0); ready : out std_logic; underflow : out std_logic; overflow : out std_logic; inexact : out std_logic; exception : out std_logic; invalid : out std_logic ); end component; signal clk : std_logic; signal rst : std_logic; signal enable : std_logic; signal rmode : std_logic_vector(1 downto 0); signal fpu_op : std_logic_vector(2 downto 0); signal opa : std_logic_vector(63 downto 0); signal opb : std_logic_vector(63 downto 0); signal out_fp : std_logic_vector(63 downto 0); signal ready : std_logic; signal underflow : std_logic; signal overflow : std_logic; signal inexact : std_logic; signal exception : std_logic; signal invalid : std_logic; signal END_SIM: BOOLEAN:=FALSE; signal out_fp1 : std_logic_vector(63 downto 0); begin out_fp1 <= out_fp; UUT : fpu_double port map ( clk => clk, rst => rst, enable => enable, rmode => rmode, fpu_op => fpu_op, opa => opa, opb => opb, out_fp => out_fp, ready => ready, underflow => underflow, overflow => overflow, inexact => inexact, exception => exception, invalid => invalid ); STIMULUS: process begin rst <= '1'; wait for 20 ns; rst <= '0'; --inputA:4.0000000000e+000 --inputB:-4.0000000000e+000 enable <= '1'; opa <= "0100000000010000000000000000000000000000000000000000000000000000"; opb <= "1100000000010000000000000000000000000000000000000000000000000000"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:0.000000000000000e+000 -- out_fp = 0000000000000000 --inputA:3.0000000000e-312 --inputB:1.0000000000e-025 enable <= '1'; opa <= "0000000000000000000000001000110101100000010101111101110111110010"; opb <= "0011101010111110111100101101000011110101110110100111110111011001"; fpu_op <= "011"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.000000000000337e-287 -- out_fp = 047245C02F8B68C5 --inputA:4.0000000000e-304 --inputB:2.0000000000e-007 enable <= '1'; opa <= "0000000011110001100011100011101110011011001101110100000101101001"; opb <= "0011111010001010110101111111001010011010101111001010111101001000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:8.000000000000074e-311 -- out_fp = 00000EBA09271E89 --inputA:3.4445600000e+002 --inputB:3.4445599000e+002 enable <= '1'; opa <= "0100000001110101100001110100101111000110101001111110111110011110"; opb <= "0100000001110101100001110100101110111100001010111001010011011001"; fpu_op <= "001"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.000000003159585e-005 -- out_fp = 3EE4F8B58A000000 --inputA:-8.8899000000e+002 --inputB:7.8898020000e+002 enable <= '1'; opa <= "1100000010001011110001111110101110000101000111101011100001010010"; opb <= "0100000010001000101001111101011101110011000110001111110001010000"; fpu_op <= "000"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.000098000000000e+002 -- out_fp = C05900A0902DE010 --inputA:4.5600000000e+002 --inputB:2.3700000000e+001 enable <= '1'; opa <= "0100000001111100100000000000000000000000000000000000000000000000"; opb <= "0100000000110111101100110011001100110011001100110011001100110011"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.924050632911392e+001 -- out_fp = 40333D91D2A2067B --inputA:4.9990000000e+003 --inputB:0.0000000000e+000 enable <= '1'; opa <= "0100000010110011100001110000000000000000000000000000000000000000"; opb <= "0000000000000000000000000000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:0.000000000000000e+000 -- out_fp = 0000000000000000 --inputA:-9.8883300000e+005 --inputB:4.4444440000e+006 enable <= '1'; opa <= "1100000100101110001011010100001000000000000000000000000000000000"; opb <= "0100000101010000111101000100011100000000000000000000000000000000"; fpu_op <= "001"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-5.433277000000000e+006 -- out_fp = C154B9EF40000000 --inputA:-4.8000000000e-311 --inputB:4.0000000000e-050 enable <= '1'; opa <= "1000000000000000000010001101011000000101011111011101111100011111"; opb <= "0011010110101101111011100111101001001010110101001011100000011111"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.200000000000011e-261 -- out_fp = 89C2E4AE4EAE705E --inputA:1.9500000000e-308 --inputB:1.8800000000e-308 enable <= '1'; opa <= "0000000000001110000001011010001000110110111111110101001011001101"; opb <= "0000000000001101100001001100011001100110111010010000011110011111"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.830000000000000e-308 -- out_fp = 001B8A689DE85A6C --inputA:-3.0000000000e-309 --inputB:9.0000000000e+100 enable <= '1'; opa <= "1000000000000010001010000100000001010111001110101111100100001100"; opb <= "0101010011100100100100101110001011001010010001110101101111101101"; fpu_op <= "010"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-2.700000000000001e-208 -- out_fp = 94D630F25FC26702 --inputA:3.0000000000e-308 --inputB:2.9900000000e-308 enable <= '1'; opa <= "0000000000010101100100101000001101101000010011011011101001110111"; opb <= "0000000000010101100000000001101011011100110111001101010001001011"; fpu_op <= "001"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.000000000000046e-310 -- out_fp = 000012688B70E62C --inputA:-9.0000000000e-300 --inputB:5.0000000000e+100 enable <= '1'; opa <= "1000000111011000000110111110001110111011010110000001000111000100"; opb <= "0101010011010110110111000001100001101110111110011111010001011100"; fpu_op <= "011"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-4.940656458412465e-324 -- out_fp = 8000000000000001 --inputA:4.0000000000e+100 --inputB:3.0000000000e-090 enable <= '1'; opa <= "0101010011010010010010011010110100100101100101001100001101111101"; opb <= "0010110101011000011100011100011001000110111001011001010110100111"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.200000000000000e+011 -- out_fp = 423BF08EB0000001 --inputA:-9.9000000000e-002 --inputB:4.0220000000e+001 enable <= '1'; opa <= "1011111110111001010110000001000001100010010011011101001011110010"; opb <= "0100000001000100000111000010100011110101110000101000111101011100"; fpu_op <= "000"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.012100000000000e+001 -- out_fp = 40440F7CED916872 --inputA:9.0770000000e+001 --inputB:-2.0330000000e+001 enable <= '1'; opa <= "0100000001010110101100010100011110101110000101000111101011100001"; opb <= "1100000000110100010101000111101011100001010001111010111000010100"; fpu_op <= "000"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:7.044000000000000e+001 -- out_fp = 40519C28F5C28F5C --inputA:4.9077000000e+002 --inputB:-3.4434000000e+002 enable <= '1'; opa <= "0100000001111110101011000101000111101011100001010001111010111000"; opb <= "1100000001110101100001010111000010100011110101110000101000111101"; fpu_op <= "001"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:8.351100000000000e+002 -- out_fp = 408A18E147AE147B --inputA:9.0000000000e+034 --inputB:2.7700000000e+000 enable <= '1'; opa <= "0100011100110001010101010101011110110100000110011100010111000010"; opb <= "0100000000000110001010001111010111000010100011110101110000101001"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.249097472924188e+034 -- out_fp = 471907B705EBEABE --inputA:3.9999999989e-315 --inputB:1.0000000000e-002 enable <= '1'; opa <= "0000000000000000000000000000000000110000010000011010011100110101"; opb <= "0011111110000100011110101110000101000111101011100001010001111011"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.000000428704504e-317 -- out_fp = 00000000007B895B --inputA:-9.0000000000e+003 --inputB:8.0000000000e+003 enable <= '1'; opa <= "1100000011000001100101000000000000000000000000000000000000000000"; opb <= "0100000010111111010000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.125000000000000e+000 -- out_fp = BFF2000000000000 --inputA:9.8440000000e+003 --inputB:0.0000000000e+000 enable <= '1'; opa <= "0100000011000011001110100000000000000000000000000000000000000000"; opb <= "0000000000000000000000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.#INF00000000000e+000 -- out_fp = 7FF0000000000000 --inputA:4.4440000000e+002 --inputB:-8.8800000000e+002 enable <= '1'; opa <= "0100000001111011110001100110011001100110011001100110011001100110"; opb <= "1100000010001011110000000000000000000000000000000000000000000000"; fpu_op <= "001"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.332400000000000e+003 -- out_fp = 4094D1999999999A --inputA:3.0000000000e-309 --inputB:3.0000000000e+080 enable <= '1'; opa <= "0000000000000010001010000100000001010111001110101111100100001100"; opb <= "0101000010100100001111011011001101111101011101001011110010000111"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:0.000000000000000e+000 -- out_fp = 0000000000000000 --inputA:4.9900000000e+002 --inputB:-3.3000000000e-003 enable <= '1'; opa <= "0100000001111111001100000000000000000000000000000000000000000000"; opb <= "1011111101101011000010001001101000000010011101010010010101000110"; fpu_op <= "010"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.646700000000000e+000 -- out_fp = BFFA58E219652BD4 --inputA:9.0000000000e+034 --inputB:4.0000000000e+023 enable <= '1'; opa <= "0100011100110001010101010101011110110100000110011100010111000010"; opb <= "0100010011010101001011010000001011000111111000010100101011110110"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.000000000040000e+034 -- out_fp = 47315557B41A1A76 --inputA:4.0000000000e+080 --inputB:3.0000000000e-002 enable <= '1'; opa <= "0101000010101010111111001110111101010001111100001111101101011111"; opb <= "0011111110011110101110000101000111101011100001010001111010111000"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.000000000000001e+080 -- out_fp = 50AAFCEF51F0FB60 --inputA:-5.4770000000e+000 --inputB:-8.9990000000e+000 enable <= '1'; opa <= "1100000000010101111010000111001010110000001000001100010010011100"; opb <= "1100000000100001111111110111110011101101100100010110100001110011"; fpu_op <= "011"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:6.086231803533726e-001 -- out_fp = 3FE379D751E6915E --inputA:-7.7000000000e+001 --inputB:-8.8400000000e+001 enable <= '1'; opa <= "1100000001010011010000000000000000000000000000000000000000000000"; opb <= "1100000001010110000110011001100110011001100110011001100110011010"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:6.806800000000001e+003 -- out_fp = 40BA96CCCCCCCCCE --inputA:4.0000000000e+009 --inputB:3.0000000000e+008 enable <= '1'; opa <= "0100000111101101110011010110010100000000000000000000000000000000"; opb <= "0100000110110001111000011010001100000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.333333333333333e+001 -- out_fp = 402AAAAAAAAAAAAB --inputA:9.0000000000e-311 --inputB:8.0000000000e-311 enable <= '1'; opa <= "0000000000000000000100001001000101001010010011000000001001011010"; opb <= "0000000000000000000011101011101000001001001001110001111010001001"; fpu_op <= "000"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.700000000000010e-310 -- out_fp = 00001F4B537320E3 --inputA:1.9999777344e-320 --inputB:5.0000000000e+099 enable <= '1'; opa <= "0000000000000000000000000000000000000000000000000000111111010000"; opb <= "0101010010100010010010011010110100100101100101001100001101111101"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.999888671826831e-221 -- out_fp = 124212D01E240533 --inputA:4.4444000000e+004 --inputB:3.3000000000e+001 enable <= '1'; opa <= "0100000011100101101100111000000000000000000000000000000000000000"; opb <= "0100000001000000100000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.346787878787879e+003 -- out_fp = 40950B26C9B26C9B --inputA:9.7730000000e+000 --inputB:9.7720000000e+000 enable <= '1'; opa <= "0100000000100011100010111100011010100111111011111001110110110010"; opb <= "0100000000100011100010110100001110010101100000010000011000100101"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.000102333196889e+000 -- out_fp = 3FF0006B4DDBBE31 --inputA:8.3345700000e+003 --inputB:1.0000000000e+000 enable <= '1'; opa <= "0100000011000000010001110100100011110101110000101000111101011100"; opb <= "0011111111110000000000000000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:8.334570000000000e+003 -- out_fp = 40C04748F5C28F5C --inputA:-1.0000000000e+000 --inputB:5.8990000000e+003 enable <= '1'; opa <= "1011111111110000000000000000000000000000000000000000000000000000"; opb <= "0100000010110111000010110000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-5.899000000000000e+003 -- out_fp = C0B70B0000000000 --inputA:6.1000000000e+000 --inputB:-6.0990000000e+000 enable <= '1'; opa <= "0100000000011000011001100110011001100110011001100110011001100110"; opb <= "1100000000011000011001010110000001000001100010010011011101001100"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.999999999994458e-004 -- out_fp = 3F50624DD2F1A000 --inputA:3.0000000000e-300 --inputB:3.0000000000e-015 enable <= '1'; opa <= "0000000111000000000100101001011111010010001110101011011010000011"; opb <= "0011110011101011000001011000011101101110010110110000000100100000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.000000001157124e-315 -- out_fp = 000000006C93B838 --inputA:-9.0000000000e+088 --inputB:4.0000000000e+084 enable <= '1'; opa <= "1101001001100110100111110000000010010101111101001101000000000000"; opb <= "0101000110000000011110001110000100010001110000110101010101101101"; fpu_op <= "000"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-8.999600000000000e+088 -- out_fp = D2669EBEB27088F3 --inputA:6.6210000000e+001 --inputB:6.9892000000e+001 enable <= '1'; opa <= "0100000001010000100011010111000010100011110101110000101000111101"; opb <= "0100000001010001011110010001011010000111001010110000001000001100"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.473187203113375e-001 -- out_fp = 3FEE506F59540645 --inputA:-5.0000000000e-309 --inputB:4.0000000000e-310 enable <= '1'; opa <= "1000000000000011100110000110101100111100000011001111010001101001"; opb <= "0000000000000000010010011010001000101101110000111001100010101100"; fpu_op <= "000"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-4.600000000000001e-309 -- out_fp = 80034EC90E495BBD --inputA:8.8000000000e+001 --inputB:0.0000000000e+000 enable <= '1'; opa <= "0100000001010110000000000000000000000000000000000000000000000000"; opb <= "0000000000000000000000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.#INF00000000000e+000 -- out_fp = 7FEFFFFFFFFFFFFF --inputA:4.5570000000e+002 --inputB:3.4229100000e+003 enable <= '1'; opa <= "0100000001111100011110110011001100110011001100110011001100110011"; opb <= "0100000010101010101111011101000111101011100001010001111010111000"; fpu_op <= "000"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.878610000000000e+003 -- out_fp = 40AE4D3851EB851E --inputA:9.9440000000e+003 --inputB:2.3000000000e+001 enable <= '1'; opa <= "0100000011000011011011000000000000000000000000000000000000000000"; opb <= "0100000000110111000000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.323478260869565e+002 -- out_fp = 407B0590B21642C8 --inputA:-9.0054400000e+005 --inputB:-3.4445500000e+005 enable <= '1'; opa <= "1100000100101011011110111000000000000000000000000000000000000000"; opb <= "1100000100010101000001100001110000000000000000000000000000000000"; fpu_op <= "001"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-5.560890000000000e+005 -- out_fp = C120F87200000000 --inputA:5.5500000000e-002 --inputB:3.2444400000e+005 enable <= '1'; opa <= "0011111110101100011010100111111011111001110110110010001011010001"; opb <= "0100000100010011110011010111000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.710618781669564e-007 -- out_fp = 3E86F5A431628F6D --inputA:1.2330000000e+000 --inputB:1.5666600000e+000 enable <= '1'; opa <= "0011111111110011101110100101111000110101001111110111110011101110"; opb <= "0011111111111001000100010000101000010011011111110011100011000101"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.931691780000000e+000 -- out_fp = 3FFEE835A3D0D51B --inputA:9.7770000000e-001 --inputB:3.0000000000e+099 enable <= '1'; opa <= "0011111111101111010010010101000110000010101010011001001100001100"; opb <= "0101010010010101111100100000001011111001111001011011011101100011"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.259000000000000e-100 -- out_fp = 2B46CF7665DCED50 --inputA:4.4000000000e+007 --inputB:6.0000000000e+002 enable <= '1'; opa <= "0100000110000100111110110001100000000000000000000000000000000000"; opb <= "0100000010000010110000000000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:2.640000000000000e+010 -- out_fp = 4218964020000000 --inputA:3.9800000000e+000 --inputB:3.7700000000e+000 enable <= '1'; opa <= "0100000000001111110101110000101000111101011100001010001111010111"; opb <= "0100000000001110001010001111010111000010100011110101110000101001"; fpu_op <= "000"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:7.750000000000000e+000 -- out_fp = 401F000000000000 --inputA:8.0400000000e+000 --inputB:8.0395700000e+000 enable <= '1'; opa <= "0100000000100000000101000111101011100001010001111010111000010100"; opb <= "0100000000100000000101000100001010000100110111111100111000110001"; fpu_op <= "001"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.299999999997084e-004 -- out_fp = 3F3C2E33EFF18000 END_SIM <= TRUE; wait; end process; CLOCK_clk : process begin if END_SIM = FALSE then clk <= '0'; wait for 5 ns; else wait; end if; if END_SIM = FALSE then clk <= '1'; wait for 5 ns; else wait; end if; end process; end TB_ARCHITECTURE; configuration TESTBENCH_FOR_fpu_double of fpu_double_tb is for TB_ARCHITECTURE for UUT : fpu_double use entity work.fpu_double(rtl); end for; end for; end TESTBENCH_FOR_fpu_double;
<gh_stars>0 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:50:52 10/27/2015 -- Design Name: -- Module Name: Shifter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Shifter is Port ( Rst : in STD_LOGIC; Clk : in STD_LOGIC; DataOut : out STD_LOGIC_VECTOR (7 downto 0)); end Shifter; architecture Behavioral of Shifter is signal Reg : STD_LOGIC_VECTOR (7 downto 0); begin process(Clk,Reg) begin if (rising_edge(Clk)) then if (Rst = '1') then Reg <= (others => '0'); else Reg <= not Reg(0) & Reg (7 downto 1); end if; end if; DataOut <= Reg; end process; end Behavioral;
function findMax( a ) dim num dim max max = 0 for each num in a if num > max then max = num next findMax = max end function function findMin( a ) dim num dim min min = 0 for each num in a if num < min then min = num next findMin = min end function 'the function returns the sorted array, but the fact is that VBScript passes the array by reference anyway function countingSort( a ) dim count() dim min, max min = findMin(a) max = findMax(a) redim count( max - min + 1 ) dim i dim z for i = 0 to ubound( a ) count( a(i) - min ) = count( a( i ) - min ) + 1 next z = 0 for i = min to max while count( i - min) > 0 a(z) = i z = z + 1 count( i - min ) = count( i - min ) - 1 wend next countingSort = a end function
<filename>admin/wmi/wbem/scripting/samples/general/os.vbs for each os in GetObject("winmgmts:{impersonationLevel=impersonate}!").InstancesOf("Win32_OperatingSystem") WScript.Echo "" WScript.Echo "Version Info:" WScript.Echo "============" WScript.Echo " Version: ", os.Caption, os.Version WScript.Echo " Build: ", os.BuildNumber, os.BuildType WScript.Echo " CSD Version: ", os.CSDVersion WScript.Echo " Serial Number: ", os.SerialNumber WScript.Echo " Manufacturer: ", os.Manufacturer WScript.Echo "" WScript.Echo "Memory Info:" WScript.Echo "===========" WScript.Echo " Free Physical Memory: ", os.FreePhysicalMemory WScript.Echo " Free Space in Paging Files: ", os.FreeSpaceInPagingFiles WScript.Echo " Size Stored in Paging Files: ", os.SizeStoredInPagingFiles WScript.Echo " Free Virtual Memory: ", os.FreeVirtualMemory WScript.Echo " Total Virtual Memory Size: ", os.TotalVirtualMemorySize WScript.Echo " Total Visible Memory Size", os.TotalVisibleMemorySize WScript.Echo "" WScript.Echo "Time Info:" WScript.Echo "=========" WScript.Echo " Current Time Zone: ", os.CurrentTimeZone WScript.Echo " Install Date: ", os.InstallDate WScript.Echo " Last Bootup Time: ", os.LastBootUpTime WScript.Echo " Local Date & Time: ", os.LocalDateTime WScript.Echo "" WScript.Echo "Process Info:" WScript.Echo "============" WScript.Echo " Foreground App Boost: ", os.ForegroundApplicationBoost WScript.Echo " Maximum #Processes: ", os.MaxNumberOfProcesses WScript.Echo " Maximum Memory Size for Processes: ", os.MaxProcessMemorySize WScript.Echo " #Processes: ", os.NumberOfProcesses WScript.Echo "" WScript.Echo "User Info:" WScript.Echo "=========" WScript.Echo "#Users: ", os.NumberOfUsers WScript.Echo "Registered User: ", os.RegisteredUser WScript.Echo "" WScript.Echo "Locale Info:" WScript.Echo "===========" WScript.Echo "Code Set: ", os.CodeSet WScript.Echo "Country Code: ", os.CountryCode WScript.Echo "Locale: ", os.Locale WScript.Echo "" WScript.Echo "System Info:" WScript.Echo "===========" WScript.Echo "Boot Device: ", os.BootDevice WScript.Echo "Name: ", os.CSName WScript.Echo "Status: ", os.Status Wscript.Echo "System Device: ", os.SystemDevice WScript.Echo "System Directory: ", os.SystemDirectory WScript.Echo "Windows Directory: ", os.WindowsDirectory next
<filename>Task/Loops-Break/VBScript/loops-break.vb do a = int( rnd * 20) wscript.stdout.write a if a = 10 then exit do b = int( rnd * 20 ) wscript.echo vbnullstring,b loop dim i for i = 1 to 100000 a = int( rnd * 20) wscript.stdout.write a if a = 10 then exit for b = int( rnd * 20 ) wscript.echo vbnullstring,b next
Function UninstallCab() on error resume next Const PRO_ID = "Windows Support Tools on Desktop" CONST SERVER_ID = "Windows Support Tools" Dim PCHUpdate Dim Item Dim strProductId Set PCHUpdate = CreateObject("HCU.PCHUpdate") if not PCHUpdate is nothing then For Each Item in PCHUpdate.VersionList If Item.ProductId = PRO_ID OR Item.ProductId = SERVER_ID Then strProductId = Item.ProductId Item.Uninstall End If Next Set PCHUpdate = Nothing end if UninstallCab = 1 End Function
<filename>Task/Identity-matrix/VBScript/identity-matrix-1.vb build_matrix(7) Sub build_matrix(n) Dim matrix() ReDim matrix(n-1,n-1) i = 0 'populate the matrix For row = 0 To n-1 For col = 0 To n-1 If col = i Then matrix(row,col) = 1 Else matrix(row,col) = 0 End If Next i = i + 1 Next 'display the matrix For row = 0 To n-1 For col = 0 To n-1 If col < n-1 Then WScript.StdOut.Write matrix(row,col) & " " Else WScript.StdOut.Write matrix(row,col) End If Next WScript.StdOut.WriteLine Next End Sub
Private Function nth_root(y As Double, n As Double) Dim eps As Double: eps = 0.00000000000001 '-- relative accuracy Dim x As Variant: x = 1 Do While True d = (y / x ^ (n - 1) - x) / n x = x + d e = eps * x '-- absolute accuracy If d > -e And d < e Then Exit Do End If Loop Debug.Print y; n; x; y ^ (1 / n) End Function Public Sub main() nth_root 1024, 10 nth_root 27, 3 nth_root 2, 2 nth_root 5642, 125 nth_root 7, 0.5 nth_root 4913, 3 nth_root 8, 3 nth_root 16, 2 nth_root 16, 4 nth_root 125, 3 nth_root 1000000000, 3 nth_root 1000000000, 9 End Sub
<filename>Task/Empty-program/VBA/empty-program.vba Sub Demo() End Sub
<filename>Task/Update-a-configuration-file/VBScript/update-a-configuration-file.vb Set objFSO = CreateObject("Scripting.FileSystemObject") 'Paramater lookups Set objParamLookup = CreateObject("Scripting.Dictionary") With objParamLookup .Add "FAVOURITEFRUIT", "banana" .Add "NEEDSPEELING", "" .Add "SEEDSREMOVED", "" .Add "NUMBEROFBANANAS", "1024" .Add "NUMBEROFSTRAWBERRIES", "62000" End With 'Open the config file for reading. Set objInFile = objFSO.OpenTextFile(objFSO.GetParentFolderName(WScript.ScriptFullName) &_ "\IN_config.txt",1) 'Initialize output. Output = "" Isnumberofstrawberries = False With objInFile Do Until .AtEndOfStream line = .ReadLine If Left(line,1) = "#" Or line = "" Then Output = Output & line & vbCrLf ElseIf Left(line,1) = " " And InStr(line,"#") Then Output = Output & Mid(line,InStr(1,line,"#"),1000) & vbCrLf ElseIf Replace(Replace(line,";","")," ","") <> "" Then If InStr(1,line,"FAVOURITEFRUIT",1) Then Output = Output & "FAVOURITEFRUIT" & " " & objParamLookup.Item("FAVOURITEFRUIT") & vbCrLf ElseIf InStr(1,line,"NEEDSPEELING",1) Then Output = Output & "; " & "NEEDSPEELING" & vbCrLf ElseIf InStr(1,line,"SEEDSREMOVED",1) Then Output = Output & "SEEDSREMOVED" & vbCrLf ElseIf InStr(1,line,"NUMBEROFBANANAS",1) Then Output = Output & "NUMBEROFBANANAS" & " " & objParamLookup.Item("NUMBEROFBANANAS") & vbCrLf ElseIf InStr(1,line,"NUMBEROFSTRAWBERRIES",1) Then Output = Output & "NUMBEROFSTRAWBERRIES" & " " & objParamLookup.Item("NUMBEROFSTRAWBERRIES") & vbCrLf Isnumberofstrawberries = True End If End If Loop If Isnumberofstrawberries = False Then Output = Output & "NUMBEROFSTRAWBERRIES" & " " & objParamLookup.Item("NUMBEROFSTRAWBERRIES") & vbCrLf Isnumberofstrawberries = True End If .Close End With 'Create a new config file. Set objOutFile = objFSO.OpenTextFile(objFSO.GetParentFolderName(WScript.ScriptFullName) &_ "\OUT_config.txt",2,True) With objOutFile .Write Output .Close End With Set objFSO = Nothing Set objParamLookup = Nothing
Function IsDirEmpty(path) IsDirEmpty = False Set objFSO = CreateObject("Scripting.FileSystemObject") Set objFolder = objFSO.GetFolder(path) If objFolder.Files.Count = 0 And objFolder.SubFolders.Count = 0 Then IsDirEmpty = True End If End Function 'Test WScript.StdOut.WriteLine IsDirEmpty("C:\Temp") WScript.StdOut.WriteLine IsDirEmpty("C:\Temp\test")
<reponame>npocmaka/Windows-Server-2003 '//on error resume next intLimit = Null intThreshold = Null set objArgs = wscript.Arguments if objArgs.count < 3 then wscript.echo "Usage createVolumeUserQuota volume domain user [limit threshold]" wscript.quit(1) end if strVolume = Replace(objArgs(0), "\", "\\") strDomain = objArgs(1) strUser = objArgs(2) if objArgs.count > 3 then intLimit = objArgs(3) intThreshold = objArgs(4) end if '// Get the volume strQuery = "select * from Win32_Volume where Name = '" & strVolume & "'" set objSet = GetObject("winmgmts:").ExecQuery(strQuery) for each obj in objSet set Volume = obj exit for next wscript.echo "Volume: " & Volume.Name '// Get the account strQuery = "select * from Win32_Account where Domain = '" & strDomain & "' AND Name = '" & strUser & "'" set objSet = GetObject("winmgmts:").ExecQuery(strQuery) for each obj in objSet set Account = obj exit for next wscript.echo "Domain: " & Account.Domain & " Name: " & Account.Name set VolumeUserQuota = GetObject("winmgmts:Win32_VolumeUserQuota").SpawnInstance_ VolumeUserQuota.Volume = Volume.Path_.RelPath VolumeUserQuota.Account = Account.Path_.RelPath 'VolumeUserQuota.Account = "Win32_Account.Domain='BogusDomain',Name='BogusUser'" if isNull(intLimit) = False Then VolumeUserQuota.Limit = intLimit end if if isNull(intThreshold) = False Then VolumeUserQuota.WarningLimit = intThreshold end if VolumeUserQuota.Put_
'http://rosettacode.org/wiki/Middle_three_digits Function mid3n(n) 'Remove the number's sign. n = CStr(Abs(n)) If Len(n) < 3 Or Len(n) Mod 2 = 0 Then mid3n = "Invalid: Either the length of n < 3 or an even number." ElseIf Round(Len(n)/2) > Len(n)/2 Then mid3n = Mid(n,Round(Len(n)/2)-1,3) Else mid3n = Mid(n,Round(Len(n)/2),3) End If End Function 'Calling the function. arrn = Array(123,12345,1234567,987654321,10001,-10001,-123,-100,100,-12345,_ 1,2,-1,-10,2002,-2002,0) For Each n In arrn WScript.StdOut.Write n & ": " & mid3n(n) WScript.StdOut.WriteLine Next
Set objFSO = CreateObject("Scripting.FileSystemObject") Set infile = objFSO.OpenTextFile(objFSO.GetParentFolderName(WScript.ScriptFullName) & "\" &_ "unixdict.txt",1) list = "" length = 0 Do Until inFile.AtEndOfStream line = infile.ReadLine If IsOrdered(line) Then If Len(line) > length Then length = Len(line) list = line & vbCrLf ElseIf Len(line) = length Then list = list & line & vbCrLf End If End If Loop WScript.StdOut.Write list Function IsOrdered(word) IsOrdered = True prev_val = 0 For i = 1 To Len(word) If i = 1 Then prev_val = Asc(Mid(word,i,1)) ElseIf Asc(Mid(word,i,1)) >= prev_val Then prev_val = Asc(Mid(word,i,1)) Else IsOrdered = False Exit For End If Next End Function
<filename>net/unimodem/tools/src/notepad.frm<gh_stars>10-100 VERSION 5.00 Begin VB.Form frmNotePad Caption = "Untitled" ClientHeight = 3990 ClientLeft = 1515 ClientTop = 3315 ClientWidth = 5670 BeginProperty Font Name = "<NAME>" Size = 8.25 Charset = 0 Weight = 700 Underline = 0 'False Italic = 0 'False Strikethrough = 0 'False EndProperty LinkTopic = "Form1" ScaleHeight = 3990 ScaleMode = 0 'User ScaleWidth = 101.07 Begin VB.TextBox Text1 Height = 3975 HideSelection = 0 'False Left = 0 MultiLine = -1 'True ScrollBars = 2 'Vertical TabIndex = 0 Top = 0 Width = 5655 End Begin VB.Menu mnuFile Caption = "&File" Begin VB.Menu mnuFileNew Caption = "&New" End Begin VB.Menu mnuFileOpen Caption = "&Open..." End Begin VB.Menu mnuFileClose Caption = "&Close" End Begin VB.Menu mnuFileSave Caption = "&Save" End Begin VB.Menu mnuFileSaveAs Caption = "Save &As..." End Begin VB.Menu mnuFSep Caption = "-" End Begin VB.Menu mnuFileExit Caption = "E&xit" End Begin VB.Menu mnuRecentFile Caption = "-" Index = 0 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile1" Index = 1 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile2" Index = 2 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile3" Index = 3 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile4" Index = 4 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile5" Index = 5 Visible = 0 'False End End Begin VB.Menu mnuEdit Caption = "&Edit" Begin VB.Menu mnuEditCut Caption = "Cu&t" Shortcut = ^X End Begin VB.Menu mnuEditCopy Caption = "&Copy" Shortcut = ^C End Begin VB.Menu mnuEditPaste Caption = "&Paste" Shortcut = ^V End Begin VB.Menu mnuEditDelete Caption = "De&lete" Shortcut = {DEL} End Begin VB.Menu mnuESep1 Caption = "-" End Begin VB.Menu mnuEditSelectAll Caption = "Select &All" End Begin VB.Menu mnuEditTime Caption = "Time/&Date" End End Begin VB.Menu mnuSearch Caption = "&Search" Begin VB.Menu mnuSearchFind Caption = "&Find" End Begin VB.Menu mnuSearchFindNext Caption = "Find &Next" Shortcut = {F3} End End Begin VB.Menu mnuOptions Caption = "&Options" Begin VB.Menu mnuFont Caption = "&Font" Begin VB.Menu mnuFontName Caption = "FontName" Index = 0 End End End End Attribute VB_Name = "frmNotePad" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False '* Child form for the MDI Notepad sample application * '********************************************************** Option Explicit Private Sub Form_Load() Dim i As Integer ' Counter variable. ' Assign the name of the first font to a font ' menu entry, then loop through the fonts ' collection, adding them to the menu mnuFontName(0).Caption = Screen.Fonts(0) For i = 1 To Screen.FontCount - 1 Load mnuFontName(i) mnuFontName(0).Caption = Screen.Fonts(i) Next End Sub Private Sub Form_QueryUnload(Cancel As Integer, UnloadMode As Integer) Dim strMsg As String Dim strFilename As String Dim intResponse As Integer ' Check to see if the text has been changed. If FState(Me.Tag).Dirty Then strFilename = Me.Caption strMsg = "The text in [" & strFilename & "] has changed." strMsg = strMsg & vbCrLf strMsg = strMsg & "Do you want to save the changes?" intResponse = MsgBox(strMsg, 51, fMainForm.Caption) Select Case intResponse Case 6 ' User chose Yes. If Left(Me.Caption, 8) = "Untitled" Then ' The file hasn't been saved yet. strFilename = "untitled.txt" ' Get the strFilename, and then call the save procedure, GetstrFilename. strFilename = GetFileName(strFilename) Else ' The form's Caption contains the name of the open file. strFilename = Me.Caption End If ' Call the save procedure. If strFilename = Empty, then ' the user chose Cancel in the Save As dialog box; otherwise, ' save the file. If strFilename <> "" Then SaveFileAs strFilename End If Case 7 ' User chose No. Unload the file. Cancel = False Case 2 ' User chose Cancel. Cancel the unload. Cancel = True End Select End If End Sub Private Sub Form_Resize() ' Expand text box to fill the current child form's internal area. Text1.Height = ScaleHeight Text1.Width = ScaleWidth End Sub Private Sub Form_Unload(Cancel As Integer) ' Show the current form instance as deleted FState(Me.Tag).Deleted = True ' Hide the toolbar edit buttons if no notepad windows exist. If Not AnyPadsLeft() Then fMainForm.imgCutButton.Visible = False fMainForm.imgCopyButton.Visible = False fMainForm.imgPasteButton.Visible = False ' Toggle the public tool state variable gToolsHidden = True ' Call the recent file list procedure GetRecentFiles End If End Sub Private Sub mnuEditCopy_Click() ' Call the copy procedure EditCopyProc End Sub Private Sub mnuEditCut_Click() ' Call the cut procedure EditCutProc End Sub Private Sub mnuEditDelete_Click() ' If the mouse pointer is not at the end of the notepad... If Screen.ActiveControl.SelStart <> Len(Screen.ActiveControl.Text) Then ' If nothing is selected, extend the selection by one. If Screen.ActiveControl.SelLength = 0 Then Screen.ActiveControl.SelLength = 1 ' If the mouse pointer is on a blank line, extend the selection by two. If Asc(Screen.ActiveControl.SelText) = 13 Then Screen.ActiveControl.SelLength = 2 End If End If ' Delete the selected text. Screen.ActiveControl.SelText = "" End If End Sub Private Sub mnuEditPaste_Click() ' Call the paste procedure. EditPasteProc End Sub Private Sub mnuEditSelectAll_Click() ' Use SelStart & SelLength to select the text. fMainForm.ActiveForm.Text1.SelStart = 0 fMainForm.ActiveForm.Text1.SelLength = Len(fMainForm.ActiveForm.Text1.Text) End Sub Private Sub mnuEditTime_Click() ' Insert the current time and date. Text1.SelText = Now End Sub Private Sub mnuFileClose_Click() ' Unload this form. Unload Me End Sub Private Sub mnuFileExit_Click() ' Unloading the MDI form invokes the QueryUnload event ' for each child form, and then the MDI form. ' Setting the Cancel argument to True in any of the ' QueryUnload events cancels the unload. Unload fMainForm End Sub Private Sub mnuFileNew_Click() ' Call the new form procedure FileNew End Sub Private Sub mnuFontName_Click(index As Integer) ' Assign the selected font to the textbox fontname property. Text1.FontName = mnuFontName(index).Caption End Sub Private Sub mnuFileOpen_Click() ' Call the file open procedure. FileOpenProc End Sub Private Sub mnuFileSave_Click() Dim strFilename As String If Left(Me.Caption, 8) = "Untitled" Then ' The file hasn't been saved yet. ' Get the filename, and then call the save procedure, GetFileName. strFilename = GetFileName(strFilename) Else ' The form's Caption contains the name of the open file. strFilename = Me.Caption End If ' Call the save procedure. If Filename = Empty, then ' the user chose Cancel in the Save As dialog box; otherwise, ' save the file. If strFilename <> "" Then SaveFileAs strFilename End If End Sub Private Sub mnuFileSaveAs_Click() Dim strSaveFileName As String Dim strDefaultName As String ' Assign the form caption to the variable. strDefaultName = Me.Caption If Left(Me.Caption, 8) = "Untitled" Then ' The file hasn't been saved yet. ' Get the filename, and then call the save procedure, strSaveFileName. strSaveFileName = GetFileName("Untitled.txt") If strSaveFileName <> "" Then SaveFileAs (strSaveFileName) ' Update the list of recently opened files in the File menu control array. UpdateFileMenu (strSaveFileName) Else ' The form's Caption contains the name of the open file. strSaveFileName = GetFileName(strDefaultName) If strSaveFileName <> "" Then SaveFileAs (strSaveFileName) ' Update the list of recently opened files in the File menu control array. UpdateFileMenu (strSaveFileName) End If End Sub Private Sub mnuOptions_Click() ' Toggle the Checked property to match the .Visible property. ' mnuOptionsToolbar.Checked = fMainForm.picToolbar.Visible End Sub Private Sub mnuOptionsToolbar_Click() ' Call the toolbar procedure, passing a reference ' to this form instance. OptionsToolbarProc Me End Sub Private Sub mnuRecentFile_Click(index As Integer) ' Call the file open procedure, passing a ' reference to the selected file name OpenFile (mnuRecentFile(index).Caption) ' Update the list of recently opened files in the File menu control array. GetRecentFiles End Sub Private Sub mnuSearchFind_Click() ' If there is text in the textbox, assign it to ' the textbox on the Find form, otherwise assign ' the last findtext value. If Me.Text1.SelText <> "" Then frmFind.Text1.Text = Me.Text1.SelText Else frmFind.Text1.Text = gFindString End If ' Set the public variable to start at the beginning. gFirstTime = True ' Set the case checkbox to match the public variable If (gFindCase) Then frmFind.chkCase = 1 End If ' Display the Find form. frmFind.Show vbModal End Sub Private Sub mnuSearchFindNext_Click() ' If the public variable isn't empty, call the ' find procedure, otherwise call the find menu If Len(gFindString) > 0 Then FindIt Else mnuSearchFind_Click End If End Sub Private Sub mnuWindowArrange_Click() ' Arrange the icons for any minimzied child forms. fMainForm.Arrange vbArrangeIcons End Sub Private Sub mnuWindowCascade_Click() ' Cascade the child forms. fMainForm.Arrange vbCascade End Sub Private Sub mnuWindowTile_Click() ' Tile the child forms. fMainForm.Arrange vbTileHorizontal End Sub Private Sub Text1_Change() ' Set the public variable to show that text has changed. FState(Me.Tag).Dirty = True End Sub
110 IF 12 > 11 THEN PRINT "ok1" 120 IF 12 < 11 THEN PRINT "fail1" 130 IF 12 < 11 THEN PRINT "fail2" 140 IF 12 > 11 THEN PRINT "ok2"
<filename>admin/pchealth/upload/client/uploadmanager/unittest/test3_deletealljobs.vbs 'Stop Set obj = CreateObject( "UploadManager.MPCUpload" ) For Each job In obj wscript.echo job.jobID job.Delete Next
<reponame>LaudateCorpus1/RosettaCodeData ' Read a file line by line Sub Main() Dim fInput As String, fOutput As String 'File names Dim sInput As String, sOutput As String 'Lines fInput = "input.txt" fOutput = "output.txt" Open fInput For Input As #1 Open fOutput For Output As #2 While Not EOF(1) Line Input #1, sInput sOutput = Process(sInput) 'do something Print #2, sOutput Wend Close #1 Close #2 End Sub 'Main
VERSION 5.00 Begin VB.Form frmMain BorderStyle = 1 'Fixed Single Caption = "SDK BVT ( wbem 494 : opal > 1035 )" ClientHeight = 3660 ClientLeft = 45 ClientTop = 330 ClientWidth = 6630 Icon = "frmMain.frx":0000 LinkTopic = "Form1" MaxButton = 0 'False ScaleHeight = 3660 ScaleWidth = 6630 StartUpPosition = 3 'Windows Default Begin VB.CommandButton cmdModInfo Caption = "Module &Info >" Height = 375 Left = 1860 TabIndex = 22 Top = 2160 Width = 1335 End Begin VB.Frame fraLoop Caption = "&Looping" Height = 1635 Left = 60 TabIndex = 14 Top = 1980 Width = 1635 Begin VB.OptionButton rdoLoopInf Caption = "Infinite" Height = 195 Left = 180 TabIndex = 23 Top = 540 Width = 1035 End Begin VB.TextBox txtLoop BackColor = &H8000000F& Enabled = 0 'False Height = 285 Left = 240 TabIndex = 18 Top = 1260 Width = 1275 End Begin VB.OptionButton rdoLoopIter Caption = "Iterations" Height = 195 Left = 180 TabIndex = 17 Top = 1020 Width = 1095 End Begin VB.OptionButton rdoLoopMin Caption = "Minutes" Enabled = 0 'False Height = 195 Left = 180 TabIndex = 16 Top = 780 Width = 1035 End Begin VB.OptionButton rdoLoopDis Caption = "Disabled" Height = 195 Left = 180 TabIndex = 15 Top = 300 Value = -1 'True Width = 975 End End Begin VB.CommandButton cmdGo Default = -1 'True Height = 915 Left = 1860 Picture = "frmMain.frx":0442 Style = 1 'Graphical TabIndex = 21 Top = 2640 Width = 1335 End Begin VB.Frame fraModules Caption = "&Modules" Height = 3555 Left = 3360 TabIndex = 19 Top = 60 Width = 3195 Begin VB.ListBox lstModules Height = 3195 IntegralHeight = 0 'False Left = 120 Style = 1 'Checkbox TabIndex = 20 Top = 240 Width = 2955 End End Begin VB.Frame fraConfig Caption = "&Configuration" Height = 1875 Left = 60 TabIndex = 0 Top = 60 Width = 3195 Begin VB.CheckBox chkAuthority Caption = "Null" Height = 195 Left = 960 TabIndex = 12 Top = 1500 Value = 1 'Checked Width = 615 End Begin VB.CheckBox chkPassword Caption = "Null" Height = 195 Left = 960 TabIndex = 9 Top = 1200 Value = 1 'Checked Width = 615 End Begin VB.CheckBox chkUserid Caption = "Null" Height = 195 Left = 960 TabIndex = 6 Top = 900 Value = 1 'Checked Width = 615 End Begin VB.TextBox txtAuthority BackColor = &H8000000F& Enabled = 0 'False Height = 285 Left = 1560 TabIndex = 13 Top = 1440 Width = 1515 End Begin VB.TextBox txtPassword BackColor = &H8000000F& Enabled = 0 'False Height = 285 IMEMode = 3 'DISABLE Left = 1560 PasswordChar = "" TabIndex = 10 Top = 1140 Width = 1515 End Begin VB.TextBox txtUserid BackColor = &H8000000F& Enabled = 0 'False Height = 285 Left = 1560 TabIndex = 7 Top = 840 Width = 1515 End Begin VB.TextBox txtServer Height = 285 Left = 1560 TabIndex = 2 Top = 240 Width = 1515 End Begin VB.TextBox txtSitecode Height = 285 Left = 1560 MaxLength = 3 TabIndex = 4 Top = 540 Width = 1515 End Begin VB.Label lblAuthority AutoSize = -1 'True Caption = "Authority:" Height = 195 Left = 120 TabIndex = 11 Top = 1500 Width = 660 End Begin VB.Label lblPassword AutoSize = -1 'True Caption = "Password:" Height = 195 Left = 120 TabIndex = 8 Top = 1200 Width = 735 End Begin VB.Label lblUserid AutoSize = -1 'True Caption = "UserID:" Height = 195 Left = 120 TabIndex = 5 Top = 900 Width = 540 End Begin VB.Label lblServer AutoSize = -1 'True Caption = "Provider Machine:" Height = 195 Left = 120 TabIndex = 1 Top = 300 Width = 1290 End Begin VB.Label lblSitecode AutoSize = -1 'True Caption = "Site code:" Height = 195 Left = 120 TabIndex = 3 Top = 600 Width = 720 End End End Attribute VB_Name = "frmMain" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Public canceled As Boolean Private Sub Form_Load() canceled = False InstallModules lstModules.ListIndex = -1 End Sub Private Sub chkAuthority_Click() If chkAuthority.Value = 0 Then txtAuthority.Enabled = True txtAuthority.BackColor = &H80000005 txtAuthority.SetFocus Else txtAuthority.Enabled = False txtAuthority.BackColor = &H8000000F End If End Sub Private Sub chkPassword_Click() If chkPassword.Value = 0 Then txtPassword.Enabled = True txtPassword.BackColor = &H80000005 txtPassword.SetFocus Else txtPassword.Enabled = False txtPassword.BackColor = &H8000000F End If End Sub Private Sub chkUserid_Click() If chkUserid.Value = 0 Then txtUserid.Enabled = True txtUserid.BackColor = &H80000005 txtUserid.SetFocus Else txtUserid.Enabled = False txtUserid.BackColor = &H8000000F End If End Sub Private Sub cmdGo_Click() Open "\bvtlog.txt" For Output As #1 Print #1, "* BVT Started **" & vbCrLf & vbCrLf Close #1 If rdoLoopDis.Value Then frmTest.Run ElseIf rdoLoopInf.Value Then Do frmTest.Run Dim f As New frmPause f.Show 1 If canceled Then canceled = False Exit Do End If Loop ElseIf rdoLoopMin.Value Then ElseIf rdoLoopIter.Value Then Dim i As Integer For i = 1 To val(txtLoop.text) frmTest.Run Dim g As New frmPause g.Show 1 If canceled Then canceled = False Exit For End If Next i End If End Sub Private Sub cmdModInfo_Click() If lstModules.ListIndex >= 0 Then Dim s As String s = Modules(lstModules.List(lstModules.ListIndex)).GetModuleInfo Dim f As New frmObjText f.Caption = "Module info for: " & lstModules.List(lstModules.ListIndex) f.txtMain.text = s f.Show End If End Sub Private Sub InstallModules() Modules.Add New SoftDist, "Software Distribution" Modules.Add New SiteCtrl, "Site Control File" Modules.Add New Methods, "Methods" Modules.Add New Queries, "Queries" Modules.Add New PDF, "Package Definition Files" End Sub Private Sub rdoLoopDis_Click() txtLoop.Enabled = False txtLoop.BackColor = &H8000000F End Sub Private Sub rdoLoopInf_Click() txtLoop.Enabled = False txtLoop.BackColor = &H8000000F End Sub Private Sub rdoLoopIter_Click() txtLoop.Enabled = True txtLoop.BackColor = &H80000005 End Sub Private Sub rdoLoopMin_Click() txtLoop.Enabled = True txtLoop.BackColor = &H80000005 End Sub
<reponame>wtywtykk/STM32Framework_SaltyProject<gh_stars>1-10 Attribute VB_Name = "ModBitOp" Option Explicit Public Declare Function SHL8 Lib "BitOp.dll" (ByVal Val As Byte, ByVal Shift As Long) As Byte Public Declare Function SHR8 Lib "BitOp.dll" (ByVal Val As Byte, ByVal Shift As Long) As Byte Public Declare Function SHL16 Lib "BitOp.dll" (ByVal Val As Integer, ByVal Shift As Long) As Integer Public Declare Function SHR16 Lib "BitOp.dll" (ByVal Val As Integer, ByVal Shift As Long) As Integer Public Declare Function SHL32 Lib "BitOp.dll" (ByVal Val As Long, ByVal Shift As Long) As Long Public Declare Function SHR32 Lib "BitOp.dll" (ByVal Val As Long, ByVal Shift As Long) As Long Public Declare Function GetU16U8 Lib "BitOp.dll" (ByVal Val As Integer, ByVal Index As Long) As Byte Public Declare Function SetU16U8 Lib "BitOp.dll" (ByVal Val16 As Integer, ByVal Val8 As Byte, ByVal Index As Long) As Integer Public Declare Function GetU32U8 Lib "BitOp.dll" (ByVal Val As Long, ByVal Index As Long) As Byte Public Declare Function SetU32U8 Lib "BitOp.dll" (ByVal Val32 As Long, ByVal Val8 As Byte, ByVal Index As Long) As Long Public Declare Function GetU32U16 Lib "BitOp.dll" (ByVal Val As Long, ByVal Index As Long) As Integer Public Declare Function SetU32U16 Lib "BitOp.dll" (ByVal Val32 As Long, ByVal Val16 As Integer, ByVal Index As Long) As Long Public Declare Function SwitchU16Edition Lib "BitOp.dll" (ByVal Val As Integer) As Integer Public Declare Function SwitchU32Edition Lib "BitOp.dll" (ByVal Val As Long) As Long Public Declare Function CheckU8Bit Lib "BitOp.dll" (ByVal Val As Byte, ByVal Index As Long) As Boolean Public Declare Function CheckU16Bit Lib "BitOp.dll" (ByVal Val As Integer, ByVal Index As Long) As Boolean Public Declare Function CheckU32Bit Lib "BitOp.dll" (ByVal Val As Long, ByVal Index As Long) As Boolean Public Declare Function U8Add Lib "BitOp.dll" (ByVal Val1 As Byte, ByVal Val2 As Byte) As Byte Public Declare Function U8Sub Lib "BitOp.dll" (ByVal Val1 As Byte, ByVal Val2 As Byte) As Byte Public Declare Function U8Cmp Lib "BitOp.dll" (ByVal Val1 As Byte, ByVal Val2 As Byte) As Long Public Declare Function U16Add Lib "BitOp.dll" (ByVal Val1 As Integer, ByVal Val2 As Integer) As Integer Public Declare Function U16Sub Lib "BitOp.dll" (ByVal Val1 As Integer, ByVal Val2 As Integer) As Integer Public Declare Function U16Cmp Lib "BitOp.dll" (ByVal Val1 As Integer, ByVal Val2 As Integer) As Long Public Declare Function U32Add Lib "BitOp.dll" (ByVal Val1 As Long, ByVal Val2 As Long) As Long Public Declare Function U32Sub Lib "BitOp.dll" (ByVal Val1 As Long, ByVal Val2 As Long) As Long Public Declare Function U32Cmp Lib "BitOp.dll" (ByVal Val1 As Long, ByVal Val2 As Long) As Long Public Function GetRGB(ByVal Color As Long) As Byte() Dim Result(3) As Byte Result(0) = GetU32U8(Color, 0) 'R Result(1) = GetU32U8(Color, 1) 'G Result(2) = GetU32U8(Color, 2) 'B Result(3) = GetU32U8(Color, 3) 'A GetRGB = Result() End Function
Option Base 1 Private Function norm(q As Variant) As Double norm = Sqr(WorksheetFunction.SumSq(q)) End Function Private Function negative(q) As Variant Dim res(4) As Double For i = 1 To 4 res(i) = -q(i) Next i negative = res End Function Private Function conj(q As Variant) As Variant Dim res(4) As Double res(1) = q(1) For i = 2 To 4 res(i) = -q(i) Next i conj = res End Function Private Function addr(r As Double, q As Variant) As Variant Dim res As Variant res = q res(1) = r + q(1) addr = res End Function Private Function add(q1 As Variant, q2 As Variant) As Variant add = WorksheetFunction.MMult(Array(1, 1), Array(q1, q2)) End Function Private Function multr(r As Double, q As Variant) As Variant multr = WorksheetFunction.MMult(r, q) End Function Private Function mult(q1 As Variant, q2 As Variant) Dim res(4) As Double res(1) = q1(1) * q2(1) - q1(2) * q2(2) - q1(3) * q2(3) - q1(4) * q2(4) res(2) = q1(1) * q2(2) + q1(2) * q2(1) + q1(3) * q2(4) - q1(4) * q2(3) res(3) = q1(1) * q2(3) - q1(2) * q2(4) + q1(3) * q2(1) + q1(4) * q2(2) res(4) = q1(1) * q2(4) + q1(2) * q2(3) - q1(3) * q2(2) + q1(4) * q2(1) mult = res End Function Private Sub quats(q As Variant) Debug.Print q(1); IIf(q(2) < 0, " - " & Abs(q(2)), " + " & q(2)); Debug.Print IIf(q(3) < 0, "i - " & Abs(q(3)), "i + " & q(3)); Debug.Print IIf(q(4) < 0, "j - " & Abs(q(4)), "j + " & q(4)); "k" End Sub Public Sub quaternions() q = [{ 1, 2, 3, 4}] q1 = [{2, 3, 4, 5}] q2 = [{3, 4, 5, 6}] Dim r_ As Double r_ = 7# Debug.Print "q = ";: quats q Debug.Print "q1 = ";: quats q1 Debug.Print "q2 = ";: quats q2 Debug.Print "r = "; r_ Debug.Print "norm(q) = "; norm(q) Debug.Print "negative(q) = ";: quats negative(q) Debug.Print "conjugate(q) = ";: quats conj(q) Debug.Print "r + q = ";: quats addr(r_, q) Debug.Print "q1 + q2 = ";: quats add(q1, q2) Debug.Print "q * r = ";: quats multr(r_, q) Debug.Print "q1 * q2 = ";: quats mult(q1, q2) Debug.Print "q2 * q1 = ";: quats mult(q2, q1) End Sub
Sub Demo() Dim arr arr = Array(1, 2, 3, 4, 5, 6, 7, 8, 9, 10) Debug.Print "sum : " & Application.WorksheetFunction.Sum(arr) Debug.Print "product : " & Application.WorksheetFunction.Product(arr) End Sub
Dim tihead As TreeItem Private Function Add(v As Integer, left As TreeItem, right As TreeItem) As TreeItem Dim x As New TreeItem x.Value = v Set x.LeftChild = left Set x.RightChild = right Set Add = x End Function Private Sub Init() Set tihead = Add(1, _ Add(2, _ Add(4, _ Add(7, Nothing, Nothing), _ Nothing), _ Add(5, Nothing, Nothing)), _ Add(3, _ Add(6, _ Add(8, Nothing, Nothing), _ Add(9, Nothing, Nothing)), _ Nothing)) End Sub Private Sub InOrder(ti As TreeItem) If Not ti Is Nothing Then Call InOrder(ti.LeftChild) Debug.Print ti.Value; Call InOrder(ti.RightChild) End If End Sub Private Sub PreOrder(ti As TreeItem) If Not ti Is Nothing Then Debug.Print ti.Value; Call PreOrder(ti.LeftChild) Call PreOrder(ti.RightChild) End If End Sub Private Sub PostOrder(ti As TreeItem) If Not ti Is Nothing Then Call PostOrder(ti.LeftChild) Call PostOrder(ti.RightChild) Debug.Print ti.Value; End If End Sub Private Sub LevelOrder(ti As TreeItem) Dim queue As Object Set queue = CreateObject("System.Collections.Queue") queue.Enqueue ti Do While (queue.Count > 0) Set next_ = queue.Dequeue Debug.Print next_.Value; If Not next_.LeftChild Is Nothing Then queue.Enqueue next_.LeftChild If Not next_.RightChild Is Nothing Then queue.Enqueue next_.RightChild Loop End Sub Public Sub Main() Init Debug.Print "preorder: "; Call PreOrder(tihead) Debug.Print vbCrLf; "inorder: "; Call InOrder(tihead) Debug.Print vbCrLf; "postorder: "; Call PostOrder(tihead) Debug.Print vbCrLf; "level-order: "; Call LevelOrder(tihead) End Sub
<reponame>npocmaka/Windows-Server-2003 ' Copy the Terminal Services ActiveX control since we don't build it, but need it for private builds strReleasePath = "\\dsys-rel-fre\release\usa" strCabFile = "msrdp.cab" Set fileSystem = CreateObject ("Scripting.FileSystemObject") Set releaseFolder = fileSystem.GetFolder(strReleasePath) 'Get the directory for the latest build 'This gets the latest build directory assuming the folders are listed alphabetically Set subFolders = releaseFolder.SubFolders For Each subFolder in subFolders name = subFolder.Name If InStr(1, name, "x86fre") Then strBuild = name End If Next strReleasePath = strReleasePath & "\" & strBuild & "\" Set WshShell = CreateObject("WScript.Shell") strPostBuildDir = WshShell.ExpandEnvironmentStrings("%_NTPOSTBLD%") 'For some reason, I get an Access Denied message if I try to copy the file programmatically, 'so I create a batch file to copy the cab If fileSystem.FileExists(strReleasePath & strCabFile) Then Set batchFile = fileSystem.CreateTextFile("CopyMsrdp.bat", True) batchFile.WriteLine("copy " & strReleasePath & strCabFile & " " & strPostBuildDir) batchFile.Close Else wscript.echo "File does NOT Exist: " & strReleasePath & strCabFile End If
Public Sub foodemo() 'declare and create separately Dim f As Foo Dim f0 As Foo Set f = New Foo 'set property f.Bar = 25 'call method f.DoubleBar 'alternative Call f.DoubleBar Debug.Print "f.Bar is "; f.Bar Debug.Print "Five times f.Bar is "; f.MultiplyBar(5) 'declare and create at the same time Dim f2 As New Foo Debug.Print "f2.Bar is "; f2.Bar 'prints default value 'destroy an object Set f = Nothing 'create an object or not, depending on a random number: If Rnd() < 0.5 Then Set f0 = New Foo End If 'check if object actually exists If f0 Is Nothing Then Debug.Print "object f0 does not exist" Else Debug.Print "object f0 was created" End If 'at the end of execution all remaining objects created in this sub will be released. 'this will trigger one or two "object destroyed" messages 'depending on whether f0 was created... End Sub
' docopy.vbs ' This script (re)calculates the build number, creates a directory on the target machine ' with that build number as a directory name, then copies all the files identified in the ' filecopy.dat file to the destinations noted there. BUILDDEST = "\\b11nlbuilds\sapi5" BUILDER = "spgbld" BUILDMAIL = "spgmake" on error resume next ' VerifyPath takes the destination from the filecopy.dat, as modified to include BUILDDEST ' and the build number, and looks to see if the destination actually exists. It starts from ' the root of the name, BUILDDEST, and checks at each node to see if that folder exists; if ' not, it creates that folder, then continues down the destination name. sub VerifyPath(pathname) if right(pathname,1) <> "\" then 'strip off filename, if any beginfname = InStrRev(pathname, "\") pathname = left(pathname,len(pathname) - beginfname) end if lasttry = instr(pathname, BUILDDEST) + len(BUILDDEST) ' offset for known directory do while lasttry < (len(pathname) - 1) ptr = InStr(lasttry + 2, pathname, "\") - 1 'end of path component trial = left(pathname, ptr) if not fso.FolderExists(trial) then fso.CreateFolder(trial) end if lasttry = ptr loop end sub set wso = CreateObject("WScript.Shell") USER = wso.ExpandEnvironmentStrings("%USERNAME%") SAPIROOT = wso.ExpandEnvironmentStrings("%SAPIROOT%") ' The following if..then ensures that only the official builder will do ' the copy functions through the buildall command file. If the username ' in the environment is not that of the official builder, the loop will ' not be executed. if USER = BUILDER then set fso = CreateObject("Scripting.FileSystemObject") ' The following retrieves the build number from the ' currver.inc file that is generated by the build process set verfile = fso.GetFile(SAPIROOT & "\build\currver.inc") set fstream = verfile.OpenAsTextStream do while fstream.AtEndOfStream <> True linein = fstream.ReadLine if left(linein, 15) = "#define VERSION" then BuildNum = left(right(linein, 5), 4) end if loop fstream.Close() ' Now read the data file to find out which files to copy and ' where to put them. set file = fso.GetFile(SAPIROOT & "\builder\filecopy.dat") set fstream = file.OpenAsTextStream do while fstream.AtEndOfStream <> True linein = fstream.ReadLine if left(linein, 1) <> "#" then fromto = split(linein, ",") filefrom = SAPIROOT & "\" & trim(fromto(0)) fileto = BUILDDEST & "\" & BuildNum & "\" & trim(fromto(1)) VerifyPath(fileto) fso.CopyFile filefrom, fileto if err.number <> 0 then wscript.echo "Error: " & err.description & ": copying " & filefrom & " to " & fileto err.clear end if end if loop fstream.Close() ' Now an xcopy to get all the source & pdbs wso.Run("xcopy /s /i " & SAPIROOT & "\src\.cpp " & BUILDDEST & "\" & BuildNum & "\src") wso.Run("xcopy /s /i " & SAPIROOT & "\src\.h " & BUILDDEST & "\" & BuildNum & "\src") wso.Run("xcopy /s /i " & SAPIROOT & "\src\.pdb " & BUILDDEST & "\" & BuildNum & "\src") wso.Run("xcopy /s /i " & SAPIROOT & "\QA\.cpp " & BUILDDEST & "\" & BuildNum & "\src\QA") wso.Run("xcopy /s /i " & SAPIROOT & "\QA\.h " & BUILDDEST & "\" & BuildNum & "\src\QA") wso.Run("xcopy /s /i " & SAPIROOT & "\QA\.pdb " & BUILDDEST & "\" & BuildNum & "\src\QA") ' Clean up attributes on copied files wso.Run("attrib -r -h " & BUILDDEST & "\" & BuildNum & " /s") ' Get rid of slm.ini files from copied files wso.Run("del /s " & BUILDDEST & "\" & BuildNum & "\slm.ini") else permstring = "You are not the official builder, therefore your build " permstring = permstring & "will not be copied to the build repository. Please look " permstring = permstring & "for your result binaries in the appropriate directories." msgbox permstring, , "SPG Build Process" end if
<filename>admin/darwin/src/msitools/scripts/widiffdb.vbs ' Windows Installer utility to report the differences between two databases ' For use with Windows Scripting Host, CScript.exe only, lists to stdout ' Copyright (c) Microsoft Corporation. All rights reserved. ' Simply generates a transform between the databases and then view the transform ' Option Explicit Const icdLong = 0 Const icdShort = &h400 Const icdObject = &h800 Const icdString = &hC00 Const icdNullable = &h1000 Const icdPrimaryKey = &h2000 Const icdNoNulls = &h0000 Const icdPersistent = &h0100 Const icdTemporary = &h0000 Const msiOpenDatabaseModeReadOnly = 0 Const msiOpenDatabaseModeTransact = 1 Const msiOpenDatabaseModeCreate = 3 Const iteViewTransform = 256 If Wscript.Arguments.Count < 2 Then Wscript.Echo "Windows Installer database difference utility" &_ vbNewLine & " Generates a temporary transform file, then display it" &_ vbNewLine & " 1st argument is the path to the original installer database" &_ vbNewLine & " 2nd argument is the path to the updated installer database" &_ vbNewLine &_ vbNewLine & "Copyright (C) Microsoft Corporation. All rights reserved." Wscript.Quit 1 End If ' Cannot run with GUI script host, as listing is performed to standard out If UCase(Mid(Wscript.FullName, Len(Wscript.Path) + 2, 1)) = "W" Then WScript.Echo "Cannot use WScript.exe - must use CScript.exe with this program" Wscript.Quit 2 End If ' Connect to Windows Installer object On Error Resume Next Dim installer : Set installer = Nothing Set installer = Wscript.CreateObject("WindowsInstaller.Installer") : CheckError ' Create path for temporary transform file Dim WshShell : Set WshShell = Wscript.CreateObject("Wscript.Shell") : CheckError Dim tempFilePath:tempFilePath = WshShell.ExpandEnvironmentStrings("%TEMP%") & "\diff.tmp" ' Open databases, generate transform, then list transform Dim database1 : Set database1 = installer.OpenDatabase(Wscript.Arguments(0), msiOpenDatabaseModeReadOnly) : CheckError Dim database2 : Set database2 = installer.OpenDatabase(Wscript.Arguments(1), msiOpenDatabaseModeReadOnly) : CheckError Dim different : different = Database2.GenerateTransform(Database1, tempFilePath) : CheckError If different Then database1.ApplyTransform tempFilePath, iteViewTransform + 0 : CheckError' should not need error suppression flags ListTransform database1 End If ' Open summary information streams and compare them Dim sumInfo1 : Set sumInfo1 = database1.SummaryInformation(0) : CheckError Dim sumInfo2 : Set sumInfo2 = database2.SummaryInformation(0) : CheckError Dim iProp, value1, value2 For iProp = 1 to 19 value1 = sumInfo1.Property(iProp) : CheckError value2 = sumInfo2.Property(iProp) : CheckError If value1 <> value2 Then Wscript.Echo "\005SummaryInformation [" & iProp & "] {" & value1 & "}->{" & value2 & "}" different = True End If Next If Not different Then Wscript.Echo "Databases are identical" Wscript.Quit 0 Function DecodeColDef(colDef) Dim def Select Case colDef AND (icdShort OR icdObject) Case icdLong def = "LONG" Case icdShort def = "SHORT" Case icdObject def = "OBJECT" Case icdString def = "CHAR(" & (colDef AND 255) & ")" End Select If (colDef AND icdNullable) = 0 Then def = def & " NOT NULL" If (colDef AND icdPrimaryKey) <> 0 Then def = def & " PRIMARY KEY" DecodeColDef = def End Function Sub ListTransform(database) Dim view, record, row, column, change On Error Resume Next Set view = database.OpenView("SELECT * FROM `_TransformView` ORDER BY `Table`, `Row`") If Err <> 0 Then Wscript.Echo "Transform viewing supported only in builds 4906 and beyond of MSI.DLL" : Wscript.Quit 2 view.Execute : CheckError Do Set record = view.Fetch : CheckError If record Is Nothing Then Exit Do change = Empty If record.IsNull(3) Then row = "<DDL>" If NOT record.IsNull(4) Then change = "[" & record.StringData(5) & "]: " & DecodeColDef(record.StringData(4)) Else row = "[" & Join(Split(record.StringData(3), vbTab, -1), ",") & "]" If record.StringData(2) <> "INSERT" AND record.StringData(2) <> "DELETE" Then change = "{" & record.StringData(5) & "}->{" & record.StringData(4) & "}" End If column = record.StringData(1) & " " & record.StringData(2) if Len(column) < 24 Then column = column & Space(24 - Len(column)) WScript.Echo column, row, change Loop End Sub Sub CheckError Dim message, errRec If Err = 0 Then Exit Sub message = Err.Source & " " & Hex(Err) & ": " & Err.Description If Not installer Is Nothing Then Set errRec = installer.LastErrorRecord If Not errRec Is Nothing Then message = message & vbNewLine & errRec.FormatText End If Wscript.Echo message Wscript.Quit 2 End Sub
VERSION 5.00 Object = "{F9043C88-F6F2-101A-A3C9-08002B2F49FB}#1.2#0"; "COMDLG32.OCX" Begin VB.Form frmMain Caption = "MiscFixes" ClientHeight = 6825 ClientLeft = 270 ClientTop = 450 ClientWidth = 9390 LinkTopic = "Form1" ScaleHeight = 6825 ScaleWidth = 9390 StartUpPosition = 3 'Windows Default Begin VB.CheckBox chkPopulate Caption = "&Populate Help Image" Height = 255 Left = 120 TabIndex = 12 Top = 1560 Width = 1935 End Begin VB.TextBox txtOutput Height = 4335 Left = 120 MultiLine = -1 'True ScrollBars = 3 'Both TabIndex = 15 Top = 2400 Width = 9135 End Begin VB.CommandButton cmdClose Caption = "Close" Height = 375 Left = 8400 TabIndex = 14 Top = 1920 Width = 855 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 3 Left = 8880 TabIndex = 11 Top = 1200 Width = 375 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 2 Left = 8880 TabIndex = 8 Top = 840 Width = 375 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 1 Left = 8880 TabIndex = 5 Top = 480 Width = 375 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 0 Left = 8880 TabIndex = 2 Top = 120 Width = 375 End Begin MSComDlg.CommonDialog dlgCommon Left = 2040 Top = 1560 _ExtentX = 847 _ExtentY = 847 _Version = 393216 End Begin VB.TextBox txtIn Height = 285 Index = 3 Left = 1200 TabIndex = 10 Top = 1200 Width = 7575 End Begin VB.TextBox txtIn Height = 285 Index = 1 Left = 1200 TabIndex = 4 Top = 480 Width = 7575 End Begin VB.CommandButton cmdGo Caption = "Go" Height = 375 Left = 7440 TabIndex = 13 Top = 1920 Width = 855 End Begin VB.TextBox txtIn Height = 285 Index = 2 Left = 1200 TabIndex = 7 Top = 840 Width = 7575 End Begin VB.TextBox txtIn Height = 285 Index = 0 Left = 1200 TabIndex = 1 Top = 120 Width = 7575 End Begin VB.Label lbl Caption = "HH&T To Add" Height = 255 Index = 3 Left = 120 TabIndex = 9 Top = 1200 Width = 1095 End Begin VB.Label lbl Caption = "&Output CAB" Height = 255 Index = 1 Left = 120 TabIndex = 3 Top = 480 Width = 855 End Begin VB.Label lbl Caption = "&SubSite XML" Height = 255 Index = 2 Left = 120 TabIndex = 6 Top = 840 Width = 1095 End Begin VB.Label lbl Caption = "&Input CAB" Height = 255 Index = 0 Left = 120 TabIndex = 0 Top = 120 Width = 855 End End Attribute VB_Name = "frmMain" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit ' Make sure that these letters correspond to the Alt key combinations. Private Const OPT_CAB_IN_C As String = "i" Private Const OPT_CAB_OUT_C As String = "o" Private Const OPT_SS_XML_C As String = "s" Private Const OPT_HHT_C As String = "t" Private Const OPT_POPULATE_C As String = "p" Private Const OPT_CLOSE_ON_WARNING_C As String = "qw" Private Const OPT_CLOSE_ALWAYS_C As String = "qa" Private Const OPT_HELP_C As String = "h,?,help" Private Enum INPUT_INDEX_E II_CAB_IN_E = 0 II_CAB_OUT_E = 1 II_SS_XML_E = 2 II_HHT_E = 3 End Enum Private Const MAX_INPUT_INDEX_C As Long = 3 Private p_strSeparator As String Private p_blnWarning As Boolean Private p_blnError As Boolean Private p_clsSizer As Sizer Private Sub p_DisplayHelp() Dim str As String str = "Usage: " & vbCrLf & vbCrLf & _ App.EXEName & " /i <Input CAB> /o <Output CAB> /s <SubSite XML> /t <HHT To Add> /p /qw /qa" & vbCrLf & vbCrLf & _ "The /s, /t, /p, /qw, and /qa arguments are optional." & vbCrLf & _ "/qw makes the window go away even if there are Warnings." & vbCrLf & _ "/qa makes the window go away even if there are Errors and/or Warnings." & vbCrLf & _ """" & App.EXEName & " /?"" displays this message." Output str, LOGGING_TYPE_NORMAL_E Output p_strSeparator, LOGGING_TYPE_NORMAL_E End Sub Private Sub Form_Load() cmdGo.Default = True cmdClose.Cancel = True Set p_clsSizer = New Sizer SetLogFile Output "Version " & App.Major & "." & App.Minor & "." & App.Revision, LOGGING_TYPE_NORMAL_E p_strSeparator = String(80, "-") Output p_strSeparator, LOGGING_TYPE_NORMAL_E p_ProcessCommandLine End Sub Private Sub p_ProcessCommandLine() Dim strCommand As String Dim blnCloseOnWarning As Boolean Dim blnCloseAlways As Boolean Dim blnClose As Boolean strCommand = Trim$(Command$) If (strCommand = "") Then Exit Sub End If txtIn(II_CAB_IN_E) = GetOption(strCommand, OPT_CAB_IN_C, True) txtIn(II_CAB_OUT_E) = GetOption(strCommand, OPT_CAB_OUT_C, True) txtIn(II_SS_XML_E) = GetOption(strCommand, OPT_SS_XML_C, True) txtIn(II_HHT_E) = GetOption(strCommand, OPT_HHT_C, True) If (OptionExists(strCommand, OPT_POPULATE_C, True)) Then chkPopulate.Value = vbChecked End If blnCloseOnWarning = OptionExists(strCommand, OPT_CLOSE_ON_WARNING_C, True) blnCloseAlways = OptionExists(strCommand, OPT_CLOSE_ALWAYS_C, True) If (OptionExists(strCommand, OPT_HELP_C, True)) Then p_DisplayHelp ElseIf (Len(strCommand) <> 0) Then cmdGo_Click If (p_blnError) Then ' If an error occurred, then close the window only if OPT_CLOSE_ALWAYS_C is specified. If (blnCloseAlways) Then blnClose = True End If ElseIf (p_blnWarning) Then ' If a warning occurred, but there was no error, then close the window only if ' OPT_CLOSE_ON_WARNING_C or OPT_CLOSE_ALWAYS_C is specified. If (blnCloseOnWarning Or blnCloseAlways) Then blnClose = True End If Else ' If there was no warning or error, then close the window. blnClose = True End If If (blnClose) Then cmdClose_Click End If End If End Sub Private Sub cmdGo_Click() On Error GoTo LError Dim strCABIn As String Dim strCABOut As String Dim strSubSiteXML As String Dim strHHT As String Dim blnPopulateHelpImage As Boolean Output "Start: " & Date & " " & Time, LOGGING_TYPE_NORMAL_E strCABIn = Trim$(txtIn(II_CAB_IN_E).Text) strCABOut = Trim$(txtIn(II_CAB_OUT_E).Text) strSubSiteXML = Trim$(txtIn(II_SS_XML_E).Text) strHHT = Trim$(txtIn(II_HHT_E).Text) If (chkPopulate.Value = vbChecked) Then blnPopulateHelpImage = True End If If ((strCABIn = "") Or (strCABOut = "")) Then Output "Please specify the Input and Output CABs", LOGGING_TYPE_ERROR_E GoTo LError End If Me.Enabled = False MainFunction strCABIn, strCABOut, strSubSiteXML, strHHT, blnPopulateHelpImage LEnd: Output "End: " & Date & " " & Time, LOGGING_TYPE_NORMAL_E Output "The log file is: " & GetLogFileName, LOGGING_TYPE_NORMAL_E Output p_strSeparator, LOGGING_TYPE_NORMAL_E Me.Enabled = True Exit Sub LError: GoTo LEnd End Sub Private Sub cmdClose_Click() Unload Me End Sub Private Sub cmdBrowse_Click(Index As Integer) On Error GoTo LError dlgCommon.CancelError = True dlgCommon.Flags = cdlOFNHideReadOnly dlgCommon.Filter = "All Files (.)\|." dlgCommon.ShowOpen txtIn(Index).Text = dlgCommon.FileName LEnd: Exit Sub LError: Select Case Err.Number Case cdlCancel ' Nothing. The user cancelled. End Select GoTo LEnd End Sub Private Sub Form_Activate() On Error GoTo LError p_SetSizingInfo DoEvents LError: End Sub Private Sub Form_Resize() On Error GoTo LError p_clsSizer.Resize LError: End Sub Private Sub p_SetSizingInfo() Dim intIndex As Long For intIndex = 0 To MAX_INPUT_INDEX_C p_clsSizer.AddControl txtIn(intIndex) Set p_clsSizer.ReferenceControl(DIM_RIGHT_E) = Me p_clsSizer.ReferenceDimension(DIM_RIGHT_E) = DIM_WIDTH_E p_clsSizer.AddControl cmdBrowse(intIndex) Set p_clsSizer.ReferenceControl(DIM_LEFT_E) = Me p_clsSizer.ReferenceDimension(DIM_LEFT_E) = DIM_WIDTH_E Next p_clsSizer.AddControl cmdGo Set p_clsSizer.ReferenceControl(DIM_LEFT_E) = Me p_clsSizer.ReferenceDimension(DIM_LEFT_E) = DIM_WIDTH_E p_clsSizer.AddControl cmdClose Set p_clsSizer.ReferenceControl(DIM_LEFT_E) = Me p_clsSizer.ReferenceDimension(DIM_LEFT_E) = DIM_WIDTH_E p_clsSizer.AddControl txtOutput Set p_clsSizer.ReferenceControl(DIM_RIGHT_E) = Me p_clsSizer.ReferenceDimension(DIM_RIGHT_E) = DIM_WIDTH_E Set p_clsSizer.ReferenceControl(DIM_BOTTOM_E) = Me p_clsSizer.ReferenceDimension(DIM_BOTTOM_E) = DIM_HEIGHT_E End Sub Public Sub Output( _ ByVal i_str As String, _ ByVal i_enumLoggingType As LOGGING_TYPE_E _ ) OutputToTextBoxAndWriteLog txtOutput, i_str, i_enumLoggingType If (i_enumLoggingType = LOGGING_TYPE_ERROR_E) Then p_blnError = True ElseIf (i_enumLoggingType = LOGGING_TYPE_WARNING_E) Then p_blnWarning = True End If End Sub
<gh_stars>0 WScript.Echo("Goodbye, World!")
<gh_stars>1-10 class flattener dim separator sub class_initialize separator = "," end sub private function makeflat( a ) dim i dim res for i = lbound( a ) to ubound( a ) if isarray( a( i ) ) then res = res & makeflat( a( i ) ) else res = res & a( i ) & separator end if next makeflat = res end function public function flatten( a ) dim res res = makeflat( a ) res = left( res, len( res ) - len(separator)) res = split( res, separator ) flatten = res end function public property let itemSeparator( c ) separator = c end property end class
On Error Resume Next 'Ask for non-existent class to force error from CIMOM Set t_Service = GetObject("winmgmts://./root/default") Set t_Object = t_Service.Get("Nosuchclass000") if Err = 0 Then WScript.Echo "Got a class" Else WScript.Echo "" WScript.Echo "Err Information:" WScript.Echo "" WScript.Echo " Source:", Err.Source WScript.Echo " Description:", Err.Description WScript.Echo " Number", Err.Number 'Create the last error object set t_Object = CreateObject("WbemScripting.SWbemLastError") WScript.Echo "" WScript.Echo "WBEM Last Error Information:" WScript.Echo "" WScript.Echo " Operation:", t_Object.Operation WScript.Echo " Provider:", t_Object.ProviderName strDescr = t_Object.Description strPInfo = t_Object.ParameterInfo strCode = t_Object.StatusCode if (strDescr <> nothing) Then WScript.Echo " Description:", strDescr end if if (strPInfo <> nothing) Then WScript.Echo " Parameter Info:", strPInfo end if if (strCode <> nothing) Then WScript.Echo " Status:", strCode end if WScript.Echo "" Err.Clear set t_Object2 = CreateObject("WbemScripting.SWbemLastError") if Err = 0 Then WScript.Echo "Got the error object again - this shouldn't have happened!" Else Err.Clear WScript.Echo "Couldn't get last error again - as expected" End if End If
<reponame>LaudateCorpus1/RosettaCodeData Len(string\|varname)
DHRYSTONE 2.1 BENCHMARK REPORTING FORM MANUF: MODEL: PROC: CLOCK: OS: OVERSION: COMPILER: CVERSION: OPTIONS: NOREG: REG: NOTES: DATE: SUBMITTER: MAILTO: uunet!pcrat!dry2
<filename>admin/wmi/wbem/scripting/test/vbscript/iproutetable.vbs on error resume next set n = getobject ("winmgmts://alanbos2/root/snmp/test") set routingtable = n.instancesof ("SNMP_RFC1213_MIB_ipRouteTable") for each route in routingtable WScript.Echo route.path_.relpath result = route.Fred () if err <> 0 then WScript.Echo Hex(Err.Number), Err.Description, Err.Source Err.Clear end if next
Function gcd(u As Long, v As Long) As Long Dim t As Long Do While v t = u u = v v = t Mod v Loop gcd = u End Function Function lcm(m As Long, n As Long) As Long lcm = Abs(m * n) / gcd(m, n) End Function
VERSION 5.00 Begin VB.Form frmFolderChooser BorderStyle = 1 'Fixed Single Caption = "Choose folder" ClientHeight = 3495 ClientLeft = 45 ClientTop = 330 ClientWidth = 4680 LinkTopic = "Form1" MaxButton = 0 'False MinButton = 0 'False ScaleHeight = 3495 ScaleWidth = 4680 StartUpPosition = 3 'Windows Default Begin VB.CommandButton cmdCancel Caption = "Cancel" Height = 375 Left = 3720 TabIndex = 3 Top = 3000 Width = 855 End Begin VB.CommandButton cmdOK Caption = "OK" Height = 375 Left = 2760 TabIndex = 2 Top = 3000 Width = 855 End Begin VB.DirListBox Dir1 Height = 2340 Left = 120 TabIndex = 1 Top = 480 Width = 4455 End Begin VB.DriveListBox Drive1 Height = 315 Left = 120 TabIndex = 0 Top = 120 Width = 4455 End End Attribute VB_Name = "frmFolderChooser" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Private p_FSO As Scripting.FileSystemObject Private p_intIndex As Long Public Event FolderChosen(ByVal intIndex As Long, ByVal strFolder As String) Private Sub Form_Load() cmdOK.Default = True cmdCancel.Cancel = True Set p_FSO = New Scripting.FileSystemObject End Sub Private Sub Form_Unload(Cancel As Integer) Set p_FSO = Nothing End Sub Private Sub cmdOK_Click() RaiseEvent FolderChosen(p_intIndex, Dir1.Path) Unload Me End Sub Private Sub cmdCancel_Click() Unload Me End Sub Private Sub Drive1_Change() Dir1.Path = Mid$(Drive1.Drive, 1, 2) & "\" End Sub Public Sub SetFolder( _ ByVal i_intIndex As Long, _ ByVal i_strFolder As String _ ) Dim strDrive As String Dim strFolder As String If (p_FSO.FolderExists(i_strFolder)) Then strFolder = i_strFolder Else strFolder = p_FSO.GetSpecialFolder(TemporaryFolder) End If Drive1.Drive = p_FSO.GetDriveName(strFolder) Dir1.Path = strFolder p_intIndex = i_intIndex End Sub
'******************************************************************* ' ' datetime.vbs ' ' Purpose: test datetime functionality ' ' Parameters: none ' ' Returns: 0 - success ' 1 - failure ' '***************************************************************** on error resume next set scriptHelper = CreateObject("WMIScriptHelper.WSC") scriptHelper.logFile = "c:\temp\datetime.txt" scriptHelper.loggingLevel = 3 scriptHelper.testName = "DATETIME" scriptHelper.testStart '************************* ' Create a datetime object '************************* set datetime = CreateObject("WbemScripting.SWbemDatetime") if err <> 0 then scriptHelper.writeErrorToLog err, "Failed to create datetime" else scriptHelper.writeToLog "Datetime created correctly", 2 end if '************************* ' Create a Variant date '************************* myDate = CDate ("January 20 11:56:32") '************************* ' Test 1 - Set as local date '************************* datetime.SetVarDate (myDate) if datetime.Value <> "20000120195632.000000-480" then scriptHelper.writeErrorToLog null, "Incorrect DMTF value" else scriptHelper.writeToLog "DMTF value reported correctly", 2 end if if datetime.Year <> 2000 then scriptHelper.writeErrorToLog null, "Incorrect Year value" else scriptHelper.writeToLog "Year value reported correctly", 2 end if if datetime.YearSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect YearSpecified value" else scriptHelper.writeToLog "YearSpecified value reported correctly", 2 end if if datetime.Month <> 1 then scriptHelper.writeErrorToLog null, "Incorrect Month value" else scriptHelper.writeToLog "Month value reported correctly", 2 end if if datetime.MonthSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect MonthSpecified value" else scriptHelper.writeToLog "MonthSpecified value reported correctly", 2 end if if datetime.Day <> 20 then scriptHelper.writeErrorToLog null, "Incorrect Day value" else scriptHelper.writeToLog "Day value reported correctly", 2 end if if datetime.DaySpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect DaySpecified value" else scriptHelper.writeToLog "DaySpecified value reported correctly", 2 end if if datetime.Hours <> 19 then scriptHelper.writeErrorToLog null, "Incorrect Hours value" else scriptHelper.writeToLog "Hours value reported correctly", 2 end if if datetime.HoursSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect HoursSpecified value" else scriptHelper.writeToLog "HoursSpecified value reported correctly", 2 end if if datetime.Minutes <> 56 then scriptHelper.writeErrorToLog null, "Incorrect Minutes value" else scriptHelper.writeToLog "Minutes value reported correctly", 2 end if if datetime.MinutesSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect MinutesSpecified value" else scriptHelper.writeToLog "MinutesSpecified value reported correctly", 2 end if if datetime.Seconds <> 32 then scriptHelper.writeErrorToLog null, "Incorrect Seconds value" else scriptHelper.writeToLog "Seconds value reported correctly", 2 end if if datetime.SecondsSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect SecondsSpecified value" else scriptHelper.writeToLog "SecondsSpecified value reported correctly", 2 end if if datetime.MicroSeconds <> 0 then scriptHelper.writeErrorToLog null, "Incorrect Microseconds value" else scriptHelper.writeToLog "Microseconds value reported correctly", 2 end if if datetime.MicroSecondsSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect MicrosecondsSpecified value" else scriptHelper.writeToLog "MicrosecondsSpecified value reported correctly", 2 end if if datetime.UTC <> -480 then scriptHelper.writeErrorToLog null, "Incorrect UTC value" else scriptHelper.writeToLog "UTC value reported correctly", 2 end if if datetime.UTCSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect UTCSpecified value" else scriptHelper.writeToLog "UTCSpecified value reported correctly", 2 end if if datetime.IsInterval <> false then scriptHelper.writeErrorToLog null, "Incorrect IsInterval value" else scriptHelper.writeToLog "IsInterval value reported correctly", 2 end if varDate = datetime.GetVarDate if err <> 0 then scriptHelper.writeErrorToLog err, "Failed to get VarDate" else scriptHelper.writeToLog "Vardate retrieved correctly: " & VarDate, 2 end if '************************* 'Test Interval strings '************************* dateTime.IsInterval = true dateTime.Day = 100 dateTime.Hours = 1 dateTime.Minutes = 0 dateTime.Seconds = 3 if datetime.Value <> "00000100010003.000000:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if '************************* 'Test wildcard strings '************************* datetime.Value = "19980416**.000000+" if datetime.Value <> "19980416***.000000+" then scriptHelper.writeErrorToLog null, "Failed to get correct wildcard value" else scriptHelper.writeToLog "Wildcard value retrieved correctly", 2 end if '************************** 'Test invalid strings '*************************** datetime.Value = "1990416***.000000+" if err <> 0 then scriptHelper.writeToLog "Invalid value correctly rejected:" & err.Description, 2 err.clear else scriptHelper.writeErrorToLog null, "Invalid value erroneously accepted" end if '************************** 'Test setting of individual properties '************************* set datetime = CreateObject("WbemScripting.SWbemDatetime") if err <> 0 then scriptHelper.writeErrorToLog err, "Failed to create datetime" else scriptHelper.writeToLog "Datetime created correctly", 2 end if datetime.Year = 2000 datetime.Month = 5 datetime.Day = 8 datetime.Hours = 14 datetime.Minutes = 20 datetime.Seconds = 32 datetime.Microseconds = 123456 datetime.UTC = 320 if datetime.Value <> "20000508142032.123456+320" then scriptHelper.writeErrorToLog null, "Failed to get correct property-set value" else scriptHelper.writeToLog "Property-set value retrieved correctly", 2 end if '************************* 'Test effects of changing IsInterval property '************************* datetime.IsInterval = true if datetime.Value <> "00000008142032.123456:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if datetime.Day = 99999999 if datetime.Value <> "99999999142032.123456:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if datetime.IsInterval = false if datetime.Day <> 31 then scriptHelper.writeErrorToLog null, "Failed to get correct Day value" else scriptHelper.writeToLog "Day value retrieved correctly", 2 end if datetime.IsInterval = true datetime.Day = 0 if datetime.Value <> "00000000142032.123456:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if datetime.IsInterval = false if datetime.Day <> 1 then scriptHelper.writeErrorToLog null, "Failed to get correct Day value" else scriptHelper.writeToLog "Day value retrieved correctly", 2 end if '************************* 'Test conversion between local and non-local formats '************************* dateTime.SetVarDate (CDate ("January 20 11:56:32")) if datetime.Value <> "20000120195632.000000-480" then scriptHelper.writeErrorToLog null, "Failed to get correct datetime value " & datetime.Value else scriptHelper.writeToLog "Datetime value retrieved correctly", 2 end if if dateTime.GetVarDate () <> "1/20/2000 11:56:32 AM" then scriptHelper.writeErrorToLog null, "Failed to get correct local vardate value" else scriptHelper.writeToLog "Local vardate value retrieved correctly", 2 end if if dateTime.GetVarDate (false) <> "1/20/2000 7:56:32 PM" then scriptHelper.writeErrorToLog null, "Failed to get correct non-local vardate value" else scriptHelper.writeToLog "Non-Local vardate value retrieved correctly", 2 end if if dateTime.GetFileTime () <> "125928429920000000" then scriptHelper.writeErrorToLog null, "Failed to get correct local filetime value" else scriptHelper.writeToLog "Local filetime value retrieved correctly", 2 end if if dateTime.GetFileTime (false) <> "125928717920000000" then scriptHelper.writeErrorToLog null, "Failed to get correct non-local filetime value" else scriptHelper.writeToLog "Non-Local filetime value retrieved correctly", 2 end if '********************************************* 'Test invariance of filetime down to 1ms precision '*********************************************** datetime.SetFileTime "126036951652031260" if datetime.GetFileTime <> "126036951652031260" then scriptHelper.writeErrorToLog null, "Failed to preserve filetime to 1ms precision" else scriptHelper.writeToLog "Filetime value preserved to 1ms precision correctly", 2 end if scriptHelper.testComplete if scriptHelper.statusOK then WScript.Echo "PASS" WScript.Quit 0 else WScript.Echo "FAIL" WScript.Quit 1 end if
Option Explicit '---------------------------------------------------------------------- Private Function coin_count(coins As Variant, amount As Long) As Variant 'return type will be Decimal Dim s() As Variant Dim n As Long, c As Long ReDim s(amount + 1) s(1) = CDec(1) For c = LBound(coins) To UBound(coins) For n = coins(c) To amount s(n + 1) = CDec(s(n + 1) + s(n - coins(c) + 1)) Next n Next c coin_count = s(amount + 1) End Function '---------------------------------------------------------------------- Sub Main() Dim us_common_coins As Variant Dim us_coins As Variant 'The next line creates 0-based array us_common_coins = Array(25, 10, 5, 1) Debug.Print coin_count(us_common_coins, 100) us_coins = Array(100, 50, 25, 10, 5, 1) Debug.Print coin_count(us_coins, 100000) End Sub
<reponame>npocmaka/Windows-Server-2003 VERSION 5.00 Object = "{EAB22AC0-30C1-11CF-A7EB-0000C05BAE0B}#1.1#0"; "shdocvw.dll" Object = "{831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0"; "mscomctl.ocx" Begin VB.Form HssX Caption = "HSC Extensions Manager" ClientHeight = 8235 ClientLeft = 3135 ClientTop = 2280 ClientWidth = 6240 LinkTopic = "Form1" ScaleHeight = 8235 ScaleWidth = 6240 Begin MSComctlLib.StatusBar StatusBar1 Align = 2 'Align Bottom Height = 285 Left = 0 TabIndex = 21 Top = 7950 Width = 6240 _ExtentX = 11007 _ExtentY = 503 _Version = 393216 BeginProperty Panels {8E3867A5-8586-11D1-B16A-00C0F0283628} NumPanels = 1 BeginProperty Panel1 {8E3867AB-8586-11D1-B16A-00C0F0283628} EndProperty EndProperty End Begin VB.TextBox txtAuxFolder Height = 300 Left = 30 TabIndex = 18 Top = 1245 Width = 5355 End Begin VB.TextBox txtCabFile Height = 300 Left = 30 TabIndex = 17 Top = 720 Width = 5355 End Begin VB.CommandButton cmdExecuteExts Caption = "E&xecute Extensions" Height = 375 Left = 3750 TabIndex = 16 Top = 7560 Width = 1800 End Begin MSComctlLib.ListView lstvwExtensions Height = 2070 Left = 30 TabIndex = 15 Top = 3195 Width = 6150 _ExtentX = 10848 _ExtentY = 3651 LabelWrap = -1 'True HideSelection = -1 'True OLEDropMode = 1 Checkboxes = -1 'True _Version = 393217 ForeColor = -2147483640 BackColor = -2147483643 BorderStyle = 1 Appearance = 1 OLEDropMode = 1 NumItems = 1 BeginProperty ColumnHeader(1) {BDD1F052-858B-11D1-B16A-00C0F0283628} Object.Width = 2540 EndProperty End Begin VB.Frame fraSKU Caption = "SKU" Height = 1575 Left = 30 TabIndex = 5 Top = 1560 Width = 6135 Begin VB.CheckBox chkStandard Caption = "32-bit Standard" Height = 255 Left = 240 TabIndex = 14 Top = 480 Width = 1695 End Begin VB.CheckBox chkProfessional Caption = "32-bit Professional" Height = 255 Left = 240 TabIndex = 13 Top = 720 Width = 1695 End Begin VB.CheckBox chkServer Caption = "32-bit Server" Height = 255 Left = 3120 TabIndex = 12 Top = 240 Width = 2055 End Begin VB.CheckBox chkAdvancedServer Caption = "32-bit Advanced Server" Height = 255 Left = 3120 TabIndex = 11 Top = 480 Width = 2055 End Begin VB.CheckBox chkDataCenterServer Caption = "32-bit Datacenter Server" Height = 255 Left = 3120 TabIndex = 10 Top = 960 Width = 2055 End Begin VB.CheckBox chkProfessional64 Caption = "64-bit Professional" Height = 255 Left = 240 TabIndex = 9 Top = 960 Width = 1695 End Begin VB.CheckBox chkAdvancedServer64 Caption = "64-bit Advanced Server" Height = 255 Left = 3120 TabIndex = 8 Top = 720 Width = 2055 End Begin VB.CheckBox chkDataCenterServer64 Caption = "64-bit Datacenter Server" Height = 255 Left = 3120 TabIndex = 7 Top = 1200 Width = 2055 End Begin VB.CheckBox chkWindowsMillennium Caption = "Windows Me" Height = 255 Left = 240 TabIndex = 6 Top = 240 Width = 1695 End End Begin SHDocVwCtl.WebBrowser wb Height = 2235 Left = 45 TabIndex = 4 Top = 5280 Width = 6165 ExtentX = 10874 ExtentY = 3942 ViewMode = 0 Offline = 0 Silent = 0 RegisterAsBrowser= 0 RegisterAsDropTarget= 1 AutoArrange = 0 'False NoClientEdge = 0 'False AlignLeft = 0 'False ViewID = "{0057D0E0-3573-11CF-AE69-08002B2E1262}" Location = "res://C:\WINNT\system32\shdoclc.dll/dnserror.htm#http:///" End Begin VB.CommandButton cmdClose Caption = "&Close" Height = 375 Left = 5565 TabIndex = 3 Top = 7560 Width = 675 End Begin VB.CommandButton cmdGo Caption = "&Go" Height = 315 Left = 5415 TabIndex = 2 Top = 240 Width = 675 End Begin VB.TextBox txtExtensionsFolder Height = 300 Left = 30 TabIndex = 0 Top = 240 Width = 5355 End Begin VB.Label Label3 Caption = "Auxiliary Folder for Storing Extensions Output:" Height = 240 Left = 75 TabIndex = 20 Top = 1035 Width = 3555 End Begin VB.Label Label2 Caption = "Cab File Location:" Height = 240 Left = 45 TabIndex = 19 Top = 525 Width = 3000 End Begin VB.Label Label1 Caption = "Extension Tools Directory Location:" Height = 240 Left = 30 TabIndex = 1 Top = 15 Width = 3000 End Begin VB.Menu mnuExt Caption = "Extension Right Click Menu" Visible = 0 'False Begin VB.Menu mnuEdit Caption = "Edit" End Begin VB.Menu mnuDelete Caption = "Delete" End End End Attribute VB_Name = "HssX" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False ' ========================================================================================== Option Explicit Private m_strTempXMLFile As String ' Temporary File for XML Rendering Private m_oDomList As IXMLDOMNodeList ' List of Extensions Private WithEvents m_oHssExt As HssExts Attribute m_oHssExt.VB_VarHelpID = -1 Private m_oFs As Scripting.FileSystemObject Private m_bIndrag As Boolean ' This variable is used to control ' dragging inside the Listview Private m_oCachedExt As IXMLDOMNode ' This is the Cached DOMNODE ' which is saved on MouseUp ' event from the ListView. ' We need to cache it because ' Menus are event driven. Private m_dblTimeLeftButtonDown As Double ' Tracks how long the Mouse Down button was pressed. Private Sub Form_Initialize() Set m_oHssExt = New HssExts Set m_oFs = New Scripting.FileSystemObject End Sub Private Sub Form_Load() With Me .txtExtensionsFolder = App.Path + "\Extensions" .txtAuxFolder = App.Path + "\AuxFolder" .txtCabFile = App.Path + "\hcdata.cab" End With ' Let's Get a Temporary File Name m_strTempXMLFile = Environ$("TEMP") + "\" + m_oFs.GetTempName + ".xml" Dim oFh As Scripting.TextStream Set oFh = m_oFs.CreateTextFile(m_strTempXMLFile) oFh.WriteLine "<Note>When you click on an extension in the List Above, the HSS Tool Extension XML Entry will show up here</Note>" oFh.Close wb.Navigate m_strTempXMLFile ' let's kick the first Extensions Search. ' txtExtensionsFolder_Change End Sub Private Sub chkAdvancedServer_Click() cmdGo_Click End Sub Private Sub chkAdvancedServer64_Click() cmdGo_Click End Sub Private Sub chkDataCenterServer_Click() cmdGo_Click End Sub Private Sub chkDataCenterServer64_Click() cmdGo_Click End Sub Private Sub chkProfessional_Click() cmdGo_Click End Sub Private Sub chkProfessional64_Click() cmdGo_Click End Sub Private Sub chkServer_Click() cmdGo_Click End Sub Private Sub chkStandard_Click() cmdGo_Click End Sub Private Sub chkWindowsMillennium_Click() cmdGo_Click End Sub Private Sub cmdExecuteExts_Click() m_oHssExt.ExecuteExtensions m_oDomList, Me.txtCabFile, Me.txtAuxFolder End Sub Private Sub cmdClose_Click() Unload Me End Sub Private Sub cmdGo_Click() Dim oDomList As IXMLDOMNodeList Set m_oDomList = m_oHssExt.GetExtensionsList(Me.txtExtensionsFolder, SkuCollection) With Me.lstvwExtensions .LabelEdit = lvwManual .ListItems.Clear .View = lvwReport .ColumnHeaders(1).Text = "Select Extensions to Run" .ColumnHeaders(1).Width = lstvwExtensions.Width - 85 If (m_oDomList Is Nothing) Then GoTo Common_Exit Dim oDomNode As IXMLDOMNode Dim l As ListItem For Each oDomNode In m_oDomList Set l = .ListItems.Add(Text:=oDomNode.selectSingleNode("display-name").Text) Set l.Tag = oDomNode Next End With Common_Exit: End Sub Private Function SkuCollection() As Scripting.Dictionary Set SkuCollection = New Scripting.Dictionary If (Me.chkAdvancedServer) Then SkuCollection.Add "ADV", "ADV" End If If (Me.chkAdvancedServer64) Then SkuCollection.Add "ADV64", "ADV64" End If If (Me.chkDataCenterServer) Then SkuCollection.Add "DAT", "DAT" End If If (Me.chkDataCenterServer64) Then SkuCollection.Add "DAT64", "DAT64" End If If (Me.chkProfessional) Then SkuCollection.Add "PRO", "PRO" End If If (Me.chkProfessional64) Then SkuCollection.Add "PRO64", "PRO64" End If If (Me.chkServer) Then SkuCollection.Add "SRV", "SRV" End If If (Me.chkStandard) Then SkuCollection.Add "STD", "STD" End If If (Me.chkWindowsMillennium) Then SkuCollection.Add "WINME", "WINME" End If End Function Private Sub lstvwExtensions_Click() DisplayTaxonomyEntry2 lstvwExtensions, m_oDomList, wb End Sub Private Sub lstvwExtensions_ItemCheck(ByVal Item As MSComctlLib.ListItem) Dim oElem As IXMLDOMElement ' Set oElem = m_oDomList.Item(lstvwExtensions.HitTest(Item.Left, Item.Top).Index - 1).selectSingleNode("run-this-extension") Set oElem = Item.Tag Set oElem = oElem.selectSingleNode("run-this-extension") oElem.Text = IIf(Item.Checked, "yes", "no") End Sub Private Sub lstvwExtensions_DragDrop(source As Control, x As Single, y As Single) DoDragDrop lstvwExtensions, source, x, y End Sub Private Sub lstvwExtensions_DragOver(source As Control, x As Single, y As Single, State As Integer) DoDragOver lstvwExtensions, source, x, y, State End Sub Private Sub lstvwExtensions_MouseDown(Button As Integer, Shift As Integer, x As Single, y As Single) If (Button = vbLeftButton) Then m_dblTimeLeftButtonDown = HighResTimer End If End Sub Private Sub lstvwExtensions_MouseUp(Button As Integer, Shift As Integer, x As Single, y As Single) ' Debug.Print "Button = " & Button & " - Shift = " & Shift Select Case Button Case vbRightButton If (Not lstvwExtensions.HitTest(x, y) Is Nothing) Then Set m_oCachedExt = lstvwExtensions.HitTest(x, y).Tag PopupMenu mnuExt Set m_oCachedExt = Nothing End If Case vbLeftButton m_dblTimeLeftButtonDown = 0 End Select End Sub Private Sub lstvwExtensions_MouseMove(Button As Integer, Shift As Integer, x As Single, y As Single) DoMouseMove lstvwExtensions, Button, Shift, x, y End Sub Sub DoMouseMove(lvw As ListView, Button As Integer, Shift As Integer, x As Single, y As Single) If (Button = vbLeftButton) Then If (LeftButtonWasPressedLongEnough) Then ' Signal a Drag operation. ' Set the drag icon with the CreateDragImage method. If (Not lvw.SelectedItem Is Nothing) Then m_bIndrag = True ' Set the flag to true. lvw.DragIcon = lvw.SelectedItem.CreateDragImage lvw.Drag vbBeginDrag ' Drag operation. End If End If Else m_bIndrag = False End If ' Debug.Print "DoMouseMove Called from " & lvw.Name; "_MouseMove. m_bIndrag = " & m_bIndrag End Sub Private Function LeftButtonWasPressedLongEnough() As Boolean LeftButtonWasPressedLongEnough = False If (m_dblTimeLeftButtonDown <> 0) Then LeftButtonWasPressedLongEnough = ((HighResTimer - m_dblTimeLeftButtonDown) > 0.4) End If End Function Sub DoDragOver(lvw As ListView, source As Control, x As Single, y As Single, State As Integer) If m_bIndrag = True Then ' Set DropHighlight to the mouse's coordinates. Set lvw.DropHighlight = lvw.HitTest(x, y) End If End Sub Sub DoDragDrop(lvw As ListView, _ source As Control, x As Single, y As Single _ ) If lvw.DropHighlight Is Nothing Then GoTo Common_Exit If (lvw Is source) Then ' We are on the Same Tree, so we need If lvw.SelectedItem.Index = lvw.DropHighlight.Index Then GoTo Common_Exit ' Temporary Variables to keep The List view Item contents. Dim strLi1 As String, strSli1 As String, strSli2 As String Dim oTag As Object, bChecked As Boolean ' The direction in which the List Items will be moved ' on the list to make room for the move Dim lDirection As Long If (lvw.DropHighlight.Index < lvw.SelectedItem.Index) Then lDirection = -1 Else lDirection = 1 End If With lvw.SelectedItem bChecked = .Checked Set oTag = .Tag strLi1 = .Text ' strSli1 = .ListSubItems(1).Text ' strSli2 = .ListSubItems(2).Text End With Dim i As Long For i = lvw.SelectedItem.Index To lvw.DropHighlight.Index - lDirection Step lDirection With lvw.ListItems .Item(i).Checked = .Item(i + lDirection).Checked Set .Item(i).Tag = .Item(i + lDirection).Tag .Item(i) = .Item(i + lDirection) ' .Item(i).ListSubItems(1) = .Item(i + lDirection).ListSubItems(1) ' .Item(i).ListSubItems(2) = .Item(i + lDirection).ListSubItems(2) End With Next i With lvw.DropHighlight .Checked = bChecked Set .Tag = oTag .Text = strLi1 ' .ListSubItems(1).Text = strSli1 ' .ListSubItems(2).Text = strSli2 End With Debug.Print lvw.SelectedItem.Text & " dropped on " & lvw.DropHighlight.Text End If Common_Exit: ' This is the exit Condition for Shutting Down the Drag operation Set lvw.DropHighlight = Nothing: m_bIndrag = False Exit Sub End Sub Private Sub lstvwExtensions_OLEDragDrop( _ Data As MSComctlLib.DataObject, _ Effect As Long, Button As Integer, _ Shift As Integer, _ x As Single, _ y As Single _ ) If Data.GetFormat(vbCFFiles) Then Dim vFN For Each vFN In Data.Files ' Screen.MousePointer = vbHourglass ' Screen.MousePointer = 99 ' Screen.MouseIcon = LoadPicture(Environ$("WINDIR") + "\cursors\wait_m.cur") Select Case UCase$(m_oFs.GetExtensionName(vFN)) Case "EXE", "VBS", "JS", "BAT", "PL" If (Not m_oHssExt.ExtensionExists(m_oFs.GetFileName(vFN))) Then Dim oFext As frmExt: Set oFext = New frmExt oFext.DropFile Nothing, vFN, "MSFT" cmdGo_Click Else MsgBox "This Extension was already added to the Extensions System " + vbCrLf + _ "in case you want to update it, please remove first the old " + vbCrLf + _ "extension and then retry the operation", vbInformation, _ Me.Caption End If End Select ' Screen.MousePointer = vbDefault Next vFN End If End Sub Private Sub m_oHssExt_RunStatus(ByVal strExt As String, bCancel As Boolean) Me.StatusBar1.SimpleText = strExt End Sub Private Sub mnuDelete_Click() m_oHssExt.DeleteExtension m_oCachedExt cmdGo_Click End Sub Private Sub mnuEdit_Click() MsgBox "Edit Menu" End Sub Private Sub txtExtensionsFolder_Change() Dim bEnabled As Boolean bEnabled = m_oFs.FolderExists(Me.txtExtensionsFolder) With Me .txtAuxFolder.Enabled = bEnabled .txtCabFile.Enabled = bEnabled .lstvwExtensions.Enabled = bEnabled .fraSKU.Enabled = bEnabled .cmdExecuteExts.Enabled = bEnabled .cmdGo.Enabled = bEnabled End With cmdGo_Click End Sub Sub DisplayTaxonomyEntry2(oList As ListView, oResultsList As IXMLDOMNodeList, wBrowser As WebBrowser) If (oList.SelectedItem Is Nothing) Then GoTo Common_Exit Dim oDom As DOMDocument: Set oDom = New DOMDocument oDom.loadXML oList.SelectedItem.Tag.xml oDom.save m_strTempXMLFile wBrowser.Navigate m_strTempXMLFile Common_Exit: End Sub
<reponame>LaudateCorpus1/RosettaCodeData<filename>Task/Align-columns/Visual-Basic/align-columns-1.vb<gh_stars>1-10 Sub AlignCols(Lines, Optional Align As AlignmentConstants, Optional Sep$ = "$", Optional Sp% = 1) Dim i&, j&, D&, L&, R&: ReDim W(UBound(Lines)): ReDim C&(0) For j = 0 To UBound(W) W(j) = Split(Lines(j), Sep) If UBound(W(j)) > UBound(C) Then ReDim Preserve C(UBound(W(j))) For i = 0 To UBound(W(j)): If Len(W(j)(i)) > C(i) Then C(i) = Len(W(j)(i)) Next i, j For j = 0 To UBound(W): For i = 0 To UBound(W(j)) D = C(i) - Len(W(j)(i)) L = Choose(Align + 1, 0, D, D \ 2) R = Choose(Align + 1, D, 0, D - L) + Sp Debug.Print Space(L); W(j)(i); Space(R); IIf(i < UBound(W(j)), "", vbLf); Next i, j End Sub
VERSION 5.00 Begin VB.Form Form1 Caption = "Form1" ClientHeight = 12675 ClientLeft = 60 ClientTop = 345 ClientWidth = 13095 LinkTopic = "Form1" ScaleHeight = 12675 ScaleWidth = 13095 StartUpPosition = 3 'Windows Default Begin VB.CommandButton Cancelc BackColor = &H000000FF& Caption = "Cancel (c)" Height = 855 Left = 10320 Style = 1 'Graphical TabIndex = 39 Top = 4560 Width = 1455 End Begin VB.CommandButton CancelButton BackColor = &H000000FF& Caption = "Cancel (s)" Height = 855 Left = 8160 MaskColor = &H8000000A& Style = 1 'Graphical TabIndex = 38 Top = 4560 Width = 1335 End Begin VB.ListBox ContextResults Height = 2985 ItemData = "Form1.frx":0000 Left = 120 List = "Form1.frx":0002 TabIndex = 37 Top = 6840 Width = 3135 End Begin VB.ListBox ContextList Height = 1815 ItemData = "Form1.frx":0004 Left = 8520 List = "Form1.frx":0006 TabIndex = 35 Top = 2040 Width = 3135 End Begin VB.CommandButton DeleteContext Caption = "Delete All" Height = 495 Left = 10200 TabIndex = 34 Top = 1320 Width = 1335 End Begin VB.CommandButton AddContext Caption = "Add" Height = 495 Left = 8760 TabIndex = 33 Top = 1320 Width = 855 End Begin VB.TextBox ContextValue Height = 375 Left = 10200 TabIndex = 32 Top = 600 Width = 1335 End Begin VB.TextBox ContextName Height = 375 Left = 8520 TabIndex = 31 Top = 600 Width = 1335 End Begin VB.CommandButton Command20 Caption = "Async Put Class (s)" Height = 615 Left = 5520 TabIndex = 29 Top = 4920 Width = 1455 End Begin VB.CommandButton Command19 Caption = "Sync Put Class" Height = 615 Left = 3840 TabIndex = 28 Top = 4920 Width = 1335 End Begin VB.TextBox QueryBox Height = 375 Left = 360 TabIndex = 25 Text = "select * from Win32_LogicalDisk" Top = 1320 Width = 3135 End Begin VB.CommandButton Command18 Caption = "Async Put Obj (s)" Height = 615 Left = 2160 TabIndex = 19 Top = 4920 Width = 1335 End Begin VB.CommandButton Command17 Caption = "Sync Put Obj" Height = 615 Left = 720 TabIndex = 18 Top = 4920 Width = 1215 End Begin VB.CheckBox Check1 Caption = "Use Object Methods" Height = 375 Left = 720 TabIndex = 17 TabStop = 0 'False Top = 5880 Width = 2175 End Begin VB.CommandButton Command16 Caption = "Sync NotificationQuery (c)" Height = 615 Left = 5520 TabIndex = 16 Top = 3960 Width = 1455 End Begin VB.CommandButton Command15 Caption = "Sync NotificationQuery" Height = 615 Left = 3840 TabIndex = 15 Top = 3960 Width = 1335 End Begin VB.CommandButton Command14 Caption = "Async ReferencesTo (c)" Height = 615 Left = 2160 TabIndex = 14 Top = 3960 Width = 1335 End Begin VB.CommandButton Command13 Caption = "Sync ReferencesTo" Height = 615 Left = 720 TabIndex = 13 Top = 3960 Width = 1215 End Begin VB.CommandButton Command12 Caption = "Async AssociatorsOf (c)" Height = 615 Left = 2160 TabIndex = 12 Top = 3000 Width = 1335 End Begin VB.CommandButton Command11 Caption = "Sync AssociatorsOf" Height = 615 Left = 720 TabIndex = 11 Top = 3000 Width = 1215 End Begin VB.CommandButton Command10 Caption = "Async SubclassesOf (c)" Height = 615 Left = 5520 TabIndex = 10 Top = 3000 Width = 1455 End Begin VB.CommandButton Command9 Caption = "Sync SubclassesOf" Height = 615 Left = 3840 TabIndex = 9 Top = 3000 Width = 1335 End Begin VB.CommandButton Command8 Caption = "Async InstancesOf (s)" Height = 615 Left = 5520 TabIndex = 8 Top = 2040 Width = 1455 End Begin VB.CommandButton Command7 Caption = "Sync InstncesOf" Height = 615 Left = 3840 TabIndex = 7 Top = 2040 Width = 1335 End Begin VB.CommandButton Command6 Caption = "Async Delete (s)" Height = 615 Left = 2160 TabIndex = 6 Top = 2040 Width = 1335 End Begin VB.CommandButton Command5 Caption = "Sync Delete" Height = 615 Left = 720 TabIndex = 5 Top = 2040 Width = 1215 End Begin VB.CommandButton Command4 Caption = "Async Get (s)" Height = 615 Left = 5520 TabIndex = 4 Top = 600 Width = 1455 End Begin VB.CommandButton Command3 Caption = "Sync Get" Height = 615 Left = 3840 TabIndex = 3 Top = 600 Width = 1335 End Begin VB.Timer Timer1 Interval = 100 Left = 2400 Top = 12480 End Begin VB.ListBox List1 Height = 2985 ItemData = "Form1.frx":0008 Left = 3600 List = "Form1.frx":000A TabIndex = 2 Top = 6840 Width = 3735 End Begin VB.CommandButton Command2 Caption = "Query Async (s)" Height = 615 Left = 2160 TabIndex = 1 Top = 600 Width = 1335 End Begin VB.CommandButton Command1 Caption = "Query Sync" Height = 615 Left = 720 TabIndex = 0 Top = 600 Width = 1215 End Begin VB.Frame Frame1 Caption = "Operations" Height = 6375 Left = 0 TabIndex = 30 Top = 240 Width = 7455 Begin VB.Line Line5 BorderColor = &H000000FF& X1 = 600 X2 = 7080 Y1 = 4560 Y2 = 4560 End Begin VB.Line Line4 X1 = 600 X2 = 7080 Y1 = 3600 Y2 = 3600 End Begin VB.Line Line3 X1 = 600 X2 = 7200 Y1 = 2640 Y2 = 2640 End Begin VB.Line Line2 X1 = 600 X2 = 7200 Y1 = 1680 Y2 = 1680 End Begin VB.Line Line1 X1 = 3720 X2 = 3720 Y1 = 240 Y2 = 5520 End End Begin VB.Frame Frame2 Caption = "Context" Height = 3855 Left = 8160 TabIndex = 36 Top = 360 Width = 3975 End Begin VB.Label ObjectPathLabel Caption = "Null" Height = 375 Left = 1560 TabIndex = 27 Top = 11160 Width = 4575 End Begin VB.Label Label4 Caption = "Put Obj Path:" Height = 375 Left = 240 TabIndex = 26 Top = 11160 Width = 1215 End Begin VB.Label LastErrorString Height = 375 Left = 2280 TabIndex = 24 Top = 10560 Width = 2415 End Begin VB.Label Label1 Caption = "Status:" Height = 255 Left = 480 TabIndex = 23 Top = 9960 Width = 615 End Begin VB.Label Label3 Caption = "Last Error:" Height = 375 Left = 240 TabIndex = 22 Top = 10560 Width = 735 End Begin VB.Label LastError Height = 375 Left = 1200 TabIndex = 21 Top = 10560 Width = 975 End Begin VB.Label Status Height = 255 Left = 1200 TabIndex = 20 Top = 9960 Width = 2055 End Begin VB.Image Image3 Height = 480 Left = 240 Picture = "Form1.frx":000C Top = 12600 Visible = 0 'False Width = 480 End Begin VB.Image Image2 Height = 480 Left = 1680 Picture = "Form1.frx":07FE Top = 12480 Visible = 0 'False Width = 480 End Begin VB.Image Image1 Height = 480 Left = 7800 Picture = "Form1.frx":0B08 Top = 7320 Width = 480 End End Attribute VB_Name = "Form1" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Dim WithEvents someSink As SWbemSink Attribute someSink.VB_VarHelpID = -1 Dim WithEvents classSink As SWbemSink Attribute classSink.VB_VarHelpID = -1 Dim WithEvents tmpSink1 As SWbemSink Attribute tmpSink1.VB_VarHelpID = -1 Dim WithEvents tmpSink2 As SWbemSink Attribute tmpSink2.VB_VarHelpID = -1 Dim WithEvents tmpSink3 As SWbemSink Attribute tmpSink3.VB_VarHelpID = -1 Dim WithEvents tmpSink4 As SWbemSink Attribute tmpSink4.VB_VarHelpID = -1 Dim WithEvents tmpSink5 As SWbemSink Attribute tmpSink5.VB_VarHelpID = -1 Dim WithEvents tmpSink6 As SWbemSink Attribute tmpSink6.VB_VarHelpID = -1 Dim WithEvents tmpSink7 As SWbemSink Attribute tmpSink7.VB_VarHelpID = -1 Dim WithEvents tmpSink8 As SWbemSink Attribute tmpSink8.VB_VarHelpID = -1 Dim WithEvents tmpSink9 As SWbemSink Attribute tmpSink9.VB_VarHelpID = -1 Dim WithEvents tmpSink10 As SWbemSink Attribute tmpSink10.VB_VarHelpID = -1 Dim WithEvents tmpSink11 As SWbemSink Attribute tmpSink11.VB_VarHelpID = -1 Dim WithEvents tmpSink12 As SWbemSink Attribute tmpSink12.VB_VarHelpID = -1 Dim WithEvents tmpSink13 As SWbemSink Attribute tmpSink13.VB_VarHelpID = -1 Dim WithEvents tmpSink14 As SWbemSink Attribute tmpSink14.VB_VarHelpID = -1 Dim WithEvents tmpSink15 As SWbemSink Attribute tmpSink15.VB_VarHelpID = -1 Dim WithEvents tmpSink16 As SWbemSink Attribute tmpSink16.VB_VarHelpID = -1 Dim WithEvents tmpSink17 As SWbemSink Attribute tmpSink17.VB_VarHelpID = -1 Dim obj As SWbemObject Dim context As SWbemNamedValueSet Dim tmpContext As SWbemNamedValueSet Dim services As SWbemServices Dim locator As SWbemLocator Dim myimage As Boolean Private Sub AddContext_Click() Dim res As SWbemNamedValue Set res = context.Add(ContextName.Text, ContextValue.Text) ContextList.AddItem (ContextName.Text & "=" & ContextValue.Text) End Sub Private Sub CancelButton_Click() someSink.Cancel End Sub Private Sub Cancelc_Click() classSink.Cancel End Sub Private Sub classSink_OnCompleted(ByVal hResult As WbemScripting.WbemErrorEnum, ByVal pErrorObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Dim str As String GetErrorString hResult, str Call DisplayContext("OnCompleted(" & str & ") ", pAsyncContext) Call HandleErrors(hResult, "", pErrorObject) End Sub Private Sub classSink_OnObjectPut(ByVal pObjectPath As WbemScripting.ISWbemObjectPath, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Call DisplayContext("OnObjectPut", pAsyncContext) ObjectPathLabel.Caption = pObjectPath.path End Sub Private Sub classSink_OnObjectReady(ByVal pObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Call DisplayContext("OnObjectReady", pAsyncContext) List1.AddItem (pObject.Path_.Class) End Sub Private Sub classSink_OnProgress(ByVal upperBound As Long, ByVal current As Long, ByVal message As String, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Call DisplayContext("OnProgress", pAsyncContext) MsgBox ("OnProgress called - upper: " & upperBound & " current: " & current & " str: " & message) End Sub Private Sub Command1_Click() Dim myenum As Object Dim obj As SWbemObject Begin On Error GoTo ErrorHandler Set myenum = services.ExecQuery(QueryBox.Text) For Each obj In myenum List1.AddItem (obj.Path_.RelPath) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command10_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.SubclassesOfAsync classSink, "Cim_LogicalDevice", , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Cim_LogicalDevice") obj.SubclassesAsync_ classSink, , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command11_Click() Dim myenum As Object Dim computer As SWbemObject Begin On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.AssociatorsOf("Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices") Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") Set myenum = obj.Associators_("Win32_SystemDevices") End If For Each computer In myenum List1.AddItem (computer.Path_.Class) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command12_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.AssociatorsOfAsync classSink, "Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices", , , , , , , , , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") obj.AssociatorsAsync_ classSink, "Win32_SystemDevices", , , , , , , , , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command13_Click() Dim myenum As Object Dim computer As SWbemObject Begin On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.ReferencesTo("Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices") Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") Set myenum = obj.References_("Win32_SystemDevices") End If For Each computer In myenum List1.AddItem (computer.Path_.Class) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command14_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.ReferencesToAsync classSink, "Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices", , , , , , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") obj.ReferencesAsync_ classSink, "Win32_SystemDevices", , , , , , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command15_Click() Dim myenum As Object Dim ev As SWbemObject Begin On Error GoTo ErrorHandler Set myenum = services.ExecNotificationQuery("select * from __InstanceCreationEvent where TargetInstance isa ""Rogers""") For Each ev In myenum List1.AddItem (ev.Path_.Class) Exit For Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command16_Click() Begin On Error GoTo ErrorHandler services.ExecNotificationQueryAsync classSink, "select * from __InstanceCreationEvent where TargetInstance isa ""Rogers""", , , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command17_Click() Dim rogers As SWbemObject Dim path As SWbemObjectPath Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers.num=1") rogers.Dummy = rogers.Dummy + 1 Set path = rogers.Put_ Status.Caption = "Completed" ObjectPathLabel.Caption = path.path Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command18_Click() Dim rogers As SWbemObject Dim result As Object Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers.num=1") rogers.Dummy = rogers.Dummy + 1 rogers.PutAsync_ someSink, , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command19_Click() Dim rogers As SWbemObject Dim path As SWbemObjectPath Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers") Set path = rogers.Put_ Status.Caption = "Completed" ObjectPathLabel.Caption = path.path Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command2_Click() Begin On Error GoTo ErrorHandler services.ExecQueryAsync someSink, QueryBox.Text, , , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command20_Click() Dim rogers As SWbemObject Dim result As Object Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers") rogers.Dummy = rogers.Dummy + 1 rogers.PutAsync_ someSink, , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command3_Click() Dim disk As SWbemObject Begin On Error GoTo ErrorHandler Set disk = services.Get("Win32_LogicalDisk.DeviceID=""C:""") List1.AddItem (disk.DeviceID) Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command4_Click() Dim result As Object Begin On Error GoTo ErrorHandler services.GetAsync someSink, "Win32_LogicalDisk.DeviceID=""C:""", , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command5_Click() Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.Delete ("Rogers.num=1") Else List1.AddItem ("Object Operation") Set obj = services.Get("Rogers.num=1") obj.Delete_ End If Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command6_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.DeleteAsync someSink, "Rogers.num=1", , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Rogers.num=1") obj.DeleteAsync_ someSink, , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command7_Click() Begin On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.InstancesOf("Win32_LogicalDisk") Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk") Set myenum = obj.Instances_ End If For Each disk In myenum List1.AddItem (disk.DeviceID) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command8_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.InstancesOfAsync someSink, "Win32_LogicalDisk", , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk") obj.InstancesAsync_ someSink, , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command9_Click() Begin Dim myClass As SWbemObject On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.SubclassesOf("Cim_LogicalDevice") Else List1.AddItem ("Object Operation") Set obj = services.Get("Cim_LogicalDevice") Set myenum = obj.Subclasses_ End If For Each myClass In myenum List1.AddItem (myClass.Path_.Class) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub DeleteContext_Click() context.DeleteAll ContextList.Clear End Sub Private Sub Form_Load() 'Set services = GetObject("WinMgmts:") Set locator = CreateObject("WbemScripting.SWbemLocator") Set services = locator.ConnectServer() services.Security_.ImpersonationLevel = wbemImpersonationLevelImpersonate Set someSink = New SWbemSink Set classSink = New SWbemSink Set context = New SWbemNamedValueSet On Error GoTo ErrorHandler Set tmpSink1 = someSink Set tmpSink2 = someSink Set tmpSink3 = someSink Set tmpSink4 = someSink Set tmpSink5 = someSink Set tmpSink6 = someSink Set tmpSink7 = someSink Set tmpSink8 = someSink Set tmpSink9 = someSink Set tmpSink10 = someSink Set tmpSink11 = someSink Set tmpSink12 = someSink Set tmpSink13 = someSink Set tmpSink14 = someSink Set tmpSink15 = someSink Set tmpSink16 = someSink Set tmpSink17 = someSink ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) myimage = True End Sub Private Sub someSink_OnCompleted(ByVal hResult As WbemScripting.WbemErrorEnum, ByVal pErrorObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Dim str As String GetErrorString hResult, str Call DisplayContext("OnCompleted(" & str & ") ", pAsyncContext) Call HandleErrors(hResult, "", pErrorObject) End Sub Private Sub someSink_OnObjectPut(ByVal pObjectPath As WbemScripting.ISWbemObjectPath, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) DisplayContext "OnObjectPut", pAsyncContext ObjectPathLabel.Caption = pObjectPath.path End Sub Private Sub someSink_OnObjectReady(ByVal pObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) DisplayContext "OnObjectReady", pAsyncContext List1.AddItem (pObject.Path_.RelPath) End Sub Private Sub someSink_OnProgress(ByVal upperBound As Long, ByVal current As Long, ByVal message As String, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) DisplayContext "OnProgress", pAsyncContext MsgBox ("OnProgress called - upper: " & upperBound & " current: " & current & " str: " & message) End Sub Private Sub Timer1_Timer() If myimage = True Then Image1.Picture = Image2.Picture myimage = False Else Image1.Picture = Image3.Picture myimage = True End If End Sub Private Sub HandleErrors(ByVal hResult As Long, ByVal str As String, ByVal pErrorObject As WbemScripting.ISWbemObject) Dim tmpStr As String Status.Caption = "Completed" LastError.Caption = hResult GetErrorString hResult, tmpStr LastErrorString.Caption = tmpStr End Sub Private Sub GetErrorString(ByVal hResult As Long, ByRef str As String) If (hResult = 0) Then str = "Success" ElseIf (str = "") Then Select Case hResult Case WbemErrorEnum.wbemErrFailed str = "wbemErrFailed" Case WbemErrorEnum.wbemErrNotFound str = "wbemErrNotFound" Case WbemErrorEnum.wbemErrAccessDenied str = "wbemErrAccessDenied" Case WbemErrorEnum.wbemErrProviderFailure str = "wbemErrProviderFailure" Case WbemErrorEnum.wbemErrTypeMismatch str = "wbemErrTypeMismatch" Case WbemErrorEnum.wbemErrOutOfMemory str = "wbemErrOutOfMemory" Case WbemErrorEnum.wbemErrInvalidContext str = "wbemErrInvalidContext" Case WbemErrorEnum.wbemErrInvalidParameter str = "wbemErrInvalidParameter" Case WbemErrorEnum.wbemErrNotAvailable str = "wbemErrNotAvailable" Case WbemErrorEnum.wbemErrCriticalError str = "wbemErrCriticalError" Case WbemErrorEnum.wbemErrInvalidStream str = "wbemErrInvalidStream" Case WbemErrorEnum.wbemErrNotSupported str = "wbemErrNotSupported" Case WbemErrorEnum.wbemErrInvalidSuperclass str = "wbemErrInvalidSuperclass" Case WbemErrorEnum.wbemErrInvalidNamespace str = "wbemErrInvalidNamespace" Case WbemErrorEnum.wbemErrInvalidObject str = "wbemErrInvalidObject" Case WbemErrorEnum.wbemErrInvalidClass str = "wbemErrInvalidClass" Case WbemErrorEnum.wbemErrProviderNotFound str = "wbemErrProviderNotFound" Case WbemErrorEnum.wbemErrInvalidProviderRegistration str = "wbemErrInvalidProviderRegistration" Case WbemErrorEnum.wbemErrProviderLoadFailure str = "wbemErrProviderLoadFailure" Case WbemErrorEnum.wbemErrInitializationFailure str = "wbemErrInitializationFailure" Case WbemErrorEnum.wbemErrTransportFailure str = "wbemErrTransportFailure" Case WbemErrorEnum.wbemErrInvalidOperation str = "wbemErrInvalidOperation" Case WbemErrorEnum.wbemErrInvalidQuery str = "wbemErrInvalidQuery" Case WbemErrorEnum.wbemErrInvalidQueryType str = "wbemErrInvalidQueryType" Case WbemErrorEnum.wbemErrAlreadyExists str = "wbemErrAlreadyExists" Case WbemErrorEnum.wbemErrOverrideNotAllowed str = "wbemErrOverrideNotAllowed" Case WbemErrorEnum.wbemErrPropagatedQualifier str = "wbemErrPropagatedQualifier" Case WbemErrorEnum.wbemErrPropagatedProperty str = "wbemErrPropagatedProperty" Case WbemErrorEnum.wbemErrUnexpected str = "wbemErrUnexpected" Case WbemErrorEnum.wbemErrIllegalOperation str = "wbemErrIllegalOperation" Case WbemErrorEnum.wbemErrCannotBeKey str = "wbemErrCannotBeKey" Case WbemErrorEnum.wbemErrIncompleteClass str = "wbemErrIncompleteClass" Case WbemErrorEnum.wbemErrInvalidSyntax str = "wbemErrInvalidSyntax" Case WbemErrorEnum.wbemErrNondecoratedObject str = "wbemErrNondecoratedObject" Case WbemErrorEnum.wbemErrReadOnly str = "wbemErrReadOnly" Case WbemErrorEnum.wbemErrProviderNotCapable str = "wbemErrProviderNotCapable" Case WbemErrorEnum.wbemErrClassHasChildren str = "wbemErrClassHasChildren" Case WbemErrorEnum.wbemErrClassHasInstances str = "wbemErrClassHasInstances" Case WbemErrorEnum.wbemErrQueryNotImplemented str = "wbemErrQueryNotImplemented" Case WbemErrorEnum.wbemErrIllegalNull str = "wbemErrIllegalNull" Case WbemErrorEnum.wbemErrInvalidQualifierType str = "wbemErrInvalidQualifierType" Case WbemErrorEnum.wbemErrInvalidPropertyType str = "wbemErrInvalidPropertyType" Case WbemErrorEnum.wbemErrValueOutOfRange str = "wbemErrValueOutOfRange" Case WbemErrorEnum.wbemErrCannotBeSingleton str = "wbemErrCannotBeSingleton" Case WbemErrorEnum.wbemErrInvalidCimType str = "wbemErrInvalidCimType" Case WbemErrorEnum.wbemErrInvalidMethod str = "wbemErrInvalidMethod" Case WbemErrorEnum.wbemErrInvalidMethodParameters str = "wbemErrInvalidMethodParameters" Case WbemErrorEnum.wbemErrSystemProperty str = "wbemErrSystemProperty" Case WbemErrorEnum.wbemErrInvalidProperty str = "wbemErrInvalidProperty" Case WbemErrorEnum.wbemErrCallCancelled str = "wbemErrCallCancelled" Case WbemErrorEnum.wbemErrShuttingDown str = "wbemErrShuttingDown" Case WbemErrorEnum.wbemErrPropagatedMethod str = "wbemErrPropagatedMethod" Case WbemErrorEnum.wbemErrUnsupportedParameter str = "wbemErrUnsupportedParameter" Case WbemErrorEnum.wbemErrMissingParameter str = "wbemErrMissingParameter" Case WbemErrorEnum.wbemErrInvalidParameterId str = "wbemErrInvalidParameterId" Case WbemErrorEnum.wbemErrNonConsecutiveParameterIds str = "wbemErrNonConsecutiveParameterIds" Case WbemErrorEnum.wbemErrParameterIdOnRetval str = "wbemErrParameterIdOnRetval" Case WbemErrorEnum.wbemErrInvalidObjectPath str = "wbemErrInvalidObjectPath" Case WbemErrorEnum.wbemErrOutOfDiskSpace str = "wbemErrOutOfDiskSpace" Case WbemErrorEnum.wbemErrRegistrationTooBroad str = "wbemErrRegistrationTooBroad" Case WbemErrorEnum.wbemErrRegistrationTooPrecise str = "wbemErrRegistrationTooPrecise" Case WbemErrorEnum.wbemErrTimedout str = "wbemErrTimedout" Case Else str = hResult End Select End If End Sub Private Sub Begin() List1.Clear ContextResults.Clear Status.Caption = "In Progress" ObjectPathLabel.Caption = "Null" If (context.Count = 0) Then Set tmpContext = Nothing Else Set tmpContext = context End If End Sub Private Sub DisplayContext(ByVal str As String, Optional ByVal asyncContext As WbemScripting.ISWbemNamedValueSet) Dim i As SWbemNamedValue ContextResults.AddItem (str) If asyncContext Is Nothing Then ContextResults.AddItem ("Empty") Else For Each i In asyncContext ContextResults.AddItem (i.Name & "=" & i.Value) Next End If End Sub
<reponame>LaudateCorpus1/RosettaCodeData Public Sub circles() tests = [{0.1234, 0.9876, 0.8765, 0.2345, 2.0; 0.0000, 2.0000, 0.0000, 0.0000, 1.0; 0.1234, 0.9876, 0.1234, 0.9876, 2.0; 0.1234, 0.9876, 0.8765, 0.2345, 0.5; 0.1234, 0.9876, 0.1234, 0.9876, 0.0}] For i = 1 To UBound(tests) x1 = tests(i, 1) y1 = tests(i, 2) x2 = tests(i, 3) y2 = tests(i, 4) R = tests(i, 5) xd = x2 - x1 yd = y1 - y2 s2 = xd * xd + yd * yd sep = Sqr(s2) xh = (x1 + x2) / 2 yh = (y1 + y2) / 2 Dim txt As String If sep = 0 Then txt = "same points/" & IIf(R = 0, "radius is zero", "infinite solutions") Else If sep = 2 * R Then txt = "opposite ends of diameter with centre " & xh & ", " & yh & "." Else If sep > 2 * R Then txt = "too far apart " & sep & " > " & 2 * R Else md = Sqr(R * R - s2 / 4) xs = md * xd / sep ys = md * yd / sep txt = "{" & Format(xh + ys, "0.0000") & ", " & Format(yh + xs, "0.0000") & _ "} and {" & Format(xh - ys, "0.0000") & ", " & Format(yh - xs, "0.0000") & "}" End If End If End If Debug.Print "points " & "{" & x1 & ", " & y1 & "}" & ", " & "{" & x2 & ", " & y2 & "}" & " with radius " & R & " ==> " & txt Next i End Sub
VERSION 5.00 Begin VB.Form Form1 Caption = "Form1" ClientHeight = 3675 ClientLeft = 120 ClientTop = 465 ClientWidth = 5580 LinkTopic = "Form1" ScaleHeight = 245 ScaleMode = 3 'Pixel ScaleWidth = 372 StartUpPosition = 3 'Windows Default Begin VB.PictureBox Pic AutoRedraw = -1 'True AutoSize = -1 'True Height = 3015 Left = 0 ScaleHeight = 197 ScaleMode = 3 'Pixel ScaleWidth = 253 TabIndex = 0 Top = 0 Width = 3855 End End Attribute VB_Name = "Form1" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Const RED As Integer = &HF800 Const GREEN As Integer = &H7E0 Const BLUE As Integer = &H1F Private Function ConvertRGB888ToRGB565(RGB888 As Long) As Integer Dim RGB888Val() As Byte RGB888Val = GetRGB(RGB888) Dim R As Byte Dim G As Byte Dim B As Byte R = RGB888Val(0) G = RGB888Val(1) B = RGB888Val(2) ConvertRGB888ToRGB565 = (SHL16(R, 8) And RED) Or (SHL16(G, 3) And GREEN) Or (SHR16(B, 3) And BLUE) End Function Private Sub OpenOutputFile() Dim SplitPath() As String Dim OutputPath As String SplitPath = Split(VBA.Command$, ".") If UBound(SplitPath()) > 0 Then SplitPath(UBound(SplitPath())) = "SP" OutputPath = Join(SplitPath(), ".") Else OutputPath = VBA.Command$ & ".SP" End If On Error Resume Next Kill OutputPath On Error GoTo 0 Open OutputPath For Binary Access Write As #1 End Sub Private Sub CloseOutputFile() Close #1 End Sub Private Sub Form_Load() If VBA.Command$ = "" Then MsgBox "No input file!", vbCritical End End If On Error GoTo Err Set Pic.Picture = LoadPicture(VBA.Command$) OpenOutputFile Dim PicWidth As Integer Dim PicHeight As Integer PicWidth = Pic.ScaleWidth PicHeight = Pic.ScaleHeight Put #1, , PicWidth Put #1, , PicHeight Dim x As Long Dim y As Long For y = 0 To PicHeight - 1 For x = 0 To PicWidth - 1 Put #1, , ConvertRGB888ToRGB565(Pic.Point(x, y)) Next x Next y CloseOutputFile MsgBox "Done", vbInformation End Err: MsgBox Err.Description, vbCritical End End Sub
<reponame>MakeNowJust/quine Imports System Module Main Sub Main() Dim s As String = "Imports System{0}Module Main{0} Sub Main(){0} Dim s As String = {1}{2}{1}{0} Console.WriteLine(s,Chr(10),Chr(34),s){0} End Sub{0}End Module" Console.WriteLine(s,Chr(10),Chr(34),s) End Sub End Module
<gh_stars>10-100 Attribute VB_Name = "Errors" Option Explicit Const FACILITY_WIN32 As Long = 7 ' These are Win32 Errors. ' They are tested against returns from WIN32 APIS using these ' error codes, BUT They must be translated into COM Errors ' using the HRESULT_FROM_WIN32 function below when ' returning then from a COM Object Public Const ERROR_FILE_NOT_FOUND As Long = 2 Public Const ERROR_DISK_FULL As Long = 112 ' These Are COM Errors Public Const E_NOTIMPL As Long = &H80004001 Public Const E_FAIL As Long = &H80004005 Public Const E_INVALIDARG As Long = &H80070057 Public Const E_UNEXPECTED As Long = &H8000FFFF Public Const errBase As Long = vbObject + 9999 Public Const errContainsGarbageChar As Long = errBase + 1 Public Const errContainsStopSign As Long = errBase + 2 Public Const errContainsStopWord As Long = errBase + 3 Public Const errContainsOperatorShortcut As Long = errBase + 4 Public Const errContainsVerbalOperator As Long = errBase + 5 Public Const errAlreadyExists As Long = errBase + 6 Public Const errDoesNotExist As Long = errBase + 7 Public Const errTooLong As Long = errBase + 8 Public Const errMultiWord As Long = errBase + 9 Public Const errCancel As Long = errBase + 10 Public Const errRefNodeCannotBeDescendent As Long = errBase + 11 Public Const errDatabaseVersionIncompatible As Long = errBase + 12 Public Const errNotConfiguredForNavigateLink As Long = errBase + 13 Public Const errContainsQuote As Long = errBase + 14 Public Const errParentCannotBeLeaf As Long = errBase + 15 Public Const errBadKeywordsFormat As Long = errBase + 16 Public Const errNodeOrTopicAlreadyModified As Long = errBase + 17 Public Const errBadSpreadsheet As Long = errBase + 18 Public Const errOutOfOrderingNumbers As Long = errBase + 19 Public Const errNotPermittedForAuthoringGroup As Long = errBase + 20 Public Const errAuthoringGroupDiffers As Long = errBase + 21 Public Const errAuthoringGroupNotPresent As Long = errBase + 22 Public Const errVendorStringNotConfigured As Long = errBase + 23 Public Const errProductIdOrVersionMissing As Long = errBase + 24 Function HRESULT_FROM_WIN32(ByVal lngWin32Err As Long) As Long If (lngWin32Err <> 0) Then HRESULT_FROM_WIN32 = lngWin32Err And &HFFFF HRESULT_FROM_WIN32 = HRESULT_FROM_WIN32 Or (FACILITY_WIN32 * &H10000) HRESULT_FROM_WIN32 = HRESULT_FROM_WIN32 Or &H80000000 Else HRESULT_FROM_WIN32 = 0 End If End Function Public Sub DisplayDatabaseLockedError( _ ) MsgBox "The database is locked because another user is saving his/her changes. " & _ "Please try again later.", vbExclamation + vbOKOnly End Sub Public Sub DisplayDatabaseVersionError( _ ) MsgBox "The database version is incompatible.", vbExclamation + vbOKOnly End Sub Public Sub DisplayAuthoringGroupError( _ ) Select Case Err.Number Case errNotPermittedForAuthoringGroup MsgBox "Your Authoring Group does not have sufficient permissions to " & _ "perform this operation.", _ vbExclamation + vbOKOnly Case errAuthoringGroupDiffers MsgBox "You cannot modify something that was created in a different " & _ "Authoring Group.", _ vbExclamation + vbOKOnly Case errAuthoringGroupNotPresent MsgBox "The Database has not been configured with an Authoring Group.", _ vbExclamation + vbOKOnly End Select End Sub
on error resume next set l = CreateObject ("WbemScripting.SwbemLocator") set ns = l.Open ("root\cimv2") ns.filter_ = Array ("Win32_service") for each p in ns WScript.Echo p.Path_.Path next set os = ns.ExecQuery ("select * from win32_process go select * from win32_service") for each p in os WScript.Echo p.Name next
<reponame>LaudateCorpus1/RosettaCodeData 'N-queens problem - non recursive & structured - vbs - 24/02/2017 const l=15 dim a(),s(),u(): redim a(l),s(l),u(4l-2) for i=1 to l: a(i)=i: next for n=1 to l m=0 i=1 j=0 r=2n-1 Do i=i-1 j=j+1 p=0 q=-r Do i=i+1 u(p)=1 u(q+r)=1 z=a(j): a(j)=a(i): a(i)=z 'swap a(i),a(j) p=i-a(i)+n q=i+a(i)-1 s(i)=j j=i+1 Loop Until j>n Or u(p)<>0 Or u(q+r)<>0 If u(p)=0 Then If u(q+r)=0 Then m=m+1 'm: number of solutions 'x="": for k=1 to n: x=x&" "&a(k): next: msgbox x,,m End If End If j=s(i) Do While j>=n And i<>0 Do z=a(j): a(j)=a(i): a(i)=z 'swap a(i),a(j) j=j-1 Loop Until j<i i=i-1 p=i-a(i)+n q=i+a(i)-1 j=s(i) u(p)=0 u(q+r)=0 Loop Loop Until i=0 wscript.echo n &":"& m next 'n
'//+---------------------------------------------------------------------------- '// '// File: cab.frm '// '// Module: pbadmin.exe '// '// Synopsis: The options dialog in PBA '// '// Copyright (c) 1997-1999 Microsoft Corporation '// '// Author: quintinb Created Header 09/02/99 '// '//+---------------------------------------------------------------------------- VERSION 5.00 Object = "{F9043C88-F6F2-101A-A3C9-08002B2F49FB}#1.2#0"; "COMDLG32.OCX" Begin VB.Form frmCab BorderStyle = 3 'Fixed Dialog Caption = "options" ClientHeight = 2595 ClientLeft = 2775 ClientTop = 1545 ClientWidth = 5955 Icon = "cab.frx":0000 KeyPreview = -1 'True LinkTopic = "Form1" LockControls = -1 'True MaxButton = 0 'False MinButton = 0 'False PaletteMode = 1 'UseZOrder ScaleHeight = 2595 ScaleWidth = 5955 ShowInTaskbar = 0 'False WhatsThisButton = -1 'True WhatsThisHelp = -1 'True Begin VB.CommandButton Command1 Cancel = -1 'True Caption = "cancel" Height = 375 Left = 4425 TabIndex = 7 Top = 2070 WhatsThisHelpID = 10040 Width = 1335 End Begin VB.CommandButton cmbcab Caption = "ok" Default = -1 'True Height = 375 Left = 4410 TabIndex = 6 Top = 1530 WhatsThisHelpID = 10030 Width = 1335 End Begin VB.TextBox txtUrl Height = 285 Left = 225 MaxLength = 100 TabIndex = 1 Top = 495 WhatsThisHelpID = 70000 Width = 5520 End Begin VB.TextBox UIDText Height = 315 Left = 210 MaxLength = 64 TabIndex = 3 Top = 1350 WhatsThisHelpID = 70010 Width = 2730 End Begin VB.TextBox PWDText Height = 330 IMEMode = 3 'DISABLE Left = 225 MaxLength = 64 PasswordChar = "*" TabIndex = 5 Top = 2085 WhatsThisHelpID = 70020 Width = 2715 End Begin MSComDlg.CommonDialog CommonDialog1 Left = 2940 Top = -30 _ExtentX = 847 _ExtentY = 847 _Version = 393216 End Begin VB.Label ServerLabel BackStyle = 0 'Transparent Caption = "server" Height = 255 Left = 210 TabIndex = 0 Top = 240 WhatsThisHelpID = 70000 Width = 5520 End Begin VB.Label UIDLabel BackStyle = 0 'Transparent Caption = "uid" Height = 255 Left = 225 TabIndex = 2 Top = 1125 WhatsThisHelpID = 70010 Width = 2790 End Begin VB.Label pwdLabel BackStyle = 0 'Transparent Caption = "pwd" Height = 270 Left = 225 TabIndex = 4 Top = 1815 WhatsThisHelpID = 70020 Width = 2670 End End Attribute VB_Name = "frmcab" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Dim configuration As Recordset Function LoadOptionsRes() Dim cRef As Integer On Error GoTo LoadErr cRef = 5200 Me.Caption = LoadResString(cRef + 25) & " " & gsCurrentPB ServerLabel.Caption = LoadResString(cRef + 21) UIDLabel.Caption = LoadResString(cRef + 22) pwdLabel.Caption = LoadResString(cRef + 23) cmbcab.Caption = LoadResString(1002) Command1.Caption = LoadResString(1003) ' set fonts SetFonts Me On Error GoTo 0 Exit Function LoadErr: Exit Function End Function Function TrimURL(URL As String) As String URL = Trim(URL) TrimURL = URL If LCase(Left(URL, 4)) = "ftp:" Then TrimURL = Right(URL, Len(URL) - 4) End If If LCase(Left(URL, 5)) = "http:" Then TrimURL = Right(URL, Len(URL) - 5) End If Do While Left(TrimURL, 1) = "/" TrimURL = Right(TrimURL, Len(TrimURL) - 1) Loop Do While Left(TrimURL, 1) = "\" TrimURL = Right(TrimURL, Len(TrimURL) - 1) Loop End Function Private Sub cmbcab_Click() Dim rt As Integer Screen.MousePointer = 11 rt = SetOptions(txtUrl.Text, UIDText.Text, PWDText.Text) If rt = 1 Then UIDText.SetFocus ElseIf rt = 2 Then PWDText.SetFocus End If Screen.MousePointer = 0 Unload Me Exit Sub ErrTrap: Screen.MousePointer = 0 MsgBox LoadResString(6056) & Chr(13) & Chr(13) & Err.Description, vbExclamation Exit Sub Exit Sub End Sub Private Sub Command1_Click() Unload Me End Sub Private Sub Form_Activate() txtUrl.SetFocus End Sub Private Sub Form_KeyPress(KeyAscii As Integer) CheckChar KeyAscii End Sub Private Sub Form_Load() Dim RS, configuration As Recordset Dim i As Integer Dim myPos As Integer On Error GoTo LoadErr If gsCurrentPB = "" Then Exit Sub End If CenterForm Me, Screen 'SSTab1.Tab = 0 LoadOptionsRes Set configuration = gsyspb.OpenRecordset("Configuration", dbOpenSnapshot) If configuration.RecordCount <> 0 Then If Not IsNull(configuration!URL) Then txtUrl.Text = configuration!URL End If If Not IsNull(configuration!ServerPWD) Then PWDText.Text = configuration!ServerPWD End If If Not IsNull(configuration!ServerUID) Then UIDText.Text = configuration!ServerUID End If End If configuration.Close Set configuration = Nothing Screen.MousePointer = 0 Exit Sub LoadErr: Screen.MousePointer = 0 MsgBox LoadResString(6056) & Chr(13) & Chr(13) & Err.Description, vbExclamation End Sub Private Sub LoadList(list As Control, sTableName As String, sName As String, sID As String) Dim RS As Recordset list.Clear Set Gsyspbpost = DBEngine.Workspaces(0).OpenDatabase(locPath + "pbserver.mdb") Set RS = Gsyspbpost.OpenRecordset("SELECT " & sName & "," & sID & " FROM " & sTableName) While Not RS.EOF list.AddItem RS(sName) list.ItemData(list.NewIndex) = RS(sID) RS.MoveNext Wend RS.Close Gsyspbpost.Close End Sub Sub selectListItem(list As Control, ByVal ID As Long) Dim i As Integer For i = 0 To list.ListCount - 1 If list.ItemData(i) = ID Then list.Selected(i) = True End If Next i End Sub Private Sub Form_QueryUnload(Cancel As Integer, UnloadMode As Integer) If UnloadMode = vbFormControlMenu Then Cancel = False Command1_Click End If End Sub Private Sub Form_Unload(Cancel As Integer) Set configuration = Nothing End Sub Private Sub PWDText_GotFocus() SelectText PWDText End Sub Private Sub txtUrl_GotFocus() SelectText txtUrl End Sub Private Sub txtUrl_KeyPress(KeyAscii As Integer) Select Case KeyAscii Case 32 'space KeyAscii = 0 Beep 'MsgBox LoadResString(6018), vbInformation End Select End Sub Private Sub UIDText_GotFocus() SelectText UIDText End Sub Private Sub UIDText_KeyPress(KeyAscii As Integer) Select Case KeyAscii '0-9 a-z A-Z Bkspc ctrl-C ctrl-V 'Case 48 To 57, 97 To 122, 65 To 90, 8, 3, 22 ' do nothing ' upper case 'Case 48 To 57 ' KeyAscii = KeyAscii + 32 ' shift to lower case 'Case Else ' KeyAscii = 0 ' Beep ' MsgBox LoadResString(6018), vbInformation Case 32 'space KeyAscii = 0 Beep Case Else 'do nothing End Select End Sub
<filename>Task/Function-composition/VBScript/function-composition-1.vb option explicit class closure private composition sub compose( f1, f2 ) composition = f2 & "(" & f1 & "(p1))" end sub public default function apply( p1 ) apply = eval( composition ) end function public property get formula formula = composition end property end class
<reponame>mullikine/RosettaCodeData<filename>Task/Stable-marriage-problem/VBA/stable-marriage-problem-1.vba Sub M_snb() c00 = "_abe abi eve cath ivy jan dee fay bea hope gay " & _ "_bob cath hope abi dee eve fay bea jan ivy gay " & _ "_col hope eve abi dee bea fay ivy gay cath jan " & _ "_dan ivy fay dee gay hope eve jan bea cath abi " & _ "_ed jan dee bea cath fay eve abi ivy hope gay " & _ "_fred bea abi dee gay eve ivy cath jan hope fay " & _ "_gav gay eve ivy bea cath abi dee hope jan fay " & _ "_hal abi eve hope fay ivy cath jan bea gay dee " & _ "_ian hope cath dee gay bea abi fay ivy jan eve " & _ "_jon abi fay jan gay eve bea dee cath ivy hope " & _ "_abi bob fred jon gav ian abe dan ed col hal " & _ "_bea bob abe col fred gav dan ian ed jon hal " & _ "_cath fred bob ed gav hal col ian abe dan jon " & _ "_dee fred jon col abe ian hal gav dan bob ed " & _ "_eve jon hal fred dan abe gav col ed ian bob " & _ "_fay bob abe ed ian jon dan fred gav col hal " & _ "_gay jon gav hal fred bob abe col ed dan ian " & _ "_hope gav jon bob abe ian dan hal ed col fred " & _ "_ivy ian col hal gav fred bob abe ed jon dan " & _ "_jan ed hal gav abe bob jon col ian fred dan " sn = Filter(Filter(Split(c00), "_"), "-", 0) Do c01 = Mid(c00, InStr(c00, sn(0) & " ")) st = Split(Left(c01, InStr(Mid(c01, 2), "_"))) For j = 1 To UBound(st) - 1 If InStr(c00, "_" & st(j) & " ") > 0 Then c00 = Replace(Replace(c00, sn(0), sn(0) & "-" & st(j)), "_" & st(j), "_" & st(j) & "." & Mid(sn(0), 2)) Exit For Else c02 = Filter(Split(c00, "_"), st(j) & ".")(0) c03 = Split(Split(c02)(0), ".")(1) If InStr(c02, " " & Mid(sn(0), 2) & " ") < InStr(c02, " " & c03 & " ") Then c00 = Replace(Replace(Replace(c00, c03 & "-" & st(j), c03), sn(0), sn(0) & "-" & st(j)), "_" & st(j), "_" & st(j) & "." & Mid(sn(0), 2)) Exit For End If End If Next sn = Filter(Filter(Filter(Split(c00), "_"), "-", 0), ".", 0) Loop Until UBound(sn) = -1 MsgBox Replace(Join(Filter(Split(c00), "-"), vbLf), "_", "") End Sub
<gh_stars>1-10 Dim onlyInstance as Boolean onlyInstance = not App.PrevInstance
For k = 1 To 5 count = 0 increment = 1 WScript.StdOut.Write "K" & k & ": " Do Until count = 10 If PrimeFactors(increment) = k Then WScript.StdOut.Write increment & " " count = count + 1 End If increment = increment + 1 Loop WScript.StdOut.WriteLine Next Function PrimeFactors(n) PrimeFactors = 0 arrP = Split(ListPrimes(n)," ") divnum = n Do Until divnum = 1 For i = 0 To UBound(arrP)-1 If divnum = 1 Then Exit For ElseIf divnum Mod arrP(i) = 0 Then divnum = divnum/arrP(i) PrimeFactors = PrimeFactors + 1 End If Next Loop End Function Function IsPrime(n) If n = 2 Then IsPrime = True ElseIf n <= 1 Or n Mod 2 = 0 Then IsPrime = False Else IsPrime = True For i = 3 To Int(Sqr(n)) Step 2 If n Mod i = 0 Then IsPrime = False Exit For End If Next End If End Function Function ListPrimes(n) ListPrimes = "" For i = 1 To n If IsPrime(i) Then ListPrimes = ListPrimes & i & " " End If Next End Function
'************************************************************************* 'This script tests the manipulation of qualifier values, in the case that the 'qualifier is an array type '************************************************************************* Set Service = GetObject("winmgmts:root/default") On Error Resume Next Set aClass = Service.Get() aClass.Path_.Class = "ARRAYQUAL00" aClass.Qualifiers_.Add "q1", Array (1, 20, 3) str = "The initial value of q1 is [1,20,3]: {" for x=LBound(aClass.Qualifiers_("q1")) to UBound(aClass.Qualifiers_("q1")) str = str & aClass.Qualifiers_("q1")(x) if x <> UBound(aClass.Qualifiers_("q1")) Then str = str & ", " End if next str = str & "}" WScript.Echo str WScript.Echo "" 'Verify we can report the value of an element of the qualifier value v = aClass.Qualifiers_("q1") WScript.Echo "By indirection the first element of q1 has value [1]:",v(0) 'Verify we can report the value directly WScript.Echo "By direct access the first element of q1 has value [1]:", aClass.Qualifiers_("q1")(0) 'Verify we can set the value of a single qualifier value element aClass.Qualifiers_("q1")(1) = 11 WScript.Echo "After direct assignment the second element of q1 has value [11]:", aClass.Qualifiers_("q1")(1) Set Qualifier = aClass.Qualifiers_("q1") Qualifier.Value(2) = 37 WScript.Echo "After direct assignment the third element of q1 has value [37]:", aClass.Qualifiers_("q1")(2) 'Verify we can set the value of a single qualifier value element Set v = aClass.Qualifiers_("q1") v(1) = 345 WScript.Echo "After indirect assignment the first element of q1 has value [345]:", aClass.Qualifiers_("q1")(1) 'Verify we can set the value of an entire qualifier value aClass.Qualifiers_("q1") = Array (5, 34, 178871) WScript.Echo "After direct array assignment the second element of q1 has value [34]:", aClass.Qualifiers_("q1")(1) str = "After direct assignment the entire value of q1 is [5,34,178871] {" for x=LBound(aClass.Qualifiers_("q1")) to UBound(aClass.Qualifiers_("q1")) str = str & aClass.Qualifiers_("q1")(x) if x <> UBound(aClass.Qualifiers_("q1")) Then str = str & ", " End if next str = str & "}" WScript.Echo str aClass.Put_ () if Err <> 0 Then WScript.Echo Err.Description Err.Clear End if
<gh_stars>1-10 Function parse_ip(addr) 'ipv4 pattern Set ipv4_pattern = New RegExp ipv4_pattern.Global = True ipv4_pattern.Pattern = "(\d{1,3}\.){3}\d{1,3}" 'ipv6 pattern Set ipv6_pattern = New RegExp ipv6_pattern.Global = True ipv6_pattern.Pattern = "([0-9a-fA-F]{0,4}:){2}[0-9a-fA-F]{0,4}" 'test if address is ipv4 If ipv4_pattern.Test(addr) Then port = Split(addr,":") octet = Split(port(0),".") ipv4_hex = "" For i = 0 To UBound(octet) If octet(i) <= 255 And octet(i) >= 0 Then ipv4_hex = ipv4_hex & Right("0" & Hex(octet(i)),2) Else ipv4_hex = "Erroneous Address" Exit For End If Next parse_ip = "Test Case: " & addr & vbCrLf &_ "Address: " & ipv4_hex & vbCrLf If UBound(port) = 1 Then If port(1) <= 65535 And port(1) >= 0 Then parse_ip = parse_ip & "Port: " & port(1) & vbCrLf Else parse_ip = parse_ip & "Port: Invalid" & vbCrLf End If End If End If 'test if address is ipv6 If ipv6_pattern.Test(addr) Then parse_ip = "Test Case: " & addr & vbCrLf port_v6 = "Port: " ipv6_hex = "" 'check and extract port information if any If InStr(1,addr,"[") Then 'extract the port port_v6 = port_v6 & Mid(addr,InStrRev(addr,"]")+2,Len(addr)-Len(Mid(addr,1,InStrRev(addr,"]")+1))) 'extract the address addr = Mid(addr,InStrRev(addr,"[")+1,InStrRev(addr,"]")-(InStrRev(addr,"[")+1)) End If word = Split(addr,":") word_count = 0 For i = 0 To UBound(word) If word(i) = "" Then If i < UBound(word) Then If Int((7-(i+1))/2) = 1 Then k = 1 ElseIf UBound(word) < 6 Then k = Int((7-(i+1))/2) ElseIf UBound(word) >= 6 Then k = Int((7-(i+1))/2)-1 End If For j = 0 To k ipv6_hex = ipv6_hex & "0000" word_count = word_count + 1 Next Else For j = 0 To (7-word_count) ipv6_hex = ipv6_hex & "0000" Next End If Else ipv6_hex = ipv6_hex & Right("0000" & word(i),4) word_count = word_count + 1 End If Next parse_ip = parse_ip & "Address: " & ipv6_hex &_ vbCrLf & port_v6 & vbCrLf End If 'test if the address in invalid If ipv4_pattern.Test(addr) = False And ipv6_pattern.Test(addr) = False Then parse_ip = "Test Case: " & addr & vbCrLf &_ "Address: Invalid Address" & vbCrLf End If End Function 'Testing the function ip_arr = Array("127.0.0.1","127.0.0.1:80","::1",_ "[::1]:80","fc00:e968:6179::de52:7100:93e3","[2605:2fc00:e968:6179::de52:7100:93e3]:80","RosettaCode") For n = 0 To UBound(ip_arr) WScript.StdOut.Write parse_ip(ip_arr(n)) & vbCrLf Next
100 REM ************************** 110 REM MAIN TEST 120 REM ************************ 121 REM 122 REM 125 REM ******* CLEAR ***** 130 CLEAR 135 REM ******* RETURN ***** 140 RETURN 145 REM ******* LIST ***** 150 LIST 155 REM ******* RUN ***** 160 RUN 165 REM ******* END ***** 170 END 175 REM ******* GOTO ***** 180 GOTO 100 185 REM ******* GOSUB ***** 190 GOSUB 100 195 REM ******* LET ***** 180 LET x = 12 185 REM ******* INPUT ***** 200 INPUT "sdsdsd";y 225 REM ******* IF ***** 220 IF x=13 THEN PRINT "xx" 230 REM ******* IF with assign ***** 240 IF x=13 THEN LET y=12 245 IF x=13 THEN y=12 245 REM ******* PRINT ***** 250 PRINT "xx" 260 REM ******* FOR ***** 270 FOR i=10 TO 15 STEP 20 275 FOR i=10 TO 15 260 REM ******* NEXT ***** 261 NEXT i 300 REM ******* DIM ***** 310 DIM j(14) 400 REM ******* SQR ***** 410 LET h = SQR(12) 420 REM ******* CHR ***** 430 LET h = CHR$(12) 440 REM ******* COLON TWO STATEMENTS ***** 450 PRINT "1" : PRINT "2" 460 REM ******* COLON COMMENT ***** 470 PRINT "1" : REM 480 PRINT "1" : REM 44 490 REM ******* NAKED ASSIGN ***** 500 j=77 490 REM ******* PRINT EXPRESSION ***** 510 PRINT CHR$ (7) 1000 TEXT 1010 HGR 490 REM ******* LEN ***** 520 ll = LEN("abc") 490 REM ******* CALL ***** 11 CALL 5010 490 REM ******* ASC ***** 520 ll = ASC("a") 490 REM ******* MID ***** 520 ll = MID$("abc",1,2) 490 REM ******* STRING VAR ***** 520 d$="sdsd" 490 REM ******* PLOT ***** 550 HPLOT 0,YS TO 279,YS 550 VPLOT 0,YS TO 279,YS 560 VPLOT 0,YS TO 279,YS 490 REM ******* PR ***** 1000 PR#1 1001 PR#2 490 REM ******* FLOATS ***** 20 XC = -0.5 : REM CENTER COORD X 30 YC = 0 : REM " " Y 40 S = 2 : REM SCALE 490 REM ******* NEQ ***** 40 IF N< > 0 GOTO 80 490 REM ******* TAB ******* 10 VTAB 6: HTAB 3
Option Base 1 Private Function pivotize(m As Variant) As Variant Dim n As Integer: n = UBound(m) Dim im() As Double ReDim im(n, n) For i = 1 To n For j = 1 To n im(i, j) = 0 Next j im(i, i) = 1 Next i For i = 1 To n mx = m(i, i) row_ = i For j = i To n If m(j, i) > mx Then mx = m(j, i) row_ = j End If Next j If i <> Row Then For j = 1 To n tmp = im(i, j) im(i, j) = im(row_, j) im(row_, j) = tmp Next j End If Next i pivotize = im End Function Private Function lu(a As Variant) As Variant Dim n As Integer: n = UBound(a) Dim l() As Double ReDim l(n, n) For i = 1 To n For j = 1 To n l(i, j) = 0 Next j Next i u = l p = pivotize(a) a2 = WorksheetFunction.MMult(p, a) For j = 1 To n l(j, j) = 1# For i = 1 To j sum1 = 0# For k = 1 To i sum1 = sum1 + u(k, j) * l(i, k) Next k u(i, j) = a2(i, j) - sum1 Next i For i = j + 1 To n sum2 = 0# For k = 1 To j sum2 = sum2 + u(k, j) * l(i, k) Next k l(i, j) = (a2(i, j) - sum2) / u(j, j) Next i Next j Dim res(4) As Variant res(1) = a res(2) = l res(3) = u res(4) = p lu = res End Function Public Sub main() a = [{1, 3, 5; 2, 4, 7; 1, 1, 0}] Debug.Print "== a,l,u,p: ==" result = lu(a) For i = 1 To 4 For j = 1 To UBound(result(1)) For k = 1 To UBound(result(1), 2) Debug.Print result(i)(j, k), Next k Debug.Print Next j Debug.Print Next i a = [{11, 9,24, 2; 1, 5, 2, 6; 3,17,18, 1; 2, 5, 7, 1}] Debug.Print "== a,l,u,p: ==" result = lu(a) For i = 1 To 4 For j = 1 To UBound(result(1)) For k = 1 To UBound(result(1), 2) Debug.Print Format(result(i)(j, k), "0.#####"), Next k Debug.Print Next j Debug.Print Next i End Sub
Const MAX = 20 Const ITER = 1000000 Function expected(n As Long) As Double Dim sum As Double For i = 1 To n sum = sum + WorksheetFunction.Fact(n) / n ^ i / WorksheetFunction.Fact(n - i) Next i expected = sum End Function Function test(n As Long) As Double Dim count As Long Dim x As Long, bits As Long For i = 1 To ITER x = 1 bits = 0 Do While Not bits And x count = count + 1 bits = bits Or x x = 2 ^ (Int(n * Rnd())) Loop Next i test = count / ITER End Function Public Sub main() Dim n As Long Debug.Print " n avg. exp. (error%)" Debug.Print "== ====== ====== ========" For n = 1 To MAX av = test(n) ex = expected(n) Debug.Print Format(n, "@@"); " "; Format(av, "0.0000"); " "; Debug.Print Format(ex, "0.0000"); " ("; Format(Abs(1 - av / ex), "0.000%"); ")" Next n End Sub
Set objfso = CreateObject("Scripting.FileSystemObject") parent_folder = objfso.GetParentFolderName(WScript.ScriptFullName) & "\" Set objcsv = objfso.OpenTextFile(parent_folder & "in.csv",1,False) Set objhtml = objfso.OpenTextFile(paren_folder & "out.html",2,True) objhtml.Write(csv_to_html(objcsv.ReadAll)) objcsv.Close objhtml.Close Set objfso = Nothing Function csv_to_html(s) row = Split(s,vbCrLf) 'write the header tmp = "<html><head><head/><body><table border=1 cellpadding=10 cellspacing=0>" For i = 0 To UBound(row) field = Split(row(i),",") If i = 0 Then tmp = tmp & "<tr><th>" & replace_chars(field(0)) & "</th><th>" & replace_chars(field(1)) & "</th><tr>" Else tmp = tmp & "<tr><td>" & replace_chars(field(0)) & "</td><td>" & replace_chars(field(1)) & "</td><tr>" End If Next 'write the footer tmp = tmp & "</table></body></html>" csv_to_html = tmp End Function Function replace_chars(s) replace_chars = Replace(Replace(s,"<","<"),">",">") End Function
<reponame>robinkjoy/JSON2RTLRegFile ' Enumerations https://msdn.microsoft.com/en-us/library/office/aa211923(v=office.11).aspx Option Explicit Sub InsertRegTable(oWord, oRange, regStrings) With oRange .Paragraphs.Add With .Paragraphs(1) .Style = -3 .Range.Text = regStrings(0) End With .Paragraphs.Add With .Paragraphs(2) .Style = -1 End With End With oRange.Tables.Add oRange.Paragraphs(2).Range, 4, 5 Dim oTable Set oTable = oRange.Tables(1) ' Set border properties With oTable.Borders .InsideLineStyle = 1 .OutsideLineStyle = 1 End With ' Set table properties With oTable .Columns(1).Width = oWord.InchesToPoints(1.1) .Columns(2).Width = oWord.InchesToPoints(0.5) .Columns(3).Width = oWord.InchesToPoints(0.5) .Columns(4).Width = oWord.InchesToPoints(1.1) .Columns(5).Width = oWord.InchesToPoints(3.2) Dim row For Each row In .Rows row.Cells.VerticalAlignment = 1 Next End With ' Insert table contents SetHeader oTable, 1, 1, "Register Name" oTable.Cell(1, 2).Range.Text = regStrings(1) SetHeader oTable, 2, 1, "Offset" oTable.Cell(2, 2).Range.Text = regStrings(2) SetHeader oTable, 3, 1, "Fields" SetHeader oTable, 4, 1, "Field Name" SetHeader oTable, 4, 2, "Bits" SetHeader oTable, 4, 3, "Type" SetHeader oTable, 4, 4, "Default Value" SetHeader oTable, 4, 5, "Description" ' Merge cells MergeCells oWord.ActiveDocument, oTable, 1, 2, 1, 5 MergeCells oWord.ActiveDocument, oTable, 2, 2, 2, 5 MergeCells oWord.ActiveDocument, oTable, 3, 1, 3, 5 oTable.Cell(3, 1).Range.ParagraphFormat.Alignment = 1 End Sub Sub InsertFieldRow(oTable, fieldStrings) Dim oRow oTable.Rows.Add Set oRow = oTable.Rows(oTable.Rows.Count) Dim i For i = 0 To 4 oRow.Cells(i + 1).Range.Text = fieldStrings(i) oRow.Cells(i + 1).Range.Font.Bold = False Next End Sub Sub MergeCells(doc, oTable, si, sj, ei, ej) doc.Range(oTable.Cell(si, sj).Range.Start, oTable.Cell(ei, ej).Range.End).Cells.Merge End Sub Sub SetHeader(oTable, row, col, header) With oTable.Cell(row, col).Range .Text = header .Font.Bold = True End With End Sub
<reponame>LaudateCorpus1/RosettaCodeData Public s As String '-- (eg "101101100010") Public t As Integer '-- scratch Function s1() s1 = Len(s) = 12 End Function Function s2() t = 0 For i = 7 To 12 t = t - (Mid(s, i, 1) = "1") Next i s2 = t = 3 End Function Function s3() t = 0 For i = 2 To 12 Step 2 t = t - (Mid(s, i, 1) = "1") Next i s3 = t = 2 End Function Function s4() s4 = Mid(s, 5, 1) = "0" Or ((Mid(s, 6, 1) = "1" And Mid(s, 7, 1) = "1")) End Function Function s5() s5 = Mid(s, 2, 1) = "0" And Mid(s, 3, 1) = "0" And Mid(s, 4, 1) = "0" End Function Function s6() t = 0 For i = 1 To 12 Step 2 t = t - (Mid(s, i, 1) = "1") Next i s6 = t = 4 End Function Function s7() s7 = Mid(s, 2, 1) <> Mid(s, 3, 1) End Function Function s8() s8 = Mid(s, 7, 1) = "0" Or (Mid(s, 5, 1) = "1" And Mid(s, 6, 1) = "1") End Function Function s9() t = 0 For i = 1 To 6 t = t - (Mid(s, i, 1) = "1") Next i s9 = t = 3 End Function Function s10() s10 = Mid(s, 11, 1) = "1" And Mid(s, 12, 1) = "1" End Function Function s11() t = 0 For i = 7 To 9 t = t - (Mid(s, i, 1) = "1") Next i s11 = t = 1 End Function Function s12() t = 0 For i = 1 To 11 t = t - (Mid(s, i, 1) = "1") Next i s12 = t = 4 End Function Public Sub twelve_statements() For i = 0 To 2 ^ 12 - 1 s = Right(CStr(WorksheetFunction.Dec2Bin(64 + i \ 128)), 5) _ & Right(CStr(WorksheetFunction.Dec2Bin(256 + i Mod 128)), 7) For b = 1 To 12 Select Case b Case 1: If s1 <> (Mid(s, b, 1) = "1") Then Exit For Case 2: If s2 <> (Mid(s, b, 1) = "1") Then Exit For Case 3: If s3 <> (Mid(s, b, 1) = "1") Then Exit For Case 4: If s4 <> (Mid(s, b, 1) = "1") Then Exit For Case 5: If s5 <> (Mid(s, b, 1) = "1") Then Exit For Case 6: If s6 <> (Mid(s, b, 1) = "1") Then Exit For Case 7: If s7 <> (Mid(s, b, 1) = "1") Then Exit For Case 8: If s8 <> (Mid(s, b, 1) = "1") Then Exit For Case 9: If s9 <> (Mid(s, b, 1) = "1") Then Exit For Case 10: If s10 <> (Mid(s, b, 1) = "1") Then Exit For Case 11: If s11 <> (Mid(s, b, 1) = "1") Then Exit For Case 12: If s12 <> (Mid(s, b, 1) = "1") Then Exit For End Select If b = 12 Then Debug.Print s Next Next End Sub

<reponame>oddek/CacheController_DDV3101 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 09/30/2020 09:53:55 AM -- Design Name: -- Module Name: OneToFourDemux - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity OneToFourDemux is Port ( i0 : in STD_LOGIC_VECTOR (31 downto 0); sel : in STD_LOGIC_VECTOR (1 downto 0); en : in STD_LOGIC; Y0 : out STD_LOGIC_VECTOR (31 downto 0); Y1 : out STD_LOGIC_VECTOR (31 downto 0); Y2 : out STD_LOGIC_VECTOR (31 downto 0); Y3 : out STD_LOGIC_VECTOR (31 downto 0)); end OneToFourDemux; architecture Behavioral of OneToFourDemux is begin process(i0, sel) is begin case sel is when "00" => Y0 <= i0; when "01" => Y1 <= i0; when "10" => Y2 <= i0; when others => Y3 <= i0; end case; end process; end Behavioral;

<filename>Exercise3/Multiplication/output_files/package.vhd ----- Libraries ----- LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -----Package---- package easy is constant iBits : integer; end easy; package body easy is constant iBits : integer := 8; end package body easy;

<reponame>ChibiKev/Single-Cycle-CPU library verilog; use verilog.vl_types.all; entity Chen_Kevin_Single_Cycle_CPU_Board is port( Chen_Kevin_Segment_A0: out vl_logic; Chen_Kevin_Clock: in vl_logic; Chen_Keivn_Reset: in vl_logic; Chen_Kevin_Segment_B0: out vl_logic; Chen_Kevin_Segment_C0: out vl_logic; Chen_Kevin_Segment_D0: out vl_logic; Chen_Kevin_Segment_E0: out vl_logic; Chen_Kevin_Segment_F0: out vl_logic; Chen_Kevin_Segment_G0: out vl_logic; Chen_Kevin_Segment_A1: out vl_logic; Chen_Kevin_Segment_B1: out vl_logic; Chen_Kevin_Segment_C1: out vl_logic; Chen_Kevin_Segment_D1: out vl_logic; Chen_Kevin_Segment_E1: out vl_logic; Chen_Kevin_Segment_F1: out vl_logic; Chen_Kevin_Segment_G1: out vl_logic; Chen_Kevin_Segment_A2: out vl_logic; Chen_Kevin_Segment_B2: out vl_logic; Chen_Kevin_Segment_C2: out vl_logic; Chen_Kevin_Segment_D2: out vl_logic; Chen_Kevin_Segment_E2: out vl_logic; Chen_Kevin_Segment_F2: out vl_logic; Chen_Kevin_Segment_G2: out vl_logic; Chen_Kevin_Segment_A3: out vl_logic; Chen_Kevin_Segment_B3: out vl_logic; Chen_Kevin_Segment_C3: out vl_logic; Chen_Kevin_Segment_D3: out vl_logic; Chen_Kevin_Segment_E3: out vl_logic; Chen_Kevin_Segment_F3: out vl_logic; Chen_Kevin_Segment_G3: out vl_logic; Chen_Kevin_Segment_A4: out vl_logic; Chen_Kevin_Segment_B4: out vl_logic; Chen_Kevin_Segment_C4: out vl_logic; Chen_Kevin_Segment_D4: out vl_logic; Chen_Kevin_Segment_E4: out vl_logic; Chen_Kevin_Segment_F4: out vl_logic; Chen_Kevin_Segment_G4: out vl_logic; Chen_Kevin_Segment_A5: out vl_logic; Chen_Kevin_Segment_B5: out vl_logic; Chen_Kevin_Segment_C5: out vl_logic; Chen_Kevin_Segment_D5: out vl_logic; Chen_Kevin_Segment_E5: out vl_logic; Chen_Kevin_Segment_F5: out vl_logic; Chen_Kevin_Segment_G5: out vl_logic; Chen_Kevin_Segment_A6: out vl_logic; Chen_Kevin_Segment_B6: out vl_logic; Chen_Kevin_Segment_C6: out vl_logic; Chen_Kevin_Segment_D6: out vl_logic; Chen_Kevin_Segment_E6: out vl_logic; Chen_Kevin_Segment_F6: out vl_logic; Chen_Kevin_Segment_G6: out vl_logic; Chen_Kevin_Segment_A7: out vl_logic; Chen_Kevin_Segment_B7: out vl_logic; Chen_Kevin_Segment_C7: out vl_logic; Chen_Kevin_Segment_D7: out vl_logic; Chen_Kevin_Segment_E7: out vl_logic; Chen_Kevin_Segment_F7: out vl_logic; Chen_Kevin_Segment_G7: out vl_logic; Chen_Kevin_Op : out vl_logic_vector(3 downto 0) ); end Chen_Kevin_Single_Cycle_CPU_Board;

-------------------------------------------------------------------------------- -- __ _ _ _ -- -- / _(_) | | | | -- -- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | -- -- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | -- -- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | -- -- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| -- -- | | -- -- |_| -- -- -- -- -- -- Peripheral-NTM for MPSoC -- -- Neural Turing Machine for MPSoC -- -- -- -------------------------------------------------------------------------------- -- Copyright (c) 2020-2021 by the author(s) -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.ntm_state_pkg.all; use work.ntm_state_top_pkg.all; entity ntm_state_top_testbench is generic ( -- SYSTEM-SIZE DATA_SIZE : integer := 32; CONTROL_SIZE : integer := 64; X : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- x in 0 to X-1 Y : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- y in 0 to Y-1 N : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- j in 0 to N-1 W : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- k in 0 to W-1 L : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- l in 0 to L-1 R : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(64, DATA_SIZE)); -- i in 0 to R-1 -- FUNCTIONALITY ENABLE_NTM_STATE_TOP_TEST : boolean := false; ENABLE_NTM_STATE_TOP_CASE_0 : boolean := false; ENABLE_NTM_STATE_TOP_CASE_1 : boolean := false ); end ntm_state_top_testbench; architecture ntm_state_top_testbench_architecture of ntm_state_top_testbench is ----------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------- -- GLOBAL signal CLK : std_logic; signal RST : std_logic; -- TOP -- CONTROL signal start_top : std_logic; signal ready_top : std_logic; signal data_a_i_in_enable_state_top : std_logic; signal data_a_j_in_enable_state_top : std_logic; signal data_b_i_in_enable_state_top : std_logic; signal data_b_j_in_enable_state_top : std_logic; signal data_c_i_in_enable_state_top : std_logic; signal data_c_j_in_enable_state_top : std_logic; signal data_d_i_in_enable_state_top : std_logic; signal data_d_j_in_enable_state_top : std_logic; signal data_k_in_i_enable_state_top : std_logic; signal data_k_in_j_enable_state_top : std_logic; signal data_k_i_enable_state_top : std_logic; signal data_k_j_enable_state_top : std_logic; signal data_x_out_enable_state_top : std_logic; signal data_y_out_enable_state_top : std_logic; -- DATA signal size_a_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_a_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_b_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_b_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_c_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_c_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_d_i_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal size_d_j_in_top : std_logic_vector(CONTROL_SIZE-1 downto 0); signal data_a_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_b_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_c_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_d_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_k_in_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_x_out_state_top : std_logic_vector(DATA_SIZE-1 downto 0); signal data_y_out_state_top : std_logic_vector(DATA_SIZE-1 downto 0); begin ----------------------------------------------------------------------- -- Body ----------------------------------------------------------------------- -- STIMULUS state_top_stimulus : ntm_state_top_stimulus generic map ( -- SYSTEM-SIZE DATA_SIZE => DATA_SIZE, CONTROL_SIZE => CONTROL_SIZE, X => X, Y => Y, N => N, W => W, L => L, R => R ) port map ( -- GLOBAL CLK => CLK, RST => RST, -- CONTROL NTM_STATE_TOP_START => start_top, NTM_STATE_TOP_READY => ready_top, NTM_STATE_TOP_DATA_A_IN_I_ENABLE => data_a_i_in_enable_state_top, NTM_STATE_TOP_DATA_A_IN_J_ENABLE => data_a_j_in_enable_state_top, NTM_STATE_TOP_DATA_B_IN_I_ENABLE => data_b_i_in_enable_state_top, NTM_STATE_TOP_DATA_B_IN_J_ENABLE => data_b_j_in_enable_state_top, NTM_STATE_TOP_DATA_C_IN_I_ENABLE => data_c_i_in_enable_state_top, NTM_STATE_TOP_DATA_C_IN_J_ENABLE => data_c_j_in_enable_state_top, NTM_STATE_TOP_DATA_D_IN_I_ENABLE => data_d_i_in_enable_state_top, NTM_STATE_TOP_DATA_D_IN_J_ENABLE => data_d_j_in_enable_state_top, NTM_STATE_TOP_DATA_K_IN_I_ENABLE => data_k_in_i_enable_state_top, NTM_STATE_TOP_DATA_K_IN_J_ENABLE => data_k_in_j_enable_state_top, NTM_STATE_TOP_DATA_K_I_ENABLE => data_k_i_enable_state_top, NTM_STATE_TOP_DATA_K_J_ENABLE => data_k_j_enable_state_top, NTM_STATE_TOP_DATA_X_OUT_ENABLE => data_x_out_enable_state_top, NTM_STATE_TOP_DATA_Y_OUT_ENABLE => data_y_out_enable_state_top, -- DATA NTM_STATE_TOP_SIZE_A_I_IN => size_a_i_in_top, NTM_STATE_TOP_SIZE_A_J_IN => size_a_j_in_top, NTM_STATE_TOP_SIZE_B_I_IN => size_b_i_in_top, NTM_STATE_TOP_SIZE_B_J_IN => size_b_j_in_top, NTM_STATE_TOP_SIZE_C_I_IN => size_c_i_in_top, NTM_STATE_TOP_SIZE_C_J_IN => size_c_j_in_top, NTM_STATE_TOP_SIZE_D_I_IN => size_d_i_in_top, NTM_STATE_TOP_SIZE_D_J_IN => size_d_j_in_top, NTM_STATE_TOP_DATA_A_IN => data_a_in_top, NTM_STATE_TOP_DATA_B_IN => data_b_in_top, NTM_STATE_TOP_DATA_C_IN => data_c_in_top, NTM_STATE_TOP_DATA_D_IN => data_d_in_top, NTM_STATE_TOP_DATA_K_IN => data_k_in_top, NTM_STATE_TOP_DATA_X_OUT => data_x_out_state_top, NTM_STATE_TOP_DATA_Y_OUT => data_y_out_state_top ); -- TOP ntm_state_top_test : if (ENABLE_NTM_STATE_TOP_TEST) generate state_top : ntm_state_top generic map ( DATA_SIZE => DATA_SIZE, CONTROL_SIZE => CONTROL_SIZE ) port map ( -- GLOBAL CLK => CLK, RST => RST, -- CONTROL START => start_top, READY => ready_top, DATA_A_IN_I_ENABLE => data_a_i_in_enable_state_top, DATA_A_IN_J_ENABLE => data_a_j_in_enable_state_top, DATA_B_IN_I_ENABLE => data_b_i_in_enable_state_top, DATA_B_IN_J_ENABLE => data_b_j_in_enable_state_top, DATA_C_IN_I_ENABLE => data_c_i_in_enable_state_top, DATA_C_IN_J_ENABLE => data_c_j_in_enable_state_top, DATA_D_IN_I_ENABLE => data_d_i_in_enable_state_top, DATA_D_IN_J_ENABLE => data_d_j_in_enable_state_top, DATA_K_IN_I_ENABLE => data_k_in_i_enable_state_top, DATA_K_IN_J_ENABLE => data_k_in_j_enable_state_top, DATA_K_I_ENABLE => data_k_i_enable_state_top, DATA_K_J_ENABLE => data_k_j_enable_state_top, DATA_X_OUT_ENABLE => data_x_out_enable_state_top, DATA_Y_OUT_ENABLE => data_y_out_enable_state_top, -- DATA SIZE_A_I_IN => size_a_i_in_top, SIZE_A_J_IN => size_a_j_in_top, SIZE_B_I_IN => size_b_i_in_top, SIZE_B_J_IN => size_b_j_in_top, SIZE_C_I_IN => size_c_i_in_top, SIZE_C_J_IN => size_c_j_in_top, SIZE_D_I_IN => size_d_i_in_top, SIZE_D_J_IN => size_d_j_in_top, DATA_A_IN => data_a_in_top, DATA_B_IN => data_b_in_top, DATA_C_IN => data_c_in_top, DATA_D_IN => data_d_in_top, DATA_K_IN => data_k_in_top, DATA_X_OUT => data_x_out_state_top, DATA_Y_OUT => data_y_out_state_top ); end generate ntm_state_top_test; end ntm_state_top_testbench_architecture;

<reponame>aquohn/SoundDisplay<gh_stars>0 `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block <KEY> `protect key_keyowner = "Synopsys", key_keyname = "<KEY>", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block <KEY> `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block svNAK+4lbGaEYTJjSxKewpvQJXVx6cCxkrxJrua3L0nOXKJb8P05WZ77H3tFvsgqxt1Aw8r7HGpc <KEY> `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block <KEY> `protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block <KEY> `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block <KEY> `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block <KEY> `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103440) `protect data_block <KEY> YrvI8ULBIWuZ28YvPcee8WRvXlkys3YoQIjWVcE/BGa2KXqKzWllq2nOLJCXjiCQmE4qnQwwyoCZ BQc3pOuJllV1lS/QA/xxqoyignXJ8NRZTibfoMnQJhddA9Ao700oApG4roOWuLVKJqmLIZfQCzR/ wPDnr5k9HZCU8eNAuPwQDrJnXW1+iZ4w2dmTTVlNr3Cft/g51JprIYqbZZwBV3ZpepxIC9lqKIQq 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-- USN VHDL 101 course -- template for test bench development -- author | date library ieee; use ieee.std_logic_1164.all; entity tb_module_name is end tb_module_name; architecture tb of tb_module_name is component module_name port (clk, reset : in std_logic; ... : in std_logic; ... : in std_logic_vector(M downto 0); ... : out std_logic; ... : out std_logic_vector(N downto 0) ); end component; signal clk, reset : std_logic; signal ... : std_logic; -- module inputs signal ... : std_logic_vector(M downto 0); -- module inputs signal ... : std_logic; -- module outputs signal ... : std_logic_vector(N downto 0); -- module outputs constant clk_period : time := 10 ns; begin uut : module_name port map (clk => clk, reset => reset, ... => ..., ... => ..., ... => ..., ... => ...); clk_process: process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimuli process stim_proc: process begin ... <= '0'; reset <= '1'; wait for clk_period*2; reset <= '0'; ... <= '1'; ... wait for clk_period*...; ... end process ; end tb;

library IEEE; use IEEE.STD_LOGIC_1164.all; use work.all; entity EX_MEM_DIV is port ( --INPUTS clock, clear : in std_logic; --MEM control signals data_format_in : in std_logic_vector(2 downto 0); datamem_write_in : in std_logic; jump_flag_in : in std_logic; --WB control signals mux0_sel_in : in std_logic_vector(1 downto 0); reg_file_write_in : in std_logic; reg_file_write_address_in : in std_logic_vector(4 downto 0); --Data ALU_output_in : in std_logic_vector(31 downto 0); register_file_output_1_in : in std_logic_vector(31 downto 0); ALU_branch_response_in : in std_logic; instruction_address_in : in std_logic_vector(31 downto 0); --OUTPUTS --MEM control signals data_format_out : out std_logic_vector(2 downto 0); datamem_write_out : out std_logic; jump_flag_out : out std_logic; --WB control signals mux0_sel_out : out std_logic_vector(1 downto 0); reg_file_write_out : out std_logic; reg_file_write_address_out : out std_logic_vector(4 downto 0); --Data ALU_output_out : out std_logic_vector(31 downto 0); register_file_output_1_out : out std_logic_vector(31 downto 0); ALU_branch_response_out : out std_logic; instruction_address_out : out std_logic_vector(31 downto 0) ); end EX_MEM_DIV; architecture behavioral of EX_MEM_DIV is --INTERNAL SIGNALS --MEM control signals signal data_format_input_signal : std_logic_vector(2 downto 0); signal datamem_write_input_signal : std_logic; signal jump_flag_input_signal : std_logic; --WB control signals signal mux0_sel_input_signal : std_logic_vector(1 downto 0); signal reg_file_write_input_signal : std_logic; signal reg_file_write_address_input_signal : std_logic_vector(4 downto 0); --Data signal ALU_output_input_signal : std_logic_vector(31 downto 0); signal register_file_output_1_input_signal : std_logic_vector(31 downto 0); signal ALU_branch_response_input_signal : std_logic; signal instruction_address_input_signal : std_logic_vector(31 downto 0); --MEM control signals signal data_format_output_signal : std_logic_vector(2 downto 0); signal datamem_write_output_signal : std_logic; signal jump_flag_output_signal : std_logic; --WB control signals signal mux0_sel_output_signal : std_logic_vector(1 downto 0); signal reg_file_write_output_signal : std_logic; signal reg_file_write_address_output_signal : std_logic_vector(4 downto 0); --Data signal ALU_output_output_signal : std_logic_vector(31 downto 0); signal register_file_output_1_output_signal : std_logic_vector(31 downto 0); signal ALU_branch_response_output_signal : std_logic; signal instruction_address_output_signal : std_logic_vector(31 downto 0); begin --INTERNAL REGISTERS --MEM control signals data_format_reg : reg3b port map(data_format_input_signal, '1', clock, clear, data_format_output_signal); datamem_write_reg : reg1b port map(datamem_write_input_signal, '1', clock, clear, datamem_write_output_signal); jump_flag_reg : reg1b port map(jump_flag_input_signal, '1', clock, clear, jump_flag_output_signal); --WB control signals mux0_sel_reg : reg2b port map(mux0_sel_input_signal, '1', clock, clear, mux0_sel_output_signal); reg_file_write_reg : reg1b port map(reg_file_write_input_signal, '1', clock, clear, reg_file_write_output_signal); reg_file_write_address_reg : reg5b port map(reg_file_write_address_input_signal, '1', clock, clear, reg_file_write_address_output_signal); --Data ALU_output_reg : reg32b port map(ALU_output_input_signal, '1', clock, clear, ALU_output_output_signal); register_file_output_1_reg : reg32b port map(register_file_output_1_input_signal, '1', clock, clear, register_file_output_1_output_signal); ALU_branch_respose_reg : reg1b port map(ALU_branch_response_input_signal, '1', clock, clear, ALU_branch_response_output_signal); instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal); --WIRING INPUT PORTS --MEM control signals data_format_input_signal <= data_format_in; datamem_write_input_signal <= datamem_write_in; jump_flag_input_signal <= jump_flag_in; --WB control signals mux0_sel_input_signal <= mux0_sel_in; reg_file_write_input_signal <= reg_file_write_in; reg_file_write_address_input_signal <= reg_file_write_address_in; --Data ALU_output_input_signal <= ALU_output_in; register_file_output_1_input_signal <= register_file_output_1_in; ALU_branch_response_input_signal <= ALU_branch_response_in; instruction_address_input_signal <= instruction_address_in; --WIRING OUTPUT PORTS --MEM control signals data_format_out <= data_format_output_signal; datamem_write_out <= datamem_write_output_signal; jump_flag_out <= jump_flag_output_signal; --WB control signals mux0_sel_out <= mux0_sel_output_signal; reg_file_write_out <= reg_file_write_output_signal; reg_file_write_address_out <= reg_file_write_address_output_signal; --Data ALU_output_out <= ALU_output_output_signal; register_file_output_1_out <= register_file_output_1_output_signal; ALU_branch_response_out <= ALU_branch_response_output_signal; instruction_address_out <= instruction_address_output_signal; end behavioral;

<gh_stars>1-10 library ieee; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity content_final_work_v2 is PORT(clk : IN STD_LOGIC; SEG_LED : OUT STD_LOGIC_VECTOR(6 downto 0); SEG_NCS : OUT STD_LOGIC_VECTOR(5 downto 0); segdot : OUT STD_LOGIC; key1 : IN STD_LOGIC; --keyTimeSet-按键1-进入时间设置模式 key2 : IN STD_LOGIC; --keyClockSet-按键2-进入闹钟设置模式 key5 : IN STD_LOGIC; --keyQuitClock-按键5-停止闹钟 key6 : IN STD_LOGIC; --keyNumAdd-按键6-选中的数字增加1 key7 : IN STD_LOGIC --keyLeftMove-按键7-左移选中数字 ); END content_final_work_v2; ARCHITECTURE behav OF content_final_work_v2 IS SIGNAL bcd_led : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others=>'0'); SIGNAL clkcnt : STD_LOGIC_VECTOR(30 DOWNTO 0) := (others =>'0'); SIGNAL bcddata_Time : STD_LOGIC_VECTOR(23 downto 0) := (others=>'0'); --当前时间的bcddata SIGNAL bcddata_TimeSet : STD_LOGIC_VECTOR(23 downto 0):=(others=>'0'); --设置时间的bcddata SIGNAL bcddata_ClockSet : STD_LOGIC_VECTOR(23 downto 0):=(others=>'0'); --设置闹钟的bcddata SIGNAL a: integer range 0 to 249999999 :=0; SIGNAL clk_1Hz,q : STD_LOGIC :='0'; SIGNAL clk_1Hz_4vectors : STD_LOGIC_VECTOR(3 DOWNTO 0) :="0000"; SIGNAL keyTimeSetfilt : STD_LOGIC := '0'; --按键1的脉冲信号 SIGNAL TimeSetting : STD_LOGIC := '1'; SIGNAL keyClockSetfilt : STD_LOGIC := '0'; --按键2的脉冲信号 SIGNAL ClockSetting : STD_LOGIC := '1'; SIGNAL keyClockQuitfilt : STD_LOGIC := '0'; --按键5的脉冲信号 SIGNAL ClockTwinkling : STD_LOGIC := '0'; SIGNAL keyNumAddfilt : STD_LOGIC := '0'; --按键6的脉冲信号 SIGNAL keyLeftMovefilt : STD_LOGIC := '0'; --按键7的脉冲信号 SIGNAL LeftMoving : BIT_VECTOR(4 DOWNTO 0) :="11110"; --选中的数字 SHARED VARIABLE displayMode : integer := 0; --数码管的显示模式：若为0则是当前时间，若为1则是设置时间，若为2则是闹钟时间 component keyfilt is port (clk : IN STD_LOGIC; keyTimeSet : IN STD_LOGIC; keyTimeSetfilt : OUT STD_LOGIC; keyClockSet : IN STD_LOGIC; keyClockSetfilt : OUT STD_LOGIC; keyClockQuit : IN STD_LOGIC; keyClockQuitfilt : OUT STD_LOGIC; keyNumAdd : IN STD_LOGIC; keyNumAddfilt : OUT STD_LOGIC; keyLeftMove : IN STD_LOGIC; keyLeftMovefilt : OUT STD_LOGIC ); end component keyfilt; BEGIN akeyfilt: keyfilt port map ( clk =>clk, keyTimeSet => key1, keyTimeSetfilt =>keyTimeSetfilt, keyClockSet => key2, keyClockSetfilt =>keyClockSetfilt, keyClockQuit => key5, keyClockQuitfilt =>keyClockQuitfilt, keyNumAdd => key6, keyNumAddfilt => keyNumAddfilt, keyLeftMove => key7, keyLeftMovefilt => keyLeftMovefilt ); process(clk,clkcnt) begin if(rising_edge(clk))then clkcnt<= clkcnt + 1; end if; end process; process(clk) --产生1Hz时钟脉冲 begin if(clk'event and clk='1') then if a=24999999 then a<=0; q<= not q; clk_1Hz_4vectors <= NOT clk_1Hz_4vectors; else a<=a+1; end if; end if; clk_1Hz <= q; end process; process(clk, clk_1Hz) begin if clk = '1' then if keyClockQuitfilt = '1' then --若按键5按下，则退出闹钟闪烁 ClockTwinkling <= '0'; elsif keyTimeSetfilt = '1' then --若按键1按下，则进入时间设置 bcddata_Time <= bcddata_TimeSet; elsif clk_1Hz'event and clk_1Hz='1' then --当前时间的计数 if bcddata_Time(3 downto 0)=x"9" then bcddata_Time(3 downto 0)<=x"0"; else bcddata_Time(3 downto 0)<=bcddata_Time(3 downto 0)+1; end if; if bcddata_Time(7 downto 0)=x"59" then bcddata_Time(7 downto 0)<=x"00"; elsif bcddata_Time(3 downto 0)=x"9" then bcddata_Time(7 downto 4)<=bcddata_Time(7 downto 4)+1; end if; if bcddata_Time(11 downto 0)=x"959" then bcddata_Time(11 downto 0)<=x"000"; elsif bcddata_Time(7 downto 0)=x"59" then bcddata_Time(11 downto 8)<=bcddata_Time(11 downto 8)+1; end if; if bcddata_Time(15 downto 0)=x"5959" then bcddata_Time(15 downto 0)<=x"0000"; elsif bcddata_Time(11 downto 0) =x"959" then bcddata_Time(15 downto 12)<=bcddata_Time(15 downto 12)+1; end if; if bcddata_Time(19 downto 0)=x"95959" then bcddata_Time(19 downto 0)<=x"00000"; elsif bcddata_Time(15 downto 0) =x"5959" then bcddata_Time(19 downto 16)<=bcddata_Time(19 downto 16)+1; end if; if bcddata_Time(23 downto 0)=x"235959" then bcddata_Time(23 downto 0)<=x"000000"; elsif bcddata_Time(19 downto 0) =x"95959" then bcddata_Time(23 downto 20)<=bcddata_Time(23 downto 20)+1; end if; if (bcddata_Time = bcddata_ClockSet OR ClockTwinkling = '1') then --若当前时间的bcddata与闹钟时间的bcddata相等，则进入闹钟闪烁 ClockTwinkling <= '1'; end if; end if; end if; end process; process(keyNumAddfilt) begin if ((keyNumAddfilt'event AND keyNumAddfilt='1') AND TimeSetting = '0') OR ((keyNumAddfilt'event AND keyNumAddfilt='1') AND ClockSetting = '0')then if displayMode = 1 then --如果是显示模式1（即时间设置模式），则对时间设置模式的bcddata进行操作 case leftMoving is when "11110" => bcddata_TimeSet(3 downto 0)<=bcddata_TimeSet(3 downto 0)+1; --设置秒针个位数 when "11101" => bcddata_TimeSet(7 downto 4)<=bcddata_TimeSet(7 downto 4)+1; --设置秒针十位数 when "11011" => bcddata_TimeSet(11 downto 8)<=bcddata_TimeSet(11 downto 8)+1; --设置分针个位数 when "10111" => bcddata_TimeSet(15 downto 12)<=bcddata_TimeSet(15 downto 12)+1; --设置分针十位数 when "01111" => bcddata_TimeSet(19 downto 16)<=bcddata_TimeSet(19 downto 16)+1; --设置时针 when others => NULL; end case; if bcddata_TimeSet(3 downto 0)=x"9" then bcddata_TimeSet(3 downto 0)<=x"0"; end if; if bcddata_TimeSet(7 downto 4)=x"5" then bcddata_TimeSet(7 downto 4)<=x"0"; end if; if bcddata_TimeSet(11 downto 8)=x"9" then bcddata_TimeSet(11 downto 8)<=x"0"; end if; if bcddata_TimeSet(15 downto 12)=x"5" then bcddata_TimeSet(15 downto 12)<=x"0"; end if; if bcddata_TimeSet(19 downto 16)=x"9" then bcddata_TimeSet(19 downto 16)<=x"0"; bcddata_TimeSet(23 downto 20)<=bcddata_TimeSet(23 downto 20)+1; end if; if bcddata_TimeSet(23 downto 16)=x"23" then bcddata_TimeSet(23 downto 16)<=x"00"; elsif bcddata_TimeSet(19 downto 16) =x"9" then bcddata_TimeSet(23 downto 20)<=bcddata_TimeSet(23 downto 20)+1; end if; elsif displayMode = 2 then --如果是显示模式2（即闹钟设置模式），则对闹钟设置模式的bcddata进行操作 case leftMoving is when "11110" => bcddata_ClockSet(3 downto 0)<=bcddata_ClockSet(3 downto 0)+1; --设置秒针个位数 when "11101" => bcddata_ClockSet(7 downto 4)<=bcddata_ClockSet(7 downto 4)+1; --设置秒针十位数 when "11011" => bcddata_ClockSet(11 downto 8)<=bcddata_ClockSet(11 downto 8)+1; --设置分针个位数 when "10111" => bcddata_ClockSet(15 downto 12)<=bcddata_ClockSet(15 downto 12)+1; --设置分针十位数 when "01111" => bcddata_ClockSet(19 downto 16)<=bcddata_ClockSet(19 downto 16)+1; --设置时针 when others => NULL; end case; if bcddata_ClockSet(3 downto 0)=x"9" then bcddata_ClockSet(3 downto 0)<=x"0"; end if; if bcddata_ClockSet(7 downto 4)=x"5" then bcddata_ClockSet(7 downto 4)<=x"0"; end if; if bcddata_ClockSet(11 downto 8)=x"9" then bcddata_ClockSet(11 downto 8)<=x"0"; end if; if bcddata_ClockSet(15 downto 12)=x"5" then bcddata_ClockSet(15 downto 12)<=x"0"; end if; if bcddata_ClockSet(19 downto 16)=x"9" then bcddata_ClockSet(19 downto 16)<=x"0"; bcddata_ClockSet(23 downto 20)<=bcddata_ClockSet(23 downto 20)+1; end if; if bcddata_ClockSet(23 downto 16)=x"23" then bcddata_ClockSet(23 downto 16)<=x"00"; elsif bcddata_ClockSet(19 downto 16) =x"9" then bcddata_ClockSet(23 downto 20)<=bcddata_ClockSet(23 downto 20)+1; end if; end if; end if; end process; process(clkcnt(17 downto 15)) begin if displayMode = 0 then case clkcnt(17 downto 15) is when "000" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(3 downto 0) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(3 downto 0); end if; SEG_NCS <= "011111"; segdot <= '1'; when "001" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(7 downto 4) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(7 downto 4); end if; SEG_NCS <= "101111"; segdot <= '1'; when "010" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(11 downto 8) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(11 downto 8); end if; SEG_NCS <= "110111"; segdot <= clk_1Hz; when "011" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(15 downto 12) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(15 downto 12); end if; SEG_NCS <= "111011"; segdot <= '1'; when "100" => if ClockTwinkling = '1' then bcd_led<=bcddata_ClockSet(19 downto 16) OR clk_1Hz_4vectors; else bcd_led<=bcddata_Time(19 downto 16); end if; SEG_NCS <= "111101"; segdot<= clk_1Hz; when "101" => if ClockTwinkling = '1' then bcd_led <= bcddata_ClockSet(23 downto 20) OR clk_1Hz_4vectors; else bcd_led <= bcddata_Time(23 downto 20); end if; SEG_NCS <= "111110"; segdot <= '1'; when "110" => SEG_NCS <= "111111"; when "111" => SEG_NCS <= "111111"; when others => NULL; end case; elsif displayMode = 1 then case clkcnt(17 downto 15) is when "000" => if LeftMoving = "11110" then bcd_led <= bcddata_TimeSet(3 downto 0) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(3 downto 0); end if; SEG_NCS <= "011111"; segdot <= '1'; when "001" => if LeftMoving = "11101" then bcd_led <= bcddata_TimeSet(7 downto 4) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(7 downto 4); end if; SEG_NCS <= "101111"; segdot <= '1'; when "010" => if LeftMoving = "11011" then bcd_led <= bcddata_TimeSet(11 downto 8) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(11 downto 8); end if; SEG_NCS <= "110111"; segdot <= clk_1Hz; when "011" => if LeftMoving = "10111" then bcd_led <= bcddata_TimeSet(15 downto 12) OR clk_1Hz_4vectors; else bcd_led <= bcddata_TimeSet(15 downto 12); end if; SEG_NCS <= "111011"; segdot<='1'; when "100" => if LeftMoving = "01111" then bcd_led<=bcddata_TimeSet(19 downto 16) OR clk_1Hz_4vectors; else bcd_led<=bcddata_TimeSet(19 downto 16); end if; SEG_NCS <= "111101"; segdot<= clk_1Hz; when "101" => bcd_led<=bcddata_TimeSet(23 downto 20); SEG_NCS <= "111110"; segdot <= '1'; when "110" => SEG_NCS <= "111111"; when "111" => SEG_NCS <= "111111"; when others => NULL; end case; elsif displayMode = 2 then case clkcnt(17 downto 15) is when "000" => if LeftMoving = "11110" then bcd_led <= bcddata_ClockSet(3 downto 0) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(3 downto 0); end if; SEG_NCS <= "011111"; segdot <= '1'; when "001" => if LeftMoving = "11101" then bcd_led <= bcddata_ClockSet(7 downto 4) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(7 downto 4); end if; SEG_NCS <= "101111"; segdot <= '1'; when "010" => if LeftMoving = "11011" then bcd_led <= bcddata_ClockSet(11 downto 8) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(11 downto 8); end if; SEG_NCS <= "110111"; segdot <= clk_1Hz; when "011" => if LeftMoving = "10111" then bcd_led <= bcddata_ClockSet(15 downto 12) OR clk_1Hz_4vectors; else bcd_led <= bcddata_ClockSet(15 downto 12); end if; SEG_NCS <= "111011"; segdot<='1'; when "100" => if LeftMoving = "01111" then bcd_led<=bcddata_ClockSet(19 downto 16) OR clk_1Hz_4vectors; else bcd_led<=bcddata_ClockSet(19 downto 16); end if; SEG_NCS <= "111101"; segdot<= clk_1Hz; when "101" => bcd_led<=bcddata_ClockSet(23 downto 20); SEG_NCS <= "111110"; segdot <= '1'; when "110" => SEG_NCS <= "111111"; when "111" => SEG_NCS <= "111111"; when others => NULL; end case; end if; end process; process(bcd_led) begin case bcd_led is WHEN "0000"=>SEG_LED<="0000001"; WHEN "0001"=>SEG_LED<="1001111"; WHEN "0010"=>SEG_LED<="0010010"; WHEN "0011"=>SEG_LED<="0000110"; WHEN "0100"=>SEG_LED<="1001100"; WHEN "0101"=>SEG_LED<="0100100"; WHEN "0110"=>SEG_LED<="0100000"; WHEN "0111"=>SEG_LED<="0001111"; WHEN "1000"=>SEG_LED<="0000000"; WHEN "1001"=>SEG_LED<="0000100"; WHEN OTHERS=>SEG_LED<="1111111"; end case; end process; -------------------------------------------------------- process(clk) begin if(rising_edge(clk))then if keyTimeSetfilt = '1' then TimeSetting <= not TimeSetting; if TimeSetting = '1' then displayMode := 1; elsif TimeSetting = '0' then displayMode := 0; end if; end if; if keyClockSetfilt = '1' then ClockSetting <= not ClockSetting; if ClockSetting = '1' then displayMode := 2; elsif ClockSetting = '0' then displayMode := 0; end if; end if; if keyLeftMovefilt = '1' then LeftMoving <= LeftMoving ROL 1; end if; end if; end process; end behav;

-- Criado por <NAME> -- Processador RISC-V Uniciclo em VHDL -- Em 22/05/2021 -- Universidade de Brasília, Matriculas 180053922 e 180023631 library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity riscV is port( clock : in std_logic ); end entity riscV; architecture arc_riscV of riscV is component bloco_pc is port( clock : in std_logic; pcin : in std_logic_vector(31 downto 0); pcout : out std_logic_vector(31 downto 0) ); end component; component bloco_rom is port( address : in std_logic_vector; dataout : out std_logic_vector ); end component; component bloco_ram is port ( clock : in std_logic; writeEnable : in std_logic; address : in std_logic_vector; datain : in std_logic_vector; dataout : out std_logic_vector ); end component; component bloco_ctrlgeral is port( opcode : in std_logic_vector(6 downto 0); branch : out std_logic; memRead : out std_logic; memToReg : out std_logic; ulaOP : out std_logic_vector(2 downto 0); memWrite : out std_logic; ulaSource : out std_logic; regWrite : out std_logic; isLUI : out std_logic; isAUIPC : out std_logic; isJALX : out std_logic; isJALR : out std_logic ); end component; component bloco_breg is port( writeData : in std_logic_vector(31 downto 0); writeEnable : in std_logic; select1 : in std_logic_vector(4 downto 0); select2 : in std_logic_vector(4 downto 0); selectWrite : in std_logic_vector(4 downto 0); clock : in std_logic; register1 : out std_logic_vector(31 downto 0); register2 : out std_logic_vector(31 downto 0) ); end component; component bloco_gimediato is port( instruc : in std_logic_vector(31 downto 0); imediato : out std_logic_vector(31 downto 0) ); end component; component bloco_ctrlula is port ( ulaOP: in std_logic_vector(2 downto 0); func3: in std_logic_vector(2 downto 0); bitfunc7: in std_logic; ulaCode: out std_logic_vector(3 downto 0) ); end component; component bloco_ula is port( opcode : in std_logic_vector(3 downto 0); A, B : in std_logic_vector(31 downto 0); Z : out std_logic_vector(31 downto 0); zero : out std_logic ); end component; component bloco_mux32 is port( selec : in std_logic; A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); Z : out std_logic_vector(31 downto 0) ); end component; component bloco_mux5 is port( selec : in std_logic; A : in std_logic_vector(4 downto 0); B : in std_logic_vector(4 downto 0); Z : out std_logic_vector(4 downto 0) ); end component; component bloco_and is port( A : in std_logic; B : in std_logic; Z : out std_logic ); end component; component bloco_somador is port( A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); Z : out std_logic_vector(31 downto 0) ); end component; signal fake_clock : std_logic; signal sig_pcin : std_logic_vector(31 downto 0); signal sig_pcout : std_logic_vector(31 downto 0); signal instruction : std_logic_vector(31 downto 0); signal sig_branch : std_logic; signal sig_memRead : std_logic; signal sig_memToReg : std_logic; signal sig_ulaOP : std_logic_vector(2 downto 0); signal sig_memWrite : std_logic; signal sig_ulaSource : std_logic; signal sig_regWrite : std_logic; signal sig_isLUI : std_logic; signal sig_isAUIPC : std_logic; signal sig_isJALX : std_logic; signal sig_isJALR : std_logic; signal sig_writeData : std_logic_vector(31 downto 0); signal sig_register1 : std_logic_vector(31 downto 0); signal sig_register2 : std_logic_vector(31 downto 0); signal sig_imediato : std_logic_vector(31 downto 0); signal sig_ulaCode : std_logic_vector(3 downto 0); signal sig_ulaB : std_logic_vector(31 downto 0); signal sig_ulaZ : std_logic_vector(31 downto 0); signal sig_ulaZero : std_logic; alias sig_addressRom : std_logic_vector(9 downto 0) is sig_pcout(11 downto 2); --n�o s�o necess�rios todos os bits de endere�o alias sig_addressRam : std_logic_vector(9 downto 0) is sig_ulaZ(11 downto 2); signal sig_dataOutRam : std_logic_vector(31 downto 0); alias sig_opcode : std_logic_vector(6 downto 0) is instruction(6 downto 0); alias sig_select1 : std_logic_vector(4 downto 0) is instruction(19 downto 15); alias sig_select2 : std_logic_vector(4 downto 0) is instruction(24 downto 20); alias sig_selectWrite : std_logic_vector(4 downto 0) is instruction(11 downto 7); alias sig_func3 : std_logic_vector(2 downto 0) is instruction(14 downto 12); alias sig_bitfunc7 : std_logic is instruction(30); signal sig_soma_pcimediato : std_logic_vector(31 downto 0); signal sig_soma_pc4 : std_logic_vector(31 downto 0); signal sig_and_branchzero : std_logic; signal sig_mux_somasdepc : std_logic_vector(31 downto 0); signal sig_mux_select1lui: std_logic_vector(4 downto 0); --Mux RAM signal sig_mux_ramulaz : std_logic_vector(31 downto 0); --Mux AUIPC signal sig_mux_auipc : std_logic_vector(31 downto 0); begin pc: bloco_pc port map( clock => fake_clock, pcin => sig_pcin, pcout => sig_pcout ); memoria_de_instrucoes: bloco_rom port map( address => sig_addressRom, dataout => instruction ); bloco_de_controle_geral : bloco_ctrlgeral port map( opcode => sig_opcode, branch => sig_branch, memRead => sig_memRead, memToReg => sig_memToReg, ulaOP => sig_ulaOP, memWrite => sig_memWrite, ulaSource => sig_ulaSource, regWrite => sig_regWrite, isLUI => sig_isLUI, isAUIPC => sig_isAUIPC, isJALX => sig_isJALX, isJALR => sig_isJALR ); breg: bloco_breg port map( writeData => sig_writeData, writeEnable => sig_regWrite, select1 => sig_mux_select1lui, select2 => sig_select2, selectWrite => sig_selectWrite, clock => fake_clock, register1 => sig_register1, register2 => sig_register2 ); gerador_de_imediato: bloco_gimediato port map( instruc => instruction, imediato => sig_imediato ); controle_da_ula: bloco_ctrlula port map( ulaOP => sig_ulaOP, func3 => sig_func3, bitfunc7 => sig_bitfunc7, ulaCode => sig_ulaCode ); mux32_breg_imm: bloco_mux32 port map( selec => sig_ulaSource, A => sig_register2, B => sig_imediato, Z => sig_ulaB ); ula: bloco_ula port map( opcode => sig_ulaCode, A => sig_register1, B => sig_ulaB, Z => sig_ulaZ, zero => sig_ulaZero ); memoria_de_dados: bloco_ram port map( clock => fake_clock, writeEnable => sig_memWrite, address => sig_addressRam, datain => sig_register2, dataout => sig_dataOutRam ); mux32_memdados_ula: bloco_mux32 port map( selec => sig_memToReg, A => sig_ulaZ, B => sig_dataOutRam, Z => sig_mux_ramulaz ); somador_pc_imm: bloco_somador port map( A => sig_pcout, B => sig_imediato, Z => sig_soma_pcimediato ); somador_pc_4: bloco_somador port map( A => sig_pcout, B => "00000000000000000000000000000100", Z => sig_soma_pc4 ); and_branch: bloco_and port map( A => sig_branch, B => sig_ulaZero, Z => sig_and_branchzero ); mux32_pc4_pcimediato: bloco_mux32 port map( selec => sig_and_branchzero, A => sig_soma_pc4, B => sig_soma_pcimediato, Z => sig_mux_somasdepc ); mux_lui: bloco_mux5 port map( selec => sig_isLUI, A => sig_select1, B => "00000", Z => sig_mux_select1lui ); mux_auipc: bloco_mux32 port map( selec => sig_isAUIPC, A => sig_mux_ramulaz, B => sig_soma_pcimediato, Z => sig_mux_auipc ); mux_jalx: bloco_mux32 port map( selec => sig_isJALX, A => sig_mux_auipc, B => sig_soma_pc4, Z => sig_writeData ); mux_jalr: bloco_mux32 port map( selec => sig_isJALR, A => sig_mux_somasdepc, B => sig_ulaZ, Z => sig_pcin ); process begin --fake_clock <= clock fake_clock <= '0'; --comentar daqui pra baixo para utilizar a entrada de clock wait for 1 ns; fake_clock <= '1'; wait for 1 ns; end process; end arc_riscV;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity cmp is Generic(N : natural := 8); Port ( rs1 : in STD_LOGIC_VECTOR (N-1 downto 0); rs2 : in STD_LOGIC_VECTOR (N-1 downto 0); uns : in STD_LOGIC; lt : out STD_LOGIC; eq : out STD_LOGIC); end cmp; architecture Behavioral of cmp is signal rs1_i: unsigned(N-1 downto 0); signal rs2_i: unsigned(N-1 downto 0); begin rs1_i(N-2 downto 0) <= unsigned(rs1(N-2 downto 0)); rs2_i(N-2 downto 0) <= unsigned(rs2(N-2 downto 0)); rs1_i(N-1) <= rs1(N-1) when uns = '1' else rs2(N-1); rs2_i(N-1) <= rs2(N-1) when uns = '1' else rs1(N-1); lt <= '1' when rs1_i < rs2_i else '0'; eq <= '1' when rs1 = rs2 else '0'; end Behavioral;

library ieee; use ieee.std_logic_1164.all; entity OrGate is port ( x1:in std_logic; x2:in std_logic; x3:out std_logic ); end OrGate; architecture beh of OrGate is begin x3 <= x1 or x2; end beh;

library IEEE; use IEEE.std_logic_1164.all; ENTITY reg8 IS PORT ( i_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; i_RESETN, i_CLOCK: IN STD_LOGIC ; o_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE arch_reg8 OF reg8 IS BEGIN PROCESS ( i_RESETN, i_CLOCK ) BEGIN IF i_RESETN = '0' THEN o_DATA <= "00000000" ; ELSIF i_CLOCK'EVENT AND i_CLOCK = '1' THEN o_DATA <= i_DATA ; END IF ; END PROCESS ; END arch_reg8 ;

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block <KEY> `protect key_keyowner = "Synopsys", key_keyname = "<KEY>", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block <KEY> `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block vjXD1J80ih5LwlwCSxRK/NqXmTUxbpB8n8TRQDYrYRHg9JBD0mDYFzzNYtEcd0e83nh6YIRmNJwe <KEY> `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block <KEY> `protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block <KEY> `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block <KEY> `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block <KEY> `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 121872) `protect data_block GkBWNbNDyxrMQ3+XPQWEPD7bX1tWcQ3v7p0IB2AOrTy0YaMYceP0E6w2qypUosaGsZqULJ/s4EBp QOOVXF8dM7rGle0Xg/hlD/6Hu+BMp2dt+Y2Lek/RZztvk697H65di+8z7HLkLmVpGPKfPROwKhSY 1Ls3VFrCY3VsvTo8f3bk9IWy2aPGwM2+3I/6yboPoRAgFwDYfz5HuWUTJzfxigW59bHw8o8M5d5T UaY/L2VZiv9juBdDVLrjX8vHeRsxOyXnn2vhNnfq5uFYzEkuv9LDSyp7mNuloMTqtKsqBcVUM2zI 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<KEY> `protect end_protected

library verilog; use verilog.vl_types.all; entity tb_top_key_beep is generic( T : integer := 20 ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of T : constant is 1; end tb_top_key_beep;

component pr_region_default_SpatialIP_0 is port ( clock : in std_logic := 'X'; -- clk io_M_AXI_0_AWID : out std_logic_vector(5 downto 0); -- awid io_M_AXI_0_AWUSER : out std_logic_vector(31 downto 0); -- awuser io_M_AXI_0_AWADDR : out std_logic_vector(31 downto 0); -- awaddr io_M_AXI_0_AWLEN : out std_logic_vector(7 downto 0); -- awlen io_M_AXI_0_AWSIZE : out std_logic_vector(2 downto 0); -- awsize io_M_AXI_0_AWBURST : out std_logic_vector(1 downto 0); -- awburst io_M_AXI_0_AWLOCK : out std_logic; -- awlock io_M_AXI_0_AWCACHE : out std_logic_vector(3 downto 0); -- awcache io_M_AXI_0_AWPROT : out std_logic_vector(2 downto 0); -- awprot io_M_AXI_0_AWQOS : out std_logic_vector(3 downto 0); -- awqos io_M_AXI_0_AWVALID : out std_logic; -- awvalid io_M_AXI_0_AWREADY : in std_logic := 'X'; -- awready io_M_AXI_0_ARID : out std_logic_vector(5 downto 0); -- arid io_M_AXI_0_ARUSER : out std_logic_vector(31 downto 0); -- aruser io_M_AXI_0_ARADDR : out std_logic_vector(31 downto 0); -- araddr io_M_AXI_0_ARLEN : out std_logic_vector(7 downto 0); -- arlen io_M_AXI_0_ARSIZE : out std_logic_vector(2 downto 0); -- arsize io_M_AXI_0_ARBURST : out std_logic_vector(1 downto 0); -- arburst io_M_AXI_0_ARLOCK : out std_logic; -- arlock io_M_AXI_0_ARCACHE : out std_logic_vector(3 downto 0); -- arcache io_M_AXI_0_ARPROT : out std_logic_vector(2 downto 0); -- arprot io_M_AXI_0_ARQOS : out std_logic_vector(3 downto 0); -- arqos io_M_AXI_0_ARVALID : out std_logic; -- arvalid io_M_AXI_0_ARREADY : in std_logic := 'X'; -- arready io_M_AXI_0_WDATA : out std_logic_vector(511 downto 0); -- wdata io_M_AXI_0_WSTRB : out std_logic_vector(63 downto 0); -- wstrb io_M_AXI_0_WLAST : out std_logic; -- wlast io_M_AXI_0_WVALID : out std_logic; -- wvalid io_M_AXI_0_WREADY : in std_logic := 'X'; -- wready io_M_AXI_0_RID : in std_logic_vector(5 downto 0) := (others => 'X'); -- rid io_M_AXI_0_RUSER : in std_logic_vector(31 downto 0) := (others => 'X'); -- ruser io_M_AXI_0_RDATA : in std_logic_vector(511 downto 0) := (others => 'X'); -- rdata io_M_AXI_0_RRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp io_M_AXI_0_RLAST : in std_logic := 'X'; -- rlast io_M_AXI_0_RVALID : in std_logic := 'X'; -- rvalid io_M_AXI_0_RREADY : out std_logic; -- rready io_M_AXI_0_BID : in std_logic_vector(5 downto 0) := (others => 'X'); -- bid io_M_AXI_0_BUSER : in std_logic_vector(31 downto 0) := (others => 'X'); -- buser io_M_AXI_0_BRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp io_M_AXI_0_BVALID : in std_logic := 'X'; -- bvalid io_M_AXI_0_BREADY : out std_logic; -- bready io_S_AVALON_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address io_S_AVALON_readdata : out std_logic_vector(31 downto 0); -- readdata io_S_AVALON_chipselect : in std_logic := 'X'; -- chipselect io_S_AVALON_write : in std_logic := 'X'; -- write io_S_AVALON_read : in std_logic := 'X'; -- read io_S_AVALON_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata reset : in std_logic := 'X' -- reset ); end component pr_region_default_SpatialIP_0; u0 : component pr_region_default_SpatialIP_0 port map ( clock => CONNECTED_TO_clock, -- clock.clk io_M_AXI_0_AWID => CONNECTED_TO_io_M_AXI_0_AWID, -- io_M_AXI_0.awid io_M_AXI_0_AWUSER => CONNECTED_TO_io_M_AXI_0_AWUSER, -- .awuser io_M_AXI_0_AWADDR => CONNECTED_TO_io_M_AXI_0_AWADDR, -- .awaddr io_M_AXI_0_AWLEN => CONNECTED_TO_io_M_AXI_0_AWLEN, -- .awlen io_M_AXI_0_AWSIZE => CONNECTED_TO_io_M_AXI_0_AWSIZE, -- .awsize io_M_AXI_0_AWBURST => CONNECTED_TO_io_M_AXI_0_AWBURST, -- .awburst io_M_AXI_0_AWLOCK => CONNECTED_TO_io_M_AXI_0_AWLOCK, -- .awlock io_M_AXI_0_AWCACHE => CONNECTED_TO_io_M_AXI_0_AWCACHE, -- .awcache io_M_AXI_0_AWPROT => CONNECTED_TO_io_M_AXI_0_AWPROT, -- .awprot io_M_AXI_0_AWQOS => CONNECTED_TO_io_M_AXI_0_AWQOS, -- .awqos io_M_AXI_0_AWVALID => CONNECTED_TO_io_M_AXI_0_AWVALID, -- .awvalid io_M_AXI_0_AWREADY => CONNECTED_TO_io_M_AXI_0_AWREADY, -- .awready io_M_AXI_0_ARID => CONNECTED_TO_io_M_AXI_0_ARID, -- .arid io_M_AXI_0_ARUSER => CONNECTED_TO_io_M_AXI_0_ARUSER, -- .aruser io_M_AXI_0_ARADDR => CONNECTED_TO_io_M_AXI_0_ARADDR, -- .araddr io_M_AXI_0_ARLEN => CONNECTED_TO_io_M_AXI_0_ARLEN, -- .arlen io_M_AXI_0_ARSIZE => CONNECTED_TO_io_M_AXI_0_ARSIZE, -- .arsize io_M_AXI_0_ARBURST => CONNECTED_TO_io_M_AXI_0_ARBURST, -- .arburst io_M_AXI_0_ARLOCK => CONNECTED_TO_io_M_AXI_0_ARLOCK, -- .arlock io_M_AXI_0_ARCACHE => CONNECTED_TO_io_M_AXI_0_ARCACHE, -- .arcache io_M_AXI_0_ARPROT => CONNECTED_TO_io_M_AXI_0_ARPROT, -- .arprot io_M_AXI_0_ARQOS => CONNECTED_TO_io_M_AXI_0_ARQOS, -- .arqos io_M_AXI_0_ARVALID => CONNECTED_TO_io_M_AXI_0_ARVALID, -- .arvalid io_M_AXI_0_ARREADY => CONNECTED_TO_io_M_AXI_0_ARREADY, -- .arready io_M_AXI_0_WDATA => CONNECTED_TO_io_M_AXI_0_WDATA, -- .wdata io_M_AXI_0_WSTRB => CONNECTED_TO_io_M_AXI_0_WSTRB, -- .wstrb io_M_AXI_0_WLAST => CONNECTED_TO_io_M_AXI_0_WLAST, -- .wlast io_M_AXI_0_WVALID => CONNECTED_TO_io_M_AXI_0_WVALID, -- .wvalid io_M_AXI_0_WREADY => CONNECTED_TO_io_M_AXI_0_WREADY, -- .wready io_M_AXI_0_RID => CONNECTED_TO_io_M_AXI_0_RID, -- .rid io_M_AXI_0_RUSER => CONNECTED_TO_io_M_AXI_0_RUSER, -- .ruser io_M_AXI_0_RDATA => CONNECTED_TO_io_M_AXI_0_RDATA, -- .rdata io_M_AXI_0_RRESP => CONNECTED_TO_io_M_AXI_0_RRESP, -- .rresp io_M_AXI_0_RLAST => CONNECTED_TO_io_M_AXI_0_RLAST, -- .rlast io_M_AXI_0_RVALID => CONNECTED_TO_io_M_AXI_0_RVALID, -- .rvalid io_M_AXI_0_RREADY => CONNECTED_TO_io_M_AXI_0_RREADY, -- .rready io_M_AXI_0_BID => CONNECTED_TO_io_M_AXI_0_BID, -- .bid io_M_AXI_0_BUSER => CONNECTED_TO_io_M_AXI_0_BUSER, -- .buser io_M_AXI_0_BRESP => CONNECTED_TO_io_M_AXI_0_BRESP, -- .bresp io_M_AXI_0_BVALID => CONNECTED_TO_io_M_AXI_0_BVALID, -- .bvalid io_M_AXI_0_BREADY => CONNECTED_TO_io_M_AXI_0_BREADY, -- .bready io_S_AVALON_address => CONNECTED_TO_io_S_AVALON_address, -- io_S_AVALON.address io_S_AVALON_readdata => CONNECTED_TO_io_S_AVALON_readdata, -- .readdata io_S_AVALON_chipselect => CONNECTED_TO_io_S_AVALON_chipselect, -- .chipselect io_S_AVALON_write => CONNECTED_TO_io_S_AVALON_write, -- .write io_S_AVALON_read => CONNECTED_TO_io_S_AVALON_read, -- .read io_S_AVALON_writedata => CONNECTED_TO_io_S_AVALON_writedata, -- .writedata reset => CONNECTED_TO_reset -- reset.reset );

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; use tip.all; entity ALU is port(CLK : in STD_LOGIC; COMMAND_IN:in std_logic_vector(3 downto 0); SELECT_IN:in std_logic_vector(3 downto 0); CONST_IN :in std_logic_vector(7 downto 0); OUT_ALU: out std_logic_vector(7 downto 0); Zero: inout std_logic:='0'; Carry: inout std_logic:='0'); end; architecture UAL of ALU is component Semi_sumator port(EN: in std_logic; A,B: in std_logic_vector(7 downto 0); SUM: out std_logic_vector(7 downto 0); CF,ZF:out std_logic); end component; component Sumator_complet port(EN: in std_logic; A,B: in std_logic_VECTOR(7 downto 0); SUM: out std_logic_VECTOR(7 downto 0); CF: inout std_logic; ZF: out std_logic); end component; component Scazator port(EN: in std_logic; A,B: in STD_LOGIC_VECTOR(7 downto 0); DIF: out STD_LOGIC_VECTOR(7 downto 0); CF,ZF: out STD_LOGIC); end component; component Scazator_complet port(EN: in std_logic; A,B: in std_logic_VECTOR(7 downto 0); DIF: out std_logic_VECTOR(7 downto 0); CF:inout std_logic; ZF: out std_logic); end component; component Poarta_SI port(EN: in std_logic; A,B: in std_logic_VECTOR(7 downto 0); Y: out std_logic_VECTOR(7 downto 0); CF,ZF: out std_logic); end component; component XOR_8 port(EN: in std_logic; A,B:in std_logic_vector(7 downto 0); X:out std_logic_vector(7 downto 0); CARRY,ZERO:out std_logic); end component; component OR_8 port(EN: in std_logic; A,B:in std_logic_vector(7 downto 0); O:out std_logic_vector(7 downto 0); CARRY,ZERO: out std_logic); end component; component SHIFT PORT(EN: in std_logic; REG_IN:in std_logic_vector(7 downto 0); --input SEL:in std_logic_vector(3 downto 0); --selectia de shift (SEE XAPP213.PDF) CARRY: inout std_logic; REG_OUT: out std_logic_vector(7 downto 0); ZERO: out std_logic); end component; component Mux2la1 port (I0,I1: in std_logic_vector(7 downto 0); SEL2_1: in std_logic; O: out std_logic_vector(7 downto 0)); end component; component Mux16la1 port ( --EN: in std_logic; MUX_IN: in M168; EN: in STD_LOGIC; SEL: in STD_LOGIC_VECTOR(3 downto 0); MUX_OUT: out STD_LOGIC_VECTOR(7 downto 0) ); end component; component REGISTRII port(CLK_R : in STD_LOGIC; CLK_W : in STD_LOGIC; IN_REG: in STD_LOGIC_VECTOR(7 downto 0); S_IO_A : in STD_LOGIC_VECTOR(3 downto 0); S_O_B : in STD_LOGIC_VECTOR(3 downto 0); OUT_A : out STD_LOGIC_VECTOR(7 downto 0); OUT_B : out STD_LOGIC_VECTOR(7 downto 0)); end component; component LOAD port(EN: in std_logic; LOAD_IN : in std_logic_vector(7 downto 0); LOAD_OUT: out std_logic_vector(7 downto 0); CF,ZF: out std_logic); end component; signal INPUT_REG: std_logic_vector(7 downto 0):="00000000"; signal sX,sY : std_logic_vector(3 downto 0); signal MUX_SELECT: std_logic_vector(3 downto 0); signal shift_command: std_logic_vector(3 downto 0); signal REG_A,REG_B: std_logic_vector(7 downto 0):="00000000"; signal A,B: std_logic_vector(7 downto 0):="00000000"; signal REZULTATE : M168; signal EN : std_logic; signal EN_VEC : std_logic_vector(15 downto 0):=(others => '0'); signal WRITE_REG : std_logic; begin process(COMMAND_IN,SELECT_IN,CONST_IN,CLK) variable EN_AUX: std_logic_vector(15 downto 0):="0000000000000000"; variable EN_GENERAL: std_logic; begin --EN_AUX:=(others => '0'); case COMMAND_IN is when "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "0000" => MUX_SELECT<= COMMAND_IN; sX <= SELECT_IN; sY <= "ZZZZ"; if(CLK = '1' and CLK'EVENT) then EN_GENERAL := '0'; end if; if(CLK = '0' and CLK'EVENT) then EN_GENERAL:= '1'; end if; EN_AUX(to_integer(unsigned(COMMAND_IN))):=not EN_GENERAL; when "1100" => MUX_SELECT<=CONST_IN(3 downto 0); sX <= SELECT_IN; sY <= CONST_IN(7 downto 4); if(CLK = '1' and CLK'EVENT) then EN_GENERAL := '0'; end if; if(CLK = '0' and CLK'EVENT) then EN_GENERAL:= '1'; end if; EN_AUX(to_integer(unsigned(CONST_IN))):=not EN_GENERAL; when "1101" => MUX_SELECT<=COMMAND_IN; sX<= SELECT_IN; shift_command<= CONST_IN(3 downto 0); if(CLK = '1' and CLK'EVENT) then EN_GENERAL := '0'; end if; if(CLK = '0' and CLK'EVENT) then EN_GENERAL:= '1'; end if; EN_AUX(to_integer(unsigned(COMMAND_IN))):= EN_GENERAL; when others => NULL; end case; if(EN_GENERAL = '1') then WRITE_REG<='0'; end if; if(EN_GENERAL = '0') then WRITE_REG<='1'; end if; EN_VEC<=EN_AUX; EN<= EN_GENERAL; end process; ATR: B<=REG_B when COMMAND_IN = "1100" else CONST_IN; REG : REGISTRII port map(EN,WRITE_REG,INPUT_REG,sX,sY,REG_A,REG_B); LOADD : LOAD port map(EN_VEC(0),B,REZULTATE(0),Carry,Zero); --0000 ANDD : Poarta_SI port map(EN_VEC(1),REG_A,B,REZULTATE(1),Carry,Zero); --0001 ORR : OR_8 port map(EN_VEC(2),REG_A,B,REZULTATE(2),Carry,Zero); --0010 XORR : XOR_8 port map(EN_VEC(3),REG_A,B,REZULTATE(3),Carry,Zero); --0011 ADD : Semi_sumator port map(EN_VEC(4),REG_A,B,REZULTATE(4),Carry,Zero); --0100 ADDCY : Sumator_complet port map(EN_VEC(5),REG_A,B,REZULTATE(5),Carry,Zero); --0101 SUB : Scazator port map(EN_VEC(6),REG_A,B,REZULTATE(6),Carry,Zero); --0110 SUBCY : Scazator_complet port map(EN_VEC(7),REG_A,B,REZULTATE(7),Carry,Zero); --0111 SHIFT1 : SHIFT port map(EN_VEC(13),REG_A,shift_command,Carry,REZULTATE(13),Zero);--1101 MUX_OUT: MUX16la1 port map(REZULTATE,'1',MUX_SELECT,INPUT_REG); REZULTATE(12 downto 8) <= (others =>"ZZZZZZZZ"); REZULTATE(15 downto 14) <= (others =>"ZZZZZZZZ"); OUT_ALU<= INPUT_REG; end;

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:59:48 05/23/2011 -- Design Name: -- Module Name: /home/silva/Documents/Dropbox/IST/PSD_TEMP/debug/sudoku_mem/tb_circuito.vhd -- Project Name: sudoku_mem -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: circuito3 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_circuito IS END tb_circuito; ARCHITECTURE behavior OF tb_circuito IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT circuito3 PORT( CLK : IN std_logic; RST : IN std_logic; clks : OUT std_logic; memout : OUT std_logic_vector(31 downto 0); canSTART : IN std_logic; execDONE : OUT std_logic; CNTbyte2 : IN std_logic_vector(11 downto 0) ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '0'; signal canSTART : std_logic := '0'; signal CNTbyte2 : std_logic_vector(11 downto 0) := (others => '0'); --Outputs signal clks : std_logic; signal memout : std_logic_vector(31 downto 0); signal execDONE : std_logic; -- Clock period definitions constant CLK_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: circuito3 PORT MAP ( CLK => CLK, RST => RST, clks => clks, memout => memout, canSTART => canSTART, execDONE => execDONE, CNTbyte2 => CNTbyte2 ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. rst <= '1', '0' after 50 ns; canstart <= '0', '1' after 100 ns; -- insert stimulus here wait; end process; END;

-- The MIT License (MIT) -- -- Copyright (c) <NAME> <EMAIL> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity camera_unit is generic( BUF_AW : integer := 8; BUF_DW : integer := 16 ); port( clk : in std_logic; reset : in std_logic; addr : in std_logic_vector(15 downto 0); strobe : in std_logic; cycle : in std_logic; c_sel : in std_logic; wr : in std_logic; ack : out std_logic; --filter : in std_logic; ack_tick : out std_logic; dout : out std_logic_vector(15 downto 0); cfinish : out std_logic; resend : in std_logic ; frame_irq : out std_logic; --- CAMERA PINS GOES HERE OV7670_VSYNC : in std_logic; OV7670_HREF : in std_logic; OV7670_PCLK : in std_logic; OV7670_D : in std_logic_vector(7 downto 0); OV7670_SIOC : out STD_LOGIC; OV7670_SIOD : inout STD_LOGIC; OV7670_RESET : out STD_LOGIC; OV7670_PWDN : out STD_LOGIC; OV7670_XCLK : out STD_LOGIC ); end entity; architecture arch of camera_unit is -- signals declaration here constant ID: natural := 1; constant VGA_ADDR: std_logic_vector(18 downto 0 ) := "1001010111111111111"; constant QVGA_ADDR: std_logic_vector(18 downto 0) := "0010010101111111111"; constant QQVGA_ADDR : std_logic_vector(18 downto 0) := "0000100101011111111"; constant OFFSET: unsigned(15 downto 0) := X"0008"; signal mem_addr : std_logic_vector(15 downto 0); signal wr_op, px_wr, ack_db, state : std_logic := '0'; --signal fr_din, fr_din_next: std_logic_vector(BUF_DW-1 downto 0); signal cam_dout: std_logic_vector(15 downto 0) ; signal buffer_out,filter_out, filter_out_next : std_logic_vector(15 downto 0); signal clk_45: std_logic; signal fr_addr: std_logic_vector(18 downto 0) ; signal fr_addr_map, fr_addr_map_next: std_logic_vector(18 downto 0) ; -- select the filter or not signal R8,R8_next,G8, G8_next,B8,B8_next : std_logic_vector(7 downto 0); signal pixon: std_logic; signal d1, d2: std_logic_vector(7 downto 0) ; signal filter_ready: std_logic; signal rez_160x120,rez_320x240: std_logic; signal rez_in: std_logic_vector(1 downto 0) ; begin ack <= strobe and cycle and c_sel; state <= (ack_db or state) and (strobe and cycle and c_sel); ack_tick <= ack_db; write_proc : process( clk,reset ) begin if(reset = '1') then rez_320x240 <= '0'; rez_160x120 <= '0'; elsif rising_edge(clk) then if((strobe and cycle and wr and c_sel) = '1' ) then if rez_in = "01" then rez_160x120 <= '1'; rez_320x240 <= '0'; elsif rez_in = "10" then rez_160x120 <= '0'; rez_320x240 <= '1'; else rez_160x120 <= '0'; rez_320x240 <= '0'; end if; else rez_320x240 <= rez_320x240; rez_160x120 <= rez_160x120; end if; end if; end process ; sync_proc:process(clk, reset) begin if reset = '1' then ack_db <= '0'; --fr_din <= (others=>'0'); filter_out <= (others=>'0'); R8 <= (others=>'0'); G8 <= (others=>'0'); B8 <= (others=>'0'); fr_addr_map <= (others=>'0'); elsif rising_edge(clk) then --fr_din <= fr_din_next; filter_out<= filter_out_next; ack_db <= strobe and cycle and c_sel and (not ack_db) and (not state); R8 <= R8_next; G8 <= G8_next; B8 <= B8_next; fr_addr_map <= fr_addr_map_next; end if; end process; mem_addr <=std_logic_vector(unsigned(addr) - OFFSET) when (strobe and cycle and c_sel) = '1' else (others=>'0'); rez_in <= mem_addr(2 downto 1); -- clock unit clkgen_unit:entity work.clock_gen port map ( clk_in => clk, clk_45 => clk_45, clk_24 => OV7670_XCLK ) ; -- controller unit cam_ctrl: entity work.ov7670_controller port map( clk45 => clk_45, resend => resend, -- to host config_finished => cfinish, -- to led sioc => OV7670_SIOC, -- to camera siod => OV7670_SIOD, -- to camera reset => OV7670_RESET,-- to camera pwdn => OV7670_PWDN -- to camera ); capture_unit: entity work.ov7670_capture port map( pclk => OV7670_PCLK, vsync => OV7670_VSYNC, -- from camera rez_160x120 => rez_160x120, rez_320x240 => rez_320x240, href => OV7670_HREF, -- from camera d => OV7670_D, -- from camera addr => fr_addr, -- to buffer address dout => cam_dout, -- to buffer out we => px_wr ); frame_irq <= '1' when ((rez_320x240 = '1' and fr_addr_map = QVGA_ADDR) OR (rez_160x120 = '1' and fr_addr_map = QQVGA_ADDR) OR (rez_160x120 = '0' and rez_320x240 = '0' and fr_addr_map = VGA_ADDR)) else '0'; -- add the filter R8_next <= cam_dout(15 downto 11) & "000" when px_wr='1' else R8; G8_next <= cam_dout(10 downto 5) & "00" when px_wr='1' else G8; B8_next <= cam_dout(4 downto 0) & "000" when px_wr='1' else B8; filter_unit: entity work.hsvfilter port map( clk => clk, reset => reset, R_in => R8_next, G_in => G8_next, B_in => B8_next, start => px_wr, pixon => pixon, available => filter_ready ); wr_op <= '1' when fr_addr_map(3 downto 0) = "1111" and filter_ready = '1' else '0';-- when filter = '1' else px_wr; filter_out_next <= pixon&filter_out(15 downto 1) when filter_ready = '1' else filter_out; --buffer_in <= cam_dout when filter = '0' else filter_out_next; --fr_din_next <= cam_dout&fr_din(7 downto 0) when wr_op = '1' else -- fr_din(15 downto 8)&cam_dout when -- (px_wr = '1') else fr_din; fr_addr_map_next <=fr_addr when px_wr='1' else fr_addr_map;--when filter = '1' else fr_addr; -- end process; frame_ent: entity work.dual_port_dual_clock generic map( ADDR_WIDTH => BUF_AW, DATA_WIDTH => BUF_DW ) port map( clka => clk,-- a bit dagerous OV7670_PCLK, clkb => clk, we => wr_op, addr_a => fr_addr_map(18 downto 4),--fr_addr_map, addr_b => mem_addr(BUF_AW downto 1), -- requested by host din_a => filter_out_next,--buffer_in,--fr_din_next, -- stacked data from camera dout_a => open, dout_b => buffer_out -- to host ); --d1 <= (others=>'1') when buffer_out(0) = '1' else (others=>'0'); --d2 <= (others=>'1') when buffer_out(1) = '1' else (others=>'0'); dout <= buffer_out; end architecture;

library ieee; use ieee.std_logic_1164.all; entity adderSubtractor is port( mode : in std_logic; A : in std_logic_vector(2 downto 0); B : in std_logic_vector(2 downto 0); S : out std_logic_vector(2 downto 0); Cout, V : out std_logic ); end adderSubtractor; architecture struct of adderSubtractor is component full_adder is port( A, B, C : IN std_logic; Sum, Carry : OUT std_logic ); end component; signal C1, C2, C3: std_logic; signal xor0, xor1, xor2: std_logic; begin xor0 <= B(0) XOR mode; xor1 <= B(1) XOR mode; xor2 <= B(2) XOR mode; FA0: full_adder port map(A(0), xor0, mode, S(0), C1); FA1: full_adder port map(A(1), xor1, C1, S(1), C2); FA2: full_adder port map(A(2), xor2, C2, S(2), C3); V <= C2 XOR C3; Cout <= C3; end struct;

<reponame>danielvcorreia/cr -------------------------------------------- -- Module Name: tutorial -------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; Entity tutorial Is port ( sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(7 downto 0) ); end tutorial; Architecture behavior of tutorial Is Signal led_int : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; begin led <= led_int; led_int(0) <= not(sw(0)); led_int(1) <= sw(1) and not(sw(2)); led_int(3) <= sw(2) and sw(3); led_int(2) <= led_int(1) or led_int(3); led_int(7 downto 4) <= sw(7 downto 4); end behavior;

<gh_stars>1-10 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; --This entity counts the number of leading '1' terms entity sixteenbitcounter is port ( CLK : in std_logic; Y : out std_logic_vector(15 downto 0) := ('0', others=>'0') -- output only ); end entity; architecture counter16_falling of sixteenbitcounter is begin process is variable x : natural := 0; begin wait until CLK = '0'; x := x + 1; Y <= CONV_STD_LOGIC_VECTOR(x, 16); end process; end counter16_falling; architecture counter16_rising of sixteenbitcounter is begin process (CLK) is variable x : natural := 0; begin if (CLK'event and CLK = '1') then x := x + 1; Y <= CONV_STD_LOGIC_VECTOR(x, 16); end if; end process; end counter16_rising; architecture counter16_rising_v2 of sixteenbitcounter is begin process (CLK) is variable x : natural := 0; begin if rising_edge(CLK) then x := x + 1; Y <= CONV_STD_LOGIC_VECTOR(x, 16); end if; end process; end counter16_rising_v2;

<gh_stars>1-10 -- ********************************************************************/ -- Actel Corporation Proprietary and Confidential -- Copyright 2010 Actel Corporation. All rights reserved. -- -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED -- IN ADVANCE IN WRITING. -- -- Description: -- -- Revision Information: -- Date Description -- ---- ----------------------------------------- -- 04AUG10 Production Release Version 1.0 -- -- SVN Revision Information: -- SVN $Revision: $ -- SVN $Date: $ -- -- Resolved SARs -- SAR Date Who Description -- -- Notes: -- -- *********************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; ENTITY CoreAHBLtoAXI_AXIAccessControlHX IS GENERIC ( ----------------------------------------------------- -- Global parameters ----------------------------------------------------- AHB_AWIDTH : integer := 32; AHB_DWIDTH : integer := 32; AXI_AWIDTH : integer := 32; AXI_DWIDTH : integer := 64; CLOCKS_ASYNC : integer := 1; UNDEF_BURST : integer := 0); -- if '0' then single transter else INCR16 PORT ( ----------------------------------------------------- -- Input-Output Ports ----------------------------------------------------- -- Inputs on the AHBL interface HSEL : IN std_logic; HADDR : IN std_logic_vector(AHB_AWIDTH - 1 DOWNTO 0); HWRITE : IN std_logic; HREADY : IN std_logic; HTRANS : IN std_logic_vector(1 DOWNTO 0); HSIZE : IN std_logic_vector(2 DOWNTO 0); HBURST : IN std_logic_vector(2 DOWNTO 0); HMASTLOCK : IN std_logic; latch_ahb_sig_sync : IN std_logic; ahb_wr_done_sync : IN std_logic; ahb_rd_req_sync : IN std_logic; burst_count_valid_sync : IN std_logic; burst_count_r : IN std_logic_vector(3 DOWNTO 0); rdch_fifo_full : IN std_logic; wrch_fifo_empty : IN std_logic; -- Inputs on AXI Interface ACLK : IN std_logic; ARESETn : IN std_logic; axi_wr_data : IN std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); -- Outputs on AXI Interface AWID : OUT std_logic_vector(3 DOWNTO 0); AWADDR : OUT std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0); AWLEN : OUT std_logic_vector(3 DOWNTO 0); AWSIZE : OUT std_logic_vector(2 DOWNTO 0); AWBURST : OUT std_logic_vector(1 DOWNTO 0); AWLOCK : OUT std_logic_vector(1 DOWNTO 0); AWVALID : OUT std_logic; AWREADY : IN std_logic; WID : OUT std_logic_vector(3 DOWNTO 0); WDATA : OUT std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); WSTRB : OUT std_logic_vector((AXI_DWIDTH / 8) - 1 DOWNTO 0); WLAST : OUT std_logic; WVALID : OUT std_logic; WREADY : IN std_logic; BREADY : OUT std_logic; BID : IN std_logic_vector(3 DOWNTO 0); BRESP : IN std_logic_vector(1 DOWNTO 0); BVALID : IN std_logic; ARID : OUT std_logic_vector(3 DOWNTO 0); ARADDR : OUT std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0); ARLEN : OUT std_logic_vector(3 DOWNTO 0); ARSIZE : OUT std_logic_vector(2 DOWNTO 0); ARBURST : OUT std_logic_vector(1 DOWNTO 0); ARLOCK : OUT std_logic_vector(1 DOWNTO 0); ARVALID : OUT std_logic; ARREADY : IN std_logic; RREADY : OUT std_logic; RID : IN std_logic_vector(3 DOWNTO 0); RDATA : IN std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); RRESP : IN std_logic_vector(1 DOWNTO 0); RLAST : IN std_logic; RVALID : IN std_logic; WRCH_fifo_rd_en : OUT std_logic; BRESP_sync : OUT std_logic_vector(1 DOWNTO 0); rdch_fifo_wr_en_r : OUT std_logic; rdch_fifo_wr_data : OUT std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0); axi_read_rlast : OUT std_logic); END ENTITY CoreAHBLtoAXI_AXIAccessControlHX; ARCHITECTURE translated OF CoreAHBLtoAXI_AXIAccessControlHX IS CONSTANT AXI_WRSTB : integer := AXI_DWIDTH / 8; CONSTANT WRITE_C : std_logic := '1'; -- write constant CONSTANT READ_C : std_logic := '0'; -- read constant CONSTANT RESPOK_C : std_logic_vector(1 DOWNTO 0) := "00"; -- response OKAY from AXI CONSTANT RESPERR_C : std_logic_vector(1 DOWNTO 0) := "01"; -- response ERROR from AXI -- State machine variables CONSTANT IDLE : std_logic_vector(2 DOWNTO 0) := "000"; CONSTANT SEND_WR_ADDR : std_logic_vector(2 DOWNTO 0) := "001"; CONSTANT SEND_WR_DATA : std_logic_vector(2 DOWNTO 0) := "010"; CONSTANT READ_WR_RESP : std_logic_vector(2 DOWNTO 0) := "011"; CONSTANT SEND_RD_ADDR : std_logic_vector(2 DOWNTO 0) := "100"; CONSTANT READ_RD_DATA : std_logic_vector(2 DOWNTO 0) := "101"; CONSTANT SHIFT_DATA_BYTE : std_logic_vector(7 DOWNTO 0) := "00000001"; CONSTANT SHIFT_DATA_HW : std_logic_vector(7 DOWNTO 0) := "00000011"; CONSTANT SHIFT_DATA_WORD : std_logic_vector(7 DOWNTO 0) := "00001111"; FUNCTION to_integer ( val : std_logic_vector) RETURN integer IS CONSTANT vec : std_logic_vector(val'high-val'low DOWNTO 0) := val; VARIABLE rtn : integer := 0; BEGIN FOR index IN vec'RANGE LOOP IF (vec(index) = '1') THEN rtn := rtn + (2**index); END IF; END LOOP; RETURN(rtn); END to_integer; FUNCTION ShiftRight ( val : std_logic_vector; shft : integer) RETURN std_logic_vector IS VARIABLE int : std_logic_vector(val'LENGTH+shft-1 DOWNTO 0); VARIABLE rtn : std_logic_vector(val'RANGE); VARIABLE fill : std_logic_vector(shft-1 DOWNTO 0) := (others => '0'); BEGIN int := fill & val; rtn := int(val'LENGTH+shft-1 DOWNTO shft); RETURN(rtn); END ShiftRight; FUNCTION ShiftLeft(s1:std_logic_vector;nn:integer) return std_logic_vector is -- shift left by nn bits, add nn 0s to LSBs -- Example s1 = 11111101, nn = 3, return = 11101000 --It is in effect unsigned multiplication by 2^nn --variable rr : std_logic_vector(s1'high downto s1'low); variable rr : std_logic_vector(7 downto 0); begin if(nn < 0) then assert false report "shln: shift index nn is negative,can't shift" severity error; end if; if(nn = 0) then rr := s1; else rr := (others => '0'); --for ii in s1'high downto s1'low+1 loop for ii in 7 downto 0 loop rr(ii) := s1(ii-nn); if(ii = nn) then exit; end if; end loop; end if; return rr; end ShiftLeft; FUNCTION to_stdlogic ( val : IN boolean) RETURN std_logic IS BEGIN IF (val) THEN RETURN('1'); ELSE RETURN('0'); END IF; END to_stdlogic; FUNCTION conv_std_logic ( val : IN boolean) RETURN std_logic IS BEGIN RETURN(to_stdlogic(val)); END conv_std_logic; ------------------------------------------------------------------------------- -- Register Declarations ------------------------------------------------------------------------------- SIGNAL wvalid_reg : std_logic; SIGNAL axi_current_state : std_logic_vector(2 DOWNTO 0); SIGNAL axi_next_state : std_logic_vector(2 DOWNTO 0); SIGNAL HSEL_sync : std_logic; SIGNAL HADDR_sync : std_logic_vector(AHB_AWIDTH - 1 DOWNTO 0) ; SIGNAL HWRITE_sync : std_logic; SIGNAL HREADY_sync : std_logic; SIGNAL HTRANS_sync : std_logic_vector(1 DOWNTO 0); SIGNAL HSIZE_sync : std_logic_vector(2 DOWNTO 0); SIGNAL HBURST_sync : std_logic_vector(2 DOWNTO 0); SIGNAL HMASTLOCK_sync : std_logic; SIGNAL awaddr_awvalid_set : std_logic; SIGNAL wvalid_set : std_logic; SIGNAL wvalid_clr : std_logic; SIGNAL bready_set : std_logic; SIGNAL burstcount_load : std_logic; SIGNAL burstcount_dec : std_logic; SIGNAL burstcount_dec_r : std_logic; SIGNAL latch_wr_resp : std_logic_vector(1 DOWNTO 0); SIGNAL latch_wr_resp_set : std_logic; SIGNAL axiwr_burst_length : std_logic_vector(3 DOWNTO 0); SIGNAL axird_burst_length : std_logic_vector(3 DOWNTO 0); SIGNAL axi_burst_type : std_logic_vector(1 DOWNTO 0); SIGNAL awaddr_awvalid_clr : std_logic; SIGNAL burstcount_reg : std_logic_vector(4 DOWNTO 0); SIGNAL burstcount_reg_r : std_logic_vector(4 DOWNTO 0); SIGNAL burst_count_r_sync : std_logic_vector(3 DOWNTO 0); SIGNAL rdch_write_data_r : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL rd_data_c : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0) ; SIGNAL axi_read_data : std_logic; SIGNAL rready_set : std_logic; SIGNAL axi_read_resp : std_logic_vector(1 DOWNTO 0); SIGNAL ahb_rd_req_sync_d : std_logic; SIGNAL latch_ahb_sig_sync_d : std_logic; SIGNAL axi_wstrb : std_logic_vector((AXI_DWIDTH / 8) - 1 DOWNTO 0); SIGNAL swap_rd_data_byte : std_logic_vector(3 DOWNTO 0); SIGNAL axi_wrdata : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL wrstb_count : std_logic_vector(1 DOWNTO 0); SIGNAL AWADDR_incr : std_logic_vector(2 DOWNTO 0); SIGNAL axi_wr_data_d : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL awaddr_awvalid_clr_d : std_logic; SIGNAL araddr_arvalid_clr_d : std_logic; SIGNAL araddr_arvalid_set : std_logic; SIGNAL araddr_arvalid_clr : std_logic; SIGNAL WREADY_reg : std_logic; SIGNAL BVALID_reg : std_logic; SIGNAL wvalid_reg_r : std_logic; SIGNAL wvalid_set_r : std_logic; SIGNAL wvalid_set_r1 : std_logic; SIGNAL wvalid_clr_t : std_logic; SIGNAL wvalid_clr_r : std_logic; SIGNAL axi_wr_data_lat : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; ------------------------------------------------------------------------------- -- Wire Declarations ------------------------------------------------------------------------------- SIGNAL rd_haddr : std_logic_vector(AHB_AWIDTH - 1 DOWNTO 0) ; SIGNAL axi_rd_start : std_logic; SIGNAL store_ahb_sig : std_logic; SIGNAL undef_wr_burst_size_32 : std_logic_vector(3 DOWNTO 0); SIGNAL undef_rd_burst_size_32 : std_logic_vector(3 DOWNTO 0); SIGNAL undef_wr_burst_size_64 : std_logic_vector(3 DOWNTO 0); SIGNAL undef_rd_burst_size_64 : std_logic_vector(3 DOWNTO 0); SIGNAL temp_xhdl28 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl29 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl30 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl31 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl32 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl33 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl34 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl35 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl36 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl37 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl38 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl39 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl40 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl41 : std_logic_vector(7 DOWNTO 0); SIGNAL temp_xhdl42 : std_logic; SIGNAL temp_xhdl43 : std_logic_vector(3 DOWNTO 0); SIGNAL temp_xhdl45 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl46 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl47 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl48 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl49 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl50 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl51 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl52 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl53 : std_logic_vector(31 DOWNTO 0); SIGNAL temp_xhdl54 : std_logic_vector(63 DOWNTO 32); SIGNAL temp_xhdl70 : std_logic; SIGNAL AWID_xhdl1 : std_logic_vector(3 DOWNTO 0); SIGNAL AWADDR_xhdl2 : std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0) ; SIGNAL AWLEN_xhdl3 : std_logic_vector(3 DOWNTO 0); SIGNAL AWSIZE_xhdl4 : std_logic_vector(2 DOWNTO 0); SIGNAL AWBURST_xhdl5 : std_logic_vector(1 DOWNTO 0); SIGNAL AWVALID_xhdl6 : std_logic; SIGNAL AWVALID_xhdl6_int : std_logic; SIGNAL WID_xhdl7 : std_logic_vector(3 DOWNTO 0); SIGNAL WDATA_xhdl8 : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0) ; SIGNAL WSTRB_xhdl9 : std_logic_vector(AXI_WRSTB - 1 DOWNTO 0); SIGNAL WLAST_xhdl10 : std_logic; SIGNAL WVALID_xhdl11 : std_logic; SIGNAL BREADY_xhdl12 : std_logic; SIGNAL ARID_xhdl13 : std_logic_vector(3 DOWNTO 0); SIGNAL ARADDR_xhdl14 : std_logic_vector(AXI_AWIDTH - 1 DOWNTO 0) ; SIGNAL ARLEN_xhdl15 : std_logic_vector(3 DOWNTO 0); SIGNAL ARSIZE_xhdl16 : std_logic_vector(2 DOWNTO 0); SIGNAL ARBURST_xhdl17 : std_logic_vector(1 DOWNTO 0); SIGNAL ARLOCK_xhdl18 : std_logic_vector(1 DOWNTO 0); SIGNAL ARVALID_xhdl19 : std_logic; SIGNAL ARVALID_xhdl19_int : std_logic; SIGNAL RREADY_xhdl20 : std_logic; SIGNAL AWLOCK_xhdl21 : std_logic_vector(1 DOWNTO 0); SIGNAL WRCH_fifo_rd_en_xhdl22 : std_logic; SIGNAL BRESP_sync_xhdl23 : std_logic_vector(1 DOWNTO 0); SIGNAL rdch_fifo_wr_en_r_xhdl24 : std_logic; SIGNAL rdch_fifo_wr_data_xhdl25 : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0) ; SIGNAL axi_read_rlast_xhdl26 : std_logic; SIGNAL axi_burst_length_ahb32 : std_logic; SIGNAL axi_burst_length_ahb64 : std_logic; SIGNAL axiwr_burst_length_ahb32 : std_logic; SIGNAL axiwr_burst_length_ahb64 : std_logic; BEGIN AWID <= AWID_xhdl1; AWADDR <= AWADDR_xhdl2; AWLEN <= AWLEN_xhdl3; AWSIZE <= AWSIZE_xhdl4; AWBURST <= AWBURST_xhdl5; AWVALID <= AWVALID_xhdl6; WID <= WID_xhdl7; WDATA <= WDATA_xhdl8; WSTRB <= WSTRB_xhdl9; WLAST <= WLAST_xhdl10; WVALID <= WVALID_xhdl11; BREADY <= BREADY_xhdl12; ARID <= ARID_xhdl13; ARADDR <= ARADDR_xhdl14; ARLEN <= ARLEN_xhdl15; ARSIZE <= ARSIZE_xhdl16; ARBURST <= ARBURST_xhdl17; ARLOCK <= ARLOCK_xhdl18; ARVALID <= ARVALID_xhdl19; RREADY <= RREADY_xhdl20; AWLOCK <= AWLOCK_xhdl21; WRCH_fifo_rd_en <= WRCH_fifo_rd_en_xhdl22; BRESP_sync <= BRESP_sync_xhdl23; rdch_fifo_wr_en_r <= rdch_fifo_wr_en_r_xhdl24; rdch_fifo_wr_data <= rdch_fifo_wr_data_xhdl25; axi_read_rlast <= axi_read_rlast_xhdl26; temp_xhdl28 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data(63 DOWNTO 32) & axi_wr_data(31 DOWNTO 0); temp_xhdl29 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl30 <= "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000"; temp_xhdl31 <= axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0); temp_xhdl32 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl33 <= "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(47 DOWNTO 32); temp_xhdl34 <= "00000000000000000000000000000000" & axi_wr_data(31 DOWNTO 16) & axi_wr_data(15 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0); temp_xhdl35 <= axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data(63 DOWNTO 48) & axi_wr_data(47 DOWNTO 32) & "00000000000000000000000000000000"; temp_xhdl36 <= axi_wr_data(31 DOWNTO 16) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data(63 DOWNTO 48) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000"; temp_xhdl37 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(31 DOWNTO 0) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl38 <= axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32) WHEN (AWADDR_incr(2) = '1') ELSE axi_wr_data; temp_xhdl39 <= axi_wr_data(31 DOWNTO 0) & "00000000000000000000000000000000" WHEN (burstcount_reg(0) = '1') ELSE axi_wr_data_d(63 DOWNTO 32) & "00000000000000000000000000000000"; temp_xhdl40 <= "00000000000000000000000000000000" & axi_wr_data(31 DOWNTO 0) WHEN (burstcount_reg(0) = '1') ELSE "00000000000000000000000000000000" & axi_wr_data_d(63 DOWNTO 32); --///////////////////////////////////////////////////////////////////////////// -- Start-of-code // --///////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------------------------- -- Generate the write data to be sent to the AXI interface -- This is the 64-bit data read from the WRCHANNEL fifo and sent on the Write -- data channel on the AXI bus ------------------------------------------------------------------------------- PROCESS (AWADDR_incr, HSIZE_sync, HBURST_sync, axi_wr_data, HADDR_sync, temp_xhdl28, temp_xhdl29, temp_xhdl30, temp_xhdl31, temp_xhdl32, temp_xhdl33, temp_xhdl34,temp_xhdl35, temp_xhdl36, temp_xhdl37, temp_xhdl38, temp_xhdl39, temp_xhdl40 ) VARIABLE axi_wrdata_xhdl27 : std_logic_vector(AXI_DWIDTH - 1 DOWNTO 0); BEGIN CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "11" => axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); WHEN "10" => IF (HBURST_sync(2 DOWNTO 0) = "000") THEN axi_wrdata_xhdl27 := temp_xhdl28; ELSE IF (HBURST_sync(2 DOWNTO 0) = "001") THEN axi_wrdata_xhdl27 := temp_xhdl29; ELSE -- For all bursts IF (HBURST_sync(0) = '1') THEN -- For incr bursts IF (HADDR_sync(2) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; ELSE -- For wrap bursts IF (HADDR_sync(2) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; END IF; END IF; END IF; WHEN "01" => IF (HBURST_sync(2 DOWNTO 0) = "000") THEN -- For Single IF (HADDR_sync(2 DOWNTO 1) = "00") THEN axi_wrdata_xhdl27 := temp_xhdl30; ELSE IF (HADDR_sync(2 DOWNTO 1) = "10") THEN axi_wrdata_xhdl27 := temp_xhdl31; ELSE IF (HADDR_sync(2 DOWNTO 1) = "11") THEN axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 16) & axi_wr_data(15 DOWNTO 0) & "00000000000000000000000000000000"; ELSE axi_wrdata_xhdl27 := axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); END IF; END IF; END IF; ELSE IF (HBURST_sync(2 DOWNTO 0) = "001") THEN axi_wrdata_xhdl27 := temp_xhdl32; ELSE -- For Bursts IF (AWADDR_incr(2 DOWNTO 1) = "00") THEN axi_wrdata_xhdl27 := temp_xhdl33; ELSE IF (AWADDR_incr(2 DOWNTO 1) = "01") THEN axi_wrdata_xhdl27 := temp_xhdl34; ELSE IF (AWADDR_incr(2 DOWNTO 1) = "10") THEN axi_wrdata_xhdl27 := temp_xhdl35; ELSE axi_wrdata_xhdl27 := temp_xhdl36; END IF; END IF; END IF; END IF; END IF; WHEN "00" => IF (HBURST_sync(2 DOWNTO 0) = "000") THEN axi_wrdata_xhdl27 := temp_xhdl37; ELSE IF (HBURST_sync(2 DOWNTO 0) = "001") THEN axi_wrdata_xhdl27 := temp_xhdl38; ELSE IF (HBURST_sync(0) = '1') THEN -- For incr bursts IF (AWADDR_incr(2) = '1') THEN axi_wrdata_xhdl27 := temp_xhdl39; ELSE axi_wrdata_xhdl27 := temp_xhdl40; END IF; ELSE -- For wrap bursts IF (HADDR_sync(2) = '0') THEN -- Address less than 4 - lower range IF (AWADDR_incr(2 DOWNTO 0) < "100") THEN IF (AWADDR_incr(0) = '1') THEN axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); ELSE axi_wrdata_xhdl27 := axi_wr_data; END IF; ELSE IF (AWADDR_incr(0) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); ELSE axi_wrdata_xhdl27 := axi_wr_data; END IF; END IF; ELSE -- Address falling in upper range IF (AWADDR_incr(2 DOWNTO 0) >= "100") THEN IF (AWADDR_incr(0) = '1') THEN axi_wrdata_xhdl27 := axi_wr_data; ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; ELSE IF (AWADDR_incr(0) = '0') THEN axi_wrdata_xhdl27 := axi_wr_data; ELSE axi_wrdata_xhdl27 := axi_wr_data(31 DOWNTO 0) & axi_wr_data(63 DOWNTO 32); END IF; END IF; END IF; END IF; -- else: !if(HBURST_sync[0] == 1'b1) END IF; END IF; -- else: !if(HBURST_sync[2:0] == 3'b001) WHEN -- case: 2'b00 OTHERS => axi_wrdata_xhdl27 := (OTHERS => '0'); END CASE; axi_wrdata <= axi_wrdata_xhdl27; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN burstcount_dec_r <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN burstcount_dec_r <= burstcount_dec; END IF; END PROCESS; temp_xhdl41 <= "00001111" WHEN (AWADDR_incr(2 DOWNTO 0) = "000") ELSE "11110000"; ------------------------------------------------------------------------------- -- Generate the write strobe to be sent to the AXI interface ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN axi_wstrb <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "11" => axi_wstrb <= '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1'; WHEN "10" => IF ((HBURST_sync(2 DOWNTO 0) = "000") OR ((HBURST_sync(2 DOWNTO 0) = "001") AND (UNDEF_BURST = 0))) THEN -- For Single/Undef IF (HADDR_sync(2 DOWNTO 0) = "000") THEN axi_wstrb <= "00001111"; ELSE IF (HADDR_sync(2 DOWNTO 0) = "100") THEN axi_wstrb <= "11110000"; END IF; END IF; ELSE -- For all bursts IF (HBURST_sync(0) = '1') THEN -- For incr bursts IF (HADDR_sync(2) = '1') THEN -- 30/01/13 - check whether start addr = '4 IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN --axi_wstrb <= ShiftLeft("00001111", to_integer(HADDR_sync(2 DOWNTO 0))) ; IF ((HADDR_sync(2)) = '1') THEN axi_wstrb <= "11110000"; ELSE axi_wstrb <= "00001111"; END IF; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF (axi_wstrb = "11110000") THEN axi_wstrb <= "00001111"; ELSE --axi_wstrb <= ShiftLeft(axi_wstrb, 4); axi_wstrb <= axi_wstrb(3 DOWNTO 0) & "0000"; END IF; END IF; END IF; -- if (HADDR_sync[2] == 1'b1) ELSE axi_wstrb <= '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1'; END IF; ELSE -- For wrap bursts IF (burstcount_reg = "00000") THEN axi_wstrb <= axi_wstrb; ELSE IF (((WVALID_xhdl11 AND WREADY) AND CONV_STD_LOGIC(axi_wstrb = "11110000")) = '1') THEN axi_wstrb <= "00001111"; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN --axi_wstrb <= ShiftLeft(axi_wstrb, 4); axi_wstrb <= axi_wstrb(3 DOWNTO 0) & "0000"; ELSE IF (wvalid_set_r = '1') THEN axi_wstrb <= temp_xhdl41; END IF; END IF; END IF; END IF; END IF; END IF; WHEN "01" => IF ((HBURST_sync(2 DOWNTO 0) = "000") OR ((HBURST_sync(2 DOWNTO 0) = "001") AND (UNDEF_BURST = 0))) THEN --axi_wstrb <= ShiftLeft("00000011", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 1)) = "00") THEN axi_wstrb <= "00000011"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "01") THEN axi_wstrb <= "00001100"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "10") THEN axi_wstrb <= "00110000"; ELSE axi_wstrb <= "11000000"; END IF; ELSE -- For all bursts IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN --axi_wstrb <= ShiftLeft("00000011", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 1)) = "00") THEN axi_wstrb <= "00000011"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "01") THEN axi_wstrb <= "00001100"; ELSIF ((HADDR_sync(2 DOWNTO 1)) = "10") THEN axi_wstrb <= "00110000"; ELSE axi_wstrb <= "11000000"; END IF; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF (axi_wstrb = "11000000") THEN axi_wstrb <= "00000011"; ELSE --axi_wstrb <= ShiftLeft(axi_wstrb, 2); axi_wstrb <= axi_wstrb(5 DOWNTO 0) & "00"; END IF; END IF; END IF; END IF; WHEN "00" => IF ((HBURST_sync(2 DOWNTO 0) = "000") OR ((HBURST_sync(2 DOWNTO 0) = "001") AND (UNDEF_BURST = 0))) THEN --axi_wstrb <= ShiftLeft("00000001", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 0)) = "111") THEN axi_wstrb <= "10000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "110") THEN axi_wstrb <= "01000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "101") THEN axi_wstrb <= "00100000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "100") THEN axi_wstrb <= "00010000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "011") THEN axi_wstrb <= "00001000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "010") THEN axi_wstrb <= "00000100"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "001") THEN axi_wstrb <= "00000010"; ELSE axi_wstrb <= "00000001"; END IF; ELSE -- For all bursts IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN --axi_wstrb <= ShiftLeft("00000001", to_integer(HADDR_sync(2 DOWNTO 0))); IF ((HADDR_sync(2 DOWNTO 0)) = "111") THEN axi_wstrb <= "10000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "110") THEN axi_wstrb <= "01000000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "101") THEN axi_wstrb <= "00100000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "100") THEN axi_wstrb <= "00010000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "011") THEN axi_wstrb <= "00001000"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "010") THEN axi_wstrb <= "00000100"; ELSIF ((HADDR_sync(2 DOWNTO 0)) = "001") THEN axi_wstrb <= "00000010"; ELSE axi_wstrb <= "00000001"; END IF; ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF (axi_wstrb = "10000000") THEN axi_wstrb <= "00000001"; ELSE --axi_wstrb <= ShiftLeft(axi_wstrb, 1); axi_wstrb <= axi_wstrb(6 DOWNTO 0) & '0'; END IF; END IF; END IF; END IF; -- For Single/Undef WHEN OTHERS => axi_wstrb <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0'; END CASE; END IF; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN wrstb_count <= "00"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (WLAST_xhdl10 = '1') THEN wrstb_count <= "00"; ELSE IF ((wvalid_reg = '1') AND (axi_next_state = SEND_WR_DATA)) THEN wrstb_count <= wrstb_count + "01"; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Generate the address increment logic on AXI -- This is write data generation on the AXI interface ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN latch_ahb_sig_sync_d <= '0'; axi_wr_data_d <= (OTHERS => '0'); AWADDR_incr <= "000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN latch_ahb_sig_sync_d <= latch_ahb_sig_sync; axi_wr_data_d <= axi_wr_data(AXI_DWIDTH - 1 DOWNTO 0); IF ((AWVALID_xhdl6 AND AWREADY) = '1') THEN AWADDR_incr <= AWADDR_xhdl2(2 DOWNTO 0); ELSE IF ((WVALID_xhdl11 AND WREADY) = '1') THEN IF ((HSIZE_sync(1 DOWNTO 0)) = "00") THEN AWADDR_incr <= AWADDR_incr + "001"; ELSIF ((HSIZE_sync(1 DOWNTO 0)) = "01") THEN AWADDR_incr <= AWADDR_incr + "010"; ELSE AWADDR_incr <= AWADDR_incr + "100"; END IF; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Create a sync pulse to trigger the AXI state machine when there is valid -- AHB command ------------------------------------------------------------------------------- store_ahb_sig <= latch_ahb_sig_sync AND (NOT latch_ahb_sig_sync_d) ; ------------------------------------------------------------------------------- -- Synchronize the AHB signals to AXI clock on store_ahb_sig signal ------------------------------------------------------------------------------- ahb_to_axi_latch_logic : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN HSEL_sync <= '0'; HADDR_sync <= (OTHERS => '0'); HWRITE_sync <= '0'; HREADY_sync <= '0'; HTRANS_sync <= "00"; HSIZE_sync <= "000"; HBURST_sync <= "000"; HMASTLOCK_sync <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (store_ahb_sig = '1') THEN HSEL_sync <= HSEL; HADDR_sync <= HADDR; HWRITE_sync <= HWRITE; HREADY_sync <= HREADY; HTRANS_sync <= HTRANS; HSIZE_sync <= HSIZE; HBURST_sync <= HBURST; HMASTLOCK_sync <= HMASTLOCK; END IF; END IF; END PROCESS ahb_to_axi_latch_logic; L0: IF (UNDEF_BURST = 1) GENERATE undef_wr_burst_size_32 <= "0111" ; undef_wr_burst_size_64 <= "1111" ; undef_rd_burst_size_32 <= "1111" ; undef_rd_burst_size_64 <= "1111" ; END GENERATE L0; L1: IF (NOT(UNDEF_BURST = 1)) GENERATE undef_wr_burst_size_32 <= "0000" ; undef_wr_burst_size_64 <= "0000" ; undef_rd_burst_size_32 <= "0000" ; undef_rd_burst_size_64 <= "0000" ; END GENERATE L1; L2: IF (AHB_DWIDTH = 32) GENERATE ------------------------------------------------------------------------------- -- Generate AXI Write channel Burst Length from HBURST and HSYNC ------------------------------------------------------------------------------- PROCESS ( HSIZE_sync, HADDR_sync, undef_wr_burst_size_32, HBURST_sync) BEGIN IF (HSIZE_sync(1 DOWNTO 0) = "00") THEN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) -- if (HSIZE_sync[1:0] == 2'b00) ELSE IF (HSIZE_sync(1 DOWNTO 0) = "01") THEN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) -- if (HSIZE_sync[1:0] == 2'b01) ELSE IF (HADDR_sync(2) = '0') THEN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0001"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0011"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "0111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) -- if (HSIZE_sync[1:0] == 2'b01) ELSE CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_32; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) END IF; END IF; END IF; -- else: !if(HSIZE_sync[1:0] == 2'b10) END PROCESS; END GENERATE L2; L3: IF (NOT(AHB_DWIDTH = 32)) GENERATE -- always @ (*) -- block: axiwr_burst_length_ahb32 PROCESS (undef_wr_burst_size_64, HBURST_sync) BEGIN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axiwr_burst_length <= "0000"; WHEN "001" => axiwr_burst_length <= undef_wr_burst_size_64; WHEN "010" => axiwr_burst_length <= "0011"; WHEN "011" => axiwr_burst_length <= "0011"; WHEN "100" => axiwr_burst_length <= "0111"; WHEN "101" => axiwr_burst_length <= "0111"; WHEN "110" => axiwr_burst_length <= "1111"; WHEN "111" => axiwr_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; -- case (HBURST_sync[2:0]) END PROCESS; END GENERATE L3; L4: IF (AHB_DWIDTH = 32) GENERATE ------------------------------------------------------------------------------- -- Generate AXI Read channel Burst Length from HBURST and HSYNC ------------------------------------------------------------------------------- PROCESS (undef_rd_burst_size_32, HBURST_sync) BEGIN -- orig CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axird_burst_length <= "0000"; WHEN "001" => axird_burst_length <= undef_rd_burst_size_32; WHEN "010" => axird_burst_length <= "0011"; WHEN "011" => axird_burst_length <= "0011"; WHEN "100" => axird_burst_length <= "0111"; WHEN "101" => axird_burst_length <= "0111"; WHEN "110" => axird_burst_length <= "1111"; WHEN "111" => axird_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; END PROCESS; END GENERATE L4; L5: IF (NOT(AHB_DWIDTH = 32)) GENERATE -- always @ (*) PROCESS (undef_rd_burst_size_64, HBURST_sync) BEGIN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axird_burst_length <= "0000"; WHEN "001" => axird_burst_length <= undef_rd_burst_size_64; WHEN "010" => axird_burst_length <= "0011"; WHEN "011" => axird_burst_length <= "0011"; WHEN "100" => axird_burst_length <= "0111"; WHEN "101" => axird_burst_length <= "0111"; WHEN "110" => axird_burst_length <= "1111"; WHEN "111" => axird_burst_length <= "1111"; WHEN OTHERS => NULL; END CASE; END PROCESS; END GENERATE L5; ------------------------------------------------------------------------------- -- Extract AXI Burst type from HBURST ------------------------------------------------------------------------------- PROCESS (HBURST_sync) BEGIN CASE HBURST_sync(2 DOWNTO 0) IS WHEN "000" => axi_burst_type <= "01"; WHEN "001" => axi_burst_type <= "01"; WHEN "010" => axi_burst_type <= "10"; WHEN "011" => axi_burst_type <= "01"; WHEN "100" => axi_burst_type <= "10"; WHEN "101" => axi_burst_type <= "01"; WHEN "110" => axi_burst_type <= "10"; WHEN "111" => axi_burst_type <= "01"; WHEN OTHERS => NULL; END CASE; END PROCESS; ------------------------------------------------------------------------------- -- Synchronize burst count value received from the AHB Access Control logic -- This is used for for loading the initial value in burstcount_reg signal ------------------------------------------------------------------------------- sync_ahb_2_axi : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN burst_count_r_sync <= "0000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (burst_count_valid_sync = '1') THEN burst_count_r_sync <= burst_count_r(3 DOWNTO 0); END IF; END IF; END PROCESS sync_ahb_2_axi; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN awaddr_awvalid_clr_d <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN awaddr_awvalid_clr_d <= awaddr_awvalid_clr; END IF; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN araddr_arvalid_clr_d <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN araddr_arvalid_clr_d <= araddr_arvalid_clr; END IF; END PROCESS; --*****************************************************************// -- Write Data Channel // --*****************************************************************// ------------------------------------------------------------------------------- -- Latch AHB signals into AXI domain on synchronised control signal ------------------------------------------------------------------------------- WDATA_xhdl8 <= axi_wrdata(AXI_DWIDTH - 1 DOWNTO 0) ; WSTRB_xhdl9 <= axi_wstrb ; WID_xhdl7 <= "0000" ; WLAST_xhdl10 <= wvalid_clr ; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN WREADY_reg <= '0'; wvalid_reg_r <= '0'; wvalid_clr_r <= '0'; axi_wr_data_lat <= (OTHERS => '0'); ELSIF (ACLK'EVENT AND ACLK = '1') THEN WREADY_reg <= WREADY; wvalid_reg_r <= wvalid_reg; wvalid_clr_r <= wvalid_clr; axi_wr_data_lat <= axi_wrdata; END IF; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN wvalid_set_r <= '0'; wvalid_set_r1 <= '0'; burstcount_reg_r <= "00000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN wvalid_set_r <= wvalid_set AND NOT wvalid_reg; wvalid_set_r1 <= wvalid_set_r; burstcount_reg_r <= burstcount_reg; END IF; END PROCESS; ------------------------------------------------------------------------------- -- The logic is used to de-assert the WVALID ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN wvalid_clr_t <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (axi_current_state = SEND_WR_DATA AND wvalid_clr = '1') THEN wvalid_clr_t <= '1'; ELSE wvalid_clr_t <= '0'; END IF; END IF; END PROCESS; temp_xhdl42 <= ((NOT wvalid_clr AND wvalid_reg) AND CONV_STD_LOGIC(axi_next_state = SEND_WR_DATA)) WHEN WREADY = '1' ELSE wvalid_reg; ------------------------------------------------------------------------------- -- Generation of WVALID signal -- wvalid_set asserts the WVALID and wvalid_clr signal de-asserts it. ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN WVALID_xhdl11 <= '0'; wvalid_reg <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (wvalid_clr = '1' AND WREADY = '1') THEN wvalid_reg <= '0'; ELSE IF (wvalid_set = '1' AND wvalid_clr_t = '0') THEN wvalid_reg <= '1'; END IF; END IF; WVALID_xhdl11 <= temp_xhdl42; END IF; END PROCESS; --*****************************************************************// -- Write Address Channel // --*****************************************************************// ------------------------------------------------------------------------------- -- Write address channel generation ------------------------------------------------------------------------------- AWVALID_xhdl6 <= '0' WHEN awaddr_awvalid_clr_d = '1' ELSE AWVALID_xhdl6_int; AWVALID_xhdl6_int <= '1' WHEN awaddr_awvalid_set = '1' ELSE '0'; PROCESS (HADDR_sync, axiwr_burst_length(3 DOWNTO 0), axi_burst_type(1 DOWNTO 0), HMASTLOCK_sync, HBURST_sync(2 DOWNTO 0), HSIZE_sync(2 DOWNTO 0)) BEGIN AWADDR_xhdl2 <= HADDR_sync(AXI_AWIDTH - 1 DOWNTO 0); AWID_xhdl1 <= "0000"; AWLEN_xhdl3 <= axiwr_burst_length(3 DOWNTO 0); AWBURST_xhdl5 <= axi_burst_type(1 DOWNTO 0); AWLOCK_xhdl21 <= HMASTLOCK_sync & '0'; IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN AWSIZE_xhdl4 <= HSIZE_sync(2 DOWNTO 0); ELSE -- For all bursts IF (HBURST_sync(0) = '1') THEN -- For incr IF (HADDR_sync(2) = '0') THEN -- 30/01/13 added to check whether address starts from '4 CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "00" => AWSIZE_xhdl4 <= "000"; -- 1 bytes in one transfer WHEN "01" => AWSIZE_xhdl4 <= "001"; -- 2 bytes in one transfer WHEN "10" => AWSIZE_xhdl4 <= "011"; -- 8 bytes in one transfer WHEN "11" => AWSIZE_xhdl4 <= "011"; WHEN OTHERS => AWSIZE_xhdl4 <= "011"; END CASE; -- case (HSIZE_sync[1:0]) ELSE CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "00" => AWSIZE_xhdl4 <= "000"; -- 1 bytes in one transfer WHEN "01" => AWSIZE_xhdl4 <= "001"; -- 2 bytes in one transfer WHEN "10" => AWSIZE_xhdl4 <= "010"; -- 4 bytes in one transfer WHEN "11" => AWSIZE_xhdl4 <= "011"; WHEN OTHERS => AWSIZE_xhdl4 <= "011"; END CASE; -- case (HSIZE_sync[1:0]) END IF; ELSE -- For wrap CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "00" => AWSIZE_xhdl4 <= "000"; -- 1 bytes in one transfer WHEN "01" => AWSIZE_xhdl4 <= "001"; -- 2 bytes in one transfer WHEN "10" => AWSIZE_xhdl4 <= "010"; -- 4 bytes in one transfer WHEN "11" => AWSIZE_xhdl4 <= "011"; WHEN OTHERS => AWSIZE_xhdl4 <= "011"; END CASE; -- case (HSIZE_sync[1:0]) END IF; END IF; END PROCESS; temp_xhdl43 <= ShiftRight(burst_count_r_sync(3 DOWNTO 0), 1) WHEN (HADDR_sync(2) = '0') ELSE burst_count_r_sync(3 DOWNTO 0); ------------------------------------------------------------------------------- -- burstcount_reg holds the burst count value -- The count value is decremented on the burstcount_dec assertion ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN burstcount_reg <= "00000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN -- Load the burst count value IF (burstcount_load = '1') THEN IF ((HSIZE_sync(1 DOWNTO 0) = "00" AND HBURST_sync /= "000") AND HBURST_sync /= "001") THEN -- Byte bursts IF (HBURST_sync(0) = '1') THEN -- incr burstcount_reg <= "00001" + (burst_count_r_sync(3 DOWNTO 0)); ELSE -- wrap burstcount_reg <= "0" & burst_count_r_sync(3 DOWNTO 0); END IF; ELSE IF ((HSIZE_sync(1 DOWNTO 0) = "01" AND HBURST_sync /= "000") AND HBURST_sync /= "001") THEN -- HW bursts burstcount_reg <= "00001" + (burst_count_r_sync(3 DOWNTO 0)); ELSE IF ((HSIZE_sync(1 DOWNTO 0) = "10" AND HBURST_sync /= "000") AND HBURST_sync /= "001") THEN -- Word bursts IF (HBURST_sync(0) = '1') THEN burstcount_reg <= "00001" + (temp_xhdl43); ELSE -- wrap burstcount_reg <= "0" & burst_count_r_sync(3 DOWNTO 0); END IF; ELSE IF (HSIZE_sync(1 DOWNTO 0) = "10" AND HBURST_sync = "001") THEN -- Word undef burstcount_reg <= "00001" + ShiftRight(burst_count_r_sync(3 DOWNTO 0), 1); ELSE -- Single burstcount_reg <= "00001" + ShiftRight(burst_count_r_sync(3 DOWNTO 0), 1); END IF; END IF; END IF; END IF; ELSE IF (burstcount_dec = '1') THEN burstcount_reg <= burstcount_reg - "00001"; END IF; END IF; END IF; END PROCESS; --*****************************************************************// -- Write Response Channel // --*****************************************************************// ------------------------------------------------------------------------------- -- Generation of BREADY write response ready signal -- BREADY is always asserted ------------------------------------------------------------------------------- BREADY_xhdl12 <= '1' ; BRESP_sync_xhdl23 <= latch_wr_resp(1 DOWNTO 0) ; ------------------------------------------------------------------------------- -- Latch the write response received on the response channel ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN latch_wr_resp <= "00"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN -- write response IF (latch_wr_resp_set = '1') THEN latch_wr_resp(1 DOWNTO 0) <= BRESP(1 DOWNTO 0); END IF; END IF; -- else: !if(ARESETn == 1'b0) END PROCESS; -- always @ (posedge ACLK or negedge ARESETn) PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN BVALID_reg <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN BVALID_reg <= BVALID; END IF; END PROCESS; --*****************************************************************// -- Read Address Channel // --*****************************************************************// ------------------------------------------------------------------------------- -- AXI Read Address channel generation ------------------------------------------------------------------------------- ARVALID_xhdl19 <= '0' WHEN araddr_arvalid_clr_d = '1' ELSE ARVALID_xhdl19_int; ARVALID_xhdl19_int <= '1' WHEN araddr_arvalid_set = '1' ELSE '0'; PROCESS (HADDR_sync, axird_burst_length(3 DOWNTO 0), HSIZE_sync(2 DOWNTO 0), axi_burst_type(1 DOWNTO 0), HMASTLOCK_sync) BEGIN ARADDR_xhdl14 <= HADDR_sync(AXI_AWIDTH - 1 DOWNTO 0); ARID_xhdl13 <= "0000"; ARLEN_xhdl15 <= axird_burst_length(3 DOWNTO 0); ARSIZE_xhdl16 <= HSIZE_sync(2 DOWNTO 0); ARBURST_xhdl17 <= axi_burst_type(1 DOWNTO 0); ARLOCK_xhdl18 <= HMASTLOCK_sync & '0'; END PROCESS; ------------------------------------------------------------------------------- -- Generation of write enable to RDCHANNEL fifo ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN ahb_rd_req_sync_d <= '0'; rdch_fifo_wr_en_r_xhdl24 <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN ahb_rd_req_sync_d <= ahb_rd_req_sync; rdch_fifo_wr_en_r_xhdl24 <= axi_read_data; END IF; END PROCESS; --*****************************************************************// -- Read Data Channel // --*****************************************************************// ------------------------------------------------------------------------------- -- Generation of RREADY ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN RREADY_xhdl20 <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (rready_set = '1') THEN RREADY_xhdl20 <= '1'; ELSE RREADY_xhdl20 <= '0'; END IF; END IF; END PROCESS; rd_haddr <= HADDR_sync ; ------------------------------------------------------------------------------- -- Latch the incoming read data from the AXI Read data channel ------------------------------------------------------------------------------- PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN rdch_write_data_r <= (OTHERS => '0'); ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (axi_read_data = '1') THEN rdch_write_data_r(AXI_DWIDTH - 1 DOWNTO 0) <= RDATA(AXI_DWIDTH - 1 DOWNTO 0); END IF; END IF; END PROCESS; temp_xhdl45 <= rdch_write_data_r(31 DOWNTO 0) WHEN (swap_rd_data_byte(0) = '1') ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl46 <= rdch_write_data_r(63 DOWNTO 32) WHEN (swap_rd_data_byte(0) = '1') ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl47 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "01") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl48 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "11") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl49 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "01") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl50 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(1 DOWNTO 0) = "11") OR (swap_rd_data_byte(1 DOWNTO 0) = "10")) ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl51 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(2 DOWNTO 0) = "001") OR (swap_rd_data_byte(2 DOWNTO 0) = "010") OR (swap_rd_data_byte(2 DOWNTO 0) = "011") OR (swap_rd_data_byte(2 DOWNTO 0) = "000")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl52 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(2 DOWNTO 0) = "101") OR (swap_rd_data_byte(2 DOWNTO 0) = "110") OR (swap_rd_data_byte(2 DOWNTO 0) = "111") OR (swap_rd_data_byte(2 DOWNTO 0) = "100")) ELSE rdch_write_data_r(31 DOWNTO 0); temp_xhdl53 <= rdch_write_data_r(31 DOWNTO 0) WHEN ((swap_rd_data_byte(3 DOWNTO 0) = "0001") OR (swap_rd_data_byte(3 DOWNTO 0) = "0010") OR (swap_rd_data_byte(3 DOWNTO 0) = "1001") OR (swap_rd_data_byte(3 DOWNTO 0) = "1010") OR (swap_rd_data_byte(3 DOWNTO 0) = "1011") OR (swap_rd_data_byte(3 DOWNTO 0) = "1100") OR (swap_rd_data_byte(3 DOWNTO 0) = "0011") OR (swap_rd_data_byte(3 DOWNTO 0) = "0100")) ELSE rdch_write_data_r(63 DOWNTO 32); temp_xhdl54 <= rdch_write_data_r(63 DOWNTO 32) WHEN ((swap_rd_data_byte(3 DOWNTO 0) = "1000") OR (swap_rd_data_byte(3 DOWNTO 0) = "0101") OR (swap_rd_data_byte(3 DOWNTO 0) = "1101") OR (swap_rd_data_byte(3 DOWNTO 0) = "1110") OR (swap_rd_data_byte(3 DOWNTO 0) = "1111") OR (swap_rd_data_byte(3 DOWNTO 0) = "0000") OR (swap_rd_data_byte(3 DOWNTO 0) = "0110") OR (swap_rd_data_byte(3 DOWNTO 0) = "0111")) ELSE rdch_write_data_r(31 DOWNTO 0) ; PROCESS (rdch_write_data_r, HSIZE_sync, HBURST_sync, temp_xhdl45, rd_haddr, temp_xhdl46, temp_xhdl47, temp_xhdl48, temp_xhdl49, temp_xhdl50, temp_xhdl51, temp_xhdl52, temp_xhdl53,temp_xhdl54 ) VARIABLE rd_data_c_xhdl44 : std_logic_vector(AHB_DWIDTH - 1 DOWNTO 0); BEGIN CASE HSIZE_sync(1 DOWNTO 0) IS WHEN "11" => rd_data_c_xhdl44 := rdch_write_data_r(AXI_DWIDTH - 1 DOWNTO 0) (31 DOWNTO 0); WHEN "10" => IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN -- For Single/undef IF (rd_haddr(2 DOWNTO 0) = "000") THEN rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(31 DOWNTO 0); ELSE rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(63 DOWNTO 32); END IF; ELSE -- For all other burst types IF (rd_haddr(2 DOWNTO 0) = "000") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl45; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl46; END IF; END IF; -- else: !if(HBURST_sync[2:0] == 3'b000) WHEN "01" => IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN -- For Single/undef IF (rd_haddr(2 DOWNTO 0) < "100") THEN IF (rd_haddr(1 DOWNTO 0) = "00" OR rd_haddr(1 DOWNTO 0) = "10") THEN rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(31 DOWNTO 0); ELSE rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(63 DOWNTO 32); END IF; ELSE IF (rd_haddr(1 DOWNTO 0) = "00" OR rd_haddr(1 DOWNTO 0) = "10") THEN rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(63 DOWNTO 32); ELSE rd_data_c_xhdl44(31 DOWNTO 0) := rdch_write_data_r(31 DOWNTO 0); END IF; END IF; -- else: !if(rd_haddr[2:0] < 3'b100) ELSE -- For all other burst types IF (rd_haddr(2 DOWNTO 0) < "100") THEN IF (rd_haddr(1 DOWNTO 0) = "00") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl47; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl48; END IF; ELSE IF (rd_haddr(1 DOWNTO 0) = "00") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl49; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl50; END IF; END IF; -- else: !if(rd_haddr[2:0] < 3'b100) END IF; -- else: !if(HBURST_sync[2:0] == 3'b000) WHEN "00" => IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN -- For Single/undef IF (rd_haddr(2 DOWNTO 0) < "100") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl51; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl52; END IF; ELSE -- For all other burst types IF (rd_haddr(2 DOWNTO 0) < "100") THEN rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl53; ELSE rd_data_c_xhdl44(31 DOWNTO 0) := temp_xhdl54; END IF; END IF; WHEN OTHERS => rd_data_c_xhdl44 := (OTHERS => '0'); END CASE; rd_data_c <= rd_data_c_xhdl44; END PROCESS; PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN swap_rd_data_byte <= "0000"; ELSIF (ACLK'EVENT AND ACLK = '1') THEN IF (HBURST_sync(2 DOWNTO 0) = "000" OR HBURST_sync(2 DOWNTO 0) = "001") THEN swap_rd_data_byte <= '0' & HADDR_sync(2 DOWNTO 0); ELSE IF ((ARREADY AND ARVALID_xhdl19) = '1') THEN swap_rd_data_byte <= '0' & ARADDR_xhdl14(2 DOWNTO 0); ELSE IF ((RREADY_xhdl20 AND RVALID) = '1') THEN swap_rd_data_byte <= swap_rd_data_byte + "0001"; END IF; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- -- Write data to RDCHANNEL fifo -- The data is the Read data from AXI Read data channel ------------------------------------------------------------------------------- rdch_fifo_wr_data_xhdl25 <= rd_data_c ; ------------------------------------------------------------------------------- -- Generate start signal for read channel fifo to enable read from AHB side ------------------------------------------------------------------------------- gen_start_for_rdch_read : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN axi_read_rlast_xhdl26 <= '0'; ELSIF (ACLK'EVENT AND ACLK = '1') THEN axi_read_rlast_xhdl26 <= (RLAST AND RVALID) AND RREADY_xhdl20; END IF; END PROCESS gen_start_for_rdch_read; ------------------------------------------------------------------------------- -- Invokes the AXI State machine on ahb_rd_req coming from the AHB Access Ctrl ------------------------------------------------------------------------------- axi_rd_start <= NOT ahb_rd_req_sync AND ahb_rd_req_sync_d ; ------------------------------------------------------------------------------- -- Sequential block for State Machine ------------------------------------------------------------------------------- axi_state_machine_seq_logic : PROCESS (ACLK, ARESETn) BEGIN IF (ARESETn = '0') THEN axi_current_state <= IDLE; ELSIF (ACLK'EVENT AND ACLK = '1') THEN axi_current_state <= axi_next_state; END IF; END PROCESS axi_state_machine_seq_logic; temp_xhdl70 <= burstcount_reg(0) WHEN (HSIZE_sync(1 DOWNTO 0) = "00") ELSE '1'; ------------------------------------------------------------------------------- -- Combinational block for State Machine ------------------------------------------------------------------------------- axi_state_machine_combo_logic : PROCESS (axi_current_state, HSIZE_sync, RVALID, ahb_wr_done_sync, RREADY_xhdl20, HADDR_sync, AWREADY, RLAST, wvalid_reg_r, axi_next_state, ARREADY, BREADY_xhdl12, BVALID_reg, wvalid_set_r, HWRITE_sync, HBURST_sync, WREADY, burstcount_reg, RRESP, wvalid_set_r1, temp_xhdl70, wvalid_reg, axi_rd_start) VARIABLE axi_next_state_xhdl55 : std_logic_vector(2 DOWNTO 0); VARIABLE awaddr_awvalid_set_xhdl56 : std_logic; VARIABLE araddr_arvalid_set_xhdl57 : std_logic; VARIABLE awaddr_awvalid_clr_xhdl58 : std_logic; VARIABLE araddr_arvalid_clr_xhdl59 : std_logic; VARIABLE wvalid_set_xhdl60 : std_logic; VARIABLE wvalid_clr_xhdl61 : std_logic; VARIABLE bready_set_xhdl62 : std_logic; VARIABLE burstcount_load_xhdl63 : std_logic; VARIABLE burstcount_dec_xhdl64 : std_logic; VARIABLE WRCH_fifo_rd_en_xhdl22_xhdl65 : std_logic; VARIABLE latch_wr_resp_set_xhdl66 : std_logic; VARIABLE axi_read_resp_xhdl67 : std_logic_vector(1 DOWNTO 0); VARIABLE axi_read_data_xhdl68 : std_logic; VARIABLE rready_set_xhdl69 : std_logic; BEGIN axi_next_state_xhdl55 := axi_current_state; awaddr_awvalid_set_xhdl56 := '0'; araddr_arvalid_set_xhdl57 := '0'; awaddr_awvalid_clr_xhdl58 := '0'; araddr_arvalid_clr_xhdl59 := '0'; wvalid_set_xhdl60 := '0'; wvalid_clr_xhdl61 := '0'; bready_set_xhdl62 := '0'; burstcount_load_xhdl63 := '0'; burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; latch_wr_resp_set_xhdl66 := '0'; axi_read_resp_xhdl67(1 DOWNTO 0) := "00"; axi_read_data_xhdl68 := '0'; rready_set_xhdl69 := '0'; CASE axi_current_state IS ----------------------------------------- -- IDLE STATE ----------------------------------------- WHEN IDLE => IF (ahb_wr_done_sync = '1') THEN axi_next_state_xhdl55 := SEND_WR_ADDR; ELSE IF (axi_rd_start = '1') THEN axi_next_state_xhdl55 := SEND_RD_ADDR; END IF; END IF; --------------------------------------------- -- SEND WRITE ADDRESS AND CONTROL ON AXI BUS --------------------------------------------- WHEN SEND_WR_ADDR => awaddr_awvalid_set_xhdl56 := '1'; burstcount_load_xhdl63 := '1'; IF (AWREADY = '1') THEN awaddr_awvalid_clr_xhdl58 := '1'; CASE HWRITE_sync IS WHEN WRITE_C => axi_next_state_xhdl55 := SEND_WR_DATA; WHEN READ_C => axi_next_state_xhdl55 := READ_RD_DATA; WHEN OTHERS => NULL; END CASE; ELSE awaddr_awvalid_clr_xhdl58 := '0'; END IF; WHEN SEND_WR_DATA => burstcount_load_xhdl63 := '0'; bready_set_xhdl62 := '1'; wvalid_set_xhdl60 := '1'; IF (HBURST_sync = "000") THEN -- All Single --IF (wvalid_reg_r = '1' AND WREADY = '1') THEN IF (wvalid_reg_r = '1' AND wvalid_reg = '1') THEN --SAR#57250 - WREADY condition added wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (burstcount_reg = "00000") THEN -- Last burst count axi_next_state_xhdl55 := READ_WR_RESP; ELSE -- Not a last burst count IF (wvalid_reg = '1' AND wvalid_set_r = '1') THEN WRCH_fifo_rd_en_xhdl22_xhdl65 := temp_xhdl70; ELSE WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; IF (wvalid_reg_r = '1' AND WREADY = '1') THEN --SAR#57250 - WREADY condition added burstcount_dec_xhdl64 := '1'; ELSE burstcount_dec_xhdl64 := '0'; END IF; END IF; -- For word undef ELSE IF (HBURST_sync = "001" AND HSIZE_sync(1 DOWNTO 0) = "10") THEN IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; -- For Halfword undef ELSE IF (HBURST_sync = "001" AND HSIZE_sync(1 DOWNTO 0) = "01") THEN IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; -- For Byte undef ELSE IF (HBURST_sync = "001" AND HSIZE_sync(1 DOWNTO 0) = "00") THEN IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; ELSE -- All Bursts IF (burstcount_reg = "00000") THEN IF (wvalid_reg = '1') THEN wvalid_clr_xhdl61 := '1'; ELSE wvalid_clr_xhdl61 := '0'; END IF; IF (wvalid_reg = '1' AND WREADY = '1') THEN axi_next_state_xhdl55 := READ_WR_RESP; END IF; ELSE -- Not a last burst count IF (HBURST_sync(0) = '1') THEN -- incr bursts IF ((WREADY AND wvalid_reg) = '1') THEN burstcount_dec_xhdl64 := '1'; IF (HSIZE_sync(1 DOWNTO 0) = "00" OR HSIZE_sync(1 DOWNTO 0) = "01") THEN -- 30/01/13 - check whether start addr = '4 WRCH_fifo_rd_en_xhdl22_xhdl65 := NOT burstcount_reg(0); ELSE IF (HSIZE_sync(1 DOWNTO 0) = "10" AND HADDR_sync(2) = '1') THEN -- 30/01/13 - check whether start addr = '4 WRCH_fifo_rd_en_xhdl22_xhdl65 := NOT burstcount_reg(0); -- else if (HADDR_sync[2] == 1'b0 && HSIZE_sync[1:0] == 2'b10) begin // 30/01/13 - check whether start addr = '4 ELSE -- 30/01/13 - check whether start addr = '4 WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; END IF; END IF; ELSE burstcount_dec_xhdl64 := '0'; WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; ELSE -- wrap bursts IF (((WREADY AND wvalid_reg) AND NOT wvalid_set_r1) = '1') THEN burstcount_dec_xhdl64 := '1'; ELSE burstcount_dec_xhdl64 := '0'; END IF; IF ((wvalid_set_r OR ((NOT burstcount_reg(0) AND WREADY) AND NOT wvalid_set_r1)) = '1') THEN -- wrap WRCH_fifo_rd_en_xhdl22_xhdl65 := '1'; ELSE WRCH_fifo_rd_en_xhdl22_xhdl65 := '0'; END IF; END IF; -- else: !if(HBURST_sync[0] == 1'b1) END IF; END IF; END IF; END IF; END IF; --------------------------------------------- -- GET WRITE RESPONSE FROM AXI SLAVE --------------------------------------------- WHEN READ_WR_RESP => IF ((BVALID_reg = '1') AND (BREADY_xhdl12 = '1')) THEN latch_wr_resp_set_xhdl66 := '1'; axi_next_state_xhdl55 := IDLE; ELSE latch_wr_resp_set_xhdl66 := '0'; END IF; --------------------------------------------- -- SEND READ ADDRESS AND CONTROL ON AXI BUS --------------------------------------------- WHEN SEND_RD_ADDR => araddr_arvalid_set_xhdl57 := '1'; burstcount_load_xhdl63 := '1'; rready_set_xhdl69 := '1'; IF (ARREADY = '1') THEN araddr_arvalid_clr_xhdl59 := '1'; CASE HWRITE_sync IS WHEN WRITE_C => axi_next_state_xhdl55 := SEND_WR_DATA; WHEN READ_C => axi_next_state_xhdl55 := READ_RD_DATA; WHEN OTHERS => NULL; END CASE; ELSE araddr_arvalid_clr_xhdl59 := '0'; END IF; -- Error respnose WHEN READ_RD_DATA => burstcount_load_xhdl63 := '0'; rready_set_xhdl69 := '1'; axi_read_data_xhdl68 := '0'; IF (RLAST = '1') THEN -- Last burst transfer IF (RVALID = '1') THEN axi_read_data_xhdl68 := '1'; IF (RRESP = RESPOK_C) THEN axi_read_resp_xhdl67(1 DOWNTO 0) := RESPOK_C; ELSE axi_read_resp_xhdl67(1 DOWNTO 0) := RESPERR_C; END IF; axi_next_state_xhdl55 := IDLE; rready_set_xhdl69 := '0'; ELSE END IF; ELSE IF ((RVALID = '1') AND (RREADY_xhdl20 = '1')) THEN axi_read_data_xhdl68 := '1'; IF (RRESP = RESPOK_C) THEN axi_read_resp_xhdl67(1 DOWNTO 0) := RESPOK_C; ELSE axi_read_resp_xhdl67(1 DOWNTO 0) := RESPERR_C; END IF; ELSE END IF; END IF; -- OKAY response WHEN OTHERS => axi_next_state_xhdl55 := axi_current_state; END CASE; axi_next_state <= axi_next_state_xhdl55; awaddr_awvalid_set <= awaddr_awvalid_set_xhdl56; araddr_arvalid_set <= araddr_arvalid_set_xhdl57; awaddr_awvalid_clr <= awaddr_awvalid_clr_xhdl58; araddr_arvalid_clr <= araddr_arvalid_clr_xhdl59; wvalid_set <= wvalid_set_xhdl60; wvalid_clr <= wvalid_clr_xhdl61; bready_set <= bready_set_xhdl62; burstcount_load <= burstcount_load_xhdl63; burstcount_dec <= burstcount_dec_xhdl64; WRCH_fifo_rd_en_xhdl22 <= WRCH_fifo_rd_en_xhdl22_xhdl65; latch_wr_resp_set <= latch_wr_resp_set_xhdl66; axi_read_resp <= axi_read_resp_xhdl67; axi_read_data <= axi_read_data_xhdl68; rready_set <= rready_set_xhdl69; END PROCESS axi_state_machine_combo_logic; END ARCHITECTURE translated;

<filename>ip/MIPI_D_PHY_RX/tb/tb_DPHY_LaneSFEN.vhd ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/04/2016 05:12:32 PM -- Design Name: -- Module Name: tb_DPHY_LaneSFEN - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.math_real.all; use IEEE.std_logic_textio.all; -- I/O for logic types library STD; use STD.textio.all; -- basic I/O -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tb_DPHY_LaneSFEN is -- Port ( ); end tb_DPHY_LaneSFEN; architecture Behavioral of tb_DPHY_LaneSFEN is component DPHY_LaneSFEN is Generic ( kCtlClkFreqHz : natural := 100_000_000 ); Port ( aLP : in STD_LOGIC_VECTOR (1 downto 0); aHS : in STD_LOGIC; CtlClk : in STD_LOGIC; SerClkHS : in STD_LOGIC; DivClk : in STD_LOGIC; RxByteClkHS : out std_logic; rbRxDataHS : out std_logic_vector(7 downto 0); rbRxValidHS : out std_logic; rbRxActiveHS : out std_logic; rbRxSyncHS : out std_logic; rbErrSotHS : out std_logic; rbErrSotSyncHS : out std_logic; aEnable : in std_logic; --Enable Lane Module. DivClk&SerClkHS must be stable aForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state aStopstate : out std_logic --Lane is in Stop state. ); end component DPHY_LaneSFEN; function max(l : time; r : time) return time is begin if (l > r) then return l; else return r; end if; end function max; constant kSerClkPeriod : time := 2 ns; constant kCtlClkPeriod : time := 10 ns; constant kUI : time := kSerClkPeriod / 2; constant kT_LPX : time := 50 ns; constant kT_HS_PREPARE : time := 40 ns + 4*kUI; constant kT_HS_ZERO : time := 100 ns + 6*kUI; constant kT_HS_TRAIL : time := max(1*8*kUI, 60 ns + 1*4*kUI); constant kT_HS_EXIT : time := 100 ns; constant kTInit : time := 100 us; constant kSyncSeq : std_logic_vector(7 downto 0) := "10111000"; --least significant bit signal SerClkHS, DivClkHS, CtlClk, cHSClkLocked : std_logic := '1'; signal HS : std_logic; signal LP : std_logic_vector(1 downto 0); signal rbRxDataHS : std_logic_vector(7 downto 0); signal rbRxValidHS, rbRxActiveHS, rbRxSyncHS, rbErrSotHS, rbErrSotSyncHS, aDataStopstate : std_logic; signal RxByteClkHS : std_logic; begin DUT: DPHY_LaneSFEN Port map ( aLP => LP, aHS => HS, CtlClk => CtlClk, SerClkHS => SerClkHS, DivClk => DivClkHS, --PPI RxByteClkHS => RxByteClkHS, rbRxDataHS => rbRxDataHS, rbRxValidHS => rbRxValidHS, rbRxActiveHS => rbRxActiveHS, rbRxSyncHS => rbRxSyncHS, rbErrSotHS => rbErrSotHS, rbErrSotSyncHS => rbErrSotSyncHS, aEnable => '1', aStopstate => aDataStopstate, aForceRxmode => '0' ); --Clocks SerClkHS <= not SerClkHS after kSerClkPeriod / 2; DivClkHS <= not DivClkHS after kSerClkPeriod / 2 * 4; CtlClk <= not CtlClk after kCtlClkPeriod / 2; Stimulus: process procedure Stopstate(dur : in time) is begin LP <= "11"; HS <= 'X'; wait for dur; end procedure; procedure HS_Rqst is begin LP <= "01"; wait for kT_LPX; end procedure; procedure HS_Prepare is begin LP <= "00"; wait for kT_HS_PREPARE; end procedure; procedure HS_Zero is begin HS <= '0'; wait for kT_HS_ZERO; end procedure; procedure HS_Send0(nbits : in natural) is begin for i in 0 to nbits-1 loop HS <= '0'; wait until SerClkHS'event; end loop; end procedure; procedure HS_Send(byte : in std_logic_vector(7 downto 0)) is begin for i in 0 to 7 loop wait for kUI / 2; --90deg phase difference between data and clock HS <= byte(i); wait until SerClkHS'event; end loop; end procedure; procedure HS_Trail is begin wait for kUI / 2; HS <= not HS; wait for kT_HS_TRAIL; end procedure; variable seed1, seed2: positive; -- seed values for random generator variable rand: real; -- random real-number value in range 0 to 1.0 variable range_of_rand : real := 10.0; -- the range of random values created will be 0 to +1000. variable to_send : natural; begin Stopstate(kTInit + 1 us); for i in 0 to 7 loop HS_Rqst; HS_Prepare; wait for kUI; -- this will test different word alignments HS_Zero; wait until Falling_Edge(SerClkHS); HS_Send(kSyncSeq); uniform(seed1, seed2, rand); -- generate random number for j in 0 to integer(rand*range_of_rand) loop case (j) is when 0 => HS_Send(x"DE"); when 1 => HS_Send(x"AD"); when 2 => HS_Send(x"BE"); when 3 => HS_Send(x"EF"); when others => HS_Send(std_logic_vector(to_unsigned(j-4,8))); end case; end loop; HS_Trail; Stopstate(kT_HS_EXIT); end loop; wait; end process Stimulus; Verification: process (LP, RxByteClkHS) variable cnt_hs : natural := 0; variable cnt_byte : natural := 0; variable bit_last : std_logic := '1'; variable f_err_hold, f_err_temp, f_intrail : boolean := true; impure function check_data(data : std_logic_vector(7 downto 0); i : natural) return boolean is begin if (not f_intrail) then if (data = (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last)) then f_intrail := true; else bit_last := data(7); --least-significant first end if; else if (data /= (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last) & (not bit_last)) then f_intrail := false; bit_last := data(7); --least-significant first end if; end if; case (i) is when 0 => f_err_temp := (data = x"DE"); when 1 => f_err_temp := (data = x"AD"); when 2 => f_err_temp := (data = x"BE"); when 3 => f_err_temp := (data = x"EF"); when others => f_err_temp := (data = std_logic_vector(to_unsigned(i-4, 8))); end case; -- Keep the error in mind for later, we might not be in trail after all if (f_intrail) then f_err_hold := f_err_hold and f_err_temp; return true; else return f_err_hold and f_err_temp; end if; end check_data; variable my_line : line; -- type 'line' comes from textio begin if LP'event and LP = "00" then cnt_hs := cnt_hs + 1; cnt_byte := 0; f_intrail := false; f_err_hold := true; bit_last := '1'; --sync sequence last bit end if; if LP = "00" and Rising_Edge(RxByteClkHS) then if rbRxValidHS = '1' then if not check_data(rbRxDataHS, cnt_byte) then write(my_line, string'("Error at byte ")); write(my_line, cnt_byte); write(my_line, string'(", data: ")); hwrite(my_line, rbRxDataHS); write(my_line, string'(", time: ")); write(my_line, now); writeline(output, my_line); end if; cnt_byte := cnt_byte + 1; end if; end if; end process; end Behavioral;

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:20:04 05/18/2010 -- Design Name: -- Module Name: /home/silva/Documents/Dropbox/IST/4 Ano/2º Semestre/AAC/Projecto/Parte II/Codigo/17.Maio/4/tadam/teste_flags.vhd -- Project Name: tadam -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Flag_Test -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY teste_flags IS END teste_flags; ARCHITECTURE behavior OF teste_flags IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Flag_Test PORT( NEG : IN std_logic; ZERO : IN std_logic; OVERFLOW : IN std_logic; CARRY : IN std_logic; COND : IN std_logic_vector(3 downto 0); OP : IN std_logic_vector(1 downto 0); UNJUMP : IN std_logic; ENABLE : IN std_logic; SEL : IN std_logic; Z : OUT std_logic ); END COMPONENT; --Inputs signal NEG : std_logic := '0'; signal ZERO : std_logic := '0'; signal OVERFLOW : std_logic := '0'; signal CARRY : std_logic := '0'; signal COND : std_logic_vector(3 downto 0) := (others => '0'); signal OP : std_logic_vector(1 downto 0) := (others => '0'); signal UNJUMP : std_logic := '0'; signal ENABLE : std_logic := '0'; signal SEL : std_logic := '0'; --Outputs signal Z : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Flag_Test PORT MAP ( NEG => NEG, ZERO => ZERO, OVERFLOW => OVERFLOW, CARRY => CARRY, COND => COND, OP => OP, UNJUMP => UNJUMP, ENABLE => ENABLE, SEL => SEL, Z => Z ); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name -- Stimulus process stim_proc: process begin -- insert stimulus here -- 04FD NEG <= '0'; ZERO <= '1','0' after 500 ns; COND <= "0101"; OP <= "00"; ENABLE <= '1'; wait; end process; END;

<filename>FPGA/DSPB_Simulink_Model/DSPB_MMSE/rtl/DSPB_MMSE/DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_atb.vhd<gh_stars>0 -- ------------------------------------------------------------------------- -- High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #625) -- Quartus Prime development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2018 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly -- subject to the terms and conditions of the Intel FPGA Software License -- Agreement, Intel MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by Intel -- and sold by Intel or its authorized distributors. Please refer to the -- applicable agreement for further details. -- --------------------------------------------------------------------------- -- VHDL created from DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror -- VHDL created on Mon Aug 16 17:44:01 2021 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use work.dspba_sim_library_package.all; entity DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_atb is end; architecture normal of DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_atb is component DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror is port ( in_1_valid : in std_logic_vector(0 downto 0); -- ufix1 in_2_input_spectrum : in std_logic_vector(31 downto 0); -- float32_m23 out_1_valid_x : out std_logic_vector(0 downto 0); -- ufix1 out_2_output_spectrum : out std_logic_vector(31 downto 0); -- float32_m23 clk : in std_logic; areset : in std_logic ); end component; component DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_stm is port ( in_1_valid_stm : out std_logic_vector(0 downto 0); in_2_input_spectrum_stm : out std_logic_vector(31 downto 0); out_1_valid_x_stm : out std_logic_vector(0 downto 0); out_2_output_spectrum_stm : out std_logic_vector(31 downto 0); clk : out std_logic; areset : out std_logic ); end component; signal in_1_valid_stm : STD_LOGIC_VECTOR (0 downto 0); signal in_2_input_spectrum_stm : STD_LOGIC_VECTOR (31 downto 0); signal out_1_valid_x_stm : STD_LOGIC_VECTOR (0 downto 0); signal out_2_output_spectrum_stm : STD_LOGIC_VECTOR (31 downto 0); signal in_1_valid_dut : STD_LOGIC_VECTOR (0 downto 0); signal in_2_input_spectrum_dut : STD_LOGIC_VECTOR (31 downto 0); signal out_1_valid_x_dut : STD_LOGIC_VECTOR (0 downto 0); signal out_2_output_spectrum_dut : STD_LOGIC_VECTOR (31 downto 0); signal clk : std_logic; signal areset : std_logic; begin -- General Purpose data in real output checkGPIn : process (clk, areset, in_1_valid_dut, in_1_valid_stm, in_2_input_spectrum_dut, in_2_input_spectrum_stm) variable in_2_input_spectrum_real : REAL := 0.0; variable in_2_input_spectrum_stm_real : REAL := 0.0; begin in_2_input_spectrum_real := vIEEE_2_real(in_2_input_spectrum_dut, 8, 23, false); in_2_input_spectrum_stm_real := vIEEE_2_real(in_2_input_spectrum_stm, 8, 23, false); END PROCESS; -- General Purpose data out check checkGPOut : process (clk, areset) variable mismatch_out_1_valid_x : BOOLEAN := FALSE; variable mismatch_out_2_output_spectrum : BOOLEAN := FALSE; variable out_2_output_spectrum_real : REAL := 0.0; variable out_2_output_spectrum_stm_real : REAL := 0.0; variable ok : BOOLEAN := TRUE; begin IF (areset = '1') THEN -- do nothing during reset ELSIF (clk'EVENT AND clk = '0') THEN -- falling clock edge to avoid transitions ok := TRUE; mismatch_out_1_valid_x := FALSE; mismatch_out_2_output_spectrum := FALSE; out_2_output_spectrum_real := vIEEE_2_real(out_2_output_spectrum_dut, 8, 23, false); out_2_output_spectrum_stm_real := vIEEE_2_real(out_2_output_spectrum_stm, 8, 23, false); IF ( (out_1_valid_x_dut /= out_1_valid_x_stm)) THEN mismatch_out_1_valid_x := TRUE; report "Mismatch on device output pin out_1_valid_x" severity Warning; END IF; IF ( not vIEEEisEqual(out_2_output_spectrum_dut, out_2_output_spectrum_stm, 8, 23, 0.000000e+00, 0.000000e+00)) THEN mismatch_out_2_output_spectrum := TRUE; report "Mismatch on device output pin out_2_output_spectrum" severity Warning; END IF; IF (mismatch_out_1_valid_x or mismatch_out_2_output_spectrum) THEN ok := FALSE; END IF; assert (ok) report "mismatch in general purpose signal. Check the status of any associated valid signals." severity Warning; END IF; END PROCESS; dut : DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror port map ( in_1_valid_stm, in_2_input_spectrum_stm, out_1_valid_x_dut, out_2_output_spectrum_dut, clk, areset ); sim : DSPB_MMSE_dut_output_adapter_IFFT_Adapter_Spectrum_Mirror_stm port map ( in_1_valid_stm, in_2_input_spectrum_stm, out_1_valid_x_stm, out_2_output_spectrum_stm, clk, areset ); end normal;

<filename>Labs/05-counter/counter/counter.srcs/sources_1/new/m7_driver.vhd ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/10/2021 03:21:51 PM -- Design Name: -- Module Name: m7_driver - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity m7_driver is Generic ( g_MAX : natural := 100000 -- update each segment every 1ms ); Port ( CLK100MHZ : in std_logic; num_in : in std_logic_vector(32 - 1 downto 0); s_mask : in std_logic_vector(8 - 1 downto 0); reset : in std_logic; t_seg_o : out std_logic_vector(7 - 1 downto 0); AN : out std_logic_vector(8 - 1 downto 0) ); end m7_driver; architecture Behavioral of m7_driver is signal switch_segment : std_logic; signal local_disply_num : std_logic_vector(4-1 downto 0); signal local_cnt : natural; begin -------------------------------------------------------------------- -- segment switching signal clk_en_16b : entity work.clock_enable generic map( g_MAX => g_MAX ) port map( clk => CLK100MHZ, reset => reset, -- no reset needed ce_o => switch_segment ); hex2seg : entity work.hex_7seg port map( hex_i => local_disply_num, seg_o(6) => t_seg_o(6), seg_o(5) => t_seg_o(5), seg_o(4) => t_seg_o(4), seg_o(3) => t_seg_o(3), seg_o(2) => t_seg_o(2), seg_o(1) => t_seg_o(1), seg_o(0) => t_seg_o(0) ); segment_switcher : process(CLK100MHZ) begin if rising_edge(CLK100MHZ) then if (reset = '1') then local_cnt <= 0; elsif (switch_segment = '1') then AN(local_cnt-1) <= '1'; -- reset previous segment if (s_mask(local_cnt) = '1') then -- check mask AN(local_cnt) <= '0'; -- activate current segment end if; -- calculate segment numbers local_disply_num <= num_in((local_cnt*4)+3 downto (local_cnt*4)); -- if last segment go to beginning if (local_cnt < 8) then local_cnt <= local_cnt + 1; else local_cnt <= 0; end if; end if; end if; end process segment_switcher; end Behavioral;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01:29:15 01/07/2018 -- Design Name: -- Module Name: top_fpga - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top_fpga is Port ( sys_clk : in STD_LOGIC; sys_rst_n : in STD_LOGIC; DAC_IN1,DAC_IN2,DAC_IN3 : in STD_LOGIC_VECTOR (35 downto 0); DAC_OUT13,DAC_OUT14,DAC_OUT15 : out STD_LOGIC_VECTOR (35 downto 0)); end top_fpga; architecture Behavioral of top_fpga is signal sys_rst : std_logic; COMPONENT MASH_HDL PORT( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic; In1 : IN std_logic_vector(35 DOWNTO 0); -- sfix36_En22 ce_out : OUT std_logic; Modulator_output : OUT std_logic_vector(35 DOWNTO 0) -- sfix36_En22 ); END COMPONENT; COMPONENT DSM_MOD8_HDL PORT ( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic; In1 : IN std_logic_vector(45 DOWNTO 0); -- sfix36_En32 ce_out : OUT std_logic; Out1 : OUT std_logic_vector(1 DOWNTO 0) -- sfix2 ); END COMPONENT; COMPONENT Eight_order_delta_sigma_modulator PORT ( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic; Baseband_signal : IN std_logic_vector(35 DOWNTO 0); -- sfix36_En32 ce_out : OUT std_logic; Modulator_output : OUT std_logic_vector(35 DOWNTO 0) -- sfix36_En32 ); END COMPONENT; begin sys_rst <= not sys_rst_n; U1 : Eight_order_delta_sigma_modulator PORT MAP( clk => sys_clk, reset => sys_rst, clk_enable => '1', Baseband_signal => DAC_IN1, ce_out => open, Modulator_output => DAC_OUT13 ); -- U2 : DSM_MOD8_LTE_HDL -- PORT MAP( -- clk => sys_clk, -- reset => sys_rst, -- clk_enable => '1', -- In1 => DAC_IN2, -- ce_out => open, -- Out1 => DAC_OUT14 -- ); -- -- U3 : MASH_HDL -- PORT MAP( -- clk => sys_clk, -- reset => sys_rst, -- clk_enable => '1', -- In1 => DAC_IN3, -- ce_out => open, -- Modulator_output => DAC_OUT15 -- ); end Behavioral;

<filename>lib/memory_tech_lib/tests/memory_tb.vhd<gh_stars>10-100 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.test_pkg.all; use work.memory_pack.all; use work.mem_test_pack.all; entity memory_tb is end memory_tb; architecture tb of memory_tb is signal select_mem : mem_type; signal clk : std_logic := '0'; signal rst : std_logic := '1'; constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; signal p0 : mem_port := MEM_PORT_NOP; signal p1 : mem_port := MEM_PORT_NOP; signal dr0 : data_array_t := (others => (others => '0')); signal dr1 : data_array_t := (others => (others => '0')); procedure tick(signal clk : inout std_logic) is begin wait for 10 ns; clk <= '1'; wait for 10 ns; clk <= '0'; end procedure; function to_bit(b : boolean) return std_logic is begin if b then return '1'; else return '0'; end if; end function; for mems : memories use configuration work.memories_inferred; begin mems: memories generic map ( FOR_SYNTHESIS => false) port map ( rst0 => rst, clk0 => clk, rst1 => rst, clk1 => clk, select_mem => select_mem, p0 => p0, p1 => p1, dr0 => dr0, dr1 => dr1); process begin test_plan(75, "memory_tb"); -- Memories do synchronous reads and writes at the rising clock edge. Setup -- read/write requests at the negative edge and check the results at the -- following negative edge. tick(clk); rst <= '0'; tick(clk); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; -- TODO: How to test ROM? Need to support initializnig it first test_comment("RAM_GEN_32x2048_1R"); select_mem <= ROM_GEN_32x2048_1R; tick(clk); --for m in one_port_rams'left to one_port_rams'right loop --select_mem <= one_port_rams(m); --end loop; test_comment("RAM_GEN_2x8x256_1RW"); select_mem <= RAM_GEN_2x8x256_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(3, x"0000FFFF", "01"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 1 byte write"); p0 <= writemem(3, x"00000000", "00"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 0 byte write"); p0 <= writemem(3, x"00000000", "10"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"000000FF", "read after 1 byte write"); p0 <= writemem(3, x"0000abcd", "11"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read after 2 byte write"); p0 <= MEM_PORT_NOP; test_comment("RAM_FIXED_2x8x256_1RW"); select_mem <= RAM_FIXED_2x8x256_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(3, x"0000FFFF", "01"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 1 byte write"); p0 <= writemem(3, x"00000000", "00"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abFF", "read after 0 byte write"); p0 <= writemem(3, x"00000000", "10"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"000000FF", "read after 1 byte write"); p0 <= writemem(3, x"0000abcd", "11"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read after 2 byte write"); p0 <= MEM_PORT_NOP; test_comment("RAM_GEN_18x2048_1RW"); select_mem <= RAM_GEN_18x2048_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0003FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= MEM_PORT_NOP; test_comment("RAM_FIXED_18x2048_1RW"); select_mem <= RAM_FIXED_18x2048_1RW; p0 <= writemem(3, x"0000abcd"); tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read back write to 3"); p0 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0003FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= MEM_PORT_NOP; test_comment("RAM_GEN_2x8x2048_2RW"); select_mem <= RAM_GEN_2x8x2048_2RW; p0 <= writemem(3, x"0000abcd"); p1 <= MEM_PORT_NOP; tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "p0 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= readmem(3); tick(clk); test_equal(dr1(select_mem), x"0000abcd", "p1 read back write to 3"); p0 <= readmem(3); p1 <= readmem(3); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "p0 & p1 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(5, x"00001256"); p1 <= writemem(6, x"00007834"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after simultaneous writes"); p0 <= writemem(5, x"0000FFFF", x"00000000"); p1 <= writemem(6, x"00000000", x"00000000"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after writes with we=0"); p0 <= writemem(5, x"0000FFFF", x"00000001"); p1 <= writemem(6, x"00000000", x"00000002"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "reads latched during partial writes"); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"00000034000012FF", "read after writes with we=10 and we=01"); test_comment("RAM_FIXED_2x8x2048_2RW"); select_mem <= RAM_FIXED_2x8x2048_2RW; p0 <= writemem(3, x"0000abcd"); p1 <= MEM_PORT_NOP; tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "p0 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= readmem(3); tick(clk); test_equal(dr1(select_mem), x"0000abcd", "p1 read back write to 3"); p0 <= readmem(3); p1 <= readmem(3); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "p0 & p1 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000abcd0000abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"0000FFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"0000abcd", "rereread back write to 3"); p0 <= writemem(5, x"00001256"); p1 <= writemem(6, x"00007834"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after simultaneous writes"); p0 <= writemem(5, x"0000FFFF", x"00000000"); p1 <= writemem(6, x"00000000", x"00000000"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "read after writes with we=0"); p0 <= writemem(5, x"0000FFFF", x"00000001"); p1 <= writemem(6, x"00000000", x"00000002"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"0000783400001256", "reads latched during partial writes"); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"00000034000012FF", "read after writes with we=10 and we=01"); test_comment("RAM_GEN_32x1x512_2RW"); select_mem <= RAM_GEN_32x1x512_2RW; p0 <= writemem(3, x"1234abcd"); p1 <= MEM_PORT_NOP; tick(clk); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"1234abcd", "p0 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= readmem(3); tick(clk); test_equal(dr1(select_mem), x"1234abcd", "p1 read back write to 3"); p0 <= readmem(3); p1 <= readmem(3); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "p0 & p1 read back write to 3"); p0 <= MEM_PORT_NOP; p1 <= MEM_PORT_NOP; tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "read data latched"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "read data still latched"); p0 <= writemem(2047, x"FFFFFFFF"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"1234abcd1234abcd", "read data latched during write"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"1234abcd", "reread back write to 3"); p0 <= readmem(2047); tick(clk); test_equal(dr0(select_mem), x"FFFFFFFF", "read write end of mem"); p0 <= readmem(3); tick(clk); test_equal(dr0(select_mem), x"1234abcd", "rereread back write to 3"); p0 <= writemem(5, x"12345678"); p1 <= writemem(6, x"abcdefcb"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"abcdefcb12345678", "read after simultaneous writes"); p0 <= writemem(5, x"0000FFFF", x"00000000"); p1 <= writemem(6, x"00000000", x"00000000"); tick(clk); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"abcdefcb12345678", "read after writes with we=0"); p0 <= writemem(5, x"FFFF0000", x"11111111"); p1 <= writemem(6, x"00000000", x"12345678"); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"abcdefcb12345678", "reads latched during partial writes"); p0 <= readmem(6); p1 <= readmem(5); tick(clk); test_equal(dr0(select_mem) & dr1(select_mem), x"a9c9a98313354668", "read after writes with mixed we"); wait; end process; end architecture;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.lib.all; -- Entity entity system is port ( clk : in std_logic; -- Declare Outputs environment_time_out : out signed(31 downto 0); membrane_v_out : out signed(31 downto 0); membrane_r_out : out signed(31 downto 0); membrane_t_out : out signed(31 downto 0); membrane_f_out : out signed(31 downto 0); membrane_dv_dt_out : out signed(31 downto 0); membrane_istimc_out : out signed(31 downto 0); fast_sodium_current_i_na_out : out signed(31 downto 0); fast_sodium_current_e_na_out : out signed(31 downto 0); fast_sodium_current_time_private_out : out signed(31 downto 0); fast_sodium_current_v_private_out : out signed(31 downto 0); fast_sodium_current_m_gate_m_out : out signed(31 downto 0); fast_sodium_current_h_gate_h_out : out signed(31 downto 0); fast_sodium_current_j_gate_j_out : out signed(31 downto 0); l_type_ca_channel_i_ca_l_out : out signed(31 downto 0); l_type_ca_channel_i_caca_out : out signed(31 downto 0); l_type_ca_channel_i_cak_out : out signed(31 downto 0); l_type_ca_channel_i_cana_out : out signed(31 downto 0); l_type_ca_channel_gamma_nai_out : out signed(31 downto 0); l_type_ca_channel_gamma_nao_out : out signed(31 downto 0); l_type_ca_channel_gamma_ki_out : out signed(31 downto 0); l_type_ca_channel_gamma_ko_out : out signed(31 downto 0); l_type_ca_channel_time_private_out : out signed(31 downto 0); l_type_ca_channel_v_private_out : out signed(31 downto 0); l_type_ca_channel_cai_private_out : out signed(31 downto 0); l_type_ca_channel_d_gate_d_out : out signed(31 downto 0); l_type_ca_channel_f_gate_f_out : out signed(31 downto 0); l_type_ca_channel_f_ca_gate_f_ca_out : out signed(31 downto 0); time_dependent_potassium_current_i_k_out : out signed(31 downto 0); time_dependent_potassium_current_time_private_out : out signed(31 downto 0); time_dependent_potassium_current_v_private_out : out signed(31 downto 0); time_dependent_potassium_current_x_gate_x_out : out signed(31 downto 0); time_dependent_potassium_current_xi_gate_xi_out : out signed(31 downto 0); time_independent_potassium_current_i_k1_out : out signed(31 downto 0); time_independent_potassium_current_e_k1_out : out signed(31 downto 0); time_independent_potassium_current_time_private_out : out signed(31 downto 0); time_independent_potassium_current_v_private_out : out signed(31 downto 0); time_independent_potassium_current_k1_gate_k1_infinity_out : out signed(31 downto 0); plateau_potassium_current_i_kp_out : out signed(31 downto 0); sarcolemmal_calcium_pump_i_p_ca_out : out signed(31 downto 0); sodium_background_current_i_na_b_out : out signed(31 downto 0); calcium_background_current_i_ca_b_out : out signed(31 downto 0); sodium_potassium_pump_i_nak_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_ca_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_na_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_k_out : out signed(31 downto 0); na_ca_exchanger_i_naca_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_rel_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_up_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_leak_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_tr_out : out signed(31 downto 0); ionic_concentrations_nai_out : out signed(31 downto 0); ionic_concentrations_nao_out : out signed(31 downto 0); ionic_concentrations_cai_out : out signed(31 downto 0); ionic_concentrations_cao_out : out signed(31 downto 0); ionic_concentrations_ki_out : out signed(31 downto 0); ionic_concentrations_ko_out : out signed(31 downto 0); ionic_concentrations_ca_jsr_out : out signed(31 downto 0); ionic_concentrations_ca_nsr_out : out signed(31 downto 0) ); end; -- Architecture architecture behavior of system is -- Declare all internal signals signal luo_rudy_1994_environment_time : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_v : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_r : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_t : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_f : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_dv_dt : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_membrane_istimc : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_i_na : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_e_na : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_m_gate_m : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_h_gate_h : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_fast_sodium_current_j_gate_j : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_ca_l : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_caca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_cak : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_i_cana : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_nai : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_nao : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_ki : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_gamma_ko : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_cai_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_d_gate_d : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_f_gate_f : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_l_type_ca_channel_f_ca_gate_f_ca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_i_k : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_x_gate_x : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_dependent_potassium_current_xi_gate_xi : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_i_k1 : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_e_k1 : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_time_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_v_private : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_time_independent_potassium_current_k1_gate_k1_infinity : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_plateau_potassium_current_i_kp : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_sarcolemmal_calcium_pump_i_p_ca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_sodium_background_current_i_na_b : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_background_current_i_ca_b : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_sodium_potassium_pump_i_nak : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_non_specific_calcium_activated_current_i_ns_ca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_non_specific_calcium_activated_current_i_ns_na : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_non_specific_calcium_activated_current_i_ns_k : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_na_ca_exchanger_i_naca : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_rel : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_up : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_leak : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_calcium_fluxes_in_the_sr_i_tr : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_nai : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_nao : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_cai : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_cao : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ki : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ko : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ca_jsr : signed(31 downto 0) := CREATE_FP(0.0); signal luo_rudy_1994_ionic_concentrations_ca_nsr : signed(31 downto 0) := CREATE_FP(0.0); -- Declare base component component LuoRudy1994 is port( clk : in std_logic; environment_time_out : out signed(31 downto 0); membrane_v_out : out signed(31 downto 0); membrane_r_out : out signed(31 downto 0); membrane_t_out : out signed(31 downto 0); membrane_f_out : out signed(31 downto 0); membrane_dv_dt_out : out signed(31 downto 0); membrane_istimc_out : out signed(31 downto 0); fast_sodium_current_i_na_out : out signed(31 downto 0); fast_sodium_current_e_na_out : out signed(31 downto 0); fast_sodium_current_time_private_out : out signed(31 downto 0); fast_sodium_current_v_private_out : out signed(31 downto 0); fast_sodium_current_m_gate_m_out : out signed(31 downto 0); fast_sodium_current_h_gate_h_out : out signed(31 downto 0); fast_sodium_current_j_gate_j_out : out signed(31 downto 0); l_type_ca_channel_i_ca_l_out : out signed(31 downto 0); l_type_ca_channel_i_caca_out : out signed(31 downto 0); l_type_ca_channel_i_cak_out : out signed(31 downto 0); l_type_ca_channel_i_cana_out : out signed(31 downto 0); l_type_ca_channel_gamma_nai_out : out signed(31 downto 0); l_type_ca_channel_gamma_nao_out : out signed(31 downto 0); l_type_ca_channel_gamma_ki_out : out signed(31 downto 0); l_type_ca_channel_gamma_ko_out : out signed(31 downto 0); l_type_ca_channel_time_private_out : out signed(31 downto 0); l_type_ca_channel_v_private_out : out signed(31 downto 0); l_type_ca_channel_cai_private_out : out signed(31 downto 0); l_type_ca_channel_d_gate_d_out : out signed(31 downto 0); l_type_ca_channel_f_gate_f_out : out signed(31 downto 0); l_type_ca_channel_f_ca_gate_f_ca_out : out signed(31 downto 0); time_dependent_potassium_current_i_k_out : out signed(31 downto 0); time_dependent_potassium_current_time_private_out : out signed(31 downto 0); time_dependent_potassium_current_v_private_out : out signed(31 downto 0); time_dependent_potassium_current_x_gate_x_out : out signed(31 downto 0); time_dependent_potassium_current_xi_gate_xi_out : out signed(31 downto 0); time_independent_potassium_current_i_k1_out : out signed(31 downto 0); time_independent_potassium_current_e_k1_out : out signed(31 downto 0); time_independent_potassium_current_time_private_out : out signed(31 downto 0); time_independent_potassium_current_v_private_out : out signed(31 downto 0); time_independent_potassium_current_k1_gate_k1_infinity_out : out signed(31 downto 0); plateau_potassium_current_i_kp_out : out signed(31 downto 0); sarcolemmal_calcium_pump_i_p_ca_out : out signed(31 downto 0); sodium_background_current_i_na_b_out : out signed(31 downto 0); calcium_background_current_i_ca_b_out : out signed(31 downto 0); sodium_potassium_pump_i_nak_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_ca_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_na_out : out signed(31 downto 0); non_specific_calcium_activated_current_i_ns_k_out : out signed(31 downto 0); na_ca_exchanger_i_naca_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_rel_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_up_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_leak_out : out signed(31 downto 0); calcium_fluxes_in_the_sr_i_tr_out : out signed(31 downto 0); ionic_concentrations_nai_out : out signed(31 downto 0); ionic_concentrations_nao_out : out signed(31 downto 0); ionic_concentrations_cai_out : out signed(31 downto 0); ionic_concentrations_cao_out : out signed(31 downto 0); ionic_concentrations_ki_out : out signed(31 downto 0); ionic_concentrations_ko_out : out signed(31 downto 0); ionic_concentrations_ca_jsr_out : out signed(31 downto 0); ionic_concentrations_ca_nsr_out : out signed(31 downto 0) ); end component LuoRudy1994; begin -- Create base instance luo_rudy_1994_inst : component LuoRudy1994 port map( clk => clk, environment_time_out => luo_rudy_1994_environment_time, membrane_v_out => luo_rudy_1994_membrane_v, membrane_r_out => luo_rudy_1994_membrane_r, membrane_t_out => luo_rudy_1994_membrane_t, membrane_f_out => luo_rudy_1994_membrane_f, membrane_dv_dt_out => luo_rudy_1994_membrane_dv_dt, membrane_istimc_out => luo_rudy_1994_membrane_istimc, fast_sodium_current_i_na_out => luo_rudy_1994_fast_sodium_current_i_na, fast_sodium_current_e_na_out => luo_rudy_1994_fast_sodium_current_e_na, fast_sodium_current_time_private_out => luo_rudy_1994_fast_sodium_current_time_private, fast_sodium_current_v_private_out => luo_rudy_1994_fast_sodium_current_v_private, fast_sodium_current_m_gate_m_out => luo_rudy_1994_fast_sodium_current_m_gate_m, fast_sodium_current_h_gate_h_out => luo_rudy_1994_fast_sodium_current_h_gate_h, fast_sodium_current_j_gate_j_out => luo_rudy_1994_fast_sodium_current_j_gate_j, l_type_ca_channel_i_ca_l_out => luo_rudy_1994_l_type_ca_channel_i_ca_l, l_type_ca_channel_i_caca_out => luo_rudy_1994_l_type_ca_channel_i_caca, l_type_ca_channel_i_cak_out => luo_rudy_1994_l_type_ca_channel_i_cak, l_type_ca_channel_i_cana_out => luo_rudy_1994_l_type_ca_channel_i_cana, l_type_ca_channel_gamma_nai_out => luo_rudy_1994_l_type_ca_channel_gamma_nai, l_type_ca_channel_gamma_nao_out => luo_rudy_1994_l_type_ca_channel_gamma_nao, l_type_ca_channel_gamma_ki_out => luo_rudy_1994_l_type_ca_channel_gamma_ki, l_type_ca_channel_gamma_ko_out => luo_rudy_1994_l_type_ca_channel_gamma_ko, l_type_ca_channel_time_private_out => luo_rudy_1994_l_type_ca_channel_time_private, l_type_ca_channel_v_private_out => luo_rudy_1994_l_type_ca_channel_v_private, l_type_ca_channel_cai_private_out => luo_rudy_1994_l_type_ca_channel_cai_private, l_type_ca_channel_d_gate_d_out => luo_rudy_1994_l_type_ca_channel_d_gate_d, l_type_ca_channel_f_gate_f_out => luo_rudy_1994_l_type_ca_channel_f_gate_f, l_type_ca_channel_f_ca_gate_f_ca_out => luo_rudy_1994_l_type_ca_channel_f_ca_gate_f_ca, time_dependent_potassium_current_i_k_out => luo_rudy_1994_time_dependent_potassium_current_i_k, time_dependent_potassium_current_time_private_out => luo_rudy_1994_time_dependent_potassium_current_time_private, time_dependent_potassium_current_v_private_out => luo_rudy_1994_time_dependent_potassium_current_v_private, time_dependent_potassium_current_x_gate_x_out => luo_rudy_1994_time_dependent_potassium_current_x_gate_x, time_dependent_potassium_current_xi_gate_xi_out => luo_rudy_1994_time_dependent_potassium_current_xi_gate_xi, time_independent_potassium_current_i_k1_out => luo_rudy_1994_time_independent_potassium_current_i_k1, time_independent_potassium_current_e_k1_out => luo_rudy_1994_time_independent_potassium_current_e_k1, time_independent_potassium_current_time_private_out => luo_rudy_1994_time_independent_potassium_current_time_private, time_independent_potassium_current_v_private_out => luo_rudy_1994_time_independent_potassium_current_v_private, time_independent_potassium_current_k1_gate_k1_infinity_out => luo_rudy_1994_time_independent_potassium_current_k1_gate_k1_infinity, plateau_potassium_current_i_kp_out => luo_rudy_1994_plateau_potassium_current_i_kp, sarcolemmal_calcium_pump_i_p_ca_out => luo_rudy_1994_sarcolemmal_calcium_pump_i_p_ca, sodium_background_current_i_na_b_out => luo_rudy_1994_sodium_background_current_i_na_b, calcium_background_current_i_ca_b_out => luo_rudy_1994_calcium_background_current_i_ca_b, sodium_potassium_pump_i_nak_out => luo_rudy_1994_sodium_potassium_pump_i_nak, non_specific_calcium_activated_current_i_ns_ca_out => luo_rudy_1994_non_specific_calcium_activated_current_i_ns_ca, non_specific_calcium_activated_current_i_ns_na_out => luo_rudy_1994_non_specific_calcium_activated_current_i_ns_na, non_specific_calcium_activated_current_i_ns_k_out => luo_rudy_1994_non_specific_calcium_activated_current_i_ns_k, na_ca_exchanger_i_naca_out => luo_rudy_1994_na_ca_exchanger_i_naca, calcium_fluxes_in_the_sr_i_rel_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_rel, calcium_fluxes_in_the_sr_i_up_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_up, calcium_fluxes_in_the_sr_i_leak_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_leak, calcium_fluxes_in_the_sr_i_tr_out => luo_rudy_1994_calcium_fluxes_in_the_sr_i_tr, ionic_concentrations_nai_out => luo_rudy_1994_ionic_concentrations_nai, ionic_concentrations_nao_out => luo_rudy_1994_ionic_concentrations_nao, ionic_concentrations_cai_out => luo_rudy_1994_ionic_concentrations_cai, ionic_concentrations_cao_out => luo_rudy_1994_ionic_concentrations_cao, ionic_concentrations_ki_out => luo_rudy_1994_ionic_concentrations_ki, ionic_concentrations_ko_out => luo_rudy_1994_ionic_concentrations_ko, ionic_concentrations_ca_jsr_out => luo_rudy_1994_ionic_concentrations_ca_jsr, ionic_concentrations_ca_nsr_out => luo_rudy_1994_ionic_concentrations_ca_nsr ); -- Perform Mapping environment_time_out <= luo_rudy_1994_environment_time; membrane_v_out <= luo_rudy_1994_membrane_v; membrane_r_out <= luo_rudy_1994_membrane_r; membrane_t_out <= luo_rudy_1994_membrane_t; membrane_f_out <= luo_rudy_1994_membrane_f; membrane_dv_dt_out <= luo_rudy_1994_membrane_dv_dt; membrane_istimc_out <= luo_rudy_1994_membrane_istimc; fast_sodium_current_i_na_out <= luo_rudy_1994_fast_sodium_current_i_na; fast_sodium_current_e_na_out <= luo_rudy_1994_fast_sodium_current_e_na; fast_sodium_current_time_private_out <= luo_rudy_1994_fast_sodium_current_time_private; fast_sodium_current_v_private_out <= luo_rudy_1994_fast_sodium_current_v_private; fast_sodium_current_m_gate_m_out <= luo_rudy_1994_fast_sodium_current_m_gate_m; fast_sodium_current_h_gate_h_out <= luo_rudy_1994_fast_sodium_current_h_gate_h; fast_sodium_current_j_gate_j_out <= luo_rudy_1994_fast_sodium_current_j_gate_j; l_type_ca_channel_i_ca_l_out <= luo_rudy_1994_l_type_ca_channel_i_ca_l; l_type_ca_channel_i_caca_out <= luo_rudy_1994_l_type_ca_channel_i_caca; l_type_ca_channel_i_cak_out <= luo_rudy_1994_l_type_ca_channel_i_cak; l_type_ca_channel_i_cana_out <= luo_rudy_1994_l_type_ca_channel_i_cana; l_type_ca_channel_gamma_nai_out <= luo_rudy_1994_l_type_ca_channel_gamma_nai; l_type_ca_channel_gamma_nao_out <= luo_rudy_1994_l_type_ca_channel_gamma_nao; l_type_ca_channel_gamma_ki_out <= luo_rudy_1994_l_type_ca_channel_gamma_ki; l_type_ca_channel_gamma_ko_out <= luo_rudy_1994_l_type_ca_channel_gamma_ko; l_type_ca_channel_time_private_out <= luo_rudy_1994_l_type_ca_channel_time_private; l_type_ca_channel_v_private_out <= luo_rudy_1994_l_type_ca_channel_v_private; l_type_ca_channel_cai_private_out <= luo_rudy_1994_l_type_ca_channel_cai_private; l_type_ca_channel_d_gate_d_out <= luo_rudy_1994_l_type_ca_channel_d_gate_d; l_type_ca_channel_f_gate_f_out <= luo_rudy_1994_l_type_ca_channel_f_gate_f; l_type_ca_channel_f_ca_gate_f_ca_out <= luo_rudy_1994_l_type_ca_channel_f_ca_gate_f_ca; time_dependent_potassium_current_i_k_out <= luo_rudy_1994_time_dependent_potassium_current_i_k; time_dependent_potassium_current_time_private_out <= luo_rudy_1994_time_dependent_potassium_current_time_private; time_dependent_potassium_current_v_private_out <= luo_rudy_1994_time_dependent_potassium_current_v_private; time_dependent_potassium_current_x_gate_x_out <= luo_rudy_1994_time_dependent_potassium_current_x_gate_x; time_dependent_potassium_current_xi_gate_xi_out <= luo_rudy_1994_time_dependent_potassium_current_xi_gate_xi; time_independent_potassium_current_i_k1_out <= luo_rudy_1994_time_independent_potassium_current_i_k1; time_independent_potassium_current_e_k1_out <= luo_rudy_1994_time_independent_potassium_current_e_k1; time_independent_potassium_current_time_private_out <= luo_rudy_1994_time_independent_potassium_current_time_private; time_independent_potassium_current_v_private_out <= luo_rudy_1994_time_independent_potassium_current_v_private; time_independent_potassium_current_k1_gate_k1_infinity_out <= luo_rudy_1994_time_independent_potassium_current_k1_gate_k1_infinity; plateau_potassium_current_i_kp_out <= luo_rudy_1994_plateau_potassium_current_i_kp; sarcolemmal_calcium_pump_i_p_ca_out <= luo_rudy_1994_sarcolemmal_calcium_pump_i_p_ca; sodium_background_current_i_na_b_out <= luo_rudy_1994_sodium_background_current_i_na_b; calcium_background_current_i_ca_b_out <= luo_rudy_1994_calcium_background_current_i_ca_b; sodium_potassium_pump_i_nak_out <= luo_rudy_1994_sodium_potassium_pump_i_nak; non_specific_calcium_activated_current_i_ns_ca_out <= luo_rudy_1994_non_specific_calcium_activated_current_i_ns_ca; non_specific_calcium_activated_current_i_ns_na_out <= luo_rudy_1994_non_specific_calcium_activated_current_i_ns_na; non_specific_calcium_activated_current_i_ns_k_out <= luo_rudy_1994_non_specific_calcium_activated_current_i_ns_k; na_ca_exchanger_i_naca_out <= luo_rudy_1994_na_ca_exchanger_i_naca; calcium_fluxes_in_the_sr_i_rel_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_rel; calcium_fluxes_in_the_sr_i_up_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_up; calcium_fluxes_in_the_sr_i_leak_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_leak; calcium_fluxes_in_the_sr_i_tr_out <= luo_rudy_1994_calcium_fluxes_in_the_sr_i_tr; ionic_concentrations_nai_out <= luo_rudy_1994_ionic_concentrations_nai; ionic_concentrations_nao_out <= luo_rudy_1994_ionic_concentrations_nao; ionic_concentrations_cai_out <= luo_rudy_1994_ionic_concentrations_cai; ionic_concentrations_cao_out <= luo_rudy_1994_ionic_concentrations_cao; ionic_concentrations_ki_out <= luo_rudy_1994_ionic_concentrations_ki; ionic_concentrations_ko_out <= luo_rudy_1994_ionic_concentrations_ko; ionic_concentrations_ca_jsr_out <= luo_rudy_1994_ionic_concentrations_ca_jsr; ionic_concentrations_ca_nsr_out <= luo_rudy_1994_ionic_concentrations_ca_nsr; end architecture;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library common; use common.all; library altera_mf; use altera_mf.all; -- writes take two cycles -- read data appears after 4 ticks -- 1 to process the start request -- 1 to get it from the SRAM -- 2 in the syncronizer entity sram is port (i_clk: in std_ulogic; -- max clk 100MHz i_reset: in std_ulogic; -- inputs i_addr: in unsigned(17 downto 0); i_wdata: in std_ulogic_vector(15 downto 0); i_rnw: in std_ulogic; i_start: in std_ulogic; -- outputs o_rdata: out std_ulogic_vector(15 downto 0); -- status o_busy: out std_ulogic; o_rdata_valid: out std_ulogic; -- bus ports io_data: inout std_ulogic_vector(15 downto 0); o_addr: out std_ulogic_vector(17 downto 0); o_nCE: out std_ulogic; o_nOE: out std_ulogic; o_nWE: out std_ulogic; o_nLB: out std_ulogic; o_nUB: out std_ulogic); end entity sram; architecture synth of sram is component delay is generic (DELAY: natural; WIDTH: natural); port (clk: in std_ulogic; rst: in std_ulogic; input: in std_ulogic_vector((WIDTH - 1) downto 0); output: out std_ulogic_vector((WIDTH - 1) downto 0)); end component delay; component altera_std_synchronizer_bundle is generic (DEPTH : integer := 3; -- must be >= 2 WIDTH : integer := 1); port (clk : in std_logic; reset_n : in std_logic; din : in std_logic_vector(width-1 downto 0); dout : out std_logic_vector(width-1 downto 0)); end component altera_std_synchronizer_bundle; signal busy: std_ulogic; begin -- syncronize the input data rdata_sync: altera_std_synchronizer_bundle generic map (DEPTH => 2, WIDTH => 16) port map (clk => i_clk, reset_n => not i_reset, din => std_logic_vector(io_data), std_ulogic_vector(dout) => o_rdata); process (i_clk, i_reset) begin if (i_reset = '1') then o_nCE <= '1'; o_nOE <= '1'; o_nWE <= '1'; o_nLB <= '1'; o_nUB <= '1'; io_data <= (others => 'Z'); busy <= '0'; elsif (rising_edge(i_clk)) then if (busy = '0') then -- not doing anything -- wait for read or write request if (i_start) then -- we have a request o_addr <= std_ulogic_vector(i_addr); if (i_rnw = '1') then -- read io_data <= (others => 'Z'); o_nOE <= '0'; o_nWE <= '1'; else -- write io_data <= i_wdata; o_nOE <= '1'; o_nWE <= '0'; -- we take more than one cycle for writes -- so have to say we're busy busy <= '1'; end if; o_nCE <= '0'; o_nUB <= '0'; o_nLB <= '0'; else -- not busy and not starting anything new -- so disable everything o_nCE <= '1'; o_nOE <= '1'; o_nWE <= '1'; o_nLB <= '1'; o_nUB <= '1'; io_data <= (others => 'Z'); end if; else -- busy -> writing -- finish off the write by releasing everything o_nCE <= '1'; o_nOE <= '1'; o_nWE <= '1'; o_nLB <= '1'; o_nUB <= '1'; io_data <= (others => 'Z'); busy <= '0'; end if; end if; end process; o_busy <= busy; -- when both i_start and i_rnw are asserted -- then the read data becomes available 4 ticks later dly: delay generic map (DELAY => 4, WIDTH => 1) port map (clk => i_clk, rst => i_reset, input(0) => i_start and i_rnw, output(0) => o_rdata_valid); end architecture synth;

<reponame>amnesia13/prince-vhdl library ieee; use ieee.std_logic_1164.all; -- The cipher without the key whitening layer entity prince_core is port(data_in: in std_logic_vector(63 downto 0); key: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end prince_core; architecture structural of prince_core is type round_constants is array(0 to 11) of std_logic_vector(63 downto 0); type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0); -- Round constants for each round constant rcs: round_constants := (x"0000000000000000", x"13198A2E03707344", x"A4093822299F31D0", x"082EFA98EC4E6C89", x"452821E638D01377", x"BE5466CF34E90C6C", x"7EF84F78FD955CB1", x"85840851F1AC43AA", x"C882D32F25323C54", x"64A51195E0E3610D", x"D3B5A399CA0C2399", x"C0AC29B7C97C50DD"); -- Signals for transporting the data between rounds signal ims: intermediate_signals; signal middle1, middle2: std_logic_vector(63 downto 0); -- Required component declarations component sbox port(data_in: in std_logic_vector(3 downto 0); data_out: out std_logic_vector(3 downto 0) ); end component; component sbox_inv port(data_in: in std_logic_vector(3 downto 0); data_out: out std_logic_vector(3 downto 0) ); end component; component linear_m port(data_in: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end component; component linear_m_inv port(data_in: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end component; component linear_mprime port(data_in: in std_logic_vector(63 downto 0); data_out: out std_logic_vector(63 downto 0) ); end component; begin -- Round 0 ims(0) <= data_in xor key xor rcs(0); -- Round 1 to 5 FIRST_HALF: for i in 1 to 5 generate signal sb_out, m_out: std_logic_vector(63 downto 0); begin SB_FH: for j in 0 to 15 generate SX_FH: sbox port map( data_in => ims(i - 1)(63 - 4*j downto 63 - 4*j - 3), data_out => sb_out(63 - 4*j downto 63 - 4*j - 3) ); end generate; LIN_M: linear_m port map( data_in => sb_out, data_out => m_out ); ims(i) <= m_out xor rcs(i) xor key; end generate; -- Middle layer SB_MID: for i in 0 to 15 generate SX_M1: sbox port map( data_in => ims(5)(63 - 4*i downto 63 - 4*i - 3), data_out => middle1(63 - 4*i downto 63 - 4*i - 3) ); end generate; MP_MID: linear_mprime port map( data_in => middle1, data_out => middle2 ); SB_MID_INV: for i in 0 to 15 generate SX_M2: sbox_inv port map( data_in => middle2(63 - 4*i downto 63 - 4*i - 3), data_out => ims(6)(63 - 4*i downto 63 - 4*i - 3) ); end generate; -- Round 6 to 10 SECOND_HALF: for i in 6 to 10 generate signal m_in, sb_in: std_logic_vector(63 downto 0); begin m_in <= ims(i) xor key xor rcs(i); LIN_M_INV: linear_m_inv port map( data_in => m_in, data_out => sb_in ); SB_SH: for j in 0 to 15 generate SX_SH: sbox_inv port map( data_in => sb_in(63 - 4*j downto 63 - 4*j - 3), data_out => ims(i + 1)(63 - 4*j downto 63 - 4*j - 3) ); end generate; end generate; -- Round 11 data_out <= ims(11) xor rcs(11) xor key; end architecture;

------------------------------------------------------------------------------- -- Title : Accelerator Adapter -- Project : ------------------------------------------------------------------------------- -- File : xd_sync_module.vhd -- Author : rmg/jn -- Company : Xilinx, Inc. -- Created : 2012-09-05 -- Last update: 2013-01-22 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- (c) Copyright 2012 Xilinx, Inc. All rights reserved. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2012-09-05 1.0 rmg/jn Created -- 2013-07-12 2.0 pankajk Added new ports iscalar_rqt_enable & -- iscalar_rqt_enable to qualify with -- iscalar_start & oscalar_start ------------------------------------------------------------------------------- -- **************************************************************************** -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- **************************************************************************** ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library axis_accelerator_adapter_v2_1_6; use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all; use axis_accelerator_adapter_v2_1_6.async_fifo_dist_wt; use axis_accelerator_adapter_v2_1_6.sync_ap_status; use axis_accelerator_adapter_v2_1_6.cdc_sync; entity xd_sync_module is generic ( -- System generics: C_FAMILY : string; -- Xilinx FPGA family C_MAX_N_IARGS : integer; C_MAX_N_OARGS : integer; C_N_INPUT_ARGS : integer; C_N_OUTPUT_ARGS : integer; C_PRMRY_IS_ACLK_ASYNC : integer; C_MTBF_STAGES : integer; C_MAX_N_ISCALARS : integer; C_N_INPUT_SCALARS : integer; C_MAX_N_OSCALARS : integer; C_N_INOUT_SCALARS : integer; C_MAX_N_IOSCALARS : integer; C_N_OUTPUT_SCALARS : integer; C_NONE : integer := 2); port ( -- SLAVE AXI LITE: S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; -- Host command input port host_cmd_data : in std_logic_vector(31 downto 0); host_cmd_we : in std_logic; host_cmd_rdy : out std_logic; host_complete_re : in std_logic; host_cmd_error : out std_logic; --- iarg_rqt_enable : in std_logic_vector(C_MAX_N_IARGS-1 downto 0); oarg_rqt_enable : in std_logic_vector(C_MAX_N_OARGS-1 downto 0); --- status_ap_start : out std_logic; status_ap_done : out std_logic; status_ap_idle : out std_logic; status_ap_ready : out std_logic; status_ap_start_clr : in std_logic; status_ap_done_clr : in std_logic; status_ap_idle_clr : in std_logic; status_ap_ready_clr : in std_logic; --- status_iarg_rqt : out std_logic_vector(C_MAX_N_IARGS-1 downto 0); status_iarg_ack : out std_logic_vector(C_MAX_N_IARGS-1 downto 0); status_oarg_rqt : out std_logic_vector(C_MAX_N_OARGS-1 downto 0); status_oarg_ack : out std_logic_vector(C_MAX_N_OARGS-1 downto 0); --- ap_clk : in std_logic; soft_rst : in std_logic; ap_rst : in std_logic; --- Control and status signals for multibuffers mb_iarg_rdy : in std_logic_vector(C_MAX_N_IARGS-1 downto 0); mb_iarg_done : out std_logic_vector(C_MAX_N_IARGS-1 downto 0); mb_oarg_rdy : in std_logic_vector(C_MAX_N_OARGS-1 downto 0); mb_oarg_done : out std_logic_vector(C_MAX_N_OARGS-1 downto 0); -- AP control handshaking ap_start : out std_logic; ap_ready : in std_logic; ap_done : in std_logic; ap_continue : out std_logic; ap_idle : in std_logic; ap_start_one_shot : out std_logic; --- iscalar_rqt_enable : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); oscalar_rqt_enable : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0); --- ap_iscalar_rdy : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); ap_iscalar_done : out std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); --- ap_oscalar_vld : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0); ap_oscalar_rdy : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0)); end entity; architecture rtl of xd_sync_module is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes"; type state_type is ( idle, apply_input_mask, wait_start, wait_done, stop); signal state : state_type; signal ap_start_i : std_logic; --------------------------------------- constant OPCODE_WIDTH : integer := 4; constant ARG_MASK_LSB : integer := 0; constant ARG_MASK_MSB : integer := 7; constant SCALAR_MASK_LSB : integer := 8; constant SCALAR_MASK_MSB : integer := 15; constant OPCODE_LSB : integer := 16; constant OPCODE_MSB : integer := OPCODE_LSB+OPCODE_WIDTH-1; constant ISCALAR_MASK_LSB: integer := OPCODE_MSB+1; constant ISCALAR_MASK_MSB: integer := ISCALAR_MASK_LSB+7; -- input commands constant UPDATE_INPUT : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0000"; constant UPDATE_OUTPUT : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0001"; constant EXECUTE_STEP : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0010"; constant EXECUTE_RESUME : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0100"; constant EXECUTE_STOP : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0101"; -- constant EXECUTE : std_logic_vector(1 downto 0) := "10"; constant IARG_UM_LSB : integer := 0; constant OARG_UM_LSB : integer := 8; constant ISCALAR_UM_LSB : integer := 16; constant OSCALAR_UM_LSB : integer := 24; -- pragma translate_off type dbg_opcode_type is ( op_update_input, op_update_output, op_exec_step, op_exec_resume, op_exec_stop, op_invalid); signal dbg_opcode : dbg_opcode_type; -- pragma translate_on signal command_full : std_logic; signal command : std_logic_vector(31 downto 0); signal command_vld : std_logic; signal command_rdy : std_logic; -- signal arg_mask : std_logic_vector(7 downto 0); signal scalar_mask : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); signal opcode : std_logic_vector(OPCODE_WIDTH-1 downto 0); -- signal input_mask_we : std_logic; signal input_mask_clr : std_logic; signal output_mask_we : std_logic; signal output_mask_clr : std_logic; -- signal iarg_mask : std_logic_vector(C_MAX_N_IARGS-1 downto 0); signal oarg_mask : std_logic_vector(C_MAX_N_OARGS-1 downto 0); signal iscalar_mask : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0); signal oscalar_mask : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0); -- signal iarg_start : std_logic; signal iarg_start_sync : std_logic; signal oarg_start : std_logic; signal oarg_start_sync : std_logic; signal iscalar_start : std_logic; signal iscalar_start_sync: std_logic; signal oscalar_start : std_logic; signal oscalar_start_sync : std_logic; signal global_start : std_logic; -- signal mb_iarg_done_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0); signal mb_oarg_done_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0); -- -- Core ap_start delayed version. signal core_ap_start : std_logic; signal set_ap_start : std_logic; signal set_ap_start_r : std_logic; signal clr_ap_start : std_logic; signal run_continous : std_logic; signal ap_cmd_error : std_logic; signal host_cmd_error_i : std_logic; signal axi_rst : std_logic; --- Syncrhonizer signals signal iarg_rqt_enable_sync : std_logic_vector(C_MAX_N_IARGS-1 downto 0); signal oarg_rqt_enable_sync : std_logic_vector(C_MAX_N_OARGS-1 downto 0); signal ap_start_i_sync : std_logic; signal ap_done_sync : std_logic; signal ap_idle_sync : std_logic; signal ap_ready_sync : std_logic; signal ap_cmd_error_sync : std_logic; signal ap_rstn : std_logic; signal ap_rst_vec : std_logic_vector(0 downto 0); signal ap_rst_axi_sync : std_logic; signal ap_rst_sync : std_logic_vector(0 downto 0); signal axin_rst : std_logic; constant C_EXTRA_SYNCS : integer := 1; ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF axi_rst : SIGNAL IS "true"; begin -- Active low ap_rst ap_rstn <= not ap_rst; ---------------------- --- Reset Synchronizer ---------------------- -- EN_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate -- begin -- -- -- XD_IARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync -- generic map ( -- C_CDC_TYPE => 1, -- C_RESET_STATE => 0, -- C_SINGLE_BIT => 0, -- C_FLOP_INPUT => 1, -- C_VECTOR_WIDTH => C_MAX_N_IARGS, -- C_MTBF_STAGES => C_MTBF_STAGES -- ) -- port map ( -- prmry_aclk => S_AXI_ACLK, -- prmry_resetn => S_AXI_ARESETN, -- prmry_in => '0', -- prmry_vect_in => iarg_rqt_enable, -- -- scndry_aclk => ap_clk, -- scndry_resetn => ap_rstn, -- scndry_out => open, -- scndry_vect_out => iarg_rqt_enable_sync -- ); -- -- -- XD_OARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync -- generic map ( -- C_CDC_TYPE => 1, -- C_RESET_STATE => 0, -- C_SINGLE_BIT => 0, -- C_FLOP_INPUT => 0, -- C_VECTOR_WIDTH => C_MAX_N_OARGS, -- C_MTBF_STAGES => C_MTBF_STAGES -- ) -- port map ( -- prmry_aclk => S_AXI_ACLK, -- prmry_resetn => S_AXI_ARESETN, -- prmry_in => '0', -- prmry_vect_in => oarg_rqt_enable, -- -- scndry_aclk => ap_clk, -- scndry_resetn => ap_rstn, -- scndry_out => open, -- scndry_vect_out => oarg_rqt_enable_sync -- ); -- -- end generate EN_SYNC_GEN; -- -- NO_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate -- begin iarg_rqt_enable_sync <= iarg_rqt_enable; oarg_rqt_enable_sync <= oarg_rqt_enable; -- end generate NO_SYNC_GEN; ---------------------- --- Reset Synchronizer ---------------------- EN_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate begin AP_START_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_start_i, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_start_i_sync, scndry_vect_out => open ); AP_DONE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_done, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_done_sync, scndry_vect_out => open ); AP_IDLE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_idle, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_idle_sync, scndry_vect_out => open ); AP_READY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_ready, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_ready_sync, scndry_vect_out => open ); AP_CMDERR_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_cmd_error, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_cmd_error_sync, scndry_vect_out => open ); end generate EN_APCLK_LITE_SYNC_GEN; NO_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate begin -- -- ap_start_i_sync <= ap_start_i; -- ap_done_sync <= ap_done; -- ap_idle_sync <= ap_idle; -- ap_ready_sync <= ap_ready; -- ap_cmd_error_sync <= ap_cmd_error; -- AP_START_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_start_i, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_start_i_sync, scndry_vect_out => open ); AP_DONE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_done, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_done_sync, scndry_vect_out => open ); AP_IDLE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_idle, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_idle_sync, scndry_vect_out => open ); AP_READY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_ready, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_ready_sync, scndry_vect_out => open ); AP_CMDERR_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 0, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => 2--C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rstn, prmry_in => ap_cmd_error, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => ap_cmd_error_sync, scndry_vect_out => open ); end generate NO_APCLK_LITE_SYNC_GEN; ---------------------- --- Reset Synchronizer ---------------------- mb_iarg_done <= mb_iarg_done_i; mb_oarg_done <= mb_oarg_done_i; axin_rst <= not(S_AXI_ARESETN); -- axi_rst <= not(S_AXI_ARESETN) or ap_rst; -- ap_rst_vec(0) <= ap_rst; -- -- rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff -- GENERIC MAP ( -- C_HAS_RST => 1, -- C_WIDTH => 1 -- ) -- PORT MAP ( -- RST => S_AXI_ARESETN, -- CLK => S_AXI_ACLK, -- D => ap_rst_vec, -- Q => ap_rst_sync -- ); -- process(S_AXI_ACLK) -- begin -- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then -- ap_rst_vec(0) <= ap_rst; -- ap_rst_sync(0) <= ap_rst_vec(0); -- end if; -- end process; -- process(S_AXI_ACLK, S_AXI_ARESETN) -- begin -- if(S_AXI_ARESETN='0') then -- axi_rst <= '1'; -- elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then -- axi_rst <= ap_rst_axi_sync; -- end if; -- end process; ap_rst_axi_sync1 : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 1, C_SINGLE_BIT => 1, C_FLOP_INPUT => 0, C_VECTOR_WIDTH => 1, C_MTBF_STAGES => 2 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => ap_rst, prmry_vect_in => (others=>'0'), scndry_aclk => S_AXI_ACLK, scndry_resetn => S_AXI_ARESETN, scndry_out => axi_rst, scndry_vect_out => open ); --------------------------------------- COMMAND_FIFO_NEW : entity axis_accelerator_adapter_v2_1_6.async_fifo_dist_inst generic map ( C_FAMILY => C_FAMILY, DEPTH => 32, WIDTH => 32) port map ( din => host_cmd_data, din_vld => host_cmd_we, din_rdy => host_cmd_rdy, wr_clk => S_AXI_ACLK, wr_rst => axi_rst, dout => command, dout_vld => command_vld, dout_rdy => command_rdy, rd_clk => ap_clk, rd_rst => ap_rst); arg_mask <= command(ARG_MASK_MSB downto ARG_MASK_LSB); scalar_mask <= command(ISCALAR_MASK_MSB downto ISCALAR_MASK_LSB) & command(SCALAR_MASK_MSB downto SCALAR_MASK_LSB); --scalar_mask <= command(SCALAR_MASK_MSB downto SCALAR_MASK_LSB); opcode <= command(OPCODE_MSB downto OPCODE_LSB); process(ap_clk) begin if(ap_clk'event and ap_clk = '1') then if(ap_rst = '1' or input_mask_clr = '1') then iarg_mask <= (others => '0'); iscalar_mask <= (others => '0'); elsif(input_mask_we = '1') then iarg_mask <= iarg_mask or arg_mask; iscalar_mask <= iscalar_mask or scalar_mask; end if; end if; end process; process(ap_clk) begin if(ap_clk'event and ap_clk = '1') then if(ap_rst = '1' or output_mask_clr = '1') then oarg_mask <= (others => '0'); oscalar_mask <= (others => '0'); elsif(output_mask_we = '1') then oarg_mask <= oarg_mask or arg_mask; oscalar_mask <= oscalar_mask or scalar_mask(15 downto 0); end if; end if; end process; ---------------------------------------- USE_INPUT_ARGS_GEN : if (C_N_INPUT_ARGS > 0) generate begin iarg_start <= and_reduce(mb_iarg_rdy(C_N_INPUT_ARGS-1 downto 0) or not(iarg_rqt_enable_sync(C_N_INPUT_ARGS-1 downto 0))); end generate USE_INPUT_ARGS_GEN; NO_INPUT_ARGS_GEN : if (C_N_INPUT_ARGS = 0) generate begin iarg_start <= '1'; end generate NO_INPUT_ARGS_GEN; USE_OUTPUT_ARGS_GEN : if (C_N_OUTPUT_ARGS > 0) generate begin oarg_start <= and_reduce(mb_oarg_rdy(C_N_OUTPUT_ARGS-1 downto 0) or not(oarg_rqt_enable_sync(C_N_OUTPUT_ARGS-1 downto 0))); end generate USE_OUTPUT_ARGS_GEN; NO_OUTPUT_ARGS_GEN : if (C_N_OUTPUT_ARGS = 0) generate begin oarg_start <= '1'; end generate NO_OUTPUT_ARGS_GEN; USE_INPUT_SCALAR_GEN1 : if (C_N_INPUT_SCALARS+C_N_INOUT_SCALARS > 0 ) generate begin iscalar_start <= and_reduce((ap_iscalar_rdy(C_MAX_N_ISCALARS-1 downto 0)) or not(iscalar_rqt_enable(C_MAX_N_ISCALARS-1 downto 0))); --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0) or not(iscalar_rqt_enable(C_N_INPUT_SCALARS-1 downto 0))) and and_reduce(ap_iscalar_rdy(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) or not(iscalar_rqt_enable(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS))); end generate USE_INPUT_SCALAR_GEN1; -- USE_INPUT_SCALAR_GEN2 : if (C_N_INPUT_SCALARS > 0 and C_N_INOUT_SCALARS = 0) generate -- begin -- --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0)); -- iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0) or not(iscalar_rqt_enable(C_N_INPUT_SCALARS-1 downto 0))); -- end generate USE_INPUT_SCALAR_GEN2; -- -- USE_INPUT_SCALAR_GEN3 : if (C_N_INPUT_SCALARS = 0 and C_N_INOUT_SCALARS > 0) generate -- begin -- --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0)); -- iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS) or not(iscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS))); -- end generate USE_INPUT_SCALAR_GEN3; NO_INPUT_SCALAR_GEN : if (C_N_INPUT_SCALARS = 0 and C_N_INOUT_SCALARS = 0) generate begin iscalar_start <= '1'; end generate NO_INPUT_SCALAR_GEN; USE_OUTPUT_SCALAR_GEN1 : if (C_N_OUTPUT_SCALARS+C_N_INOUT_SCALARS > 0 ) generate begin oscalar_start <= and_reduce((ap_oscalar_rdy(C_MAX_N_OSCALARS-1 downto 0)) or not(oscalar_rqt_enable(C_MAX_N_OSCALARS-1 downto 0))); --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0) or not(oscalar_rqt_enable(C_N_OUTPUT_SCALARS-1 downto 0))); end generate USE_OUTPUT_SCALAR_GEN1; -- USE_OUTPUT_SCALAR_GEN2 : if (C_N_OUTPUT_SCALARS > 0 and C_N_INOUT_SCALARS > 0) generate -- begin -- --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0)); -- oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) or not(oscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS))) and and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0) or not(oscalar_rqt_enable(C_N_OUTPUT_SCALARS-1 downto 0))); -- end generate USE_OUTPUT_SCALAR_GEN2; -- -- USE_OUTPUT_SCALAR_GEN3 : if (C_N_OUTPUT_SCALARS = 0 and C_N_INOUT_SCALARS > 0) generate -- begin -- --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0)); -- oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) or not(oscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS))); -- end generate USE_OUTPUT_SCALAR_GEN3; NO_OUTPUT_SCALAR_GEN : if (C_N_OUTPUT_SCALARS = 0 and C_N_INOUT_SCALARS = 0) generate begin oscalar_start <= '1'; end generate NO_OUTPUT_SCALAR_GEN; -- pragma translate_off process(opcode) begin dbg_opcode <= op_invalid; case opcode is when UPDATE_INPUT => dbg_opcode <= op_update_input; when UPDATE_OUTPUT => dbg_opcode <= op_update_output; when EXECUTE_STEP => dbg_opcode <= op_exec_step; when EXECUTE_RESUME => dbg_opcode <= op_exec_resume; when EXECUTE_STOP => dbg_opcode <= op_exec_stop; when others => null; end case; end process; -- pragma translate_on EXISTING : if (C_EXTRA_SYNCS = 0) generate begin global_start <= iarg_start and oarg_start and iscalar_start and oscalar_start; end generate EXISTING; NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate begin AP_IARGSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => ap_clk, prmry_resetn => ap_rst, prmry_in => iarg_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => iarg_start_sync, scndry_vect_out => open ); AP_OARGSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => S_AXI_ACLK, prmry_resetn => S_AXI_ARESETN, prmry_in => oarg_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => oarg_start_sync, scndry_vect_out => open ); AP_ISCALARSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => S_AXI_ACLK, prmry_resetn => S_AXI_ARESETN, prmry_in => iscalar_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => iscalar_start_sync, scndry_vect_out => open ); AP_OSCALARSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_FLOP_INPUT => 1, C_VECTOR_WIDTH => C_MAX_N_IARGS, C_MTBF_STAGES => C_MTBF_STAGES ) port map ( prmry_aclk => S_AXI_ACLK, prmry_resetn => S_AXI_ARESETN, prmry_in => oscalar_start, prmry_vect_in => (others=>'0'), scndry_aclk => ap_clk, scndry_resetn => ap_rst, scndry_out => oscalar_start_sync, scndry_vect_out => open ); global_start <= iarg_start_sync and oarg_start_sync and iscalar_start_sync and oscalar_start_sync; end generate NEW_INTRO; process(ap_clk, ap_rst) begin if(ap_rst = '1') then state <= idle; ap_start_i <= '0'; ap_start_one_shot <= '0'; run_continous <= '0'; elsif(ap_clk'event and ap_clk = '1') then ap_start_i <= '0'; ap_start_one_shot <= '0'; case state is when idle => -- Wait until there is a command available if (command_vld = '1') then case opcode is when EXECUTE_STEP => state <= wait_start; when EXECUTE_RESUME => run_continous <= '1'; state <= wait_start; when others => end case; end if; when apply_input_mask => -- In this state we apply the command. For input arguments and -- scalars we give a "done" of the elements. state <= wait_start; when wait_start => if (run_continous = '0') then -- accelerator start is given when: -- 1.- all input arguments have data valid to process. -- 2.- all ouput arguments have free memory where to wite the -- processed data. if (global_start = '1') then state <= wait_done; ap_start_i <= '1'; ap_start_one_shot <= '1'; end if; else if (command_vld = '1') then case opcode is when EXECUTE_STOP => run_continous <= '0'; state <= idle; when others => state <= stop; end case; elsif (global_start = '1') then state <= wait_done; ap_start_i <= '1'; ap_start_one_shot <= '1'; end if; end if; when wait_done => if(ap_done = '1') then if (run_continous = '0') then state <= idle; else state <= apply_input_mask; end if; end if; when others => end case; end if; end process; ap_start <= core_ap_start; process(state, global_start, run_continous, command_vld, opcode, iarg_mask, iscalar_mask, arg_mask, scalar_mask, ap_done, oarg_mask, oscalar_mask) begin command_rdy <= '0'; input_mask_we <= '0'; output_mask_we <= '0'; input_mask_clr <= '0'; output_mask_clr <= '0'; mb_iarg_done_i <= (others => '0'); ap_iscalar_done <= (others => '0'); mb_oarg_done_i <= (others => '0'); ap_oscalar_vld <= (others => '0'); set_ap_start <= '0'; ap_cmd_error <= '0'; case state is when idle => command_rdy <= command_vld; if(command_vld = '1') then case opcode is when UPDATE_INPUT => input_mask_we <= '1'; mb_iarg_done_i <= arg_mask; ap_iscalar_done <= scalar_mask; when UPDATE_OUTPUT => output_mask_we <= '1'; when EXECUTE_STEP => when EXECUTE_RESUME => when EXECUTE_STOP => when others => end case; end if; when apply_input_mask => mb_iarg_done_i <= iarg_mask; ap_iscalar_done <= iscalar_mask; when wait_start => if (run_continous = '0') then set_ap_start <= global_start; else if (command_vld = '1') then command_rdy <= '1'; if (opcode = EXECUTE_STOP) then input_mask_clr <= '1'; output_mask_clr <= '1'; else ap_cmd_error <= '1'; end if; else set_ap_start <= global_start; end if; end if; when wait_done => if(ap_done = '1') then -- Toggle the output argument multibuffer (if enabled) if (C_N_OUTPUT_ARGS > 0) then mb_oarg_done_i(C_N_OUTPUT_ARGS-1 downto 0) <= oarg_mask(C_N_OUTPUT_ARGS-1 downto 0); end if; -- Write values in output FIFOs (if enabled) if (C_N_OUTPUT_SCALARS+C_N_INOUT_SCALARS > 0) then ap_oscalar_vld(C_MAX_N_OSCALARS-1 downto 0) <= oscalar_mask(C_MAX_N_OSCALARS-1 downto 0); end if; -- if (C_N_INOUT_SCALARS > 0) then -- ap_oscalar_vld(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= oscalar_mask(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS); -- end if; -- clear input/output masks before we start a new iteration input_mask_clr <= not(run_continous); output_mask_clr <= not(run_continous); end if; when others => end case; end process; clr_ap_start <= ap_ready; process(ap_clk, ap_rst) begin if(ap_rst = '1') then set_ap_start_r <= '0'; elsif(ap_clk'event and ap_clk = '1') then set_ap_start_r <= set_ap_start; end if; end process; process(ap_clk, ap_rst) begin if(ap_rst = '1') then core_ap_start <= '0'; elsif(ap_clk'event and ap_clk = '1') then -- Core ap_start delayed version. if(core_ap_start = '0') then core_ap_start <= set_ap_start_r; else core_ap_start <= not(clr_ap_start); end if; end if; end process; --------------------------- SYNC_AP_START_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_start_i_sync, axi_clk => S_AXI_ACLK, flag => status_ap_start, flag_clr => status_ap_start_clr); SYNC_AP_DONE_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_done_sync, axi_clk => S_AXI_ACLK, flag => status_ap_done, flag_clr => status_ap_done_clr); STATUS_AP_IDLE_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_idle_sync, axi_clk => S_AXI_ACLK, flag => status_ap_idle, flag_clr => status_ap_idle_clr); STATUS_AP_READY_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_ready_sync, axi_clk => S_AXI_ACLK, flag => status_ap_ready, flag_clr => status_ap_ready_clr); SYNC_AP_CMD_ERROR_I : entity work.sync_ap_status port map ( rst => soft_rst, ap_clk => S_AXI_ACLK, ap_flag => ap_cmd_error_sync, axi_clk => S_AXI_ACLK, flag => host_cmd_error_i, flag_clr => host_cmd_error_i); host_cmd_error <= host_cmd_error_i; -- TODO: status_iarg_rqt <= (others => '0'); status_iarg_ack <= (others => '0'); status_oarg_rqt <= (others => '0'); status_oarg_ack <= (others => '0'); ap_continue <= ap_done; end rtl;

<filename>bin_Erosion_Operation/ip/Erosion/fp_delbit.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DELBIT.VHD *** --*** *** --*** Function: Generic Bit Delay *** --*** *** --*** 01/12/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_delbit IS GENERIC ( pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); END fp_delbit; ARCHITECTURE rtl OF fp_delbit IS component fp_delbit_one IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; component fp_delbit_var IS GENERIC ( pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; BEGIN genone: IF (pipes = 1) GENERATE delone: fp_delbit_one PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; genvar: IF (pipes > 1) GENERATE delvar: fp_delbit_var GENERIC MAP (pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; END rtl;

<reponame>MohammadNiknam17/VHDL-12BIT-Counter-to-7segment-output library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- common cathode 7Segment entity Binary_To_7S_HEX is port (Binary: in std_logic_vector (3 downto 0); a,b,c,d,e,f,g: out std_logic); end Binary_To_7S_HEX; architecture Behavioral of Binary_To_7S_HEX is signal TMP: std_logic_vector(6 downto 0); begin process(Binary) begin case Binary is when "0000" => TMP <= "1111110" ; -- 0 HEX when "0001" => TMP <= "0110000" ; -- 1 HEX when "0010" => TMP <= "1101101" ; -- 2 HEX when "0011" => TMP <= "1111001" ; -- 3 HEX when "0100" => TMP <= "0110011" ; -- 4 HEX when "0101" => TMP <= "1011011" ; -- 5 HEX when "0110" => TMP <= "1011111" ; -- 6 HEX when "0111" => TMP <= "1110001" ; -- 7 HEX when "1000" => TMP <= "1111111" ; -- 8 HEX when "1001" => TMP <= "1110011" ; -- 9 HEX when "1010" => TMP <= "1110111" ; -- A HEX when "1011" => TMP <= "0011111" ; -- B HEX when "1100" => TMP <= "1001110" ; -- C HEX when "1101" => TMP <= "0111101" ; -- D HEX when "1110" => TMP <= "1001111" ; -- E HEX when "1111" => TMP <= "1000111" ; -- F HEX when others => TMP <= "0000000" ; end case; end process; a <= TMP(6); b <= TMP(5); c <= TMP(4); d <= TMP(3); e <= TMP(2); f <= TMP(1); g <= TMP(0); end Behavioral;

----------------------------------------------------------------------- -- int mul wrapper ----------------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.customTypes.all; entity mul_op is Generic ( INPUTS: integer; OUTPUTS: integer; DATA_SIZE_IN: integer; DATA_SIZE_OUT: integer ); port ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; pValidArray : IN std_logic_vector(1 downto 0); nReadyArray : in std_logic_vector(0 downto 0); validArray : out std_logic_vector(0 downto 0); readyArray : OUT std_logic_vector(1 downto 0); dataInArray : in data_array (1 downto 0)(DATA_SIZE_IN-1 downto 0); dataOutArray : out data_array (0 downto 0)(DATA_SIZE_OUT-1 downto 0)); end entity; architecture arch of mul_op is signal join_valid : STD_LOGIC; -- multiplier latency (4 or 8) constant LATENCY : integer := 4; --constant LATENCY : integer := 8; begin join: entity work.join(arch) generic map(2) port map( pValidArray, nReadyArray(0), join_valid, readyArray); -- instantiated multiplier (work.mul_4_stage or work.mul_8_stage) multiply_unit: entity work.mul_4_stage(behav) --multiply_unit: entity work.mul_8_stage(behav) port map ( clk => clk, ce => nReadyArray(0), a => dataInArray(0), b => dataInArray(1), p => dataOutArray(0)); buff: entity work.delay_buffer(arch) generic map(LATENCY) port map(clk, rst, join_valid, nReadyArray(0), validArray(0)); end architecture;

<reponame>Scheams/vhdl-calculator -------------------------------------------------------------------------------- -- Author: <NAME> -- -- Created: 01.12.2019 -- -- Unit: IO Control Unit (Testbench) -- -- Version: -- -) Version 1.0.0 -- -- Changelog: -- -) Version 1.0.0 (01.12.2019) -- First implementation of IO Control Unit testbench. -- -- Description: -- Check if the IO Control Unit debounces the buttons and switches with a -- lower frequency than the system clock. Furthermore, check if the LED -- signals are looped through. Change the signals on the the digits and -- verfiy that the unit hops through all the digts with the select line. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity tb_io_ctrl is end tb_io_ctrl; architecture sim of tb_io_ctrl is component io_ctrl port ( clk_i : in std_logic; reset_i : in std_logic; dig0_i : in std_logic_vector ( 7 downto 0); dig1_i : in std_logic_vector ( 7 downto 0); dig2_i : in std_logic_vector ( 7 downto 0); dig3_i : in std_logic_vector ( 7 downto 0); led_i : in std_logic_vector (15 downto 0); sw_i : in std_logic_vector (15 downto 0); pb_i : in std_logic_vector ( 3 downto 0); ss_o : out std_logic_vector( 7 downto 0); ss_sel_o : out std_logic_vector( 3 downto 0); led_o : out std_logic_vector(15 downto 0); swsync_o : out std_logic_vector(15 downto 0); pbsync_o : out std_logic_vector( 3 downto 0) ); end component; signal s_clk_i : std_logic; signal s_reset_i : std_logic; signal s_dig0_i : std_logic_vector ( 7 downto 0); signal s_dig1_i : std_logic_vector ( 7 downto 0); signal s_dig2_i : std_logic_vector ( 7 downto 0); signal s_dig3_i : std_logic_vector ( 7 downto 0); signal s_led_i : std_logic_vector (15 downto 0); signal s_sw_i : std_logic_vector (15 downto 0); signal s_pb_i : std_logic_vector ( 3 downto 0); signal s_ss_o : std_logic_vector( 7 downto 0); signal s_ss_sel_o : std_logic_vector( 3 downto 0); signal s_led_o : std_logic_vector(15 downto 0); signal s_swsync_o : std_logic_vector(15 downto 0); signal s_pbsync_o : std_logic_vector( 3 downto 0); begin u_sim: io_ctrl port map ( clk_i => s_clk_i, reset_i => s_reset_i, dig0_i => s_dig0_i, dig1_i => s_dig1_i, dig2_i => s_dig2_i, dig3_i => s_dig3_i, led_i => s_led_i, sw_i => s_sw_i, pb_i => s_pb_i, ss_o => s_ss_o, ss_sel_o => s_ss_sel_o, led_o => s_led_o, swsync_o => s_swsync_o, pbsync_o => s_pbsync_o ); ---------------------------------------------------------------------------- -- Create a reset pulse ---------------------------------------------------------------------------- p_reset: process begin s_reset_i <= '1'; wait for 500 us; s_reset_i <= '0'; wait; end process p_reset; ---------------------------------------------------------------------------- -- Create a 100MHz clock ---------------------------------------------------------------------------- p_clk: process begin s_clk_i <= '1'; wait for 5 ns; s_clk_i <= '0'; wait for 5 ns; end process p_clk; ---------------------------------------------------------------------------- -- Simulate push buttons and check if they are debounced ---------------------------------------------------------------------------- p_pb: process begin s_pb_i <= "0000"; wait for 1 ms; s_pb_i <= "0001"; wait for 3 ms; s_pb_i <= "0010"; wait for 3 ms; s_pb_i <= "0100"; wait for 3 ms; s_pb_i <= "1000"; wait for 1 ms; s_pb_i <= "0000"; wait for 1 ms; s_pb_i <= "1000"; wait; end process p_pb; ---------------------------------------------------------------------------- -- Simulate switches and check if they are debounced ---------------------------------------------------------------------------- p_sw: process begin s_sw_i <= X"0000"; wait for 1 ms; s_sw_i <= X"0F00"; wait for 3 ms; s_sw_i <= X"00F0"; wait for 3 ms; s_sw_i <= X"0000"; wait for 3 ms; s_sw_i <= X"5555"; wait for 1 ms; s_sw_i <= X"AAA5"; wait; end process p_sw; ---------------------------------------------------------------------------- -- Simulate LEDs turn on or off ---------------------------------------------------------------------------- p_led: process begin s_led_i <= X"0000"; wait for 1 ms; s_led_i <= X"5555"; wait for 6 ms; s_led_i <= X"AAAA"; wait for 3 ms; s_led_i <= X"0000"; wait; end process p_led; ---------------------------------------------------------------------------- -- Simulate raw values on the digits and check if they are displayed -- one after another. ---------------------------------------------------------------------------- p_dig: process begin s_dig0_i <= "11111111"; s_dig1_i <= "11111111"; s_dig2_i <= "11111111"; s_dig3_i <= "11111111"; wait for 1 ms; s_dig0_i <= "00111111"; s_dig1_i <= "11001111"; s_dig2_i <= "11110011"; s_dig3_i <= "11111100"; wait for 3 ms; s_dig0_i <= "00000000"; s_dig1_i <= "00111100"; s_dig2_i <= "11111111"; s_dig3_i <= "11000011"; wait for 3 ms; s_dig0_i <= "01010101"; s_dig1_i <= "10101010"; s_dig2_i <= "11110000"; s_dig3_i <= "00001111"; wait for 3 ms; s_dig0_i <= "10000000"; s_dig1_i <= "00100000"; s_dig2_i <= "00001000"; s_dig3_i <= "00000010"; wait; end process p_dig; end sim;

<filename>VHDL/dual_port_vram/ram.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RAM is port ( clock : in std_logic; -- Port a has read and write a_addr : in std_logic_vector(9 downto 0); a_write : in std_logic; a_din : in std_logic_vector(7 downto 0); a_dout : out std_logic_vector(7 downto 0); -- Port b is read only b_addr : in std_logic_vector(9 downto 0); b_dout : out std_logic_vector(7 downto 0) ); end entity RAM; architecture behavioural of RAM is type memory is array(0 to 1023) of std_logic_vector(7 downto 0); signal storage : memory := (others => (others => '0')); begin process(clock) begin if rising_edge(clock) then a_dout <= storage(to_integer(unsigned(a_addr))); b_dout <= storage(to_integer(unsigned(b_addr))); if a_write = '1' then storage(to_integer(unsigned(a_addr))) <= a_din; end if; end if; end process; end behavioural;

--********************************************************************** -- Copyright 2011-2012 by XESS Corp <http://www.xess.com>. -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. --********************************************************************** ---------------------------------------------------------------------------------- -- Modules for passing bits back and forth from the host PC -- to FPGA application logic through the JTAG port. ---------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.CommonPckg.all; package HostIoPckg is -- FPGA device type that's used to select the appropriate BSCAN primitive. type FpgaDevice_t is (SPARTAN3A, SPARTAN6); -- Use one of these to select which USER opcode enables the I/O to the host through the JTAG port. type TapUserInstr_t is (USER0, USER1, USER2, USER3, USER4); -- Use one of these to select the memory operation to perform via the JTAG port. constant NOP_OPCODE_C : std_logic_vector(1 downto 0) := "00"; constant SIZE_OPCODE_C : std_logic_vector(1 downto 0) := "01"; constant WRITE_OPCODE_C : std_logic_vector(1 downto 0) := "10"; constant READ_OPCODE_C : std_logic_vector(1 downto 0) := "11"; component BscanToHostIo is generic ( FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1 -- USER instruction this module responds to. ); port ( -- Interface to HostIoHdrScanner. inShiftDr_o : out std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_o : out std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_o : out std_logic; -- Bit from the host to the FPGA application logic. tdo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoa_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdob_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoc_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdod_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoe_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdof_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdog_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoh_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoi_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoj_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdok_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdol_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdom_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdon_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdop_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoq_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdor_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdos_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdot_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdou_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdov_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdow_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdox_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoy_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoz_i : in std_logic := LO -- Bit from the FPGA application logic to the host. ); end component; component HostIoHdrScanner is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32 -- Length of payload bit counter. ); port ( -- Interface to BscanHostIo. inShiftDr_i : in std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic; -- Bit from the host to the FPGA application logic. -- Interface to FPGA application logic. pyldCntr_o : out std_logic_vector(PYLD_CNTR_LENGTH_G-1 downto 0); -- This counts down the number of payload bits still to be received. active_o : out std_logic -- Tell the external circuitry it has been activated. ); end component; component RamCtrlSync is port ( drck_i : in std_logic; -- Clock from JTAG domain. clk_i : in std_logic; -- Clock from RAM domain. ctrlIn_i : in std_logic; -- Control signal from JTAG domain. ctrlOut_o : out std_logic; -- Control signal to RAM domain. opBegun_i : in std_logic := HI; -- R/W operation begun signal from RAM domain. doneIn_i : in std_logic := HI; -- R/W operation done signal from RAM domain. doneOut_o : out std_logic -- R/W operation done signal to the JTAG domain. ); end component; component HostIoToRamCore is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1 -- Add to address after each memory R/W operation. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the FPGA application logic. tdo_o : out std_logic; -- Bit from the FPGA application logic to the host. -- Interface to the memory. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. rwDone_i : in std_logic := HI -- True when memory read/write operation is done. ); end component; component HostIoToRam is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1; -- Add to address after each memory R/W operation. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false; -- If true, include BscanToHostIo module in this module. SYNC_G : boolean := true -- If true, sync this module with the memory clock domain. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the memory. tdo_o : out std_logic; -- Bit from the memory to the host. -- Interface to the memory. clk_i : in std_logic := LO; -- Clock from FPGA application logic. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. opBegun_i : in std_logic := HI; -- High when memory read/write operation has begun. done_i : in std_logic := HI -- High when memory read/write operation is done. ); end component; component HostIoToDut is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false -- If true, include BscanToHostIo module in this module. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the DUT. tdo_o : out std_logic; -- Bit from the DUT to the host. -- Interface to DUT. clkToDut_o : out std_logic; -- Rising edge clock signals arrival of vector to DUT. vectorFromDut_i : in std_logic_vector; -- Gather inputs to send back to host thru this bus. vectorToDut_o : out std_logic_vector -- Output test vector from the host to DUT thru this bus. ); end component; end package; --************************************************************************************************** -- This module connects the BSCAN primitive to a HostIo module. --************************************************************************************************** library IEEE, UNISIM; use IEEE.STD_LOGIC_1164.all; use UNISIM.VComponents.all; use work.CommonPckg.all; use work.HostIoPckg.all; entity BscanToHostIo is generic ( FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1 -- USER instruction this module responds to. ); port ( -- Interface to HostIoHdrScanner. inShiftDr_o : out std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_o : out std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_o : out std_logic; -- Bit from the host to the FPGA application logic. tdo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoa_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdob_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoc_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdod_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoe_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdof_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdog_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoh_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoi_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoj_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdok_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdol_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdom_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdon_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoo_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdop_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoq_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdor_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdos_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdot_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdou_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdov_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdow_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdox_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoy_i : in std_logic := LO; -- Bit from the FPGA application logic to the host. tdoz_i : in std_logic := LO -- Bit from the FPGA application logic to the host. ); end entity; architecture arch of BscanToHostIo is -- Signals from BSCAN primitive. signal bscanReset_s : std_logic; signal bscanShift_s : std_logic; signal bscanDrck1_s : std_logic; signal bscanDrck2_s : std_logic; signal bscanSel1_s : std_logic; signal bscanSel2_s : std_logic; signal bscanSel_s : std_logic; signal tdo_s : std_logic; begin spartan3a_bscan : if FPGA_DEVICE_G = SPARTAN3A generate -- Boundary-scan interface to FPGA JTAG port. UBscanUser : BSCAN_SPARTAN3A port map( DRCK1 => bscanDrck1_s, -- data clock after USER1 instruction received. DRCK2 => bscanDrck2_s, -- data clock after USER2 instruction received. RESET => bscanReset_s, -- JTAG TAP FSM reset. SEL1 => bscanSel1_s, -- USER1 instruction enables user-I/O. SEL2 => bscanSel2_s, -- USER2 instruction enables user-I/O. SHIFT => bscanShift_s, -- True when JTAG TAP FSM is in the SHIFT-DR state. TDI => tdi_o, -- Data bits from the host arrive through here. TDO1 => tdo_s, -- Bits from the FPGA app. logic go to the TDO pin and back to the host. TDO2 => tdo_s -- Bits from the FPGA app. logic go to the TDO pin and back to the host. ); -- All the bits from the application logic are OR'ed together since only one HostIo module -- will be active and the others will pull their TDO outputs to logic 0. tdo_s <= tdo_i or tdoa_i or tdob_i or tdoc_i or tdod_i or tdoe_i or tdof_i or tdog_i or tdoh_i or tdoi_i or tdoj_i or tdok_i or tdol_i or tdom_i or tdon_i or tdoo_i or tdop_i or tdoq_i or tdor_i or tdos_i or tdot_i or tdou_i or tdov_i or tdow_i or tdox_i or tdoy_i or tdoz_i; -- Select the appropriate sel signal based upon which USER instruction this module responds to. bscanSel_s <= bscanSel1_s when TAP_USER_INSTR_G = USER1 else bscanSel2_s; -- Detect when a USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. inShiftDr_o <= YES when bscanReset_s = LO and bscanShift_s = HI and bscanSel_s = HI else NO; -- Output the appropriate drck signal to the HostIo module. drck_o <= bscanDrck1_s when TAP_USER_INSTR_G = USER1 else bscanDrck2_s; end generate; spartan6_bscan : if FPGA_DEVICE_G = SPARTAN6 generate -- Boundary-scan interface to FPGA JTAG port. UBscanUser : BSCAN_SPARTAN6 generic map( JTAG_CHAIN => TapUserInstr_t'pos(TAP_USER_INSTR_G) ) port map( DRCK => drck_o, -- Data clock after USER instruction received. RESET => bscanReset_s, -- JTAG TAP FSM reset. SEL => bscanSel_s, -- True when USER instruction enters IR. SHIFT => bscanShift_s, -- True when JTAG TAP FSM is in the SHIFT-DR state. TDI => tdi_o, -- Data bits from the host arrive through here. TDO => tdo_s -- Bits from the FPGA app. logic go to the TDO pin and back to the host. ); -- All the bits from the application logic are OR'ed together since only one HostIo module -- will be active and the others will pull their TDO outputs to logic 0. tdo_s <= tdo_i or tdoa_i or tdob_i or tdoc_i or tdod_i or tdoe_i or tdof_i or tdog_i or tdoh_i or tdoi_i or tdoj_i or tdok_i or tdol_i or tdom_i or tdon_i or tdoo_i or tdop_i or tdoq_i or tdor_i or tdos_i or tdot_i or tdou_i or tdov_i or tdow_i or tdox_i or tdoy_i or tdoz_i; -- Detect when a USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. inShiftDr_o <= YES when bscanReset_s = LO and bscanShift_s = HI and bscanSel_s = HI else NO; end generate; end architecture; --************************************************************************************************** -- This module accepts a bitstream from a BscanHostIo module and extracts an ID and -- the number of payload bits that follow. It triggers an attached module if the received -- ID matches the ID passed in by the generic parameter. The attached module accepts the -- bitstream until all the payload bits are processed. The attached module can also return -- results that it has produced (usually from an operation initiated by a previous instruction). -- After the payload bit counter decrements to zero, this module is reset and it -- repeats the entire process for the next instruction. -- -- If the received ID does not match, the attached module is not triggered. The bitstream -- continues downstream to look for a possible match with another module. -- -- | Complete Instruction | -- | Header reception | Payload reception | -- TDI: | ID | # of payload bits | Payload bits from host | -- TDO: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| Result bits from FPGA | -- Bit counter |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| N-1 N-2 ...... 2 1 0 | --************************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.CommonPckg.all; entity HostIoHdrScanner is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32 -- Length of payload bit counter. ); port ( -- Interface to BscanHostIo. inShiftDr_i : in std_logic; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic; -- Bit from the host to the FPGA application logic. -- Interface to FPGA application logic. pyldCntr_o : out std_logic_vector(PYLD_CNTR_LENGTH_G-1 downto 0); -- This counts down the number of payload bits still to be received. active_o : out std_logic -- Tell the external circuitry it has been activated. ); end entity; architecture arch of HostIoHdrScanner is -- The header register consists of the ID field and a field with the # of payload bits that follow. signal id_r : std_logic_vector(ID_G'high downto ID_G'low); signal pyldCntr_r : std_logic_vector(pyldCntr_o'range); signal hdrRcvd_r : std_logic; -- High after an ID and # of payload bits have been shifted in. begin -- Scan in the header and any following payload bits. process(drck_i) begin if rising_edge(drck_i) then -- Reset the header register if BSCAN drops out of USER SHIFT-DR state or if the current instruction is done. -- Detect when an instruction is done, i.e. has received all its payload bits. -- Detection uses payload counter value of 1 (not 0) because the last bit has entered at that point. if inShiftDr_i = NO or (hdrRcvd_r = YES and pyldCntr_r = 1) then -- Clear the header register and set MSbit of payload bit counter. A header has -- been received when this bit has been shifted all the way through the counter and ID -- registers and into the header received flag. id_r <= (others => ZERO); pyldCntr_r <= (others => ZERO); pyldCntr_r(pyldCntr_r'high) <= YES; hdrRcvd_r <= NO; else -- Otherwise, shift in header bits on the rising edge of DRCK. if hdrRcvd_r = NO then -- Shift bits into the header register until a complete header is received. pyldCntr_r <= tdi_i & pyldCntr_r(pyldCntr_r'high downto 1); id_r <= pyldCntr_r(0) & id_r(id_r'high downto 1); hdrRcvd_r <= id_r(0); else -- After a header has been received, count down the number of payload bits following the header. pyldCntr_r <= pyldCntr_r - 1; end if; end if; end if; end process; -- The attached module is activated if it matches the ID in the header. active_o <= HI when (id_r(id_r'high downto 0) = ID_G(0 to ID_G'high)) and (hdrRcvd_r = HI) else LO; -- Output the number of payload bits still to be received. pyldCntr_o <= pyldCntr_r; end architecture; --************************************************************************************************** -- This module interfaces with BscanToHostIo to perform read/write operations to memory devices. -- -- Write operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a write operation is activated by the opcode in the first two bits in the payload. -- This module then extracts a starting address from the payload bitstream. -- Then this module extracts data words from the payload bitstream and writes them to -- the memory device at sequentially increasing addresses beginning from that address. -- -- | Header reception | Payload bits | -- TDI: | ID | # of payload bits | Opcode | Starting address | Data1 | ..... | DataN | -- TDO: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| -- Addr: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| Addr1 | ..... | AddrN | -- Data: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| Data1 | ..... | DataN | -- -- Read operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a read operation is activated by the opcode in the first two bits in the payload. -- This module then extracts a starting address from the payload bitstream. -- Then this module reads data from the memory device at sequentially increasing addresses -- starting from that address, and it shifts them serially back to the host. -- (Valid data on TDO starts after the first read of the memory completes.) -- -- | Header reception | Payload bits | RAM data goes back to host | -- TDI: | ID | # of payload bits | Opcode | Starting address |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| -- TDO: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| Data1 | ... | DataN-1 | -- Addr: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| Addr1 | Addr2 | ... | AddrN | -- Data: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| Data1 | Data2 | ... | DataN | -- -- Parameter query operation: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a parameter query operation is activated by the opcode in the first two bits in the payload. -- This module then places the width of the memory address and data buses into a register -- and shifts it serially back to the host. -- -- | Header reception | Payload bits | Parameter data goes back to host | -- TDI: | ID | # of payload bits | Opcode |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| -- TDO: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| Address width | Data width | -- Addr: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| -- Data: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| --************************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.CommonPckg.all; use work.HostIoPckg.all; entity HostIoToRamCore is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1 -- Add to address after each memory R/W operation. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the FPGA application logic. tdo_o : out std_logic; -- Bit from the FPGA application logic to the host. -- Interface to the memory. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. rwDone_i : in std_logic := HI -- True when memory read/write operation is done. ); end entity; architecture arch of HostIoToRamCore is signal pyldCntr_s : std_logic_vector(PYLD_CNTR_LENGTH_G-1 downto 0); signal active_s : std_logic; signal opcode_r : std_logic_vector(NOP_OPCODE_C'range) := NOP_OPCODE_C; signal opcodeRcvd_r : std_logic := NO; signal addrFromHost_r : std_logic_vector(addr_o'high downto 0) := (others => ZERO); signal addrFromHostRcvd_r : std_logic := NO; constant PARAM_SIZE_C : natural := 16; constant SHIFT_REG_SIZE_C : natural := IntMax(PARAM_SIZE_C, dataFromHost_o'length); signal shiftReg_r : std_logic_vector(SHIFT_REG_SIZE_C-1 downto 0) := (others => ZERO); signal bitCntr_r : natural range 0 to SHIFT_REG_SIZE_C := 0; signal wrToMemory_r : std_logic := NO; signal rdFromMemory_r : std_logic := NO; signal dataFromMemory_r : std_logic_vector(dataToHost_i'high downto 0); begin -- Scan the bits from the host looking for an instruction header. UHdrScannner : HostIoHdrScanner generic map ( ID_G => ID_G, PYLD_CNTR_LENGTH_G => PYLD_CNTR_LENGTH_G ) port map ( -- Interface to BSCAN primitive. inShiftDr_i => inShiftDr_i, drck_i => drck_i, tdi_i => tdi_i, -- Interface to FPGA application logic. pyldCntr_o => pyldCntr_s, active_o => active_s ); -- Process the instruction bits as they arrive from the host. process(drck_i) begin if rising_edge(drck_i) then -- Keep processing as long as this module is activated or writing to memory. if (active_s = YES or wrToMemory_r = HI) and (reset_i = LO) then -- First, get the opcode from the host. if opcodeRcvd_r = NO then opcode_r <= tdi_i & opcode_r(opcode_r'high downto 1); opcodeRcvd_r <= opcode_r(0); -- Opcode complete once LSB is set. -- Next, process the received opcode. else case opcode_r is when SIZE_OPCODE_C => -- Return memory address and data bus parameters. if bitCntr_r = 0 then -- Load the memory parameters into the host shift register. shiftReg_r(PARAM_SIZE_C-1 downto 0) <= CONV_STD_LOGIC_VECTOR(dataFromHost_o'length, PARAM_SIZE_C/2) & CONV_STD_LOGIC_VECTOR(addr_o'length, PARAM_SIZE_C/2); bitCntr_r <= PARAM_SIZE_C; -- Set the number of data bits to send. else -- Shift next bit of memory parameters to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. end if; when WRITE_OPCODE_C => -- Perform write to memory. if addrFromHostRcvd_r = NO then -- Receiving the memory write address from the host. addrFromHost_r <= tdi_i & addrFromHost_r(addrFromHost_r'high downto 1); addrFromHostRcvd_r <= addrFromHost_r(0); -- Address complete once LSB is set. wrToMemory_r <= NO; shiftReg_r <= (others => ZERO); shiftReg_r(dataFromHost_o'high) <= ONE; else -- Now get data to write to memory from the host. if wrToMemory_r = YES and rwDone_i = YES then -- Write to memory is done. wrToMemory_r <= NO; -- Stop any further writes till another complete data word arrives from host. addrFromHost_r <= addrFromHost_r + ADDR_INC; -- Point to next memory location to be written (if needed). end if; if shiftReg_r(0) = LO then -- Shifting in data from host before writing it to memory. shiftReg_r(dataFromHost_o'range) <= tdi_i & shiftReg_r(dataFromHost_o'high downto 1); else -- Data from host received, now write it into the memory. dataFromHost_o <= tdi_i & shiftReg_r(dataFromHost_o'high downto 1); -- Store host data so it doesn't change if more bits arrive from host. -- Clear shift register so it can receive more data from the host. shiftReg_r <= (others => ZERO); shiftReg_r(dataFromHost_o'high) <= HI; wrToMemory_r <= YES; -- Initiate write of host data to memory. end if; end if; -- Perform read of memory. when READ_OPCODE_C => if addrFromHostRcvd_r = NO then -- Receiving the memory read address from the host. addrFromHost_r <= tdi_i & addrFromHost_r(addrFromHost_r'high downto 1); addrFromHostRcvd_r <= addrFromHost_r(0); -- Address complete once LSB is set. rdFromMemory_r <= addrFromHost_r(0); -- Initiate read as soon as address is received. bitCntr_r <= dataFromMemory_r'length - 1; -- Output garbage word until 1st read has a chance to complete. else if rdFromMemory_r = YES and rwDone_i = YES then -- Receive a complete data word from the host. rdFromMemory_r <= NO; -- OK, data is here so stop the reading the memory. dataFromMemory_r <= dataToHost_i; -- Store the memory data until it can be loaded into the host shift reg. end if; if bitCntr_r = 0 then -- Shift register is empty. shiftReg_r(dataFromMemory_r'range) <= dataFromMemory_r; -- Reload it with new data from memory. bitCntr_r <= dataFromMemory_r'length-1; -- Reload the bit counter. if pyldCntr_s >= shiftReg_r'length then -- Is more data expected by the host? addrFromHost_r <= addrFromHost_r + ADDR_INC; -- Point to next memory location to read from. rdFromMemory_r <= YES; -- Initiate the read operation. end if; else -- Shift register is shifting its contents to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. end if; end if; -- Default case is NOP. when others => null; end case; end if; else -- Reset everything when this module is not selected or is reset. opcode_r <= (others => ZERO); opcode_r(opcode_r'high) <= ONE; opcodeRcvd_r <= NO; addrFromHost_r <= (others => ZERO); addrFromHost_r(addrFromHost_r'high) <= ONE; addrFromHostRcvd_r <= NO; shiftReg_r <= (others => ZERO); shiftReg_r(dataFromHost_o'high) <= ONE; bitCntr_r <= 0; wrToMemory_r <= NO; rdFromMemory_r <= NO; end if; end if; end process; -- Force output low if this module has not been selected. -- This allows the bit outputs of multiple modules to be OR'ed together -- and sent to the TDO input of the BSCAN primitive. tdo_o <= shiftReg_r(0) when active_s = YES else LO; -- Attach this module to a memory. addr_o <= addrFromHost_r; wr_o <= wrToMemory_r; rd_o <= rdFromMemory_r; end architecture; --************************************************************************************************** -- This module synchronizes a HostIoToRamCore read or write control signal to the clock domain -- of the memory device. --************************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use work.CommonPckg.all; use work.SyncToClockPckg.all; entity RamCtrlSync is port ( drck_i : in std_logic; -- Clock from JTAG domain. clk_i : in std_logic; -- Clock from RAM domain. ctrlIn_i : in std_logic; -- Control signal from JTAG domain. ctrlOut_o : out std_logic; -- Control signal to RAM domain. opBegun_i : in std_logic := HI; -- R/W operation begun signal from RAM domain. doneIn_i : in std_logic := HI; -- R/W operation done signal from RAM domain. doneOut_o : out std_logic -- R/W operation done signal to the JTAG domain. ); end entity; architecture arch of RamCtrlSync is signal ctrlIn_s : std_logic; -- JTAG domain control signal sync'ed to RAM domain. begin -- Sync the RAM control signal from the JTAG clock domain to the RAM domain. UCtrlSync : SyncToClock port map (clk_i => clk_i, unsynced_i => ctrlIn_i, synced_o => ctrlIn_s); -- Now raise-and-hold the output control signal to the RAM upon a rising edge of the input control signal. -- Lower the output control signal if the input control signal goes low or if the RAM signals that the -- operation has begun or has finished. process(clk_i) variable prevCtrlIn_v : std_logic := HI; -- Previous value of the input control signal. begin if rising_edge(clk_i) then if ctrlIn_s = LO then -- Lower the RAM control signal if the input signal has been deactivated. ctrlOut_o <= LO; elsif prevCtrlIn_v = LO then -- Raise the RAM control signal upon a rising edge of the input control signal. ctrlOut_o <= HI; elsif opBegun_i = HI or doneIn_i = HI then -- Lower the RAM control signal once the RAM has begun or completed the R/W operation. ctrlOut_o <= LO; end if; prevCtrlIn_v := CtrlIn_s; -- Store the previous value of the input control signal. end if; end process; -- Inform the HostIoToRamCore when the memory operation is done. Latch the done signal -- from the RAM until the HostIoToRamCore sees it and lowers its control signal. -- Once the control signal is lowered, the RAM will eventually lower its done signal. process(clk_i) begin if rising_edge(clk_i) then if ctrlIn_s = LO then doneOut_o <= LO; elsif doneIn_i = HI then doneOut_o <= HI; end if; end if; end process; end architecture; --************************************************************************************************** -- This module combines the HostIoToRamCore with two RamCtrlSync modules for the R/W control -- signals to form a complete interface between the JTAG port and a memory device. --************************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use work.CommonPckg.all; use work.SyncToClockPckg.all; use work.HostIoPckg.all; entity HostIoToRam is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. ADDR_INC : integer := 1; -- Add to address after each memory R/W operation. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false; -- If true, include BscanToHostIo module in this module. SYNC_G : boolean := true -- If true, sync this module with the memory clock domain. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- true when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the memory. tdo_o : out std_logic; -- Bit from the memory to the host. -- Interface to the memory. clk_i : in std_logic := LO; -- Clock from FPGA application logic. addr_o : out std_logic_vector; -- Address to memory. wr_o : out std_logic; -- Write data to memory when high. dataFromHost_o : out std_logic_vector; -- Data written to memory. rd_o : out std_logic; -- Read data from memory when high. dataToHost_i : in std_logic_vector; -- Data read from memory. opBegun_i : in std_logic := HI; -- High when memory read/write operation has begun. done_i : in std_logic := HI -- High when memory read/write operation is done. ); end entity; architecture arch of HostIoToRam is -- Internal memory signals. signal wr_s : std_logic; signal rd_s : std_logic; signal wrDone_s : std_logic; signal rdDone_s : std_logic; signal rwDone_s : std_logic; -- Internal JTAG signals. signal inShiftDr_s : std_logic; signal drck_s : std_logic; signal tdi_s : std_logic; signal tdo_s : std_logic; begin -- If you're only interfacing the JTAG port to a single module, then the -- SIMPLE_G parameter lets you build the JTAG interface right into this interface -- and connect it to the internal JTAG signals. USimple : if SIMPLE_G = true generate begin UBscanHostIo : BscanToHostIo generic map( FPGA_DEVICE_G => FPGA_DEVICE_G, TAP_USER_INSTR_G => TAP_USER_INSTR_G ) port map( inShiftDr_o => inShiftDr_s, drck_o => drck_s, tdi_o => tdi_s, tdo_i => tdo_s ); end generate; -- If you're interfacing several modules to the JTAG port, then you'll be using -- an external JTAG module. So just connect the I/O ports to the internal -- JTAG signals. UComplex : if SIMPLE_G = false generate begin inShiftDr_s <= inShiftDr_i; drck_s <= drck_i; tdi_s <= tdi_i; tdo_o <= tdo_s; end generate; -- Connect the HostIoToRamCore to the internal JTAG and memory signals. UHostIoToRamCore : HostIoToRamCore generic map ( ID_G => ID_G, PYLD_CNTR_LENGTH_G => PYLD_CNTR_LENGTH_G, ADDR_INC => ADDR_INC ) port map( reset_i => reset_i, inShiftDr_i => inShiftDr_s, drck_i => drck_s, tdi_i => tdi_s, tdo_o => tdo_s, addr_o => addr_o, wr_o => wr_s, dataFromHost_o => dataFromHost_o, rd_o => rd_s, dataToHost_i => dataToHost_i, rwDone_i => rwDone_s ); -- Synchronize the JTAG interface to the memory clock domain. USync : if SYNC_G = true generate begin UWrRamCtrlSync : RamCtrlSync port map ( drck_i => drck_s, clk_i => clk_i, ctrlIn_i => wr_s, ctrlOut_o => wr_o, opBegun_i => opBegun_i, doneIn_i => done_i, doneOut_o => wrDone_s ); URdRamCtrlSync : RamCtrlSync port map ( drck_i => drck_s, clk_i => clk_i, ctrlIn_i => rd_s, ctrlOut_o => rd_o, opBegun_i => opBegun_i, doneIn_i => done_i, doneOut_o => rdDone_s ); -- Only one read or write memory operation can be in-process at a time, -- so OR their done signals together to create a unified -- "memory operation done" signal. rwDone_s <= rdDone_s or wrDone_s; end generate; -- Don't synchronize the JTAG interface to the memory clock domain. UUnsync : if SYNC_G = false generate begin rwDone_s <= done_i; rd_o <= rd_s; wr_o <= wr_s; end generate; end architecture; --************************************************************************************************** -- This module interfaces with BscanToHostIo to send/receive test vectors to/from a device-under-test (DUT). -- -- Write operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a write operation is activated by the opcode in the first two bits in the payload. -- This module then captures N bits serially from TDI and outputs them in parallel -- onto the inputs of the DUT. A clock pulse is also generated which can be used to clock -- the DUT if desired. -- -- | Header reception | Payload bits | One clock cycle | -- TDI: | ID | # of payload bits | Opcode | b1 b2 b3 b4 b5 ... bN | -- TDO: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| -- DUT INP: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| b1b2b3b4...bN | -- DUT clk: |____________________________________________________________________|^^^^^^^^|____ -- -- Read operations: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a read operation is activated by the opcode in the first two bits in the payload. -- This module captures all the outputs from the DUT in parallel and then shifts them -- back to the host on TDO. -- -- | Header reception | Payload bits | One clock cycle | DUT output bits | -- TDI: | ID | # of payload bits | Opcode |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| -- TDO: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| b1 b2 b3 b4 ... bN | -- DUT OUTP: | b1b2b3b4...bN | -- -- Parameter query operation: -- Once the HostIoHdrScanner module extracts the ID and number of payload bits, -- a parameter query operation is activated by the opcode in the first two bits in the payload. -- This module then places the number of DUT inputs and outputs into a register and shifts it -- serially back to the host. -- -- | Header reception | Payload bits | Parameter data goes back to host | -- TDI: | ID | # of payload bits | Opcode |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| -- TDO: |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| # DUT inputs | # DUT outputs | --************************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; use work.CommonPckg.all; use work.HostIoPckg.all; entity HostIoToDut is generic ( ID_G : std_logic_vector := "11111111"; -- The ID this module responds to. PYLD_CNTR_LENGTH_G : natural := 32; -- Length of payload bit counter. FPGA_DEVICE_G : FpgaDevice_t := SPARTAN6; -- FPGA device type. TAP_USER_INSTR_G : TapUserInstr_t := USER1; -- USER instruction this module responds to. SIMPLE_G : boolean := false -- If true, include BscanToHostIo module in this module. ); port ( reset_i : in std_logic := LO; -- Active-high reset signal. -- Interface to BscanHostIo. inShiftDr_i : in std_logic := LO; -- True when USER JTAG instruction is active and the TAP FSM is in the Shift-DR state. drck_i : in std_logic := LO; -- Bit clock. TDI clocked in on rising edge, TDO sampled on falling edge. tdi_i : in std_logic := LO; -- Bit from the host to the DUT. tdo_o : out std_logic; -- Bit from the DUT to the host. -- Interface to DUT. clkToDut_o : out std_logic; -- Rising edge clock signals arrival of vector to DUT. vectorFromDut_i : in std_logic_vector; -- Gather inputs to send back to host thru this bus. vectorToDut_o : out std_logic_vector -- Output test vector from the host to DUT thru this bus. ); end entity; architecture arch of HostIoToDut is signal active_s : std_logic; -- True when the module is activated by a matching ID. signal opcode_r : std_logic_vector(NOP_OPCODE_C'range); -- Stores opcode received via JTAG. signal opcodeRcvd_r : std_logic; -- True once opcode is received. constant PARAM_SIZE_C : natural := 16; constant SHIFT_REG_SIZE_C : natural := IntMax(IntMax(PARAM_SIZE_C, vectorFromDut_i'length), vectorToDut_o'length); signal shiftReg_r : std_logic_vector(SHIFT_REG_SIZE_C-1 downto 0); -- Stores DUT input & output bits. signal bitCntr_r : natural range 0 to SHIFT_REG_SIZE_C; signal activateClk_r : std_logic; -- Internal JTAG signals. signal inShiftDr_s : std_logic; signal drck_s : std_logic; signal tdi_s : std_logic; signal tdo_s : std_logic; begin -- If you're only interfacing the JTAG port to a single module, then the -- SIMPLE_G parameter lets you build the JTAG interface right into this interface -- and connect it to the internal JTAG signals. USimple : if SIMPLE_G = true generate begin UBscanHostIo : BscanToHostIo generic map( FPGA_DEVICE_G => FPGA_DEVICE_G, TAP_USER_INSTR_G => TAP_USER_INSTR_G ) port map( inShiftDr_o => inShiftDr_s, drck_o => drck_s, tdi_o => tdi_s, tdo_i => tdo_s ); end generate; -- If you're interfacing several modules to the JTAG port, then you'll be using -- an external JTAG module. So just connect the I/O ports to the internal -- JTAG signals. UComplex : if SIMPLE_G = false generate begin inShiftDr_s <= inShiftDr_i; drck_s <= drck_i; tdi_s <= tdi_i; tdo_o <= tdo_s; end generate; -- Scan the bits from the host looking for an instruction header. UHdrScanner : HostIoHdrScanner generic map ( ID_G => ID_G, PYLD_CNTR_LENGTH_G => PYLD_CNTR_LENGTH_G ) port map ( -- Interface to BSCAN primitive. inShiftDr_i => inShiftDr_s, drck_i => drck_s, tdi_i => tdi_s, -- Interface to DUT. active_o => active_s ); -- Process the instruction bits as they arrive from the host. process(drck_s) begin if rising_edge(drck_s) then activateClk_r <= LO; -- By default, keep clock to DUT inactive. -- Keep processing as long as this module is activated. if active_s = YES and reset_i = LO then -- First, get the opcode from the host. if opcodeRcvd_r = NO then opcode_r <= tdi_s & opcode_r(opcode_r'high downto 1); opcodeRcvd_r <= opcode_r(0); -- Opcode complete once LSB is set. -- Next, process the received opcode. else case opcode_r is when SIZE_OPCODE_C => -- Return DUT input and output-width parameters. if bitCntr_r = 0 then -- Load the I/O parameters into the host shift register. shiftReg_r(PARAM_SIZE_C-1 downto 0) <= CONV_STD_LOGIC_VECTOR(vectorFromDut_i'length, PARAM_SIZE_C/2) & CONV_STD_LOGIC_VECTOR(vectorToDut_o'length, PARAM_SIZE_C/2); bitCntr_r <= PARAM_SIZE_C; -- Set the number of bits to send. else -- Shift next bit of I/O parameters to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. end if; when WRITE_OPCODE_C => -- Output a test vector to the DUT. case vectorToDut_o'length is when 0 => -- No inputs to the DUT, so just pulse the clock. activateClk_r <= HI; when 1 => -- Only one input to DUT, so drive it directly from the TDI pin. vectorToDut_o(vectorToDut_o'low) <= tdi_s; activateClk_r <= HI; when others => if shiftReg_r(0) = NO then -- Shifting in data from host before applying it to the DUT. shiftReg_r(vectorToDut_o'length-1 downto 0) <= tdi_s & shiftReg_r(vectorToDut_o'length-1 downto 1); else -- Vector from host received, now apply it to the DUT. vectorToDut_o <= tdi_s & shiftReg_r(vectorToDut_o'length-1 downto 1); -- Output test vector to DUT. activateClk_r <= HI; -- Pulse vector clock for one cycle after vector is received. -- Clear shift register so it can receive another vector from the host. shiftReg_r <= (others => ZERO); -- Clear all shift register bits and ... shiftReg_r(vectorToDut_o'length-1) <= HI; -- ... set MSbit so we can tell when all bits are received. end if; end case; when READ_OPCODE_C => -- Get results of a test vector from the DUT. if bitCntr_r /= 0 then -- Shifting DUT outputs to the host. shiftReg_r <= ZERO & shiftReg_r(shiftReg_r'high downto 1); -- Shift register contents. bitCntr_r <= bitCntr_r - 1; -- One more bit has been sent to the host. else -- Load the DUT output bits into the shift register. shiftReg_r(vectorFromDut_i'length-1 downto 0) <= vectorFromDut_i; -- Load the DUT outputs into the host shift register. bitCntr_r <= vectorFromDut_i'length - 1; -- Set the number of bits to send. end if; -- Default case is NOP. when others => null; end case; end if; else -- Reset everything when this module is not selected or is reset. opcode_r <= (others => ZERO); -- Clear all opcode shift register bits and ... opcode_r(opcode_r'high) <= ONE; -- ... set MSbit so we can tell when a complete opcode is received. opcodeRcvd_r <= NO; shiftReg_r <= (others => ZERO); -- Clear all shift register bits and ... if vectorToDut_o'length > 0 then shiftReg_r(vectorToDut_o'length-1) <= ONE; -- ... set MSbit so we can tell when all bits are received. end if; bitCntr_r <= 0; end if; end if; end process; -- The inputs to the DUT are changed and the clock-enable signal is set on the rising edge of the DRCK. -- The following statement generates a rising clock edge to the DUT when DRCK goes low. This gives -- the inputs to the DUT time to settle. clkToDut_o <= not drck_s when activateClk_r = HI else LO; -- Force output low if this module has not been selected. -- This allows the bit outputs of multiple modules to be OR'ed together -- and sent to the TDO input of the BSCAN primitive. tdo_s <= shiftReg_r(0) when active_s = YES else LO; end architecture;

<reponame>chandanpalai/VHDL-example-codes library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.abc.all; entity tri is port ( I : in std_logic_vector(m-1 downto 0); -- input En : in std_logic; -- input Y : out std_logic_vector(m-1 downto 0)); -- output end entity tri; architecture tri_arc of tri is begin -- architecture tri_arc Y<= I when En='0' else (others=>'Z'); end architecture tri_arc;

<gh_stars>0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY HA_DF IS PORT ( a, b : IN std_logic; sum, cout : OUT std_logic); END ENTITY; ARCHITECTURE dataflow OF HA_DF IS BEGIN sum <= a XOR b; cout <= a AND b; END ARCHITECTURE;

<reponame>Elthra/patmos --------------------------------------------------------------------- ---- ---- ---- FPU ---- ---- Floating Point Unit (Double precision) ---- ---- ---- ---- Author: <NAME> ---- ---- <EMAIL> ---- ---- ---- --------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2009 <NAME> ---- ---- <EMAIL> ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer.---- ---- ---- ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ---- POSSIBILITY OF SUCH DAMAGE. ---- ---- ---- --------------------------------------------------------------------- library ieee; use work.fpupack.all; use work.comppack.all; use ieee.std_logic_misc.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; entity fpu_double_tb is end fpu_double_tb; architecture TB_ARCHITECTURE of fpu_double_tb is component fpu_double port( clk : in std_logic; rst : in std_logic; enable : in std_logic; rmode : in std_logic_vector(1 downto 0); fpu_op : in std_logic_vector(2 downto 0); opa : in std_logic_vector(63 downto 0); opb : in std_logic_vector(63 downto 0); out_fp : out std_logic_vector(63 downto 0); ready : out std_logic; underflow : out std_logic; overflow : out std_logic; inexact : out std_logic; exception : out std_logic; invalid : out std_logic ); end component; signal clk : std_logic; signal rst : std_logic; signal enable : std_logic; signal rmode : std_logic_vector(1 downto 0); signal fpu_op : std_logic_vector(2 downto 0); signal opa : std_logic_vector(63 downto 0); signal opb : std_logic_vector(63 downto 0); signal out_fp : std_logic_vector(63 downto 0); signal ready : std_logic; signal underflow : std_logic; signal overflow : std_logic; signal inexact : std_logic; signal exception : std_logic; signal invalid : std_logic; signal END_SIM: BOOLEAN:=FALSE; signal out_fp1 : std_logic_vector(63 downto 0); begin out_fp1 <= out_fp; UUT : fpu_double port map ( clk => clk, rst => rst, enable => enable, rmode => rmode, fpu_op => fpu_op, opa => opa, opb => opb, out_fp => out_fp, ready => ready, underflow => underflow, overflow => overflow, inexact => inexact, exception => exception, invalid => invalid ); STIMULUS: process begin rst <= '1'; wait for 20 ns; rst <= '0'; --inputA:4.0000000000e+000 --inputB:-4.0000000000e+000 enable <= '1'; opa <= "0100000000010000000000000000000000000000000000000000000000000000"; opb <= "1100000000010000000000000000000000000000000000000000000000000000"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:0.000000000000000e+000 -- out_fp = 0000000000000000 --inputA:3.0000000000e-312 --inputB:1.0000000000e-025 enable <= '1'; opa <= "0000000000000000000000001000110101100000010101111101110111110010"; opb <= "0011101010111110111100101101000011110101110110100111110111011001"; fpu_op <= "011"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.000000000000337e-287 -- out_fp = 047245C02F8B68C5 --inputA:4.0000000000e-304 --inputB:2.0000000000e-007 enable <= '1'; opa <= "0000000011110001100011100011101110011011001101110100000101101001"; opb <= "0011111010001010110101111111001010011010101111001010111101001000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:8.000000000000074e-311 -- out_fp = 00000EBA09271E89 --inputA:3.4445600000e+002 --inputB:3.4445599000e+002 enable <= '1'; opa <= "0100000001110101100001110100101111000110101001111110111110011110"; opb <= "0100000001110101100001110100101110111100001010111001010011011001"; fpu_op <= "001"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.000000003159585e-005 -- out_fp = 3EE4F8B58A000000 --inputA:-8.8899000000e+002 --inputB:7.8898020000e+002 enable <= '1'; opa <= "1100000010001011110001111110101110000101000111101011100001010010"; opb <= "0100000010001000101001111101011101110011000110001111110001010000"; fpu_op <= "000"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.000098000000000e+002 -- out_fp = C05900A0902DE010 --inputA:4.5600000000e+002 --inputB:2.3700000000e+001 enable <= '1'; opa <= "0100000001111100100000000000000000000000000000000000000000000000"; opb <= "0100000000110111101100110011001100110011001100110011001100110011"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.924050632911392e+001 -- out_fp = 40333D91D2A2067B --inputA:4.9990000000e+003 --inputB:0.0000000000e+000 enable <= '1'; opa <= "0100000010110011100001110000000000000000000000000000000000000000"; opb <= "0000000000000000000000000000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:0.000000000000000e+000 -- out_fp = 0000000000000000 --inputA:-9.8883300000e+005 --inputB:4.4444440000e+006 enable <= '1'; opa <= "1100000100101110001011010100001000000000000000000000000000000000"; opb <= "0100000101010000111101000100011100000000000000000000000000000000"; fpu_op <= "001"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-5.433277000000000e+006 -- out_fp = C154B9EF40000000 --inputA:-4.8000000000e-311 --inputB:4.0000000000e-050 enable <= '1'; opa <= "1000000000000000000010001101011000000101011111011101111100011111"; opb <= "0011010110101101111011100111101001001010110101001011100000011111"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.200000000000011e-261 -- out_fp = 89C2E4AE4EAE705E --inputA:1.9500000000e-308 --inputB:1.8800000000e-308 enable <= '1'; opa <= "0000000000001110000001011010001000110110111111110101001011001101"; opb <= "0000000000001101100001001100011001100110111010010000011110011111"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.830000000000000e-308 -- out_fp = 001B8A689DE85A6C --inputA:-3.0000000000e-309 --inputB:9.0000000000e+100 enable <= '1'; opa <= "1000000000000010001010000100000001010111001110101111100100001100"; opb <= "0101010011100100100100101110001011001010010001110101101111101101"; fpu_op <= "010"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-2.700000000000001e-208 -- out_fp = 94D630F25FC26702 --inputA:3.0000000000e-308 --inputB:2.9900000000e-308 enable <= '1'; opa <= "0000000000010101100100101000001101101000010011011011101001110111"; opb <= "0000000000010101100000000001101011011100110111001101010001001011"; fpu_op <= "001"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.000000000000046e-310 -- out_fp = 000012688B70E62C --inputA:-9.0000000000e-300 --inputB:5.0000000000e+100 enable <= '1'; opa <= "1000000111011000000110111110001110111011010110000001000111000100"; opb <= "0101010011010110110111000001100001101110111110011111010001011100"; fpu_op <= "011"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-4.940656458412465e-324 -- out_fp = 8000000000000001 --inputA:4.0000000000e+100 --inputB:3.0000000000e-090 enable <= '1'; opa <= "0101010011010010010010011010110100100101100101001100001101111101"; opb <= "0010110101011000011100011100011001000110111001011001010110100111"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.200000000000000e+011 -- out_fp = 423BF08EB0000001 --inputA:-9.9000000000e-002 --inputB:4.0220000000e+001 enable <= '1'; opa <= "1011111110111001010110000001000001100010010011011101001011110010"; opb <= "0100000001000100000111000010100011110101110000101000111101011100"; fpu_op <= "000"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.012100000000000e+001 -- out_fp = 40440F7CED916872 --inputA:9.0770000000e+001 --inputB:-2.0330000000e+001 enable <= '1'; opa <= "0100000001010110101100010100011110101110000101000111101011100001"; opb <= "1100000000110100010101000111101011100001010001111010111000010100"; fpu_op <= "000"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:7.044000000000000e+001 -- out_fp = 40519C28F5C28F5C --inputA:4.9077000000e+002 --inputB:-3.4434000000e+002 enable <= '1'; opa <= "0100000001111110101011000101000111101011100001010001111010111000"; opb <= "1100000001110101100001010111000010100011110101110000101000111101"; fpu_op <= "001"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:8.351100000000000e+002 -- out_fp = 408A18E147AE147B --inputA:9.0000000000e+034 --inputB:2.7700000000e+000 enable <= '1'; opa <= "0100011100110001010101010101011110110100000110011100010111000010"; opb <= "0100000000000110001010001111010111000010100011110101110000101001"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.249097472924188e+034 -- out_fp = 471907B705EBEABE --inputA:3.9999999989e-315 --inputB:1.0000000000e-002 enable <= '1'; opa <= "0000000000000000000000000000000000110000010000011010011100110101"; opb <= "0011111110000100011110101110000101000111101011100001010001111011"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.000000428704504e-317 -- out_fp = 00000000007B895B --inputA:-9.0000000000e+003 --inputB:8.0000000000e+003 enable <= '1'; opa <= "1100000011000001100101000000000000000000000000000000000000000000"; opb <= "0100000010111111010000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.125000000000000e+000 -- out_fp = BFF2000000000000 --inputA:9.8440000000e+003 --inputB:0.0000000000e+000 enable <= '1'; opa <= "0100000011000011001110100000000000000000000000000000000000000000"; opb <= "0000000000000000000000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.#INF00000000000e+000 -- out_fp = 7FF0000000000000 --inputA:4.4440000000e+002 --inputB:-8.8800000000e+002 enable <= '1'; opa <= "0100000001111011110001100110011001100110011001100110011001100110"; opb <= "1100000010001011110000000000000000000000000000000000000000000000"; fpu_op <= "001"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.332400000000000e+003 -- out_fp = 4094D1999999999A --inputA:3.0000000000e-309 --inputB:3.0000000000e+080 enable <= '1'; opa <= "0000000000000010001010000100000001010111001110101111100100001100"; opb <= "0101000010100100001111011011001101111101011101001011110010000111"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:0.000000000000000e+000 -- out_fp = 0000000000000000 --inputA:4.9900000000e+002 --inputB:-3.3000000000e-003 enable <= '1'; opa <= "0100000001111111001100000000000000000000000000000000000000000000"; opb <= "1011111101101011000010001001101000000010011101010010010101000110"; fpu_op <= "010"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-1.646700000000000e+000 -- out_fp = BFFA58E219652BD4 --inputA:9.0000000000e+034 --inputB:4.0000000000e+023 enable <= '1'; opa <= "0100011100110001010101010101011110110100000110011100010111000010"; opb <= "0100010011010101001011010000001011000111111000010100101011110110"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.000000000040000e+034 -- out_fp = 47315557B41A1A76 --inputA:4.0000000000e+080 --inputB:3.0000000000e-002 enable <= '1'; opa <= "0101000010101010111111001110111101010001111100001111101101011111"; opb <= "0011111110011110101110000101000111101011100001010001111010111000"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.000000000000001e+080 -- out_fp = 50AAFCEF51F0FB60 --inputA:-5.4770000000e+000 --inputB:-8.9990000000e+000 enable <= '1'; opa <= "1100000000010101111010000111001010110000001000001100010010011100"; opb <= "1100000000100001111111110111110011101101100100010110100001110011"; fpu_op <= "011"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:6.086231803533726e-001 -- out_fp = 3FE379D751E6915E --inputA:-7.7000000000e+001 --inputB:-8.8400000000e+001 enable <= '1'; opa <= "1100000001010011010000000000000000000000000000000000000000000000"; opb <= "1100000001010110000110011001100110011001100110011001100110011010"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:6.806800000000001e+003 -- out_fp = 40BA96CCCCCCCCCE --inputA:4.0000000000e+009 --inputB:3.0000000000e+008 enable <= '1'; opa <= "0100000111101101110011010110010100000000000000000000000000000000"; opb <= "0100000110110001111000011010001100000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.333333333333333e+001 -- out_fp = 402AAAAAAAAAAAAB --inputA:9.0000000000e-311 --inputB:8.0000000000e-311 enable <= '1'; opa <= "0000000000000000000100001001000101001010010011000000001001011010"; opb <= "0000000000000000000011101011101000001001001001110001111010001001"; fpu_op <= "000"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.700000000000010e-310 -- out_fp = 00001F4B537320E3 --inputA:1.9999777344e-320 --inputB:5.0000000000e+099 enable <= '1'; opa <= "0000000000000000000000000000000000000000000000000000111111010000"; opb <= "0101010010100010010010011010110100100101100101001100001101111101"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.999888671826831e-221 -- out_fp = 124212D01E240533 --inputA:4.4444000000e+004 --inputB:3.3000000000e+001 enable <= '1'; opa <= "0100000011100101101100111000000000000000000000000000000000000000"; opb <= "0100000001000000100000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.346787878787879e+003 -- out_fp = 40950B26C9B26C9B --inputA:9.7730000000e+000 --inputB:9.7720000000e+000 enable <= '1'; opa <= "0100000000100011100010111100011010100111111011111001110110110010"; opb <= "0100000000100011100010110100001110010101100000010000011000100101"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.000102333196889e+000 -- out_fp = 3FF0006B4DDBBE31 --inputA:8.3345700000e+003 --inputB:1.0000000000e+000 enable <= '1'; opa <= "0100000011000000010001110100100011110101110000101000111101011100"; opb <= "0011111111110000000000000000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:8.334570000000000e+003 -- out_fp = 40C04748F5C28F5C --inputA:-1.0000000000e+000 --inputB:5.8990000000e+003 enable <= '1'; opa <= "1011111111110000000000000000000000000000000000000000000000000000"; opb <= "0100000010110111000010110000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-5.899000000000000e+003 -- out_fp = C0B70B0000000000 --inputA:6.1000000000e+000 --inputB:-6.0990000000e+000 enable <= '1'; opa <= "0100000000011000011001100110011001100110011001100110011001100110"; opb <= "1100000000011000011001010110000001000001100010010011011101001100"; fpu_op <= "000"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.999999999994458e-004 -- out_fp = 3F50624DD2F1A000 --inputA:3.0000000000e-300 --inputB:3.0000000000e-015 enable <= '1'; opa <= "0000000111000000000100101001011111010010001110101011011010000011"; opb <= "0011110011101011000001011000011101101110010110110000000100100000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.000000001157124e-315 -- out_fp = 000000006C93B838 --inputA:-9.0000000000e+088 --inputB:4.0000000000e+084 enable <= '1'; opa <= "1101001001100110100111110000000010010101111101001101000000000000"; opb <= "0101000110000000011110001110000100010001110000110101010101101101"; fpu_op <= "000"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-8.999600000000000e+088 -- out_fp = D2669EBEB27088F3 --inputA:6.6210000000e+001 --inputB:6.9892000000e+001 enable <= '1'; opa <= "0100000001010000100011010111000010100011110101110000101000111101"; opb <= "0100000001010001011110010001011010000111001010110000001000001100"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:9.473187203113375e-001 -- out_fp = 3FEE506F59540645 --inputA:-5.0000000000e-309 --inputB:4.0000000000e-310 enable <= '1'; opa <= "1000000000000011100110000110101100111100000011001111010001101001"; opb <= "0000000000000000010010011010001000101101110000111001100010101100"; fpu_op <= "000"; rmode <= "11"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-4.600000000000001e-309 -- out_fp = 80034EC90E495BBD --inputA:8.8000000000e+001 --inputB:0.0000000000e+000 enable <= '1'; opa <= "0100000001010110000000000000000000000000000000000000000000000000"; opb <= "0000000000000000000000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.#INF00000000000e+000 -- out_fp = 7FEFFFFFFFFFFFFF --inputA:4.5570000000e+002 --inputB:3.4229100000e+003 enable <= '1'; opa <= "0100000001111100011110110011001100110011001100110011001100110011"; opb <= "0100000010101010101111011101000111101011100001010001111010111000"; fpu_op <= "000"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.878610000000000e+003 -- out_fp = 40AE4D3851EB851E --inputA:9.9440000000e+003 --inputB:2.3000000000e+001 enable <= '1'; opa <= "0100000011000011011011000000000000000000000000000000000000000000"; opb <= "0100000000110111000000000000000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.323478260869565e+002 -- out_fp = 407B0590B21642C8 --inputA:-9.0054400000e+005 --inputB:-3.4445500000e+005 enable <= '1'; opa <= "1100000100101011011110111000000000000000000000000000000000000000"; opb <= "1100000100010101000001100001110000000000000000000000000000000000"; fpu_op <= "001"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:-5.560890000000000e+005 -- out_fp = C120F87200000000 --inputA:5.5500000000e-002 --inputB:3.2444400000e+005 enable <= '1'; opa <= "0011111110101100011010100111111011111001110110110010001011010001"; opb <= "0100000100010011110011010111000000000000000000000000000000000000"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.710618781669564e-007 -- out_fp = 3E86F5A431628F6D --inputA:1.2330000000e+000 --inputB:1.5666600000e+000 enable <= '1'; opa <= "0011111111110011101110100101111000110101001111110111110011101110"; opb <= "0011111111111001000100010000101000010011011111110011100011000101"; fpu_op <= "010"; rmode <= "10"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:1.931691780000000e+000 -- out_fp = 3FFEE835A3D0D51B --inputA:9.7770000000e-001 --inputB:3.0000000000e+099 enable <= '1'; opa <= "0011111111101111010010010101000110000010101010011001001100001100"; opb <= "0101010010010101111100100000001011111001111001011011011101100011"; fpu_op <= "011"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:3.259000000000000e-100 -- out_fp = 2B46CF7665DCED50 --inputA:4.4000000000e+007 --inputB:6.0000000000e+002 enable <= '1'; opa <= "0100000110000100111110110001100000000000000000000000000000000000"; opb <= "0100000010000010110000000000000000000000000000000000000000000000"; fpu_op <= "010"; rmode <= "00"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:2.640000000000000e+010 -- out_fp = 4218964020000000 --inputA:3.9800000000e+000 --inputB:3.7700000000e+000 enable <= '1'; opa <= "0100000000001111110101110000101000111101011100001010001111010111"; opb <= "0100000000001110001010001111010111000010100011110101110000101001"; fpu_op <= "000"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:7.750000000000000e+000 -- out_fp = 401F000000000000 --inputA:8.0400000000e+000 --inputB:8.0395700000e+000 enable <= '1'; opa <= "0100000000100000000101000111101011100001010001111010111000010100"; opb <= "0100000000100000000101000100001010000100110111111100111000110001"; fpu_op <= "001"; rmode <= "01"; wait for 20ns; enable <= '0'; wait for 800 ns; --Output:4.299999999997084e-004 -- out_fp = 3F3C2E33EFF18000 END_SIM <= TRUE; wait; end process; CLOCK_clk : process begin if END_SIM = FALSE then clk <= '0'; wait for 5 ns; else wait; end if; if END_SIM = FALSE then clk <= '1'; wait for 5 ns; else wait; end if; end process; end TB_ARCHITECTURE; configuration TESTBENCH_FOR_fpu_double of fpu_double_tb is for TB_ARCHITECTURE for UUT : fpu_double use entity work.fpu_double(rtl); end for; end for; end TESTBENCH_FOR_fpu_double;

<gh_stars>0 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:50:52 10/27/2015 -- Design Name: -- Module Name: Shifter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Shifter is Port ( Rst : in STD_LOGIC; Clk : in STD_LOGIC; DataOut : out STD_LOGIC_VECTOR (7 downto 0)); end Shifter; architecture Behavioral of Shifter is signal Reg : STD_LOGIC_VECTOR (7 downto 0); begin process(Clk,Reg) begin if (rising_edge(Clk)) then if (Rst = '1') then Reg <= (others => '0'); else Reg <= not Reg(0) & Reg (7 downto 1); end if; end if; DataOut <= Reg; end process; end Behavioral;

function findMax( a ) dim num dim max max = 0 for each num in a if num > max then max = num next findMax = max end function function findMin( a ) dim num dim min min = 0 for each num in a if num < min then min = num next findMin = min end function 'the function returns the sorted array, but the fact is that VBScript passes the array by reference anyway function countingSort( a ) dim count() dim min, max min = findMin(a) max = findMax(a) redim count( max - min + 1 ) dim i dim z for i = 0 to ubound( a ) count( a(i) - min ) = count( a( i ) - min ) + 1 next z = 0 for i = min to max while count( i - min) > 0 a(z) = i z = z + 1 count( i - min ) = count( i - min ) - 1 wend next countingSort = a end function

<filename>admin/wmi/wbem/scripting/samples/general/os.vbs for each os in GetObject("winmgmts:{impersonationLevel=impersonate}!").InstancesOf("Win32_OperatingSystem") WScript.Echo "" WScript.Echo "Version Info:" WScript.Echo "============" WScript.Echo " Version: ", os.Caption, os.Version WScript.Echo " Build: ", os.BuildNumber, os.BuildType WScript.Echo " CSD Version: ", os.CSDVersion WScript.Echo " Serial Number: ", os.SerialNumber WScript.Echo " Manufacturer: ", os.Manufacturer WScript.Echo "" WScript.Echo "Memory Info:" WScript.Echo "===========" WScript.Echo " Free Physical Memory: ", os.FreePhysicalMemory WScript.Echo " Free Space in Paging Files: ", os.FreeSpaceInPagingFiles WScript.Echo " Size Stored in Paging Files: ", os.SizeStoredInPagingFiles WScript.Echo " Free Virtual Memory: ", os.FreeVirtualMemory WScript.Echo " Total Virtual Memory Size: ", os.TotalVirtualMemorySize WScript.Echo " Total Visible Memory Size", os.TotalVisibleMemorySize WScript.Echo "" WScript.Echo "Time Info:" WScript.Echo "=========" WScript.Echo " Current Time Zone: ", os.CurrentTimeZone WScript.Echo " Install Date: ", os.InstallDate WScript.Echo " Last Bootup Time: ", os.LastBootUpTime WScript.Echo " Local Date & Time: ", os.LocalDateTime WScript.Echo "" WScript.Echo "Process Info:" WScript.Echo "============" WScript.Echo " Foreground App Boost: ", os.ForegroundApplicationBoost WScript.Echo " Maximum #Processes: ", os.MaxNumberOfProcesses WScript.Echo " Maximum Memory Size for Processes: ", os.MaxProcessMemorySize WScript.Echo " #Processes: ", os.NumberOfProcesses WScript.Echo "" WScript.Echo "User Info:" WScript.Echo "=========" WScript.Echo "#Users: ", os.NumberOfUsers WScript.Echo "Registered User: ", os.RegisteredUser WScript.Echo "" WScript.Echo "Locale Info:" WScript.Echo "===========" WScript.Echo "Code Set: ", os.CodeSet WScript.Echo "Country Code: ", os.CountryCode WScript.Echo "Locale: ", os.Locale WScript.Echo "" WScript.Echo "System Info:" WScript.Echo "===========" WScript.Echo "Boot Device: ", os.BootDevice WScript.Echo "Name: ", os.CSName WScript.Echo "Status: ", os.Status Wscript.Echo "System Device: ", os.SystemDevice WScript.Echo "System Directory: ", os.SystemDirectory WScript.Echo "Windows Directory: ", os.WindowsDirectory next

<filename>Task/Loops-Break/VBScript/loops-break.vb do a = int( rnd * 20) wscript.stdout.write a if a = 10 then exit do b = int( rnd * 20 ) wscript.echo vbnullstring,b loop dim i for i = 1 to 100000 a = int( rnd * 20) wscript.stdout.write a if a = 10 then exit for b = int( rnd * 20 ) wscript.echo vbnullstring,b next

Function UninstallCab() on error resume next Const PRO_ID = "Windows Support Tools on Desktop" CONST SERVER_ID = "Windows Support Tools" Dim PCHUpdate Dim Item Dim strProductId Set PCHUpdate = CreateObject("HCU.PCHUpdate") if not PCHUpdate is nothing then For Each Item in PCHUpdate.VersionList If Item.ProductId = PRO_ID OR Item.ProductId = SERVER_ID Then strProductId = Item.ProductId Item.Uninstall End If Next Set PCHUpdate = Nothing end if UninstallCab = 1 End Function

<filename>Task/Identity-matrix/VBScript/identity-matrix-1.vb build_matrix(7) Sub build_matrix(n) Dim matrix() ReDim matrix(n-1,n-1) i = 0 'populate the matrix For row = 0 To n-1 For col = 0 To n-1 If col = i Then matrix(row,col) = 1 Else matrix(row,col) = 0 End If Next i = i + 1 Next 'display the matrix For row = 0 To n-1 For col = 0 To n-1 If col < n-1 Then WScript.StdOut.Write matrix(row,col) & " " Else WScript.StdOut.Write matrix(row,col) End If Next WScript.StdOut.WriteLine Next End Sub

Private Function nth_root(y As Double, n As Double) Dim eps As Double: eps = 0.00000000000001 '-- relative accuracy Dim x As Variant: x = 1 Do While True d = (y / x ^ (n - 1) - x) / n x = x + d e = eps * x '-- absolute accuracy If d > -e And d < e Then Exit Do End If Loop Debug.Print y; n; x; y ^ (1 / n) End Function Public Sub main() nth_root 1024, 10 nth_root 27, 3 nth_root 2, 2 nth_root 5642, 125 nth_root 7, 0.5 nth_root 4913, 3 nth_root 8, 3 nth_root 16, 2 nth_root 16, 4 nth_root 125, 3 nth_root 1000000000, 3 nth_root 1000000000, 9 End Sub

<filename>Task/Empty-program/VBA/empty-program.vba Sub Demo() End Sub

<filename>Task/Update-a-configuration-file/VBScript/update-a-configuration-file.vb Set objFSO = CreateObject("Scripting.FileSystemObject") 'Paramater lookups Set objParamLookup = CreateObject("Scripting.Dictionary") With objParamLookup .Add "FAVOURITEFRUIT", "banana" .Add "NEEDSPEELING", "" .Add "SEEDSREMOVED", "" .Add "NUMBEROFBANANAS", "1024" .Add "NUMBEROFSTRAWBERRIES", "62000" End With 'Open the config file for reading. Set objInFile = objFSO.OpenTextFile(objFSO.GetParentFolderName(WScript.ScriptFullName) &_ "\IN_config.txt",1) 'Initialize output. Output = "" Isnumberofstrawberries = False With objInFile Do Until .AtEndOfStream line = .ReadLine If Left(line,1) = "#" Or line = "" Then Output = Output & line & vbCrLf ElseIf Left(line,1) = " " And InStr(line,"#") Then Output = Output & Mid(line,InStr(1,line,"#"),1000) & vbCrLf ElseIf Replace(Replace(line,";","")," ","") <> "" Then If InStr(1,line,"FAVOURITEFRUIT",1) Then Output = Output & "FAVOURITEFRUIT" & " " & objParamLookup.Item("FAVOURITEFRUIT") & vbCrLf ElseIf InStr(1,line,"NEEDSPEELING",1) Then Output = Output & "; " & "NEEDSPEELING" & vbCrLf ElseIf InStr(1,line,"SEEDSREMOVED",1) Then Output = Output & "SEEDSREMOVED" & vbCrLf ElseIf InStr(1,line,"NUMBEROFBANANAS",1) Then Output = Output & "NUMBEROFBANANAS" & " " & objParamLookup.Item("NUMBEROFBANANAS") & vbCrLf ElseIf InStr(1,line,"NUMBEROFSTRAWBERRIES",1) Then Output = Output & "NUMBEROFSTRAWBERRIES" & " " & objParamLookup.Item("NUMBEROFSTRAWBERRIES") & vbCrLf Isnumberofstrawberries = True End If End If Loop If Isnumberofstrawberries = False Then Output = Output & "NUMBEROFSTRAWBERRIES" & " " & objParamLookup.Item("NUMBEROFSTRAWBERRIES") & vbCrLf Isnumberofstrawberries = True End If .Close End With 'Create a new config file. Set objOutFile = objFSO.OpenTextFile(objFSO.GetParentFolderName(WScript.ScriptFullName) &_ "\OUT_config.txt",2,True) With objOutFile .Write Output .Close End With Set objFSO = Nothing Set objParamLookup = Nothing

Function IsDirEmpty(path) IsDirEmpty = False Set objFSO = CreateObject("Scripting.FileSystemObject") Set objFolder = objFSO.GetFolder(path) If objFolder.Files.Count = 0 And objFolder.SubFolders.Count = 0 Then IsDirEmpty = True End If End Function 'Test WScript.StdOut.WriteLine IsDirEmpty("C:\Temp") WScript.StdOut.WriteLine IsDirEmpty("C:\Temp\test")

<reponame>npocmaka/Windows-Server-2003 '//on error resume next intLimit = Null intThreshold = Null set objArgs = wscript.Arguments if objArgs.count < 3 then wscript.echo "Usage createVolumeUserQuota volume domain user [limit threshold]" wscript.quit(1) end if strVolume = Replace(objArgs(0), "\", "\\") strDomain = objArgs(1) strUser = objArgs(2) if objArgs.count > 3 then intLimit = objArgs(3) intThreshold = objArgs(4) end if '// Get the volume strQuery = "select * from Win32_Volume where Name = '" & strVolume & "'" set objSet = GetObject("winmgmts:").ExecQuery(strQuery) for each obj in objSet set Volume = obj exit for next wscript.echo "Volume: " & Volume.Name '// Get the account strQuery = "select * from Win32_Account where Domain = '" & strDomain & "' AND Name = '" & strUser & "'" set objSet = GetObject("winmgmts:").ExecQuery(strQuery) for each obj in objSet set Account = obj exit for next wscript.echo "Domain: " & Account.Domain & " Name: " & Account.Name set VolumeUserQuota = GetObject("winmgmts:Win32_VolumeUserQuota").SpawnInstance_ VolumeUserQuota.Volume = Volume.Path_.RelPath VolumeUserQuota.Account = Account.Path_.RelPath 'VolumeUserQuota.Account = "Win32_Account.Domain='BogusDomain',Name='BogusUser'" if isNull(intLimit) = False Then VolumeUserQuota.Limit = intLimit end if if isNull(intThreshold) = False Then VolumeUserQuota.WarningLimit = intThreshold end if VolumeUserQuota.Put_

'http://rosettacode.org/wiki/Middle_three_digits Function mid3n(n) 'Remove the number's sign. n = CStr(Abs(n)) If Len(n) < 3 Or Len(n) Mod 2 = 0 Then mid3n = "Invalid: Either the length of n < 3 or an even number." ElseIf Round(Len(n)/2) > Len(n)/2 Then mid3n = Mid(n,Round(Len(n)/2)-1,3) Else mid3n = Mid(n,Round(Len(n)/2),3) End If End Function 'Calling the function. arrn = Array(123,12345,1234567,987654321,10001,-10001,-123,-100,100,-12345,_ 1,2,-1,-10,2002,-2002,0) For Each n In arrn WScript.StdOut.Write n & ": " & mid3n(n) WScript.StdOut.WriteLine Next

Set objFSO = CreateObject("Scripting.FileSystemObject") Set infile = objFSO.OpenTextFile(objFSO.GetParentFolderName(WScript.ScriptFullName) & "\" &_ "unixdict.txt",1) list = "" length = 0 Do Until inFile.AtEndOfStream line = infile.ReadLine If IsOrdered(line) Then If Len(line) > length Then length = Len(line) list = line & vbCrLf ElseIf Len(line) = length Then list = list & line & vbCrLf End If End If Loop WScript.StdOut.Write list Function IsOrdered(word) IsOrdered = True prev_val = 0 For i = 1 To Len(word) If i = 1 Then prev_val = Asc(Mid(word,i,1)) ElseIf Asc(Mid(word,i,1)) >= prev_val Then prev_val = Asc(Mid(word,i,1)) Else IsOrdered = False Exit For End If Next End Function

<filename>net/unimodem/tools/src/notepad.frm<gh_stars>10-100 VERSION 5.00 Begin VB.Form frmNotePad Caption = "Untitled" ClientHeight = 3990 ClientLeft = 1515 ClientTop = 3315 ClientWidth = 5670 BeginProperty Font Name = "<NAME>" Size = 8.25 Charset = 0 Weight = 700 Underline = 0 'False Italic = 0 'False Strikethrough = 0 'False EndProperty LinkTopic = "Form1" ScaleHeight = 3990 ScaleMode = 0 'User ScaleWidth = 101.07 Begin VB.TextBox Text1 Height = 3975 HideSelection = 0 'False Left = 0 MultiLine = -1 'True ScrollBars = 2 'Vertical TabIndex = 0 Top = 0 Width = 5655 End Begin VB.Menu mnuFile Caption = "&File" Begin VB.Menu mnuFileNew Caption = "&New" End Begin VB.Menu mnuFileOpen Caption = "&Open..." End Begin VB.Menu mnuFileClose Caption = "&Close" End Begin VB.Menu mnuFileSave Caption = "&Save" End Begin VB.Menu mnuFileSaveAs Caption = "Save &As..." End Begin VB.Menu mnuFSep Caption = "-" End Begin VB.Menu mnuFileExit Caption = "E&xit" End Begin VB.Menu mnuRecentFile Caption = "-" Index = 0 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile1" Index = 1 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile2" Index = 2 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile3" Index = 3 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile4" Index = 4 Visible = 0 'False End Begin VB.Menu mnuRecentFile Caption = "RecentFile5" Index = 5 Visible = 0 'False End End Begin VB.Menu mnuEdit Caption = "&Edit" Begin VB.Menu mnuEditCut Caption = "Cu&t" Shortcut = ^X End Begin VB.Menu mnuEditCopy Caption = "&Copy" Shortcut = ^C End Begin VB.Menu mnuEditPaste Caption = "&Paste" Shortcut = ^V End Begin VB.Menu mnuEditDelete Caption = "De&lete" Shortcut = {DEL} End Begin VB.Menu mnuESep1 Caption = "-" End Begin VB.Menu mnuEditSelectAll Caption = "Select &All" End Begin VB.Menu mnuEditTime Caption = "Time/&Date" End End Begin VB.Menu mnuSearch Caption = "&Search" Begin VB.Menu mnuSearchFind Caption = "&Find" End Begin VB.Menu mnuSearchFindNext Caption = "Find &Next" Shortcut = {F3} End End Begin VB.Menu mnuOptions Caption = "&Options" Begin VB.Menu mnuFont Caption = "&Font" Begin VB.Menu mnuFontName Caption = "FontName" Index = 0 End End End End Attribute VB_Name = "frmNotePad" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False '*** Child form for the MDI Notepad sample application *** '********************************************************** Option Explicit Private Sub Form_Load() Dim i As Integer ' Counter variable. ' Assign the name of the first font to a font ' menu entry, then loop through the fonts ' collection, adding them to the menu mnuFontName(0).Caption = Screen.Fonts(0) For i = 1 To Screen.FontCount - 1 Load mnuFontName(i) mnuFontName(0).Caption = Screen.Fonts(i) Next End Sub Private Sub Form_QueryUnload(Cancel As Integer, UnloadMode As Integer) Dim strMsg As String Dim strFilename As String Dim intResponse As Integer ' Check to see if the text has been changed. If FState(Me.Tag).Dirty Then strFilename = Me.Caption strMsg = "The text in [" & strFilename & "] has changed." strMsg = strMsg & vbCrLf strMsg = strMsg & "Do you want to save the changes?" intResponse = MsgBox(strMsg, 51, fMainForm.Caption) Select Case intResponse Case 6 ' User chose Yes. If Left(Me.Caption, 8) = "Untitled" Then ' The file hasn't been saved yet. strFilename = "untitled.txt" ' Get the strFilename, and then call the save procedure, GetstrFilename. strFilename = GetFileName(strFilename) Else ' The form's Caption contains the name of the open file. strFilename = Me.Caption End If ' Call the save procedure. If strFilename = Empty, then ' the user chose Cancel in the Save As dialog box; otherwise, ' save the file. If strFilename <> "" Then SaveFileAs strFilename End If Case 7 ' User chose No. Unload the file. Cancel = False Case 2 ' User chose Cancel. Cancel the unload. Cancel = True End Select End If End Sub Private Sub Form_Resize() ' Expand text box to fill the current child form's internal area. Text1.Height = ScaleHeight Text1.Width = ScaleWidth End Sub Private Sub Form_Unload(Cancel As Integer) ' Show the current form instance as deleted FState(Me.Tag).Deleted = True ' Hide the toolbar edit buttons if no notepad windows exist. If Not AnyPadsLeft() Then fMainForm.imgCutButton.Visible = False fMainForm.imgCopyButton.Visible = False fMainForm.imgPasteButton.Visible = False ' Toggle the public tool state variable gToolsHidden = True ' Call the recent file list procedure GetRecentFiles End If End Sub Private Sub mnuEditCopy_Click() ' Call the copy procedure EditCopyProc End Sub Private Sub mnuEditCut_Click() ' Call the cut procedure EditCutProc End Sub Private Sub mnuEditDelete_Click() ' If the mouse pointer is not at the end of the notepad... If Screen.ActiveControl.SelStart <> Len(Screen.ActiveControl.Text) Then ' If nothing is selected, extend the selection by one. If Screen.ActiveControl.SelLength = 0 Then Screen.ActiveControl.SelLength = 1 ' If the mouse pointer is on a blank line, extend the selection by two. If Asc(Screen.ActiveControl.SelText) = 13 Then Screen.ActiveControl.SelLength = 2 End If End If ' Delete the selected text. Screen.ActiveControl.SelText = "" End If End Sub Private Sub mnuEditPaste_Click() ' Call the paste procedure. EditPasteProc End Sub Private Sub mnuEditSelectAll_Click() ' Use SelStart & SelLength to select the text. fMainForm.ActiveForm.Text1.SelStart = 0 fMainForm.ActiveForm.Text1.SelLength = Len(fMainForm.ActiveForm.Text1.Text) End Sub Private Sub mnuEditTime_Click() ' Insert the current time and date. Text1.SelText = Now End Sub Private Sub mnuFileClose_Click() ' Unload this form. Unload Me End Sub Private Sub mnuFileExit_Click() ' Unloading the MDI form invokes the QueryUnload event ' for each child form, and then the MDI form. ' Setting the Cancel argument to True in any of the ' QueryUnload events cancels the unload. Unload fMainForm End Sub Private Sub mnuFileNew_Click() ' Call the new form procedure FileNew End Sub Private Sub mnuFontName_Click(index As Integer) ' Assign the selected font to the textbox fontname property. Text1.FontName = mnuFontName(index).Caption End Sub Private Sub mnuFileOpen_Click() ' Call the file open procedure. FileOpenProc End Sub Private Sub mnuFileSave_Click() Dim strFilename As String If Left(Me.Caption, 8) = "Untitled" Then ' The file hasn't been saved yet. ' Get the filename, and then call the save procedure, GetFileName. strFilename = GetFileName(strFilename) Else ' The form's Caption contains the name of the open file. strFilename = Me.Caption End If ' Call the save procedure. If Filename = Empty, then ' the user chose Cancel in the Save As dialog box; otherwise, ' save the file. If strFilename <> "" Then SaveFileAs strFilename End If End Sub Private Sub mnuFileSaveAs_Click() Dim strSaveFileName As String Dim strDefaultName As String ' Assign the form caption to the variable. strDefaultName = Me.Caption If Left(Me.Caption, 8) = "Untitled" Then ' The file hasn't been saved yet. ' Get the filename, and then call the save procedure, strSaveFileName. strSaveFileName = GetFileName("Untitled.txt") If strSaveFileName <> "" Then SaveFileAs (strSaveFileName) ' Update the list of recently opened files in the File menu control array. UpdateFileMenu (strSaveFileName) Else ' The form's Caption contains the name of the open file. strSaveFileName = GetFileName(strDefaultName) If strSaveFileName <> "" Then SaveFileAs (strSaveFileName) ' Update the list of recently opened files in the File menu control array. UpdateFileMenu (strSaveFileName) End If End Sub Private Sub mnuOptions_Click() ' Toggle the Checked property to match the .Visible property. ' mnuOptionsToolbar.Checked = fMainForm.picToolbar.Visible End Sub Private Sub mnuOptionsToolbar_Click() ' Call the toolbar procedure, passing a reference ' to this form instance. OptionsToolbarProc Me End Sub Private Sub mnuRecentFile_Click(index As Integer) ' Call the file open procedure, passing a ' reference to the selected file name OpenFile (mnuRecentFile(index).Caption) ' Update the list of recently opened files in the File menu control array. GetRecentFiles End Sub Private Sub mnuSearchFind_Click() ' If there is text in the textbox, assign it to ' the textbox on the Find form, otherwise assign ' the last findtext value. If Me.Text1.SelText <> "" Then frmFind.Text1.Text = Me.Text1.SelText Else frmFind.Text1.Text = gFindString End If ' Set the public variable to start at the beginning. gFirstTime = True ' Set the case checkbox to match the public variable If (gFindCase) Then frmFind.chkCase = 1 End If ' Display the Find form. frmFind.Show vbModal End Sub Private Sub mnuSearchFindNext_Click() ' If the public variable isn't empty, call the ' find procedure, otherwise call the find menu If Len(gFindString) > 0 Then FindIt Else mnuSearchFind_Click End If End Sub Private Sub mnuWindowArrange_Click() ' Arrange the icons for any minimzied child forms. fMainForm.Arrange vbArrangeIcons End Sub Private Sub mnuWindowCascade_Click() ' Cascade the child forms. fMainForm.Arrange vbCascade End Sub Private Sub mnuWindowTile_Click() ' Tile the child forms. fMainForm.Arrange vbTileHorizontal End Sub Private Sub Text1_Change() ' Set the public variable to show that text has changed. FState(Me.Tag).Dirty = True End Sub

110 IF 12 > 11 THEN PRINT "ok1" 120 IF 12 < 11 THEN PRINT "fail1" 130 IF 12 < 11 THEN PRINT "fail2" 140 IF 12 > 11 THEN PRINT "ok2"

<filename>admin/pchealth/upload/client/uploadmanager/unittest/test3_deletealljobs.vbs 'Stop Set obj = CreateObject( "UploadManager.MPCUpload" ) For Each job In obj wscript.echo job.jobID job.Delete Next

<reponame>LaudateCorpus1/RosettaCodeData ' Read a file line by line Sub Main() Dim fInput As String, fOutput As String 'File names Dim sInput As String, sOutput As String 'Lines fInput = "input.txt" fOutput = "output.txt" Open fInput For Input As #1 Open fOutput For Output As #2 While Not EOF(1) Line Input #1, sInput sOutput = Process(sInput) 'do something Print #2, sOutput Wend Close #1 Close #2 End Sub 'Main

VERSION 5.00 Begin VB.Form frmMain BorderStyle = 1 'Fixed Single Caption = "SDK BVT ( wbem 494 : opal > 1035 )" ClientHeight = 3660 ClientLeft = 45 ClientTop = 330 ClientWidth = 6630 Icon = "frmMain.frx":0000 LinkTopic = "Form1" MaxButton = 0 'False ScaleHeight = 3660 ScaleWidth = 6630 StartUpPosition = 3 'Windows Default Begin VB.CommandButton cmdModInfo Caption = "Module &Info >" Height = 375 Left = 1860 TabIndex = 22 Top = 2160 Width = 1335 End Begin VB.Frame fraLoop Caption = "&Looping" Height = 1635 Left = 60 TabIndex = 14 Top = 1980 Width = 1635 Begin VB.OptionButton rdoLoopInf Caption = "Infinite" Height = 195 Left = 180 TabIndex = 23 Top = 540 Width = 1035 End Begin VB.TextBox txtLoop BackColor = &H8000000F& Enabled = 0 'False Height = 285 Left = 240 TabIndex = 18 Top = 1260 Width = 1275 End Begin VB.OptionButton rdoLoopIter Caption = "Iterations" Height = 195 Left = 180 TabIndex = 17 Top = 1020 Width = 1095 End Begin VB.OptionButton rdoLoopMin Caption = "Minutes" Enabled = 0 'False Height = 195 Left = 180 TabIndex = 16 Top = 780 Width = 1035 End Begin VB.OptionButton rdoLoopDis Caption = "Disabled" Height = 195 Left = 180 TabIndex = 15 Top = 300 Value = -1 'True Width = 975 End End Begin VB.CommandButton cmdGo Default = -1 'True Height = 915 Left = 1860 Picture = "frmMain.frx":0442 Style = 1 'Graphical TabIndex = 21 Top = 2640 Width = 1335 End Begin VB.Frame fraModules Caption = "&Modules" Height = 3555 Left = 3360 TabIndex = 19 Top = 60 Width = 3195 Begin VB.ListBox lstModules Height = 3195 IntegralHeight = 0 'False Left = 120 Style = 1 'Checkbox TabIndex = 20 Top = 240 Width = 2955 End End Begin VB.Frame fraConfig Caption = "&Configuration" Height = 1875 Left = 60 TabIndex = 0 Top = 60 Width = 3195 Begin VB.CheckBox chkAuthority Caption = "Null" Height = 195 Left = 960 TabIndex = 12 Top = 1500 Value = 1 'Checked Width = 615 End Begin VB.CheckBox chkPassword Caption = "Null" Height = 195 Left = 960 TabIndex = 9 Top = 1200 Value = 1 'Checked Width = 615 End Begin VB.CheckBox chkUserid Caption = "Null" Height = 195 Left = 960 TabIndex = 6 Top = 900 Value = 1 'Checked Width = 615 End Begin VB.TextBox txtAuthority BackColor = &H8000000F& Enabled = 0 'False Height = 285 Left = 1560 TabIndex = 13 Top = 1440 Width = 1515 End Begin VB.TextBox txtPassword BackColor = &H8000000F& Enabled = 0 'False Height = 285 IMEMode = 3 'DISABLE Left = 1560 PasswordChar = "*" TabIndex = 10 Top = 1140 Width = 1515 End Begin VB.TextBox txtUserid BackColor = &H8000000F& Enabled = 0 'False Height = 285 Left = 1560 TabIndex = 7 Top = 840 Width = 1515 End Begin VB.TextBox txtServer Height = 285 Left = 1560 TabIndex = 2 Top = 240 Width = 1515 End Begin VB.TextBox txtSitecode Height = 285 Left = 1560 MaxLength = 3 TabIndex = 4 Top = 540 Width = 1515 End Begin VB.Label lblAuthority AutoSize = -1 'True Caption = "Authority:" Height = 195 Left = 120 TabIndex = 11 Top = 1500 Width = 660 End Begin VB.Label lblPassword AutoSize = -1 'True Caption = "Password:" Height = 195 Left = 120 TabIndex = 8 Top = 1200 Width = 735 End Begin VB.Label lblUserid AutoSize = -1 'True Caption = "UserID:" Height = 195 Left = 120 TabIndex = 5 Top = 900 Width = 540 End Begin VB.Label lblServer AutoSize = -1 'True Caption = "Provider Machine:" Height = 195 Left = 120 TabIndex = 1 Top = 300 Width = 1290 End Begin VB.Label lblSitecode AutoSize = -1 'True Caption = "Site code:" Height = 195 Left = 120 TabIndex = 3 Top = 600 Width = 720 End End End Attribute VB_Name = "frmMain" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Public canceled As Boolean Private Sub Form_Load() canceled = False InstallModules lstModules.ListIndex = -1 End Sub Private Sub chkAuthority_Click() If chkAuthority.Value = 0 Then txtAuthority.Enabled = True txtAuthority.BackColor = &H80000005 txtAuthority.SetFocus Else txtAuthority.Enabled = False txtAuthority.BackColor = &H8000000F End If End Sub Private Sub chkPassword_Click() If chkPassword.Value = 0 Then txtPassword.Enabled = True txtPassword.BackColor = &H80000005 txtPassword.SetFocus Else txtPassword.Enabled = False txtPassword.BackColor = &H8000000F End If End Sub Private Sub chkUserid_Click() If chkUserid.Value = 0 Then txtUserid.Enabled = True txtUserid.BackColor = &H80000005 txtUserid.SetFocus Else txtUserid.Enabled = False txtUserid.BackColor = &H8000000F End If End Sub Private Sub cmdGo_Click() Open "\bvtlog.txt" For Output As #1 Print #1, "** BVT Started **" & vbCrLf & vbCrLf Close #1 If rdoLoopDis.Value Then frmTest.Run ElseIf rdoLoopInf.Value Then Do frmTest.Run Dim f As New frmPause f.Show 1 If canceled Then canceled = False Exit Do End If Loop ElseIf rdoLoopMin.Value Then ElseIf rdoLoopIter.Value Then Dim i As Integer For i = 1 To val(txtLoop.text) frmTest.Run Dim g As New frmPause g.Show 1 If canceled Then canceled = False Exit For End If Next i End If End Sub Private Sub cmdModInfo_Click() If lstModules.ListIndex >= 0 Then Dim s As String s = Modules(lstModules.List(lstModules.ListIndex)).GetModuleInfo Dim f As New frmObjText f.Caption = "Module info for: " & lstModules.List(lstModules.ListIndex) f.txtMain.text = s f.Show End If End Sub Private Sub InstallModules() Modules.Add New SoftDist, "Software Distribution" Modules.Add New SiteCtrl, "Site Control File" Modules.Add New Methods, "Methods" Modules.Add New Queries, "Queries" Modules.Add New PDF, "Package Definition Files" End Sub Private Sub rdoLoopDis_Click() txtLoop.Enabled = False txtLoop.BackColor = &H8000000F End Sub Private Sub rdoLoopInf_Click() txtLoop.Enabled = False txtLoop.BackColor = &H8000000F End Sub Private Sub rdoLoopIter_Click() txtLoop.Enabled = True txtLoop.BackColor = &H80000005 End Sub Private Sub rdoLoopMin_Click() txtLoop.Enabled = True txtLoop.BackColor = &H80000005 End Sub

<reponame>wtywtykk/STM32Framework_SaltyProject<gh_stars>1-10 Attribute VB_Name = "ModBitOp" Option Explicit Public Declare Function SHL8 Lib "BitOp.dll" (ByVal Val As Byte, ByVal Shift As Long) As Byte Public Declare Function SHR8 Lib "BitOp.dll" (ByVal Val As Byte, ByVal Shift As Long) As Byte Public Declare Function SHL16 Lib "BitOp.dll" (ByVal Val As Integer, ByVal Shift As Long) As Integer Public Declare Function SHR16 Lib "BitOp.dll" (ByVal Val As Integer, ByVal Shift As Long) As Integer Public Declare Function SHL32 Lib "BitOp.dll" (ByVal Val As Long, ByVal Shift As Long) As Long Public Declare Function SHR32 Lib "BitOp.dll" (ByVal Val As Long, ByVal Shift As Long) As Long Public Declare Function GetU16U8 Lib "BitOp.dll" (ByVal Val As Integer, ByVal Index As Long) As Byte Public Declare Function SetU16U8 Lib "BitOp.dll" (ByVal Val16 As Integer, ByVal Val8 As Byte, ByVal Index As Long) As Integer Public Declare Function GetU32U8 Lib "BitOp.dll" (ByVal Val As Long, ByVal Index As Long) As Byte Public Declare Function SetU32U8 Lib "BitOp.dll" (ByVal Val32 As Long, ByVal Val8 As Byte, ByVal Index As Long) As Long Public Declare Function GetU32U16 Lib "BitOp.dll" (ByVal Val As Long, ByVal Index As Long) As Integer Public Declare Function SetU32U16 Lib "BitOp.dll" (ByVal Val32 As Long, ByVal Val16 As Integer, ByVal Index As Long) As Long Public Declare Function SwitchU16Edition Lib "BitOp.dll" (ByVal Val As Integer) As Integer Public Declare Function SwitchU32Edition Lib "BitOp.dll" (ByVal Val As Long) As Long Public Declare Function CheckU8Bit Lib "BitOp.dll" (ByVal Val As Byte, ByVal Index As Long) As Boolean Public Declare Function CheckU16Bit Lib "BitOp.dll" (ByVal Val As Integer, ByVal Index As Long) As Boolean Public Declare Function CheckU32Bit Lib "BitOp.dll" (ByVal Val As Long, ByVal Index As Long) As Boolean Public Declare Function U8Add Lib "BitOp.dll" (ByVal Val1 As Byte, ByVal Val2 As Byte) As Byte Public Declare Function U8Sub Lib "BitOp.dll" (ByVal Val1 As Byte, ByVal Val2 As Byte) As Byte Public Declare Function U8Cmp Lib "BitOp.dll" (ByVal Val1 As Byte, ByVal Val2 As Byte) As Long Public Declare Function U16Add Lib "BitOp.dll" (ByVal Val1 As Integer, ByVal Val2 As Integer) As Integer Public Declare Function U16Sub Lib "BitOp.dll" (ByVal Val1 As Integer, ByVal Val2 As Integer) As Integer Public Declare Function U16Cmp Lib "BitOp.dll" (ByVal Val1 As Integer, ByVal Val2 As Integer) As Long Public Declare Function U32Add Lib "BitOp.dll" (ByVal Val1 As Long, ByVal Val2 As Long) As Long Public Declare Function U32Sub Lib "BitOp.dll" (ByVal Val1 As Long, ByVal Val2 As Long) As Long Public Declare Function U32Cmp Lib "BitOp.dll" (ByVal Val1 As Long, ByVal Val2 As Long) As Long Public Function GetRGB(ByVal Color As Long) As Byte() Dim Result(3) As Byte Result(0) = GetU32U8(Color, 0) 'R Result(1) = GetU32U8(Color, 1) 'G Result(2) = GetU32U8(Color, 2) 'B Result(3) = GetU32U8(Color, 3) 'A GetRGB = Result() End Function

Option Base 1 Private Function norm(q As Variant) As Double norm = Sqr(WorksheetFunction.SumSq(q)) End Function Private Function negative(q) As Variant Dim res(4) As Double For i = 1 To 4 res(i) = -q(i) Next i negative = res End Function Private Function conj(q As Variant) As Variant Dim res(4) As Double res(1) = q(1) For i = 2 To 4 res(i) = -q(i) Next i conj = res End Function Private Function addr(r As Double, q As Variant) As Variant Dim res As Variant res = q res(1) = r + q(1) addr = res End Function Private Function add(q1 As Variant, q2 As Variant) As Variant add = WorksheetFunction.MMult(Array(1, 1), Array(q1, q2)) End Function Private Function multr(r As Double, q As Variant) As Variant multr = WorksheetFunction.MMult(r, q) End Function Private Function mult(q1 As Variant, q2 As Variant) Dim res(4) As Double res(1) = q1(1) * q2(1) - q1(2) * q2(2) - q1(3) * q2(3) - q1(4) * q2(4) res(2) = q1(1) * q2(2) + q1(2) * q2(1) + q1(3) * q2(4) - q1(4) * q2(3) res(3) = q1(1) * q2(3) - q1(2) * q2(4) + q1(3) * q2(1) + q1(4) * q2(2) res(4) = q1(1) * q2(4) + q1(2) * q2(3) - q1(3) * q2(2) + q1(4) * q2(1) mult = res End Function Private Sub quats(q As Variant) Debug.Print q(1); IIf(q(2) < 0, " - " & Abs(q(2)), " + " & q(2)); Debug.Print IIf(q(3) < 0, "i - " & Abs(q(3)), "i + " & q(3)); Debug.Print IIf(q(4) < 0, "j - " & Abs(q(4)), "j + " & q(4)); "k" End Sub Public Sub quaternions() q = [{ 1, 2, 3, 4}] q1 = [{2, 3, 4, 5}] q2 = [{3, 4, 5, 6}] Dim r_ As Double r_ = 7# Debug.Print "q = ";: quats q Debug.Print "q1 = ";: quats q1 Debug.Print "q2 = ";: quats q2 Debug.Print "r = "; r_ Debug.Print "norm(q) = "; norm(q) Debug.Print "negative(q) = ";: quats negative(q) Debug.Print "conjugate(q) = ";: quats conj(q) Debug.Print "r + q = ";: quats addr(r_, q) Debug.Print "q1 + q2 = ";: quats add(q1, q2) Debug.Print "q * r = ";: quats multr(r_, q) Debug.Print "q1 * q2 = ";: quats mult(q1, q2) Debug.Print "q2 * q1 = ";: quats mult(q2, q1) End Sub

Sub Demo() Dim arr arr = Array(1, 2, 3, 4, 5, 6, 7, 8, 9, 10) Debug.Print "sum : " & Application.WorksheetFunction.Sum(arr) Debug.Print "product : " & Application.WorksheetFunction.Product(arr) End Sub

Dim tihead As TreeItem Private Function Add(v As Integer, left As TreeItem, right As TreeItem) As TreeItem Dim x As New TreeItem x.Value = v Set x.LeftChild = left Set x.RightChild = right Set Add = x End Function Private Sub Init() Set tihead = Add(1, _ Add(2, _ Add(4, _ Add(7, Nothing, Nothing), _ Nothing), _ Add(5, Nothing, Nothing)), _ Add(3, _ Add(6, _ Add(8, Nothing, Nothing), _ Add(9, Nothing, Nothing)), _ Nothing)) End Sub Private Sub InOrder(ti As TreeItem) If Not ti Is Nothing Then Call InOrder(ti.LeftChild) Debug.Print ti.Value; Call InOrder(ti.RightChild) End If End Sub Private Sub PreOrder(ti As TreeItem) If Not ti Is Nothing Then Debug.Print ti.Value; Call PreOrder(ti.LeftChild) Call PreOrder(ti.RightChild) End If End Sub Private Sub PostOrder(ti As TreeItem) If Not ti Is Nothing Then Call PostOrder(ti.LeftChild) Call PostOrder(ti.RightChild) Debug.Print ti.Value; End If End Sub Private Sub LevelOrder(ti As TreeItem) Dim queue As Object Set queue = CreateObject("System.Collections.Queue") queue.Enqueue ti Do While (queue.Count > 0) Set next_ = queue.Dequeue Debug.Print next_.Value; If Not next_.LeftChild Is Nothing Then queue.Enqueue next_.LeftChild If Not next_.RightChild Is Nothing Then queue.Enqueue next_.RightChild Loop End Sub Public Sub Main() Init Debug.Print "preorder: "; Call PreOrder(tihead) Debug.Print vbCrLf; "inorder: "; Call InOrder(tihead) Debug.Print vbCrLf; "postorder: "; Call PostOrder(tihead) Debug.Print vbCrLf; "level-order: "; Call LevelOrder(tihead) End Sub

<reponame>npocmaka/Windows-Server-2003 ' Copy the Terminal Services ActiveX control since we don't build it, but need it for private builds strReleasePath = "\\dsys-rel-fre\release\usa" strCabFile = "msrdp.cab" Set fileSystem = CreateObject ("Scripting.FileSystemObject") Set releaseFolder = fileSystem.GetFolder(strReleasePath) 'Get the directory for the latest build 'This gets the latest build directory assuming the folders are listed alphabetically Set subFolders = releaseFolder.SubFolders For Each subFolder in subFolders name = subFolder.Name If InStr(1, name, "x86fre") Then strBuild = name End If Next strReleasePath = strReleasePath & "\" & strBuild & "\" Set WshShell = CreateObject("WScript.Shell") strPostBuildDir = WshShell.ExpandEnvironmentStrings("%_NTPOSTBLD%") 'For some reason, I get an Access Denied message if I try to copy the file programmatically, 'so I create a batch file to copy the cab If fileSystem.FileExists(strReleasePath & strCabFile) Then Set batchFile = fileSystem.CreateTextFile("CopyMsrdp.bat", True) batchFile.WriteLine("copy " & strReleasePath & strCabFile & " " & strPostBuildDir) batchFile.Close Else wscript.echo "File does NOT Exist: " & strReleasePath & strCabFile End If

Public Sub foodemo() 'declare and create separately Dim f As Foo Dim f0 As Foo Set f = New Foo 'set property f.Bar = 25 'call method f.DoubleBar 'alternative Call f.DoubleBar Debug.Print "f.Bar is "; f.Bar Debug.Print "Five times f.Bar is "; f.MultiplyBar(5) 'declare and create at the same time Dim f2 As New Foo Debug.Print "f2.Bar is "; f2.Bar 'prints default value 'destroy an object Set f = Nothing 'create an object or not, depending on a random number: If Rnd() < 0.5 Then Set f0 = New Foo End If 'check if object actually exists If f0 Is Nothing Then Debug.Print "object f0 does not exist" Else Debug.Print "object f0 was created" End If 'at the end of execution all remaining objects created in this sub will be released. 'this will trigger one or two "object destroyed" messages 'depending on whether f0 was created... End Sub

' docopy.vbs ' This script (re)calculates the build number, creates a directory on the target machine ' with that build number as a directory name, then copies all the files identified in the ' filecopy.dat file to the destinations noted there. BUILDDEST = "\\b11nlbuilds\sapi5" BUILDER = "spgbld" BUILDMAIL = "spgmake" on error resume next ' VerifyPath takes the destination from the filecopy.dat, as modified to include BUILDDEST ' and the build number, and looks to see if the destination actually exists. It starts from ' the root of the name, BUILDDEST, and checks at each node to see if that folder exists; if ' not, it creates that folder, then continues down the destination name. sub VerifyPath(pathname) if right(pathname,1) <> "\" then 'strip off filename, if any beginfname = InStrRev(pathname, "\") pathname = left(pathname,len(pathname) - beginfname) end if lasttry = instr(pathname, BUILDDEST) + len(BUILDDEST) ' offset for known directory do while lasttry < (len(pathname) - 1) ptr = InStr(lasttry + 2, pathname, "\") - 1 'end of path component trial = left(pathname, ptr) if not fso.FolderExists(trial) then fso.CreateFolder(trial) end if lasttry = ptr loop end sub set wso = CreateObject("WScript.Shell") USER = wso.ExpandEnvironmentStrings("%USERNAME%") SAPIROOT = wso.ExpandEnvironmentStrings("%SAPIROOT%") ' The following if..then ensures that only the official builder will do ' the copy functions through the buildall command file. If the username ' in the environment is not that of the official builder, the loop will ' not be executed. if USER = BUILDER then set fso = CreateObject("Scripting.FileSystemObject") ' The following retrieves the build number from the ' currver.inc file that is generated by the build process set verfile = fso.GetFile(SAPIROOT & "\build\currver.inc") set fstream = verfile.OpenAsTextStream do while fstream.AtEndOfStream <> True linein = fstream.ReadLine if left(linein, 15) = "#define VERSION" then BuildNum = left(right(linein, 5), 4) end if loop fstream.Close() ' Now read the data file to find out which files to copy and ' where to put them. set file = fso.GetFile(SAPIROOT & "\builder\filecopy.dat") set fstream = file.OpenAsTextStream do while fstream.AtEndOfStream <> True linein = fstream.ReadLine if left(linein, 1) <> "#" then fromto = split(linein, ",") filefrom = SAPIROOT & "\" & trim(fromto(0)) fileto = BUILDDEST & "\" & BuildNum & "\" & trim(fromto(1)) VerifyPath(fileto) fso.CopyFile filefrom, fileto if err.number <> 0 then wscript.echo "Error: " & err.description & ": copying " & filefrom & " to " & fileto err.clear end if end if loop fstream.Close() ' Now an xcopy to get all the source & pdbs wso.Run("xcopy /s /i " & SAPIROOT & "\src\*.cpp " & BUILDDEST & "\" & BuildNum & "\src") wso.Run("xcopy /s /i " & SAPIROOT & "\src\*.h " & BUILDDEST & "\" & BuildNum & "\src") wso.Run("xcopy /s /i " & SAPIROOT & "\src\*.pdb " & BUILDDEST & "\" & BuildNum & "\src") wso.Run("xcopy /s /i " & SAPIROOT & "\QA\*.cpp " & BUILDDEST & "\" & BuildNum & "\src\QA") wso.Run("xcopy /s /i " & SAPIROOT & "\QA\*.h " & BUILDDEST & "\" & BuildNum & "\src\QA") wso.Run("xcopy /s /i " & SAPIROOT & "\QA\*.pdb " & BUILDDEST & "\" & BuildNum & "\src\QA") ' Clean up attributes on copied files wso.Run("attrib -r -h " & BUILDDEST & "\" & BuildNum & " /s") ' Get rid of slm.ini files from copied files wso.Run("del /s " & BUILDDEST & "\" & BuildNum & "\slm.ini") else permstring = "You are not the official builder, therefore your build " permstring = permstring & "will not be copied to the build repository. Please look " permstring = permstring & "for your result binaries in the appropriate directories." msgbox permstring, , "SPG Build Process" end if

<filename>admin/darwin/src/msitools/scripts/widiffdb.vbs ' Windows Installer utility to report the differences between two databases ' For use with Windows Scripting Host, CScript.exe only, lists to stdout ' Copyright (c) Microsoft Corporation. All rights reserved. ' Simply generates a transform between the databases and then view the transform ' Option Explicit Const icdLong = 0 Const icdShort = &h400 Const icdObject = &h800 Const icdString = &hC00 Const icdNullable = &h1000 Const icdPrimaryKey = &h2000 Const icdNoNulls = &h0000 Const icdPersistent = &h0100 Const icdTemporary = &h0000 Const msiOpenDatabaseModeReadOnly = 0 Const msiOpenDatabaseModeTransact = 1 Const msiOpenDatabaseModeCreate = 3 Const iteViewTransform = 256 If Wscript.Arguments.Count < 2 Then Wscript.Echo "Windows Installer database difference utility" &_ vbNewLine & " Generates a temporary transform file, then display it" &_ vbNewLine & " 1st argument is the path to the original installer database" &_ vbNewLine & " 2nd argument is the path to the updated installer database" &_ vbNewLine &_ vbNewLine & "Copyright (C) Microsoft Corporation. All rights reserved." Wscript.Quit 1 End If ' Cannot run with GUI script host, as listing is performed to standard out If UCase(Mid(Wscript.FullName, Len(Wscript.Path) + 2, 1)) = "W" Then WScript.Echo "Cannot use WScript.exe - must use CScript.exe with this program" Wscript.Quit 2 End If ' Connect to Windows Installer object On Error Resume Next Dim installer : Set installer = Nothing Set installer = Wscript.CreateObject("WindowsInstaller.Installer") : CheckError ' Create path for temporary transform file Dim WshShell : Set WshShell = Wscript.CreateObject("Wscript.Shell") : CheckError Dim tempFilePath:tempFilePath = WshShell.ExpandEnvironmentStrings("%TEMP%") & "\diff.tmp" ' Open databases, generate transform, then list transform Dim database1 : Set database1 = installer.OpenDatabase(Wscript.Arguments(0), msiOpenDatabaseModeReadOnly) : CheckError Dim database2 : Set database2 = installer.OpenDatabase(Wscript.Arguments(1), msiOpenDatabaseModeReadOnly) : CheckError Dim different : different = Database2.GenerateTransform(Database1, tempFilePath) : CheckError If different Then database1.ApplyTransform tempFilePath, iteViewTransform + 0 : CheckError' should not need error suppression flags ListTransform database1 End If ' Open summary information streams and compare them Dim sumInfo1 : Set sumInfo1 = database1.SummaryInformation(0) : CheckError Dim sumInfo2 : Set sumInfo2 = database2.SummaryInformation(0) : CheckError Dim iProp, value1, value2 For iProp = 1 to 19 value1 = sumInfo1.Property(iProp) : CheckError value2 = sumInfo2.Property(iProp) : CheckError If value1 <> value2 Then Wscript.Echo "\005SummaryInformation [" & iProp & "] {" & value1 & "}->{" & value2 & "}" different = True End If Next If Not different Then Wscript.Echo "Databases are identical" Wscript.Quit 0 Function DecodeColDef(colDef) Dim def Select Case colDef AND (icdShort OR icdObject) Case icdLong def = "LONG" Case icdShort def = "SHORT" Case icdObject def = "OBJECT" Case icdString def = "CHAR(" & (colDef AND 255) & ")" End Select If (colDef AND icdNullable) = 0 Then def = def & " NOT NULL" If (colDef AND icdPrimaryKey) <> 0 Then def = def & " PRIMARY KEY" DecodeColDef = def End Function Sub ListTransform(database) Dim view, record, row, column, change On Error Resume Next Set view = database.OpenView("SELECT * FROM `_TransformView` ORDER BY `Table`, `Row`") If Err <> 0 Then Wscript.Echo "Transform viewing supported only in builds 4906 and beyond of MSI.DLL" : Wscript.Quit 2 view.Execute : CheckError Do Set record = view.Fetch : CheckError If record Is Nothing Then Exit Do change = Empty If record.IsNull(3) Then row = "<DDL>" If NOT record.IsNull(4) Then change = "[" & record.StringData(5) & "]: " & DecodeColDef(record.StringData(4)) Else row = "[" & Join(Split(record.StringData(3), vbTab, -1), ",") & "]" If record.StringData(2) <> "INSERT" AND record.StringData(2) <> "DELETE" Then change = "{" & record.StringData(5) & "}->{" & record.StringData(4) & "}" End If column = record.StringData(1) & " " & record.StringData(2) if Len(column) < 24 Then column = column & Space(24 - Len(column)) WScript.Echo column, row, change Loop End Sub Sub CheckError Dim message, errRec If Err = 0 Then Exit Sub message = Err.Source & " " & Hex(Err) & ": " & Err.Description If Not installer Is Nothing Then Set errRec = installer.LastErrorRecord If Not errRec Is Nothing Then message = message & vbNewLine & errRec.FormatText End If Wscript.Echo message Wscript.Quit 2 End Sub

VERSION 5.00 Object = "{F9043C88-F6F2-101A-A3C9-08002B2F49FB}#1.2#0"; "COMDLG32.OCX" Begin VB.Form frmMain Caption = "MiscFixes" ClientHeight = 6825 ClientLeft = 270 ClientTop = 450 ClientWidth = 9390 LinkTopic = "Form1" ScaleHeight = 6825 ScaleWidth = 9390 StartUpPosition = 3 'Windows Default Begin VB.CheckBox chkPopulate Caption = "&Populate Help Image" Height = 255 Left = 120 TabIndex = 12 Top = 1560 Width = 1935 End Begin VB.TextBox txtOutput Height = 4335 Left = 120 MultiLine = -1 'True ScrollBars = 3 'Both TabIndex = 15 Top = 2400 Width = 9135 End Begin VB.CommandButton cmdClose Caption = "Close" Height = 375 Left = 8400 TabIndex = 14 Top = 1920 Width = 855 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 3 Left = 8880 TabIndex = 11 Top = 1200 Width = 375 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 2 Left = 8880 TabIndex = 8 Top = 840 Width = 375 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 1 Left = 8880 TabIndex = 5 Top = 480 Width = 375 End Begin VB.CommandButton cmdBrowse Caption = "..." Height = 255 Index = 0 Left = 8880 TabIndex = 2 Top = 120 Width = 375 End Begin MSComDlg.CommonDialog dlgCommon Left = 2040 Top = 1560 _ExtentX = 847 _ExtentY = 847 _Version = 393216 End Begin VB.TextBox txtIn Height = 285 Index = 3 Left = 1200 TabIndex = 10 Top = 1200 Width = 7575 End Begin VB.TextBox txtIn Height = 285 Index = 1 Left = 1200 TabIndex = 4 Top = 480 Width = 7575 End Begin VB.CommandButton cmdGo Caption = "Go" Height = 375 Left = 7440 TabIndex = 13 Top = 1920 Width = 855 End Begin VB.TextBox txtIn Height = 285 Index = 2 Left = 1200 TabIndex = 7 Top = 840 Width = 7575 End Begin VB.TextBox txtIn Height = 285 Index = 0 Left = 1200 TabIndex = 1 Top = 120 Width = 7575 End Begin VB.Label lbl Caption = "HH&T To Add" Height = 255 Index = 3 Left = 120 TabIndex = 9 Top = 1200 Width = 1095 End Begin VB.Label lbl Caption = "&Output CAB" Height = 255 Index = 1 Left = 120 TabIndex = 3 Top = 480 Width = 855 End Begin VB.Label lbl Caption = "&SubSite XML" Height = 255 Index = 2 Left = 120 TabIndex = 6 Top = 840 Width = 1095 End Begin VB.Label lbl Caption = "&Input CAB" Height = 255 Index = 0 Left = 120 TabIndex = 0 Top = 120 Width = 855 End End Attribute VB_Name = "frmMain" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit ' Make sure that these letters correspond to the Alt key combinations. Private Const OPT_CAB_IN_C As String = "i" Private Const OPT_CAB_OUT_C As String = "o" Private Const OPT_SS_XML_C As String = "s" Private Const OPT_HHT_C As String = "t" Private Const OPT_POPULATE_C As String = "p" Private Const OPT_CLOSE_ON_WARNING_C As String = "qw" Private Const OPT_CLOSE_ALWAYS_C As String = "qa" Private Const OPT_HELP_C As String = "h,?,help" Private Enum INPUT_INDEX_E II_CAB_IN_E = 0 II_CAB_OUT_E = 1 II_SS_XML_E = 2 II_HHT_E = 3 End Enum Private Const MAX_INPUT_INDEX_C As Long = 3 Private p_strSeparator As String Private p_blnWarning As Boolean Private p_blnError As Boolean Private p_clsSizer As Sizer Private Sub p_DisplayHelp() Dim str As String str = "Usage: " & vbCrLf & vbCrLf & _ App.EXEName & " /i <Input CAB> /o <Output CAB> /s <SubSite XML> /t <HHT To Add> /p /qw /qa" & vbCrLf & vbCrLf & _ "The /s, /t, /p, /qw, and /qa arguments are optional." & vbCrLf & _ "/qw makes the window go away even if there are Warnings." & vbCrLf & _ "/qa makes the window go away even if there are Errors and/or Warnings." & vbCrLf & _ """" & App.EXEName & " /?"" displays this message." Output str, LOGGING_TYPE_NORMAL_E Output p_strSeparator, LOGGING_TYPE_NORMAL_E End Sub Private Sub Form_Load() cmdGo.Default = True cmdClose.Cancel = True Set p_clsSizer = New Sizer SetLogFile Output "Version " & App.Major & "." & App.Minor & "." & App.Revision, LOGGING_TYPE_NORMAL_E p_strSeparator = String(80, "-") Output p_strSeparator, LOGGING_TYPE_NORMAL_E p_ProcessCommandLine End Sub Private Sub p_ProcessCommandLine() Dim strCommand As String Dim blnCloseOnWarning As Boolean Dim blnCloseAlways As Boolean Dim blnClose As Boolean strCommand = Trim$(Command$) If (strCommand = "") Then Exit Sub End If txtIn(II_CAB_IN_E) = GetOption(strCommand, OPT_CAB_IN_C, True) txtIn(II_CAB_OUT_E) = GetOption(strCommand, OPT_CAB_OUT_C, True) txtIn(II_SS_XML_E) = GetOption(strCommand, OPT_SS_XML_C, True) txtIn(II_HHT_E) = GetOption(strCommand, OPT_HHT_C, True) If (OptionExists(strCommand, OPT_POPULATE_C, True)) Then chkPopulate.Value = vbChecked End If blnCloseOnWarning = OptionExists(strCommand, OPT_CLOSE_ON_WARNING_C, True) blnCloseAlways = OptionExists(strCommand, OPT_CLOSE_ALWAYS_C, True) If (OptionExists(strCommand, OPT_HELP_C, True)) Then p_DisplayHelp ElseIf (Len(strCommand) <> 0) Then cmdGo_Click If (p_blnError) Then ' If an error occurred, then close the window only if OPT_CLOSE_ALWAYS_C is specified. If (blnCloseAlways) Then blnClose = True End If ElseIf (p_blnWarning) Then ' If a warning occurred, but there was no error, then close the window only if ' OPT_CLOSE_ON_WARNING_C or OPT_CLOSE_ALWAYS_C is specified. If (blnCloseOnWarning Or blnCloseAlways) Then blnClose = True End If Else ' If there was no warning or error, then close the window. blnClose = True End If If (blnClose) Then cmdClose_Click End If End If End Sub Private Sub cmdGo_Click() On Error GoTo LError Dim strCABIn As String Dim strCABOut As String Dim strSubSiteXML As String Dim strHHT As String Dim blnPopulateHelpImage As Boolean Output "Start: " & Date & " " & Time, LOGGING_TYPE_NORMAL_E strCABIn = Trim$(txtIn(II_CAB_IN_E).Text) strCABOut = Trim$(txtIn(II_CAB_OUT_E).Text) strSubSiteXML = Trim$(txtIn(II_SS_XML_E).Text) strHHT = Trim$(txtIn(II_HHT_E).Text) If (chkPopulate.Value = vbChecked) Then blnPopulateHelpImage = True End If If ((strCABIn = "") Or (strCABOut = "")) Then Output "Please specify the Input and Output CABs", LOGGING_TYPE_ERROR_E GoTo LError End If Me.Enabled = False MainFunction strCABIn, strCABOut, strSubSiteXML, strHHT, blnPopulateHelpImage LEnd: Output "End: " & Date & " " & Time, LOGGING_TYPE_NORMAL_E Output "The log file is: " & GetLogFileName, LOGGING_TYPE_NORMAL_E Output p_strSeparator, LOGGING_TYPE_NORMAL_E Me.Enabled = True Exit Sub LError: GoTo LEnd End Sub Private Sub cmdClose_Click() Unload Me End Sub Private Sub cmdBrowse_Click(Index As Integer) On Error GoTo LError dlgCommon.CancelError = True dlgCommon.Flags = cdlOFNHideReadOnly dlgCommon.Filter = "All Files (*.*)|*.*" dlgCommon.ShowOpen txtIn(Index).Text = dlgCommon.FileName LEnd: Exit Sub LError: Select Case Err.Number Case cdlCancel ' Nothing. The user cancelled. End Select GoTo LEnd End Sub Private Sub Form_Activate() On Error GoTo LError p_SetSizingInfo DoEvents LError: End Sub Private Sub Form_Resize() On Error GoTo LError p_clsSizer.Resize LError: End Sub Private Sub p_SetSizingInfo() Dim intIndex As Long For intIndex = 0 To MAX_INPUT_INDEX_C p_clsSizer.AddControl txtIn(intIndex) Set p_clsSizer.ReferenceControl(DIM_RIGHT_E) = Me p_clsSizer.ReferenceDimension(DIM_RIGHT_E) = DIM_WIDTH_E p_clsSizer.AddControl cmdBrowse(intIndex) Set p_clsSizer.ReferenceControl(DIM_LEFT_E) = Me p_clsSizer.ReferenceDimension(DIM_LEFT_E) = DIM_WIDTH_E Next p_clsSizer.AddControl cmdGo Set p_clsSizer.ReferenceControl(DIM_LEFT_E) = Me p_clsSizer.ReferenceDimension(DIM_LEFT_E) = DIM_WIDTH_E p_clsSizer.AddControl cmdClose Set p_clsSizer.ReferenceControl(DIM_LEFT_E) = Me p_clsSizer.ReferenceDimension(DIM_LEFT_E) = DIM_WIDTH_E p_clsSizer.AddControl txtOutput Set p_clsSizer.ReferenceControl(DIM_RIGHT_E) = Me p_clsSizer.ReferenceDimension(DIM_RIGHT_E) = DIM_WIDTH_E Set p_clsSizer.ReferenceControl(DIM_BOTTOM_E) = Me p_clsSizer.ReferenceDimension(DIM_BOTTOM_E) = DIM_HEIGHT_E End Sub Public Sub Output( _ ByVal i_str As String, _ ByVal i_enumLoggingType As LOGGING_TYPE_E _ ) OutputToTextBoxAndWriteLog txtOutput, i_str, i_enumLoggingType If (i_enumLoggingType = LOGGING_TYPE_ERROR_E) Then p_blnError = True ElseIf (i_enumLoggingType = LOGGING_TYPE_WARNING_E) Then p_blnWarning = True End If End Sub

<gh_stars>0 WScript.Echo("Goodbye, World!")

<gh_stars>1-10 class flattener dim separator sub class_initialize separator = "," end sub private function makeflat( a ) dim i dim res for i = lbound( a ) to ubound( a ) if isarray( a( i ) ) then res = res & makeflat( a( i ) ) else res = res & a( i ) & separator end if next makeflat = res end function public function flatten( a ) dim res res = makeflat( a ) res = left( res, len( res ) - len(separator)) res = split( res, separator ) flatten = res end function public property let itemSeparator( c ) separator = c end property end class

On Error Resume Next 'Ask for non-existent class to force error from CIMOM Set t_Service = GetObject("winmgmts://./root/default") Set t_Object = t_Service.Get("Nosuchclass000") if Err = 0 Then WScript.Echo "Got a class" Else WScript.Echo "" WScript.Echo "Err Information:" WScript.Echo "" WScript.Echo " Source:", Err.Source WScript.Echo " Description:", Err.Description WScript.Echo " Number", Err.Number 'Create the last error object set t_Object = CreateObject("WbemScripting.SWbemLastError") WScript.Echo "" WScript.Echo "WBEM Last Error Information:" WScript.Echo "" WScript.Echo " Operation:", t_Object.Operation WScript.Echo " Provider:", t_Object.ProviderName strDescr = t_Object.Description strPInfo = t_Object.ParameterInfo strCode = t_Object.StatusCode if (strDescr <> nothing) Then WScript.Echo " Description:", strDescr end if if (strPInfo <> nothing) Then WScript.Echo " Parameter Info:", strPInfo end if if (strCode <> nothing) Then WScript.Echo " Status:", strCode end if WScript.Echo "" Err.Clear set t_Object2 = CreateObject("WbemScripting.SWbemLastError") if Err = 0 Then WScript.Echo "Got the error object again - this shouldn't have happened!" Else Err.Clear WScript.Echo "Couldn't get last error again - as expected" End if End If

<reponame>LaudateCorpus1/RosettaCodeData Len(string|varname)

DHRYSTONE 2.1 BENCHMARK REPORTING FORM MANUF: MODEL: PROC: CLOCK: OS: OVERSION: COMPILER: CVERSION: OPTIONS: NOREG: REG: NOTES: DATE: SUBMITTER: MAILTO: uunet!pcrat!dry2

<filename>admin/wmi/wbem/scripting/test/vbscript/iproutetable.vbs on error resume next set n = getobject ("winmgmts://alanbos2/root/snmp/test") set routingtable = n.instancesof ("SNMP_RFC1213_MIB_ipRouteTable") for each route in routingtable WScript.Echo route.path_.relpath result = route.Fred () if err <> 0 then WScript.Echo Hex(Err.Number), Err.Description, Err.Source Err.Clear end if next

Function gcd(u As Long, v As Long) As Long Dim t As Long Do While v t = u u = v v = t Mod v Loop gcd = u End Function Function lcm(m As Long, n As Long) As Long lcm = Abs(m * n) / gcd(m, n) End Function

VERSION 5.00 Begin VB.Form frmFolderChooser BorderStyle = 1 'Fixed Single Caption = "Choose folder" ClientHeight = 3495 ClientLeft = 45 ClientTop = 330 ClientWidth = 4680 LinkTopic = "Form1" MaxButton = 0 'False MinButton = 0 'False ScaleHeight = 3495 ScaleWidth = 4680 StartUpPosition = 3 'Windows Default Begin VB.CommandButton cmdCancel Caption = "Cancel" Height = 375 Left = 3720 TabIndex = 3 Top = 3000 Width = 855 End Begin VB.CommandButton cmdOK Caption = "OK" Height = 375 Left = 2760 TabIndex = 2 Top = 3000 Width = 855 End Begin VB.DirListBox Dir1 Height = 2340 Left = 120 TabIndex = 1 Top = 480 Width = 4455 End Begin VB.DriveListBox Drive1 Height = 315 Left = 120 TabIndex = 0 Top = 120 Width = 4455 End End Attribute VB_Name = "frmFolderChooser" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Private p_FSO As Scripting.FileSystemObject Private p_intIndex As Long Public Event FolderChosen(ByVal intIndex As Long, ByVal strFolder As String) Private Sub Form_Load() cmdOK.Default = True cmdCancel.Cancel = True Set p_FSO = New Scripting.FileSystemObject End Sub Private Sub Form_Unload(Cancel As Integer) Set p_FSO = Nothing End Sub Private Sub cmdOK_Click() RaiseEvent FolderChosen(p_intIndex, Dir1.Path) Unload Me End Sub Private Sub cmdCancel_Click() Unload Me End Sub Private Sub Drive1_Change() Dir1.Path = Mid$(Drive1.Drive, 1, 2) & "\" End Sub Public Sub SetFolder( _ ByVal i_intIndex As Long, _ ByVal i_strFolder As String _ ) Dim strDrive As String Dim strFolder As String If (p_FSO.FolderExists(i_strFolder)) Then strFolder = i_strFolder Else strFolder = p_FSO.GetSpecialFolder(TemporaryFolder) End If Drive1.Drive = p_FSO.GetDriveName(strFolder) Dir1.Path = strFolder p_intIndex = i_intIndex End Sub

'********************************************************************* ' ' datetime.vbs ' ' Purpose: test datetime functionality ' ' Parameters: none ' ' Returns: 0 - success ' 1 - failure ' '********************************************************************* on error resume next set scriptHelper = CreateObject("WMIScriptHelper.WSC") scriptHelper.logFile = "c:\temp\datetime.txt" scriptHelper.loggingLevel = 3 scriptHelper.testName = "DATETIME" scriptHelper.testStart '***************************** ' Create a datetime object '***************************** set datetime = CreateObject("WbemScripting.SWbemDatetime") if err <> 0 then scriptHelper.writeErrorToLog err, "Failed to create datetime" else scriptHelper.writeToLog "Datetime created correctly", 2 end if '***************************** ' Create a Variant date '***************************** myDate = CDate ("January 20 11:56:32") '***************************** ' Test 1 - Set as local date '***************************** datetime.SetVarDate (myDate) if datetime.Value <> "20000120195632.000000-480" then scriptHelper.writeErrorToLog null, "Incorrect DMTF value" else scriptHelper.writeToLog "DMTF value reported correctly", 2 end if if datetime.Year <> 2000 then scriptHelper.writeErrorToLog null, "Incorrect Year value" else scriptHelper.writeToLog "Year value reported correctly", 2 end if if datetime.YearSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect YearSpecified value" else scriptHelper.writeToLog "YearSpecified value reported correctly", 2 end if if datetime.Month <> 1 then scriptHelper.writeErrorToLog null, "Incorrect Month value" else scriptHelper.writeToLog "Month value reported correctly", 2 end if if datetime.MonthSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect MonthSpecified value" else scriptHelper.writeToLog "MonthSpecified value reported correctly", 2 end if if datetime.Day <> 20 then scriptHelper.writeErrorToLog null, "Incorrect Day value" else scriptHelper.writeToLog "Day value reported correctly", 2 end if if datetime.DaySpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect DaySpecified value" else scriptHelper.writeToLog "DaySpecified value reported correctly", 2 end if if datetime.Hours <> 19 then scriptHelper.writeErrorToLog null, "Incorrect Hours value" else scriptHelper.writeToLog "Hours value reported correctly", 2 end if if datetime.HoursSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect HoursSpecified value" else scriptHelper.writeToLog "HoursSpecified value reported correctly", 2 end if if datetime.Minutes <> 56 then scriptHelper.writeErrorToLog null, "Incorrect Minutes value" else scriptHelper.writeToLog "Minutes value reported correctly", 2 end if if datetime.MinutesSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect MinutesSpecified value" else scriptHelper.writeToLog "MinutesSpecified value reported correctly", 2 end if if datetime.Seconds <> 32 then scriptHelper.writeErrorToLog null, "Incorrect Seconds value" else scriptHelper.writeToLog "Seconds value reported correctly", 2 end if if datetime.SecondsSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect SecondsSpecified value" else scriptHelper.writeToLog "SecondsSpecified value reported correctly", 2 end if if datetime.MicroSeconds <> 0 then scriptHelper.writeErrorToLog null, "Incorrect Microseconds value" else scriptHelper.writeToLog "Microseconds value reported correctly", 2 end if if datetime.MicroSecondsSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect MicrosecondsSpecified value" else scriptHelper.writeToLog "MicrosecondsSpecified value reported correctly", 2 end if if datetime.UTC <> -480 then scriptHelper.writeErrorToLog null, "Incorrect UTC value" else scriptHelper.writeToLog "UTC value reported correctly", 2 end if if datetime.UTCSpecified <> true then scriptHelper.writeErrorToLog null, "Incorrect UTCSpecified value" else scriptHelper.writeToLog "UTCSpecified value reported correctly", 2 end if if datetime.IsInterval <> false then scriptHelper.writeErrorToLog null, "Incorrect IsInterval value" else scriptHelper.writeToLog "IsInterval value reported correctly", 2 end if varDate = datetime.GetVarDate if err <> 0 then scriptHelper.writeErrorToLog err, "Failed to get VarDate" else scriptHelper.writeToLog "Vardate retrieved correctly: " & VarDate, 2 end if '***************************** 'Test Interval strings '***************************** dateTime.IsInterval = true dateTime.Day = 100 dateTime.Hours = 1 dateTime.Minutes = 0 dateTime.Seconds = 3 if datetime.Value <> "00000100010003.000000:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if '***************************** 'Test wildcard strings '***************************** datetime.Value = "19980416******.000000+***" if datetime.Value <> "19980416******.000000+***" then scriptHelper.writeErrorToLog null, "Failed to get correct wildcard value" else scriptHelper.writeToLog "Wildcard value retrieved correctly", 2 end if '***************************** 'Test invalid strings '***************************** datetime.Value = "199*0416******.000000+***" if err <> 0 then scriptHelper.writeToLog "Invalid value correctly rejected:" & err.Description, 2 err.clear else scriptHelper.writeErrorToLog null, "Invalid value erroneously accepted" end if '***************************** 'Test setting of individual properties '***************************** set datetime = CreateObject("WbemScripting.SWbemDatetime") if err <> 0 then scriptHelper.writeErrorToLog err, "Failed to create datetime" else scriptHelper.writeToLog "Datetime created correctly", 2 end if datetime.Year = 2000 datetime.Month = 5 datetime.Day = 8 datetime.Hours = 14 datetime.Minutes = 20 datetime.Seconds = 32 datetime.Microseconds = 123456 datetime.UTC = 320 if datetime.Value <> "20000508142032.123456+320" then scriptHelper.writeErrorToLog null, "Failed to get correct property-set value" else scriptHelper.writeToLog "Property-set value retrieved correctly", 2 end if '***************************** 'Test effects of changing IsInterval property '***************************** datetime.IsInterval = true if datetime.Value <> "00000008142032.123456:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if datetime.Day = 99999999 if datetime.Value <> "99999999142032.123456:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if datetime.IsInterval = false if datetime.Day <> 31 then scriptHelper.writeErrorToLog null, "Failed to get correct Day value" else scriptHelper.writeToLog "Day value retrieved correctly", 2 end if datetime.IsInterval = true datetime.Day = 0 if datetime.Value <> "00000000142032.123456:000" then scriptHelper.writeErrorToLog null, "Failed to get correct interval value" else scriptHelper.writeToLog "Interval value retrieved correctly", 2 end if datetime.IsInterval = false if datetime.Day <> 1 then scriptHelper.writeErrorToLog null, "Failed to get correct Day value" else scriptHelper.writeToLog "Day value retrieved correctly", 2 end if '***************************** 'Test conversion between local and non-local formats '***************************** dateTime.SetVarDate (CDate ("January 20 11:56:32")) if datetime.Value <> "20000120195632.000000-480" then scriptHelper.writeErrorToLog null, "Failed to get correct datetime value " & datetime.Value else scriptHelper.writeToLog "Datetime value retrieved correctly", 2 end if if dateTime.GetVarDate () <> "1/20/2000 11:56:32 AM" then scriptHelper.writeErrorToLog null, "Failed to get correct local vardate value" else scriptHelper.writeToLog "Local vardate value retrieved correctly", 2 end if if dateTime.GetVarDate (false) <> "1/20/2000 7:56:32 PM" then scriptHelper.writeErrorToLog null, "Failed to get correct non-local vardate value" else scriptHelper.writeToLog "Non-Local vardate value retrieved correctly", 2 end if if dateTime.GetFileTime () <> "125928429920000000" then scriptHelper.writeErrorToLog null, "Failed to get correct local filetime value" else scriptHelper.writeToLog "Local filetime value retrieved correctly", 2 end if if dateTime.GetFileTime (false) <> "125928717920000000" then scriptHelper.writeErrorToLog null, "Failed to get correct non-local filetime value" else scriptHelper.writeToLog "Non-Local filetime value retrieved correctly", 2 end if '************************************************* 'Test invariance of filetime down to 1ms precision '************************************************* datetime.SetFileTime "126036951652031260" if datetime.GetFileTime <> "126036951652031260" then scriptHelper.writeErrorToLog null, "Failed to preserve filetime to 1ms precision" else scriptHelper.writeToLog "Filetime value preserved to 1ms precision correctly", 2 end if scriptHelper.testComplete if scriptHelper.statusOK then WScript.Echo "PASS" WScript.Quit 0 else WScript.Echo "FAIL" WScript.Quit 1 end if

Option Explicit '---------------------------------------------------------------------- Private Function coin_count(coins As Variant, amount As Long) As Variant 'return type will be Decimal Dim s() As Variant Dim n As Long, c As Long ReDim s(amount + 1) s(1) = CDec(1) For c = LBound(coins) To UBound(coins) For n = coins(c) To amount s(n + 1) = CDec(s(n + 1) + s(n - coins(c) + 1)) Next n Next c coin_count = s(amount + 1) End Function '---------------------------------------------------------------------- Sub Main() Dim us_common_coins As Variant Dim us_coins As Variant 'The next line creates 0-based array us_common_coins = Array(25, 10, 5, 1) Debug.Print coin_count(us_common_coins, 100) us_coins = Array(100, 50, 25, 10, 5, 1) Debug.Print coin_count(us_coins, 100000) End Sub

<reponame>npocmaka/Windows-Server-2003 VERSION 5.00 Object = "{EAB22AC0-30C1-11CF-A7EB-0000C05BAE0B}#1.1#0"; "shdocvw.dll" Object = "{831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0"; "mscomctl.ocx" Begin VB.Form HssX Caption = "HSC Extensions Manager" ClientHeight = 8235 ClientLeft = 3135 ClientTop = 2280 ClientWidth = 6240 LinkTopic = "Form1" ScaleHeight = 8235 ScaleWidth = 6240 Begin MSComctlLib.StatusBar StatusBar1 Align = 2 'Align Bottom Height = 285 Left = 0 TabIndex = 21 Top = 7950 Width = 6240 _ExtentX = 11007 _ExtentY = 503 _Version = 393216 BeginProperty Panels {8E3867A5-8586-11D1-B16A-00C0F0283628} NumPanels = 1 BeginProperty Panel1 {8E3867AB-8586-11D1-B16A-00C0F0283628} EndProperty EndProperty End Begin VB.TextBox txtAuxFolder Height = 300 Left = 30 TabIndex = 18 Top = 1245 Width = 5355 End Begin VB.TextBox txtCabFile Height = 300 Left = 30 TabIndex = 17 Top = 720 Width = 5355 End Begin VB.CommandButton cmdExecuteExts Caption = "E&xecute Extensions" Height = 375 Left = 3750 TabIndex = 16 Top = 7560 Width = 1800 End Begin MSComctlLib.ListView lstvwExtensions Height = 2070 Left = 30 TabIndex = 15 Top = 3195 Width = 6150 _ExtentX = 10848 _ExtentY = 3651 LabelWrap = -1 'True HideSelection = -1 'True OLEDropMode = 1 Checkboxes = -1 'True _Version = 393217 ForeColor = -2147483640 BackColor = -2147483643 BorderStyle = 1 Appearance = 1 OLEDropMode = 1 NumItems = 1 BeginProperty ColumnHeader(1) {BDD1F052-858B-11D1-B16A-00C0F0283628} Object.Width = 2540 EndProperty End Begin VB.Frame fraSKU Caption = "SKU" Height = 1575 Left = 30 TabIndex = 5 Top = 1560 Width = 6135 Begin VB.CheckBox chkStandard Caption = "32-bit Standard" Height = 255 Left = 240 TabIndex = 14 Top = 480 Width = 1695 End Begin VB.CheckBox chkProfessional Caption = "32-bit Professional" Height = 255 Left = 240 TabIndex = 13 Top = 720 Width = 1695 End Begin VB.CheckBox chkServer Caption = "32-bit Server" Height = 255 Left = 3120 TabIndex = 12 Top = 240 Width = 2055 End Begin VB.CheckBox chkAdvancedServer Caption = "32-bit Advanced Server" Height = 255 Left = 3120 TabIndex = 11 Top = 480 Width = 2055 End Begin VB.CheckBox chkDataCenterServer Caption = "32-bit Datacenter Server" Height = 255 Left = 3120 TabIndex = 10 Top = 960 Width = 2055 End Begin VB.CheckBox chkProfessional64 Caption = "64-bit Professional" Height = 255 Left = 240 TabIndex = 9 Top = 960 Width = 1695 End Begin VB.CheckBox chkAdvancedServer64 Caption = "64-bit Advanced Server" Height = 255 Left = 3120 TabIndex = 8 Top = 720 Width = 2055 End Begin VB.CheckBox chkDataCenterServer64 Caption = "64-bit Datacenter Server" Height = 255 Left = 3120 TabIndex = 7 Top = 1200 Width = 2055 End Begin VB.CheckBox chkWindowsMillennium Caption = "Windows Me" Height = 255 Left = 240 TabIndex = 6 Top = 240 Width = 1695 End End Begin SHDocVwCtl.WebBrowser wb Height = 2235 Left = 45 TabIndex = 4 Top = 5280 Width = 6165 ExtentX = 10874 ExtentY = 3942 ViewMode = 0 Offline = 0 Silent = 0 RegisterAsBrowser= 0 RegisterAsDropTarget= 1 AutoArrange = 0 'False NoClientEdge = 0 'False AlignLeft = 0 'False ViewID = "{0057D0E0-3573-11CF-AE69-08002B2E1262}" Location = "res://C:\WINNT\system32\shdoclc.dll/dnserror.htm#http:///" End Begin VB.CommandButton cmdClose Caption = "&Close" Height = 375 Left = 5565 TabIndex = 3 Top = 7560 Width = 675 End Begin VB.CommandButton cmdGo Caption = "&Go" Height = 315 Left = 5415 TabIndex = 2 Top = 240 Width = 675 End Begin VB.TextBox txtExtensionsFolder Height = 300 Left = 30 TabIndex = 0 Top = 240 Width = 5355 End Begin VB.Label Label3 Caption = "Auxiliary Folder for Storing Extensions Output:" Height = 240 Left = 75 TabIndex = 20 Top = 1035 Width = 3555 End Begin VB.Label Label2 Caption = "Cab File Location:" Height = 240 Left = 45 TabIndex = 19 Top = 525 Width = 3000 End Begin VB.Label Label1 Caption = "Extension Tools Directory Location:" Height = 240 Left = 30 TabIndex = 1 Top = 15 Width = 3000 End Begin VB.Menu mnuExt Caption = "Extension Right Click Menu" Visible = 0 'False Begin VB.Menu mnuEdit Caption = "Edit" End Begin VB.Menu mnuDelete Caption = "Delete" End End End Attribute VB_Name = "HssX" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False ' ========================================================================================== Option Explicit Private m_strTempXMLFile As String ' Temporary File for XML Rendering Private m_oDomList As IXMLDOMNodeList ' List of Extensions Private WithEvents m_oHssExt As HssExts Attribute m_oHssExt.VB_VarHelpID = -1 Private m_oFs As Scripting.FileSystemObject Private m_bIndrag As Boolean ' This variable is used to control ' dragging inside the Listview Private m_oCachedExt As IXMLDOMNode ' This is the Cached DOMNODE ' which is saved on MouseUp ' event from the ListView. ' We need to cache it because ' Menus are event driven. Private m_dblTimeLeftButtonDown As Double ' Tracks how long the Mouse Down button was pressed. Private Sub Form_Initialize() Set m_oHssExt = New HssExts Set m_oFs = New Scripting.FileSystemObject End Sub Private Sub Form_Load() With Me .txtExtensionsFolder = App.Path + "\Extensions" .txtAuxFolder = App.Path + "\AuxFolder" .txtCabFile = App.Path + "\hcdata.cab" End With ' Let's Get a Temporary File Name m_strTempXMLFile = Environ$("TEMP") + "\" + m_oFs.GetTempName + ".xml" Dim oFh As Scripting.TextStream Set oFh = m_oFs.CreateTextFile(m_strTempXMLFile) oFh.WriteLine "<Note>When you click on an extension in the List Above, the HSS Tool Extension XML Entry will show up here</Note>" oFh.Close wb.Navigate m_strTempXMLFile ' let's kick the first Extensions Search. ' txtExtensionsFolder_Change End Sub Private Sub chkAdvancedServer_Click() cmdGo_Click End Sub Private Sub chkAdvancedServer64_Click() cmdGo_Click End Sub Private Sub chkDataCenterServer_Click() cmdGo_Click End Sub Private Sub chkDataCenterServer64_Click() cmdGo_Click End Sub Private Sub chkProfessional_Click() cmdGo_Click End Sub Private Sub chkProfessional64_Click() cmdGo_Click End Sub Private Sub chkServer_Click() cmdGo_Click End Sub Private Sub chkStandard_Click() cmdGo_Click End Sub Private Sub chkWindowsMillennium_Click() cmdGo_Click End Sub Private Sub cmdExecuteExts_Click() m_oHssExt.ExecuteExtensions m_oDomList, Me.txtCabFile, Me.txtAuxFolder End Sub Private Sub cmdClose_Click() Unload Me End Sub Private Sub cmdGo_Click() Dim oDomList As IXMLDOMNodeList Set m_oDomList = m_oHssExt.GetExtensionsList(Me.txtExtensionsFolder, SkuCollection) With Me.lstvwExtensions .LabelEdit = lvwManual .ListItems.Clear .View = lvwReport .ColumnHeaders(1).Text = "Select Extensions to Run" .ColumnHeaders(1).Width = lstvwExtensions.Width - 85 If (m_oDomList Is Nothing) Then GoTo Common_Exit Dim oDomNode As IXMLDOMNode Dim l As ListItem For Each oDomNode In m_oDomList Set l = .ListItems.Add(Text:=oDomNode.selectSingleNode("display-name").Text) Set l.Tag = oDomNode Next End With Common_Exit: End Sub Private Function SkuCollection() As Scripting.Dictionary Set SkuCollection = New Scripting.Dictionary If (Me.chkAdvancedServer) Then SkuCollection.Add "ADV", "ADV" End If If (Me.chkAdvancedServer64) Then SkuCollection.Add "ADV64", "ADV64" End If If (Me.chkDataCenterServer) Then SkuCollection.Add "DAT", "DAT" End If If (Me.chkDataCenterServer64) Then SkuCollection.Add "DAT64", "DAT64" End If If (Me.chkProfessional) Then SkuCollection.Add "PRO", "PRO" End If If (Me.chkProfessional64) Then SkuCollection.Add "PRO64", "PRO64" End If If (Me.chkServer) Then SkuCollection.Add "SRV", "SRV" End If If (Me.chkStandard) Then SkuCollection.Add "STD", "STD" End If If (Me.chkWindowsMillennium) Then SkuCollection.Add "WINME", "WINME" End If End Function Private Sub lstvwExtensions_Click() DisplayTaxonomyEntry2 lstvwExtensions, m_oDomList, wb End Sub Private Sub lstvwExtensions_ItemCheck(ByVal Item As MSComctlLib.ListItem) Dim oElem As IXMLDOMElement ' Set oElem = m_oDomList.Item(lstvwExtensions.HitTest(Item.Left, Item.Top).Index - 1).selectSingleNode("run-this-extension") Set oElem = Item.Tag Set oElem = oElem.selectSingleNode("run-this-extension") oElem.Text = IIf(Item.Checked, "yes", "no") End Sub Private Sub lstvwExtensions_DragDrop(source As Control, x As Single, y As Single) DoDragDrop lstvwExtensions, source, x, y End Sub Private Sub lstvwExtensions_DragOver(source As Control, x As Single, y As Single, State As Integer) DoDragOver lstvwExtensions, source, x, y, State End Sub Private Sub lstvwExtensions_MouseDown(Button As Integer, Shift As Integer, x As Single, y As Single) If (Button = vbLeftButton) Then m_dblTimeLeftButtonDown = HighResTimer End If End Sub Private Sub lstvwExtensions_MouseUp(Button As Integer, Shift As Integer, x As Single, y As Single) ' Debug.Print "Button = " & Button & " - Shift = " & Shift Select Case Button Case vbRightButton If (Not lstvwExtensions.HitTest(x, y) Is Nothing) Then Set m_oCachedExt = lstvwExtensions.HitTest(x, y).Tag PopupMenu mnuExt Set m_oCachedExt = Nothing End If Case vbLeftButton m_dblTimeLeftButtonDown = 0 End Select End Sub Private Sub lstvwExtensions_MouseMove(Button As Integer, Shift As Integer, x As Single, y As Single) DoMouseMove lstvwExtensions, Button, Shift, x, y End Sub Sub DoMouseMove(lvw As ListView, Button As Integer, Shift As Integer, x As Single, y As Single) If (Button = vbLeftButton) Then If (LeftButtonWasPressedLongEnough) Then ' Signal a Drag operation. ' Set the drag icon with the CreateDragImage method. If (Not lvw.SelectedItem Is Nothing) Then m_bIndrag = True ' Set the flag to true. lvw.DragIcon = lvw.SelectedItem.CreateDragImage lvw.Drag vbBeginDrag ' Drag operation. End If End If Else m_bIndrag = False End If ' Debug.Print "DoMouseMove Called from " & lvw.Name; "_MouseMove. m_bIndrag = " & m_bIndrag End Sub Private Function LeftButtonWasPressedLongEnough() As Boolean LeftButtonWasPressedLongEnough = False If (m_dblTimeLeftButtonDown <> 0) Then LeftButtonWasPressedLongEnough = ((HighResTimer - m_dblTimeLeftButtonDown) > 0.4) End If End Function Sub DoDragOver(lvw As ListView, source As Control, x As Single, y As Single, State As Integer) If m_bIndrag = True Then ' Set DropHighlight to the mouse's coordinates. Set lvw.DropHighlight = lvw.HitTest(x, y) End If End Sub Sub DoDragDrop(lvw As ListView, _ source As Control, x As Single, y As Single _ ) If lvw.DropHighlight Is Nothing Then GoTo Common_Exit If (lvw Is source) Then ' We are on the Same Tree, so we need If lvw.SelectedItem.Index = lvw.DropHighlight.Index Then GoTo Common_Exit ' Temporary Variables to keep The List view Item contents. Dim strLi1 As String, strSli1 As String, strSli2 As String Dim oTag As Object, bChecked As Boolean ' The direction in which the List Items will be moved ' on the list to make room for the move Dim lDirection As Long If (lvw.DropHighlight.Index < lvw.SelectedItem.Index) Then lDirection = -1 Else lDirection = 1 End If With lvw.SelectedItem bChecked = .Checked Set oTag = .Tag strLi1 = .Text ' strSli1 = .ListSubItems(1).Text ' strSli2 = .ListSubItems(2).Text End With Dim i As Long For i = lvw.SelectedItem.Index To lvw.DropHighlight.Index - lDirection Step lDirection With lvw.ListItems .Item(i).Checked = .Item(i + lDirection).Checked Set .Item(i).Tag = .Item(i + lDirection).Tag .Item(i) = .Item(i + lDirection) ' .Item(i).ListSubItems(1) = .Item(i + lDirection).ListSubItems(1) ' .Item(i).ListSubItems(2) = .Item(i + lDirection).ListSubItems(2) End With Next i With lvw.DropHighlight .Checked = bChecked Set .Tag = oTag .Text = strLi1 ' .ListSubItems(1).Text = strSli1 ' .ListSubItems(2).Text = strSli2 End With Debug.Print lvw.SelectedItem.Text & " dropped on " & lvw.DropHighlight.Text End If Common_Exit: ' This is the exit Condition for Shutting Down the Drag operation Set lvw.DropHighlight = Nothing: m_bIndrag = False Exit Sub End Sub Private Sub lstvwExtensions_OLEDragDrop( _ Data As MSComctlLib.DataObject, _ Effect As Long, Button As Integer, _ Shift As Integer, _ x As Single, _ y As Single _ ) If Data.GetFormat(vbCFFiles) Then Dim vFN For Each vFN In Data.Files ' Screen.MousePointer = vbHourglass ' Screen.MousePointer = 99 ' Screen.MouseIcon = LoadPicture(Environ$("WINDIR") + "\cursors\wait_m.cur") Select Case UCase$(m_oFs.GetExtensionName(vFN)) Case "EXE", "VBS", "JS", "BAT", "PL" If (Not m_oHssExt.ExtensionExists(m_oFs.GetFileName(vFN))) Then Dim oFext As frmExt: Set oFext = New frmExt oFext.DropFile Nothing, vFN, "MSFT" cmdGo_Click Else MsgBox "This Extension was already added to the Extensions System " + vbCrLf + _ "in case you want to update it, please remove first the old " + vbCrLf + _ "extension and then retry the operation", vbInformation, _ Me.Caption End If End Select ' Screen.MousePointer = vbDefault Next vFN End If End Sub Private Sub m_oHssExt_RunStatus(ByVal strExt As String, bCancel As Boolean) Me.StatusBar1.SimpleText = strExt End Sub Private Sub mnuDelete_Click() m_oHssExt.DeleteExtension m_oCachedExt cmdGo_Click End Sub Private Sub mnuEdit_Click() MsgBox "Edit Menu" End Sub Private Sub txtExtensionsFolder_Change() Dim bEnabled As Boolean bEnabled = m_oFs.FolderExists(Me.txtExtensionsFolder) With Me .txtAuxFolder.Enabled = bEnabled .txtCabFile.Enabled = bEnabled .lstvwExtensions.Enabled = bEnabled .fraSKU.Enabled = bEnabled .cmdExecuteExts.Enabled = bEnabled .cmdGo.Enabled = bEnabled End With cmdGo_Click End Sub Sub DisplayTaxonomyEntry2(oList As ListView, oResultsList As IXMLDOMNodeList, wBrowser As WebBrowser) If (oList.SelectedItem Is Nothing) Then GoTo Common_Exit Dim oDom As DOMDocument: Set oDom = New DOMDocument oDom.loadXML oList.SelectedItem.Tag.xml oDom.save m_strTempXMLFile wBrowser.Navigate m_strTempXMLFile Common_Exit: End Sub

<reponame>LaudateCorpus1/RosettaCodeData<filename>Task/Align-columns/Visual-Basic/align-columns-1.vb<gh_stars>1-10 Sub AlignCols(Lines, Optional Align As AlignmentConstants, Optional Sep$ = "$", Optional Sp% = 1) Dim i&, j&, D&, L&, R&: ReDim W(UBound(Lines)): ReDim C&(0) For j = 0 To UBound(W) W(j) = Split(Lines(j), Sep) If UBound(W(j)) > UBound(C) Then ReDim Preserve C(UBound(W(j))) For i = 0 To UBound(W(j)): If Len(W(j)(i)) > C(i) Then C(i) = Len(W(j)(i)) Next i, j For j = 0 To UBound(W): For i = 0 To UBound(W(j)) D = C(i) - Len(W(j)(i)) L = Choose(Align + 1, 0, D, D \ 2) R = Choose(Align + 1, D, 0, D - L) + Sp Debug.Print Space(L); W(j)(i); Space(R); IIf(i < UBound(W(j)), "", vbLf); Next i, j End Sub

VERSION 5.00 Begin VB.Form Form1 Caption = "Form1" ClientHeight = 12675 ClientLeft = 60 ClientTop = 345 ClientWidth = 13095 LinkTopic = "Form1" ScaleHeight = 12675 ScaleWidth = 13095 StartUpPosition = 3 'Windows Default Begin VB.CommandButton Cancelc BackColor = &H000000FF& Caption = "Cancel (c)" Height = 855 Left = 10320 Style = 1 'Graphical TabIndex = 39 Top = 4560 Width = 1455 End Begin VB.CommandButton CancelButton BackColor = &H000000FF& Caption = "Cancel (s)" Height = 855 Left = 8160 MaskColor = &H8000000A& Style = 1 'Graphical TabIndex = 38 Top = 4560 Width = 1335 End Begin VB.ListBox ContextResults Height = 2985 ItemData = "Form1.frx":0000 Left = 120 List = "Form1.frx":0002 TabIndex = 37 Top = 6840 Width = 3135 End Begin VB.ListBox ContextList Height = 1815 ItemData = "Form1.frx":0004 Left = 8520 List = "Form1.frx":0006 TabIndex = 35 Top = 2040 Width = 3135 End Begin VB.CommandButton DeleteContext Caption = "Delete All" Height = 495 Left = 10200 TabIndex = 34 Top = 1320 Width = 1335 End Begin VB.CommandButton AddContext Caption = "Add" Height = 495 Left = 8760 TabIndex = 33 Top = 1320 Width = 855 End Begin VB.TextBox ContextValue Height = 375 Left = 10200 TabIndex = 32 Top = 600 Width = 1335 End Begin VB.TextBox ContextName Height = 375 Left = 8520 TabIndex = 31 Top = 600 Width = 1335 End Begin VB.CommandButton Command20 Caption = "Async Put Class (s)" Height = 615 Left = 5520 TabIndex = 29 Top = 4920 Width = 1455 End Begin VB.CommandButton Command19 Caption = "Sync Put Class" Height = 615 Left = 3840 TabIndex = 28 Top = 4920 Width = 1335 End Begin VB.TextBox QueryBox Height = 375 Left = 360 TabIndex = 25 Text = "select * from Win32_LogicalDisk" Top = 1320 Width = 3135 End Begin VB.CommandButton Command18 Caption = "Async Put Obj (s)" Height = 615 Left = 2160 TabIndex = 19 Top = 4920 Width = 1335 End Begin VB.CommandButton Command17 Caption = "Sync Put Obj" Height = 615 Left = 720 TabIndex = 18 Top = 4920 Width = 1215 End Begin VB.CheckBox Check1 Caption = "Use Object Methods" Height = 375 Left = 720 TabIndex = 17 TabStop = 0 'False Top = 5880 Width = 2175 End Begin VB.CommandButton Command16 Caption = "Sync NotificationQuery (c)" Height = 615 Left = 5520 TabIndex = 16 Top = 3960 Width = 1455 End Begin VB.CommandButton Command15 Caption = "Sync NotificationQuery" Height = 615 Left = 3840 TabIndex = 15 Top = 3960 Width = 1335 End Begin VB.CommandButton Command14 Caption = "Async ReferencesTo (c)" Height = 615 Left = 2160 TabIndex = 14 Top = 3960 Width = 1335 End Begin VB.CommandButton Command13 Caption = "Sync ReferencesTo" Height = 615 Left = 720 TabIndex = 13 Top = 3960 Width = 1215 End Begin VB.CommandButton Command12 Caption = "Async AssociatorsOf (c)" Height = 615 Left = 2160 TabIndex = 12 Top = 3000 Width = 1335 End Begin VB.CommandButton Command11 Caption = "Sync AssociatorsOf" Height = 615 Left = 720 TabIndex = 11 Top = 3000 Width = 1215 End Begin VB.CommandButton Command10 Caption = "Async SubclassesOf (c)" Height = 615 Left = 5520 TabIndex = 10 Top = 3000 Width = 1455 End Begin VB.CommandButton Command9 Caption = "Sync SubclassesOf" Height = 615 Left = 3840 TabIndex = 9 Top = 3000 Width = 1335 End Begin VB.CommandButton Command8 Caption = "Async InstancesOf (s)" Height = 615 Left = 5520 TabIndex = 8 Top = 2040 Width = 1455 End Begin VB.CommandButton Command7 Caption = "Sync InstncesOf" Height = 615 Left = 3840 TabIndex = 7 Top = 2040 Width = 1335 End Begin VB.CommandButton Command6 Caption = "Async Delete (s)" Height = 615 Left = 2160 TabIndex = 6 Top = 2040 Width = 1335 End Begin VB.CommandButton Command5 Caption = "Sync Delete" Height = 615 Left = 720 TabIndex = 5 Top = 2040 Width = 1215 End Begin VB.CommandButton Command4 Caption = "Async Get (s)" Height = 615 Left = 5520 TabIndex = 4 Top = 600 Width = 1455 End Begin VB.CommandButton Command3 Caption = "Sync Get" Height = 615 Left = 3840 TabIndex = 3 Top = 600 Width = 1335 End Begin VB.Timer Timer1 Interval = 100 Left = 2400 Top = 12480 End Begin VB.ListBox List1 Height = 2985 ItemData = "Form1.frx":0008 Left = 3600 List = "Form1.frx":000A TabIndex = 2 Top = 6840 Width = 3735 End Begin VB.CommandButton Command2 Caption = "Query Async (s)" Height = 615 Left = 2160 TabIndex = 1 Top = 600 Width = 1335 End Begin VB.CommandButton Command1 Caption = "Query Sync" Height = 615 Left = 720 TabIndex = 0 Top = 600 Width = 1215 End Begin VB.Frame Frame1 Caption = "Operations" Height = 6375 Left = 0 TabIndex = 30 Top = 240 Width = 7455 Begin VB.Line Line5 BorderColor = &H000000FF& X1 = 600 X2 = 7080 Y1 = 4560 Y2 = 4560 End Begin VB.Line Line4 X1 = 600 X2 = 7080 Y1 = 3600 Y2 = 3600 End Begin VB.Line Line3 X1 = 600 X2 = 7200 Y1 = 2640 Y2 = 2640 End Begin VB.Line Line2 X1 = 600 X2 = 7200 Y1 = 1680 Y2 = 1680 End Begin VB.Line Line1 X1 = 3720 X2 = 3720 Y1 = 240 Y2 = 5520 End End Begin VB.Frame Frame2 Caption = "Context" Height = 3855 Left = 8160 TabIndex = 36 Top = 360 Width = 3975 End Begin VB.Label ObjectPathLabel Caption = "Null" Height = 375 Left = 1560 TabIndex = 27 Top = 11160 Width = 4575 End Begin VB.Label Label4 Caption = "Put Obj Path:" Height = 375 Left = 240 TabIndex = 26 Top = 11160 Width = 1215 End Begin VB.Label LastErrorString Height = 375 Left = 2280 TabIndex = 24 Top = 10560 Width = 2415 End Begin VB.Label Label1 Caption = "Status:" Height = 255 Left = 480 TabIndex = 23 Top = 9960 Width = 615 End Begin VB.Label Label3 Caption = "Last Error:" Height = 375 Left = 240 TabIndex = 22 Top = 10560 Width = 735 End Begin VB.Label LastError Height = 375 Left = 1200 TabIndex = 21 Top = 10560 Width = 975 End Begin VB.Label Status Height = 255 Left = 1200 TabIndex = 20 Top = 9960 Width = 2055 End Begin VB.Image Image3 Height = 480 Left = 240 Picture = "Form1.frx":000C Top = 12600 Visible = 0 'False Width = 480 End Begin VB.Image Image2 Height = 480 Left = 1680 Picture = "Form1.frx":07FE Top = 12480 Visible = 0 'False Width = 480 End Begin VB.Image Image1 Height = 480 Left = 7800 Picture = "Form1.frx":0B08 Top = 7320 Width = 480 End End Attribute VB_Name = "Form1" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Dim WithEvents someSink As SWbemSink Attribute someSink.VB_VarHelpID = -1 Dim WithEvents classSink As SWbemSink Attribute classSink.VB_VarHelpID = -1 Dim WithEvents tmpSink1 As SWbemSink Attribute tmpSink1.VB_VarHelpID = -1 Dim WithEvents tmpSink2 As SWbemSink Attribute tmpSink2.VB_VarHelpID = -1 Dim WithEvents tmpSink3 As SWbemSink Attribute tmpSink3.VB_VarHelpID = -1 Dim WithEvents tmpSink4 As SWbemSink Attribute tmpSink4.VB_VarHelpID = -1 Dim WithEvents tmpSink5 As SWbemSink Attribute tmpSink5.VB_VarHelpID = -1 Dim WithEvents tmpSink6 As SWbemSink Attribute tmpSink6.VB_VarHelpID = -1 Dim WithEvents tmpSink7 As SWbemSink Attribute tmpSink7.VB_VarHelpID = -1 Dim WithEvents tmpSink8 As SWbemSink Attribute tmpSink8.VB_VarHelpID = -1 Dim WithEvents tmpSink9 As SWbemSink Attribute tmpSink9.VB_VarHelpID = -1 Dim WithEvents tmpSink10 As SWbemSink Attribute tmpSink10.VB_VarHelpID = -1 Dim WithEvents tmpSink11 As SWbemSink Attribute tmpSink11.VB_VarHelpID = -1 Dim WithEvents tmpSink12 As SWbemSink Attribute tmpSink12.VB_VarHelpID = -1 Dim WithEvents tmpSink13 As SWbemSink Attribute tmpSink13.VB_VarHelpID = -1 Dim WithEvents tmpSink14 As SWbemSink Attribute tmpSink14.VB_VarHelpID = -1 Dim WithEvents tmpSink15 As SWbemSink Attribute tmpSink15.VB_VarHelpID = -1 Dim WithEvents tmpSink16 As SWbemSink Attribute tmpSink16.VB_VarHelpID = -1 Dim WithEvents tmpSink17 As SWbemSink Attribute tmpSink17.VB_VarHelpID = -1 Dim obj As SWbemObject Dim context As SWbemNamedValueSet Dim tmpContext As SWbemNamedValueSet Dim services As SWbemServices Dim locator As SWbemLocator Dim myimage As Boolean Private Sub AddContext_Click() Dim res As SWbemNamedValue Set res = context.Add(ContextName.Text, ContextValue.Text) ContextList.AddItem (ContextName.Text & "=" & ContextValue.Text) End Sub Private Sub CancelButton_Click() someSink.Cancel End Sub Private Sub Cancelc_Click() classSink.Cancel End Sub Private Sub classSink_OnCompleted(ByVal hResult As WbemScripting.WbemErrorEnum, ByVal pErrorObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Dim str As String GetErrorString hResult, str Call DisplayContext("OnCompleted(" & str & ") ", pAsyncContext) Call HandleErrors(hResult, "", pErrorObject) End Sub Private Sub classSink_OnObjectPut(ByVal pObjectPath As WbemScripting.ISWbemObjectPath, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Call DisplayContext("OnObjectPut", pAsyncContext) ObjectPathLabel.Caption = pObjectPath.path End Sub Private Sub classSink_OnObjectReady(ByVal pObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Call DisplayContext("OnObjectReady", pAsyncContext) List1.AddItem (pObject.Path_.Class) End Sub Private Sub classSink_OnProgress(ByVal upperBound As Long, ByVal current As Long, ByVal message As String, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Call DisplayContext("OnProgress", pAsyncContext) MsgBox ("OnProgress called - upper: " & upperBound & " current: " & current & " str: " & message) End Sub Private Sub Command1_Click() Dim myenum As Object Dim obj As SWbemObject Begin On Error GoTo ErrorHandler Set myenum = services.ExecQuery(QueryBox.Text) For Each obj In myenum List1.AddItem (obj.Path_.RelPath) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command10_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.SubclassesOfAsync classSink, "Cim_LogicalDevice", , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Cim_LogicalDevice") obj.SubclassesAsync_ classSink, , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command11_Click() Dim myenum As Object Dim computer As SWbemObject Begin On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.AssociatorsOf("Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices") Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") Set myenum = obj.Associators_("Win32_SystemDevices") End If For Each computer In myenum List1.AddItem (computer.Path_.Class) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command12_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.AssociatorsOfAsync classSink, "Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices", , , , , , , , , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") obj.AssociatorsAsync_ classSink, "Win32_SystemDevices", , , , , , , , , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command13_Click() Dim myenum As Object Dim computer As SWbemObject Begin On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.ReferencesTo("Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices") Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") Set myenum = obj.References_("Win32_SystemDevices") End If For Each computer In myenum List1.AddItem (computer.Path_.Class) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command14_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.ReferencesToAsync classSink, "Win32_LogicalDisk.DeviceID=""C:""", "Win32_SystemDevices", , , , , , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk.DeviceID=""C:""") obj.ReferencesAsync_ classSink, "Win32_SystemDevices", , , , , , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command15_Click() Dim myenum As Object Dim ev As SWbemObject Begin On Error GoTo ErrorHandler Set myenum = services.ExecNotificationQuery("select * from __InstanceCreationEvent where TargetInstance isa ""Rogers""") For Each ev In myenum List1.AddItem (ev.Path_.Class) Exit For Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command16_Click() Begin On Error GoTo ErrorHandler services.ExecNotificationQueryAsync classSink, "select * from __InstanceCreationEvent where TargetInstance isa ""Rogers""", , , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command17_Click() Dim rogers As SWbemObject Dim path As SWbemObjectPath Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers.num=1") rogers.Dummy = rogers.Dummy + 1 Set path = rogers.Put_ Status.Caption = "Completed" ObjectPathLabel.Caption = path.path Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command18_Click() Dim rogers As SWbemObject Dim result As Object Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers.num=1") rogers.Dummy = rogers.Dummy + 1 rogers.PutAsync_ someSink, , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command19_Click() Dim rogers As SWbemObject Dim path As SWbemObjectPath Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers") Set path = rogers.Put_ Status.Caption = "Completed" ObjectPathLabel.Caption = path.path Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command2_Click() Begin On Error GoTo ErrorHandler services.ExecQueryAsync someSink, QueryBox.Text, , , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command20_Click() Dim rogers As SWbemObject Dim result As Object Begin On Error GoTo ErrorHandler Set rogers = services.Get("Rogers") rogers.Dummy = rogers.Dummy + 1 rogers.PutAsync_ someSink, , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command3_Click() Dim disk As SWbemObject Begin On Error GoTo ErrorHandler Set disk = services.Get("Win32_LogicalDisk.DeviceID=""C:""") List1.AddItem (disk.DeviceID) Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command4_Click() Dim result As Object Begin On Error GoTo ErrorHandler services.GetAsync someSink, "Win32_LogicalDisk.DeviceID=""C:""", , , tmpContext Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command5_Click() Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.Delete ("Rogers.num=1") Else List1.AddItem ("Object Operation") Set obj = services.Get("Rogers.num=1") obj.Delete_ End If Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command6_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.DeleteAsync someSink, "Rogers.num=1", , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Rogers.num=1") obj.DeleteAsync_ someSink, , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command7_Click() Begin On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.InstancesOf("Win32_LogicalDisk") Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk") Set myenum = obj.Instances_ End If For Each disk In myenum List1.AddItem (disk.DeviceID) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command8_Click() Dim result As Object Begin On Error GoTo ErrorHandler If Check1 = 0 Then services.InstancesOfAsync someSink, "Win32_LogicalDisk", , , tmpContext Else List1.AddItem ("Object Operation") Set obj = services.Get("Win32_LogicalDisk") obj.InstancesAsync_ someSink, , , tmpContext End If Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub Command9_Click() Begin Dim myClass As SWbemObject On Error GoTo ErrorHandler If Check1 = 0 Then Set myenum = services.SubclassesOf("Cim_LogicalDevice") Else List1.AddItem ("Object Operation") Set obj = services.Get("Cim_LogicalDevice") Set myenum = obj.Subclasses_ End If For Each myClass In myenum List1.AddItem (myClass.Path_.Class) Next Status.Caption = "Completed" Exit Sub ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) End Sub Private Sub DeleteContext_Click() context.DeleteAll ContextList.Clear End Sub Private Sub Form_Load() 'Set services = GetObject("WinMgmts:") Set locator = CreateObject("WbemScripting.SWbemLocator") Set services = locator.ConnectServer() services.Security_.ImpersonationLevel = wbemImpersonationLevelImpersonate Set someSink = New SWbemSink Set classSink = New SWbemSink Set context = New SWbemNamedValueSet On Error GoTo ErrorHandler Set tmpSink1 = someSink Set tmpSink2 = someSink Set tmpSink3 = someSink Set tmpSink4 = someSink Set tmpSink5 = someSink Set tmpSink6 = someSink Set tmpSink7 = someSink Set tmpSink8 = someSink Set tmpSink9 = someSink Set tmpSink10 = someSink Set tmpSink11 = someSink Set tmpSink12 = someSink Set tmpSink13 = someSink Set tmpSink14 = someSink Set tmpSink15 = someSink Set tmpSink16 = someSink Set tmpSink17 = someSink ErrorHandler: Call HandleErrors(Err.Number, Err.Description, Nothing) myimage = True End Sub Private Sub someSink_OnCompleted(ByVal hResult As WbemScripting.WbemErrorEnum, ByVal pErrorObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) Dim str As String GetErrorString hResult, str Call DisplayContext("OnCompleted(" & str & ") ", pAsyncContext) Call HandleErrors(hResult, "", pErrorObject) End Sub Private Sub someSink_OnObjectPut(ByVal pObjectPath As WbemScripting.ISWbemObjectPath, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) DisplayContext "OnObjectPut", pAsyncContext ObjectPathLabel.Caption = pObjectPath.path End Sub Private Sub someSink_OnObjectReady(ByVal pObject As WbemScripting.ISWbemObject, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) DisplayContext "OnObjectReady", pAsyncContext List1.AddItem (pObject.Path_.RelPath) End Sub Private Sub someSink_OnProgress(ByVal upperBound As Long, ByVal current As Long, ByVal message As String, ByVal pAsyncContext As WbemScripting.ISWbemNamedValueSet) DisplayContext "OnProgress", pAsyncContext MsgBox ("OnProgress called - upper: " & upperBound & " current: " & current & " str: " & message) End Sub Private Sub Timer1_Timer() If myimage = True Then Image1.Picture = Image2.Picture myimage = False Else Image1.Picture = Image3.Picture myimage = True End If End Sub Private Sub HandleErrors(ByVal hResult As Long, ByVal str As String, ByVal pErrorObject As WbemScripting.ISWbemObject) Dim tmpStr As String Status.Caption = "Completed" LastError.Caption = hResult GetErrorString hResult, tmpStr LastErrorString.Caption = tmpStr End Sub Private Sub GetErrorString(ByVal hResult As Long, ByRef str As String) If (hResult = 0) Then str = "Success" ElseIf (str = "") Then Select Case hResult Case WbemErrorEnum.wbemErrFailed str = "wbemErrFailed" Case WbemErrorEnum.wbemErrNotFound str = "wbemErrNotFound" Case WbemErrorEnum.wbemErrAccessDenied str = "wbemErrAccessDenied" Case WbemErrorEnum.wbemErrProviderFailure str = "wbemErrProviderFailure" Case WbemErrorEnum.wbemErrTypeMismatch str = "wbemErrTypeMismatch" Case WbemErrorEnum.wbemErrOutOfMemory str = "wbemErrOutOfMemory" Case WbemErrorEnum.wbemErrInvalidContext str = "wbemErrInvalidContext" Case WbemErrorEnum.wbemErrInvalidParameter str = "wbemErrInvalidParameter" Case WbemErrorEnum.wbemErrNotAvailable str = "wbemErrNotAvailable" Case WbemErrorEnum.wbemErrCriticalError str = "wbemErrCriticalError" Case WbemErrorEnum.wbemErrInvalidStream str = "wbemErrInvalidStream" Case WbemErrorEnum.wbemErrNotSupported str = "wbemErrNotSupported" Case WbemErrorEnum.wbemErrInvalidSuperclass str = "wbemErrInvalidSuperclass" Case WbemErrorEnum.wbemErrInvalidNamespace str = "wbemErrInvalidNamespace" Case WbemErrorEnum.wbemErrInvalidObject str = "wbemErrInvalidObject" Case WbemErrorEnum.wbemErrInvalidClass str = "wbemErrInvalidClass" Case WbemErrorEnum.wbemErrProviderNotFound str = "wbemErrProviderNotFound" Case WbemErrorEnum.wbemErrInvalidProviderRegistration str = "wbemErrInvalidProviderRegistration" Case WbemErrorEnum.wbemErrProviderLoadFailure str = "wbemErrProviderLoadFailure" Case WbemErrorEnum.wbemErrInitializationFailure str = "wbemErrInitializationFailure" Case WbemErrorEnum.wbemErrTransportFailure str = "wbemErrTransportFailure" Case WbemErrorEnum.wbemErrInvalidOperation str = "wbemErrInvalidOperation" Case WbemErrorEnum.wbemErrInvalidQuery str = "wbemErrInvalidQuery" Case WbemErrorEnum.wbemErrInvalidQueryType str = "wbemErrInvalidQueryType" Case WbemErrorEnum.wbemErrAlreadyExists str = "wbemErrAlreadyExists" Case WbemErrorEnum.wbemErrOverrideNotAllowed str = "wbemErrOverrideNotAllowed" Case WbemErrorEnum.wbemErrPropagatedQualifier str = "wbemErrPropagatedQualifier" Case WbemErrorEnum.wbemErrPropagatedProperty str = "wbemErrPropagatedProperty" Case WbemErrorEnum.wbemErrUnexpected str = "wbemErrUnexpected" Case WbemErrorEnum.wbemErrIllegalOperation str = "wbemErrIllegalOperation" Case WbemErrorEnum.wbemErrCannotBeKey str = "wbemErrCannotBeKey" Case WbemErrorEnum.wbemErrIncompleteClass str = "wbemErrIncompleteClass" Case WbemErrorEnum.wbemErrInvalidSyntax str = "wbemErrInvalidSyntax" Case WbemErrorEnum.wbemErrNondecoratedObject str = "wbemErrNondecoratedObject" Case WbemErrorEnum.wbemErrReadOnly str = "wbemErrReadOnly" Case WbemErrorEnum.wbemErrProviderNotCapable str = "wbemErrProviderNotCapable" Case WbemErrorEnum.wbemErrClassHasChildren str = "wbemErrClassHasChildren" Case WbemErrorEnum.wbemErrClassHasInstances str = "wbemErrClassHasInstances" Case WbemErrorEnum.wbemErrQueryNotImplemented str = "wbemErrQueryNotImplemented" Case WbemErrorEnum.wbemErrIllegalNull str = "wbemErrIllegalNull" Case WbemErrorEnum.wbemErrInvalidQualifierType str = "wbemErrInvalidQualifierType" Case WbemErrorEnum.wbemErrInvalidPropertyType str = "wbemErrInvalidPropertyType" Case WbemErrorEnum.wbemErrValueOutOfRange str = "wbemErrValueOutOfRange" Case WbemErrorEnum.wbemErrCannotBeSingleton str = "wbemErrCannotBeSingleton" Case WbemErrorEnum.wbemErrInvalidCimType str = "wbemErrInvalidCimType" Case WbemErrorEnum.wbemErrInvalidMethod str = "wbemErrInvalidMethod" Case WbemErrorEnum.wbemErrInvalidMethodParameters str = "wbemErrInvalidMethodParameters" Case WbemErrorEnum.wbemErrSystemProperty str = "wbemErrSystemProperty" Case WbemErrorEnum.wbemErrInvalidProperty str = "wbemErrInvalidProperty" Case WbemErrorEnum.wbemErrCallCancelled str = "wbemErrCallCancelled" Case WbemErrorEnum.wbemErrShuttingDown str = "wbemErrShuttingDown" Case WbemErrorEnum.wbemErrPropagatedMethod str = "wbemErrPropagatedMethod" Case WbemErrorEnum.wbemErrUnsupportedParameter str = "wbemErrUnsupportedParameter" Case WbemErrorEnum.wbemErrMissingParameter str = "wbemErrMissingParameter" Case WbemErrorEnum.wbemErrInvalidParameterId str = "wbemErrInvalidParameterId" Case WbemErrorEnum.wbemErrNonConsecutiveParameterIds str = "wbemErrNonConsecutiveParameterIds" Case WbemErrorEnum.wbemErrParameterIdOnRetval str = "wbemErrParameterIdOnRetval" Case WbemErrorEnum.wbemErrInvalidObjectPath str = "wbemErrInvalidObjectPath" Case WbemErrorEnum.wbemErrOutOfDiskSpace str = "wbemErrOutOfDiskSpace" Case WbemErrorEnum.wbemErrRegistrationTooBroad str = "wbemErrRegistrationTooBroad" Case WbemErrorEnum.wbemErrRegistrationTooPrecise str = "wbemErrRegistrationTooPrecise" Case WbemErrorEnum.wbemErrTimedout str = "wbemErrTimedout" Case Else str = hResult End Select End If End Sub Private Sub Begin() List1.Clear ContextResults.Clear Status.Caption = "In Progress" ObjectPathLabel.Caption = "Null" If (context.Count = 0) Then Set tmpContext = Nothing Else Set tmpContext = context End If End Sub Private Sub DisplayContext(ByVal str As String, Optional ByVal asyncContext As WbemScripting.ISWbemNamedValueSet) Dim i As SWbemNamedValue ContextResults.AddItem (str) If asyncContext Is Nothing Then ContextResults.AddItem ("Empty") Else For Each i In asyncContext ContextResults.AddItem (i.Name & "=" & i.Value) Next End If End Sub

<reponame>LaudateCorpus1/RosettaCodeData Public Sub circles() tests = [{0.1234, 0.9876, 0.8765, 0.2345, 2.0; 0.0000, 2.0000, 0.0000, 0.0000, 1.0; 0.1234, 0.9876, 0.1234, 0.9876, 2.0; 0.1234, 0.9876, 0.8765, 0.2345, 0.5; 0.1234, 0.9876, 0.1234, 0.9876, 0.0}] For i = 1 To UBound(tests) x1 = tests(i, 1) y1 = tests(i, 2) x2 = tests(i, 3) y2 = tests(i, 4) R = tests(i, 5) xd = x2 - x1 yd = y1 - y2 s2 = xd * xd + yd * yd sep = Sqr(s2) xh = (x1 + x2) / 2 yh = (y1 + y2) / 2 Dim txt As String If sep = 0 Then txt = "same points/" & IIf(R = 0, "radius is zero", "infinite solutions") Else If sep = 2 * R Then txt = "opposite ends of diameter with centre " & xh & ", " & yh & "." Else If sep > 2 * R Then txt = "too far apart " & sep & " > " & 2 * R Else md = Sqr(R * R - s2 / 4) xs = md * xd / sep ys = md * yd / sep txt = "{" & Format(xh + ys, "0.0000") & ", " & Format(yh + xs, "0.0000") & _ "} and {" & Format(xh - ys, "0.0000") & ", " & Format(yh - xs, "0.0000") & "}" End If End If End If Debug.Print "points " & "{" & x1 & ", " & y1 & "}" & ", " & "{" & x2 & ", " & y2 & "}" & " with radius " & R & " ==> " & txt Next i End Sub

VERSION 5.00 Begin VB.Form Form1 Caption = "Form1" ClientHeight = 3675 ClientLeft = 120 ClientTop = 465 ClientWidth = 5580 LinkTopic = "Form1" ScaleHeight = 245 ScaleMode = 3 'Pixel ScaleWidth = 372 StartUpPosition = 3 'Windows Default Begin VB.PictureBox Pic AutoRedraw = -1 'True AutoSize = -1 'True Height = 3015 Left = 0 ScaleHeight = 197 ScaleMode = 3 'Pixel ScaleWidth = 253 TabIndex = 0 Top = 0 Width = 3855 End End Attribute VB_Name = "Form1" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Const RED As Integer = &HF800 Const GREEN As Integer = &H7E0 Const BLUE As Integer = &H1F Private Function ConvertRGB888ToRGB565(RGB888 As Long) As Integer Dim RGB888Val() As Byte RGB888Val = GetRGB(RGB888) Dim R As Byte Dim G As Byte Dim B As Byte R = RGB888Val(0) G = RGB888Val(1) B = RGB888Val(2) ConvertRGB888ToRGB565 = (SHL16(R, 8) And RED) Or (SHL16(G, 3) And GREEN) Or (SHR16(B, 3) And BLUE) End Function Private Sub OpenOutputFile() Dim SplitPath() As String Dim OutputPath As String SplitPath = Split(VBA.Command$, ".") If UBound(SplitPath()) > 0 Then SplitPath(UBound(SplitPath())) = "SP" OutputPath = Join(SplitPath(), ".") Else OutputPath = VBA.Command$ & ".SP" End If On Error Resume Next Kill OutputPath On Error GoTo 0 Open OutputPath For Binary Access Write As #1 End Sub Private Sub CloseOutputFile() Close #1 End Sub Private Sub Form_Load() If VBA.Command$ = "" Then MsgBox "No input file!", vbCritical End End If On Error GoTo Err Set Pic.Picture = LoadPicture(VBA.Command$) OpenOutputFile Dim PicWidth As Integer Dim PicHeight As Integer PicWidth = Pic.ScaleWidth PicHeight = Pic.ScaleHeight Put #1, , PicWidth Put #1, , PicHeight Dim x As Long Dim y As Long For y = 0 To PicHeight - 1 For x = 0 To PicWidth - 1 Put #1, , ConvertRGB888ToRGB565(Pic.Point(x, y)) Next x Next y CloseOutputFile MsgBox "Done", vbInformation End Err: MsgBox Err.Description, vbCritical End End Sub

<reponame>MakeNowJust/quine Imports System Module Main Sub Main() Dim s As String = "Imports System{0}Module Main{0} Sub Main(){0} Dim s As String = {1}{2}{1}{0} Console.WriteLine(s,Chr(10),Chr(34),s){0} End Sub{0}End Module" Console.WriteLine(s,Chr(10),Chr(34),s) End Sub End Module

<gh_stars>10-100 Attribute VB_Name = "Errors" Option Explicit Const FACILITY_WIN32 As Long = 7 ' These are Win32 Errors. ' They are tested against returns from WIN32 APIS using these ' error codes, BUT They must be translated into COM Errors ' using the HRESULT_FROM_WIN32 function below when ' returning then from a COM Object Public Const ERROR_FILE_NOT_FOUND As Long = 2 Public Const ERROR_DISK_FULL As Long = 112 ' These Are COM Errors Public Const E_NOTIMPL As Long = &H80004001 Public Const E_FAIL As Long = &H80004005 Public Const E_INVALIDARG As Long = &H80070057 Public Const E_UNEXPECTED As Long = &H8000FFFF Public Const errBase As Long = vbObject + 9999 Public Const errContainsGarbageChar As Long = errBase + 1 Public Const errContainsStopSign As Long = errBase + 2 Public Const errContainsStopWord As Long = errBase + 3 Public Const errContainsOperatorShortcut As Long = errBase + 4 Public Const errContainsVerbalOperator As Long = errBase + 5 Public Const errAlreadyExists As Long = errBase + 6 Public Const errDoesNotExist As Long = errBase + 7 Public Const errTooLong As Long = errBase + 8 Public Const errMultiWord As Long = errBase + 9 Public Const errCancel As Long = errBase + 10 Public Const errRefNodeCannotBeDescendent As Long = errBase + 11 Public Const errDatabaseVersionIncompatible As Long = errBase + 12 Public Const errNotConfiguredForNavigateLink As Long = errBase + 13 Public Const errContainsQuote As Long = errBase + 14 Public Const errParentCannotBeLeaf As Long = errBase + 15 Public Const errBadKeywordsFormat As Long = errBase + 16 Public Const errNodeOrTopicAlreadyModified As Long = errBase + 17 Public Const errBadSpreadsheet As Long = errBase + 18 Public Const errOutOfOrderingNumbers As Long = errBase + 19 Public Const errNotPermittedForAuthoringGroup As Long = errBase + 20 Public Const errAuthoringGroupDiffers As Long = errBase + 21 Public Const errAuthoringGroupNotPresent As Long = errBase + 22 Public Const errVendorStringNotConfigured As Long = errBase + 23 Public Const errProductIdOrVersionMissing As Long = errBase + 24 Function HRESULT_FROM_WIN32(ByVal lngWin32Err As Long) As Long If (lngWin32Err <> 0) Then HRESULT_FROM_WIN32 = lngWin32Err And &HFFFF HRESULT_FROM_WIN32 = HRESULT_FROM_WIN32 Or (FACILITY_WIN32 * &H10000) HRESULT_FROM_WIN32 = HRESULT_FROM_WIN32 Or &H80000000 Else HRESULT_FROM_WIN32 = 0 End If End Function Public Sub DisplayDatabaseLockedError( _ ) MsgBox "The database is locked because another user is saving his/her changes. " & _ "Please try again later.", vbExclamation + vbOKOnly End Sub Public Sub DisplayDatabaseVersionError( _ ) MsgBox "The database version is incompatible.", vbExclamation + vbOKOnly End Sub Public Sub DisplayAuthoringGroupError( _ ) Select Case Err.Number Case errNotPermittedForAuthoringGroup MsgBox "Your Authoring Group does not have sufficient permissions to " & _ "perform this operation.", _ vbExclamation + vbOKOnly Case errAuthoringGroupDiffers MsgBox "You cannot modify something that was created in a different " & _ "Authoring Group.", _ vbExclamation + vbOKOnly Case errAuthoringGroupNotPresent MsgBox "The Database has not been configured with an Authoring Group.", _ vbExclamation + vbOKOnly End Select End Sub

on error resume next set l = CreateObject ("WbemScripting.SwbemLocator") set ns = l.Open ("root\cimv2") ns.filter_ = Array ("Win32_service") for each p in ns WScript.Echo p.Path_.Path next set os = ns.ExecQuery ("select * from win32_process go select * from win32_service") for each p in os WScript.Echo p.Name next

<reponame>LaudateCorpus1/RosettaCodeData 'N-queens problem - non recursive & structured - vbs - 24/02/2017 const l=15 dim a(),s(),u(): redim a(l),s(l),u(4*l-2) for i=1 to l: a(i)=i: next for n=1 to l m=0 i=1 j=0 r=2*n-1 Do i=i-1 j=j+1 p=0 q=-r Do i=i+1 u(p)=1 u(q+r)=1 z=a(j): a(j)=a(i): a(i)=z 'swap a(i),a(j) p=i-a(i)+n q=i+a(i)-1 s(i)=j j=i+1 Loop Until j>n Or u(p)<>0 Or u(q+r)<>0 If u(p)=0 Then If u(q+r)=0 Then m=m+1 'm: number of solutions 'x="": for k=1 to n: x=x&" "&a(k): next: msgbox x,,m End If End If j=s(i) Do While j>=n And i<>0 Do z=a(j): a(j)=a(i): a(i)=z 'swap a(i),a(j) j=j-1 Loop Until j<i i=i-1 p=i-a(i)+n q=i+a(i)-1 j=s(i) u(p)=0 u(q+r)=0 Loop Loop Until i=0 wscript.echo n &":"& m next 'n

'//+---------------------------------------------------------------------------- '// '// File: cab.frm '// '// Module: pbadmin.exe '// '// Synopsis: The options dialog in PBA '// '// Copyright (c) 1997-1999 Microsoft Corporation '// '// Author: quintinb Created Header 09/02/99 '// '//+---------------------------------------------------------------------------- VERSION 5.00 Object = "{F9043C88-F6F2-101A-A3C9-08002B2F49FB}#1.2#0"; "COMDLG32.OCX" Begin VB.Form frmCab BorderStyle = 3 'Fixed Dialog Caption = "options" ClientHeight = 2595 ClientLeft = 2775 ClientTop = 1545 ClientWidth = 5955 Icon = "cab.frx":0000 KeyPreview = -1 'True LinkTopic = "Form1" LockControls = -1 'True MaxButton = 0 'False MinButton = 0 'False PaletteMode = 1 'UseZOrder ScaleHeight = 2595 ScaleWidth = 5955 ShowInTaskbar = 0 'False WhatsThisButton = -1 'True WhatsThisHelp = -1 'True Begin VB.CommandButton Command1 Cancel = -1 'True Caption = "cancel" Height = 375 Left = 4425 TabIndex = 7 Top = 2070 WhatsThisHelpID = 10040 Width = 1335 End Begin VB.CommandButton cmbcab Caption = "ok" Default = -1 'True Height = 375 Left = 4410 TabIndex = 6 Top = 1530 WhatsThisHelpID = 10030 Width = 1335 End Begin VB.TextBox txtUrl Height = 285 Left = 225 MaxLength = 100 TabIndex = 1 Top = 495 WhatsThisHelpID = 70000 Width = 5520 End Begin VB.TextBox UIDText Height = 315 Left = 210 MaxLength = 64 TabIndex = 3 Top = 1350 WhatsThisHelpID = 70010 Width = 2730 End Begin VB.TextBox PWDText Height = 330 IMEMode = 3 'DISABLE Left = 225 MaxLength = 64 PasswordChar = "*" TabIndex = 5 Top = 2085 WhatsThisHelpID = 70020 Width = 2715 End Begin MSComDlg.CommonDialog CommonDialog1 Left = 2940 Top = -30 _ExtentX = 847 _ExtentY = 847 _Version = 393216 End Begin VB.Label ServerLabel BackStyle = 0 'Transparent Caption = "server" Height = 255 Left = 210 TabIndex = 0 Top = 240 WhatsThisHelpID = 70000 Width = 5520 End Begin VB.Label UIDLabel BackStyle = 0 'Transparent Caption = "uid" Height = 255 Left = 225 TabIndex = 2 Top = 1125 WhatsThisHelpID = 70010 Width = 2790 End Begin VB.Label pwdLabel BackStyle = 0 'Transparent Caption = "pwd" Height = 270 Left = 225 TabIndex = 4 Top = 1815 WhatsThisHelpID = 70020 Width = 2670 End End Attribute VB_Name = "frmcab" Attribute VB_GlobalNameSpace = False Attribute VB_Creatable = False Attribute VB_PredeclaredId = True Attribute VB_Exposed = False Option Explicit Dim configuration As Recordset Function LoadOptionsRes() Dim cRef As Integer On Error GoTo LoadErr cRef = 5200 Me.Caption = LoadResString(cRef + 25) & " " & gsCurrentPB ServerLabel.Caption = LoadResString(cRef + 21) UIDLabel.Caption = LoadResString(cRef + 22) pwdLabel.Caption = LoadResString(cRef + 23) cmbcab.Caption = LoadResString(1002) Command1.Caption = LoadResString(1003) ' set fonts SetFonts Me On Error GoTo 0 Exit Function LoadErr: Exit Function End Function Function TrimURL(URL As String) As String URL = Trim(URL) TrimURL = URL If LCase(Left(URL, 4)) = "ftp:" Then TrimURL = Right(URL, Len(URL) - 4) End If If LCase(Left(URL, 5)) = "http:" Then TrimURL = Right(URL, Len(URL) - 5) End If Do While Left(TrimURL, 1) = "/" TrimURL = Right(TrimURL, Len(TrimURL) - 1) Loop Do While Left(TrimURL, 1) = "\" TrimURL = Right(TrimURL, Len(TrimURL) - 1) Loop End Function Private Sub cmbcab_Click() Dim rt As Integer Screen.MousePointer = 11 rt = SetOptions(txtUrl.Text, UIDText.Text, PWDText.Text) If rt = 1 Then UIDText.SetFocus ElseIf rt = 2 Then PWDText.SetFocus End If Screen.MousePointer = 0 Unload Me Exit Sub ErrTrap: Screen.MousePointer = 0 MsgBox LoadResString(6056) & Chr(13) & Chr(13) & Err.Description, vbExclamation Exit Sub Exit Sub End Sub Private Sub Command1_Click() Unload Me End Sub Private Sub Form_Activate() txtUrl.SetFocus End Sub Private Sub Form_KeyPress(KeyAscii As Integer) CheckChar KeyAscii End Sub Private Sub Form_Load() Dim RS, configuration As Recordset Dim i As Integer Dim myPos As Integer On Error GoTo LoadErr If gsCurrentPB = "" Then Exit Sub End If CenterForm Me, Screen 'SSTab1.Tab = 0 LoadOptionsRes Set configuration = gsyspb.OpenRecordset("Configuration", dbOpenSnapshot) If configuration.RecordCount <> 0 Then If Not IsNull(configuration!URL) Then txtUrl.Text = configuration!URL End If If Not IsNull(configuration!ServerPWD) Then PWDText.Text = configuration!ServerPWD End If If Not IsNull(configuration!ServerUID) Then UIDText.Text = configuration!ServerUID End If End If configuration.Close Set configuration = Nothing Screen.MousePointer = 0 Exit Sub LoadErr: Screen.MousePointer = 0 MsgBox LoadResString(6056) & Chr(13) & Chr(13) & Err.Description, vbExclamation End Sub Private Sub LoadList(list As Control, sTableName As String, sName As String, sID As String) Dim RS As Recordset list.Clear Set Gsyspbpost = DBEngine.Workspaces(0).OpenDatabase(locPath + "pbserver.mdb") Set RS = Gsyspbpost.OpenRecordset("SELECT " & sName & "," & sID & " FROM " & sTableName) While Not RS.EOF list.AddItem RS(sName) list.ItemData(list.NewIndex) = RS(sID) RS.MoveNext Wend RS.Close Gsyspbpost.Close End Sub Sub selectListItem(list As Control, ByVal ID As Long) Dim i As Integer For i = 0 To list.ListCount - 1 If list.ItemData(i) = ID Then list.Selected(i) = True End If Next i End Sub Private Sub Form_QueryUnload(Cancel As Integer, UnloadMode As Integer) If UnloadMode = vbFormControlMenu Then Cancel = False Command1_Click End If End Sub Private Sub Form_Unload(Cancel As Integer) Set configuration = Nothing End Sub Private Sub PWDText_GotFocus() SelectText PWDText End Sub Private Sub txtUrl_GotFocus() SelectText txtUrl End Sub Private Sub txtUrl_KeyPress(KeyAscii As Integer) Select Case KeyAscii Case 32 'space KeyAscii = 0 Beep 'MsgBox LoadResString(6018), vbInformation End Select End Sub Private Sub UIDText_GotFocus() SelectText UIDText End Sub Private Sub UIDText_KeyPress(KeyAscii As Integer) Select Case KeyAscii '0-9 a-z A-Z Bkspc ctrl-C ctrl-V 'Case 48 To 57, 97 To 122, 65 To 90, 8, 3, 22 ' do nothing ' upper case 'Case 48 To 57 ' KeyAscii = KeyAscii + 32 ' shift to lower case 'Case Else ' KeyAscii = 0 ' Beep ' MsgBox LoadResString(6018), vbInformation Case 32 'space KeyAscii = 0 Beep Case Else 'do nothing End Select End Sub

<filename>Task/Function-composition/VBScript/function-composition-1.vb option explicit class closure private composition sub compose( f1, f2 ) composition = f2 & "(" & f1 & "(p1))" end sub public default function apply( p1 ) apply = eval( composition ) end function public property get formula formula = composition end property end class

<reponame>mullikine/RosettaCodeData<filename>Task/Stable-marriage-problem/VBA/stable-marriage-problem-1.vba Sub M_snb() c00 = "_abe abi eve cath ivy jan dee fay bea hope gay " & _ "_bob cath hope abi dee eve fay bea jan ivy gay " & _ "_col hope eve abi dee bea fay ivy gay cath jan " & _ "_dan ivy fay dee gay hope eve jan bea cath abi " & _ "_ed jan dee bea cath fay eve abi ivy hope gay " & _ "_fred bea abi dee gay eve ivy cath jan hope fay " & _ "_gav gay eve ivy bea cath abi dee hope jan fay " & _ "_hal abi eve hope fay ivy cath jan bea gay dee " & _ "_ian hope cath dee gay bea abi fay ivy jan eve " & _ "_jon abi fay jan gay eve bea dee cath ivy hope " & _ "_abi bob fred jon gav ian abe dan ed col hal " & _ "_bea bob abe col fred gav dan ian ed jon hal " & _ "_cath fred bob ed gav hal col ian abe dan jon " & _ "_dee fred jon col abe ian hal gav dan bob ed " & _ "_eve jon hal fred dan abe gav col ed ian bob " & _ "_fay bob abe ed ian jon dan fred gav col hal " & _ "_gay jon gav hal fred bob abe col ed dan ian " & _ "_hope gav jon bob abe ian dan hal ed col fred " & _ "_ivy ian col hal gav fred bob abe ed jon dan " & _ "_jan ed hal gav abe bob jon col ian fred dan " sn = Filter(Filter(Split(c00), "_"), "-", 0) Do c01 = Mid(c00, InStr(c00, sn(0) & " ")) st = Split(Left(c01, InStr(Mid(c01, 2), "_"))) For j = 1 To UBound(st) - 1 If InStr(c00, "_" & st(j) & " ") > 0 Then c00 = Replace(Replace(c00, sn(0), sn(0) & "-" & st(j)), "_" & st(j), "_" & st(j) & "." & Mid(sn(0), 2)) Exit For Else c02 = Filter(Split(c00, "_"), st(j) & ".")(0) c03 = Split(Split(c02)(0), ".")(1) If InStr(c02, " " & Mid(sn(0), 2) & " ") < InStr(c02, " " & c03 & " ") Then c00 = Replace(Replace(Replace(c00, c03 & "-" & st(j), c03), sn(0), sn(0) & "-" & st(j)), "_" & st(j), "_" & st(j) & "." & Mid(sn(0), 2)) Exit For End If End If Next sn = Filter(Filter(Filter(Split(c00), "_"), "-", 0), ".", 0) Loop Until UBound(sn) = -1 MsgBox Replace(Join(Filter(Split(c00), "-"), vbLf), "_", "") End Sub

<gh_stars>1-10 Dim onlyInstance as Boolean onlyInstance = not App.PrevInstance

For k = 1 To 5 count = 0 increment = 1 WScript.StdOut.Write "K" & k & ": " Do Until count = 10 If PrimeFactors(increment) = k Then WScript.StdOut.Write increment & " " count = count + 1 End If increment = increment + 1 Loop WScript.StdOut.WriteLine Next Function PrimeFactors(n) PrimeFactors = 0 arrP = Split(ListPrimes(n)," ") divnum = n Do Until divnum = 1 For i = 0 To UBound(arrP)-1 If divnum = 1 Then Exit For ElseIf divnum Mod arrP(i) = 0 Then divnum = divnum/arrP(i) PrimeFactors = PrimeFactors + 1 End If Next Loop End Function Function IsPrime(n) If n = 2 Then IsPrime = True ElseIf n <= 1 Or n Mod 2 = 0 Then IsPrime = False Else IsPrime = True For i = 3 To Int(Sqr(n)) Step 2 If n Mod i = 0 Then IsPrime = False Exit For End If Next End If End Function Function ListPrimes(n) ListPrimes = "" For i = 1 To n If IsPrime(i) Then ListPrimes = ListPrimes & i & " " End If Next End Function

'*************************************************************************** 'This script tests the manipulation of qualifier values, in the case that the 'qualifier is an array type '*************************************************************************** Set Service = GetObject("winmgmts:root/default") On Error Resume Next Set aClass = Service.Get() aClass.Path_.Class = "ARRAYQUAL00" aClass.Qualifiers_.Add "q1", Array (1, 20, 3) str = "The initial value of q1 is [1,20,3]: {" for x=LBound(aClass.Qualifiers_("q1")) to UBound(aClass.Qualifiers_("q1")) str = str & aClass.Qualifiers_("q1")(x) if x <> UBound(aClass.Qualifiers_("q1")) Then str = str & ", " End if next str = str & "}" WScript.Echo str WScript.Echo "" 'Verify we can report the value of an element of the qualifier value v = aClass.Qualifiers_("q1") WScript.Echo "By indirection the first element of q1 has value [1]:",v(0) 'Verify we can report the value directly WScript.Echo "By direct access the first element of q1 has value [1]:", aClass.Qualifiers_("q1")(0) 'Verify we can set the value of a single qualifier value element aClass.Qualifiers_("q1")(1) = 11 WScript.Echo "After direct assignment the second element of q1 has value [11]:", aClass.Qualifiers_("q1")(1) Set Qualifier = aClass.Qualifiers_("q1") Qualifier.Value(2) = 37 WScript.Echo "After direct assignment the third element of q1 has value [37]:", aClass.Qualifiers_("q1")(2) 'Verify we can set the value of a single qualifier value element Set v = aClass.Qualifiers_("q1") v(1) = 345 WScript.Echo "After indirect assignment the first element of q1 has value [345]:", aClass.Qualifiers_("q1")(1) 'Verify we can set the value of an entire qualifier value aClass.Qualifiers_("q1") = Array (5, 34, 178871) WScript.Echo "After direct array assignment the second element of q1 has value [34]:", aClass.Qualifiers_("q1")(1) str = "After direct assignment the entire value of q1 is [5,34,178871] {" for x=LBound(aClass.Qualifiers_("q1")) to UBound(aClass.Qualifiers_("q1")) str = str & aClass.Qualifiers_("q1")(x) if x <> UBound(aClass.Qualifiers_("q1")) Then str = str & ", " End if next str = str & "}" WScript.Echo str aClass.Put_ () if Err <> 0 Then WScript.Echo Err.Description Err.Clear End if

<gh_stars>1-10 Function parse_ip(addr) 'ipv4 pattern Set ipv4_pattern = New RegExp ipv4_pattern.Global = True ipv4_pattern.Pattern = "(\d{1,3}\.){3}\d{1,3}" 'ipv6 pattern Set ipv6_pattern = New RegExp ipv6_pattern.Global = True ipv6_pattern.Pattern = "([0-9a-fA-F]{0,4}:){2}[0-9a-fA-F]{0,4}" 'test if address is ipv4 If ipv4_pattern.Test(addr) Then port = Split(addr,":") octet = Split(port(0),".") ipv4_hex = "" For i = 0 To UBound(octet) If octet(i) <= 255 And octet(i) >= 0 Then ipv4_hex = ipv4_hex & Right("0" & Hex(octet(i)),2) Else ipv4_hex = "Erroneous Address" Exit For End If Next parse_ip = "Test Case: " & addr & vbCrLf &_ "Address: " & ipv4_hex & vbCrLf If UBound(port) = 1 Then If port(1) <= 65535 And port(1) >= 0 Then parse_ip = parse_ip & "Port: " & port(1) & vbCrLf Else parse_ip = parse_ip & "Port: Invalid" & vbCrLf End If End If End If 'test if address is ipv6 If ipv6_pattern.Test(addr) Then parse_ip = "Test Case: " & addr & vbCrLf port_v6 = "Port: " ipv6_hex = "" 'check and extract port information if any If InStr(1,addr,"[") Then 'extract the port port_v6 = port_v6 & Mid(addr,InStrRev(addr,"]")+2,Len(addr)-Len(Mid(addr,1,InStrRev(addr,"]")+1))) 'extract the address addr = Mid(addr,InStrRev(addr,"[")+1,InStrRev(addr,"]")-(InStrRev(addr,"[")+1)) End If word = Split(addr,":") word_count = 0 For i = 0 To UBound(word) If word(i) = "" Then If i < UBound(word) Then If Int((7-(i+1))/2) = 1 Then k = 1 ElseIf UBound(word) < 6 Then k = Int((7-(i+1))/2) ElseIf UBound(word) >= 6 Then k = Int((7-(i+1))/2)-1 End If For j = 0 To k ipv6_hex = ipv6_hex & "0000" word_count = word_count + 1 Next Else For j = 0 To (7-word_count) ipv6_hex = ipv6_hex & "0000" Next End If Else ipv6_hex = ipv6_hex & Right("0000" & word(i),4) word_count = word_count + 1 End If Next parse_ip = parse_ip & "Address: " & ipv6_hex &_ vbCrLf & port_v6 & vbCrLf End If 'test if the address in invalid If ipv4_pattern.Test(addr) = False And ipv6_pattern.Test(addr) = False Then parse_ip = "Test Case: " & addr & vbCrLf &_ "Address: Invalid Address" & vbCrLf End If End Function 'Testing the function ip_arr = Array("127.0.0.1","127.0.0.1:80","::1",_ "[::1]:80","fc00:e968:6179::de52:7100:93e3","[2605:2fc00:e968:6179::de52:7100:93e3]:80","RosettaCode") For n = 0 To UBound(ip_arr) WScript.StdOut.Write parse_ip(ip_arr(n)) & vbCrLf Next

100 REM **************************** 110 REM MAIN TEST 120 REM **************************** 121 REM 122 REM 125 REM *********** CLEAR ********* 130 CLEAR 135 REM *********** RETURN ********* 140 RETURN 145 REM *********** LIST ********* 150 LIST 155 REM *********** RUN ********* 160 RUN 165 REM *********** END ********* 170 END 175 REM *********** GOTO ********* 180 GOTO 100 185 REM *********** GOSUB ********* 190 GOSUB 100 195 REM *********** LET ********* 180 LET x = 12 185 REM *********** INPUT ********* 200 INPUT "sdsdsd";y 225 REM *********** IF ********* 220 IF x=13 THEN PRINT "xx" 230 REM *********** IF with assign ********* 240 IF x=13 THEN LET y=12 245 IF x=13 THEN y=12 245 REM *********** PRINT ********* 250 PRINT "xx" 260 REM *********** FOR ********* 270 FOR i=10 TO 15 STEP 20 275 FOR i=10 TO 15 260 REM *********** NEXT ********* 261 NEXT i 300 REM *********** DIM ********* 310 DIM j(14) 400 REM *********** SQR ********* 410 LET h = SQR(12) 420 REM *********** CHR ********* 430 LET h = CHR$(12) 440 REM *********** COLON TWO STATEMENTS ********* 450 PRINT "1" : PRINT "2" 460 REM *********** COLON COMMENT ********* 470 PRINT "1" : REM 480 PRINT "1" : REM 44 490 REM *********** NAKED ASSIGN ********* 500 j=77 490 REM *********** PRINT EXPRESSION ********* 510 PRINT CHR$ (7) 1000 TEXT 1010 HGR 490 REM *********** LEN ********* 520 ll = LEN("abc") 490 REM *********** CALL ********* 11 CALL 5010 490 REM *********** ASC ********* 520 ll = ASC("a") 490 REM *********** MID ********* 520 ll = MID$("abc",1,2) 490 REM *********** STRING VAR ********* 520 d$="sdsd" 490 REM *********** PLOT ********* 550 HPLOT 0,YS TO 279,YS 550 VPLOT 0,YS TO 279,YS 560 VPLOT 0,YS TO 279,YS 490 REM *********** PR ********* 1000 PR#1 1001 PR#2 490 REM *********** FLOATS ********* 20 XC = -0.5 : REM CENTER COORD X 30 YC = 0 : REM " " Y 40 S = 2 : REM SCALE 490 REM *********** NEQ ********* 40 IF N< > 0 GOTO 80 490 REM *********** TAB ********* 10 VTAB 6: HTAB 3

Option Base 1 Private Function pivotize(m As Variant) As Variant Dim n As Integer: n = UBound(m) Dim im() As Double ReDim im(n, n) For i = 1 To n For j = 1 To n im(i, j) = 0 Next j im(i, i) = 1 Next i For i = 1 To n mx = m(i, i) row_ = i For j = i To n If m(j, i) > mx Then mx = m(j, i) row_ = j End If Next j If i <> Row Then For j = 1 To n tmp = im(i, j) im(i, j) = im(row_, j) im(row_, j) = tmp Next j End If Next i pivotize = im End Function Private Function lu(a As Variant) As Variant Dim n As Integer: n = UBound(a) Dim l() As Double ReDim l(n, n) For i = 1 To n For j = 1 To n l(i, j) = 0 Next j Next i u = l p = pivotize(a) a2 = WorksheetFunction.MMult(p, a) For j = 1 To n l(j, j) = 1# For i = 1 To j sum1 = 0# For k = 1 To i sum1 = sum1 + u(k, j) * l(i, k) Next k u(i, j) = a2(i, j) - sum1 Next i For i = j + 1 To n sum2 = 0# For k = 1 To j sum2 = sum2 + u(k, j) * l(i, k) Next k l(i, j) = (a2(i, j) - sum2) / u(j, j) Next i Next j Dim res(4) As Variant res(1) = a res(2) = l res(3) = u res(4) = p lu = res End Function Public Sub main() a = [{1, 3, 5; 2, 4, 7; 1, 1, 0}] Debug.Print "== a,l,u,p: ==" result = lu(a) For i = 1 To 4 For j = 1 To UBound(result(1)) For k = 1 To UBound(result(1), 2) Debug.Print result(i)(j, k), Next k Debug.Print Next j Debug.Print Next i a = [{11, 9,24, 2; 1, 5, 2, 6; 3,17,18, 1; 2, 5, 7, 1}] Debug.Print "== a,l,u,p: ==" result = lu(a) For i = 1 To 4 For j = 1 To UBound(result(1)) For k = 1 To UBound(result(1), 2) Debug.Print Format(result(i)(j, k), "0.#####"), Next k Debug.Print Next j Debug.Print Next i End Sub

Const MAX = 20 Const ITER = 1000000 Function expected(n As Long) As Double Dim sum As Double For i = 1 To n sum = sum + WorksheetFunction.Fact(n) / n ^ i / WorksheetFunction.Fact(n - i) Next i expected = sum End Function Function test(n As Long) As Double Dim count As Long Dim x As Long, bits As Long For i = 1 To ITER x = 1 bits = 0 Do While Not bits And x count = count + 1 bits = bits Or x x = 2 ^ (Int(n * Rnd())) Loop Next i test = count / ITER End Function Public Sub main() Dim n As Long Debug.Print " n avg. exp. (error%)" Debug.Print "== ====== ====== ========" For n = 1 To MAX av = test(n) ex = expected(n) Debug.Print Format(n, "@@"); " "; Format(av, "0.0000"); " "; Debug.Print Format(ex, "0.0000"); " ("; Format(Abs(1 - av / ex), "0.000%"); ")" Next n End Sub

Set objfso = CreateObject("Scripting.FileSystemObject") parent_folder = objfso.GetParentFolderName(WScript.ScriptFullName) & "\" Set objcsv = objfso.OpenTextFile(parent_folder & "in.csv",1,False) Set objhtml = objfso.OpenTextFile(paren_folder & "out.html",2,True) objhtml.Write(csv_to_html(objcsv.ReadAll)) objcsv.Close objhtml.Close Set objfso = Nothing Function csv_to_html(s) row = Split(s,vbCrLf) 'write the header tmp = "<html><head><head/><body><table border=1 cellpadding=10 cellspacing=0>" For i = 0 To UBound(row) field = Split(row(i),",") If i = 0 Then tmp = tmp & "<tr><th>" & replace_chars(field(0)) & "</th><th>" & replace_chars(field(1)) & "</th><tr>" Else tmp = tmp & "<tr><td>" & replace_chars(field(0)) & "</td><td>" & replace_chars(field(1)) & "</td><tr>" End If Next 'write the footer tmp = tmp & "</table></body></html>" csv_to_html = tmp End Function Function replace_chars(s) replace_chars = Replace(Replace(s,"<","<"),">",">") End Function

<reponame>robinkjoy/JSON2RTLRegFile ' Enumerations https://msdn.microsoft.com/en-us/library/office/aa211923(v=office.11).aspx Option Explicit Sub InsertRegTable(oWord, oRange, regStrings) With oRange .Paragraphs.Add With .Paragraphs(1) .Style = -3 .Range.Text = regStrings(0) End With .Paragraphs.Add With .Paragraphs(2) .Style = -1 End With End With oRange.Tables.Add oRange.Paragraphs(2).Range, 4, 5 Dim oTable Set oTable = oRange.Tables(1) ' Set border properties With oTable.Borders .InsideLineStyle = 1 .OutsideLineStyle = 1 End With ' Set table properties With oTable .Columns(1).Width = oWord.InchesToPoints(1.1) .Columns(2).Width = oWord.InchesToPoints(0.5) .Columns(3).Width = oWord.InchesToPoints(0.5) .Columns(4).Width = oWord.InchesToPoints(1.1) .Columns(5).Width = oWord.InchesToPoints(3.2) Dim row For Each row In .Rows row.Cells.VerticalAlignment = 1 Next End With ' Insert table contents SetHeader oTable, 1, 1, "Register Name" oTable.Cell(1, 2).Range.Text = regStrings(1) SetHeader oTable, 2, 1, "Offset" oTable.Cell(2, 2).Range.Text = regStrings(2) SetHeader oTable, 3, 1, "Fields" SetHeader oTable, 4, 1, "Field Name" SetHeader oTable, 4, 2, "Bits" SetHeader oTable, 4, 3, "Type" SetHeader oTable, 4, 4, "Default Value" SetHeader oTable, 4, 5, "Description" ' Merge cells MergeCells oWord.ActiveDocument, oTable, 1, 2, 1, 5 MergeCells oWord.ActiveDocument, oTable, 2, 2, 2, 5 MergeCells oWord.ActiveDocument, oTable, 3, 1, 3, 5 oTable.Cell(3, 1).Range.ParagraphFormat.Alignment = 1 End Sub Sub InsertFieldRow(oTable, fieldStrings) Dim oRow oTable.Rows.Add Set oRow = oTable.Rows(oTable.Rows.Count) Dim i For i = 0 To 4 oRow.Cells(i + 1).Range.Text = fieldStrings(i) oRow.Cells(i + 1).Range.Font.Bold = False Next End Sub Sub MergeCells(doc, oTable, si, sj, ei, ej) doc.Range(oTable.Cell(si, sj).Range.Start, oTable.Cell(ei, ej).Range.End).Cells.Merge End Sub Sub SetHeader(oTable, row, col, header) With oTable.Cell(row, col).Range .Text = header .Font.Bold = True End With End Sub

<reponame>LaudateCorpus1/RosettaCodeData Public s As String '-- (eg "101101100010") Public t As Integer '-- scratch Function s1() s1 = Len(s) = 12 End Function Function s2() t = 0 For i = 7 To 12 t = t - (Mid(s, i, 1) = "1") Next i s2 = t = 3 End Function Function s3() t = 0 For i = 2 To 12 Step 2 t = t - (Mid(s, i, 1) = "1") Next i s3 = t = 2 End Function Function s4() s4 = Mid(s, 5, 1) = "0" Or ((Mid(s, 6, 1) = "1" And Mid(s, 7, 1) = "1")) End Function Function s5() s5 = Mid(s, 2, 1) = "0" And Mid(s, 3, 1) = "0" And Mid(s, 4, 1) = "0" End Function Function s6() t = 0 For i = 1 To 12 Step 2 t = t - (Mid(s, i, 1) = "1") Next i s6 = t = 4 End Function Function s7() s7 = Mid(s, 2, 1) <> Mid(s, 3, 1) End Function Function s8() s8 = Mid(s, 7, 1) = "0" Or (Mid(s, 5, 1) = "1" And Mid(s, 6, 1) = "1") End Function Function s9() t = 0 For i = 1 To 6 t = t - (Mid(s, i, 1) = "1") Next i s9 = t = 3 End Function Function s10() s10 = Mid(s, 11, 1) = "1" And Mid(s, 12, 1) = "1" End Function Function s11() t = 0 For i = 7 To 9 t = t - (Mid(s, i, 1) = "1") Next i s11 = t = 1 End Function Function s12() t = 0 For i = 1 To 11 t = t - (Mid(s, i, 1) = "1") Next i s12 = t = 4 End Function Public Sub twelve_statements() For i = 0 To 2 ^ 12 - 1 s = Right(CStr(WorksheetFunction.Dec2Bin(64 + i \ 128)), 5) _ & Right(CStr(WorksheetFunction.Dec2Bin(256 + i Mod 128)), 7) For b = 1 To 12 Select Case b Case 1: If s1 <> (Mid(s, b, 1) = "1") Then Exit For Case 2: If s2 <> (Mid(s, b, 1) = "1") Then Exit For Case 3: If s3 <> (Mid(s, b, 1) = "1") Then Exit For Case 4: If s4 <> (Mid(s, b, 1) = "1") Then Exit For Case 5: If s5 <> (Mid(s, b, 1) = "1") Then Exit For Case 6: If s6 <> (Mid(s, b, 1) = "1") Then Exit For Case 7: If s7 <> (Mid(s, b, 1) = "1") Then Exit For Case 8: If s8 <> (Mid(s, b, 1) = "1") Then Exit For Case 9: If s9 <> (Mid(s, b, 1) = "1") Then Exit For Case 10: If s10 <> (Mid(s, b, 1) = "1") Then Exit For Case 11: If s11 <> (Mid(s, b, 1) = "1") Then Exit For Case 12: If s12 <> (Mid(s, b, 1) = "1") Then Exit For End Select If b = 12 Then Debug.Print s Next Next End Sub