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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity arctan_comparison_tb is
end arctan_comparison_tb;
architecture behavior of arctan_comparison_tb is
component fast_arctan is
port (
clk : in std_logic;
ce : in std_logic;
input_x : in std_logic_vector(16-1 downto 0);
input_y : in std_logic_vector(16-1 downto 0);
angle : out std_logic_vector(20-1 downto 0)
);
end component;
-- Inputs
signal clk : std_logic := '0';
signal ce : std_logic := '1';
signal input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal input_y : std_logic_vector(16-1 downto 0) := (others => '0');
-- Outputs
signal angle_fast : std_logic_vector(20-1 downto 0);
signal angle_fast_narrow : std_logic_vector (10 downto 0);
signal ramp : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg0_input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg1_input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg2_input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg3_input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg4_input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg5_input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg6_input_x : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg0_input_y : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg1_input_y : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg2_input_y : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg3_input_y : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg4_input_y : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg5_input_y : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg6_input_y : std_logic_vector(16-1 downto 0) := (others => '0');
signal input_x_real : real := 0.0;
signal input_y_real : real := 0.0;
signal angle_real : real := 0.0;
signal angle_wide : std_logic_vector(32-1 downto 0) := (others => '0');
signal angle_ref : std_logic_vector(20-1 downto 0) := (others => '0');
signal angle_error : std_logic_vector(20-1 downto 0) := (others => '0');
signal angle : std_logic_vector(20-1 downto 0) := (others => '0');
-- Clock period definition
constant clk_period : time := 8 ns;
begin
-- Unit under test
--fast_arctan_inst : fast_arctan
--port map (
-- clk => clk,
-- ce => ce,
-- input_x => input_x,
-- input_y => input_y,
-- angle => angle
--);
process (clk) is
begin
if rising_edge(clk) then
ramp <= std_logic_vector(signed(ramp) + 1);
end if;
end process;
process (clk) is
begin
if rising_edge(clk) then
reg0_input_x <= input_x;
reg1_input_x <= reg0_input_x;
reg2_input_x <= reg1_input_x;
reg3_input_x <= reg2_input_x;
reg4_input_x <= reg3_input_x;
reg5_input_x <= reg4_input_x;
reg6_input_x <= reg5_input_x;
reg0_input_y <= input_y;
reg1_input_y <= reg0_input_y;
reg2_input_y <= reg1_input_y;
reg3_input_y <= reg2_input_y;
reg4_input_y <= reg3_input_y;
reg5_input_y <= reg4_input_y;
reg6_input_y <= reg5_input_y;
end if;
end process;
input_x_real <= real(to_integer(signed(reg4_input_x)));
input_y_real <= real(to_integer(signed(reg4_input_y)));
angle_real <= ARCTAN(input_y_real, input_x_real);
angle_wide <= std_logic_vector(to_signed(integer(angle_real*1048576.0/6.283185307179586), 32));
angle_ref <= angle_wide(20-1 downto 0);
angle_error <= std_logic_vector(signed(angle) - signed(angle_ref));
-- Clock process definition for "clk"
process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
input_y <= ramp;
input_x <= std_logic_vector(to_signed(3456, 16));
-- Stimulus process
process
begin
wait for clk_period*10;
wait until rising_edge(clk);
--wait for clk_period*30;
--wait until rising_edge(clk);
--ce <= '0';
--wait for clk_period*30;
--wait until rising_edge(clk);
--ce <= '1';
wait;
end process;
end architecture;
|
<gh_stars>0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---Declare the very beginning and very end (terminals)
entity lab1p1top4 is
port (
input4 : IN std_logic_vector(3 downto 0);
select_next : IN std_logic;
output7 : OUT std_logic_vector(6 downto 0);
valid_fib : OUT std_logic
);
end lab1p1top4;
architecture mixed of lab1p1top4 is
component mux_2_to_1
port (
x : IN std_logic_vector(3 downto 0);---input
y : IN std_logic_vector(3 downto 0);---next
s : IN std_logic; ---triger
m : OUT std_logic_vector(3 downto 0)---the output may be input or next
);
end component;
component simple_fib
port (
x : IN std_logic_vector(3 downto 0);--- the output from the x of the mux_2_to_1
f : OUT std_logic---the output for the valid input from x
);
end component;
component four_to_five
port (
x : IN std_logic_vector(3 downto 0);--- the input from the x of mux_2_to_1
f : OUT std_logic_vector(4 downto 0) --- the output of the next fib
);
end component;
component seven_seg_decoder
port (
x : IN std_logic_vector(3 downto 0);--- the final output from the four_to_five
f : OUT std_logic_vector(6 downto 0)--- the output needs to map to the HEX0
);
end component;
-- Set the signals for the bits transactions
signal output_next4 : std_logic_vector(4 downto 0);
signal mux_out : std_logic_vector(3 downto 0);-- should map or you will lost the signal
begin
p2_simple_fib: simple_fib
port map (input4,valid_fib);
p3_4_to_5 : four_to_five
port map (input4,output_next4);
p1_mux_2_to_1 : mux_2_to_1
port map (input4,output_next4(3 downto 0),select_next,mux_out);
p4_seven_seg_decoder : seven_seg_decoder
port map (mux_out, output7);
end mixed;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_pulse_gen is
end tb_pulse_gen;
architecture test of tb_pulse_gen is
component pulse_gen IS
GENERIC (N : integer := 16);
PORT (
clk : IN std_logic;
rst_n : IN std_logic;
trigger : IN std_logic;
pulse : OUT std_logic
);
END component;
constant N : integer := 4;
signal clk_t : std_logic;
signal rst_n_t : std_logic;
signal trigger_t : std_logic;
signal pulse_t : std_logic;
begin -- test
DUT: pulse_gen
generic map (N)
port map (clk_t, rst_n_t, trigger_t, pulse_t);
clk_p : process
begin
wait for 0.5 ns;
clk_t <= '1';
wait for 0.5 ns;
clk_t <= '0';
end process;
input_gen: process
begin
rst_n_t <= '0';
trigger_t <= '0';
wait for 2 ns;
rst_n_t <= '1';
trigger_t <= '0';
wait for 2 ns;
rst_n_t <= '1';
trigger_t <= '1';
wait for 2 ns;
rst_n_t <= '1';
trigger_t <= '0';
wait for 2 ns;
rst_n_t <= '1';
trigger_t <= '1';
wait for 4 ns;
rst_n_t <= '1';
trigger_t <= '0';
wait for 2 ns;
rst_n_t <= '1';
trigger_t <= '1';
wait for 8 ns;
rst_n_t <= '1';
trigger_t <= '0';
wait for 2 ns;
rst_n_t <= '1';
trigger_t <= '1';
wait for 20 ns;
rst_n_t <= '1';
trigger_t <= '0';
wait for 2 ns;
rst_n_t <= '1';
trigger_t <= '1';
wait for 20 ns;
rst_n_t <= '1';
trigger_t <= '0';
wait;
end process;
end test;
|
library ieee;
use ieee.std_logic_1164.all;
use work.util.all;
entity key_schedule is
generic(k: natural := 64);
port(data_in: in std_logic_vector(k-1 downto 0);
rc: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(k-1 downto 0)
);
end key_schedule;
architecture structural of key_schedule is
signal rotated, swapped: std_logic_vector(k-1 downto 0);
component sbox
port(data_in: in std_logic_vector(3 downto 0);
data_out: out std_logic_vector(3 downto 0)
);
end component;
begin
rotated <= data_in(k-9 downto k/2) & data_in(k-1 downto k-8) &
data_in((k/2)-9 downto 0) & data_in((k/2)-1 downto (k/2)-8);
swapped <= rotated((k/2)-1 downto 0) &
(rotated(k-1 downto k/2) xor rotated((k/2)-1 downto 0));
data_out(k-1 downto k-19) <= swapped(k-1 downto k-19);
data_out(k-20 downto k-24) <= swapped(k-20 downto k-24) xor rc;
data_out(k-25 downto (k/2)-8) <= swapped(k-25 downto (k/2)-8);
GEN_SBOXES: for i in 0 to 3 generate
SX: sbox port map(
data_in => swapped((k/2)-9-(4*i) downto (k/2)-9-(4*i)-3),
data_out => data_out((k/2)-9-(4*i) downto (k/2)-9-(4*i)-3)
);
end generate;
data_out((k/2)-25 downto 0) <= swapped((k/2)-25 downto 0);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:58:31 10/16/2018
-- Design Name:
-- Module Name: COMPLEMENTADOR_4BITS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity COMPLEMENTADOR_4BITS is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
K : in STD_LOGIC;
Z : out STD_LOGIC_VECTOR (3 downto 0));
end COMPLEMENTADOR_4BITS;
architecture Behavioral of COMPLEMENTADOR_4BITS is
begin
process (I, K)
begin
if (K = '1') then
Z <= not I;
else
Z <= I;
end if;
end process;
end Behavioral;
|
--
-- File : nf_register.vhd
-- Autor : <NAME>.
-- Data : 2019.04.24
-- Language : VHDL
-- Description : This is file with registers modules
-- Copyright(c) : 2019 <NAME>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- simple register with reset and clock
entity nf_register is
generic
(
width : integer := 1
);
port
(
clk : in std_logic; -- clk
resetn : in std_logic; -- resetn
datai : in std_logic_vector(width-1 downto 0); -- input data
datao : out std_logic_vector(width-1 downto 0) -- output data
);
end nf_register;
architecture rtl of nf_register is
begin
reg_proc : process( clk, resetn )
begin
if( rising_edge(clk) ) then
if( not resetn ) then
datao <= (others => '0');
else
datao <= datai;
end if;
end if;
end process;
end rtl; -- nf_register
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- register with write enable input
entity nf_register_we is
generic
(
width : integer := 1
);
port
(
clk : in std_logic; -- clk
resetn : in std_logic; -- resetn
we : in std_logic; -- write enable
datai : in std_logic_vector(width-1 downto 0); -- input data
datao : out std_logic_vector(width-1 downto 0) -- output data
);
end nf_register_we;
architecture rtl of nf_register_we is
begin
reg_proc : process( clk )
begin
if( rising_edge(clk) ) then
if( not resetn ) then
datao <= (others => '0');
elsif( we ) then
datao <= datai;
end if;
end if;
end process;
end rtl; -- nf_register_we
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- register with write enable input and not zero reset value
entity nf_register_we_r is
generic
(
width : integer := 1;
rst_val : integer := 0
);
port
(
clk : in std_logic; -- clk
resetn : in std_logic; -- resetn
we : in std_logic; -- write enable
datai : in std_logic_vector(width-1 downto 0); -- input data
datao : out std_logic_vector(width-1 downto 0) -- output data
);
end nf_register_we_r;
architecture rtl of nf_register_we_r is
begin
reg_proc : process( clk )
begin
if( rising_edge(clk) ) then
if( not resetn ) then
datao <= std_logic_vector(to_unsigned(rst_val,width));
elsif( we ) then
datao <= datai;
end if;
end if;
end process;
end rtl; -- nf_register_we_r
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- register with clr input
entity nf_register_clr is
generic
(
width : integer := 1
);
port
(
clk : in std_logic; -- clk
resetn : in std_logic; -- resetn
clr : in std_logic; -- clear register
datai : in std_logic_vector(width-1 downto 0); -- input data
datao : out std_logic_vector(width-1 downto 0) -- output data
);
end nf_register_clr;
architecture rtl of nf_register_clr is
begin
reg_proc : process( clk )
begin
if( rising_edge(clk) ) then
if( not resetn ) then
datao <= (others => '0');
elsif( clr ) then
datao <= (others => '0');
else
datao <= datai;
end if;
end if;
end process;
end rtl; -- nf_register_clr
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- register with clr and we input's
entity nf_register_we_clr is
generic
(
width : integer := 1
);
port
(
clk : in std_logic; -- clk
resetn : in std_logic; -- resetn
we : in std_logic; -- write enable
clr : in std_logic; -- clear register
datai : in std_logic_vector(width-1 downto 0); -- input data
datao : out std_logic_vector(width-1 downto 0) -- output data
);
end nf_register_we_clr;
architecture rtl of nf_register_we_clr is
begin
reg_proc : process( clk )
begin
if( rising_edge(clk) ) then
if( not resetn ) then
datao <= (others => '0');
elsif( we ) then
if( clr ) then
datao <= (others => '0');
else
datao <= datai;
end if;
end if;
end if;
end process;
end rtl; -- nf_register_we_clr
|
--
-- Copyright (c) 2018 Allmine Inc
-- OrphanedGland (<EMAIL>)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity simd512_ntt256 is
port (
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
start : in std_logic;
ccode_start : in std_logic;
ccode_last : in std_logic;
wb_start : in std_logic;
wb_r : in std_logic_vector(1 downto 0);
wb_rnd_i : in std_logic_vector(2 downto 0);
d_in : in std_logic_vector(1023 downto 0);
d_out : out std_logic_vector(8191 downto 0);
w : out std_logic_vector(255 downto 0);
done : out std_logic;
ccode_done : out std_logic;
wb_done : out std_logic
);
end entity simd512_ntt256;
architecture simd512_ntt256_rtl of simd512_ntt256 is
alias slv is std_logic_vector;
component simd512_ntt64 is
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
d_in : in std_logic_vector(1023 downto 0);
d_in_off : in std_logic_vector(1 downto 0);
nl_d_in_off : in std_logic_vector(3 downto 0);
nl_d_out : in std_logic_vector(8191 downto 0);
nl_done : in std_logic;
nl_start : out std_logic;
nl_rb : out std_logic_vector(3 downto 0);
nl_hk : out std_logic_vector(3 downto 0);
nl_as : out std_logic_vector(3 downto 0);
nl_d_in : out std_logic_vector(8191 downto 0);
nl_d_in_we : out std_logic;
ntt64_done : out std_logic
);
end component simd512_ntt64;
component simd512_ntt_loop is
port (
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
start : in std_logic;
ccode_start : in std_logic;
ccode_last : in std_logic;
wb_start : in std_logic;
rb : in std_logic_vector(3 downto 0);
hk : in std_logic_vector(3 downto 0);
as : in std_logic_vector(3 downto 0);
d_in : in std_logic_vector(8191 downto 0);
d_in_we : in std_logic;
wb_r : in std_logic_vector(1 downto 0);
wb_rnd_i : in std_logic_vector(2 downto 0);
d_out : out std_logic_vector(8191 downto 0);
w : out std_logic_vector(255 downto 0);
done : out std_logic;
ccode_done : out std_logic;
wb_done : out std_logic
);
end component simd512_ntt_loop;
type ntt256_state is (IDLE, NTT64_1, NTT64_2, NTT_LOOP_INIT_1, NTT_LOOP_1, NTT64_3, NTT64_4, NTT_LOOP_INIT_2,
NTT_LOOP_2, NTT_LOOP_INIT_3, NTT_LOOP_3);
subtype word64 is slv(63 downto 0);
subtype word32 is slv(31 downto 0);
subtype word8 is slv(7 downto 0);
subtype word6 is slv(5 downto 0);
subtype natural_0_3 is natural range 0 to 3;
constant zeros64 : word64 := (others => '0');
constant zeros32 : word32 := (others => '0');
constant zeros6 : word6 := (others => '0');
function byte_sel(x: word32; n: natural_0_3) return unsigned is
begin
return unsigned(x((n+1)*8-1 downto n*8));
end byte_sel;
function endian_swap64(x: word64) return word64 is
begin
return word64(x(7 downto 0) & x(15 downto 8) & x(23 downto 16) & x(31 downto 24) &
x(39 downto 32) & x(47 downto 40) & x(55 downto 48) & x(63 downto 56));
end endian_swap64;
function endian_swap32(x: word32) return word32 is
begin
return word32(x(7 downto 0) & x(15 downto 8) & x(23 downto 16) & x(31 downto 24));
end endian_swap32;
function shr64(x: word64; n: natural) return word64 is
begin
return word64(zeros64(n-1 downto 0) & x(x'high downto n));
end shr64;
function shr32(x: word32; n: natural) return word32 is
begin
return word32(zeros32(n-1 downto 0) & x(x'high downto n));
end shr32;
function shl64(x: word64; n: natural) return word64 is
begin
return word64(x(x'high-n downto 0) & zeros64(x'high downto x'length-n));
end shl64;
function shl32(x: word32; n: natural) return word32 is
begin
return word32(x(x'high-n downto 0) & zeros32(x'high downto x'length-n));
end shl32;
function shl6(x: word6; n: natural) return word6 is
begin
return word6(x(x'high-n downto 0) & zeros6(x'high downto x'length-n));
end shl6;
function rotr64(x: word64; n: natural) return word64 is
begin
return word64(x(n-1 downto 0) & x(x'high downto n));
end rotr64;
function rotr32(x: word32; n: natural) return word32 is
begin
return word32(x(n-1 downto 0) & x(x'high downto n));
end rotr32;
function rotl64(x: word64; n: natural) return word64 is
begin
return word64(x(x'high-n downto 0) & x(x'high downto x'length-n));
end rotl64;
function rotl32(x: word32; n: natural) return word32 is
begin
return word32(x(x'high-n downto 0) & x(x'high downto x'length-n));
end rotl32;
signal ntt256_state_next : ntt256_state;
signal done_int : std_logic;
signal ntt64_start : std_logic;
signal d_in_off : slv(1 downto 0);
signal nl_d_in_off : slv(3 downto 0);
signal nl_d_out : slv(8191 downto 0);
signal nl_done : std_logic;
signal nl_start : std_logic;
signal ntt64_nl_start : std_logic;
signal nl_rb : slv(3 downto 0);
signal nl_rb_off : slv(3 downto 0);
signal nl_rb_int : slv(3 downto 0);
signal nl_hk : slv(3 downto 0);
signal ntt64_nl_hk : slv(3 downto 0);
signal nl_as : slv(3 downto 0);
signal ntt64_nl_as : slv(3 downto 0);
signal nl_d_in : slv(8191 downto 0);
signal nl_d_in_we : std_logic;
signal cc_d_in : slv(511 downto 0);
signal cc_d_in_we : std_logic;
signal ntt64_done : std_logic;
signal q_ntt256_state : ntt256_state;
begin
d_out <= nl_d_out;
done <= done_int;
simd512_ntt64_inst : simd512_ntt64
port map (
clk => clk,
reset => reset,
start => ntt64_start,
d_in => d_in,
d_in_off => d_in_off,
nl_d_in_off => nl_d_in_off,
nl_d_out => nl_d_out,
nl_done => nl_done,
nl_start => ntt64_nl_start,
nl_rb => nl_rb,
nl_hk => ntt64_nl_hk,
nl_as => ntt64_nl_as,
nl_d_in => nl_d_in,
nl_d_in_we => nl_d_in_we,
ntt64_done => ntt64_done
);
nl_rb_int <= slv(unsigned(nl_rb) + unsigned(nl_rb_off));
simd512_ntt_loop_inst : simd512_ntt_loop
port map (
clk => clk,
reset => reset,
clr => clr,
start => nl_start,
ccode_start => ccode_start,
ccode_last => ccode_last,
wb_start => wb_start,
rb => nl_rb_int,
hk => nl_hk,
as => nl_as,
d_in => nl_d_in,
d_in_we => nl_d_in_we,
wb_r => wb_r,
wb_rnd_i => wb_rnd_i,
d_out => nl_d_out,
w => w,
done => nl_done,
ccode_done => ccode_done,
wb_done => wb_done
);
ntt256_proc : process(q_ntt256_state, ntt64_nl_start, ntt64_nl_hk, ntt64_nl_as, start, ntt64_done, nl_done)
begin
ntt256_state_next <= q_ntt256_state;
ntt64_start <= '0';
d_in_off <= "00";
nl_d_in_off <= X"0";
nl_rb_off <= X"0";
nl_start <= ntt64_nl_start;
nl_hk <= ntt64_nl_hk;
nl_as <= ntt64_nl_as;
done_int <= '0';
case q_ntt256_state is
when IDLE =>
ntt64_start <= start;
if start = '1' then
ntt256_state_next <= NTT64_1;
end if;
when NTT64_1 =>
ntt64_start <= ntt64_done;
if ntt64_done = '1' then
d_in_off <= "10";
nl_d_in_off <= X"2";
nl_rb_off <= X"4";
ntt256_state_next <= NTT64_2;
end if;
when NTT64_2 =>
d_in_off <= "10";
nl_d_in_off <= X"2";
nl_rb_off <= X"4";
if ntt64_done = '1' then
ntt256_state_next <= NTT_LOOP_INIT_1;
end if;
when NTT_LOOP_INIT_1 =>
nl_start <= '1';
nl_hk <= X"4";
nl_as <= X"2";
ntt256_state_next <= NTT_LOOP_1;
when NTT_LOOP_1 =>
nl_hk <= X"4";
nl_as <= X"2";
ntt64_start <= nl_done;
if nl_done = '1' then
d_in_off <= "01";
nl_d_in_off <= X"4";
nl_rb_off <= X"8";
ntt256_state_next <= NTT64_3;
end if;
when NTT64_3 =>
d_in_off <= "01";
nl_d_in_off <= X"4";
nl_rb_off <= X"8";
ntt64_start <= ntt64_done;
if ntt64_done = '1' then
d_in_off <= "11";
nl_d_in_off <= X"6";
nl_rb_off <= X"C";
ntt256_state_next <= NTT64_4;
end if;
when NTT64_4 =>
d_in_off <= "11";
nl_d_in_off <= X"6";
nl_rb_off <= X"C";
if ntt64_done = '1' then
ntt256_state_next <= NTT_LOOP_INIT_2;
end if;
when NTT_LOOP_INIT_2 =>
nl_start <= '1';
nl_rb_off <= X"8";
nl_hk <= X"4";
nl_as <= X"2";
ntt256_state_next <= NTT_LOOP_2;
when NTT_LOOP_2 =>
nl_rb_off <= X"8";
nl_hk <= X"4";
nl_as <= X"2";
if nl_done = '1' then
ntt256_state_next <= NTT_LOOP_INIT_3;
end if;
when NTT_LOOP_INIT_3 =>
nl_start <= '1';
nl_hk <= X"8";
nl_as <= X"1";
ntt256_state_next <= NTT_LOOP_3;
when NTT_LOOP_3 =>
nl_hk <= X"8";
nl_as <= X"1";
done_int <= nl_done;
if nl_done = '1' then
ntt256_state_next <= IDLE;
end if;
when others =>
null;
end case;
end process ntt256_proc;
registers : process(reset, clk) is
begin
if reset = '1' then
q_ntt256_state <= IDLE;
elsif rising_edge(clk) then
q_ntt256_state <= ntt256_state_next;
end if;
end process registers;
end architecture simd512_ntt256_rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrctrl
-- File: ddrctrl.vhd
-- Author: <NAME> - Gaisler Research
-- Description: DDR-RAM memory controller with AMBA interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
use gaisler.ddrrec.all;
entity ddrctrl is
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 2; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 16; -- Allowed: 4, 8, 16
chipsize : integer := 256; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := virtex2;
clkperiod : integer := 10); -- (ns)
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end ddrctrl;
architecture rtl of ddrctrl is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant DELAY_15600NS : integer := (15600 / clkperiod);
constant DELAY_7800NS : integer := (7800 / clkperiod);
constant DELAY_7_15600NS : integer := (7*(15600 / clkperiod));
constant DELAY_7_7800NS : integer := (7*(7800 / clkperiod));
constant DELAY_200US : integer := (200000 / clkperiod);
constant REVISION : integer := 0;
constant pmask : integer := 16#fff#;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant dqsize : integer := numchips*chipbits;
constant dmsize : integer := (dqsize/8);
constant strobesize : integer := (dqsize/8) * dmvector(chipbits);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal toAHB : two_ahb_ctrl_in_type;
signal fromAHB : two_ahb_ctrl_out_type;
signal fromAHB2Main : two_ahb_ctrl_out_type;
signal apbr : apb_reg_type;
signal apbri : apb_reg_type;
signal fromAPB : apb_ctrl_out_type;
signal fromAPB2Main : apb_ctrl_out_type;
signal mainr : main_reg_type;
signal mainri : main_reg_type;
signal fromMain : main_ctrl_out_type;
signal fromMain2APB : apb_ctrl_in_type;
signal fromMain2AHB : two_ahb_ctrl_in_type;
signal fromMain2HS : hs_in_type;
signal toHS : hs_in_type;
signal fromHS : hs_out_type;
begin -- achitecture rtl
-------------------------------------------------------------------------------
-- Error reports
assert (tech = virtex2 or tech = virtex4 or tech = lattice) report "Unsupported technology by DDR controller (generic tech)" severity failure;
assert (modbanks=1 or modbanks=2) report "Only 1 or 2 module banks is supported (generic modbanks)" severity failure;
assert (chipbits=4 or chipbits=8 or chipbits=16) report "DDR chips either have 4, 8 or 16 bits output (generic chipbits)" severity failure;
assert (chipsize=64 or chipsize=128 or chipsize=256 or chipsize=512 or chipsize=1024) report "DDR chips either have 64, 128, 256, 512 or 1024 Mbit size" severity failure;
assert (buffersize>=2) report "Buffer must have room for at least 2 bursts (generic buffersize)" severity failure;
assert (plldelay=0 or plldelay=1) report "Invalid setting for DDRRAM PLL delay (generic plldelay)" severity failure;
assert (numahb=1 or numahb=2) report "Only one or two AHB interfaces can be used (generic numahb)" severity failure;
-------------------------------------------------------------------------------
-- APB control
-- Controls APB bus. Contains the DDRCFG register. Clear memcmd
-- bits when a memory command requested on APB is complete.
apbcomb : process(apbr, apbsi, fromMain2APB, rst)
variable v : apb_reg_type;
begin
v:= apbr;
if rst = '0' then -- Reset
v.ddrcfg_reg := ddrcfg_reset;
elsif fromMain2APB.apb_cmd_done = '1' then -- Clear memcmd bits
v.ddrcfg_reg(28 downto 27) := "00";
elsif (apbsi.psel(pindex) and apbsi.penable and apbsi.pwrite) = '1' then -- Write
v.ddrcfg_reg := apbsi.pwdata(31 downto 1) & fromMain2APB.ready;
else
v.ddrcfg_reg(0) := fromMain2APB.ready;
end if;
apbri <= v;
fromAPB.ddrcfg_reg <= v.ddrcfg_reg;
end process apbcomb;
apbclk : process(pclk)
begin
if rising_edge(pclk) then apbr <= apbri; end if;
end process;
apbso.prdata <= fromAPB.ddrcfg_reg; apbso.pirq <= (others => '0');
apbso.pindex <= pindex; apbso.pconfig <= pconfig;
-------------------------------------------------------------------------------
-- Main controller
-------------------------------------------------------------------------------
maincomb : process(mainr, fromAHB, fromAHB2Main, fromAPB2Main, rst, fromHS)
variable v : main_reg_type;
begin
v := mainr; v.loadcmdbuffer := '0'; -- Clear Cmd loading bit
-------------------------------------------------------------------------------
-- DDRCFG control
-- Reads DDRCFG from APB controller. Handles refresh command from refresh
-- timer and memoory comand requested on APB.
case v.apbstate is
when idle =>
v.apb_cmd_done := '0';
-- Refresh timer signals refresh
if v.doRefresh = '1' and v.ddrcfg.refresh = '1' then
v.apbstate := refresh;
-- LMR cmd on APB bus
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) = "11" then
v.lockAHB := "11";
v.apbstate := wait_lmr1;
-- Refresh or Precharge cmd on APB BUS
elsif fromAPB2Main.ddrcfg_reg(28 downto 27) > "00" then
v.apbstate := cmd;
-- Nothing to be done
else
v.ddrcfg.memcmd := "00";
end if;
-- Refresh from Timer
when refresh =>
if v.mainstate = idle then v.ddrcfg.memcmd := "10"; end if;
if v.dorefresh = '0' then v.ddrcfg.memcmd := "00"; v.apbstate := idle; end if;
-- Refresh or Precharge from APB BUS
when cmd =>
if v.mainstate = idle then v.ddrcfg.memcmd := fromAPB2Main.ddrcfg_reg(28 downto 27); end if;
v.apbstate := cmdDone;
-- Wait until no more cmd can arrive from AHB ctrl
when wait_lmr1 => v.apbstate := wait_lmr2;
when wait_lmr2 => v.apbstate := cmdlmr;
when cmdlmr =>
-- Check that no new R/W cmd is to be performed
if fromAHB2Main(0).rw_cmd_valid = v.rw_cmd_done(0) and
fromAHB2Main(1).rw_cmd_valid = v.rw_cmd_done(1) and v.mainstate = idle then
v.ddrcfg.memcmd := "11";
v.ddrcfg.cas := fromAPB2Main.ddrcfg_reg(30 downto 29);
v.ddrcfg.bl := fromAPB2Main.ddrcfg_reg(26 downto 25);
v.apbstate := cmdDone;
end if;
when cmdDone =>
v.lockAHB := "00";
if v.memCmdDone = '1' then
v.ddrcfg.memcmd := "00"; v.apb_cmd_done := '1'; v.apbstate := cmdDone2;
end if;
when cmdDone2 =>
if fromAPB2Main.ddrcfg_reg(28 downto 27) = "00" then
v.apb_cmd_done := '0'; v.apbstate := idle;
end if;
end case;
if v.mainstate = idle then
v.ddrcfg.refresh := fromAPB2Main.ddrcfg_reg(31);
v.ddrcfg.autopre := fromAPB2Main.ddrcfg_reg(24);
v.ddrcfg.r_predict := fromAPB2Main.ddrcfg_reg(23 downto 22);
v.ddrcfg.w_prot := fromAPB2Main.ddrcfg_reg(21 downto 20);
v.ddrcfg.ready := fromAPB2Main.ddrcfg_reg(0);
end if;
-------------------------------------------------------------------------------
-- Calcualtes burst length
case v.ddrcfg.bl is
when "00" => v.burstlength := 2;
when "01" => v.burstlength := 4;
when "10" => v.burstlength := 8;
when others => v.burstlength := 8;
end case;
-------------------------------------------------------------------------------
-- Calculates row and column address
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.coladdress := (others => (others => '0'));
v.tmpcolbits := 0; v.colbits := 0; v.rowbits := 0;
-- Based on the size of the chip its organization can be calculated
case chipsize is
when 64 => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 64Mbit
when 128 => v.tmpcolbits := 11; v.rowbits := 12; v.refreshTime := DELAY_15600NS; v.maxRefreshTime := DELAY_7_15600NS; -- 128Mbit
when 256 => v.tmpcolbits := 11; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 256Mbit
when 512 => v.tmpcolbits := 12; v.rowbits := 13; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 512Mbit
when 1024 => v.tmpcolbits := 12; v.rowbits := 14; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- 1Gbit
when others => v.tmpcolbits := 10; v.rowbits := 12; v.refreshTime := DELAY_7800NS; v.maxRefreshTime := DELAY_7_7800NS; -- Others 64Mbit
end case;
case chipbits is
when 4 => v.colbits := v.tmpcolbits; -- x4 bits
when 8 => v.colbits := (v.tmpcolbits-1); -- x8 bits
when 16 => v.colbits := (v.tmpcolbits-2); -- x16 bits
when others => null;
end case;
v.addressrange := v.colbits + v.rowbits;
-- AHB controller 1 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(0)(i) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(0)(i-v.colbits) := fromAHB(0).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(0)(i - v.addressrange) := fromAHB(0).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(0)(adrbits-1 downto 0) := v.intbankbits(0) &
v.tmpcoladdress(0)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(0)(9 downto 0); --Bit 9 to 0
v.rowaddress(0)(adrbits-1 downto (adrbits-2)) := v.intbankbits(0);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(0).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(0) := BANK0;
else
v.bankselect(0) := BANK1;
end if;
else
v.bankselect(0) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(0):= conv_integer(v.bankselect(0)(0) & v.rowaddress(0)(adrbits-1 downto (adrbits-2)));
-- AHB Controller 2 --
for i in 0 to ahbadr loop
if (i < v.colbits) then
v.tmpcoladdress(1)(i) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange) and i >= v.colbits) then
v.rowaddress(1)(i-v.colbits) := fromAHB(1).asramso.dataout(i); end if;
if (i < (v.addressrange+2) and i >= v.addressrange) then
v.intbankbits(1)(i - v.addressrange) := fromAHB(1).asramso.dataout(i); end if;
end loop;
-- Inserts bank address and auto precharge bit as A10
v.coladdress(1)(adrbits-1 downto 0) := v.intbankbits(1) &
v.tmpcoladdress(1)(12 downto 10) & -- Bit 13 to 11
v.ddrcfg.autopre & -- Bit 10
v.tmpcoladdress(1)(9 downto 0); --Bit 9 to 0
v.rowaddress(1)(adrbits-1 downto (adrbits-2)) := v.intbankbits(1);
-- Calculate total numer of useable address bits
if modbanks = 2 then
-- Calculate memory module bank (CS signals)
if fromAHB(1).asramso.dataout(v.addressrange +2) = '0' then
v.bankselect(1) := BANK0;
else
v.bankselect(1) := BANK1;
end if;
else
v.bankselect(1) := BANK0;
end if;
-- This is for keeping track of which banks has a active row
v.pre_bankadr(1):= conv_integer(v.bankselect(1)(0) & v.rowaddress(1)(adrbits-1 downto (adrbits-2)));
-- ((1bit(Lower/upper half if 32 bit mode))) + 1bit(module bank select) +
-- 2bits(Chip bank selekt) + Xbits(address, depending on chip size)
-------------------------------------------------------------------------------
-- Calculate LMR command address
v.lmradr(adrbits-1 downto 7) := (others => '0');
-- CAS value
case v.ddrcfg.cas is
when "00" => v.lmradr(6 downto 4) := "010";
when "01" => v.lmradr(6 downto 4) := "110";
when "10" => v.lmradr(6 downto 4) := "011";
when others => v.lmradr(6 downto 4) := "010";
end case;
-- Burst type, seqencial or interleaved (fixed att seqencial)
v.lmradr(3) := '0';
-- Burst length
case v.ddrcfg.bl is
when "00" => v.lmradr(2 downto 0) := "001";
when "01" => v.lmradr(2 downto 0) := "010";
when "10" => v.lmradr(2 downto 0) := "011";
when others => v.lmradr(2 downto 0) := "010";
end case;
-------------------------------------------------------------------------------
-- Auto refresh timer
case v.timerstate is
when t1 =>
v.doRefresh := '0'; v.refreshcnt := v.refreshTime; v.timerstate := t2;
when t2 =>
v.doRefresh := '0'; v.refreshcnt := mainr.refreshcnt -1;
if v.refreshcnt < 50 then v.timerstate := t3; end if;
when t3 =>
if mainr.refreshcnt > 1 then v.refreshcnt := mainr.refreshcnt -1; end if;
v.doRefresh := '1';
if v.refreshDone = '1' then
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
v.timerstate := t4;
end if;
when t4 =>
v.doRefresh := '0'; v.timerstate := t2; when others => null;
end case;
-------------------------------------------------------------------------------
-- Init statemachine
case v.initstate is
when idle =>
v.memInitDone := '0';
if v.doMemInit = '1' then
if plldelay = 1 then
-- Using refrshtimer for initial wait
v.refreshcnt := DELAY_200US +50; v.timerstate := t2; v.initstate := i1;
else v.initstate := i2; end if;
end if;
when i1 =>
if v.doRefresh = '1' then v.initstate := i2; end if;
when i2 =>
v.cs := "00";
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_NOP; v.loadcmdbuffer := '1'; v.initstate := i3;
end if;
when i3 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i4;
end if;
when i4 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1';
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := "01";
v.adrbufferdata((adrbits -3) downto 0) := (others => '0');
v.initstate := i5;
end if;
when i5 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.refreshcnt := 250; v.timerstate := t2; --200 cycle count
v.adrbufferdata(8) := '1'; v.initstate := i6;
end if;
when i6 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_PRE; v.loadcmdbuffer := '1';
v.adrbufferdata(10) := '1'; v.initstate := i7;
end if;
when i7 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i8;
end if;
when i8 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_AR; v.loadcmdbuffer := '1'; v.initstate := i9;
end if;
when i9 =>
if fromHS.hs_busy = '0' then
v.cmdbufferdata := CMD_LMR; v.loadcmdbuffer := '1'; v.adrbufferdata := v.lmradr;
v.initstate := i10;
end if;
when i10 =>
if v.doRefresh = '1' then v.initstate := i11; end if;
when i11 =>
v.memInitDone := '1';
if v.doMemInit = '0' then v.initstate := idle; end if;
when others => null;
end case;
-------------------------------------------------------------------------------
-- Main controller statemachine
case v.mainstate is
-- Initialize memory
when init =>
v.doMemInit := '1';
v.ready := '0';
if v.memInitDone = '1' then
v.mainstate := idle;
end if;
-- Await command
when idle =>
v.doMemInit := '0';
v.RefreshDone := '0';
v.memCmdDone := '0';
v.ready := '1';
v.use_bl := mainr.burstlength;
v.use_cas := mainr.ddrcfg.cas;
if v.ddrcfg.memcmd /= "00" then
v.mainstate := c1;
elsif fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) or
fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) then
-- This code is to add read priority between the ahb controllers
-- if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) and
-- fromAHB(0).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 0;
-- v.use_buf := v.rw_cmd_done(0)+1;
-- elsif fromAHB2Main(1).rw_cmd_valid /= v.rw_cmd_done(1) and
-- fromAHB(1).asramso.dataout(ahbadr) = '0' then
-- v.use_ahb := 1;
-- v.use_buf := v.rw_cmd_done(1)+1;
if fromAHB2Main(0).rw_cmd_valid /= v.rw_cmd_done(0) then
v.use_ahb := 0;
v.use_buf := v.rw_cmd_done(0)+1;
else
v.use_ahb := 1;
v.use_buf := v.rw_cmd_done(1)+1;
end if;
-- Check if the chip bank which is to be R/W has a row open
if mainr.pre_chg(v.pre_bankadr(v.use_ahb)) = '1' then
-- Check if the row which is open is the same that will be R/W
if mainr.pre_row(v.pre_bankadr(v.use_ahb)) = v.rowaddress(v.use_ahb) then
v.mainstate := rw;
-- R/W to a different row then the one open, has to precharge and
-- activate new row
else
v.mainstate := pre1;
end if;
-- No row open, has to activate row
else
v.mainstate := act1;
end if;
end if;
-- Nothing to do, if 10 idle cycles, run Refreash (if needed)
if v.idlecnt = 10 and v.refreshcnt < v.maxRefreshTime then
v.doRefresh := '1';
v.idlecnt := 0;
v.timerstate := t3;
v.refreshcnt := mainr.refreshcnt + v.refreshTime;
elsif v.idlecnt = 10 then
v.idlecnt := 0;
else
v.idlecnt := mainr.idlecnt + 1;
end if;
-- Precharge memory
when pre1 =>
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
-- Select chip bank to precharge
v.adrbufferdata := (others => '0');
v.adrbufferdata(adrbits-1 downto (adrbits-2)) := v.rowaddress(mainr.use_ahb)(adrbits-1 downto (adrbits-2));
v.cmdbufferdata := CMD_PRE;
-- Clear bit in register for active rows
v.pre_chg(v.pre_bankadr(mainr.use_ahb)):= '0';
v.loadcmdbuffer := '1';
v.mainstate := act1;
end if;
-- Activate row in memory
when act1 => -- Get adr and cmd from AHB, set to HS
if fromHS.hs_busy = '0' then
v.cs := v.bankselect(mainr.use_ahb);
v.cmdbufferdata := CMD_ACTIVE;
v.adrbufferdata := v.rowaddress(mainr.use_ahb);
v.loadcmdbuffer := '1';
-- Set bit in register for active row if auto-precharge is disabled
if v.ddrcfg.autopre = '0' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '1';
v.pre_row(v.pre_bankadr(mainr.use_ahb)) := v.rowaddress(mainr.use_ahb);
end if;
v.mainstate := rw;
end if;
-- Issu read or write to HS part
when rw =>
if fromAHB(mainr.use_ahb).asramso.dataout(ahbadr) = '1' then
v.cmdbufferdata := CMD_WRITE;
else
v.cmdbufferdata := CMD_READ;
end if;
if v.ddrcfg.autopre = '1' then
v.pre_chg(v.pre_bankadr(mainr.use_ahb)) := '0';
end if;
v.adrbufferdata := v.coladdress(mainr.use_ahb);
v.cs := v.bankselect(mainr.use_ahb);
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
if fromAHB2Main(mainr.use_ahb).w_data_valid /= v.rw_cmd_done(mainr.use_ahb) then
v.loadcmdbuffer := '1';
v.rw_cmd_done(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.sync2_adr(mainr.use_ahb) := v.rw_cmd_done(mainr.use_ahb)+1;
v.mainstate := idle;
end if;
end if;
-- Issue prechare, auto refresh or LMR to HS part
when c1 =>
v.idlecnt := 0;
if fromHS.hs_busy = '0' then
v.cs := BANK01;
case v.ddrcfg.memCmd is
when "01" => -- Precharge all
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.memCmdDone := '1';
v.mainstate := c2;
when "10" => -- AutoRefresh
-- All banks have to be precharged before AR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_AR;
v.memCmdDone := '1';
v.mainstate := c2;
v.refreshDone := '1';
else -- Run Precharge, and let AR begin when finished
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when "11" => -- LMR
-- All banks have to be precharged before LMR
if v.pre_chg = "00000000" then
v.cmdbufferdata := CMD_LMR;
v.adrbufferdata := v.lmradr;
v.memCmdDone := '1';
v.mainstate := c2;
else
v.cmdbufferdata := CMD_PRE;
v.adrbufferdata(10) := '1';
v.pre_chg := (others => '0');
v.mainstate := idle;
end if;
when others => null;
end case;
v.loadcmdbuffer := '1';
end if;
when c2 =>
if v.ddrcfg.memCmd = "00" then
v.refreshDone := '0';
v.mainstate := idle;
end if;
when others =>
v.mainstate := init;
end case;
-- Reset
if rst = '0' then
-- Main controller
v.mainstate := init;
v.loadcmdbuffer := '0';
v.cmdbufferdata := CMD_NOP;
v.adrbufferdata := (others => '0');
v.use_ahb := 0;
v.use_bl := 4;
v.use_cas := "00";
v.use_buf := (others => '1');
v.burstlength := 8;
v.rw_cmd_done := (others => (others => '1'));
v.lmradr := (others => '0');
v.memCmdDone := '0';
v.lockAHB := "00";
v.pre_row := (others => (others => '0'));
v.pre_chg := (others => '0');
v.pre_bankadr := (0,0);
v.sync2_adr := (others =>(others => '0'));
-- For init statemachine
v.initstate := idle;
v.doMemInit := '0';
v.memInitDone := '0';
v.initDelay := 0;
v.cs := "11";
-- For address calculator
v.coladdress := (others => (others => '0'));
v.tmpcoladdress := (others => (others => '0'));
v.rowaddress := (others => (others => '0'));
v.addressrange := 0;
v.tmpcolbits := 0;
v.colbits := 0;
v.rowbits := 0;
v.bankselect := ("11","11");
v.intbankbits := ("00","00");
-- For refresh timer statemachine
v.timerstate := t2;
v.doRefresh := '0';
v.refreshDone := '0';
v.refreshTime := 0;
v.maxRefreshTime := 0;
v.idlecnt := 0;
v.refreshcnt := DELAY_200us;
-- For DDRCFG register
v.apbstate := idle;
v.apb_cmd_done := '0';
v.ready := '0';
v.ddrcfg := (ddrcfg_reset(31),ddrcfg_reset(30 downto 29),ddrcfg_reset(28 downto 27),
ddrcfg_reset(26 downto 25),ddrcfg_reset(24),ddrcfg_reset(23 downto 22),
ddrcfg_reset(21 downto 20),'0');
end if;
-- Set output signals
mainri <= v;
fromMain.hssi.bl <= v.use_bl;
fromMain.hssi.ml <= fromAHB(mainr.use_ahb).burst_dm(conv_integer(mainr.use_buf));
fromMain.hssi.cas <= v.use_cas;
fromMain.hssi.buf <= v.use_buf;
fromMain.hssi.ahb <= v.use_ahb;
fromMain.hssi.cs <= v.cs;
fromMain.hssi.cmd <= v.cmdbufferdata;
fromMain.hssi.cmd_valid <= v.loadcmdbuffer;
fromMain.hssi.adr <= v.adrbufferdata;
fromMain.ahbctrlsi(0).burstlength <= v.burstlength;
fromMain.ahbctrlsi(1).burstlength <= v.burstlength;
fromMain.ahbctrlsi(0).r_predict <= v.ddrcfg.r_predict(0);
fromMain.ahbctrlsi(1).r_predict <= v.ddrcfg.r_predict(1);
fromMain.ahbctrlsi(0).w_prot <= v.ddrcfg.w_prot(0);
fromMain.ahbctrlsi(1).w_prot <= v.ddrcfg.w_prot(1);
fromMain.ahbctrlsi(0).locked <= v.lockAHB(0);
fromMain.ahbctrlsi(1).locked <= v.lockAHB(1);
fromMain.ahbctrlsi(0).asramsi.raddress <= v.sync2_adr(0);
fromMain.ahbctrlsi(1).asramsi.raddress <= v.sync2_adr(1);
fromMain.apbctrlsi.apb_cmd_done <= v.apb_cmd_done;
fromMain.apbctrlsi.ready <= v.ready;
end process;
--Main clocked register
mainclk : process(clk0)
begin
if rising_edge(clk0) then
mainr <= mainri;
-- Register to sync between different clock domains
fromAPB2Main.ddrcfg_reg <= fromAPB.ddrcfg_reg;
-- Makes signals from main to AHB, ABP, HS registerd
fromMain2AHB <= fromMain.ahbctrlsi;
fromMain2APB <= fromMain.apbctrlsi;
fromMain2HS <= fromMain.hssi;
end if;
end process;
-- Sync of incoming data valid signals from AHB
-- Either if separate clock domains or if syncram_2p
-- doesn't support write through (write first)
a1rt : if ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip1 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end if;
end process;
end generate;
arf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(0).rw_cmd_valid <= fromAHB(0).rw_cmd_valid;
fromAHB2Main(0).w_data_valid <= fromAHB(0).w_data_valid;
end generate;
a2rt : if ahb2sepclk = 1 or syncram_2p_write_through(tech) = 0 generate
regip2 : process(clk0)
begin
if rising_edge(clk0) then
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end if;
end process;
end generate;
a2rf : if not (ahb1sepclk = 1 or syncram_2p_write_through(tech) = 0) generate
fromAHB2Main(1).rw_cmd_valid <= fromAHB(1).rw_cmd_valid;
fromAHB2Main(1).w_data_valid <= fromAHB(1).w_data_valid;
end generate;
-------------------------------------------------------------------------------
-- High speed interface (Physical layer towards memory)
-------------------------------------------------------------------------------
D0 : hs
generic map(
tech => tech,
dqsize => dqsize,
dmsize => dmsize,
strobesize => strobesize,
clkperiod => clkperiod)
port map(
rst => rst,
clk0 => clk0,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
hclk => pclk,
hssi => toHS,
hsso => fromHS);
A0 : ahb_slv
generic map(
hindex => hindex1,
haddr => haddr1,
hmask => hmask1,
sepclk => ahb1sepclk,
dqsize => dqsize,
dmsize => dmsize,
tech => tech)
port map (
rst => rst,
hclk => hclk1,
clk0 => clk0,
csi => toAHB(0),
cso => fromAHB(0));
B1: if numahb = 2 generate
A1 : ahb_slv
generic map(
hindex => hindex2,
haddr => haddr2,
hmask => hmask2,
sepclk => ahb2sepclk,
dqsize => dqsize,
dmsize => dmsize)
port map (
rst => rst,
hclk => hclk2,
clk0 => clk0,
csi => toAHB(1),
cso => fromAHB(1));
end generate;
B2 : if numahb /= 2 generate
fromAHB(1).rw_cmd_valid <= (others => '1');
end generate;
-------------------------------------------------------------------------------
-- Mapping signals
-- Signals to HS
toHS.bl <= fromMain.hssi.bl;
toHS.ml <= fromMain.hssi.ml;
toHS.cas <= fromMain.hssi.cas;
toHS.buf <= fromMain.hssi.buf;
toHS.ahb <= fromMain.hssi.ahb;
toHS.cs <= fromMain.hssi.cs;
toHS.adr <= fromMain.hssi.adr;
toHS.cmd <= fromMain.hssi.cmd;
toHS.cmd_valid <= fromMain.hssi.cmd_valid;
toHS.dsramso(0) <= fromAHB(0).dsramso;
toHS.dsramso(1) <= fromAHB(1).dsramso;
toHS.ddso <= ddso;
-- Signals to AHB ctrl 1
toAHB(0).ahbsi <= ahb1si;
toAHB(0).asramsi <= fromMain.ahbctrlsi(0).asramsi;
toAHB(0).dsramsi <= fromHS.dsramsi(0);
toAHB(0).burstlength <= fromMain2AHB(0).burstlength;
toAHB(0).r_predict <= fromMain2AHB(0).r_predict;
toAHB(0).w_prot <= fromMain2AHB(0).w_prot;
toAHB(0).locked <= fromMain2AHB(0).locked;
toAHB(0).rw_cmd_done <= fromHS.cmdDone(0);
-- Signals to AHB ctrl 2
toAHB(1).ahbsi <= ahb2si;
toAHB(1).asramsi <= fromMain.ahbctrlsi(1).asramsi;
toAHB(1).dsramsi <= fromHS.dsramsi(1);
toAHB(1).burstlength <= fromMain2AHB(1).burstlength;
toAHB(1).r_predict <= fromMain2AHB(1).r_predict;
toAHB(1).w_prot <= fromMain2AHB(1).w_prot;
toAHB(1).locked <= fromMain2AHB(1).locked;
toAHB(1).rw_cmd_done <= fromHS.cmdDone(1);
-- Ouput signals
ahb1so <= fromAHB(0).ahbso;
ahb2so <= fromAHB(1).ahbso;
ddsi <= fromHS.ddsi;
end rtl;
|
--
-- Copyright (c) 2018 Allmine Inc
--
-- Testvectors generated from reference code
-- https://github.com/tpruvot/cpuminer-multi/blob/linux/algo/nist5.c
-- Len = 80 bytes
-- Msg =
-- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-- Blake-512 Output digest:
-- 13cee4af d536f7ed 6aa3f7fc 90e00050 4bf01dd0 41a8a3c1 f38f0bfa 14258308 384b6c5c 75d2ab52 8277de92 a0968b66 50fcb806 87a4eab0 dcd87216 bc522dc6
-- Groestl-512 Output digest:
-- 5ba55893 849a3e48 bd588b37 5803f510 10b842fb e173b7b3 2121d67b e8befdfd 704be904 708fc801 979e4762 100f7c98 137291f6 7d3ad515 766ef9b1 ef02e8ab
-- JH-512 Output digest:
-- 231afb47 84a18785 dc4c124e 1e460ec3 38e13fd3 84a1b178 12a5a0f0 d3c97df5 7cb16b3c 9ff06f87 bdc982c0 b5882a75 927aad0e 73338cd6 28cfe8c6 cfe744b8
-- Keccak-512 Output digest:
-- 946b44b6 347724a4 88a25a15 0a39d0c4 3d183438 7772662b aa9e1ae6 5967b64d 84ef71ee 85ce690c fa2f8e2c a0f21f91 659d4857 1d9cabf9 aa941e65 5351898d
-- Skein-512 Output digest:
-- f793aee4 ec7c83ad 3fb06661 fc514201 ea8865a2 22eb7cc5 50fb0fcb 7644435d 4856ad97 ccf1fbbe d547b5a5 30b2c108 3924c5d1 024b380e eac2058d 68ef44da
--
-- Len = 80 bytes
-- Msg =
-- 000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f202122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f404142434445464748494a4b4c4d4e4f
-- Blake-512 Output digest:
-- dbc2a885 76bdc79a 75daad04 c1426223 7cba3eed 3421381c 5ae269e8 f2ac537d dc87a7be f5267469 daea8a63 e35437a0 f30ce92c ea8e25dc 67b9848b e1276536
-- Groestl-512 Output digest:
-- 8df4f1a6 e8445c6b 9277a1d3 4bb79b6e a99afe34 6ab518c7 ad4a4516 c45fb662 5587671f 1866058c 0735e147 29843e35 8c9805a0 50c62f26 c7968709 c57f81bc
-- JH-512 Output digest:
-- 566b6da2 4ca006fe 56edb031 876135a3 001deb97 f0d45f8e 442cd2f3 c716d35d 4d0f402c c63fa1a9 57af916d 26bee124 e93e126e 7cc813d0 7e5760c7 468bfe16
-- Keccak-512 Output digest:
-- 9856cf74 e797a3ba c21c3066 ada508ae 6b9b06a7 7f87c95a 13d86744 a87f6e54 87e6f03b 53486880 4d649cec 186765d2 239c6ec9 c0db0d73 906865ef 4e5df881
-- Skein-512 Output digest:
-- 613f61e8 346b89ae 0429f1d4 9108b588 f3ad050d e7f0ad13 589bf758 40e6e3d3 89b247ca 6b44b1ca c0880bf3 6213c7f3 6cdf0a29 5fbf71ba 7ce60cbb 97494c23
--
-- Len = 80 bytes
-- Msg =
-- 716f6e863f744b9ac22c97ec7b76ea5f5908bc5b2f67c61510bfc4751384ea7a0ce8d4ef4dd7cd8d62dfded9d4edb0a774ae6a41929a74da23109e8f11139c870c7b159452328517463db487df5e39b7
-- Blake-512 Output digest:
-- 8d80f6fd 793001d8 f84790cc 65d7f3b0 99196b88 b1d4f468 bff7c25d c40bc9c1 c20e4d0f c4ca9954 ba207d15 9bbe44f3 a1d0a106 a0d55ad1 5079f4e9 73c02243
-- Groestl-512 Output digest:
-- f78d2b4f eb58e228 75fe0406 7a4be5a9 52321628 ad0a1e06 fe552517 2ca5ad2a 671afa4f 182f09c2 784f3d01 fc48d31b c3bfe6fe 7669e594 8472e876 88b172e1
-- JH-512 Output digest:
-- fe884342 c74beeaa d9ad2852 3f820e37 e5702bfc 7a6aaf4f 43b9cdc1 2a1baa74 44ecc4f1 403dc749 d162873e b8bd8788 ec084c0e 2d37c8e3 d7a2d0f7 343d12fd
-- Keccak-512 Output digest:
-- 4a817a52 0f53ba10 371e65b9 ad88fbcc de465251 8f46efde c98746c7 785fca46 675cdf1c 02fcbd9a 6fe48a2e f8017e6a fb69c3d9 cbf38832 b1d7ed6f 47fdbeb8
-- Skein-512 Output digest:
-- a46c6177 ddcffcb9 615e7cc0 037c9a4c f7ee0b85 c190a98f 43796ffc 383ac7f3 883e32e9 e3152913 d135f9e4 3657e8a0 eafcb004 4f000551 c26df057 ee90f433
library work;
use work.bk_globals.all;
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned."+";
entity tb_nist5 is
end tb_nist5;
architecture tb of tb_nist5 is
-- components
component db_nist5
port( clk : in std_logic;
msg : in std_logic_vector(639 downto 0);
digest : out std_logic_vector(511 downto 0)
);
end component;
-- signal declarations
signal clk : std_logic;
signal state_in : std_logic_vector (639 downto 0);
signal msg0, msg1, msg2 : std_logic_vector (639 downto 0);
signal dout : std_logic_vector (511 downto 0);
signal rst_n : std_logic;
type st_type is (in0,in1,in2,in3,in4,run,out0,out1,out2,out3,out4,STOP);
signal st : st_type;
signal counter : unsigned(8 downto 0);
begin -- Rtl
-- port map
coremap : db_nist5 port map(clk, state_in, dout);
--main process
rst_n <= '0', '1' after 19 ns;
msg0 <= x"00000000" & x"00000000" & x"00000000" & x"00000000" &
x"00000000" & x"00000000" & x"00000000" & x"00000000" &
x"00000000" & x"00000000" & x"00000000" & x"00000000" &
x"00000000" & x"00000000" & x"00000000" & x"00000000" &
x"00000000" & x"00000000" & x"00000000" & x"00000000";
msg1 <= x"00010203" & x"04050607" & x"08090a0b" & x"0c0d0e0f" &
x"10111213" & x"14151617" & x"18191a1b" & x"1c1d1e1f" &
x"20212223" & x"24252627" & x"28292a2b" & x"2c2d2e2f" &
x"30313233" & x"34353637" & x"38393a3b" & x"3c3d3e3f" &
x"40414243" & x"44454647" & x"48494a4b" & x"4c4d4e4f";
msg2 <= x"716f6e863f744b9ac22c97ec7b76ea5f" &
x"5908bc5b2f67c61510bfc4751384ea7a" &
x"0ce8d4ef4dd7cd8d62dfded9d4edb0a7" &
x"74ae6a41929a74da23109e8f11139c87" &
x"0c7b159452328517463db487df5e39b7";
state_in <= msg1 when (counter=1) else
msg2 when (counter=2) else
msg0;
tbgen : process(clk, rst_n)
variable line_in : line;
variable line_out : line;
variable temp: std_logic_vector(63 downto 0);
file fileout : text open write_mode is "test_vhdlout.txt";
begin
if(rst_n='0') then
st <= in0;
counter <= (others => '0');
elsif(clk'event and clk='1') then
case st is
when in0 =>
counter <= counter+1;
st <= in1;
when in1 =>
counter <= counter+1;
st <= in2;
when in2 =>
counter <= counter+1;
st <= in3;
when in3 =>
counter <= counter+1;
st <= in4;
when in4 =>
counter <= counter+1;
st <= run;
when run =>
if (counter = 265) then
st <= out0;
else
counter <= counter+1;
end if;
when out0 =>
st <= out1;
when out1 =>
for col in 7 downto 0 loop
temp := dout(col*64+63 downto col*64);
hwrite(line_out,temp);
writeline(fileout,line_out);
end loop;
write(fileout,string'("-"));
writeline(fileout,line_out);
st <= out2;
when out2 =>
for col in 7 downto 0 loop
temp := dout(col*64+63 downto col*64);
hwrite(line_out,temp);
writeline(fileout,line_out);
end loop;
write(fileout,string'("-"));
writeline(fileout,line_out);
st <= out3;
when out3 =>
for col in 7 downto 0 loop
temp := dout(col*64+63 downto col*64);
hwrite(line_out,temp);
writeline(fileout,line_out);
end loop;
write(fileout,string'("-"));
writeline(fileout,line_out);
st <= out4;
when out4 =>
for col in 7 downto 0 loop
temp := dout(col*64+63 downto col*64);
hwrite(line_out,temp);
writeline(fileout,line_out);
end loop;
write(fileout,string'("-"));
writeline(fileout,line_out);
st <= STOP;
when STOP =>
null;
end case;
end if;
end process;
-- clock generation
clkgen : process
begin
clk <= '1';
loop
wait for 10 ns;
clk<=not clk;
end loop;
end process;
end tb;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/16/2021 12:58:57 AM
-- Design Name:
-- Module Name: TestBench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestBench is
-- Port ( );
end TestBench;
architecture Behavioral of testBench is
-- Inputs
signal Clock : STD_LOGIC := '1'; --default value for clock
signal X : STD_LOGIC;
signal Y : STD_LOGIC;
signal Z : STD_LOGIC;
-- Outputs
signal P1 : STD_LOGIC;
signal P2 : STD_LOGIC;
signal P5 : STD_LOGIC;
component FSM_OneHot is
Port (
clock : in STD_LOGIC;
X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : in STD_LOGIC;
P1 : out STD_LOGIC;
P2 : out STD_LOGIC;
P5 : out STD_LOGIC
);
end component;
begin
uut : FSM_OneHot port map(
clock => Clock,
X => X,
Y => Y,
Z => Z,
P1 => P1,
P2 => P2,
P5 => P5
);
Clock <= '1' after 2.5 ns when Clock = '0' else
'0' after 2.5 ns when Clock = '1';
tb : process
begin
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '1';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '1';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '1';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '1';
X <= '0';
wait for 5ns;
Z <= '1';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait for 5ns;
Z <= '0';
Y <= '0';
X <= '0';
wait;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Synchronise all signals in a bus. The value on bus_in will
-- appear on bus_out two rising edges later.
-- Use this to synchronize gray counters. Synchronizing
-- busses with more than one signal changing at a time is
-- pointless.
entity bus_sync is
generic (
width : positive
);
port (
bus_in : in std_logic_vector(width - 1 downto 0) := (others => '0');
bus_out : out std_logic_vector(width - 1 downto 0);
clk : in std_logic
);
end bus_sync;
architecture behavioral of bus_sync is
signal temp : std_logic_vector(width - 1 downto 0) := (others => '0');
attribute shreg_extract : string;
attribute shreg_extract of temp : signal is "no";
begin
process(clk)
begin
if rising_edge(clk) then
for i in 0 to width - 1 loop
temp(i) <= bus_in(i);
bus_out(i) <= temp(i);
end loop;
end if;
end process;
end behavioral;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
ENTITY ffjk IS
PORT(j, k, clr, clk : IN BIT;
q, qbar : BUFFER BIT);
END ffjk;
ARCHITECTURE arch OF ffjk IS
BEGIN
PROCESS(j,k,clr,clk)
VARIABLE qv, qvbar : BIT;
BEGIN
IF(clr = '0') THEN
qv := '0';
qvbar := NOT qv;
ELSIF(clk'EVENT AND clk = '0') THEN
IF(j = '1' AND k = '0') THEN
qv := '1';
qvbar := NOT qv;
ELSIF(j = '0' AND k = '1') THEN
qv := '0';
qvbar := NOT qv;
ELSIF(j = '1' AND k = '1') THEN
qv := NOT qv;
qvbar := NOT qv;
ELSE
qv := qv;
qvbar := NOT qv;
END IF;
END IF;
q <= qv;
qbar <= qvbar;
END PROCESS;
END arch;
PACKAGE ffjk_package IS
COMPONENT ffjk
PORT(j, k, clr, clk : IN BIT;
q, qbar : BUFFER BIT);
END COMPONENT;
END ffjk_package;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity QuadratureModulator is
generic (
SIG_IN_WIDTH : positive := 8; -- signal input path width
SIG_OUT_WIDTH : positive := 8 -- signal output path width
);
port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
EN_IN : in STD_LOGIC; -- sample rate must be 8x frequency of interest
EN_OUT : in STD_LOGIC; -- output sample rate could be higher (for example, to maintain precision when bit-width is reduced to small value)
EN_PHASE : in STD_LOGIC; -- enable the PHASE input (overrides PHASE_CHANGE)
PHASE : in STD_LOGIC_VECTOR (SIG_IN_WIDTH-1 downto 0);
EN_PHASE_CHANGE : in STD_LOGIC; -- enable the PHASE_CHANGE input
PHASE_CHANGE : in STD_LOGIC_VECTOR (SIG_IN_WIDTH-1 downto 0);
SIG_OUT : out STD_LOGIC_VECTOR (SIG_OUT_WIDTH-1 downto 0)
);
end QuadratureModulator;
architecture Behavioral of QuadratureModulator is
signal a_in_sig : std_logic_vector (7 downto 0);
signal a_out_sig : std_logic_vector (7 downto 0);
signal phase_sig : std_logic_vector (7 downto 0);
signal phase_change_sig : std_logic_vector (7 downto 0);
signal x_out_sig : std_logic_vector (11 downto 0);
signal y_out_sig : std_logic_vector (11 downto 0);
signal i_out_sig : std_logic_vector (15 downto 0);
signal q_out_sig : std_logic_vector (15 downto 0);
signal sum_sig : std_logic_vector (15 downto 0);
begin
phase_in_coupler: entity work.BitWidthCoupler
generic map (
SIG_IN_WIDTH => SIG_IN_WIDTH,
SIG_OUT_WIDTH => 8
)
port map (
CLK => CLK,
RST => RST,
EN => EN_IN,
SIG_IN => PHASE,
SIG_OUT => phase_sig
);
phase_change_in_coupler: entity work.BitWidthCoupler
generic map (
SIG_IN_WIDTH => SIG_IN_WIDTH,
SIG_OUT_WIDTH => 8
)
port map (
CLK => CLK,
RST => RST,
EN => EN_IN,
SIG_IN => PHASE_CHANGE,
SIG_OUT => phase_change_sig
);
process(EN_PHASE, phase_sig, EN_PHASE_CHANGE, phase_change_sig)
begin
if (EN_PHASE = '1') then
a_in_sig <= phase_sig;
elsif (EN_PHASE_CHANGE = '1') then
a_in_sig <= std_logic_vector(signed(a_out_sig) + signed(phase_change_sig));
else
a_in_sig <= a_out_sig;
end if;
end process;
angle_reg : entity work.Reg1D
generic map (
LENGTH => 8
)
port map (
CLK => CLK,
RST => RST,
PAR_EN => EN_IN,
PAR_IN => a_in_sig,
PAR_OUT => a_out_sig
);
phase_angle: entity work.UnitVector8Bit
port map (
CLK => CLK,
EN => EN_IN,
RST => RST,
A_IN => a_out_sig,
X_OUT => x_out_sig,
Y_OUT => y_out_sig
);
I: entity work.LOMixerPassband
generic map (
SIG_IN_WIDTH => 12, -- signal input path width
SIG_OUT_WIDTH => 16,
PHASE_90_DEG_LAG => false
)
port map (
CLK => CLK,
RST => RST,
EN_IN => EN_IN, -- sample rate must be 8x frequency of interest
EN_OUT => EN_IN,
SIG_IN => x_out_sig,
SIG_OUT => i_out_sig
);
Q: entity work.LOMixerPassband
generic map (
SIG_IN_WIDTH => 12, -- signal input path width
SIG_OUT_WIDTH => 16,
PHASE_90_DEG_LAG => true
)
port map (
CLK => CLK,
RST => RST,
EN_IN => EN_IN, -- sample rate must be 8x frequency of interest
EN_OUT => EN_IN,
SIG_IN => y_out_sig,
SIG_OUT => q_out_sig
);
sum_sig <= std_logic_vector(signed(i_out_sig) + signed(q_out_sig));
sig_out_coupler: entity work.BitWidthCoupler
generic map (
SIG_IN_WIDTH => 16,
SIG_OUT_WIDTH => SIG_OUT_WIDTH
)
port map (
CLK => CLK,
RST => RST,
EN => EN_OUT,
SIG_IN => sum_sig,
SIG_OUT => SIG_OUT
);
end Behavioral;
|
<reponame>nfproc/DRFront
-- DRFront: A Dynamic Reconfiguration Frontend for Xilinx FPGAs
-- Copyright (C) 2022 <NAME>. New BSD License is applied.
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
-- This is a top module of the whole circuit implemented on an FPGA.
entity TOP is
port ( SW : in std_logic_vector(15 downto 0);
BTNC, BTNL, BTNR, BTNU, BTND : in std_logic;
CLK, RST_X : in std_logic;
LD : out std_logic_vector(15 downto 0);
AN : out std_logic_vector(7 downto 0);
CA, CB, CC, CD, CE, CF, CG, DP : out std_logic);
end TOP;
architecture STRUCTURE of TOP is
component DR_TOP is
port ( SW : in std_logic_vector(15 downto 0);
BTNC, BTNL, BTNR, BTNU, BTND : in std_logic;
CLK, RST : in std_logic;
LD : out std_logic_vector(15 downto 0);
AN : out std_logic_vector(7 downto 0);
CA, CB, CC, CD, CE, CF, CG, DP : out std_logic);
end component;
signal INT_RST : std_logic;
signal INT_SW : std_logic_vector(15 downto 0);
signal INT_BTNC, INT_BTNL, INT_BTNR, INT_BTNU, INT_BTND : std_logic;
signal INT_LD : std_logic_vector(15 downto 0);
signal INT_AN : std_logic_vector(7 downto 0);
signal INT_CA, INT_CB, INT_CC, INT_CD : std_logic;
signal INT_CE, INT_CF, INT_CG, INT_DP : std_logic;
begin
process (CLK) begin
if (rising_edge(CLK)) then
INT_RST <= not RST_X;
INT_SW <= SW;
INT_BTNC <= BTNC;
INT_BTNL <= BTNL;
INT_BTNR <= BTNR;
INT_BTNU <= BTNU;
INT_BTND <= BTND;
LD <= INT_LD;
AN <= INT_AN;
CA <= INT_CA;
CB <= INT_CB;
CC <= INT_CC;
CD <= INT_CD;
CE <= INT_CE;
CF <= INT_CF;
CG <= INT_CG;
DP <= INT_DP;
end if;
end process;
DR : DR_TOP port map (
SW => INT_SW,
BTNC => INT_BTNC,
BTNL => INT_BTNL,
BTNR => INT_BTNR,
BTNU => INT_BTNU,
BTND => INT_BTND,
CLK => CLK,
RST => INT_RST,
LD => INT_LD,
AN => INT_AN,
CA => INT_CA,
CB => INT_CB,
CC => INT_CC,
CD => INT_CD,
CE => INT_CE,
CF => INT_CF,
CG => INT_CG,
DP => INT_DP);
end STRUCTURE;
|
<gh_stars>1-10
-----------------------------------------------------------------
-- COMPANY : Ruhr University Bochum
-- AUTHOR : <NAME> (<EMAIL>) and <NAME> (<EMAIL>)
-- DOCUMENT: [New First-Order Secure AES Performance Records](IACR Transactions on Cryptographic Hardware and Embeded Systems 2021(2))
-- -----------------------------------------------------------------
--
-- Copyright (c) 2021, <NAME>, <NAME>,
--
-- All rights reserved.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTERS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Please see LICENSE and README for license and further instructions.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY KeySchedule is
GENERIC ( ShareNumber : integer );
PORT ( clk : in STD_LOGIC;
ShowRcon : in STD_LOGIC;
Rcon : in STD_LOGIC_VECTOR (7 downto 0);
S_key : in STD_LOGIC_VECTOR (7 downto 0);
K0 : in STD_LOGIC_VECTOR (7 downto 0);
Key_forCipherText : out STD_LOGIC_VECTOR (7 downto 0);
Key_out : out STD_LOGIC_VECTOR (7 downto 0));
END KeySchedule;
architecture Behavioral of KeySchedule is
begin
GenShareNumber1: IF ShareNumber = 1 GENERATE
Key_out <= S_key xor K0 xor Rcon;
Key_forCipherText <= S_key xor K0 xor Rcon;
END GENERATE;
GenShareNumber2: IF ShareNumber = 2 GENERATE
Key_out <= S_key xor K0;
Key_forCipherText <= S_key xor K0;
END GENERATE;
end Behavioral;
|
<gh_stars>1-10
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2020.1
-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_handler_compute_i is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ipDataMetaFifo_V_dat_dout : IN STD_LOGIC_VECTOR (511 downto 0);
ipDataMetaFifo_V_dat_empty_n : IN STD_LOGIC;
ipDataMetaFifo_V_dat_read : OUT STD_LOGIC;
ipDataMetaFifo_V_kee_dout : IN STD_LOGIC_VECTOR (63 downto 0);
ipDataMetaFifo_V_kee_empty_n : IN STD_LOGIC;
ipDataMetaFifo_V_kee_read : OUT STD_LOGIC;
ipDataMetaFifo_V_las_dout : IN STD_LOGIC_VECTOR (0 downto 0);
ipDataMetaFifo_V_las_empty_n : IN STD_LOGIC;
ipDataMetaFifo_V_las_read : OUT STD_LOGIC;
ipDataCheckFifo_V_din : OUT STD_LOGIC_VECTOR (576 downto 0);
ipDataCheckFifo_V_full_n : IN STD_LOGIC;
ipDataCheckFifo_V_write : OUT STD_LOGIC;
iph_subSumsFifoOut_V_din : OUT STD_LOGIC_VECTOR (543 downto 0);
iph_subSumsFifoOut_V_full_n : IN STD_LOGIC;
iph_subSumsFifoOut_V_write : OUT STD_LOGIC );
end;
architecture behav of ip_handler_compute_i is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_68 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101000";
constant ap_const_lv32_6F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_67 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100111";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
constant ap_const_lv32_77 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110111";
constant ap_const_lv32_88 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001000";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_87 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000111";
constant ap_const_lv32_98 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_97 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010111";
constant ap_const_lv32_A8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101000";
constant ap_const_lv32_AF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_A7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100111";
constant ap_const_lv32_B8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_B0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110000";
constant ap_const_lv32_B7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110111";
constant ap_const_lv32_C8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001000";
constant ap_const_lv32_CF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001111";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_C7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000111";
constant ap_const_lv32_D8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_D0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010000";
constant ap_const_lv32_D7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010111";
constant ap_const_lv32_E8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101000";
constant ap_const_lv32_EF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101111";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_E7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100111";
constant ap_const_lv32_F8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_F0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110000";
constant ap_const_lv32_F7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110111";
constant ap_const_lv32_108 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001000";
constant ap_const_lv32_10F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001111";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_107 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000111";
constant ap_const_lv32_118 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_110 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010000";
constant ap_const_lv32_117 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010111";
constant ap_const_lv32_128 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101000";
constant ap_const_lv32_12F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101111";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_127 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100111";
constant ap_const_lv32_138 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111000";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_130 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110000";
constant ap_const_lv32_137 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110111";
constant ap_const_lv32_148 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001000";
constant ap_const_lv32_14F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001111";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_147 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000111";
constant ap_const_lv32_158 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011000";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_150 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010000";
constant ap_const_lv32_157 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010111";
constant ap_const_lv32_168 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101101000";
constant ap_const_lv32_16F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101101111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_167 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100111";
constant ap_const_lv32_178 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111000";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_170 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101110000";
constant ap_const_lv32_177 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101110111";
constant ap_const_lv32_188 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110001000";
constant ap_const_lv32_18F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110001111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_187 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000111";
constant ap_const_lv32_198 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv32_190 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110010000";
constant ap_const_lv32_197 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110010111";
constant ap_const_lv32_1A8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110101000";
constant ap_const_lv32_1AF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110101111";
constant ap_const_lv32_1A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110100000";
constant ap_const_lv32_1A7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110100111";
constant ap_const_lv32_1B8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110111000";
constant ap_const_lv32_1BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110111111";
constant ap_const_lv32_1B0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110110000";
constant ap_const_lv32_1B7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110110111";
constant ap_const_lv32_1C8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111001000";
constant ap_const_lv32_1CF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111001111";
constant ap_const_lv32_1C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111000000";
constant ap_const_lv32_1C7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111000111";
constant ap_const_lv32_1D8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111011000";
constant ap_const_lv32_1DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111011111";
constant ap_const_lv32_1D0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111010000";
constant ap_const_lv32_1D7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111010111";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv4_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_const_lv4_A : STD_LOGIC_VECTOR (3 downto 0) := "1010";
constant ap_const_lv4_B : STD_LOGIC_VECTOR (3 downto 0) := "1011";
constant ap_const_lv4_C : STD_LOGIC_VECTOR (3 downto 0) := "1100";
constant ap_const_lv4_D : STD_LOGIC_VECTOR (3 downto 0) := "1101";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv34_0 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal io_acc_block_signal_op5 : STD_LOGIC;
signal tmp_nbreadreq_fu_388_p5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal tmp_reg_3994 : STD_LOGIC_VECTOR (0 downto 0);
signal cics_firstWord_load_reg_4064 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_predicate_op429_write_state2 : BOOLEAN;
signal ap_block_state2_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal cics_firstWord : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal cics_ip_sums_sum_V_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_1 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_2 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_3 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_4 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_5 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_6 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_7 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_8 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_9 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_10 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_11 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_12 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_13 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_14 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_15 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_16 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_17 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_18 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_19 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_20 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_21 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_22 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_23 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_24 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_25 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_26 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_27 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_28 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal cics_ip_sums_sum_V_29 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
signal ipDataMetaFifo_V_dat_blk_n : STD_LOGIC;
signal ap_block_pp0_stage0 : BOOLEAN;
signal ipDataMetaFifo_V_kee_blk_n : STD_LOGIC;
signal ipDataMetaFifo_V_las_blk_n : STD_LOGIC;
signal ipDataCheckFifo_V_blk_n : STD_LOGIC;
signal iph_subSumsFifoOut_V_blk_n : STD_LOGIC;
signal tmp_data_V_reg_3998 : STD_LOGIC_VECTOR (511 downto 0);
signal tmp_keep_V_reg_4007 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_last_V_reg_4012 : STD_LOGIC_VECTOR (0 downto 0);
signal cics_firstWord_load_load_fu_943_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal cics_ip_sums_sum_V_0_1_reg_4068 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_1_reg_4074 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_1_reg_4080 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_3_1_reg_4086 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_4_1_reg_4092 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_5_1_reg_4098 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_6_1_reg_4104 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_7_1_reg_4110 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_8_1_reg_4116 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_9_1_reg_4122 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_2_reg_4128 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_3_reg_4134 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_4_reg_4140 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_5_reg_4146 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_6_reg_4152 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_7_reg_4158 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_8_reg_4164 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_9_reg_4170 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_10_reg_4176 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_1_11_reg_4182 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_2_reg_4188 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_3_reg_4194 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_4_reg_4200 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_5_reg_4206 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_6_reg_4212 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_7_reg_4218 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_8_reg_4224 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_9_reg_4230 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_10_reg_4236 : STD_LOGIC_VECTOR (16 downto 0);
signal cics_ip_sums_sum_V_2_11_reg_4242 : STD_LOGIC_VECTOR (16 downto 0);
signal agg_result_V_0_1_i_i_fu_1081_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i_i_reg_4248 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_13_reg_4253 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i_fu_1127_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i_reg_4258 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_14_reg_4263 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i1_fu_1173_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i1_reg_4268 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_reg_4273 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i14_1_fu_1219_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i14_1_reg_4278 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_17_reg_4283 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i14_2_fu_1265_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i14_2_reg_4288 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_18_reg_4293 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i14_3_fu_1311_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i14_3_reg_4298 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_19_reg_4303 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i2_fu_1357_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i2_reg_4308 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_21_reg_4313 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i15_1_fu_1403_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i15_1_reg_4318 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_22_reg_4323 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i15_2_fu_1449_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i15_2_reg_4328 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_23_reg_4333 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i3_fu_1495_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i3_reg_4338 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_24_reg_4343 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i16_1_fu_1541_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i16_1_reg_4348 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_25_reg_4353 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i16_2_fu_1587_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i16_2_reg_4358 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_26_reg_4363 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i4_fu_1633_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i4_reg_4368 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_27_reg_4373 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i17_1_fu_1679_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i17_1_reg_4378 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_28_reg_4383 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i17_2_fu_1725_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i17_2_reg_4388 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_30_reg_4393 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i17_3_fu_1771_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i17_3_reg_4398 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_31_reg_4403 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i5_fu_1817_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i5_reg_4408 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_32_reg_4413 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i18_1_fu_1863_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i18_1_reg_4418 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_33_reg_4423 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i18_2_fu_1909_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i18_2_reg_4428 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_34_reg_4433 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i6_fu_1955_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i6_reg_4438 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_35_reg_4443 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i19_1_fu_2001_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i19_1_reg_4448 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_36_reg_4453 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i19_2_fu_2047_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i19_2_reg_4458 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_37_reg_4463 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i7_fu_2093_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i7_reg_4468 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_38_reg_4473 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i20_1_fu_2139_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i20_1_reg_4478 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_39_reg_4483 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i20_2_fu_2185_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i20_2_reg_4488 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_40_reg_4493 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i20_3_fu_2231_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i20_3_reg_4498 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_41_reg_4503 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i8_fu_2277_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i8_reg_4508 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_42_reg_4513 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i21_1_fu_2323_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i21_1_reg_4518 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_43_reg_4523 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i21_2_fu_2369_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i21_2_reg_4528 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_44_reg_4533 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_V_0_1_i9_fu_2415_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_V_0_1_i9_reg_4538 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_45_reg_4543 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_phi_mux_cics_firstWord_flag_s_phi_fu_428_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_firstWord_flag_s_reg_424 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_firstWord_flag_s_reg_424 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_0_2_phi_fu_440_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal xor_ln887_fu_2479_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_2_reg_436 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_0_2_reg_436 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_0_3_phi_fu_451_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_fu_2486_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_3_reg_447 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_12_phi_fu_462_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_1_fu_2515_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_12_reg_458 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_12_phi_fu_473_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_1_fu_2532_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_12_reg_469 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_12_reg_469 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_13_phi_fu_484_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_2_fu_2560_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_13_reg_480 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_3_2_phi_fu_495_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_3_fu_2589_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_3_2_reg_491 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_4_2_phi_fu_506_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_2_fu_2597_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_2_reg_502 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_4_2_reg_502 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_4_3_phi_fu_517_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_4_fu_2625_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_3_reg_513 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_5_2_phi_fu_528_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_5_fu_2654_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_5_2_reg_524 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_6_2_phi_fu_539_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_3_fu_2671_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_2_reg_535 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_6_2_reg_535 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_6_3_phi_fu_550_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_6_fu_2699_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_3_reg_546 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_7_2_phi_fu_561_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_7_fu_2728_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_7_2_reg_557 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_8_2_phi_fu_572_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_4_fu_2736_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_2_reg_568 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_8_2_reg_568 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_8_3_phi_fu_583_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_8_fu_2764_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_3_reg_579 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_9_2_phi_fu_594_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_9_fu_2793_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_9_2_reg_590 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_13_phi_fu_605_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_5_fu_2801_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_13_reg_601 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_13_reg_601 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_14_phi_fu_616_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_10_fu_2829_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_14_reg_612 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_15_phi_fu_627_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_11_fu_2858_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_15_reg_623 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_16_phi_fu_638_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_6_fu_2866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_16_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_16_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_17_phi_fu_649_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_12_fu_2894_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_17_reg_645 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_18_phi_fu_660_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_13_fu_2923_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_18_reg_656 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_19_phi_fu_671_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_2931_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_19_reg_667 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_19_reg_667 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_20_phi_fu_682_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_14_fu_2960_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_20_reg_678 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_21_phi_fu_693_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_15_fu_2989_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_21_reg_689 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_22_phi_fu_704_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_7_fu_2997_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_22_reg_700 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_22_reg_700 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_23_phi_fu_715_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_16_fu_3025_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_23_reg_711 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_24_phi_fu_726_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_17_fu_3054_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_24_reg_722 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_25_phi_fu_737_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_8_fu_3062_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_25_reg_733 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_25_reg_733 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_26_phi_fu_748_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_18_fu_3090_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_26_reg_744 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_1_27_phi_fu_759_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_19_fu_3119_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_27_reg_755 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_14_phi_fu_770_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_9_fu_3127_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_14_reg_766 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_14_reg_766 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_15_phi_fu_781_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_20_fu_3155_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_15_reg_777 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_16_phi_fu_792_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_21_fu_3184_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_16_reg_788 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_17_phi_fu_803_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_10_fu_3192_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_17_reg_799 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_17_reg_799 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_18_phi_fu_814_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_22_fu_3220_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_18_reg_810 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_19_phi_fu_825_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_23_fu_3249_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_19_reg_821 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_20_phi_fu_836_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_11_fu_3257_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_20_reg_832 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_20_reg_832 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_21_phi_fu_847_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_24_fu_3285_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_21_reg_843 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_22_phi_fu_858_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_25_fu_3314_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_22_reg_854 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_23_phi_fu_869_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_12_fu_3322_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_23_reg_865 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_23_reg_865 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_24_phi_fu_880_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_26_fu_3350_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_24_reg_876 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_25_phi_fu_891_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_27_fu_3379_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_25_reg_887 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_26_phi_fu_902_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln887_13_fu_3387_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_26_reg_898 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_26_reg_898 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_27_phi_fu_913_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_28_fu_3415_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_27_reg_909 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_mux_cics_ip_sums_sum_V_2_28_phi_fu_924_p4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln887_29_fu_3444_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_28_reg_920 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_fu_3519_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_firstWord_load : STD_LOGIC_VECTOR (0 downto 0);
signal select_ln566_fu_3529_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_1_fu_3524_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_0_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_1_fu_3536_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_2_fu_3548_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_2_fu_3543_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_3_fu_3555_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_3_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_4_fu_3567_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_3_fu_3562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_4_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_5_fu_3574_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_5_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_6_fu_3586_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_4_fu_3581_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_6_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_7_fu_3593_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_7_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_8_fu_3605_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_5_fu_3600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_8_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_9_fu_3612_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_9_1 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_10_fu_3624_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_6_fu_3619_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_2 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_11_fu_3631_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_3 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_12_fu_3643_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_7_fu_3638_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_13_fu_3650_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_5 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_14_fu_3662_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_8_fu_3657_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_6 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_15_fu_3669_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_7 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_16_fu_3681_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_9_fu_3676_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_8 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_17_fu_3688_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_9 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_18_fu_3700_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_10_fu_3695_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_10 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_19_fu_3707_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_1_11 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_20_fu_3719_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_11_fu_3714_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_2 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_21_fu_3726_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_3 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_22_fu_3738_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_12_fu_3733_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_4 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_23_fu_3745_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_5 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_24_fu_3757_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_13_fu_3752_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_6 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_25_fu_3764_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_7 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_26_fu_3776_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_14_fu_3771_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_8 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_27_fu_3783_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_9 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_28_fu_3795_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal or_ln566_15_fu_3790_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_10 : STD_LOGIC_VECTOR (16 downto 0);
signal select_ln566_29_fu_3802_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_allocacmp_cics_ip_sums_sum_V_2_11 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal trunc_ln647_3_fu_1077_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i_i_fu_1067_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_fu_1089_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_fu_1093_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i136_s_fu_1117_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i135_i_fu_1107_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_1_fu_1135_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_1_fu_1139_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i139_s_fu_1163_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i138_i_fu_1153_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_2_fu_1181_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_2_fu_1185_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i142_s_fu_1209_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i141_i_fu_1199_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_3_fu_1227_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_3_fu_1231_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i145_s_fu_1255_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i144_i_fu_1245_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_4_fu_1273_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_4_fu_1277_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i148_s_fu_1301_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i147_i_fu_1291_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_5_fu_1319_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_5_fu_1323_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i151_s_fu_1347_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i150_i_fu_1337_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_6_fu_1365_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_6_fu_1369_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i154_s_fu_1393_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i153_i_fu_1383_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_7_fu_1411_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_7_fu_1415_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i157_s_fu_1439_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i156_i_fu_1429_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_8_fu_1457_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_8_fu_1461_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i160_s_fu_1485_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i159_i_fu_1475_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_9_fu_1503_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_9_fu_1507_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i163_s_fu_1531_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i162_i_fu_1521_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_10_fu_1549_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_10_fu_1553_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i166_s_fu_1577_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i165_i_fu_1567_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_11_fu_1595_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_11_fu_1599_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i169_s_fu_1623_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i168_i_fu_1613_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_12_fu_1641_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_12_fu_1645_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i172_s_fu_1669_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i171_i_fu_1659_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_13_fu_1687_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_13_fu_1691_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i175_s_fu_1715_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i174_i_fu_1705_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_14_fu_1733_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_14_fu_1737_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i178_s_fu_1761_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i177_i_fu_1751_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_15_fu_1779_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_15_fu_1783_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i181_s_fu_1807_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i180_i_fu_1797_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_16_fu_1825_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_16_fu_1829_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i184_s_fu_1853_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i183_i_fu_1843_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_17_fu_1871_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_17_fu_1875_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i187_s_fu_1899_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i186_i_fu_1889_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_18_fu_1917_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_18_fu_1921_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i190_s_fu_1945_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i189_i_fu_1935_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_19_fu_1963_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_19_fu_1967_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i193_s_fu_1991_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i192_i_fu_1981_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_20_fu_2009_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_20_fu_2013_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i196_s_fu_2037_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i195_i_fu_2027_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_21_fu_2055_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_21_fu_2059_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i199_s_fu_2083_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i198_i_fu_2073_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_22_fu_2101_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_22_fu_2105_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i202_s_fu_2129_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i201_i_fu_2119_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_23_fu_2147_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_23_fu_2151_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i205_s_fu_2175_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i204_i_fu_2165_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_24_fu_2193_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_24_fu_2197_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i208_s_fu_2221_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i207_i_fu_2211_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_25_fu_2239_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_25_fu_2243_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i211_s_fu_2267_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i210_i_fu_2257_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_26_fu_2285_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_26_fu_2289_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i214_s_fu_2313_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i213_i_fu_2303_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_27_fu_2331_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_27_fu_2335_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i217_s_fu_2359_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i216_i_fu_2349_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_28_fu_2377_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_28_fu_2381_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Result_2_1_i220_s_fu_2405_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_i219_i_fu_2395_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln700_29_fu_2423_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal add_ln700_29_fu_2427_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal trunc_ln647_fu_2449_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal zext_ln214_30_fu_2461_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_fu_2458_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_fu_2464_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_1_fu_2470_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal icmp_ln887_fu_2452_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal zext_ln214_fu_2475_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_31_fu_2497_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_1_fu_2494_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_2_fu_2500_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_3_fu_2506_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_1_fu_2511_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_15_fu_2523_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal zext_ln214_32_fu_2542_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_2_fu_2539_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_4_fu_2545_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_5_fu_2551_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_2_fu_2556_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_33_fu_2571_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_3_fu_2568_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_6_fu_2574_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_7_fu_2580_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_3_fu_2585_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_34_fu_2607_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_4_fu_2604_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_8_fu_2610_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_9_fu_2616_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_4_fu_2621_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_35_fu_2636_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_5_fu_2633_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_10_fu_2639_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_11_fu_2645_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_5_fu_2650_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_20_fu_2662_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal zext_ln214_36_fu_2681_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_6_fu_2678_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_12_fu_2684_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_13_fu_2690_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_6_fu_2695_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_37_fu_2710_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_7_fu_2707_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_14_fu_2713_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_15_fu_2719_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_7_fu_2724_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_38_fu_2746_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_8_fu_2743_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_16_fu_2749_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_17_fu_2755_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_8_fu_2760_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_39_fu_2775_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_9_fu_2772_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_18_fu_2778_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_19_fu_2784_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_9_fu_2789_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_40_fu_2811_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_10_fu_2808_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_20_fu_2814_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_21_fu_2820_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_10_fu_2825_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_41_fu_2840_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_11_fu_2837_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_22_fu_2843_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_23_fu_2849_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_11_fu_2854_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_42_fu_2876_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_12_fu_2873_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_24_fu_2879_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_25_fu_2885_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_12_fu_2890_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_43_fu_2905_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_13_fu_2902_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_26_fu_2908_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_27_fu_2914_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_13_fu_2919_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_44_fu_2942_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_14_fu_2939_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_28_fu_2945_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_29_fu_2951_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_14_fu_2956_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_45_fu_2971_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_15_fu_2968_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_30_fu_2974_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_31_fu_2980_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_15_fu_2985_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_46_fu_3007_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_16_fu_3004_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_32_fu_3010_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_33_fu_3016_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_16_fu_3021_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_47_fu_3036_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_17_fu_3033_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_34_fu_3039_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_35_fu_3045_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_17_fu_3050_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_48_fu_3072_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_18_fu_3069_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_36_fu_3075_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_37_fu_3081_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_18_fu_3086_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_49_fu_3101_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_19_fu_3098_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_38_fu_3104_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_39_fu_3110_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_19_fu_3115_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_50_fu_3137_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_20_fu_3134_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_40_fu_3140_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_41_fu_3146_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_20_fu_3151_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_51_fu_3166_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_21_fu_3163_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_42_fu_3169_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_43_fu_3175_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_21_fu_3180_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_52_fu_3202_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_22_fu_3199_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_44_fu_3205_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_45_fu_3211_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_22_fu_3216_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_53_fu_3231_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_23_fu_3228_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_46_fu_3234_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_47_fu_3240_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_23_fu_3245_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_54_fu_3267_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_24_fu_3264_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_48_fu_3270_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_49_fu_3276_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_24_fu_3281_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_55_fu_3296_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_25_fu_3293_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_50_fu_3299_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_51_fu_3305_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_25_fu_3310_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_56_fu_3332_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_26_fu_3329_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_52_fu_3335_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_53_fu_3341_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_26_fu_3346_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_57_fu_3361_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_27_fu_3358_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_54_fu_3364_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_55_fu_3370_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_27_fu_3375_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_58_fu_3397_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_28_fu_3394_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_56_fu_3400_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_57_fu_3406_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_28_fu_3411_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal zext_ln214_59_fu_3426_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal trunc_ln700_29_fu_3423_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_58_fu_3429_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal add_ln214_59_fu_3435_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal zext_ln214_29_fu_3440_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_idle_pp0_0to0 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal ap_condition_86 : BOOLEAN;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter1 <= ap_start;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_firstWord_flag_s_reg_424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_firstWord_flag_s_reg_424 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_firstWord_flag_s_reg_424 <= ap_phi_reg_pp0_iter0_cics_firstWord_flag_s_reg_424;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_2_reg_436_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_2_reg_436 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_2_reg_436 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_0_2_reg_436;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_13_reg_601_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_13_reg_601 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_13_reg_601 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_13_reg_601;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_16_reg_634_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_16_reg_634 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_16_reg_634 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_16_reg_634;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_19_reg_667_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_19_reg_667 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_19_reg_667 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_19_reg_667;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_22_reg_700_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_22_reg_700 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_22_reg_700 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_22_reg_700;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_25_reg_733_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_25_reg_733 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_25_reg_733 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_25_reg_733;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_12_reg_469_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_12_reg_469 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_12_reg_469 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_12_reg_469;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_14_reg_766_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_14_reg_766 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_14_reg_766 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_14_reg_766;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_17_reg_799_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_17_reg_799 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_17_reg_799 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_17_reg_799;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_20_reg_832_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_20_reg_832 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_20_reg_832 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_20_reg_832;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_23_reg_865_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_23_reg_865 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_23_reg_865 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_23_reg_865;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_26_reg_898_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_26_reg_898 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_26_reg_898 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_26_reg_898;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_2_reg_502_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_2_reg_502 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_2_reg_502 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_4_2_reg_502;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_2_reg_535_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_2_reg_535 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_2_reg_535 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_6_2_reg_535;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_2_reg_568_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_86)) then
if (((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_2_reg_568 <= ap_const_lv1_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_2_reg_568 <= ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_8_2_reg_568;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (cics_firstWord_load_load_fu_943_p1 = ap_const_lv1_1) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
agg_result_V_0_1_i14_1_reg_4278 <= agg_result_V_0_1_i14_1_fu_1219_p3;
agg_result_V_0_1_i14_2_reg_4288 <= agg_result_V_0_1_i14_2_fu_1265_p3;
agg_result_V_0_1_i14_3_reg_4298 <= agg_result_V_0_1_i14_3_fu_1311_p3;
agg_result_V_0_1_i15_1_reg_4318 <= agg_result_V_0_1_i15_1_fu_1403_p3;
agg_result_V_0_1_i15_2_reg_4328 <= agg_result_V_0_1_i15_2_fu_1449_p3;
agg_result_V_0_1_i16_1_reg_4348 <= agg_result_V_0_1_i16_1_fu_1541_p3;
agg_result_V_0_1_i16_2_reg_4358 <= agg_result_V_0_1_i16_2_fu_1587_p3;
agg_result_V_0_1_i17_1_reg_4378 <= agg_result_V_0_1_i17_1_fu_1679_p3;
agg_result_V_0_1_i17_2_reg_4388 <= agg_result_V_0_1_i17_2_fu_1725_p3;
agg_result_V_0_1_i17_3_reg_4398 <= agg_result_V_0_1_i17_3_fu_1771_p3;
agg_result_V_0_1_i18_1_reg_4418 <= agg_result_V_0_1_i18_1_fu_1863_p3;
agg_result_V_0_1_i18_2_reg_4428 <= agg_result_V_0_1_i18_2_fu_1909_p3;
agg_result_V_0_1_i19_1_reg_4448 <= agg_result_V_0_1_i19_1_fu_2001_p3;
agg_result_V_0_1_i19_2_reg_4458 <= agg_result_V_0_1_i19_2_fu_2047_p3;
agg_result_V_0_1_i1_reg_4268 <= agg_result_V_0_1_i1_fu_1173_p3;
agg_result_V_0_1_i20_1_reg_4478 <= agg_result_V_0_1_i20_1_fu_2139_p3;
agg_result_V_0_1_i20_2_reg_4488 <= agg_result_V_0_1_i20_2_fu_2185_p3;
agg_result_V_0_1_i20_3_reg_4498 <= agg_result_V_0_1_i20_3_fu_2231_p3;
agg_result_V_0_1_i21_1_reg_4518 <= agg_result_V_0_1_i21_1_fu_2323_p3;
agg_result_V_0_1_i21_2_reg_4528 <= agg_result_V_0_1_i21_2_fu_2369_p3;
agg_result_V_0_1_i2_reg_4308 <= agg_result_V_0_1_i2_fu_1357_p3;
agg_result_V_0_1_i3_reg_4338 <= agg_result_V_0_1_i3_fu_1495_p3;
agg_result_V_0_1_i4_reg_4368 <= agg_result_V_0_1_i4_fu_1633_p3;
agg_result_V_0_1_i5_reg_4408 <= agg_result_V_0_1_i5_fu_1817_p3;
agg_result_V_0_1_i6_reg_4438 <= agg_result_V_0_1_i6_fu_1955_p3;
agg_result_V_0_1_i7_reg_4468 <= agg_result_V_0_1_i7_fu_2093_p3;
agg_result_V_0_1_i8_reg_4508 <= agg_result_V_0_1_i8_fu_2277_p3;
agg_result_V_0_1_i9_reg_4538 <= agg_result_V_0_1_i9_fu_2415_p3;
agg_result_V_0_1_i_i_reg_4248 <= agg_result_V_0_1_i_i_fu_1081_p3;
agg_result_V_0_1_i_reg_4258 <= agg_result_V_0_1_i_fu_1127_p3;
tmp_13_reg_4253 <= add_ln700_fu_1093_p2(16 downto 16);
tmp_14_reg_4263 <= add_ln700_1_fu_1139_p2(16 downto 16);
tmp_16_reg_4273 <= add_ln700_2_fu_1185_p2(16 downto 16);
tmp_17_reg_4283 <= add_ln700_3_fu_1231_p2(16 downto 16);
tmp_18_reg_4293 <= add_ln700_4_fu_1277_p2(16 downto 16);
tmp_19_reg_4303 <= add_ln700_5_fu_1323_p2(16 downto 16);
tmp_21_reg_4313 <= add_ln700_6_fu_1369_p2(16 downto 16);
tmp_22_reg_4323 <= add_ln700_7_fu_1415_p2(16 downto 16);
tmp_23_reg_4333 <= add_ln700_8_fu_1461_p2(16 downto 16);
tmp_24_reg_4343 <= add_ln700_9_fu_1507_p2(16 downto 16);
tmp_25_reg_4353 <= add_ln700_10_fu_1553_p2(16 downto 16);
tmp_26_reg_4363 <= add_ln700_11_fu_1599_p2(16 downto 16);
tmp_27_reg_4373 <= add_ln700_12_fu_1645_p2(16 downto 16);
tmp_28_reg_4383 <= add_ln700_13_fu_1691_p2(16 downto 16);
tmp_30_reg_4393 <= add_ln700_14_fu_1737_p2(16 downto 16);
tmp_31_reg_4403 <= add_ln700_15_fu_1783_p2(16 downto 16);
tmp_32_reg_4413 <= add_ln700_16_fu_1829_p2(16 downto 16);
tmp_33_reg_4423 <= add_ln700_17_fu_1875_p2(16 downto 16);
tmp_34_reg_4433 <= add_ln700_18_fu_1921_p2(16 downto 16);
tmp_35_reg_4443 <= add_ln700_19_fu_1967_p2(16 downto 16);
tmp_36_reg_4453 <= add_ln700_20_fu_2013_p2(16 downto 16);
tmp_37_reg_4463 <= add_ln700_21_fu_2059_p2(16 downto 16);
tmp_38_reg_4473 <= add_ln700_22_fu_2105_p2(16 downto 16);
tmp_39_reg_4483 <= add_ln700_23_fu_2151_p2(16 downto 16);
tmp_40_reg_4493 <= add_ln700_24_fu_2197_p2(16 downto 16);
tmp_41_reg_4503 <= add_ln700_25_fu_2243_p2(16 downto 16);
tmp_42_reg_4513 <= add_ln700_26_fu_2289_p2(16 downto 16);
tmp_43_reg_4523 <= add_ln700_27_fu_2335_p2(16 downto 16);
tmp_44_reg_4533 <= add_ln700_28_fu_2381_p2(16 downto 16);
tmp_45_reg_4543 <= add_ln700_29_fu_2427_p2(16 downto 16);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_fu_3519_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_firstWord <= tmp_last_V_reg_4012;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_firstWord_load_reg_4064 <= ap_sig_allocacmp_cics_firstWord_load;
cics_ip_sums_sum_V_0_1_reg_4068 <= ap_sig_allocacmp_cics_ip_sums_sum_V_0_1;
cics_ip_sums_sum_V_1_10_reg_4176 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_10;
cics_ip_sums_sum_V_1_11_reg_4182 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_11;
cics_ip_sums_sum_V_1_1_reg_4074 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_1;
cics_ip_sums_sum_V_1_2_reg_4128 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_2;
cics_ip_sums_sum_V_1_3_reg_4134 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_3;
cics_ip_sums_sum_V_1_4_reg_4140 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_4;
cics_ip_sums_sum_V_1_5_reg_4146 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_5;
cics_ip_sums_sum_V_1_6_reg_4152 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_6;
cics_ip_sums_sum_V_1_7_reg_4158 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_7;
cics_ip_sums_sum_V_1_8_reg_4164 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_8;
cics_ip_sums_sum_V_1_9_reg_4170 <= ap_sig_allocacmp_cics_ip_sums_sum_V_1_9;
cics_ip_sums_sum_V_2_10_reg_4236 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_10;
cics_ip_sums_sum_V_2_11_reg_4242 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_11;
cics_ip_sums_sum_V_2_1_reg_4080 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_1;
cics_ip_sums_sum_V_2_2_reg_4188 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_2;
cics_ip_sums_sum_V_2_3_reg_4194 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_3;
cics_ip_sums_sum_V_2_4_reg_4200 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_4;
cics_ip_sums_sum_V_2_5_reg_4206 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_5;
cics_ip_sums_sum_V_2_6_reg_4212 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_6;
cics_ip_sums_sum_V_2_7_reg_4218 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_7;
cics_ip_sums_sum_V_2_8_reg_4224 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_8;
cics_ip_sums_sum_V_2_9_reg_4230 <= ap_sig_allocacmp_cics_ip_sums_sum_V_2_9;
cics_ip_sums_sum_V_3_1_reg_4086 <= ap_sig_allocacmp_cics_ip_sums_sum_V_3_1;
cics_ip_sums_sum_V_4_1_reg_4092 <= ap_sig_allocacmp_cics_ip_sums_sum_V_4_1;
cics_ip_sums_sum_V_5_1_reg_4098 <= ap_sig_allocacmp_cics_ip_sums_sum_V_5_1;
cics_ip_sums_sum_V_6_1_reg_4104 <= ap_sig_allocacmp_cics_ip_sums_sum_V_6_1;
cics_ip_sums_sum_V_7_1_reg_4110 <= ap_sig_allocacmp_cics_ip_sums_sum_V_7_1;
cics_ip_sums_sum_V_8_1_reg_4116 <= ap_sig_allocacmp_cics_ip_sums_sum_V_8_1;
cics_ip_sums_sum_V_9_1_reg_4122 <= ap_sig_allocacmp_cics_ip_sums_sum_V_9_1;
tmp_data_V_reg_3998 <= ipDataMetaFifo_V_dat_dout;
tmp_keep_V_reg_4007 <= ipDataMetaFifo_V_kee_dout;
tmp_last_V_reg_4012 <= ipDataMetaFifo_V_las_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_1_fu_3524_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_0 <= select_ln566_fu_3529_p3;
cics_ip_sums_sum_V_1 <= select_ln566_1_fu_3536_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_6_fu_3619_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_10 <= select_ln566_10_fu_3624_p3;
cics_ip_sums_sum_V_11 <= select_ln566_11_fu_3631_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_7_fu_3638_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_12 <= select_ln566_12_fu_3643_p3;
cics_ip_sums_sum_V_13 <= select_ln566_13_fu_3650_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_8_fu_3657_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_14 <= select_ln566_14_fu_3662_p3;
cics_ip_sums_sum_V_15 <= select_ln566_15_fu_3669_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_9_fu_3676_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_16 <= select_ln566_16_fu_3681_p3;
cics_ip_sums_sum_V_17 <= select_ln566_17_fu_3688_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_10_fu_3695_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_18 <= select_ln566_18_fu_3700_p3;
cics_ip_sums_sum_V_19 <= select_ln566_19_fu_3707_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_2_fu_3543_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_2 <= select_ln566_2_fu_3548_p3;
cics_ip_sums_sum_V_3 <= select_ln566_3_fu_3555_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_11_fu_3714_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_20 <= select_ln566_20_fu_3719_p3;
cics_ip_sums_sum_V_21 <= select_ln566_21_fu_3726_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_12_fu_3733_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_22 <= select_ln566_22_fu_3738_p3;
cics_ip_sums_sum_V_23 <= select_ln566_23_fu_3745_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_13_fu_3752_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_24 <= select_ln566_24_fu_3757_p3;
cics_ip_sums_sum_V_25 <= select_ln566_25_fu_3764_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_14_fu_3771_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_26 <= select_ln566_26_fu_3776_p3;
cics_ip_sums_sum_V_27 <= select_ln566_27_fu_3783_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_15_fu_3790_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_28 <= select_ln566_28_fu_3795_p3;
cics_ip_sums_sum_V_29 <= select_ln566_29_fu_3802_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_3_fu_3562_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_4 <= select_ln566_4_fu_3567_p3;
cics_ip_sums_sum_V_5 <= select_ln566_5_fu_3574_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_4_fu_3581_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_6 <= select_ln566_6_fu_3586_p3;
cics_ip_sums_sum_V_7 <= select_ln566_7_fu_3593_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_ln566_5_fu_3600_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
cics_ip_sums_sum_V_8 <= select_ln566_8_fu_3605_p3;
cics_ip_sums_sum_V_9 <= select_ln566_9_fu_3612_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
tmp_reg_3994 <= tmp_nbreadreq_fu_388_p5;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_block_pp0_stage0_subdone, ap_reset_idle_pp0)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
add_ln214_10_fu_2639_p2 <= std_logic_vector(unsigned(zext_ln214_35_fu_2636_p1) + unsigned(trunc_ln700_5_fu_2633_p1));
add_ln214_11_fu_2645_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i14_3_reg_4298) + unsigned(add_ln214_10_fu_2639_p2));
add_ln214_12_fu_2684_p2 <= std_logic_vector(unsigned(zext_ln214_36_fu_2681_p1) + unsigned(trunc_ln700_6_fu_2678_p1));
add_ln214_13_fu_2690_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i2_reg_4308) + unsigned(add_ln214_12_fu_2684_p2));
add_ln214_14_fu_2713_p2 <= std_logic_vector(unsigned(zext_ln214_37_fu_2710_p1) + unsigned(trunc_ln700_7_fu_2707_p1));
add_ln214_15_fu_2719_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i15_1_reg_4318) + unsigned(add_ln214_14_fu_2713_p2));
add_ln214_16_fu_2749_p2 <= std_logic_vector(unsigned(zext_ln214_38_fu_2746_p1) + unsigned(trunc_ln700_8_fu_2743_p1));
add_ln214_17_fu_2755_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i15_2_reg_4328) + unsigned(add_ln214_16_fu_2749_p2));
add_ln214_18_fu_2778_p2 <= std_logic_vector(unsigned(zext_ln214_39_fu_2775_p1) + unsigned(trunc_ln700_9_fu_2772_p1));
add_ln214_19_fu_2784_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i3_reg_4338) + unsigned(add_ln214_18_fu_2778_p2));
add_ln214_1_fu_2470_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i_i_reg_4248) + unsigned(add_ln214_fu_2464_p2));
add_ln214_20_fu_2814_p2 <= std_logic_vector(unsigned(zext_ln214_40_fu_2811_p1) + unsigned(trunc_ln700_10_fu_2808_p1));
add_ln214_21_fu_2820_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i16_1_reg_4348) + unsigned(add_ln214_20_fu_2814_p2));
add_ln214_22_fu_2843_p2 <= std_logic_vector(unsigned(zext_ln214_41_fu_2840_p1) + unsigned(trunc_ln700_11_fu_2837_p1));
add_ln214_23_fu_2849_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i16_2_reg_4358) + unsigned(add_ln214_22_fu_2843_p2));
add_ln214_24_fu_2879_p2 <= std_logic_vector(unsigned(zext_ln214_42_fu_2876_p1) + unsigned(trunc_ln700_12_fu_2873_p1));
add_ln214_25_fu_2885_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i4_reg_4368) + unsigned(add_ln214_24_fu_2879_p2));
add_ln214_26_fu_2908_p2 <= std_logic_vector(unsigned(zext_ln214_43_fu_2905_p1) + unsigned(trunc_ln700_13_fu_2902_p1));
add_ln214_27_fu_2914_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i17_1_reg_4378) + unsigned(add_ln214_26_fu_2908_p2));
add_ln214_28_fu_2945_p2 <= std_logic_vector(unsigned(zext_ln214_44_fu_2942_p1) + unsigned(trunc_ln700_14_fu_2939_p1));
add_ln214_29_fu_2951_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i17_2_reg_4388) + unsigned(add_ln214_28_fu_2945_p2));
add_ln214_2_fu_2500_p2 <= std_logic_vector(unsigned(zext_ln214_31_fu_2497_p1) + unsigned(trunc_ln700_1_fu_2494_p1));
add_ln214_30_fu_2974_p2 <= std_logic_vector(unsigned(zext_ln214_45_fu_2971_p1) + unsigned(trunc_ln700_15_fu_2968_p1));
add_ln214_31_fu_2980_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i17_3_reg_4398) + unsigned(add_ln214_30_fu_2974_p2));
add_ln214_32_fu_3010_p2 <= std_logic_vector(unsigned(zext_ln214_46_fu_3007_p1) + unsigned(trunc_ln700_16_fu_3004_p1));
add_ln214_33_fu_3016_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i5_reg_4408) + unsigned(add_ln214_32_fu_3010_p2));
add_ln214_34_fu_3039_p2 <= std_logic_vector(unsigned(zext_ln214_47_fu_3036_p1) + unsigned(trunc_ln700_17_fu_3033_p1));
add_ln214_35_fu_3045_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i18_1_reg_4418) + unsigned(add_ln214_34_fu_3039_p2));
add_ln214_36_fu_3075_p2 <= std_logic_vector(unsigned(zext_ln214_48_fu_3072_p1) + unsigned(trunc_ln700_18_fu_3069_p1));
add_ln214_37_fu_3081_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i18_2_reg_4428) + unsigned(add_ln214_36_fu_3075_p2));
add_ln214_38_fu_3104_p2 <= std_logic_vector(unsigned(zext_ln214_49_fu_3101_p1) + unsigned(trunc_ln700_19_fu_3098_p1));
add_ln214_39_fu_3110_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i6_reg_4438) + unsigned(add_ln214_38_fu_3104_p2));
add_ln214_3_fu_2506_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i_reg_4258) + unsigned(add_ln214_2_fu_2500_p2));
add_ln214_40_fu_3140_p2 <= std_logic_vector(unsigned(zext_ln214_50_fu_3137_p1) + unsigned(trunc_ln700_20_fu_3134_p1));
add_ln214_41_fu_3146_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i19_1_reg_4448) + unsigned(add_ln214_40_fu_3140_p2));
add_ln214_42_fu_3169_p2 <= std_logic_vector(unsigned(zext_ln214_51_fu_3166_p1) + unsigned(trunc_ln700_21_fu_3163_p1));
add_ln214_43_fu_3175_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i19_2_reg_4458) + unsigned(add_ln214_42_fu_3169_p2));
add_ln214_44_fu_3205_p2 <= std_logic_vector(unsigned(zext_ln214_52_fu_3202_p1) + unsigned(trunc_ln700_22_fu_3199_p1));
add_ln214_45_fu_3211_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i7_reg_4468) + unsigned(add_ln214_44_fu_3205_p2));
add_ln214_46_fu_3234_p2 <= std_logic_vector(unsigned(zext_ln214_53_fu_3231_p1) + unsigned(trunc_ln700_23_fu_3228_p1));
add_ln214_47_fu_3240_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i20_1_reg_4478) + unsigned(add_ln214_46_fu_3234_p2));
add_ln214_48_fu_3270_p2 <= std_logic_vector(unsigned(zext_ln214_54_fu_3267_p1) + unsigned(trunc_ln700_24_fu_3264_p1));
add_ln214_49_fu_3276_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i20_2_reg_4488) + unsigned(add_ln214_48_fu_3270_p2));
add_ln214_4_fu_2545_p2 <= std_logic_vector(unsigned(zext_ln214_32_fu_2542_p1) + unsigned(trunc_ln700_2_fu_2539_p1));
add_ln214_50_fu_3299_p2 <= std_logic_vector(unsigned(zext_ln214_55_fu_3296_p1) + unsigned(trunc_ln700_25_fu_3293_p1));
add_ln214_51_fu_3305_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i20_3_reg_4498) + unsigned(add_ln214_50_fu_3299_p2));
add_ln214_52_fu_3335_p2 <= std_logic_vector(unsigned(zext_ln214_56_fu_3332_p1) + unsigned(trunc_ln700_26_fu_3329_p1));
add_ln214_53_fu_3341_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i8_reg_4508) + unsigned(add_ln214_52_fu_3335_p2));
add_ln214_54_fu_3364_p2 <= std_logic_vector(unsigned(zext_ln214_57_fu_3361_p1) + unsigned(trunc_ln700_27_fu_3358_p1));
add_ln214_55_fu_3370_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i21_1_reg_4518) + unsigned(add_ln214_54_fu_3364_p2));
add_ln214_56_fu_3400_p2 <= std_logic_vector(unsigned(zext_ln214_58_fu_3397_p1) + unsigned(trunc_ln700_28_fu_3394_p1));
add_ln214_57_fu_3406_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i21_2_reg_4528) + unsigned(add_ln214_56_fu_3400_p2));
add_ln214_58_fu_3429_p2 <= std_logic_vector(unsigned(zext_ln214_59_fu_3426_p1) + unsigned(trunc_ln700_29_fu_3423_p1));
add_ln214_59_fu_3435_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i9_reg_4538) + unsigned(add_ln214_58_fu_3429_p2));
add_ln214_5_fu_2551_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i1_reg_4268) + unsigned(add_ln214_4_fu_2545_p2));
add_ln214_6_fu_2574_p2 <= std_logic_vector(unsigned(zext_ln214_33_fu_2571_p1) + unsigned(trunc_ln700_3_fu_2568_p1));
add_ln214_7_fu_2580_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i14_1_reg_4278) + unsigned(add_ln214_6_fu_2574_p2));
add_ln214_8_fu_2610_p2 <= std_logic_vector(unsigned(zext_ln214_34_fu_2607_p1) + unsigned(trunc_ln700_4_fu_2604_p1));
add_ln214_9_fu_2616_p2 <= std_logic_vector(unsigned(agg_result_V_0_1_i14_2_reg_4288) + unsigned(add_ln214_8_fu_2610_p2));
add_ln214_fu_2464_p2 <= std_logic_vector(unsigned(zext_ln214_30_fu_2461_p1) + unsigned(trunc_ln700_fu_2458_p1));
add_ln700_10_fu_1553_p2 <= std_logic_vector(unsigned(zext_ln700_10_fu_1549_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_2));
add_ln700_11_fu_1599_p2 <= std_logic_vector(unsigned(zext_ln700_11_fu_1595_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_3));
add_ln700_12_fu_1645_p2 <= std_logic_vector(unsigned(zext_ln700_12_fu_1641_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_4));
add_ln700_13_fu_1691_p2 <= std_logic_vector(unsigned(zext_ln700_13_fu_1687_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_5));
add_ln700_14_fu_1737_p2 <= std_logic_vector(unsigned(zext_ln700_14_fu_1733_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_6));
add_ln700_15_fu_1783_p2 <= std_logic_vector(unsigned(zext_ln700_15_fu_1779_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_7));
add_ln700_16_fu_1829_p2 <= std_logic_vector(unsigned(zext_ln700_16_fu_1825_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_8));
add_ln700_17_fu_1875_p2 <= std_logic_vector(unsigned(zext_ln700_17_fu_1871_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_9));
add_ln700_18_fu_1921_p2 <= std_logic_vector(unsigned(zext_ln700_18_fu_1917_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_10));
add_ln700_19_fu_1967_p2 <= std_logic_vector(unsigned(zext_ln700_19_fu_1963_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_11));
add_ln700_1_fu_1139_p2 <= std_logic_vector(unsigned(zext_ln700_1_fu_1135_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_1_1));
add_ln700_20_fu_2013_p2 <= std_logic_vector(unsigned(zext_ln700_20_fu_2009_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_2));
add_ln700_21_fu_2059_p2 <= std_logic_vector(unsigned(zext_ln700_21_fu_2055_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_3));
add_ln700_22_fu_2105_p2 <= std_logic_vector(unsigned(zext_ln700_22_fu_2101_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_4));
add_ln700_23_fu_2151_p2 <= std_logic_vector(unsigned(zext_ln700_23_fu_2147_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_5));
add_ln700_24_fu_2197_p2 <= std_logic_vector(unsigned(zext_ln700_24_fu_2193_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_6));
add_ln700_25_fu_2243_p2 <= std_logic_vector(unsigned(zext_ln700_25_fu_2239_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_7));
add_ln700_26_fu_2289_p2 <= std_logic_vector(unsigned(zext_ln700_26_fu_2285_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_8));
add_ln700_27_fu_2335_p2 <= std_logic_vector(unsigned(zext_ln700_27_fu_2331_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_9));
add_ln700_28_fu_2381_p2 <= std_logic_vector(unsigned(zext_ln700_28_fu_2377_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_10));
add_ln700_29_fu_2427_p2 <= std_logic_vector(unsigned(zext_ln700_29_fu_2423_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_11));
add_ln700_2_fu_1185_p2 <= std_logic_vector(unsigned(zext_ln700_2_fu_1181_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_2_1));
add_ln700_3_fu_1231_p2 <= std_logic_vector(unsigned(zext_ln700_3_fu_1227_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_3_1));
add_ln700_4_fu_1277_p2 <= std_logic_vector(unsigned(zext_ln700_4_fu_1273_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_4_1));
add_ln700_5_fu_1323_p2 <= std_logic_vector(unsigned(zext_ln700_5_fu_1319_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_5_1));
add_ln700_6_fu_1369_p2 <= std_logic_vector(unsigned(zext_ln700_6_fu_1365_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_6_1));
add_ln700_7_fu_1415_p2 <= std_logic_vector(unsigned(zext_ln700_7_fu_1411_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_7_1));
add_ln700_8_fu_1461_p2 <= std_logic_vector(unsigned(zext_ln700_8_fu_1457_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_8_1));
add_ln700_9_fu_1507_p2 <= std_logic_vector(unsigned(zext_ln700_9_fu_1503_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_9_1));
add_ln700_fu_1093_p2 <= std_logic_vector(unsigned(zext_ln700_fu_1089_p1) + unsigned(ap_sig_allocacmp_cics_ip_sums_sum_V_0_1));
agg_result_V_0_1_i14_1_fu_1219_p3 <= (p_Result_2_1_i142_s_fu_1209_p4 & p_Result_2_i141_i_fu_1199_p4);
agg_result_V_0_1_i14_2_fu_1265_p3 <= (p_Result_2_1_i145_s_fu_1255_p4 & p_Result_2_i144_i_fu_1245_p4);
agg_result_V_0_1_i14_3_fu_1311_p3 <= (p_Result_2_1_i148_s_fu_1301_p4 & p_Result_2_i147_i_fu_1291_p4);
agg_result_V_0_1_i15_1_fu_1403_p3 <= (p_Result_2_1_i154_s_fu_1393_p4 & p_Result_2_i153_i_fu_1383_p4);
agg_result_V_0_1_i15_2_fu_1449_p3 <= (p_Result_2_1_i157_s_fu_1439_p4 & p_Result_2_i156_i_fu_1429_p4);
agg_result_V_0_1_i16_1_fu_1541_p3 <= (p_Result_2_1_i163_s_fu_1531_p4 & p_Result_2_i162_i_fu_1521_p4);
agg_result_V_0_1_i16_2_fu_1587_p3 <= (p_Result_2_1_i166_s_fu_1577_p4 & p_Result_2_i165_i_fu_1567_p4);
agg_result_V_0_1_i17_1_fu_1679_p3 <= (p_Result_2_1_i172_s_fu_1669_p4 & p_Result_2_i171_i_fu_1659_p4);
agg_result_V_0_1_i17_2_fu_1725_p3 <= (p_Result_2_1_i175_s_fu_1715_p4 & p_Result_2_i174_i_fu_1705_p4);
agg_result_V_0_1_i17_3_fu_1771_p3 <= (p_Result_2_1_i178_s_fu_1761_p4 & p_Result_2_i177_i_fu_1751_p4);
agg_result_V_0_1_i18_1_fu_1863_p3 <= (p_Result_2_1_i184_s_fu_1853_p4 & p_Result_2_i183_i_fu_1843_p4);
agg_result_V_0_1_i18_2_fu_1909_p3 <= (p_Result_2_1_i187_s_fu_1899_p4 & p_Result_2_i186_i_fu_1889_p4);
agg_result_V_0_1_i19_1_fu_2001_p3 <= (p_Result_2_1_i193_s_fu_1991_p4 & p_Result_2_i192_i_fu_1981_p4);
agg_result_V_0_1_i19_2_fu_2047_p3 <= (p_Result_2_1_i196_s_fu_2037_p4 & p_Result_2_i195_i_fu_2027_p4);
agg_result_V_0_1_i1_fu_1173_p3 <= (p_Result_2_1_i139_s_fu_1163_p4 & p_Result_2_i138_i_fu_1153_p4);
agg_result_V_0_1_i20_1_fu_2139_p3 <= (p_Result_2_1_i202_s_fu_2129_p4 & p_Result_2_i201_i_fu_2119_p4);
agg_result_V_0_1_i20_2_fu_2185_p3 <= (p_Result_2_1_i205_s_fu_2175_p4 & p_Result_2_i204_i_fu_2165_p4);
agg_result_V_0_1_i20_3_fu_2231_p3 <= (p_Result_2_1_i208_s_fu_2221_p4 & p_Result_2_i207_i_fu_2211_p4);
agg_result_V_0_1_i21_1_fu_2323_p3 <= (p_Result_2_1_i214_s_fu_2313_p4 & p_Result_2_i213_i_fu_2303_p4);
agg_result_V_0_1_i21_2_fu_2369_p3 <= (p_Result_2_1_i217_s_fu_2359_p4 & p_Result_2_i216_i_fu_2349_p4);
agg_result_V_0_1_i2_fu_1357_p3 <= (p_Result_2_1_i151_s_fu_1347_p4 & p_Result_2_i150_i_fu_1337_p4);
agg_result_V_0_1_i3_fu_1495_p3 <= (p_Result_2_1_i160_s_fu_1485_p4 & p_Result_2_i159_i_fu_1475_p4);
agg_result_V_0_1_i4_fu_1633_p3 <= (p_Result_2_1_i169_s_fu_1623_p4 & p_Result_2_i168_i_fu_1613_p4);
agg_result_V_0_1_i5_fu_1817_p3 <= (p_Result_2_1_i181_s_fu_1807_p4 & p_Result_2_i180_i_fu_1797_p4);
agg_result_V_0_1_i6_fu_1955_p3 <= (p_Result_2_1_i190_s_fu_1945_p4 & p_Result_2_i189_i_fu_1935_p4);
agg_result_V_0_1_i7_fu_2093_p3 <= (p_Result_2_1_i199_s_fu_2083_p4 & p_Result_2_i198_i_fu_2073_p4);
agg_result_V_0_1_i8_fu_2277_p3 <= (p_Result_2_1_i211_s_fu_2267_p4 & p_Result_2_i210_i_fu_2257_p4);
agg_result_V_0_1_i9_fu_2415_p3 <= (p_Result_2_1_i220_s_fu_2405_p4 & p_Result_2_i219_i_fu_2395_p4);
agg_result_V_0_1_i_fu_1127_p3 <= (p_Result_2_1_i136_s_fu_1117_p4 & p_Result_2_i135_i_fu_1107_p4);
agg_result_V_0_1_i_i_fu_1081_p3 <= (trunc_ln647_3_fu_1077_p1 & p_Result_2_i_i_fu_1067_p4);
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(ap_start, ap_done_reg, ap_enable_reg_pp0_iter1, io_acc_block_signal_op5, tmp_nbreadreq_fu_388_p5, ipDataCheckFifo_V_full_n, tmp_reg_3994, iph_subSumsFifoOut_V_full_n, ap_predicate_op429_write_state2)
begin
ap_block_pp0_stage0_01001 <= ((ap_done_reg = ap_const_logic_1) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((iph_subSumsFifoOut_V_full_n = ap_const_logic_0) and (ap_predicate_op429_write_state2 = ap_const_boolean_1)) or ((tmp_reg_3994 = ap_const_lv1_1) and (ipDataCheckFifo_V_full_n = ap_const_logic_0)))) or ((ap_start = ap_const_logic_1) and ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1) or ((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (io_acc_block_signal_op5 = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(ap_start, ap_done_reg, ap_enable_reg_pp0_iter1, io_acc_block_signal_op5, tmp_nbreadreq_fu_388_p5, ipDataCheckFifo_V_full_n, tmp_reg_3994, iph_subSumsFifoOut_V_full_n, ap_predicate_op429_write_state2)
begin
ap_block_pp0_stage0_11001 <= ((ap_done_reg = ap_const_logic_1) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((iph_subSumsFifoOut_V_full_n = ap_const_logic_0) and (ap_predicate_op429_write_state2 = ap_const_boolean_1)) or ((tmp_reg_3994 = ap_const_lv1_1) and (ipDataCheckFifo_V_full_n = ap_const_logic_0)))) or ((ap_start = ap_const_logic_1) and ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1) or ((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (io_acc_block_signal_op5 = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(ap_start, ap_done_reg, ap_enable_reg_pp0_iter1, io_acc_block_signal_op5, tmp_nbreadreq_fu_388_p5, ipDataCheckFifo_V_full_n, tmp_reg_3994, iph_subSumsFifoOut_V_full_n, ap_predicate_op429_write_state2)
begin
ap_block_pp0_stage0_subdone <= ((ap_done_reg = ap_const_logic_1) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((iph_subSumsFifoOut_V_full_n = ap_const_logic_0) and (ap_predicate_op429_write_state2 = ap_const_boolean_1)) or ((tmp_reg_3994 = ap_const_lv1_1) and (ipDataCheckFifo_V_full_n = ap_const_logic_0)))) or ((ap_start = ap_const_logic_1) and ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1) or ((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (io_acc_block_signal_op5 = ap_const_logic_0)))));
end process;
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start, ap_done_reg, io_acc_block_signal_op5, tmp_nbreadreq_fu_388_p5)
begin
ap_block_state1_pp0_stage0_iter0 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1) or ((tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (io_acc_block_signal_op5 = ap_const_logic_0)));
end process;
ap_block_state2_pp0_stage0_iter1_assign_proc : process(ipDataCheckFifo_V_full_n, tmp_reg_3994, iph_subSumsFifoOut_V_full_n, ap_predicate_op429_write_state2)
begin
ap_block_state2_pp0_stage0_iter1 <= (((iph_subSumsFifoOut_V_full_n = ap_const_logic_0) and (ap_predicate_op429_write_state2 = ap_const_boolean_1)) or ((tmp_reg_3994 = ap_const_lv1_1) and (ipDataCheckFifo_V_full_n = ap_const_logic_0)));
end process;
ap_condition_86_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
ap_condition_86 <= ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0 <= ap_start;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_start = ap_const_logic_0) and (ap_idle_pp0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to0_assign_proc : process(ap_enable_reg_pp0_iter0)
begin
if ((ap_enable_reg_pp0_iter0 = ap_const_logic_0)) then
ap_idle_pp0_0to0 <= ap_const_logic_1;
else
ap_idle_pp0_0to0 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_cics_firstWord_flag_s_phi_fu_428_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, ap_phi_reg_pp0_iter1_cics_firstWord_flag_s_reg_424)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_firstWord_flag_s_phi_fu_428_p4 <= ap_const_lv1_1;
else
ap_phi_mux_cics_firstWord_flag_s_phi_fu_428_p4 <= ap_phi_reg_pp0_iter1_cics_firstWord_flag_s_reg_424;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_0_2_phi_fu_440_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, xor_ln887_fu_2479_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_2_reg_436)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_0_2_phi_fu_440_p4 <= xor_ln887_fu_2479_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_0_2_phi_fu_440_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_2_reg_436;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_0_3_phi_fu_451_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_fu_2486_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_3_reg_447)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_0_3_phi_fu_451_p4 <= select_ln887_fu_2486_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_0_3_phi_fu_451_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_3_reg_447;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_12_phi_fu_462_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_1_fu_2515_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_12_reg_458)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_12_phi_fu_462_p4 <= select_ln887_1_fu_2515_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_12_phi_fu_462_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_12_reg_458;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_13_phi_fu_605_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_5_fu_2801_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_13_reg_601)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_13_phi_fu_605_p4 <= icmp_ln887_5_fu_2801_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_1_13_phi_fu_605_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_13_reg_601;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_14_phi_fu_616_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_10_fu_2829_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_14_reg_612)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_14_phi_fu_616_p4 <= select_ln887_10_fu_2829_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_14_phi_fu_616_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_14_reg_612;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_15_phi_fu_627_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_11_fu_2858_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_15_reg_623)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_15_phi_fu_627_p4 <= select_ln887_11_fu_2858_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_15_phi_fu_627_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_15_reg_623;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_16_phi_fu_638_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_6_fu_2866_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_16_reg_634)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_16_phi_fu_638_p4 <= icmp_ln887_6_fu_2866_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_1_16_phi_fu_638_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_16_reg_634;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_17_phi_fu_649_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_12_fu_2894_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_17_reg_645)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_17_phi_fu_649_p4 <= select_ln887_12_fu_2894_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_17_phi_fu_649_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_17_reg_645;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_18_phi_fu_660_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_13_fu_2923_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_18_reg_656)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_18_phi_fu_660_p4 <= select_ln887_13_fu_2923_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_18_phi_fu_660_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_18_reg_656;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_19_phi_fu_671_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, tmp_data_V_reg_3998, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_19_reg_667)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_19_phi_fu_671_p4 <= tmp_data_V_reg_3998(3 downto 3);
else
ap_phi_mux_cics_ip_sums_sum_V_1_19_phi_fu_671_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_19_reg_667;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_20_phi_fu_682_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_14_fu_2960_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_20_reg_678)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_20_phi_fu_682_p4 <= select_ln887_14_fu_2960_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_20_phi_fu_682_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_20_reg_678;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_21_phi_fu_693_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_15_fu_2989_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_21_reg_689)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_21_phi_fu_693_p4 <= select_ln887_15_fu_2989_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_21_phi_fu_693_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_21_reg_689;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_22_phi_fu_704_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_7_fu_2997_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_22_reg_700)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_22_phi_fu_704_p4 <= icmp_ln887_7_fu_2997_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_1_22_phi_fu_704_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_22_reg_700;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_23_phi_fu_715_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_16_fu_3025_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_23_reg_711)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_23_phi_fu_715_p4 <= select_ln887_16_fu_3025_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_23_phi_fu_715_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_23_reg_711;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_24_phi_fu_726_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_17_fu_3054_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_24_reg_722)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_24_phi_fu_726_p4 <= select_ln887_17_fu_3054_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_24_phi_fu_726_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_24_reg_722;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_25_phi_fu_737_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_8_fu_3062_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_25_reg_733)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_25_phi_fu_737_p4 <= icmp_ln887_8_fu_3062_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_1_25_phi_fu_737_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_25_reg_733;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_26_phi_fu_748_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_18_fu_3090_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_26_reg_744)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_26_phi_fu_748_p4 <= select_ln887_18_fu_3090_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_26_phi_fu_748_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_26_reg_744;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_1_27_phi_fu_759_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_19_fu_3119_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_27_reg_755)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_1_27_phi_fu_759_p4 <= select_ln887_19_fu_3119_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_1_27_phi_fu_759_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_27_reg_755;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_12_phi_fu_473_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_1_fu_2532_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_12_reg_469)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_12_phi_fu_473_p4 <= icmp_ln887_1_fu_2532_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_2_12_phi_fu_473_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_12_reg_469;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_13_phi_fu_484_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_2_fu_2560_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_13_reg_480)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_13_phi_fu_484_p4 <= select_ln887_2_fu_2560_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_13_phi_fu_484_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_13_reg_480;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_14_phi_fu_770_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_9_fu_3127_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_14_reg_766)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_14_phi_fu_770_p4 <= icmp_ln887_9_fu_3127_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_2_14_phi_fu_770_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_14_reg_766;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_15_phi_fu_781_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_20_fu_3155_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_15_reg_777)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_15_phi_fu_781_p4 <= select_ln887_20_fu_3155_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_15_phi_fu_781_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_15_reg_777;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_16_phi_fu_792_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_21_fu_3184_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_16_reg_788)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_16_phi_fu_792_p4 <= select_ln887_21_fu_3184_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_16_phi_fu_792_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_16_reg_788;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_17_phi_fu_803_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_10_fu_3192_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_17_reg_799)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_17_phi_fu_803_p4 <= icmp_ln887_10_fu_3192_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_2_17_phi_fu_803_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_17_reg_799;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_18_phi_fu_814_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_22_fu_3220_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_18_reg_810)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_18_phi_fu_814_p4 <= select_ln887_22_fu_3220_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_18_phi_fu_814_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_18_reg_810;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_19_phi_fu_825_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_23_fu_3249_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_19_reg_821)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_19_phi_fu_825_p4 <= select_ln887_23_fu_3249_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_19_phi_fu_825_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_19_reg_821;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_20_phi_fu_836_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_11_fu_3257_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_20_reg_832)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_20_phi_fu_836_p4 <= icmp_ln887_11_fu_3257_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_2_20_phi_fu_836_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_20_reg_832;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_21_phi_fu_847_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_24_fu_3285_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_21_reg_843)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_21_phi_fu_847_p4 <= select_ln887_24_fu_3285_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_21_phi_fu_847_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_21_reg_843;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_22_phi_fu_858_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_25_fu_3314_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_22_reg_854)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_22_phi_fu_858_p4 <= select_ln887_25_fu_3314_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_22_phi_fu_858_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_22_reg_854;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_23_phi_fu_869_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_12_fu_3322_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_23_reg_865)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_23_phi_fu_869_p4 <= icmp_ln887_12_fu_3322_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_2_23_phi_fu_869_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_23_reg_865;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_24_phi_fu_880_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_26_fu_3350_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_24_reg_876)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_24_phi_fu_880_p4 <= select_ln887_26_fu_3350_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_24_phi_fu_880_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_24_reg_876;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_25_phi_fu_891_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_27_fu_3379_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_25_reg_887)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_25_phi_fu_891_p4 <= select_ln887_27_fu_3379_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_25_phi_fu_891_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_25_reg_887;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_26_phi_fu_902_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_13_fu_3387_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_26_reg_898)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_26_phi_fu_902_p4 <= icmp_ln887_13_fu_3387_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_2_26_phi_fu_902_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_26_reg_898;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_27_phi_fu_913_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_28_fu_3415_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_27_reg_909)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_27_phi_fu_913_p4 <= select_ln887_28_fu_3415_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_27_phi_fu_913_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_27_reg_909;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_2_28_phi_fu_924_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_29_fu_3444_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_28_reg_920)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_2_28_phi_fu_924_p4 <= select_ln887_29_fu_3444_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_2_28_phi_fu_924_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_28_reg_920;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_3_2_phi_fu_495_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_3_fu_2589_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_3_2_reg_491)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_3_2_phi_fu_495_p4 <= select_ln887_3_fu_2589_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_3_2_phi_fu_495_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_3_2_reg_491;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_4_2_phi_fu_506_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_2_fu_2597_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_2_reg_502)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_4_2_phi_fu_506_p4 <= icmp_ln887_2_fu_2597_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_4_2_phi_fu_506_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_2_reg_502;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_4_3_phi_fu_517_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_4_fu_2625_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_3_reg_513)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_4_3_phi_fu_517_p4 <= select_ln887_4_fu_2625_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_4_3_phi_fu_517_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_3_reg_513;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_5_2_phi_fu_528_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_5_fu_2654_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_5_2_reg_524)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_5_2_phi_fu_528_p4 <= select_ln887_5_fu_2654_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_5_2_phi_fu_528_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_5_2_reg_524;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_6_2_phi_fu_539_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_3_fu_2671_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_2_reg_535)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_6_2_phi_fu_539_p4 <= icmp_ln887_3_fu_2671_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_6_2_phi_fu_539_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_2_reg_535;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_6_3_phi_fu_550_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_6_fu_2699_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_3_reg_546)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_6_3_phi_fu_550_p4 <= select_ln887_6_fu_2699_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_6_3_phi_fu_550_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_3_reg_546;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_7_2_phi_fu_561_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_7_fu_2728_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_7_2_reg_557)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_7_2_phi_fu_561_p4 <= select_ln887_7_fu_2728_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_7_2_phi_fu_561_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_7_2_reg_557;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_8_2_phi_fu_572_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, icmp_ln887_4_fu_2736_p2, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_2_reg_568)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_8_2_phi_fu_572_p4 <= icmp_ln887_4_fu_2736_p2;
else
ap_phi_mux_cics_ip_sums_sum_V_8_2_phi_fu_572_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_2_reg_568;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_8_3_phi_fu_583_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_8_fu_2764_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_3_reg_579)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_8_3_phi_fu_583_p4 <= select_ln887_8_fu_2764_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_8_3_phi_fu_583_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_3_reg_579;
end if;
end process;
ap_phi_mux_cics_ip_sums_sum_V_9_2_phi_fu_594_p4_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064, select_ln887_9_fu_2793_p3, ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_9_2_reg_590)
begin
if (((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1))) then
ap_phi_mux_cics_ip_sums_sum_V_9_2_phi_fu_594_p4 <= select_ln887_9_fu_2793_p3;
else
ap_phi_mux_cics_ip_sums_sum_V_9_2_phi_fu_594_p4 <= ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_9_2_reg_590;
end if;
end process;
ap_phi_reg_pp0_iter0_cics_firstWord_flag_s_reg_424 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_0_2_reg_436 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_13_reg_601 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_16_reg_634 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_19_reg_667 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_22_reg_700 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_1_25_reg_733 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_12_reg_469 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_14_reg_766 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_17_reg_799 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_20_reg_832 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_23_reg_865 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_2_26_reg_898 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_4_2_reg_502 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_6_2_reg_535 <= "X";
ap_phi_reg_pp0_iter0_cics_ip_sums_sum_V_8_2_reg_568 <= "X";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_0_3_reg_447 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_12_reg_458 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_14_reg_612 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_15_reg_623 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_17_reg_645 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_18_reg_656 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_20_reg_678 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_21_reg_689 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_23_reg_711 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_24_reg_722 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_26_reg_744 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_1_27_reg_755 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_13_reg_480 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_15_reg_777 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_16_reg_788 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_18_reg_810 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_19_reg_821 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_21_reg_843 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_22_reg_854 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_24_reg_876 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_25_reg_887 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_27_reg_909 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_2_28_reg_920 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_3_2_reg_491 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_4_3_reg_513 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_5_2_reg_524 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_6_3_reg_546 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_7_2_reg_557 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_8_3_reg_579 <= "XXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter1_cics_ip_sums_sum_V_9_2_reg_590 <= "XXXXXXXXXXXXXXXXX";
ap_predicate_op429_write_state2_assign_proc : process(tmp_reg_3994, cics_firstWord_load_reg_4064)
begin
ap_predicate_op429_write_state2 <= ((cics_firstWord_load_reg_4064 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1));
end process;
ap_ready_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to0)
begin
if (((ap_start = ap_const_logic_0) and (ap_idle_pp0_0to0 = ap_const_logic_1))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_sig_allocacmp_cics_firstWord_load_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_firstWord, ap_block_pp0_stage0, tmp_last_V_reg_4012, or_ln566_fu_3519_p2)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_fu_3519_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_firstWord_load <= tmp_last_V_reg_4012;
else
ap_sig_allocacmp_cics_firstWord_load <= cics_firstWord;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_0_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_0, ap_block_pp0_stage0, select_ln566_fu_3529_p3, or_ln566_1_fu_3524_p2)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_1_fu_3524_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_0_1 <= select_ln566_fu_3529_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_0_1 <= cics_ip_sums_sum_V_0;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_1, ap_block_pp0_stage0, or_ln566_1_fu_3524_p2, select_ln566_1_fu_3536_p3)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_1_fu_3524_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_1 <= select_ln566_1_fu_3536_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_1 <= cics_ip_sums_sum_V_1;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_10_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_18, ap_block_pp0_stage0, select_ln566_18_fu_3700_p3, or_ln566_10_fu_3695_p2)
begin
if (((or_ln566_10_fu_3695_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_10 <= select_ln566_18_fu_3700_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_10 <= cics_ip_sums_sum_V_18;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_11_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_19, ap_block_pp0_stage0, or_ln566_10_fu_3695_p2, select_ln566_19_fu_3707_p3)
begin
if (((or_ln566_10_fu_3695_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_11 <= select_ln566_19_fu_3707_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_11 <= cics_ip_sums_sum_V_19;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_2_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_10, ap_block_pp0_stage0, select_ln566_10_fu_3624_p3, or_ln566_6_fu_3619_p2)
begin
if (((or_ln566_6_fu_3619_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_2 <= select_ln566_10_fu_3624_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_2 <= cics_ip_sums_sum_V_10;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_3_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_11, ap_block_pp0_stage0, or_ln566_6_fu_3619_p2, select_ln566_11_fu_3631_p3)
begin
if (((or_ln566_6_fu_3619_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_3 <= select_ln566_11_fu_3631_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_3 <= cics_ip_sums_sum_V_11;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_4_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_12, ap_block_pp0_stage0, select_ln566_12_fu_3643_p3, or_ln566_7_fu_3638_p2)
begin
if (((or_ln566_7_fu_3638_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_4 <= select_ln566_12_fu_3643_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_4 <= cics_ip_sums_sum_V_12;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_5_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_13, ap_block_pp0_stage0, or_ln566_7_fu_3638_p2, select_ln566_13_fu_3650_p3)
begin
if (((or_ln566_7_fu_3638_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_5 <= select_ln566_13_fu_3650_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_5 <= cics_ip_sums_sum_V_13;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_6_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_14, ap_block_pp0_stage0, select_ln566_14_fu_3662_p3, or_ln566_8_fu_3657_p2)
begin
if (((or_ln566_8_fu_3657_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_6 <= select_ln566_14_fu_3662_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_6 <= cics_ip_sums_sum_V_14;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_7_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_15, ap_block_pp0_stage0, or_ln566_8_fu_3657_p2, select_ln566_15_fu_3669_p3)
begin
if (((or_ln566_8_fu_3657_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_7 <= select_ln566_15_fu_3669_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_7 <= cics_ip_sums_sum_V_15;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_8_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_16, ap_block_pp0_stage0, select_ln566_16_fu_3681_p3, or_ln566_9_fu_3676_p2)
begin
if (((or_ln566_9_fu_3676_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_8 <= select_ln566_16_fu_3681_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_8 <= cics_ip_sums_sum_V_16;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_1_9_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_17, ap_block_pp0_stage0, or_ln566_9_fu_3676_p2, select_ln566_17_fu_3688_p3)
begin
if (((or_ln566_9_fu_3676_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_1_9 <= select_ln566_17_fu_3688_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_1_9 <= cics_ip_sums_sum_V_17;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_2, ap_block_pp0_stage0, select_ln566_2_fu_3548_p3, or_ln566_2_fu_3543_p2)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_2_fu_3543_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_1 <= select_ln566_2_fu_3548_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_1 <= cics_ip_sums_sum_V_2;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_10_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_28, ap_block_pp0_stage0, select_ln566_28_fu_3795_p3, or_ln566_15_fu_3790_p2)
begin
if (((or_ln566_15_fu_3790_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_10 <= select_ln566_28_fu_3795_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_10 <= cics_ip_sums_sum_V_28;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_11_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_29, ap_block_pp0_stage0, or_ln566_15_fu_3790_p2, select_ln566_29_fu_3802_p3)
begin
if (((or_ln566_15_fu_3790_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_11 <= select_ln566_29_fu_3802_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_11 <= cics_ip_sums_sum_V_29;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_2_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_20, ap_block_pp0_stage0, select_ln566_20_fu_3719_p3, or_ln566_11_fu_3714_p2)
begin
if (((or_ln566_11_fu_3714_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_2 <= select_ln566_20_fu_3719_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_2 <= cics_ip_sums_sum_V_20;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_3_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_21, ap_block_pp0_stage0, or_ln566_11_fu_3714_p2, select_ln566_21_fu_3726_p3)
begin
if (((or_ln566_11_fu_3714_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_3 <= select_ln566_21_fu_3726_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_3 <= cics_ip_sums_sum_V_21;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_4_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_22, ap_block_pp0_stage0, select_ln566_22_fu_3738_p3, or_ln566_12_fu_3733_p2)
begin
if (((or_ln566_12_fu_3733_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_4 <= select_ln566_22_fu_3738_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_4 <= cics_ip_sums_sum_V_22;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_5_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_23, ap_block_pp0_stage0, or_ln566_12_fu_3733_p2, select_ln566_23_fu_3745_p3)
begin
if (((or_ln566_12_fu_3733_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_5 <= select_ln566_23_fu_3745_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_5 <= cics_ip_sums_sum_V_23;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_6_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_24, ap_block_pp0_stage0, select_ln566_24_fu_3757_p3, or_ln566_13_fu_3752_p2)
begin
if (((or_ln566_13_fu_3752_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_6 <= select_ln566_24_fu_3757_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_6 <= cics_ip_sums_sum_V_24;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_7_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_25, ap_block_pp0_stage0, or_ln566_13_fu_3752_p2, select_ln566_25_fu_3764_p3)
begin
if (((or_ln566_13_fu_3752_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_7 <= select_ln566_25_fu_3764_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_7 <= cics_ip_sums_sum_V_25;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_8_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_26, ap_block_pp0_stage0, select_ln566_26_fu_3776_p3, or_ln566_14_fu_3771_p2)
begin
if (((or_ln566_14_fu_3771_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_8 <= select_ln566_26_fu_3776_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_8 <= cics_ip_sums_sum_V_26;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_2_9_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_27, ap_block_pp0_stage0, or_ln566_14_fu_3771_p2, select_ln566_27_fu_3783_p3)
begin
if (((or_ln566_14_fu_3771_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_2_9 <= select_ln566_27_fu_3783_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_2_9 <= cics_ip_sums_sum_V_27;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_3_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_3, ap_block_pp0_stage0, or_ln566_2_fu_3543_p2, select_ln566_3_fu_3555_p3)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_2_fu_3543_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_3_1 <= select_ln566_3_fu_3555_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_3_1 <= cics_ip_sums_sum_V_3;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_4_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_4, ap_block_pp0_stage0, select_ln566_4_fu_3567_p3, or_ln566_3_fu_3562_p2)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_3_fu_3562_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_4_1 <= select_ln566_4_fu_3567_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_4_1 <= cics_ip_sums_sum_V_4;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_5_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_5, ap_block_pp0_stage0, or_ln566_3_fu_3562_p2, select_ln566_5_fu_3574_p3)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_3_fu_3562_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_5_1 <= select_ln566_5_fu_3574_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_5_1 <= cics_ip_sums_sum_V_5;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_6_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_6, ap_block_pp0_stage0, select_ln566_6_fu_3586_p3, or_ln566_4_fu_3581_p2)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_4_fu_3581_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_6_1 <= select_ln566_6_fu_3586_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_6_1 <= cics_ip_sums_sum_V_6;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_7_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_7, ap_block_pp0_stage0, or_ln566_4_fu_3581_p2, select_ln566_7_fu_3593_p3)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (or_ln566_4_fu_3581_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_7_1 <= select_ln566_7_fu_3593_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_7_1 <= cics_ip_sums_sum_V_7;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_8_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_8, ap_block_pp0_stage0, select_ln566_8_fu_3605_p3, or_ln566_5_fu_3600_p2)
begin
if (((or_ln566_5_fu_3600_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_8_1 <= select_ln566_8_fu_3605_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_8_1 <= cics_ip_sums_sum_V_8;
end if;
end process;
ap_sig_allocacmp_cics_ip_sums_sum_V_9_1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, cics_ip_sums_sum_V_9, ap_block_pp0_stage0, or_ln566_5_fu_3600_p2, select_ln566_9_fu_3612_p3)
begin
if (((or_ln566_5_fu_3600_p2 = ap_const_lv1_1) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_sig_allocacmp_cics_ip_sums_sum_V_9_1 <= select_ln566_9_fu_3612_p3;
else
ap_sig_allocacmp_cics_ip_sums_sum_V_9_1 <= cics_ip_sums_sum_V_9;
end if;
end process;
cics_firstWord_load_load_fu_943_p1 <= ap_sig_allocacmp_cics_firstWord_load;
icmp_ln887_10_fu_3192_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_B)) else "0";
icmp_ln887_11_fu_3257_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_C)) else "0";
icmp_ln887_12_fu_3322_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_D)) else "0";
icmp_ln887_13_fu_3387_p2 <= "1" when (trunc_ln647_fu_2449_p1 = ap_const_lv4_F) else "0";
icmp_ln887_1_fu_2532_p2 <= "0" when (tmp_15_fu_2523_p4 = ap_const_lv3_0) else "1";
icmp_ln887_2_fu_2597_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_2)) else "0";
icmp_ln887_3_fu_2671_p2 <= "0" when (tmp_20_fu_2662_p4 = ap_const_lv2_0) else "1";
icmp_ln887_4_fu_2736_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_4)) else "0";
icmp_ln887_5_fu_2801_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_5)) else "0";
icmp_ln887_6_fu_2866_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_6)) else "0";
icmp_ln887_7_fu_2997_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_8)) else "0";
icmp_ln887_8_fu_3062_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_9)) else "0";
icmp_ln887_9_fu_3127_p2 <= "1" when (unsigned(trunc_ln647_fu_2449_p1) > unsigned(ap_const_lv4_A)) else "0";
icmp_ln887_fu_2452_p2 <= "1" when (trunc_ln647_fu_2449_p1 = ap_const_lv4_0) else "0";
io_acc_block_signal_op5 <= (ipDataMetaFifo_V_las_empty_n and ipDataMetaFifo_V_kee_empty_n and ipDataMetaFifo_V_dat_empty_n);
ipDataCheckFifo_V_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ipDataCheckFifo_V_full_n, tmp_reg_3994, ap_block_pp0_stage0)
begin
if (((tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ipDataCheckFifo_V_blk_n <= ipDataCheckFifo_V_full_n;
else
ipDataCheckFifo_V_blk_n <= ap_const_logic_1;
end if;
end process;
ipDataCheckFifo_V_din <= ((tmp_last_V_reg_4012 & tmp_keep_V_reg_4007) & tmp_data_V_reg_3998);
ipDataCheckFifo_V_write_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_reg_3994, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_reg_3994 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ipDataCheckFifo_V_write <= ap_const_logic_1;
else
ipDataCheckFifo_V_write <= ap_const_logic_0;
end if;
end process;
ipDataMetaFifo_V_dat_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_pp0_stage0, ipDataMetaFifo_V_dat_empty_n, tmp_nbreadreq_fu_388_p5, ap_block_pp0_stage0)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ipDataMetaFifo_V_dat_blk_n <= ipDataMetaFifo_V_dat_empty_n;
else
ipDataMetaFifo_V_dat_blk_n <= ap_const_logic_1;
end if;
end process;
ipDataMetaFifo_V_dat_read_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, tmp_nbreadreq_fu_388_p5, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ipDataMetaFifo_V_dat_read <= ap_const_logic_1;
else
ipDataMetaFifo_V_dat_read <= ap_const_logic_0;
end if;
end process;
ipDataMetaFifo_V_kee_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_pp0_stage0, ipDataMetaFifo_V_kee_empty_n, tmp_nbreadreq_fu_388_p5, ap_block_pp0_stage0)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ipDataMetaFifo_V_kee_blk_n <= ipDataMetaFifo_V_kee_empty_n;
else
ipDataMetaFifo_V_kee_blk_n <= ap_const_logic_1;
end if;
end process;
ipDataMetaFifo_V_kee_read_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, tmp_nbreadreq_fu_388_p5, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ipDataMetaFifo_V_kee_read <= ap_const_logic_1;
else
ipDataMetaFifo_V_kee_read <= ap_const_logic_0;
end if;
end process;
ipDataMetaFifo_V_las_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_pp0_stage0, ipDataMetaFifo_V_las_empty_n, tmp_nbreadreq_fu_388_p5, ap_block_pp0_stage0)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ipDataMetaFifo_V_las_blk_n <= ipDataMetaFifo_V_las_empty_n;
else
ipDataMetaFifo_V_las_blk_n <= ap_const_logic_1;
end if;
end process;
ipDataMetaFifo_V_las_read_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, tmp_nbreadreq_fu_388_p5, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_nbreadreq_fu_388_p5 = ap_const_lv1_1) and (ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ipDataMetaFifo_V_las_read <= ap_const_logic_1;
else
ipDataMetaFifo_V_las_read <= ap_const_logic_0;
end if;
end process;
iph_subSumsFifoOut_V_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, iph_subSumsFifoOut_V_full_n, ap_predicate_op429_write_state2, ap_block_pp0_stage0)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_predicate_op429_write_state2 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
iph_subSumsFifoOut_V_blk_n <= iph_subSumsFifoOut_V_full_n;
else
iph_subSumsFifoOut_V_blk_n <= ap_const_logic_1;
end if;
end process;
iph_subSumsFifoOut_V_din <= ((((((((((((((((((((((((((((((ap_const_lv34_0 & select_ln887_29_fu_3444_p3) & select_ln887_28_fu_3415_p3) & select_ln887_27_fu_3379_p3) & select_ln887_26_fu_3350_p3) & select_ln887_25_fu_3314_p3) & select_ln887_24_fu_3285_p3) & select_ln887_23_fu_3249_p3) & select_ln887_22_fu_3220_p3) & select_ln887_21_fu_3184_p3) & select_ln887_20_fu_3155_p3) & select_ln887_19_fu_3119_p3) & select_ln887_18_fu_3090_p3) & select_ln887_17_fu_3054_p3) & select_ln887_16_fu_3025_p3) & select_ln887_15_fu_2989_p3) & select_ln887_14_fu_2960_p3) & select_ln887_13_fu_2923_p3) & select_ln887_12_fu_2894_p3) & select_ln887_11_fu_2858_p3) & select_ln887_10_fu_2829_p3) & select_ln887_9_fu_2793_p3) & select_ln887_8_fu_2764_p3) & select_ln887_7_fu_2728_p3) & select_ln887_6_fu_2699_p3) & select_ln887_5_fu_2654_p3) & select_ln887_4_fu_2625_p3) & select_ln887_3_fu_2589_p3) & select_ln887_2_fu_2560_p3) & select_ln887_1_fu_2515_p3) & select_ln887_fu_2486_p3);
iph_subSumsFifoOut_V_write_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_predicate_op429_write_state2, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_predicate_op429_write_state2 = ap_const_boolean_1))) then
iph_subSumsFifoOut_V_write <= ap_const_logic_1;
else
iph_subSumsFifoOut_V_write <= ap_const_logic_0;
end if;
end process;
or_ln566_10_fu_3695_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_1_25_phi_fu_737_p4);
or_ln566_11_fu_3714_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_2_14_phi_fu_770_p4);
or_ln566_12_fu_3733_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_2_17_phi_fu_803_p4);
or_ln566_13_fu_3752_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_2_20_phi_fu_836_p4);
or_ln566_14_fu_3771_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_2_23_phi_fu_869_p4);
or_ln566_15_fu_3790_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_2_26_phi_fu_902_p4);
or_ln566_1_fu_3524_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_0_2_phi_fu_440_p4);
or_ln566_2_fu_3543_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_2_12_phi_fu_473_p4);
or_ln566_3_fu_3562_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_4_2_phi_fu_506_p4);
or_ln566_4_fu_3581_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_6_2_phi_fu_539_p4);
or_ln566_5_fu_3600_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_8_2_phi_fu_572_p4);
or_ln566_6_fu_3619_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_1_13_phi_fu_605_p4);
or_ln566_7_fu_3638_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_1_16_phi_fu_638_p4);
or_ln566_8_fu_3657_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_1_19_phi_fu_671_p4);
or_ln566_9_fu_3676_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_ip_sums_sum_V_1_22_phi_fu_704_p4);
or_ln566_fu_3519_p2 <= (tmp_last_V_reg_4012 or ap_phi_mux_cics_firstWord_flag_s_phi_fu_428_p4);
p_Result_2_1_i136_s_fu_1117_p4 <= ipDataMetaFifo_V_dat_dout(23 downto 16);
p_Result_2_1_i139_s_fu_1163_p4 <= ipDataMetaFifo_V_dat_dout(39 downto 32);
p_Result_2_1_i142_s_fu_1209_p4 <= ipDataMetaFifo_V_dat_dout(55 downto 48);
p_Result_2_1_i145_s_fu_1255_p4 <= ipDataMetaFifo_V_dat_dout(71 downto 64);
p_Result_2_1_i148_s_fu_1301_p4 <= ipDataMetaFifo_V_dat_dout(87 downto 80);
p_Result_2_1_i151_s_fu_1347_p4 <= ipDataMetaFifo_V_dat_dout(103 downto 96);
p_Result_2_1_i154_s_fu_1393_p4 <= ipDataMetaFifo_V_dat_dout(119 downto 112);
p_Result_2_1_i157_s_fu_1439_p4 <= ipDataMetaFifo_V_dat_dout(135 downto 128);
p_Result_2_1_i160_s_fu_1485_p4 <= ipDataMetaFifo_V_dat_dout(151 downto 144);
p_Result_2_1_i163_s_fu_1531_p4 <= ipDataMetaFifo_V_dat_dout(167 downto 160);
p_Result_2_1_i166_s_fu_1577_p4 <= ipDataMetaFifo_V_dat_dout(183 downto 176);
p_Result_2_1_i169_s_fu_1623_p4 <= ipDataMetaFifo_V_dat_dout(199 downto 192);
p_Result_2_1_i172_s_fu_1669_p4 <= ipDataMetaFifo_V_dat_dout(215 downto 208);
p_Result_2_1_i175_s_fu_1715_p4 <= ipDataMetaFifo_V_dat_dout(231 downto 224);
p_Result_2_1_i178_s_fu_1761_p4 <= ipDataMetaFifo_V_dat_dout(247 downto 240);
p_Result_2_1_i181_s_fu_1807_p4 <= ipDataMetaFifo_V_dat_dout(263 downto 256);
p_Result_2_1_i184_s_fu_1853_p4 <= ipDataMetaFifo_V_dat_dout(279 downto 272);
p_Result_2_1_i187_s_fu_1899_p4 <= ipDataMetaFifo_V_dat_dout(295 downto 288);
p_Result_2_1_i190_s_fu_1945_p4 <= ipDataMetaFifo_V_dat_dout(311 downto 304);
p_Result_2_1_i193_s_fu_1991_p4 <= ipDataMetaFifo_V_dat_dout(327 downto 320);
p_Result_2_1_i196_s_fu_2037_p4 <= ipDataMetaFifo_V_dat_dout(343 downto 336);
p_Result_2_1_i199_s_fu_2083_p4 <= ipDataMetaFifo_V_dat_dout(359 downto 352);
p_Result_2_1_i202_s_fu_2129_p4 <= ipDataMetaFifo_V_dat_dout(375 downto 368);
p_Result_2_1_i205_s_fu_2175_p4 <= ipDataMetaFifo_V_dat_dout(391 downto 384);
p_Result_2_1_i208_s_fu_2221_p4 <= ipDataMetaFifo_V_dat_dout(407 downto 400);
p_Result_2_1_i211_s_fu_2267_p4 <= ipDataMetaFifo_V_dat_dout(423 downto 416);
p_Result_2_1_i214_s_fu_2313_p4 <= ipDataMetaFifo_V_dat_dout(439 downto 432);
p_Result_2_1_i217_s_fu_2359_p4 <= ipDataMetaFifo_V_dat_dout(455 downto 448);
p_Result_2_1_i220_s_fu_2405_p4 <= ipDataMetaFifo_V_dat_dout(471 downto 464);
p_Result_2_i135_i_fu_1107_p4 <= ipDataMetaFifo_V_dat_dout(31 downto 24);
p_Result_2_i138_i_fu_1153_p4 <= ipDataMetaFifo_V_dat_dout(47 downto 40);
p_Result_2_i141_i_fu_1199_p4 <= ipDataMetaFifo_V_dat_dout(63 downto 56);
p_Result_2_i144_i_fu_1245_p4 <= ipDataMetaFifo_V_dat_dout(79 downto 72);
p_Result_2_i147_i_fu_1291_p4 <= ipDataMetaFifo_V_dat_dout(95 downto 88);
p_Result_2_i150_i_fu_1337_p4 <= ipDataMetaFifo_V_dat_dout(111 downto 104);
p_Result_2_i153_i_fu_1383_p4 <= ipDataMetaFifo_V_dat_dout(127 downto 120);
p_Result_2_i156_i_fu_1429_p4 <= ipDataMetaFifo_V_dat_dout(143 downto 136);
p_Result_2_i159_i_fu_1475_p4 <= ipDataMetaFifo_V_dat_dout(159 downto 152);
p_Result_2_i162_i_fu_1521_p4 <= ipDataMetaFifo_V_dat_dout(175 downto 168);
p_Result_2_i165_i_fu_1567_p4 <= ipDataMetaFifo_V_dat_dout(191 downto 184);
p_Result_2_i168_i_fu_1613_p4 <= ipDataMetaFifo_V_dat_dout(207 downto 200);
p_Result_2_i171_i_fu_1659_p4 <= ipDataMetaFifo_V_dat_dout(223 downto 216);
p_Result_2_i174_i_fu_1705_p4 <= ipDataMetaFifo_V_dat_dout(239 downto 232);
p_Result_2_i177_i_fu_1751_p4 <= ipDataMetaFifo_V_dat_dout(255 downto 248);
p_Result_2_i180_i_fu_1797_p4 <= ipDataMetaFifo_V_dat_dout(271 downto 264);
p_Result_2_i183_i_fu_1843_p4 <= ipDataMetaFifo_V_dat_dout(287 downto 280);
p_Result_2_i186_i_fu_1889_p4 <= ipDataMetaFifo_V_dat_dout(303 downto 296);
p_Result_2_i189_i_fu_1935_p4 <= ipDataMetaFifo_V_dat_dout(319 downto 312);
p_Result_2_i192_i_fu_1981_p4 <= ipDataMetaFifo_V_dat_dout(335 downto 328);
p_Result_2_i195_i_fu_2027_p4 <= ipDataMetaFifo_V_dat_dout(351 downto 344);
p_Result_2_i198_i_fu_2073_p4 <= ipDataMetaFifo_V_dat_dout(367 downto 360);
p_Result_2_i201_i_fu_2119_p4 <= ipDataMetaFifo_V_dat_dout(383 downto 376);
p_Result_2_i204_i_fu_2165_p4 <= ipDataMetaFifo_V_dat_dout(399 downto 392);
p_Result_2_i207_i_fu_2211_p4 <= ipDataMetaFifo_V_dat_dout(415 downto 408);
p_Result_2_i210_i_fu_2257_p4 <= ipDataMetaFifo_V_dat_dout(431 downto 424);
p_Result_2_i213_i_fu_2303_p4 <= ipDataMetaFifo_V_dat_dout(447 downto 440);
p_Result_2_i216_i_fu_2349_p4 <= ipDataMetaFifo_V_dat_dout(463 downto 456);
p_Result_2_i219_i_fu_2395_p4 <= ipDataMetaFifo_V_dat_dout(479 downto 472);
p_Result_2_i_i_fu_1067_p4 <= ipDataMetaFifo_V_dat_dout(15 downto 8);
select_ln566_10_fu_3624_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_14_phi_fu_616_p4;
select_ln566_11_fu_3631_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_15_phi_fu_627_p4;
select_ln566_12_fu_3643_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_17_phi_fu_649_p4;
select_ln566_13_fu_3650_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_18_phi_fu_660_p4;
select_ln566_14_fu_3662_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_20_phi_fu_682_p4;
select_ln566_15_fu_3669_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_21_phi_fu_693_p4;
select_ln566_16_fu_3681_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_23_phi_fu_715_p4;
select_ln566_17_fu_3688_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_24_phi_fu_726_p4;
select_ln566_18_fu_3700_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_26_phi_fu_748_p4;
select_ln566_19_fu_3707_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_27_phi_fu_759_p4;
select_ln566_1_fu_3536_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_1_12_phi_fu_462_p4;
select_ln566_20_fu_3719_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_15_phi_fu_781_p4;
select_ln566_21_fu_3726_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_16_phi_fu_792_p4;
select_ln566_22_fu_3738_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_18_phi_fu_814_p4;
select_ln566_23_fu_3745_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_19_phi_fu_825_p4;
select_ln566_24_fu_3757_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_21_phi_fu_847_p4;
select_ln566_25_fu_3764_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_22_phi_fu_858_p4;
select_ln566_26_fu_3776_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_24_phi_fu_880_p4;
select_ln566_27_fu_3783_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_25_phi_fu_891_p4;
select_ln566_28_fu_3795_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_27_phi_fu_913_p4;
select_ln566_29_fu_3802_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_28_phi_fu_924_p4;
select_ln566_2_fu_3548_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_2_13_phi_fu_484_p4;
select_ln566_3_fu_3555_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_3_2_phi_fu_495_p4;
select_ln566_4_fu_3567_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_4_3_phi_fu_517_p4;
select_ln566_5_fu_3574_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_5_2_phi_fu_528_p4;
select_ln566_6_fu_3586_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_6_3_phi_fu_550_p4;
select_ln566_7_fu_3593_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_7_2_phi_fu_561_p4;
select_ln566_8_fu_3605_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_8_3_phi_fu_583_p4;
select_ln566_9_fu_3612_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_9_2_phi_fu_594_p4;
select_ln566_fu_3529_p3 <=
ap_const_lv17_0 when (tmp_last_V_reg_4012(0) = '1') else
ap_phi_mux_cics_ip_sums_sum_V_0_3_phi_fu_451_p4;
select_ln887_10_fu_2829_p3 <=
zext_ln214_10_fu_2825_p1 when (icmp_ln887_5_fu_2801_p2(0) = '1') else
cics_ip_sums_sum_V_1_2_reg_4128;
select_ln887_11_fu_2858_p3 <=
zext_ln214_11_fu_2854_p1 when (icmp_ln887_5_fu_2801_p2(0) = '1') else
cics_ip_sums_sum_V_1_3_reg_4134;
select_ln887_12_fu_2894_p3 <=
zext_ln214_12_fu_2890_p1 when (icmp_ln887_6_fu_2866_p2(0) = '1') else
cics_ip_sums_sum_V_1_4_reg_4140;
select_ln887_13_fu_2923_p3 <=
zext_ln214_13_fu_2919_p1 when (icmp_ln887_6_fu_2866_p2(0) = '1') else
cics_ip_sums_sum_V_1_5_reg_4146;
select_ln887_14_fu_2960_p3 <=
zext_ln214_14_fu_2956_p1 when (tmp_29_fu_2931_p3(0) = '1') else
cics_ip_sums_sum_V_1_6_reg_4152;
select_ln887_15_fu_2989_p3 <=
zext_ln214_15_fu_2985_p1 when (tmp_29_fu_2931_p3(0) = '1') else
cics_ip_sums_sum_V_1_7_reg_4158;
select_ln887_16_fu_3025_p3 <=
zext_ln214_16_fu_3021_p1 when (icmp_ln887_7_fu_2997_p2(0) = '1') else
cics_ip_sums_sum_V_1_8_reg_4164;
select_ln887_17_fu_3054_p3 <=
zext_ln214_17_fu_3050_p1 when (icmp_ln887_7_fu_2997_p2(0) = '1') else
cics_ip_sums_sum_V_1_9_reg_4170;
select_ln887_18_fu_3090_p3 <=
zext_ln214_18_fu_3086_p1 when (icmp_ln887_8_fu_3062_p2(0) = '1') else
cics_ip_sums_sum_V_1_10_reg_4176;
select_ln887_19_fu_3119_p3 <=
zext_ln214_19_fu_3115_p1 when (icmp_ln887_8_fu_3062_p2(0) = '1') else
cics_ip_sums_sum_V_1_11_reg_4182;
select_ln887_1_fu_2515_p3 <=
cics_ip_sums_sum_V_1_1_reg_4074 when (icmp_ln887_fu_2452_p2(0) = '1') else
zext_ln214_1_fu_2511_p1;
select_ln887_20_fu_3155_p3 <=
zext_ln214_20_fu_3151_p1 when (icmp_ln887_9_fu_3127_p2(0) = '1') else
cics_ip_sums_sum_V_2_2_reg_4188;
select_ln887_21_fu_3184_p3 <=
zext_ln214_21_fu_3180_p1 when (icmp_ln887_9_fu_3127_p2(0) = '1') else
cics_ip_sums_sum_V_2_3_reg_4194;
select_ln887_22_fu_3220_p3 <=
zext_ln214_22_fu_3216_p1 when (icmp_ln887_10_fu_3192_p2(0) = '1') else
cics_ip_sums_sum_V_2_4_reg_4200;
select_ln887_23_fu_3249_p3 <=
zext_ln214_23_fu_3245_p1 when (icmp_ln887_10_fu_3192_p2(0) = '1') else
cics_ip_sums_sum_V_2_5_reg_4206;
select_ln887_24_fu_3285_p3 <=
zext_ln214_24_fu_3281_p1 when (icmp_ln887_11_fu_3257_p2(0) = '1') else
cics_ip_sums_sum_V_2_6_reg_4212;
select_ln887_25_fu_3314_p3 <=
zext_ln214_25_fu_3310_p1 when (icmp_ln887_11_fu_3257_p2(0) = '1') else
cics_ip_sums_sum_V_2_7_reg_4218;
select_ln887_26_fu_3350_p3 <=
zext_ln214_26_fu_3346_p1 when (icmp_ln887_12_fu_3322_p2(0) = '1') else
cics_ip_sums_sum_V_2_8_reg_4224;
select_ln887_27_fu_3379_p3 <=
zext_ln214_27_fu_3375_p1 when (icmp_ln887_12_fu_3322_p2(0) = '1') else
cics_ip_sums_sum_V_2_9_reg_4230;
select_ln887_28_fu_3415_p3 <=
zext_ln214_28_fu_3411_p1 when (icmp_ln887_13_fu_3387_p2(0) = '1') else
cics_ip_sums_sum_V_2_10_reg_4236;
select_ln887_29_fu_3444_p3 <=
zext_ln214_29_fu_3440_p1 when (icmp_ln887_13_fu_3387_p2(0) = '1') else
cics_ip_sums_sum_V_2_11_reg_4242;
select_ln887_2_fu_2560_p3 <=
zext_ln214_2_fu_2556_p1 when (icmp_ln887_1_fu_2532_p2(0) = '1') else
cics_ip_sums_sum_V_2_1_reg_4080;
select_ln887_3_fu_2589_p3 <=
zext_ln214_3_fu_2585_p1 when (icmp_ln887_1_fu_2532_p2(0) = '1') else
cics_ip_sums_sum_V_3_1_reg_4086;
select_ln887_4_fu_2625_p3 <=
zext_ln214_4_fu_2621_p1 when (icmp_ln887_2_fu_2597_p2(0) = '1') else
cics_ip_sums_sum_V_4_1_reg_4092;
select_ln887_5_fu_2654_p3 <=
zext_ln214_5_fu_2650_p1 when (icmp_ln887_2_fu_2597_p2(0) = '1') else
cics_ip_sums_sum_V_5_1_reg_4098;
select_ln887_6_fu_2699_p3 <=
zext_ln214_6_fu_2695_p1 when (icmp_ln887_3_fu_2671_p2(0) = '1') else
cics_ip_sums_sum_V_6_1_reg_4104;
select_ln887_7_fu_2728_p3 <=
zext_ln214_7_fu_2724_p1 when (icmp_ln887_3_fu_2671_p2(0) = '1') else
cics_ip_sums_sum_V_7_1_reg_4110;
select_ln887_8_fu_2764_p3 <=
zext_ln214_8_fu_2760_p1 when (icmp_ln887_4_fu_2736_p2(0) = '1') else
cics_ip_sums_sum_V_8_1_reg_4116;
select_ln887_9_fu_2793_p3 <=
zext_ln214_9_fu_2789_p1 when (icmp_ln887_4_fu_2736_p2(0) = '1') else
cics_ip_sums_sum_V_9_1_reg_4122;
select_ln887_fu_2486_p3 <=
cics_ip_sums_sum_V_0_1_reg_4068 when (icmp_ln887_fu_2452_p2(0) = '1') else
zext_ln214_fu_2475_p1;
tmp_15_fu_2523_p4 <= tmp_data_V_reg_3998(3 downto 1);
tmp_20_fu_2662_p4 <= tmp_data_V_reg_3998(3 downto 2);
tmp_29_fu_2931_p3 <= tmp_data_V_reg_3998(3 downto 3);
tmp_nbreadreq_fu_388_p5 <= (0=>(ipDataMetaFifo_V_las_empty_n and ipDataMetaFifo_V_kee_empty_n and ipDataMetaFifo_V_dat_empty_n), others=>'-');
trunc_ln647_3_fu_1077_p1 <= ipDataMetaFifo_V_dat_dout(8 - 1 downto 0);
trunc_ln647_fu_2449_p1 <= tmp_data_V_reg_3998(4 - 1 downto 0);
trunc_ln700_10_fu_2808_p1 <= cics_ip_sums_sum_V_1_2_reg_4128(16 - 1 downto 0);
trunc_ln700_11_fu_2837_p1 <= cics_ip_sums_sum_V_1_3_reg_4134(16 - 1 downto 0);
trunc_ln700_12_fu_2873_p1 <= cics_ip_sums_sum_V_1_4_reg_4140(16 - 1 downto 0);
trunc_ln700_13_fu_2902_p1 <= cics_ip_sums_sum_V_1_5_reg_4146(16 - 1 downto 0);
trunc_ln700_14_fu_2939_p1 <= cics_ip_sums_sum_V_1_6_reg_4152(16 - 1 downto 0);
trunc_ln700_15_fu_2968_p1 <= cics_ip_sums_sum_V_1_7_reg_4158(16 - 1 downto 0);
trunc_ln700_16_fu_3004_p1 <= cics_ip_sums_sum_V_1_8_reg_4164(16 - 1 downto 0);
trunc_ln700_17_fu_3033_p1 <= cics_ip_sums_sum_V_1_9_reg_4170(16 - 1 downto 0);
trunc_ln700_18_fu_3069_p1 <= cics_ip_sums_sum_V_1_10_reg_4176(16 - 1 downto 0);
trunc_ln700_19_fu_3098_p1 <= cics_ip_sums_sum_V_1_11_reg_4182(16 - 1 downto 0);
trunc_ln700_1_fu_2494_p1 <= cics_ip_sums_sum_V_1_1_reg_4074(16 - 1 downto 0);
trunc_ln700_20_fu_3134_p1 <= cics_ip_sums_sum_V_2_2_reg_4188(16 - 1 downto 0);
trunc_ln700_21_fu_3163_p1 <= cics_ip_sums_sum_V_2_3_reg_4194(16 - 1 downto 0);
trunc_ln700_22_fu_3199_p1 <= cics_ip_sums_sum_V_2_4_reg_4200(16 - 1 downto 0);
trunc_ln700_23_fu_3228_p1 <= cics_ip_sums_sum_V_2_5_reg_4206(16 - 1 downto 0);
trunc_ln700_24_fu_3264_p1 <= cics_ip_sums_sum_V_2_6_reg_4212(16 - 1 downto 0);
trunc_ln700_25_fu_3293_p1 <= cics_ip_sums_sum_V_2_7_reg_4218(16 - 1 downto 0);
trunc_ln700_26_fu_3329_p1 <= cics_ip_sums_sum_V_2_8_reg_4224(16 - 1 downto 0);
trunc_ln700_27_fu_3358_p1 <= cics_ip_sums_sum_V_2_9_reg_4230(16 - 1 downto 0);
trunc_ln700_28_fu_3394_p1 <= cics_ip_sums_sum_V_2_10_reg_4236(16 - 1 downto 0);
trunc_ln700_29_fu_3423_p1 <= cics_ip_sums_sum_V_2_11_reg_4242(16 - 1 downto 0);
trunc_ln700_2_fu_2539_p1 <= cics_ip_sums_sum_V_2_1_reg_4080(16 - 1 downto 0);
trunc_ln700_3_fu_2568_p1 <= cics_ip_sums_sum_V_3_1_reg_4086(16 - 1 downto 0);
trunc_ln700_4_fu_2604_p1 <= cics_ip_sums_sum_V_4_1_reg_4092(16 - 1 downto 0);
trunc_ln700_5_fu_2633_p1 <= cics_ip_sums_sum_V_5_1_reg_4098(16 - 1 downto 0);
trunc_ln700_6_fu_2678_p1 <= cics_ip_sums_sum_V_6_1_reg_4104(16 - 1 downto 0);
trunc_ln700_7_fu_2707_p1 <= cics_ip_sums_sum_V_7_1_reg_4110(16 - 1 downto 0);
trunc_ln700_8_fu_2743_p1 <= cics_ip_sums_sum_V_8_1_reg_4116(16 - 1 downto 0);
trunc_ln700_9_fu_2772_p1 <= cics_ip_sums_sum_V_9_1_reg_4122(16 - 1 downto 0);
trunc_ln700_fu_2458_p1 <= cics_ip_sums_sum_V_0_1_reg_4068(16 - 1 downto 0);
xor_ln887_fu_2479_p2 <= (icmp_ln887_fu_2452_p2 xor ap_const_lv1_1);
zext_ln214_10_fu_2825_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_21_fu_2820_p2),17));
zext_ln214_11_fu_2854_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_23_fu_2849_p2),17));
zext_ln214_12_fu_2890_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_25_fu_2885_p2),17));
zext_ln214_13_fu_2919_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_27_fu_2914_p2),17));
zext_ln214_14_fu_2956_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_29_fu_2951_p2),17));
zext_ln214_15_fu_2985_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_31_fu_2980_p2),17));
zext_ln214_16_fu_3021_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_33_fu_3016_p2),17));
zext_ln214_17_fu_3050_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_35_fu_3045_p2),17));
zext_ln214_18_fu_3086_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_37_fu_3081_p2),17));
zext_ln214_19_fu_3115_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_39_fu_3110_p2),17));
zext_ln214_1_fu_2511_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_3_fu_2506_p2),17));
zext_ln214_20_fu_3151_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_41_fu_3146_p2),17));
zext_ln214_21_fu_3180_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_43_fu_3175_p2),17));
zext_ln214_22_fu_3216_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_45_fu_3211_p2),17));
zext_ln214_23_fu_3245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_47_fu_3240_p2),17));
zext_ln214_24_fu_3281_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_49_fu_3276_p2),17));
zext_ln214_25_fu_3310_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_51_fu_3305_p2),17));
zext_ln214_26_fu_3346_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_53_fu_3341_p2),17));
zext_ln214_27_fu_3375_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_55_fu_3370_p2),17));
zext_ln214_28_fu_3411_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_57_fu_3406_p2),17));
zext_ln214_29_fu_3440_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_59_fu_3435_p2),17));
zext_ln214_2_fu_2556_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_5_fu_2551_p2),17));
zext_ln214_30_fu_2461_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_reg_4253),16));
zext_ln214_31_fu_2497_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_14_reg_4263),16));
zext_ln214_32_fu_2542_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_16_reg_4273),16));
zext_ln214_33_fu_2571_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_17_reg_4283),16));
zext_ln214_34_fu_2607_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_18_reg_4293),16));
zext_ln214_35_fu_2636_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_19_reg_4303),16));
zext_ln214_36_fu_2681_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_21_reg_4313),16));
zext_ln214_37_fu_2710_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_22_reg_4323),16));
zext_ln214_38_fu_2746_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_23_reg_4333),16));
zext_ln214_39_fu_2775_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_24_reg_4343),16));
zext_ln214_3_fu_2585_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_7_fu_2580_p2),17));
zext_ln214_40_fu_2811_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_25_reg_4353),16));
zext_ln214_41_fu_2840_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_26_reg_4363),16));
zext_ln214_42_fu_2876_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_27_reg_4373),16));
zext_ln214_43_fu_2905_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_28_reg_4383),16));
zext_ln214_44_fu_2942_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_30_reg_4393),16));
zext_ln214_45_fu_2971_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_reg_4403),16));
zext_ln214_46_fu_3007_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_32_reg_4413),16));
zext_ln214_47_fu_3036_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_33_reg_4423),16));
zext_ln214_48_fu_3072_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_34_reg_4433),16));
zext_ln214_49_fu_3101_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_35_reg_4443),16));
zext_ln214_4_fu_2621_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_9_fu_2616_p2),17));
zext_ln214_50_fu_3137_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_36_reg_4453),16));
zext_ln214_51_fu_3166_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_37_reg_4463),16));
zext_ln214_52_fu_3202_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_38_reg_4473),16));
zext_ln214_53_fu_3231_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_39_reg_4483),16));
zext_ln214_54_fu_3267_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_40_reg_4493),16));
zext_ln214_55_fu_3296_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_41_reg_4503),16));
zext_ln214_56_fu_3332_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_42_reg_4513),16));
zext_ln214_57_fu_3361_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_43_reg_4523),16));
zext_ln214_58_fu_3397_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_44_reg_4533),16));
zext_ln214_59_fu_3426_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_45_reg_4543),16));
zext_ln214_5_fu_2650_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_11_fu_2645_p2),17));
zext_ln214_6_fu_2695_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_13_fu_2690_p2),17));
zext_ln214_7_fu_2724_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_15_fu_2719_p2),17));
zext_ln214_8_fu_2760_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_17_fu_2755_p2),17));
zext_ln214_9_fu_2789_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_19_fu_2784_p2),17));
zext_ln214_fu_2475_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln214_1_fu_2470_p2),17));
zext_ln700_10_fu_1549_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i16_1_fu_1541_p3),17));
zext_ln700_11_fu_1595_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i16_2_fu_1587_p3),17));
zext_ln700_12_fu_1641_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i4_fu_1633_p3),17));
zext_ln700_13_fu_1687_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i17_1_fu_1679_p3),17));
zext_ln700_14_fu_1733_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i17_2_fu_1725_p3),17));
zext_ln700_15_fu_1779_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i17_3_fu_1771_p3),17));
zext_ln700_16_fu_1825_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i5_fu_1817_p3),17));
zext_ln700_17_fu_1871_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i18_1_fu_1863_p3),17));
zext_ln700_18_fu_1917_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i18_2_fu_1909_p3),17));
zext_ln700_19_fu_1963_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i6_fu_1955_p3),17));
zext_ln700_1_fu_1135_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i_fu_1127_p3),17));
zext_ln700_20_fu_2009_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i19_1_fu_2001_p3),17));
zext_ln700_21_fu_2055_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i19_2_fu_2047_p3),17));
zext_ln700_22_fu_2101_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i7_fu_2093_p3),17));
zext_ln700_23_fu_2147_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i20_1_fu_2139_p3),17));
zext_ln700_24_fu_2193_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i20_2_fu_2185_p3),17));
zext_ln700_25_fu_2239_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i20_3_fu_2231_p3),17));
zext_ln700_26_fu_2285_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i8_fu_2277_p3),17));
zext_ln700_27_fu_2331_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i21_1_fu_2323_p3),17));
zext_ln700_28_fu_2377_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i21_2_fu_2369_p3),17));
zext_ln700_29_fu_2423_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i9_fu_2415_p3),17));
zext_ln700_2_fu_1181_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i1_fu_1173_p3),17));
zext_ln700_3_fu_1227_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i14_1_fu_1219_p3),17));
zext_ln700_4_fu_1273_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i14_2_fu_1265_p3),17));
zext_ln700_5_fu_1319_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i14_3_fu_1311_p3),17));
zext_ln700_6_fu_1365_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i2_fu_1357_p3),17));
zext_ln700_7_fu_1411_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i15_1_fu_1403_p3),17));
zext_ln700_8_fu_1457_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i15_2_fu_1449_p3),17));
zext_ln700_9_fu_1503_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i3_fu_1495_p3),17));
zext_ln700_fu_1089_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(agg_result_V_0_1_i_i_fu_1081_p3),17));
end behav;
|
<filename>small_board/LABS/digital_logic/vhdl/lab2/part5/circuitb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY circuitb IS
PORT (SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END circuitb;
ARCHITECTURE Behavior OF circuitb IS
BEGIN
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= SW;
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= '0';
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= '0';
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= SW;
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= SW;
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= SW;
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= '1';
END Behavior;
|
-- Error definitions for the parsing of a PGM image file.
library ieee;
use ieee.std_logic_1164.all;
package image_io_error is
constant NONE : std_logic_vector(3 downto 0) := "0000";
constant INVALID_FILETYPE : std_logic_vector(3 downto 0) := "0001";
constant WIDTH_TOO_LARGE : std_logic_vector(3 downto 0) := "0010";
constant HEIGHT_TOO_LARGE : std_logic_vector(3 downto 0) := "0011";
constant MAXVAL_TOO_LARGE : std_logic_vector(3 downto 0) := "0100";
constant PIXEL_TOO_LARGE : std_logic_vector(3 downto 0) := "0101";
constant TOO_MANY_PIXELS : std_logic_vector(3 downto 0) := "0110";
constant TOO_FEW_PIXELS : std_logic_vector(3 downto 0) := "0111";
constant INVALID_TOKEN : std_logic_vector(3 downto 0) := "<PASSWORD>";
end package;
|
<filename>hardware/src_rtl/lboxTop.vhd<gh_stars>0
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01/21/2022 05:03:49 PM
-- Design Name:
-- Module Name: lboxTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lboxTop is
Port (
Din: in std_logic_vector(127 downto 0);
Dout: out std_logic_vector(127 downto 0)
);
end lboxTop;
architecture Behavioral of lboxTop is
signal temp: std_logic_vector(127 downto 0):=Din;
begin
lbox_calc: for I in 0 to 1 generate
--able to add logic for if generate statement
--TO DO: add decryption logic for lbox and sbox top levels
lbox: ENTITY work.l_box
port map(
input => temp(64*I+63 downto 64*I),
output => temp(64*I+63 downto 64*I)
);
end generate;
Dout <= temp;
end Behavioral;
|
<filename>src/input_control.vhd
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
---input_control
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity input_control is
port (
clk:in std_logic;
UD0: out std_logic_vector(1 downto 0);
LR0: out std_logic_vector(1 downto 0);
Rx : in std_logic
);
type array3 is array(10 downto 0) of std_logic_vector(7 downto 0);
end input_control;
architecture input of input_control is
signal angle_lr:std_logic_vector(7 downto 0);---取[-180,180]取整,左负右正，最高位表示正副，其余八位表示数值.大于128则以128计
signal angle_ud: std_logic_vector(7 downto 0);
signal async_ready: std_logic:='0';
signal async_buff : unsigned(7 downto 0);
signal Rd_clear: std_logic:='1';
signal my_buffer : array3;
signal state_buffer:integer:=0;
signal ud :std_logic_vector(1 downto 0):="01";
signal lr :std_logic_vector(1 downto 0):="01";
--signal temp0:std_logic_vector(15 downto 0);
--------------------------------------------------------------------------------------------------------------------------------------
component async_receiver
port(
RxD:in std_logic;
RxD_clear:in std_logic;
RxD_data:out unsigned(7 downto 0);
RxD_data_ready:out std_logic;
clk:in std_logic
);
end component;
-------------------------------------------------------------------------------------------------------------------------------------
begin
a_r:async_receiver port map(Rx,Rd_clear,async_buff,async_ready,clk);
ud0<=ud;
lr0<=lr;
process(async_buff,async_ready)
variable temp0:std_logic_vector(15 downto 0);
variable temp1:integer;
variable temp2:std_logic_vector(15 downto 0);
variable temp3:std_logic_vector(15 downto 0);
variable temp4:integer;
variable temp5:std_logic_vector(15 downto 0);
begin
if(rising_edge(clk))then
if(async_ready = '1')then
case state_buffer is
when 0 =>
if(async_buff = "01010101") then
my_buffer(0) <= std_logic_vector(async_buff);
state_buffer <= 1;
Rd_clear <= '1';
else
Rd_clear <= '1';
end if;
when 12 =>
if(my_buffer(1)="01010011") then
if(my_buffer(10)=my_buffer(0)+my_buffer(1)+my_buffer(2)+my_buffer(3)+my_buffer(4)+my_buffer(5)+my_buffer(6)+my_buffer(7)+my_buffer(8)+my_buffer(9))then
temp0(15 downto 8) := my_buffer(3);
temp0(7 downto 0) :=my_buffer(2);
temp1 := to_integer(unsigned(temp0))*180;
temp2 := std_logic_vector(to_unsigned(temp1,16));
angle_lr<=temp2(15 downto 8);
temp3(15 downto 8) := my_buffer(5);
temp3(7 downto 0) :=my_buffer(4);
temp4 := to_integer(unsigned(temp3))*180;
temp5 := std_logic_vector(to_unsigned(temp4,16));
angle_ud<=temp5(15 downto 8);
state_buffer <= 0;
end if;
Rd_clear <= '1';
else
Rd_clear <= '1';
end if;
state_buffer <= 0;
when others =>
my_buffer(state_buffer-1) <= std_logic_vector(async_buff);
state_buffer <= state_buffer+1;
Rd_clear <= '1';
end case;
end if;
end if;
end process;
process(angle_lr,angle_ud)
begin
if(rising_edge(clk)) then
if(angle_lr(6)= '0' and angle_lr(5)='0' and angle_lr(4)='0') then---绝对值小
LR <= "01";---不操作
else---绝对值大，由正负判断操作
if(angle_lr(7)='0')then
LR <= "00";
else
LR <= "11";
end if;
end if;
if(angle_ud(6)= '0' and angle_ud(5)='0' and angle_ud(4)='0') then---绝对值小
UD <= "01";---不操作
else---绝对值大，由正负判断操作
if(angle_ud(7)='0')then
UD <= "00";
else
UD <= "11";
end if;
end if;
end if;
end process;
end input;
--------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 10.3 (stable) (v10_3)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Generated from Verilog module ASSERTION_ERROR (async.v:186)
entity ASSERTION_ERROR is
end entity;
-- Generated from Verilog module ASSERTION_ERROR (async.v:186)
architecture from_verilog of ASSERTION_ERROR is
begin
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Generated from Verilog module async_receiver (async.v:75)
-- Baud = 115200
-- ClkFrequency = 25000000
-- Oversampling = 8
-- l2o = 4
entity async_receiver is
port (
RxD : in std_logic;
RxD_clear : in std_logic;
RxD_data : out unsigned(7 downto 0);
RxD_data_ready : out std_logic;
clk : in std_logic
);
end entity;
-- Generated from Verilog module async_receiver (async.v:75)
-- Baud = 115200
-- ClkFrequency = 25000000
-- Oversampling = 8
-- l2o = 4
architecture from_verilog of async_receiver is
function log2 (
v : signed(31 downto 0)
)
return signed;
signal RxD_data_Reg : unsigned(7 downto 0);
signal RxD_data_ready_Reg : std_logic;
signal Filter_cnt : unsigned(1 downto 0) := "11"; -- Declared at async.v:119
signal GapCnt : unsigned(5 downto 0) := "000000"; -- Declared at async.v:175
signal OversamplingCnt : unsigned(2 downto 0) := "000"; -- Declared at async.v:137
signal OversamplingTick : std_logic; -- Declared at async.v:111
signal RxD_bit : std_logic := '1'; -- Declared at async.v:120
signal RxD_endofpacket : std_logic; -- Declared at async.v:101
signal RxD_idle : std_logic; -- Declared at async.v:100
signal RxD_state : unsigned(3 downto 0) := X"0"; -- Declared at async.v:104
signal RxD_sync : unsigned(1 downto 0) := "11"; -- Declared at async.v:115
signal tmp_s2 : unsigned(31 downto 0); -- Temporary created at async.v:139
signal tmp_s5 : unsigned(28 downto 0); -- Temporary created at async.v:139
signal tmp_s6 : unsigned(31 downto 0); -- Temporary created at async.v:139
signal tmp_s8 : std_logic; -- Temporary created at async.v:139
signal sampleNow : std_logic; -- Declared at async.v:139
component BaudTickGen is
port (
clk : in std_logic;
enable : in std_logic;
tick : out std_logic
);
end component;
function Signed_To_Boolean(X : signed) return Boolean is
begin
return X /= To_Signed(0, X'Length);
end function;
-- Generated from function log2 at async.v:135
function log2 (
v : signed(31 downto 0)
)
return signed is
variable log2_Result : signed(31 downto 0);
begin
log2_Result := X"00000000";
while Signed_To_Boolean(v srl To_Integer(Resize(unsigned(log2_Result), 32))) loop
log2_Result := log2_Result + X"00000001";
end loop;
return log2_Result;
end function;
function Boolean_To_Logic(B : Boolean) return std_logic is
begin
if B then
return '1';
else
return '0';
end if;
end function;
function Reduce_AND(X : std_logic_vector) return std_logic is
variable R : std_logic := '1';
begin
for I in X'Range loop
R := X(I) and R;
end loop;
return R;
end function;
begin
RxD_data <= RxD_data_Reg;
RxD_data_ready <= RxD_data_ready_Reg;
sampleNow <= OversamplingTick and tmp_s8;
tmp_s2 <= tmp_s5 & OversamplingCnt;
tmp_s8 <= '1' when tmp_s2 = tmp_s6 else '0';
RxD_idle <= GapCnt(5);
-- Generated from instantiation at async.v:112
tickgen: BaudTickGen
port map (
clk => clk,
enable => '1',
tick => OversamplingTick
);
tmp_s5 <= "00000000000000000000000000000";
tmp_s6 <= X"00000003";
-- Removed one empty process
-- Generated from always process in async_receiver (async.v:116)
process (clk) is
begin
if rising_edge(clk) then
if OversamplingTick = '1' then
RxD_sync <= RxD_sync(0) & RxD;
end if;
end if;
end process;
-- Generated from always process in async_receiver (async.v:122)
process (clk) is
begin
if rising_edge(clk) then
if OversamplingTick = '1' then
if (RxD_sync(1) = '1') and (Filter_cnt /= "11") then
Filter_cnt <= Filter_cnt + "01";
else
if (RxD_sync(1) = '0') and (Filter_cnt /= "00") then
Filter_cnt <= Filter_cnt - "01";
end if;
end if;
if Filter_cnt = "11" then
RxD_bit <= '1';
else
if Filter_cnt = "00" then
RxD_bit <= '0';
end if;
end if;
end if;
end if;
end process;
-- Generated from always process in async_receiver (async.v:138)
process (clk) is
begin
if rising_edge(clk) then
if OversamplingTick = '1' then
if Resize(RxD_state, 32) = X"00000000" then
OversamplingCnt <= "000";
else
OversamplingCnt <= OversamplingCnt + "001";
end if;
end if;
end if;
end process;
-- Generated from always process in async_receiver (async.v:143)
process (clk) is
begin
if rising_edge(clk) then
case RxD_state is
when X"0" =>
if (not RxD_bit) = '1' then
RxD_state <= X"1";
end if;
when X"1" =>
if sampleNow = '1' then
RxD_state <= X"8";
end if;
when X"8" =>
if sampleNow = '1' then
RxD_state <= X"9";
end if;
when X"9" =>
if sampleNow = '1' then
RxD_state <= X"a";
end if;
when X"a" =>
if sampleNow = '1' then
RxD_state <= X"b";
end if;
when X"b" =>
if sampleNow = '1' then
RxD_state <= X"c";
end if;
when X"c" =>
if sampleNow = '1' then
RxD_state <= X"d";
end if;
when X"d" =>
if sampleNow = '1' then
RxD_state <= X"e";
end if;
when X"e" =>
if sampleNow = '1' then
RxD_state <= X"f";
end if;
when X"f" =>
if sampleNow = '1' then
RxD_state <= X"2";
end if;
when X"2" =>
if sampleNow = '1' then
RxD_state <= X"0";
end if;
when others =>
RxD_state <= X"0";
end case;
end if;
end process;
-- Generated from always process in async_receiver (async.v:159)
process (clk) is
begin
if rising_edge(clk) then
if (sampleNow = '1') and (RxD_state(3) = '1') then
RxD_data_Reg <= RxD_bit & RxD_data_Reg(1 + 6 downto 1);
end if;
end if;
end process;
-- Generated from always process in async_receiver (async.v:163)
process (clk) is
begin
if rising_edge(clk) then
if RxD_clear = '1' then
RxD_data_ready_Reg <= '0';
else
RxD_data_ready_Reg <= Boolean_To_Logic((RxD_data_ready_Reg = '1') or (((sampleNow = '1') and (RxD_state = X"2")) and (RxD_bit = '1')));
end if;
end if;
end process;
-- Generated from always process in async_receiver (async.v:176)
process (clk) is
begin
if rising_edge(clk) then
if Resize(RxD_state, 32) /= X"00000000" then
GapCnt <= "000000";
else
if (OversamplingTick and (not GapCnt(To_Integer((log2(X"00000008") + X"00000001"))))) = '1' then
GapCnt <= GapCnt + "000001";
end if;
end if;
end if;
end process;
-- Generated from always process in async_receiver (async.v:178)
process (clk) is
begin
if rising_edge(clk) then
RxD_endofpacket <= (OversamplingTick and (not GapCnt(5))) and Reduce_AND(std_logic_vector(GapCnt(0 + 4 downto 0)));
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Generated from Verilog module BaudTickGen (async.v:191)
-- AccWidth = 16
-- Baud = 115200
-- ClkFrequency = 25000000
-- Inc = 2416
-- Oversampling = 8
-- ShiftLimiter = 5
entity BaudTickGen is
port (
clk : in std_logic;
enable : in std_logic;
tick : out std_logic
);
end entity;
-- Generated from Verilog module BaudTickGen (async.v:191)
-- AccWidth = 16
-- Baud = 115200
-- ClkFrequency = 25000000
-- Inc = 2416
-- Oversampling = 8
-- ShiftLimiter = 5
architecture from_verilog of BaudTickGen is
signal Acc : unsigned(16 downto 0) := "00000000000000000"; -- Declared at async.v:201
begin
tick <= Acc(16);
-- Removed one empty process
-- Generated from always process in BaudTickGen (async.v:204)
process (clk) is
begin
if rising_edge(clk) then
if enable = '1' then
Acc <= Resize(Acc(0 + 15 downto 0), 17) + "00000100101110000";
else
Acc <= "00000100101110000";
end if;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Generated from Verilog module async_transmitter (async.v:14)
-- Baud = 115200
-- ClkFrequency = 25000000
entity async_transmitter is
port (
TxD : out std_logic;
TxD_busy : out std_logic;
TxD_data : in unsigned(7 downto 0);
TxD_start : in std_logic;
clk : in std_logic
);
end entity;
-- Generated from Verilog module async_transmitter (async.v:14)
-- Baud = 115200
-- ClkFrequency = 25000000
architecture from_verilog of async_transmitter is
signal BitTick : std_logic; -- Declared at async.v:36
signal TxD_ready : std_logic; -- Declared at async.v:41
signal TxD_shift : unsigned(7 downto 0) := X"00"; -- Declared at async.v:44
signal TxD_state : unsigned(3 downto 0) := X"0"; -- Declared at async.v:40
signal tmp_s0 : unsigned(31 downto 0); -- Temporary created at async.v:41
signal tmp_s10 : unsigned(31 downto 0); -- Temporary created at async.v:70
signal tmp_s13 : unsigned(27 downto 0); -- Temporary created at async.v:70
signal tmp_s14 : unsigned(31 downto 0); -- Temporary created at async.v:70
signal tmp_s16 : std_logic; -- Temporary created at async.v:70
signal tmp_s19 : std_logic; -- Temporary created at async.v:70
signal tmp_s21 : std_logic; -- Temporary created at async.v:70
signal tmp_s22 : std_logic; -- Temporary created at async.v:70
signal tmp_s3 : unsigned(27 downto 0); -- Temporary created at async.v:41
signal tmp_s4 : unsigned(31 downto 0); -- Temporary created at async.v:41
component BaudTickGen1 is
port (
clk : in std_logic;
enable : in std_logic;
tick : out std_logic
);
end component;
signal enable_Readable : std_logic; -- Needed to connect outputs
begin
TxD_busy <= not TxD_ready;
tmp_s22 <= tmp_s19 and tmp_s21;
TxD <= tmp_s16 or tmp_s22;
tmp_s0 <= tmp_s3 & TxD_state;
TxD_ready <= '1' when tmp_s0 = tmp_s4 else '0';
tmp_s10 <= tmp_s13 & TxD_state;
tmp_s16 <= '1' when tmp_s14 > tmp_s10 else '0';
tmp_s19 <= TxD_state(3);
tmp_s21 <= TxD_shift(0);
TxD_busy <= enable_Readable;
-- Generated from instantiation at async.v:37
tickgen: BaudTickGen1
port map (
clk => clk,
enable => enable_Readable,
tick => BitTick
);
tmp_s13 <= X"0000000";
tmp_s14 <= X"00000004";
tmp_s3 <= X"0000000";
tmp_s4 <= X"00000000";
-- Removed one empty process
-- Generated from always process in async_transmitter (async.v:45)
process (clk) is
begin
if rising_edge(clk) then
if (TxD_ready and TxD_start) = '1' then
TxD_shift <= TxD_data;
else
if (TxD_state(3) and BitTick) = '1' then
TxD_shift <= Resize(Resize(TxD_shift, 32) srl 1, 8);
end if;
end if;
case TxD_state is
when X"0" =>
if TxD_start = '1' then
TxD_state <= X"4";
end if;
when X"4" =>
if BitTick = '1' then
TxD_state <= X"8";
end if;
when X"8" =>
if BitTick = '1' then
TxD_state <= X"9";
end if;
when X"9" =>
if BitTick = '1' then
TxD_state <= X"a";
end if;
when X"a" =>
if BitTick = '1' then
TxD_state <= X"b";
end if;
when X"b" =>
if BitTick = '1' then
TxD_state <= X"c";
end if;
when X"c" =>
if BitTick = '1' then
TxD_state <= X"d";
end if;
when X"d" =>
if BitTick = '1' then
TxD_state <= X"e";
end if;
when X"e" =>
if BitTick = '1' then
TxD_state <= X"f";
end if;
when X"f" =>
if BitTick = '1' then
TxD_state <= X"2";
end if;
when X"2" =>
if BitTick = '1' then
TxD_state <= X"0";
end if;
when others =>
if BitTick = '1' then
TxD_state <= X"0";
end if;
end case;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Generated from Verilog module BaudTickGen (async.v:191)
-- AccWidth = 16
-- Baud = 115200
-- ClkFrequency = 25000000
-- Inc = 302
-- Oversampling = 1
-- ShiftLimiter = 2
entity BaudTickGen1 is
port (
clk : in std_logic;
enable : in std_logic;
tick : out std_logic
);
end entity;
-- Generated from Verilog module BaudTickGen (async.v:191)
-- AccWidth = 16
-- Baud = 115200
-- ClkFrequency = 25000000
-- Inc = 302
-- Oversampling = 1
-- ShiftLimiter = 2
architecture from_verilog of BaudTickGen1 is
signal Acc : unsigned(16 downto 0) := "00000000000000000"; -- Declared at async.v:201
begin
tick <= Acc(16);
-- Removed one empty process
-- Generated from always process in BaudTickGen (async.v:204)
process (clk) is
begin
if rising_edge(clk) then
if enable = '1' then
Acc <= Resize(Acc(0 + 15 downto 0), 17) + "00000000100101110";
else
Acc <= "00000000100101110";
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: <NAME> A01203712
--
-- Create Date: 09:22:39 09/15/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/Exam_SN74Ls42/SN74Ls42_TB.vhd
-- Project Name: Exam_SN74Ls42
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SN74Ls42
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SN74Ls42_TB IS
END SN74Ls42_TB;
ARCHITECTURE behavior OF SN74Ls42_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SN74Ls42
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
output : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal output : std_logic_vector(9 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SN74Ls42 PORT MAP (
A => A,
B => B,
C => C,
D => D,
output => output
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
D <= '0'; C <= '0'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '0'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '0'; C <= '0'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '0'; B <= '1'; A <= '1';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '1'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '1'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '1'; A <= '1';
wait for 100 ns;
wait;
end process;
END;
|
<filename>asynchronous_quadrature_decoder.vhd<gh_stars>1-10
-- asynchronous_quadrature_decoder - quadrature decoder without synchronizing clock input
-- Written in 2016 by <<NAME>> <<EMAIL>>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
-- prior debouncing of rotary input is unnecessary
entity asynchronous_quadrature_decoder is
port (
rotary : in std_logic_vector (1 downto 0);
direction : out std_logic;
pulse : out std_logic
);
end asynchronous_quadrature_decoder;
architecture gate_level of asynchronous_quadrature_decoder is
signal a, b, c, d, e, f : std_logic;
signal pul, pul_n, dir, dir_n : std_logic;
begin
a <= rotary(0);
b <= rotary(1);
c <= a and b;
d <= a nor b;
e <= a and not b;
f <= b and not a;
dir <= dir_n nor e;
dir_n <= dir nor f;
pul <= pul_n nor d;
pul_n <= pul nor c;
pulse <= pul;
direction <= dir;
end gate_level;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:12:12 01/20/2020
-- Design Name:
-- Module Name: multipexer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multipexer is
Port ( d0 : in STD_LOGIC;
d1 : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end multipexer;
architecture Structural of multipexer is
component and2gate port(
i1, i2: in std_logic;
o: out std_logic);
end component;
component or2gate port(
i1, i2: in std_logic;
o: out std_logic);
end component;
component notgate port(
i: in std_logic;
o: out std_logic);
end component;
signal sn, sd1, snd0: std_logic;
begin
u1: notgate port map(s, sn);
u2: and2gate port map(d0,sn, snd0);
u3: and2gate port map(s, d1, sd1);
u4: or2gate port map(snd0, sd1, y);
end Structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trafficlightsimulatorTB is
end entity;
architecture sim of trafficlightsimulatorTB is
constant ClockFrequencyHz : integer := 100; -- 100 Hz
constant ClockPeriod : time := 1000 ms / ClockFrequencyHz;
signal clock :std_logic := '1';
signal nRed :std_logic;
signal nYellow :std_logic;
signal nGreen :std_logic;
signal wRed :std_logic;
signal wYellow :std_logic;
signal wGreen :std_logic;
signal nPathWayRed :std_logic;
signal nPathWayGreen:std_logic;
signal wPathWayRed :std_logic;
signal wPathWayGreen:std_logic;
begin
i_TrafficLights : entity work.trafficlightsimulator(rtl)
generic map(ClockFrequencyHz => ClockFrequencyHz)
port map (
clock => clock,
nRed => nRed,
nYellow => nYellow,
nGreen => nGreen,
wRed => wRed,
wYellow => wYellow,
wGreen => wGreen,
wPathWayRed => wPathWayRed,
wPathWayGreen => wPathWayGreen,
nPathWayRed => nPathWayRed,
nPathWayGreen => nPathWayGreen);
clock <= not clock after ClockPeriod / 2;
-- Testbench sequence
process is
begin
wait until rising_edge(clock);
wait until rising_edge(clock);
wait;
end process;
end architecture;
|
<reponame>rahmant3/polymath-iot
library IEEE;
use IEEE.std_logic_1164.all;
entity RAM8K_2X1_CELL_MACRO is
Port ( A1_0 : In STD_LOGIC_VECTOR (10 downto 0);
A1_1 : In STD_LOGIC_VECTOR (10 downto 0);
A2_0 : In STD_LOGIC_VECTOR (10 downto 0);
A2_1 : In STD_LOGIC_VECTOR (10 downto 0);
ASYNC_FLUSH_0 : In STD_LOGIC;
ASYNC_FLUSH_1 : In STD_LOGIC;
ASYNC_FLUSH_S0,ASYNC_FLUSH_S1:in std_logic;
CLK1_0 : In STD_LOGIC;
CLK1_1 : In STD_LOGIC;
CLK1EN_0 : In STD_LOGIC;
CLK1EN_1 : In STD_LOGIC;
CLK2_0 : In STD_LOGIC;
CLK2_1 : In STD_LOGIC;
CLK2EN_0 : In STD_LOGIC;
CLK2EN_1 : In STD_LOGIC;
CLK1S_0 : In STD_LOGIC;
CLK1S_1 : In STD_LOGIC;
CLK2S_0 : In STD_LOGIC;
CLK2S_1 : In STD_LOGIC;
CONCAT_EN_0 : In STD_LOGIC;
CONCAT_EN_1 : In STD_LOGIC;
CS1_0 : In STD_LOGIC;
CS1_1 : In STD_LOGIC;
CS2_0 : In STD_LOGIC;
CS2_1 : In STD_LOGIC;
DIR_0 : In STD_LOGIC;
DIR_1 : In STD_LOGIC;
FIFO_EN_0 : In STD_LOGIC;
FIFO_EN_1 : In STD_LOGIC;
PIPELINE_RD_0 : In STD_LOGIC;
PIPELINE_RD_1 : In STD_LOGIC;
P1_0 : In STD_LOGIC;
P1_1 : In STD_LOGIC;
P2_0 : In STD_LOGIC;
P2_1 : In STD_LOGIC;
SYNC_FIFO_0 : In STD_LOGIC;
SYNC_FIFO_1 : In STD_LOGIC;
WD_0 : In STD_LOGIC_VECTOR (17 downto 0);
WD_1 : In STD_LOGIC_VECTOR (17 downto 0);
WEN1_0 : In STD_LOGIC_VECTOR (1 downto 0);
WEN1_1 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT1_0 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT1_1 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT2_0 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT2_1 : In STD_LOGIC_VECTOR (1 downto 0);
Almost_Empty_0 : Out STD_LOGIC;
Almost_Empty_1 : Out STD_LOGIC;
Almost_Full_0 : Out STD_LOGIC;
Almost_Full_1 : Out STD_LOGIC;
POP_FLAG_0 : Out STD_LOGIC_VECTOR (3 downto 0);
POP_FLAG_1 : Out STD_LOGIC_VECTOR (3 downto 0);
PUSH_FLAG_0 : Out STD_LOGIC_VECTOR (3 downto 0);
PUSH_FLAG_1 : Out STD_LOGIC_VECTOR (3 downto 0);
RD_0 : Out STD_LOGIC_VECTOR (17 downto 0);
RD_1 : Out STD_LOGIC_VECTOR (17 downto 0) );
attribute syn_isclock: boolean;
attribute syn_isclock of CLK1_0: signal is true;
attribute syn_isclock of CLK1_1: signal is true;
attribute syn_isclock of CLK2_0: signal is true;
attribute syn_isclock of CLK2_1: signal is true;
attribute BLACK_BOX : boolean;
attribute BLACK_BOX of RAM8K_2X1_CELL_MACRO : entity is true;
end RAM8K_2X1_CELL_MACRO;
architecture SCHEMATIC of RAM8K_2X1_CELL_MACRO is
signal Almost_Empty_0_DUMMY : STD_LOGIC;
signal Almost_Empty_1_DUMMY : STD_LOGIC;
signal Almost_Full_0_DUMMY : STD_LOGIC;
signal Almost_Full_1_DUMMY : STD_LOGIC;
signal POP_FLAG_0_DUMMY : STD_LOGIC_VECTOR (3 downto 0);
signal POP_FLAG_1_DUMMY : STD_LOGIC_VECTOR (3 downto 0);
signal PUSH_FLAG_0_DUMMY : STD_LOGIC_VECTOR (3 downto 0);
signal PUSH_FLAG_1_DUMMY : STD_LOGIC_VECTOR (3 downto 0);
signal RD_0_DUMMY : STD_LOGIC_VECTOR (17 downto 0);
signal RD_1_DUMMY : STD_LOGIC_VECTOR (17 downto 0);
component RAM8K_2X1_CELL
Port ( A1_0 : In STD_LOGIC_VECTOR (10 downto 0);
A1_1 : In STD_LOGIC_VECTOR (10 downto 0);
A2_0 : In STD_LOGIC_VECTOR (10 downto 0);
A2_1 : In STD_LOGIC_VECTOR (10 downto 0);
ASYNC_FLUSH_0 : In STD_LOGIC;
ASYNC_FLUSH_1 : In STD_LOGIC;
ASYNC_FLUSH_S0 ,ASYNC_FLUSH_S1:in std_logic;
CLK1_0 : In STD_LOGIC;
CLK1_1 : In STD_LOGIC;
CLK1EN_0 : In STD_LOGIC;
CLK1EN_1 : In STD_LOGIC;
CLK2_0 : In STD_LOGIC;
CLK2_1 : In STD_LOGIC;
CLK2EN_0 : In STD_LOGIC;
CLK2EN_1 : In STD_LOGIC;
CLK1S_0 : In STD_LOGIC;
CLK1S_1 : In STD_LOGIC;
CLK2S_0 : In STD_LOGIC;
CLK2S_1 : In STD_LOGIC;
CONCAT_EN_0 : In STD_LOGIC;
CONCAT_EN_1 : In STD_LOGIC;
CS1_0 : In STD_LOGIC;
CS1_1 : In STD_LOGIC;
CS2_0 : In STD_LOGIC;
CS2_1 : In STD_LOGIC;
DIR_0 : in STD_LOGIC;
DIR_1 : in STD_LOGIC;
FIFO_EN_0 : In STD_LOGIC;
FIFO_EN_1 : In STD_LOGIC;
PIPELINE_RD_0 : In STD_LOGIC;
PIPELINE_RD_1 : In STD_LOGIC;
P1_0 : In STD_LOGIC;
P1_1 : In STD_LOGIC;
P2_0 : In STD_LOGIC;
P2_1 : In STD_LOGIC;
SYNC_FIFO_0 : In STD_LOGIC;
SYNC_FIFO_1 : In STD_LOGIC;
WD_0 : In STD_LOGIC_VECTOR (17 downto 0);
WD_1 : In STD_LOGIC_VECTOR (17 downto 0);
WEN1_0 : In STD_LOGIC_VECTOR (1 downto 0);
WEN1_1 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT1_0 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT1_1 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT2_0 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT2_1 : In STD_LOGIC_VECTOR (1 downto 0);
Almost_Empty_0 : Out STD_LOGIC;
Almost_Empty_1 : Out STD_LOGIC;
Almost_Full_0 : Out STD_LOGIC;
Almost_Full_1 : Out STD_LOGIC;
POP_FLAG_0 : Out STD_LOGIC_VECTOR (3 downto 0);
POP_FLAG_1 : Out STD_LOGIC_VECTOR (3 downto 0);
PUSH_FLAG_0 : Out STD_LOGIC_VECTOR (3 downto 0);
PUSH_FLAG_1 : Out STD_LOGIC_VECTOR (3 downto 0);
RD_0 : Out STD_LOGIC_VECTOR (17 downto 0);
RD_1 : Out STD_LOGIC_VECTOR (17 downto 0) );
end component;
begin
Almost_Empty_0 <= Almost_Empty_0_DUMMY;
Almost_Empty_1 <= Almost_Empty_1_DUMMY;
Almost_Full_0 <= Almost_Full_0_DUMMY;
Almost_Full_1 <= Almost_Full_1_DUMMY;
POP_FLAG_0(3 downto 0) <= POP_FLAG_0_DUMMY(3 downto 0);
POP_FLAG_1(3 downto 0) <= POP_FLAG_1_DUMMY(3 downto 0);
PUSH_FLAG_0(3 downto 0) <= PUSH_FLAG_0_DUMMY(3 downto 0);
PUSH_FLAG_1(3 downto 0) <= PUSH_FLAG_1_DUMMY(3 downto 0);
RD_0(17 downto 0) <= RD_0_DUMMY(17 downto 0);
RD_1(17 downto 0) <= RD_1_DUMMY(17 downto 0);
I1 : RAM8K_2X1_CELL
Port Map ( A1_0(10 downto 0)=>A1_0(10 downto 0),
A1_1(10 downto 0)=>A1_1(10 downto 0),
A2_0(10 downto 0)=>A2_0(10 downto 0),
A2_1(10 downto 0)=>A2_1(10 downto 0),
ASYNC_FLUSH_0=>ASYNC_FLUSH_0,
ASYNC_FLUSH_1=>ASYNC_FLUSH_1,
ASYNC_FLUSH_S0=>ASYNC_FLUSH_S0 ,
ASYNC_FLUSH_S1=>ASYNC_FLUSH_S1,
CLK1_0=>CLK1_0,
CLK1_1=>CLK1_1, CLK2_0=>CLK2_0, CLK2_1=>CLK2_1,
CLK1S_0=>CLK1S_0, CLK1S_1=>CLK1S_1, CLK2S_0=>CLK2S_0, CLK2S_1=>CLK2S_1,
CONCAT_EN_0=>CONCAT_EN_0, CONCAT_EN_1=>CONCAT_EN_1, CLK2EN_0=>CLK2EN_0,
CLK2EN_1=>CLK2EN_1,CLK1EN_0=>CLK1EN_0, CLK1EN_1=>CLK1EN_1,
CS1_0=>CS1_0, CS1_1=>CS1_1, CS2_0=>CS2_0, CS2_1=>CS2_1,
FIFO_EN_0=>FIFO_EN_0, FIFO_EN_1=>FIFO_EN_1,
PIPELINE_RD_0=>PIPELINE_RD_0,
PIPELINE_RD_1=>PIPELINE_RD_1, P1_0=>P1_0,
DIR_0 => DIR_0, DIR_1=> DIR_1,
P1_1=>P1_1, P2_0=>P2_0,
P2_1=>P2_1, SYNC_FIFO_0=>SYNC_FIFO_0,
SYNC_FIFO_1=>SYNC_FIFO_1,
WD_0(17 downto 0)=>WD_0(17 downto 0),
WD_1(17 downto 0)=>WD_1(17 downto 0),
WEN1_0(1 downto 0)=>WEN1_0(1 downto 0),
WEN1_1(1 downto 0)=>WEN1_1(1 downto 0),
WIDTH_SELECT1_0(1 downto 0)=>WIDTH_SELECT1_0(1 downto 0),
WIDTH_SELECT1_1(1 downto 0)=>WIDTH_SELECT1_1(1 downto 0),
WIDTH_SELECT2_0(1 downto 0)=>WIDTH_SELECT2_0(1 downto 0),
WIDTH_SELECT2_1(1 downto 0)=>WIDTH_SELECT2_1(1 downto 0),
Almost_Empty_0=>Almost_Empty_0_DUMMY,
Almost_Empty_1=>Almost_Empty_1_DUMMY,
Almost_Full_0=>Almost_Full_0_DUMMY,
Almost_Full_1=>Almost_Full_1_DUMMY,
POP_FLAG_0(3 downto 0)=>POP_FLAG_0_DUMMY(3 downto 0),
POP_FLAG_1(3 downto 0)=>POP_FLAG_1_DUMMY(3 downto 0),
PUSH_FLAG_0(3 downto 0)=>PUSH_FLAG_0_DUMMY(3 downto 0),
PUSH_FLAG_1(3 downto 0)=>PUSH_FLAG_1_DUMMY(3 downto 0),
RD_0(17 downto 0)=>RD_0_DUMMY(17 downto 0),
RD_1(17 downto 0)=>RD_1_DUMMY(17 downto 0) );
end SCHEMATIC;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM_RW is
generic(wr_addr_int :integer := 9;
rd_addr_int :integer := 8;
wr_depth_int :integer := 1024;
rd_depth_int :integer := 512;
wr_width_int :integer := 9;
rd_width_int :integer := 18;
reg_rd_int : integer :=0;
wr_enable_int:integer:=1;
device_8k_int :integer := 1);
port (WA : in std_logic_vector (wr_addr_int-1 downto 0);
RA:in std_logic_vector(rd_addr_int-1 downto 0);
WD : in std_logic_vector( wr_width_int-1 downto 0);
WD_SEL,RD_SEL:in std_logic;
WEN:std_logic_vector(wr_enable_int-1 downto 0);
WClk,RClk: in std_logic;
WClk_En,RClk_En: in std_logic;
WClk_Sel,RClk_Sel: in std_logic;
RD : out std_logic_vector(rd_width_int-1 downto 0) );
attribute syn_isclock: boolean;
attribute syn_isclock of WClk: signal is true;
attribute syn_isclock of RClk: signal is true;
end RAM_RW;
Architecture arch of RAM_RW is
attribute noopt:boolean;
component RAM8K_2X1_CELL_MACRO
Port ( A1_0 : In STD_LOGIC_VECTOR (10 downto 0);
A1_1 : In STD_LOGIC_VECTOR (10 downto 0);
A2_0 : In STD_LOGIC_VECTOR (10 downto 0);
A2_1 : In STD_LOGIC_VECTOR (10 downto 0);
ASYNC_FLUSH_0 : In STD_LOGIC;
ASYNC_FLUSH_1 : In STD_LOGIC;
ASYNC_FLUSH_S0,ASYNC_FLUSH_S1:in std_logic;
CLK1_0 : In STD_LOGIC;
CLK1_1 : In STD_LOGIC;
CLK1EN_0 : In STD_LOGIC;
CLK1EN_1 : In STD_LOGIC;
CLK2_0 : In STD_LOGIC;
CLK2_1 : In STD_LOGIC;
CLK2EN_0 : In STD_LOGIC;
CLK2EN_1 : In STD_LOGIC;
CLK1S_0 : In STD_LOGIC;
CLK1S_1 : In STD_LOGIC;
CLK2S_0 : In STD_LOGIC;
CLK2S_1 : In STD_LOGIC;
CONCAT_EN_0 : In STD_LOGIC;
CONCAT_EN_1 : In STD_LOGIC;
CS1_0 : In STD_LOGIC;
CS1_1 : In STD_LOGIC;
CS2_0 : In STD_LOGIC;
CS2_1 : In STD_LOGIC;
DIR_0 : In STD_LOGIC;
DIR_1 : In STD_LOGIC;
FIFO_EN_0 : In STD_LOGIC;
FIFO_EN_1 : In STD_LOGIC;
PIPELINE_RD_0 : In STD_LOGIC;
PIPELINE_RD_1 : In STD_LOGIC;
P1_0 : In STD_LOGIC;
P1_1 : In STD_LOGIC;
P2_0 : In STD_LOGIC;
P2_1 : In STD_LOGIC;
SYNC_FIFO_0 : In STD_LOGIC;
SYNC_FIFO_1 : In STD_LOGIC;
WD_0 : In STD_LOGIC_VECTOR (17 downto 0);
WD_1 : In STD_LOGIC_VECTOR (17 downto 0);
WEN1_0 : In STD_LOGIC_VECTOR (1 downto 0);
WEN1_1 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT1_0 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT1_1 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT2_0 : In STD_LOGIC_VECTOR (1 downto 0);
WIDTH_SELECT2_1 : In STD_LOGIC_VECTOR (1 downto 0);
Almost_Empty_0 : Out STD_LOGIC;
Almost_Empty_1 : Out STD_LOGIC;
Almost_Full_0 : Out STD_LOGIC;
Almost_Full_1 : Out STD_LOGIC;
POP_FLAG_0 : Out STD_LOGIC_VECTOR (3 downto 0);
POP_FLAG_1 : Out STD_LOGIC_VECTOR (3 downto 0);
PUSH_FLAG_0 : Out STD_LOGIC_VECTOR (3 downto 0);
PUSH_FLAG_1 : Out STD_LOGIC_VECTOR (3 downto 0);
RD_0 : Out STD_LOGIC_VECTOR (17 downto 0);
RD_1 : Out STD_LOGIC_VECTOR (17 downto 0) );
end component;
constant mod2 :integer :=(wr_width_int) mod 2;
constant mod4 : integer :=(wr_width_int) mod 4;
constant zero_36_2 :integer := (36-wr_width_int) / 2;
constant zero_36_2_odd : integer :=(36-wr_width_int+1)/2;
constant zero_18_2_odd:integer := (18-wr_width_int+1)/2;
constant zero_36_4_1:integer :=(36-wr_width_int+1)/4;
constant zero_36_4_2 :integer :=(36-wr_width_int+2)/4;
constant zero_36_4_3 :integer :=(36-wr_width_int+3)/4;
constant zero_36_4 :integer := (36- wr_width_int) /4 ;
constant zero_18_2:integer :=(18-wr_width_int)/2;
constant by_2 :integer := (wr_width_int)/2;
constant by_4 :integer := (wr_width_int)/4;
constant by_4_2:integer := (wr_width_int/4)*2;
constant by_4_3:integer :=(wr_width_int/4)*3;
constant zero_18_2_rg :integer := 18-wr_width_int;
constant zero_9_2_rg :integer := 9-wr_width_int;
constant by_2_read :integer := (rd_width_int)/2;
constant by_4_read :integer := (rd_width_int)/4;
constant by_4_readx2 :integer :=(rd_width_int/4)*2;
constant by_4_readx3 :integer :=(rd_width_int/4)*3;
Signal VCC,GND :std_logic;
Signal WS1,WS2,WS_GND,WEN2,WEN1:std_logic_vector(1 downto 0);
signal addr_wr0,addr_rd0,addr_wr1,addr_rd1: std_logic_vector(10 downto 0);
signal in_reg :std_logic_vector(36 downto 0);
signal out_reg: std_logic_vector(36 downto 0);
signal wen_reg:std_logic_vector( 3 downto 0);
signal reg_rd : std_logic;
begin
VCC <='1';
GND<='0';
reg_rd <= '0' when reg_rd_int=0 else '1';
WS_GND<="00";
wen_reg(3 downto wr_enable_int)<=(others=>'0');
wen_reg(wr_enable_int-1 downto 0)<=WEN;
U1:if((wr_width_int =36 or wr_width_int = 18 or wr_width_int =9) or (wr_width_int = rd_width_int))generate
in_reg(35 downto wr_width_int)<=(others=>'0');
in_reg(wr_width_int-1 downto 0)<=WD;
end generate U1;
U2: if(wr_depth_int = 512) generate
U3:if(rd_depth_int = 1024)generate
U7:if(wr_width_int > 18)generate
U8:if(mod2 = 0)generate
in_reg(17 downto 18-zero_36_2)<=(others=>'0');
in_reg(35 downto 36-zero_36_2)<=(others=>'0');
in_reg(18-zero_36_2-1 downto 0)<=WD(by_2-1 downto 0);
in_reg(36-zero_36_2-1 downto 18)<=WD(wr_width_int-1 downto by_2);
end generate U8;
U9:if(mod2 /= 0)generate
in_reg(35 downto wr_width_int)<=(others=>'0');
in_reg(wr_width_int-1 downto 0)<=WD;
end generate U9;
end generate U7;
U10:if(wr_width_int <= 18) generate
U11: if(mod2 = 0)generate
in_reg(8 downto 9-zero_18_2)<=(others=>'0');
in_reg(17 downto 18-zero_18_2)<=(others=>'0');
in_reg(9-zero_18_2-1 downto 0)<=WD(by_2-1 downto 0);
in_reg(18-zero_18_2-1 downto 9) <= WD(wr_width_int-1 downto by_2);
end generate U11;
U12: if(mod2 /= 0)generate
in_reg(35 downto wr_width_int)<=(others=>'0');
in_reg(wr_width_int-1 downto 0)<=WD;
end generate U12;
end generate U10;
end generate U3;
U13: if(rd_depth_int = 2048)generate
U14:if(mod4=0)generate
in_reg(35 downto 36-zero_36_4)<=(others=>'0');
in_reg(26 downto 27-zero_36_4)<=(others=>'0');
in_reg(17 downto 18-zero_36_4)<=(others=>'0');
in_reg(8 downto 9-zero_36_4)<=(others=>'0');
in_reg(36-zero_36_4-1 downto 27)<=WD(wr_width_int-1 downto by_4_3);
in_reg(27-zero_36_4-1 downto 18)<=WD(by_4_3-1 downto by_4_2);
in_reg(18-zero_36_4-1 downto 9)<=WD(by_4_2-1 downto by_4);
in_reg(9-zero_36_4-1 downto 0)<=WD(by_4-1 downto 0);
end generate U14;
U15:if(mod4 /= 0)generate
in_reg(35 downto wr_width_int)<=(others=>'0');
in_reg(wr_width_int-1 downto 0)<=WD;
end generate U15;
end generate U13;
end generate U2;
U16: if(wr_depth_int = 1024)generate
U17:if(rd_depth_int = 2048)generate
U18:if(mod2=0)generate
in_reg(8 downto 9-zero_18_2)<=(others=>'0');
in_reg(17 downto 18-zero_18_2)<=(others=>'0');
in_reg(9-zero_18_2-1 downto 0)<=WD(by_2-1 downto 0);
in_reg(18-zero_18_2-1 downto 9)<=WD(wr_width_int-1 downto by_2);
end generate U18;
U19:if(mod2 /= 0)generate
in_reg(35 downto wr_width_int)<=(others=>'0');
in_reg(wr_width_int-1 downto 0)<=WD;
end generate U19;
end generate U17;
U18: if(rd_depth_int=512)generate
in_reg(35 downto wr_width_int)<=(others=>'0');
in_reg(wr_width_int-1 downto 0)<=WD;
end generate U18;
end generate U16;
U19: if(wr_depth_int= 2048) generate
in_reg(35 downto wr_width_int)<=(others=>'0');
in_reg(wr_width_int-1 downto 0)<=WD;
end generate U19;
---Generating widht selects
U20: if(rd_depth_int = 2048 and wr_depth_int = 512) generate
WS1<="10";
end generate U20;
U21: if(rd_depth_int = 2048 and wr_depth_int=1024) generate
WS1<="01";
end generate U21;
U22: if(wr_depth_int =512 and wr_width_int <=18 and rd_depth_int/=2048) generate
WS1<="01";
end generate U22;
U23: if((wr_width_int <= 9 and wr_depth_int /=512) or (wr_depth_int=1024 and rd_depth_int /=2048 and wr_width_int <=9)) generate
WS1<="00";
end generate U23;
U24:if((wr_width_int >9 and wr_width_int<=18)or (wr_depth_int =512 and rd_depth_int /= 2048 and wr_width_int<=18)) generate
WS1<="01";
end generate U24;
U25:if(wr_width_int >18) generate
WS1<="10";
end generate U25;
U26: if(wr_depth_int=2048 and rd_depth_int=512) generate
WS2<= "10";
end generate U26;
U27: if(wr_depth_int = 2048 and rd_depth_int = 1024)generate
WS2<="01";
end generate U27;
U28: if(rd_depth_int =512 and rd_width_int <=18 and wr_depth_int /= 2048) generate
WS2<="01";
end generate U28;
U29:if((rd_width_int <=9 and rd_depth_int /= 512 ) or (rd_depth_int =1024 and wr_depth_int /=2048 and rd_width_int <=9))generate
WS2<="00";
End generate U29;
U30: if((rd_width_int>9 and rd_width_int <=18 ) or (rd_depth_int = 512 and wr_depth_int /=2048 and rd_width_int <=18) )generate
WS2<="01";
End generate U30;
U31: if(rd_width_int >18)generate
WS2<= "10";
end generate U31;
---Generating write address
U32:if(wr_addr_int = 11) generate
addr_wr0(10 downto 0)<= WA;
end generate U32;
U33: if(wr_addr_int <11) generate
addr_wr0(10 downto wr_addr_int)<=(others=>'0');
addr_wr0(wr_addr_int-1 downto 0)<=WA;
end generate U33;
addr_wr1<=(others=>'0');
---Generating read address
U34:if(rd_addr_int = 11) generate
addr_rd0(10 downto 0)<=RA;
end generate U34;
U60:if(rd_addr_int < 11) generate
addr_rd0(10 downto rd_addr_int)<=(others=>'0');
addr_rd0(rd_addr_int-1 downto 0)<=RA;
end generate U60;
addr_rd1<=(others=>'0');
U35: if((((wr_width_int<= 18) and (wr_depth_int=512)) or ((wr_width_int<=9) and (wr_depth_int=1024))) and (rd_depth_int /=2048)) generate
DRAM8k : RAM8K_2X1_CELL_MACRO
port map( CLK1_0=>WClk,
CLK2_0=>RClk,
CLK1EN_0=>WClk_En,
CLK2EN_0=>RClk_En,
CLK1EN_1=>GND,
CLK2EN_1=>GND,
CLK1S_0=>WClk_Sel,
CLK2S_0=>RClk_Sel,
WD_0=>in_reg(17 downto 0),
RD_0 => out_reg(17 downto 0),
A1_0(10 downto 0)=>addr_wr0,
A2_0(10 downto 0)=>addr_rd0,
CS1_0=>WD_SEL,
CS2_0=>RD_SEL,
WEN1_0=>wen_reg(1 downto 0),
ASYNC_FLUSH_0=>GND,
P1_0=>GND,
P2_0=>GND,
ALMOST_FULL_0=>open,
ALMOST_EMPTY_0=>open,
PUSH_FLAG_0=>open,
POP_FLAG_0=>open,
FIFO_EN_0=>GND,
SYNC_FIFO_0=>GND,
DIR_0=>GND,
DIR_1=>GND,
PIPELINE_RD_0=>reg_rd,
WIDTH_SELECT1_0=>WS1,
WIDTH_SELECT2_0=>WS2,
ASYNC_FLUSH_1 => GND,
ASYNC_FLUSH_S0=>GND,
ASYNC_FLUSH_S1=>GND,
Clk1_1=>GND,
CLK2_1=>GND,
CLK1S_1=>VCC,
CLK2S_1=>VCC,
WD_1=>in_reg(35 downto 18),
RD_1=>out_reg(35 downto 18),
A1_1(10 downto 0)=>addr_wr1,
A2_1(10 downto 0)=>addr_rd1,
CS1_1=>GND,
CS2_1=>GND,
WEN1_1=>wen_reg(3 downto 2),
P1_1=>GND,
P2_1=>GND,
ALMOST_FULL_1=>open,
ALMOST_EMPTY_1=>open,
PUSH_FLAG_1=>open,
POP_FLAG_1=>open,
FIFO_EN_1 => GND,
SYNC_FIFO_1=>GND,
PIPELINE_RD_1=>reg_rd,
WIDTH_SELECT1_1=>WS_GND,
WIDTH_SELECT2_1=>WS_GND,
CONCAT_EN_0 =>GND,
CONCAT_EN_1 => GND
);
end generate U35;
U36: if( (wr_width_int > 18 and wr_depth_int=512) or (wr_width_int > 9 and wr_depth_int=1024)or wr_depth_int > 1024 or rd_depth_int =2048 ) generate
DRAM16k : RAM8K_2X1_CELL_MACRO
port map( CLK1_0=>WClk,
CLK2_0=>RClk,
CLK1S_0=>WClk_Sel,
CLK2S_0=>RClk_Sel,
CLK1EN_0=>WClk_En,
CLK2EN_0=>RClk_En,
CLK1EN_1=>GND,
CLK2EN_1=>GND,
WD_0=>in_reg(17 downto 0),
RD_0 => out_reg(17 downto 0),
A1_0(10 downto 0)=>addr_wr0,
A2_0(10 downto 0)=>addr_rd0,
CS1_0=>WD_SEL,
CS2_0=>RD_SEL,
WEN1_0=>wen_reg(1 downto 0),
ASYNC_FLUSH_0=>GND,
ASYNC_FLUSH_1 => GND,
ASYNC_FLUSH_S0=>GND,ASYNC_FLUSH_S1=>GND,
P1_0=>GND,
P2_0=>GND,
ALMOST_FULL_0=>open,
ALMOST_EMPTY_0=>open,
PUSH_FLAG_0=>open,
POP_FLAG_0=>open,
FIFO_EN_0=>GND,
SYNC_FIFO_0=>GND,
DIR_0=>GND,
DIR_1=>GND,
PIPELINE_RD_0=>reg_rd,
WIDTH_SELECT1_0=>WS1,
WIDTH_SELECT2_0=>WS2,
Clk1_1=>WClk,
CLK2_1=>RClk,
CLK1S_1=>WClk_Sel,
CLK2S_1=>RClk_Sel,
WD_1=>in_reg(35 downto 18),
RD_1=>out_reg(35 downto 18),
A1_1(10 downto 0)=>addr_wr1,
A2_1(10 downto 0)=>addr_rd1,
CS1_1=>GND,
CS2_1=>GND,
WEN1_1=>wen_reg(3 downto 2),
P1_1=>GND,
P2_1=>GND,
ALMOST_FULL_1=>open,
ALMOST_EMPTY_1=>open,
PUSH_FLAG_1=>open,
POP_FLAG_1=>open,
FIFO_EN_1 => GND,
SYNC_FIFO_1=>GND,
PIPELINE_RD_1=>reg_rd,
WIDTH_SELECT1_1=>WS_GND,
WIDTH_SELECT2_1=>WS_GND,
CONCAT_EN_0 => VCC,
CONCAT_EN_1 => GND
);
end generate U36;
U37: if (wr_width_int = rd_width_int ) generate
RD<=out_reg(rd_width_int-1 downto 0);
end generate U37;
U38: if((wr_depth_int = 1024 and wr_width_int >9) and (wr_width_int/=rd_width_int)) generate
U39: if(rd_width_int >18) generate
RD(rd_width_int-1 downto by_2_read)<=out_reg(35-zero_18_2_rg downto 18);
RD(by_2_read-1 downto 0)<= out_reg(17-zero_18_2_rg downto 0);
end generate U39;
U40:if(rd_width_int <=9) generate
RD(rd_width_int-1 downto 0)<=out_reg(rd_width_int-1 downto 0);
end generate U40;
U41: if(rd_width_int <18 and rd_width_int >9) generate
RD(rd_width_int-1 downto by_2_read) <= out_reg(17-zero_9_2_rg downto 9);
RD(by_2_read-1 downto 0)<=out_reg(8-zero_9_2_rg downto 0);
end generate U41;
end generate U38;
U42 :if(wr_depth_int =1024 and wr_width_int <=9 and rd_width_int /= wr_width_int) generate
RD(rd_width_int-1 downto by_2_read) <= out_reg(17-zero_9_2_rg downto 9);
RD(by_2_read-1 downto 0)<=out_reg(8-zero_9_2_rg downto 0);
end generate U42;
U43: if(wr_depth_int = 2048) generate
U44:if(rd_depth_int = 512) generate
RD(rd_width_int-1 downto by_4_readx3 )<= out_reg(35-zero_9_2_rg downto 27);
RD(by_4_readx3-1 downto by_4_readx2)<=out_reg(26-zero_9_2_rg downto 18);
RD(by_4_readx2-1 downto by_4_read)<=out_reg(17-zero_9_2_rg downto 9);
RD(by_4_read-1 downto 0)<=out_reg(8-zero_9_2_rg downto 0);
end generate U44;
U45: if(rd_depth_int = 1024) generate
RD(rd_width_int-1 downto by_2_read) <= out_reg(17-zero_9_2_rg downto 9);
RD(by_2_read-1 downto 0)<=out_reg(8-zero_9_2_rg downto 0);
end generate U45;
end generate U43;
U46: if(wr_depth_int = 512) generate
RD(rd_width_int-1 downto 0) <= out_reg(rd_width_int-1 downto 0);
end generate U46;
end arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY uart_rx_tb IS
END uart_rx_tb;
ARCHITECTURE behave OF uart_rx_tb IS
COMPONENT uart_rx IS
GENERIC (
g_CLKS_PER_BIT : INTEGER := 115 -- Needs to be set correctly
);
PORT (
i_clk : IN STD_LOGIC;
i_rx_line : IN STD_LOGIC;
o_rx_data_valid : OUT STD_LOGIC;
o_rx_byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT uart_rx;
-- Test Bench uses a 10 MHz Clock
-- Want to interface to 115200 baud UART
-- 10000000 / 115200 = 87 Clocks Per Bit.
CONSTANT c_CLKS_PER_BIT : INTEGER := 87;
CONSTANT c_BIT_PERIOD : TIME := 8680 ns;
SIGNAL r_CLOCK : STD_LOGIC := '0';
SIGNAL w_RX_DV : STD_LOGIC;
SIGNAL w_RX_BYTE : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_RX_SERIAL : STD_LOGIC := '1';
-- Low-level byte-write
PROCEDURE UART_WRITE_BYTE (
i_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL o_serial : OUT STD_LOGIC) IS
BEGIN
-- Send Start Bit
o_serial <= '0';
WAIT FOR c_BIT_PERIOD;
-- Send Data Byte
FOR ii IN 0 TO 7 LOOP
o_serial <= i_data_in(ii);
WAIT FOR c_BIT_PERIOD;
END LOOP; -- ii
-- Send Stop Bit
o_serial <= '1';
WAIT FOR c_BIT_PERIOD;
END UART_WRITE_BYTE;
BEGIN
-- Instantiate UART Receiver
UART_RX_INST : uart_rx
GENERIC MAP(
g_CLKS_PER_BIT => c_CLKS_PER_BIT
)
PORT MAP(
i_clk => r_CLOCK,
i_rx_line => r_RX_SERIAL,
o_rx_data_valid => w_RX_DV,
o_rx_byte => w_RX_BYTE
);
r_CLOCK <= NOT r_CLOCK AFTER 50 ns;
PROCESS IS
BEGIN
-- Send a command to the UART
WAIT UNTIL rising_edge(r_CLOCK);
UART_WRITE_BYTE(X"ad", r_RX_SERIAL);
WAIT UNTIL rising_edge(r_CLOCK);
-- Check that the correct command was received
IF w_RX_BYTE = X"ad" THEN
REPORT "Test Passed - Correct Byte Received" SEVERITY note;
ELSE
REPORT "Test Failed - Incorrect Byte Received" SEVERITY note;
END IF;
ASSERT false REPORT "Tests Complete" SEVERITY failure;
END PROCESS;
END behave;
|
<filename>labs/semester_project/semester_project/project_original/project_orig/project_orig.srcs/sources_1/new/pwm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
entity pwm02 is
Port ( clk : in STD_LOGIC;
duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm : out STD_LOGIC;
pwm_i : out STD_LOGIC
);
end pwm02;
architecture Behavioral02 of pwm02 is
signal counter : std_logic_vector (7 downto 0) := "00000000"; --initialize to 0
signal duty_sig : std_logic_vector (7 downto 0) := "00000000";
begin
process(clk)
begin
if rising_edge(clk) then
counter <= counter + 1;
end if;
if counter = 0 then
duty_sig <= duty;
end if;
end process;
pwm <= '1' when counter <= duty_sig else '0';
pwm_i <= '1' when counter < duty_sig else '0';
end Behavioral02;
|
<reponame>itepifanio/vhdl
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
-- DATE "11/09/2019 12:32:02"
--
-- Device: Altera 5CGXFC7C7F23C8 Package FBGA484
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY ALTERA;
LIBRARY ALTERA_LNSIM;
LIBRARY CYCLONEV;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE ALTERA_LNSIM.ALTERA_LNSIM_COMPONENTS.ALL;
USE CYCLONEV.CYCLONEV_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY exercicio2 IS
PORT (
clk : IN std_logic;
c : IN std_logic;
s : IN std_logic_vector(7 DOWNTO 0);
a : IN std_logic_vector(7 DOWNTO 0);
d : OUT std_logic;
troco : OUT std_logic
);
END exercicio2;
-- Design Ports Information
-- d => Location: PIN_P16, I/O Standard: 2.5 V, Current Strength: Default
-- troco => Location: PIN_N16, I/O Standard: 2.5 V, Current Strength: Default
-- s[4] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
-- s[7] => Location: PIN_L17, I/O Standard: 2.5 V, Current Strength: Default
-- s[6] => Location: PIN_M20, I/O Standard: 2.5 V, Current Strength: Default
-- s[5] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default
-- s[3] => Location: PIN_K17, I/O Standard: 2.5 V, Current Strength: Default
-- s[2] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default
-- s[1] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default
-- s[0] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default
-- c => Location: PIN_M18, I/O Standard: 2.5 V, Current Strength: Default
-- clk => Location: PIN_M16, I/O Standard: 2.5 V, Current Strength: Default
-- a[4] => Location: PIN_B20, I/O Standard: 2.5 V, Current Strength: Default
-- a[7] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default
-- a[6] => Location: PIN_N19, I/O Standard: 2.5 V, Current Strength: Default
-- a[5] => Location: PIN_K22, I/O Standard: 2.5 V, Current Strength: Default
-- a[3] => Location: PIN_L19, I/O Standard: 2.5 V, Current Strength: Default
-- a[2] => Location: PIN_P18, I/O Standard: 2.5 V, Current Strength: Default
-- a[1] => Location: PIN_P17, I/O Standard: 2.5 V, Current Strength: Default
-- a[0] => Location: PIN_L18, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF exercicio2 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_c : std_logic;
SIGNAL ww_s : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_a : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_d : std_logic;
SIGNAL ww_troco : std_logic;
SIGNAL \~QUARTUS_CREATED_GND~I_combout\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputCLKENA0_outclk\ : std_logic;
SIGNAL \s[4]~input_o\ : std_logic;
SIGNAL \a[4]~input_o\ : std_logic;
SIGNAL \a[3]~input_o\ : std_logic;
SIGNAL \a[2]~input_o\ : std_logic;
SIGNAL \a[1]~input_o\ : std_logic;
SIGNAL \a[0]~input_o\ : std_logic;
SIGNAL \i1|Add0~29_sumout\ : std_logic;
SIGNAL \c~input_o\ : std_logic;
SIGNAL \i2|Mux1~0_combout\ : std_logic;
SIGNAL \i2|d~1_combout\ : std_logic;
SIGNAL \i1|Add0~30\ : std_logic;
SIGNAL \i1|Add0~25_sumout\ : std_logic;
SIGNAL \i1|Add0~26\ : std_logic;
SIGNAL \i1|Add0~21_sumout\ : std_logic;
SIGNAL \i1|Add0~22\ : std_logic;
SIGNAL \i1|Add0~17_sumout\ : std_logic;
SIGNAL \i1|Add0~18\ : std_logic;
SIGNAL \i1|Add0~1_sumout\ : std_logic;
SIGNAL \i1|LessThan1~6_combout\ : std_logic;
SIGNAL \s[3]~input_o\ : std_logic;
SIGNAL \s[5]~input_o\ : std_logic;
SIGNAL \s[7]~input_o\ : std_logic;
SIGNAL \a[6]~input_o\ : std_logic;
SIGNAL \a[5]~input_o\ : std_logic;
SIGNAL \i1|Add0~2\ : std_logic;
SIGNAL \i1|Add0~13_sumout\ : std_logic;
SIGNAL \i1|Add0~14\ : std_logic;
SIGNAL \i1|Add0~9_sumout\ : std_logic;
SIGNAL \s[6]~input_o\ : std_logic;
SIGNAL \a[7]~input_o\ : std_logic;
SIGNAL \i1|Add0~10\ : std_logic;
SIGNAL \i1|Add0~5_sumout\ : std_logic;
SIGNAL \i1|LessThan1~0_combout\ : std_logic;
SIGNAL \i1|LessThan0~2_combout\ : std_logic;
SIGNAL \s[1]~input_o\ : std_logic;
SIGNAL \i1|LessThan0~1_combout\ : std_logic;
SIGNAL \s[2]~input_o\ : std_logic;
SIGNAL \i1|LessThan1~5_combout\ : std_logic;
SIGNAL \s[0]~input_o\ : std_logic;
SIGNAL \i1|LessThan0~3_combout\ : std_logic;
SIGNAL \i2|Mux0~3_combout\ : std_logic;
SIGNAL \i2|Mux0~0_combout\ : std_logic;
SIGNAL \i1|LessThan0~0_combout\ : std_logic;
SIGNAL \i2|Mux0~1_combout\ : std_logic;
SIGNAL \i2|Mux0~2_combout\ : std_logic;
SIGNAL \i2|Mux0~4_combout\ : std_logic;
SIGNAL \i2|d~0_combout\ : std_logic;
SIGNAL \i1|LessThan1~3_combout\ : std_logic;
SIGNAL \i1|LessThan1~1_combout\ : std_logic;
SIGNAL \i1|LessThan1~2_combout\ : std_logic;
SIGNAL \i1|LessThan1~4_combout\ : std_logic;
SIGNAL \i2|y\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \i1|tot_saida\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \ALT_INV_a[0]~input_o\ : std_logic;
SIGNAL \ALT_INV_a[1]~input_o\ : std_logic;
SIGNAL \ALT_INV_a[2]~input_o\ : std_logic;
SIGNAL \ALT_INV_a[3]~input_o\ : std_logic;
SIGNAL \ALT_INV_a[5]~input_o\ : std_logic;
SIGNAL \ALT_INV_a[6]~input_o\ : std_logic;
SIGNAL \ALT_INV_a[7]~input_o\ : std_logic;
SIGNAL \ALT_INV_a[4]~input_o\ : std_logic;
SIGNAL \ALT_INV_c~input_o\ : std_logic;
SIGNAL \ALT_INV_s[0]~input_o\ : std_logic;
SIGNAL \ALT_INV_s[1]~input_o\ : std_logic;
SIGNAL \ALT_INV_s[2]~input_o\ : std_logic;
SIGNAL \ALT_INV_s[3]~input_o\ : std_logic;
SIGNAL \ALT_INV_s[5]~input_o\ : std_logic;
SIGNAL \ALT_INV_s[6]~input_o\ : std_logic;
SIGNAL \ALT_INV_s[7]~input_o\ : std_logic;
SIGNAL \ALT_INV_s[4]~input_o\ : std_logic;
SIGNAL \i2|ALT_INV_Mux0~3_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan0~3_combout\ : std_logic;
SIGNAL \i2|ALT_INV_Mux0~2_combout\ : std_logic;
SIGNAL \i2|ALT_INV_Mux0~1_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan0~2_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan0~1_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan0~0_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan1~6_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan1~5_combout\ : std_logic;
SIGNAL \i2|ALT_INV_Mux0~0_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan1~3_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan1~2_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan1~1_combout\ : std_logic;
SIGNAL \i1|ALT_INV_LessThan1~0_combout\ : std_logic;
SIGNAL \i2|ALT_INV_d~0_combout\ : std_logic;
SIGNAL \i2|ALT_INV_y\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \i1|ALT_INV_tot_saida\ : std_logic_vector(7 DOWNTO 0);
BEGIN
ww_clk <= clk;
ww_c <= c;
ww_s <= s;
ww_a <= a;
d <= ww_d;
troco <= ww_troco;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_a[0]~input_o\ <= NOT \a[0]~input_o\;
\ALT_INV_a[1]~input_o\ <= NOT \a[1]~input_o\;
\ALT_INV_a[2]~input_o\ <= NOT \a[2]~input_o\;
\ALT_INV_a[3]~input_o\ <= NOT \a[3]~input_o\;
\ALT_INV_a[5]~input_o\ <= NOT \a[5]~input_o\;
\ALT_INV_a[6]~input_o\ <= NOT \a[6]~input_o\;
\ALT_INV_a[7]~input_o\ <= NOT \a[7]~input_o\;
\ALT_INV_a[4]~input_o\ <= NOT \a[4]~input_o\;
\ALT_INV_c~input_o\ <= NOT \c~input_o\;
\ALT_INV_s[0]~input_o\ <= NOT \s[0]~input_o\;
\ALT_INV_s[1]~input_o\ <= NOT \s[1]~input_o\;
\ALT_INV_s[2]~input_o\ <= NOT \s[2]~input_o\;
\ALT_INV_s[3]~input_o\ <= NOT \s[3]~input_o\;
\ALT_INV_s[5]~input_o\ <= NOT \s[5]~input_o\;
\ALT_INV_s[6]~input_o\ <= NOT \s[6]~input_o\;
\ALT_INV_s[7]~input_o\ <= NOT \s[7]~input_o\;
\ALT_INV_s[4]~input_o\ <= NOT \s[4]~input_o\;
\i2|ALT_INV_Mux0~3_combout\ <= NOT \i2|Mux0~3_combout\;
\i1|ALT_INV_LessThan0~3_combout\ <= NOT \i1|LessThan0~3_combout\;
\i2|ALT_INV_Mux0~2_combout\ <= NOT \i2|Mux0~2_combout\;
\i2|ALT_INV_Mux0~1_combout\ <= NOT \i2|Mux0~1_combout\;
\i1|ALT_INV_LessThan0~2_combout\ <= NOT \i1|LessThan0~2_combout\;
\i1|ALT_INV_LessThan0~1_combout\ <= NOT \i1|LessThan0~1_combout\;
\i1|ALT_INV_LessThan0~0_combout\ <= NOT \i1|LessThan0~0_combout\;
\i1|ALT_INV_LessThan1~6_combout\ <= NOT \i1|LessThan1~6_combout\;
\i1|ALT_INV_LessThan1~5_combout\ <= NOT \i1|LessThan1~5_combout\;
\i2|ALT_INV_Mux0~0_combout\ <= NOT \i2|Mux0~0_combout\;
\i1|ALT_INV_LessThan1~3_combout\ <= NOT \i1|LessThan1~3_combout\;
\i1|ALT_INV_LessThan1~2_combout\ <= NOT \i1|LessThan1~2_combout\;
\i1|ALT_INV_LessThan1~1_combout\ <= NOT \i1|LessThan1~1_combout\;
\i1|ALT_INV_LessThan1~0_combout\ <= NOT \i1|LessThan1~0_combout\;
\i2|ALT_INV_d~0_combout\ <= NOT \i2|d~0_combout\;
\i2|ALT_INV_y\(1) <= NOT \i2|y\(1);
\i2|ALT_INV_y\(0) <= NOT \i2|y\(0);
\i1|ALT_INV_tot_saida\(0) <= NOT \i1|tot_saida\(0);
\i1|ALT_INV_tot_saida\(1) <= NOT \i1|tot_saida\(1);
\i1|ALT_INV_tot_saida\(2) <= NOT \i1|tot_saida\(2);
\i1|ALT_INV_tot_saida\(3) <= NOT \i1|tot_saida\(3);
\i1|ALT_INV_tot_saida\(5) <= NOT \i1|tot_saida\(5);
\i1|ALT_INV_tot_saida\(6) <= NOT \i1|tot_saida\(6);
\i1|ALT_INV_tot_saida\(7) <= NOT \i1|tot_saida\(7);
\i1|ALT_INV_tot_saida\(4) <= NOT \i1|tot_saida\(4);
-- Location: IOOBUF_X89_Y9_N5
\d~output\ : cyclonev_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false",
shift_series_termination_control => "false")
-- pragma translate_on
PORT MAP (
i => \i2|ALT_INV_d~0_combout\,
devoe => ww_devoe,
o => ww_d);
-- Location: IOOBUF_X89_Y35_N45
\troco~output\ : cyclonev_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false",
shift_series_termination_control => "false")
-- pragma translate_on
PORT MAP (
i => \i1|LessThan1~4_combout\,
devoe => ww_devoe,
o => ww_troco);
-- Location: IOIBUF_X89_Y35_N61
\clk~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_clk,
o => \clk~input_o\);
-- Location: CLKCTRL_G10
\clk~inputCLKENA0\ : cyclonev_clkena
-- pragma translate_off
GENERIC MAP (
clock_type => "global clock",
disable_mode => "low",
ena_register_mode => "always enabled",
ena_register_power_up => "high",
test_syn => "high")
-- pragma translate_on
PORT MAP (
inclk => \clk~input_o\,
outclk => \clk~inputCLKENA0_outclk\);
-- Location: IOIBUF_X89_Y37_N55
\s[4]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(4),
o => \s[4]~input_o\);
-- Location: IOIBUF_X86_Y81_N52
\a[4]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(4),
o => \a[4]~input_o\);
-- Location: IOIBUF_X89_Y38_N4
\a[3]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(3),
o => \a[3]~input_o\);
-- Location: IOIBUF_X89_Y9_N55
\a[2]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(2),
o => \a[2]~input_o\);
-- Location: IOIBUF_X89_Y9_N21
\a[1]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(1),
o => \a[1]~input_o\);
-- Location: IOIBUF_X89_Y38_N21
\a[0]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(0),
o => \a[0]~input_o\);
-- Location: MLABCELL_X87_Y42_N0
\i1|Add0~29\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~29_sumout\ = SUM(( \i1|tot_saida\(0) ) + ( \a[0]~input_o\ ) + ( !VCC ))
-- \i1|Add0~30\ = CARRY(( \i1|tot_saida\(0) ) + ( \a[0]~input_o\ ) + ( !VCC ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datac => \ALT_INV_a[0]~input_o\,
datad => \i1|ALT_INV_tot_saida\(0),
cin => GND,
sumout => \i1|Add0~29_sumout\,
cout => \i1|Add0~30\);
-- Location: IOIBUF_X89_Y36_N21
\c~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_c,
o => \c~input_o\);
-- Location: LABCELL_X88_Y42_N3
\i2|Mux1~0\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|Mux1~0_combout\ = ( !\i2|y\(1) & ( \i2|y\(0) & ( !\c~input_o\ ) ) ) # ( \i2|y\(1) & ( !\i2|y\(0) ) ) # ( !\i2|y\(1) & ( !\i2|y\(0) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "1111111111111111111111111111111110101010101010100000000000000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_c~input_o\,
datae => \i2|ALT_INV_y\(1),
dataf => \i2|ALT_INV_y\(0),
combout => \i2|Mux1~0_combout\);
-- Location: FF_X87_Y42_N41
\i2|y[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
asdata => \i2|Mux1~0_combout\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i2|y\(0));
-- Location: MLABCELL_X87_Y42_N51
\i2|d~1\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|d~1_combout\ = (!\i2|y\(0) & !\i2|y\(1))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "1111000000000000111100000000000011110000000000001111000000000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datac => \i2|ALT_INV_y\(0),
datad => \i2|ALT_INV_y\(1),
combout => \i2|d~1_combout\);
-- Location: FF_X87_Y42_N2
\i1|tot_saida[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~29_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(0));
-- Location: MLABCELL_X87_Y42_N3
\i1|Add0~25\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~25_sumout\ = SUM(( \i1|tot_saida\(1) ) + ( \a[1]~input_o\ ) + ( \i1|Add0~30\ ))
-- \i1|Add0~26\ = CARRY(( \i1|tot_saida\(1) ) + ( \a[1]~input_o\ ) + ( \i1|Add0~30\ ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datac => \ALT_INV_a[1]~input_o\,
datad => \i1|ALT_INV_tot_saida\(1),
cin => \i1|Add0~30\,
sumout => \i1|Add0~25_sumout\,
cout => \i1|Add0~26\);
-- Location: FF_X87_Y42_N5
\i1|tot_saida[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~25_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(1));
-- Location: MLABCELL_X87_Y42_N6
\i1|Add0~21\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~21_sumout\ = SUM(( \i1|tot_saida\(2) ) + ( \a[2]~input_o\ ) + ( \i1|Add0~26\ ))
-- \i1|Add0~22\ = CARRY(( \i1|tot_saida\(2) ) + ( \a[2]~input_o\ ) + ( \i1|Add0~26\ ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datac => \ALT_INV_a[2]~input_o\,
datad => \i1|ALT_INV_tot_saida\(2),
cin => \i1|Add0~26\,
sumout => \i1|Add0~21_sumout\,
cout => \i1|Add0~22\);
-- Location: FF_X87_Y42_N8
\i1|tot_saida[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~21_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(2));
-- Location: MLABCELL_X87_Y42_N9
\i1|Add0~17\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~17_sumout\ = SUM(( \i1|tot_saida\(3) ) + ( \a[3]~input_o\ ) + ( \i1|Add0~22\ ))
-- \i1|Add0~18\ = CARRY(( \i1|tot_saida\(3) ) + ( \a[3]~input_o\ ) + ( \i1|Add0~22\ ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datac => \ALT_INV_a[3]~input_o\,
datad => \i1|ALT_INV_tot_saida\(3),
cin => \i1|Add0~22\,
sumout => \i1|Add0~17_sumout\,
cout => \i1|Add0~18\);
-- Location: FF_X87_Y42_N11
\i1|tot_saida[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~17_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(3));
-- Location: MLABCELL_X87_Y42_N12
\i1|Add0~1\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~1_sumout\ = SUM(( \i1|tot_saida\(4) ) + ( \a[4]~input_o\ ) + ( \i1|Add0~18\ ))
-- \i1|Add0~2\ = CARRY(( \i1|tot_saida\(4) ) + ( \a[4]~input_o\ ) + ( \i1|Add0~18\ ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datac => \ALT_INV_a[4]~input_o\,
datad => \i1|ALT_INV_tot_saida\(4),
cin => \i1|Add0~18\,
sumout => \i1|Add0~1_sumout\,
cout => \i1|Add0~2\);
-- Location: FF_X87_Y42_N14
\i1|tot_saida[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~1_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(4));
-- Location: MLABCELL_X87_Y42_N30
\i1|LessThan1~6\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan1~6_combout\ = ( \i1|tot_saida\(4) & ( !\s[4]~input_o\ ) ) # ( !\i1|tot_saida\(4) & ( \s[4]~input_o\ ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000011111111000000001111111111111111000000001111111100000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datad => \ALT_INV_s[4]~input_o\,
dataf => \i1|ALT_INV_tot_saida\(4),
combout => \i1|LessThan1~6_combout\);
-- Location: IOIBUF_X89_Y37_N4
\s[3]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(3),
o => \s[3]~input_o\);
-- Location: IOIBUF_X89_Y36_N55
\s[5]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(5),
o => \s[5]~input_o\);
-- Location: IOIBUF_X89_Y37_N21
\s[7]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(7),
o => \s[7]~input_o\);
-- Location: IOIBUF_X89_Y36_N4
\a[6]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(6),
o => \a[6]~input_o\);
-- Location: IOIBUF_X89_Y38_N55
\a[5]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(5),
o => \a[5]~input_o\);
-- Location: MLABCELL_X87_Y42_N15
\i1|Add0~13\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~13_sumout\ = SUM(( \i1|tot_saida\(5) ) + ( \a[5]~input_o\ ) + ( \i1|Add0~2\ ))
-- \i1|Add0~14\ = CARRY(( \i1|tot_saida\(5) ) + ( \a[5]~input_o\ ) + ( \i1|Add0~2\ ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000101010101010101000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_a[5]~input_o\,
datad => \i1|ALT_INV_tot_saida\(5),
cin => \i1|Add0~2\,
sumout => \i1|Add0~13_sumout\,
cout => \i1|Add0~14\);
-- Location: FF_X87_Y42_N17
\i1|tot_saida[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~13_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(5));
-- Location: MLABCELL_X87_Y42_N18
\i1|Add0~9\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~9_sumout\ = SUM(( \i1|tot_saida\(6) ) + ( \a[6]~input_o\ ) + ( \i1|Add0~14\ ))
-- \i1|Add0~10\ = CARRY(( \i1|tot_saida\(6) ) + ( \a[6]~input_o\ ) + ( \i1|Add0~14\ ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000110011001100110000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datab => \ALT_INV_a[6]~input_o\,
datad => \i1|ALT_INV_tot_saida\(6),
cin => \i1|Add0~14\,
sumout => \i1|Add0~9_sumout\,
cout => \i1|Add0~10\);
-- Location: FF_X87_Y42_N20
\i1|tot_saida[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~9_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(6));
-- Location: IOIBUF_X89_Y37_N38
\s[6]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(6),
o => \s[6]~input_o\);
-- Location: IOIBUF_X89_Y38_N38
\a[7]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_a(7),
o => \a[7]~input_o\);
-- Location: MLABCELL_X87_Y42_N21
\i1|Add0~5\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|Add0~5_sumout\ = SUM(( \i1|tot_saida\(7) ) + ( \a[7]~input_o\ ) + ( \i1|Add0~10\ ))
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000101010101010101000000000000000000000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_a[7]~input_o\,
datad => \i1|ALT_INV_tot_saida\(7),
cin => \i1|Add0~10\,
sumout => \i1|Add0~5_sumout\);
-- Location: FF_X87_Y42_N23
\i1|tot_saida[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i1|Add0~5_sumout\,
sclr => \i2|d~1_combout\,
ena => \i2|ALT_INV_y\(0),
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i1|tot_saida\(7));
-- Location: MLABCELL_X87_Y42_N54
\i1|LessThan1~0\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan1~0_combout\ = ( \i1|tot_saida\(7) & ( \i1|tot_saida\(5) & ( (\s[5]~input_o\ & (\s[7]~input_o\ & (!\i1|tot_saida\(6) $ (\s[6]~input_o\)))) ) ) ) # ( !\i1|tot_saida\(7) & ( \i1|tot_saida\(5) & ( (\s[5]~input_o\ & (!\s[7]~input_o\ &
-- (!\i1|tot_saida\(6) $ (\s[6]~input_o\)))) ) ) ) # ( \i1|tot_saida\(7) & ( !\i1|tot_saida\(5) & ( (!\s[5]~input_o\ & (\s[7]~input_o\ & (!\i1|tot_saida\(6) $ (\s[6]~input_o\)))) ) ) ) # ( !\i1|tot_saida\(7) & ( !\i1|tot_saida\(5) & ( (!\s[5]~input_o\ &
-- (!\s[7]~input_o\ & (!\i1|tot_saida\(6) $ (\s[6]~input_o\)))) ) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "1000000000001000001000000000001001000000000001000001000000000001",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[5]~input_o\,
datab => \ALT_INV_s[7]~input_o\,
datac => \i1|ALT_INV_tot_saida\(6),
datad => \ALT_INV_s[6]~input_o\,
datae => \i1|ALT_INV_tot_saida\(7),
dataf => \i1|ALT_INV_tot_saida\(5),
combout => \i1|LessThan1~0_combout\);
-- Location: MLABCELL_X87_Y42_N33
\i1|LessThan0~2\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan0~2_combout\ = ( \i1|LessThan1~0_combout\ & ( (!\i1|LessThan1~6_combout\ & (\s[3]~input_o\ & !\i1|tot_saida\(3))) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000000000000000000000100000001000000010000000100000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \i1|ALT_INV_LessThan1~6_combout\,
datab => \ALT_INV_s[3]~input_o\,
datac => \i1|ALT_INV_tot_saida\(3),
dataf => \i1|ALT_INV_LessThan1~0_combout\,
combout => \i1|LessThan0~2_combout\);
-- Location: IOIBUF_X89_Y35_N78
\s[1]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(1),
o => \s[1]~input_o\);
-- Location: LABCELL_X88_Y42_N15
\i1|LessThan0~1\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan0~1_combout\ = ( !\i1|tot_saida\(1) & ( \s[1]~input_o\ ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000000000000000000011111111111111110000000000000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datae => \i1|ALT_INV_tot_saida\(1),
dataf => \ALT_INV_s[1]~input_o\,
combout => \i1|LessThan0~1_combout\);
-- Location: IOIBUF_X89_Y36_N38
\s[2]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(2),
o => \s[2]~input_o\);
-- Location: MLABCELL_X87_Y42_N24
\i1|LessThan1~5\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan1~5_combout\ = ( \i1|tot_saida\(3) & ( !\s[3]~input_o\ ) ) # ( !\i1|tot_saida\(3) & ( \s[3]~input_o\ ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0011001100110011001100110011001111001100110011001100110011001100",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datab => \ALT_INV_s[3]~input_o\,
dataf => \i1|ALT_INV_tot_saida\(3),
combout => \i1|LessThan1~5_combout\);
-- Location: IOIBUF_X89_Y35_N95
\s[0]~input\ : cyclonev_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_s(0),
o => \s[0]~input_o\);
-- Location: LABCELL_X88_Y42_N42
\i1|LessThan0~3\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan0~3_combout\ = ( \i1|tot_saida\(1) & ( (\s[0]~input_o\ & (\s[1]~input_o\ & !\i1|tot_saida\(0))) ) ) # ( !\i1|tot_saida\(1) & ( (\s[0]~input_o\ & (!\s[1]~input_o\ & !\i1|tot_saida\(0))) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0100000001000000000100000001000001000000010000000001000000010000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[0]~input_o\,
datab => \ALT_INV_s[1]~input_o\,
datac => \i1|ALT_INV_tot_saida\(0),
datae => \i1|ALT_INV_tot_saida\(1),
combout => \i1|LessThan0~3_combout\);
-- Location: LABCELL_X88_Y42_N33
\i2|Mux0~3\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|Mux0~3_combout\ = ( \i1|LessThan1~0_combout\ & ( \i1|LessThan0~3_combout\ & ( (!\i1|LessThan1~5_combout\ & (!\i1|LessThan1~6_combout\ & ((!\i1|tot_saida\(2)) # (\s[2]~input_o\)))) ) ) ) # ( \i1|LessThan1~0_combout\ & ( !\i1|LessThan0~3_combout\ & (
-- (\s[2]~input_o\ & (!\i1|tot_saida\(2) & (!\i1|LessThan1~5_combout\ & !\i1|LessThan1~6_combout\))) ) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000010000000000000000000000000000001101000000000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[2]~input_o\,
datab => \i1|ALT_INV_tot_saida\(2),
datac => \i1|ALT_INV_LessThan1~5_combout\,
datad => \i1|ALT_INV_LessThan1~6_combout\,
datae => \i1|ALT_INV_LessThan1~0_combout\,
dataf => \i1|ALT_INV_LessThan0~3_combout\,
combout => \i2|Mux0~3_combout\);
-- Location: MLABCELL_X87_Y42_N27
\i2|Mux0~0\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|Mux0~0_combout\ = ( \i2|y\(0) & ( (\c~input_o\ & !\i2|y\(1)) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datac => \ALT_INV_c~input_o\,
datad => \i2|ALT_INV_y\(1),
dataf => \i2|ALT_INV_y\(0),
combout => \i2|Mux0~0_combout\);
-- Location: MLABCELL_X87_Y42_N48
\i1|LessThan0~0\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan0~0_combout\ = ( \i1|LessThan1~0_combout\ & ( (!\i1|LessThan1~5_combout\ & (!\i1|LessThan1~6_combout\ & (!\i1|tot_saida\(2) $ (\s[2]~input_o\)))) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000000000000000000010000000001000001000000000100000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \i1|ALT_INV_LessThan1~5_combout\,
datab => \i1|ALT_INV_tot_saida\(2),
datac => \i1|ALT_INV_LessThan1~6_combout\,
datad => \ALT_INV_s[2]~input_o\,
dataf => \i1|ALT_INV_LessThan1~0_combout\,
combout => \i1|LessThan0~0_combout\);
-- Location: LABCELL_X88_Y42_N18
\i2|Mux0~1\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|Mux0~1_combout\ = ( \i1|tot_saida\(7) & ( \i1|tot_saida\(6) & ( (\s[7]~input_o\ & (\s[5]~input_o\ & (\s[6]~input_o\ & !\i1|tot_saida\(5)))) ) ) ) # ( !\i1|tot_saida\(7) & ( \i1|tot_saida\(6) & ( ((\s[5]~input_o\ & (\s[6]~input_o\ &
-- !\i1|tot_saida\(5)))) # (\s[7]~input_o\) ) ) ) # ( \i1|tot_saida\(7) & ( !\i1|tot_saida\(6) & ( (\s[7]~input_o\ & (((\s[5]~input_o\ & !\i1|tot_saida\(5))) # (\s[6]~input_o\))) ) ) ) # ( !\i1|tot_saida\(7) & ( !\i1|tot_saida\(6) & ( (((\s[5]~input_o\ &
-- !\i1|tot_saida\(5))) # (\s[6]~input_o\)) # (\s[7]~input_o\) ) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0111111101011111000101010000010101010111010101010000000100000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[7]~input_o\,
datab => \ALT_INV_s[5]~input_o\,
datac => \ALT_INV_s[6]~input_o\,
datad => \i1|ALT_INV_tot_saida\(5),
datae => \i1|ALT_INV_tot_saida\(7),
dataf => \i1|ALT_INV_tot_saida\(6),
combout => \i2|Mux0~1_combout\);
-- Location: MLABCELL_X87_Y42_N42
\i2|Mux0~2\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|Mux0~2_combout\ = ( !\i2|y\(1) & ( !\i2|Mux0~1_combout\ & ( (\i2|y\(0) & ((!\s[4]~input_o\) # ((!\i1|LessThan1~0_combout\) # (\i1|tot_saida\(4))))) ) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000011111011000000000000000000000000000000000000000000000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[4]~input_o\,
datab => \i1|ALT_INV_tot_saida\(4),
datac => \i1|ALT_INV_LessThan1~0_combout\,
datad => \i2|ALT_INV_y\(0),
datae => \i2|ALT_INV_y\(1),
dataf => \i2|ALT_INV_Mux0~1_combout\,
combout => \i2|Mux0~2_combout\);
-- Location: MLABCELL_X87_Y42_N36
\i2|Mux0~4\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|Mux0~4_combout\ = ( \i1|LessThan0~0_combout\ & ( \i2|Mux0~2_combout\ & ( ((!\i1|LessThan0~2_combout\ & (!\i1|LessThan0~1_combout\ & !\i2|Mux0~3_combout\))) # (\i2|Mux0~0_combout\) ) ) ) # ( !\i1|LessThan0~0_combout\ & ( \i2|Mux0~2_combout\ & (
-- ((!\i1|LessThan0~2_combout\ & !\i2|Mux0~3_combout\)) # (\i2|Mux0~0_combout\) ) ) ) # ( \i1|LessThan0~0_combout\ & ( !\i2|Mux0~2_combout\ & ( \i2|Mux0~0_combout\ ) ) ) # ( !\i1|LessThan0~0_combout\ & ( !\i2|Mux0~2_combout\ & ( \i2|Mux0~0_combout\ ) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000011111111000000001111111110100000111111111000000011111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \i1|ALT_INV_LessThan0~2_combout\,
datab => \i1|ALT_INV_LessThan0~1_combout\,
datac => \i2|ALT_INV_Mux0~3_combout\,
datad => \i2|ALT_INV_Mux0~0_combout\,
datae => \i1|ALT_INV_LessThan0~0_combout\,
dataf => \i2|ALT_INV_Mux0~2_combout\,
combout => \i2|Mux0~4_combout\);
-- Location: FF_X87_Y42_N38
\i2|y[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputCLKENA0_outclk\,
d => \i2|Mux0~4_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \i2|y\(1));
-- Location: LABCELL_X88_Y42_N48
\i2|d~0\ : cyclonev_lcell_comb
-- Equation(s):
-- \i2|d~0_combout\ = ( !\i2|y\(1) & ( \i2|y\(0) ) ) # ( \i2|y\(1) & ( !\i2|y\(0) ) ) # ( !\i2|y\(1) & ( !\i2|y\(0) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "1111111111111111111111111111111111111111111111110000000000000000",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
datae => \i2|ALT_INV_y\(1),
dataf => \i2|ALT_INV_y\(0),
combout => \i2|d~0_combout\);
-- Location: LABCELL_X88_Y42_N6
\i1|LessThan1~3\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan1~3_combout\ = ( \s[7]~input_o\ & ( \i1|tot_saida\(5) & ( (\i1|tot_saida\(7) & ((!\s[6]~input_o\ & ((!\s[5]~input_o\) # (\i1|tot_saida\(6)))) # (\s[6]~input_o\ & (\i1|tot_saida\(6) & !\s[5]~input_o\)))) ) ) ) # ( !\s[7]~input_o\ & (
-- \i1|tot_saida\(5) & ( ((!\s[6]~input_o\ & ((!\s[5]~input_o\) # (\i1|tot_saida\(6)))) # (\s[6]~input_o\ & (\i1|tot_saida\(6) & !\s[5]~input_o\))) # (\i1|tot_saida\(7)) ) ) ) # ( \s[7]~input_o\ & ( !\i1|tot_saida\(5) & ( (!\s[6]~input_o\ &
-- (\i1|tot_saida\(6) & \i1|tot_saida\(7))) ) ) ) # ( !\s[7]~input_o\ & ( !\i1|tot_saida\(5) & ( ((!\s[6]~input_o\ & \i1|tot_saida\(6))) # (\i1|tot_saida\(7)) ) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0010111100101111000000100000001010111111001011110000101100000010",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[6]~input_o\,
datab => \i1|ALT_INV_tot_saida\(6),
datac => \i1|ALT_INV_tot_saida\(7),
datad => \ALT_INV_s[5]~input_o\,
datae => \ALT_INV_s[7]~input_o\,
dataf => \i1|ALT_INV_tot_saida\(5),
combout => \i1|LessThan1~3_combout\);
-- Location: LABCELL_X88_Y42_N54
\i1|LessThan1~1\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan1~1_combout\ = ( \i1|tot_saida\(0) & ( (!\s[0]~input_o\ & ((!\s[1]~input_o\) # (\i1|tot_saida\(1)))) # (\s[0]~input_o\ & (!\s[1]~input_o\ & \i1|tot_saida\(1))) ) ) # ( !\i1|tot_saida\(0) & ( (!\s[1]~input_o\ & \i1|tot_saida\(1)) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000110000001100100011101000111000001100000011001000111010001110",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[0]~input_o\,
datab => \ALT_INV_s[1]~input_o\,
datac => \i1|ALT_INV_tot_saida\(1),
datae => \i1|ALT_INV_tot_saida\(0),
combout => \i1|LessThan1~1_combout\);
-- Location: LABCELL_X88_Y42_N39
\i1|LessThan1~2\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan1~2_combout\ = ( \s[3]~input_o\ & ( \i1|tot_saida\(2) & ( (\i1|tot_saida\(3) & ((!\s[2]~input_o\) # (\i1|LessThan1~1_combout\))) ) ) ) # ( !\s[3]~input_o\ & ( \i1|tot_saida\(2) & ( ((!\s[2]~input_o\) # (\i1|tot_saida\(3))) #
-- (\i1|LessThan1~1_combout\) ) ) ) # ( \s[3]~input_o\ & ( !\i1|tot_saida\(2) & ( (\i1|LessThan1~1_combout\ & (\i1|tot_saida\(3) & !\s[2]~input_o\)) ) ) ) # ( !\s[3]~input_o\ & ( !\i1|tot_saida\(2) & ( ((\i1|LessThan1~1_combout\ & !\s[2]~input_o\)) #
-- (\i1|tot_saida\(3)) ) ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0111001101110011000100000001000011110111111101110011000100110001",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \i1|ALT_INV_LessThan1~1_combout\,
datab => \i1|ALT_INV_tot_saida\(3),
datac => \ALT_INV_s[2]~input_o\,
datae => \ALT_INV_s[3]~input_o\,
dataf => \i1|ALT_INV_tot_saida\(2),
combout => \i1|LessThan1~2_combout\);
-- Location: LABCELL_X88_Y42_N24
\i1|LessThan1~4\ : cyclonev_lcell_comb
-- Equation(s):
-- \i1|LessThan1~4_combout\ = ( \i1|tot_saida\(4) & ( \i1|LessThan1~2_combout\ & ( (\i1|LessThan1~0_combout\) # (\i1|LessThan1~3_combout\) ) ) ) # ( !\i1|tot_saida\(4) & ( \i1|LessThan1~2_combout\ & ( ((!\s[4]~input_o\ & \i1|LessThan1~0_combout\)) #
-- (\i1|LessThan1~3_combout\) ) ) ) # ( \i1|tot_saida\(4) & ( !\i1|LessThan1~2_combout\ & ( ((!\s[4]~input_o\ & \i1|LessThan1~0_combout\)) # (\i1|LessThan1~3_combout\) ) ) ) # ( !\i1|tot_saida\(4) & ( !\i1|LessThan1~2_combout\ & ( \i1|LessThan1~3_combout\ )
-- ) )
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0011001100110011001100111011101100110011101110110011001111111111",
shared_arith => "off")
-- pragma translate_on
PORT MAP (
dataa => \ALT_INV_s[4]~input_o\,
datab => \i1|ALT_INV_LessThan1~3_combout\,
datad => \i1|ALT_INV_LessThan1~0_combout\,
datae => \i1|ALT_INV_tot_saida\(4),
dataf => \i1|ALT_INV_LessThan1~2_combout\,
combout => \i1|LessThan1~4_combout\);
-- Location: LABCELL_X35_Y34_N0
\~QUARTUS_CREATED_GND~I\ : cyclonev_lcell_comb
-- Equation(s):
-- pragma translate_off
GENERIC MAP (
extended_lut => "off",
lut_mask => "0000000000000000000000000000000000000000000000000000000000000000",
shared_arith => "off")
-- pragma translate_on
;
END structure;
|
--
-- Copyright (c) 2018, UPC
-- All rights reserved.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cte_tipos_buffer_pkg.all;
package procedimientos_prueba_acceso_pkg is
procedure wait_until_falling_edges(signal reloj: in std_logic; n: in integer);
procedure escribir (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic);
procedure leer (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic);
procedure concesclec (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic);
procedure desactivar (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic);
end package procedimientos_prueba_acceso_pkg;
package body procedimientos_prueba_acceso_pkg is
procedure wait_until_falling_edges(signal reloj: in std_logic; n: in integer) is
begin
for i in 1 to n loop
wait until falling_edge(reloj);
end loop;
end procedure;
procedure escribir (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic) is
begin
wait_until_falling_edges(reloj,1);
escritura <= '1';
lectura <= '0';
end procedure;
procedure leer (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic) is
begin
wait_until_falling_edges(reloj,1);
escritura <= '0';
lectura <= '1';
end procedure;
procedure concesclec (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic) is
begin
wait_until_falling_edges(reloj,1);
escritura <= '1';
lectura <= '1';
end procedure;
procedure desactivar (signal escritura: out std_logic; signal lectura: out std_logic; signal reloj: in std_logic) is
begin
wait_until_falling_edges(reloj,1);
escritura <= '0';
lectura <= '0';
end procedure;
end package body procedimientos_prueba_acceso_pkg;
|
<reponame>abdcelik/GTU
library verilog;
use verilog.vl_types.all;
entity mux_2x1_16bit is
port(
in1 : in vl_logic_vector(15 downto 0);
in2 : in vl_logic_vector(15 downto 0);
s : in vl_logic;
\out\ : out vl_logic_vector(15 downto 0)
);
end mux_2x1_16bit;
|
<filename>VHDL/system.vhd
--
-- Based on <NAME>'s build of the SAP breadboard computer and his excellent videos.
-- https://eater.net/
--
-- Copyright (c) 2017 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY system IS
generic
(
C_SYSTEM_HZ : integer := 12_000_000; -- master clock (in Hz)
C_BPS : integer := 9600;
C_AUTOBAUD : boolean := false; -- use RX bit interval to set baud rate
C_TRACE : boolean := true
);
PORT(
clk_i : IN STD_LOGIC;
clk_en_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
out_o : OUT STD_LOGIC_VECTOR(7 downto 0);
halt_o : OUT STD_LOGIC;
tx_o : OUT STD_LOGIC;
rx_i : IN STD_LOGIC
);
END system;
ARCHITECTURE RTL OF system IS
SIGNAL rst : STD_LOGIC := '0'; -- asynchronous reset
SIGNAL clk : STD_LOGIC := '0'; -- CPU clock
SIGNAL clk_en : STD_LOGIC := '0'; -- CPU clock enable (clock ignored if 0)
SIGNAL ram_we : STD_LOGIC := '0';
SIGNAL ram_addr : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
SIGNAL data_ram_to_cpu : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
SIGNAL data_cpu_to_ram : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
SIGNAL halt : STD_LOGIC := '0';
SIGNAL cpu_debug_sel : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
SIGNAL cpu_debug_out : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
SIGNAL tx_busy : STD_LOGIC := '0';
SIGNAL tx_write : STD_LOGIC := '0';
SIGNAL tx_data : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
SIGNAL trace_busy : STD_LOGIC := '0';
BEGIN
-- internal signals
rst <= rst_i;
clk <= clk_i;
clk_en <= clk_en_i AND (NOT trace_busy);
-- instantiate CPU
CPU: entity work.cpu
port map(
clk_i => clk,
clk_en_i => clk_en,
rst_i => rst,
ram_data_i => data_ram_to_cpu,
ram_data_o => data_cpu_to_ram,
ram_addr_o => ram_addr,
ram_write_o => ram_we,
hlt_o => halt,
out_val_o => out_o,
debug_sel_i => cpu_debug_sel, -- CPU debug register select
debug_out_o => cpu_debug_out -- CPU debug register data
);
halt_o <= halt;
-- instantiate RAM
-- NOTE: FPGA BRAM is clocked, not asynchronous. So we clock it on falling edge (so data will be ready for CPU on next rising edge).
bram: entity work.ram
generic map(
addrwidth => 4,
datawidth => 8
)
port map(
clk_i => clk,
we_i => ram_we,
addr_i => ram_addr,
write_i => data_cpu_to_ram,
read_o => data_ram_to_cpu
);
-- simple "command processor" to print CPU state trace as text via serial
DOTRACE: if (C_TRACE) generate
TRACE: entity work.cpu_trace
port map (
clk_i => clk,
clk_en_i => clk_en,
rst_i => rst,
halt_i => halt,
busy_o => trace_busy,
tx_busy_i => tx_busy,
tx_write_o => tx_write,
tx_data_o => tx_data,
debug_sel_o => cpu_debug_sel, -- CPU debug register select
debug_val_i => cpu_debug_out -- CPU debug register data
);
-- simple transmit only serial UART for CPU trace output
UART: entity work.tx_uart
generic map(
C_SYSTEM_HZ => C_SYSTEM_HZ,
C_BPS => C_BPS, -- baud rate (8-bit, no parity, 1 stop bit)
C_AUTOBAUD => C_AUTOBAUD
)
port map(
rst_i => rst, -- reset
clk_i => clk, -- FPGA clock
tx_o => tx_o, -- TX out
rx_i => rx_i, -- RX in
busy_o => tx_busy, -- high when UART busy transmitting
data_i => tx_data, -- data to send
we_i => tx_write -- set high to send byte (when busy_o is low)
);
end generate DOTRACE;
END ARCHITECTURE RTL;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: <NAME> ----
---- <EMAIL> ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 <NAME> ----
---- <EMAIL> ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
--
-- $Date: 2009-02-04 20:17:34 $
-- $Revision: 1.17 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.16 2009/01/20 20:40:36 rherveille
-- Fixed type iscl_oen instead of scl_oen
--
-- Revision 1.15 2009/01/20 10:34:51 rherveille
-- Added SCL clock synchronization logic
-- Fixed slave_wait signal generation
--
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
signal clk_en : std_logic; -- statemachine clock enable
signal scl_sync, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk, nReset)
begin
if (nReset = '0') then
dscl_oen <= '0';
elsif (clk'event and clk = '1') then
dscl_oen <= iscl_oen;
end if;
end process;
-- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
-- slave_wait remains asserted until the slave releases SCL
process (clk, nReset)
begin
if (nReset = '0') then
slave_wait <= '0';
elsif (clk'event and clk = '1') then
slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
end if;
end process;
-- master drives SCL high, but another master pulls it low
-- master start counting down its low cycle now (clock synchronization)
scl_sync <= dSCL and not sSCL and iscl_oen;
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL
signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- capture SCL and SDA
capture_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
cSCL <= "00";
cSDA <= "00";
elsif (clk'event and clk = '1') then
if (rst = '1') then
cSCL <= "00";
cSDA <= "00";
else
cSCL <= (cSCL(0) & scl_i);
cSDA <= (cSDA(0) & sda_i);
end if;
end if;
end process capture_scl_sda;
-- filter SCL and SDA; (attempt to) remove glitches
filter_divider: process(clk, nReset)
begin
if (nReset = '0') then
filter_cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if ( (rst = '1') or (ena = '0') ) then
filter_cnt <= (others => '0');
elsif (filter_cnt = 0) then
filter_cnt <= clk_cnt(15 downto 2);
else
filter_cnt <= filter_cnt -1;
end if;
end if;
end process filter_divider;
filter_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (filter_cnt = 0) then
fSCL <= (fSCL(1 downto 0) & cSCL(1));
fSDA <= (fSDA(1 downto 0) & cSDA(1));
end if;
end if;
end process filter_scl_sda;
-- generate filtered SCL and SDA signals
scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
sSCL <= (fSCL(2) and fSCL(1)) or
(fSCL(2) and fSCL(0)) or
(fSCL(1) and fSCL(0));
sSDA <= (fSDA(2) and fSDA(1)) or
(fSDA(2) and fSDA(0)) or
(fSDA(1) and fSDA(0));
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process scl_sda;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
else
ial <= (sda_chk and not sSDA and isda_oen);
end if;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk, nReset)
begin
if (nReset = '0') then
dout <= '0';
elsif (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= sSDA;
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA yet
-- Allow some more time for SDA and SCL to settle
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
<reponame>mkotormus/G3_OrchestraConductorDemo
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`protect end_protected
|
<gh_stars>0
library IEEE;
use ieee.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.Constants.all;
entity TB_DECODE_COMPARATOR is
end TB_DECODE_COMPARATOR;
architecture TEST_TB_DECODE_COMPARATOR of TB_DECODE_COMPARATOR is
COMPONENT DECODE_COMPARATOR IS
PORT(
DATA1 : in STD_LOGIC_VECTOR(31 downto 0);
DATA2 : in STD_LOGIC_VECTOR(31 DOWNTO 0);
DATAOUT: OUT STD_LOGIC
);
END COMPONENT;
SIGNAL D1 : STD_LOGIC_VECTOR(31 downto 0) ;
SIGNAL D2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL DOUT : STD_LOGIC;
begin
COMP:DECODE_COMPARATOR
port map (D1,D2,DOUT );
D2<=x"FFA003EF", x"FFC003FE" after 8 ns ,(others => '1') after 12 ns;
D1<=x"FFA003EF", x"FFC003FF" after 8 ns ,(others => '1') after 12 ns;
end TEST_TB_DECODE_COMPARATOR ;
|
<reponame>moehawamdeh/computer-organization-lab
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;
use work.constants.BUS_WIDTH;
entity shr_register is
generic(N:integer:=BUS_WIDTH);
port( Din: in std_logic_vector(N-1 downto 0);
ld,en,clk: in std_logic;
Dout: buffer std_logic_vector(N-1 downto 0)
);
end;
architecture shr_register of shr_register is
begin
process(clk)
begin
if(rising_edge(clk)) then
if ld='1' then
Dout<= Din;
elsif en='1' then
Dout<= '0'&Dout(N-1 downto 1);
else Dout<= Dout;
end if;
else Dout<= Dout;
end if;
end process;
end;
|
<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.DLX_package.all;
-- rounding mode: 00 --> minus infinity
-- 01 --> plus infinity
-- 10 --> Zero
-- 11 --> Nearest
ENTITY rounding IS
PORT( result : IN std_logic_vector(47 downto 0);
rounding_mode : IN std_logic_vector(1 downto 0);
result_sign : IN std_logic;
rounded_result : OUT std_logic_vector(23 downto 0);
exp_incr : OUT std_logic);
END ENTITY;
ARCHITECTURE Behavioral OF rounding IS
signal product : std_logic_vector(47 downto 0);
signal sticky_bit : std_logic;
signal round_bit : std_logic;
signal exp_incr_partial_1, exp_incr_partial_2 : std_logic;
signal rounded_res : std_logic_vector(23 downto 0);
BEGIN
round_proc : process(result)
begin
product <= result;
sticky_bit <= or_reduce(result(21 downto 0));
round_bit <= result(22);
exp_incr_partial_1 <='0';
if result(47) = '0' then
product(47 downto 24) <= result(46 downto 23);
else
sticky_bit <= or_reduce(result(22 downto 0));
round_bit <= result(23);
exp_incr_partial_1 <= '1';
end if;
end process;
rounding_mode_proc: process(product, rounding_mode, result_sign, sticky_bit, round_bit)
begin
rounded_res <= product(47 downto 24);
case rounding_mode is
when "00" => if result_sign = '1' then
if round_bit = '1' or sticky_bit = '1' then
rounded_res <= std_logic_vector(unsigned(product(47 downto 24))+1);
end if;
end if;
when "01" => if result_sign = '0' then
if round_bit = '1' or sticky_bit = '1' then
rounded_res <= std_logic_vector(unsigned(product(47 downto 24))+1);
end if;
end if;
when "10" => rounded_res <= product(47 downto 24);
when others => if round_bit = '1' and (sticky_bit = '1' or product(24) = '1') then
rounded_res <= std_logic_vector(unsigned(product(47 downto 24))+1);
end if;
end case;
end process;
exp_incr_partial_2 <= not(or_reduce(rounded_res));
exp_incr <= exp_incr_partial_1 or exp_incr_partial_2;
rounded_result <= rounded_res;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_types.all;
entity toplevel is
generic (
MEMORY_SIZE : positive := (384*1024);
RAM_INIT_FILE : string := "firmware.hex";
RESET_LOW : boolean := true;
CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000;
USE_DRAM : boolean := false;
DRAM_SIZE : integer := 0;
DISABLE_FLATTEN_CORE : boolean := false;
UART_IS_16550 : boolean := true
);
port(
ext_clk : in std_ulogic;
ext_rst : in std_ulogic;
-- UART0 signals:
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
-- DRAM main data wishbone connection
-- Remove the upper two address bits?
signal wb_dram_in_adr : out std_ulogic_vector(28 downto 0);
signal wb_dram_in_dat : out std_ulogic_vector(63 downto 0);
signal wb_dram_in_cyc : out std_ulogic;
signal wb_dram_in_stb : out std_ulogic;
signal wb_dram_in_sel : out std_ulogic_vector(7 downto 0);
signal wb_dram_in_we : out std_ulogic;
signal wb_dram_out_dat : in std_ulogic_vector(63 downto 0)
:= x"FFFFFFFFFFFFFFFF";
signal wb_dram_out_ack : in std_ulogic := '0';
signal wb_dram_out_stall : in std_ulogic := '0'
);
end entity toplevel;
architecture behaviour of toplevel is
-- Reset signals:
signal soc_rst : std_ulogic;
signal pll_rst : std_ulogic;
-- Internal clock signals:
signal system_clk : std_ulogic;
signal system_clk_locked : std_ulogic;
-- DRAM main data wishbone connection
signal wb_dram_in : wishbone_master_out;
signal wb_dram_out : wishbone_slave_out;
begin
reset_controller: entity work.soc_reset
generic map(
RESET_LOW => RESET_LOW
)
port map(
ext_clk => ext_clk,
pll_clk => system_clk,
pll_locked_in => system_clk_locked,
ext_rst_in => ext_rst,
pll_rst_out => pll_rst,
rst_out => soc_rst
);
clkgen: entity work.clock_generator
generic map(
CLK_INPUT_HZ => CLK_INPUT,
CLK_OUTPUT_HZ => CLK_FREQUENCY
)
port map(
ext_clk => ext_clk,
pll_rst_in => pll_rst,
pll_clk_out => system_clk,
pll_locked_out => system_clk_locked
);
-- Main SoC
soc0: entity work.soc
generic map(
MEMORY_SIZE => MEMORY_SIZE,
RAM_INIT_FILE => RAM_INIT_FILE,
SIM => false,
CLK_FREQ => CLK_FREQUENCY,
HAS_DRAM => USE_DRAM,
DRAM_SIZE => DRAM_SIZE,
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
UART0_IS_16550 => UART_IS_16550
)
port map (
system_clk => system_clk,
rst => soc_rst,
uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out
);
has_dram: if USE_DRAM generate
begin
-- Make the address compatible with "generic" RAM:
-- Cut off the segment prefix and narrow the address to word
-- granularity.
wb_dram_in_adr(28 downto 27) <= "00";
wb_dram_in_adr(26 downto 0) <= wb_dram_in.adr(29 downto 3);
wb_dram_in_dat <= wb_dram_in.dat;
wb_dram_in_cyc <= wb_dram_in.cyc;
wb_dram_in_stb <= wb_dram_in.stb;
wb_dram_in_sel <= wb_dram_in.sel;
wb_dram_in_we <= wb_dram_in.we;
wb_dram_out.ack <= wb_dram_out_ack;
wb_dram_out.dat <= wb_dram_out_dat;
wb_dram_out.stall <= wb_dram_out_stall;
end generate;
end architecture behaviour;
|
<filename>Implementations/hardware/remus-hw-pkg/ConstGen.vhd<gh_stars>0
----------------------------------------------------------------------------------
-- COPYRIGHT (c) 2016 ALL RIGHT RESERVED
--
-- COMPANY: Ruhr-Universitaet Bochum, Chair for Embedded Security
-- AUTHOR: <NAME>
--
-- CREATE DATA: 17/11/2016
-- MODULE NAME: ConstGenerator
--
-- REVISION: 1.00 - File created
--
-- LICENCE: Please look at licence.txt
-- USAGE INFORMATION: Please look at readme.txt. If licence.txt or readme.txt
-- are missing or if you have questions regarding the code
-- please contact <NAME> (<EMAIL>)
-- or <NAME> (<EMAIL>).
--
-- THIS CODE AND INFORMATION ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
-- KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
-- PARTICULAR PURPOSE.
----------------------------------------------------------------------------------
-- IMPORTS
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- ENTITY
----------------------------------------------------------------------------------
ENTITY ConstGen IS
PORT (CLK : IN STD_LOGIC;
INIT : IN STD_LOGIC;
CONST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ConstGen;
-- ARCHITECTURE : DATAFLOW
----------------------------------------------------------------------------------
ARCHITECTURE Dataflow OF ConstGen IS
-- SIGNALS --------------------------------------------------------------------
SIGNAL STATE, UPDATE : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- DATAFLOW
----------------------------------------------------------------------------------
BEGIN
-- STATE ----------------------------------------------------------------------
REG : PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
IF (INIT = '1') THEN
STATE <= "000000";
ELSE
STATE <= UPDATE;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
-- UPDATE FUNCTION ------------------------------------------------------------
UPDATE(5 DOWNTO 0) <= STATE(4 DOWNTO 0) & (STATE(5) XNOR STATE(4));
-------------------------------------------------------------------------------
-- CONSTANT -------------------------------------------------------------------
CONST <= UPDATE;
-------------------------------------------------------------------------------
END Dataflow;
|
<gh_stars>0
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/10/2021 12:31:19 PM
-- Design Name:
-- Module Name: aggregator_AXIfull - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.config.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aggregator_AXIfull is
Port (
write_ack_time: in std_logic;
catch_time: in std_logic;
write_ack_event: in std_logic;
catch_event: in std_logic;
count_out_event: in std_logic_vector (31 downto 0);
count_out_time: in std_logic_vector (31 downto 0);
event_attr: in std_logic_Vector (1 downto 0);
result: out std_logic_vector(size_AXIfull_sniffer_result-1 downto 0);
catch: out std_logic;
write_ack: out std_logic
);
end aggregator_AXIfull;
architecture Behavioral of aggregator_AXIfull is
constant sniffer_id: std_logic_vector (1 downto 0) := "10";
constant metric_id: std_logic_vector (1 downto 0) := "10";
begin
-- only event here
result <= event_attr & metric_id & sniffer_id & count_out_event & count_out_time;
write_ack <= write_ack_time and write_ack_event;
catch <= catch_time and catch_event;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;
use work.ring_bus_pack.all;
entity word_tap is
end;
architecture tb of word_tap is
begin
process
begin
test_plan(16, "bus words");
test_equal(cmd_word_9b(IDLE, 0).fr, '1', "cmd8 has fr 1");
test_equal(data_word_9b(x"12" & '0').fr, '0', "data9 has fr 0");
test_equal(cmd_word_8b(IDLE, 0).fr, '1', "cmd8 has fr 1");
test_equal(data_word_8b(x"12").fr, '0', "data9 has fr 0");
test_ok(to_cmd(cmd_word_8b(IDLE, 0).d) = IDLE, "cmd8 is IDLE");
test_ok(to_cmd(cmd_word_8b(WRITE, 2).d) = WRITE, "cmd8 is WRITE");
test_equal(to_hops(cmd_word_8b(IDLE, 0).d), 0, "cmd8 zero hops");
test_equal(to_hops(cmd_word_8b(WRITE, 2).d), 2, "cmd8 hops");
test_ok(to_cmd(cmd_word_9b(IDLE, 0).d) = IDLE, "cmd9 is IDLE");
test_ok(to_cmd(cmd_word_9b(WRITE, 2).d) = WRITE, "cmd9 is WRITE");
test_equal(to_hops(cmd_word_9b(IDLE, 0).d), 0, "cmd9 zero hops");
test_equal(to_hops(cmd_word_9b(WRITE, 2).d), 2, "cmd9 hops");
test_ok(is_idle(cmd_word_9b(IDLE, 0)), "cmd9 is_idle IDLE");
test_ok(not is_idle(cmd_word_9b(READ, 0)), "cmd9 is_idle READ");
test_ok(is_idle(cmd_word_8b(IDLE, 0)), "cmd8 is_idle IDLE");
test_ok(not is_idle(cmd_word_8b(READ, 0)), "cmd8 is_idle READ");
wait;
end process;
end tb;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 2019 <NAME>. All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_prbs23 is
end entity tb_prbs23;
architecture tb_prbs23_rtl of tb_prbs23 is
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal o_prbs1 : std_logic;
signal o_prbs2 : std_logic;
signal o_prbs1_delay : std_logic;
begin -- architecture tb_prbs23_rtl
-- Component instantiations
DUT1 : entity work.prbs23
port map (
clk => clk,
rst => rst,
o_prbs => o_prbs1);
DUT2 : entity work.prbs23_small
port map (
clk => clk,
o_prbs => o_prbs2);
-- Make a delay-matched version for comparison
o_prbs1_delay <= transport o_prbs1 after 380 ns;
-------------------------------------------------------------------------------
-- System clock generation
clk_gen : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process clk_gen;
-----------------------------------------------------------------------------
-- Reset generation
rst_gen : process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
wait;
end process rst_gen;
end architecture tb_prbs23_rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity g8_to_rgb888 is
port (
g8 : in std_logic_vector(7 downto 0);
rgb888 : out std_logic_vector(23 downto 0)
);
end g8_to_rgb888;
architecture Behavioral of g8_to_rgb888 is
begin
rgb888(23 downto 16) <= g8;
rgb888(15 downto 8) <= g8;
rgb888(7 downto 0) <= g8;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.consts.ALL;
use IEEE.NUMERIC_STD.ALL;
entity EX is
port (
fatal_o: out std_logic;
alu_op_i: in alu_op_t;
alu_v1_i: in dword;
alu_v2_i: in dword;
regwr_en_i: in std_logic;
regwr_en_o: out std_logic;
regwr_addr_i: in reg_addr_t;
regwr_addr_o: out reg_addr_t;
mod_lr_i: in std_logic;
mod_lr_o: out std_logic;
alu_data_o: out dword;
jb_en_i: in std_logic;
jb_en_o: out std_logic;
jb_pc_o: out mem_addr_t;
ram_mode_i: in rammode_t;
ram_mode_o: out rammode_t;
ram_wdata_i: in dword;
ram_wdata_o: out dword
);
end EX;
architecture behave of EX is
begin
regwr_en_o <= regwr_en_i;
regwr_addr_o <= regwr_addr_i;
mod_lr_o <= mod_lr_i;
ram_mode_o <= ram_mode_i;
ram_wdata_o <= ram_wdata_i;
jb_en_o <= jb_en_i;
process (all)
begin
alu_data_o <= (others=> '0');
fatal_o <= '0';
jb_pc_o <= (others=> '0');
case alu_op_i is
when ALUOP_ADD =>
alu_data_o <= std_logic_vector(unsigned(alu_v1_i) + unsigned(alu_v2_i));
if (jb_en_i = '1') then
jb_pc_o <= alu_data_o;
end if;
when ALUOP_SUB =>
alu_data_o <= std_logic_vector(unsigned(alu_v1_i) - unsigned(alu_v2_i));
when ALUOP_MUL =>
alu_data_o <= std_logic_vector(unsigned(alu_v1_i) * unsigned(alu_v2_i))(31 downto 0);
when ALUOP_AND =>
alu_data_o <= alu_v1_i and alu_v2_i;
when ALUOP_OR =>
alu_data_o <= alu_v1_i or alu_v2_i;
when ALUOP_XOR =>
alu_data_o <= alu_v1_i xor alu_v2_i;
when ALUOP_LOA =>
alu_data_o <= std_logic_vector(unsigned(alu_v1_i) + unsigned(alu_v2_i));
when ALUOP_STO =>
-- see id:TODO: why this?
alu_data_o <= std_logic_vector(unsigned(alu_v1_i) + unsigned(alu_v2_i));
when ALUOP_SHR =>
alu_data_o <= to_stdlogicvector(to_bitvector(alu_v1_i) srl to_integer(unsigned(alu_v2_i)));
when ALUOP_SHL =>
alu_data_o <= to_stdlogicvector(to_bitvector(alu_v1_i) sll to_integer(unsigned(alu_v2_i)));
when ALUOP_LUI =>
alu_data_o <= alu_v2_i;
when others =>
fatal_o <= '1';
end case;
end process;
end behave;
|
-- Author: <NAME>
-- Date: 2016.04.28
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity video_framer is
port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
res_sel : in STD_LOGIC;
DE : out STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC);
end video_framer;
architecture behavioral of video_framer is
type hregion_type is (HINIT, HSYNC, HBACK, HACTIVE, HFRONT);
type vregion_type is (VINIT, VSYNC, VBACK, VACTIVE, VFRONT);
signal c_hr, n_hr: hregion_type;
signal c_vr, n_vr: vregion_type;
signal hpos, vpos: integer := 0;
constant hsync_px : integer := 32;
constant hback_px : integer := 80;
constant hfront_px : integer := 48;
constant vsync_lines : integer := 6;
constant vback_lines : integer := 26;
constant vfront_lines : integer := 3;
-- Resolution mode definition
constant res_width_mode0 : integer := 1920;
constant res_height_mode0 : integer := 1200;
constant res_width_mode1 : integer := 1280;
constant res_height_mode1 : integer := 1024;
signal hactive_px : integer; -- Used to store width resolution
signal vactive_lines : integer; -- Used to store height resolution
signal hsync_pos, hback_pos, hactive_pos, hfront_pos, htotal : integer;
signal vsync_pos, vback_pos, vactive_pos, vfront_pos, vtotal : integer;
begin
region_update:
process (clk, rst, en, res_sel)
begin
if (rst = '1') then
c_hr <= HINIT;
c_vr <= VINIT;
elsif (en = '1') then
if (rising_edge (clk)) then
c_hr <= n_hr;
c_vr <= n_vr;
end if;
end if;
end process region_update;
pos_update: -- Update hpos and vpos
process (clk, rst, en, res_sel)
variable res_width, res_height : integer;
variable c_hpos, c_vpos : integer;
begin
if (rst = '1') then
hpos <= 0;
vpos <= 1;
elsif (en = '1') then
if (rising_edge (clk)) then
-- Set resolution if VINIT & HINIT
if ((c_hr = HINIT) and (c_vr = VINIT)) then
if (res_sel = '0') then -- 1920 x 1200
res_width := res_width_mode0; res_height := res_height_mode0;
else -- 1280 x 1024
res_width := res_width_mode1; res_height := res_height_mode1;
end if;
hactive_px <= res_width; vactive_lines <= res_height; -- Set resolution
hsync_pos <= 1;
hback_pos <= hsync_px;
hactive_pos <= hsync_px + hback_px;
hfront_pos <= hsync_px + hback_px + res_width;
htotal <= hsync_px + hback_px + res_width + hfront_px;
vsync_pos <= 1;
vback_pos <= vsync_lines;
vactive_pos <= vsync_lines + vback_lines;
vfront_pos <= vsync_lines + vback_lines + res_height;
vtotal <= vsync_lines + vback_lines + res_height + vfront_lines;
end if;
-- Increment hpos & vpos
c_hpos := hpos;
c_vpos := vpos;
if (c_hpos = htotal) then
if (c_vpos = vtotal) then
vpos <= 1; -- Back to first line
else
vpos <= vpos + 1; -- Go to next line
end if;
hpos <= 1; -- Back to left side
else
hpos <= hpos + 1; -- Go to next pixel
end if;
end if;
end if;
end process pos_update;
hs_process:
process (c_hr, hpos)
begin
case c_hr is
when HINIT =>
HS <= '0'; -- now
n_hr <= HSYNC;
when HSYNC =>
HS <= '1';
if (hpos = hback_pos) then n_hr <= HBACK;
else n_hr <= HSYNC;
end if;
when HBACK =>
HS <= '0';
if (hpos = hactive_pos) then n_hr <= HACTIVE;
else n_hr <= HBACK;
end if;
when HACTIVE =>
-- HS <= '0';
if (hpos = hfront_pos) then n_hr <= HFRONT;
else n_hr <= HACTIVE;
end if;
when HFRONT =>
-- HS <= '0';
if (hpos = htotal) then n_hr <= HSYNC;
else n_hr <= HFRONT;
end if;
end case;
end process hs_process;
vs_process:
process (c_vr, vpos, hpos)
begin
case c_vr is
when VINIT =>
VS <= '1';
n_vr <= VSYNC;
when VSYNC =>
VS <= '0'; -- Low polarity
if ((vpos = vback_pos) and (hpos = htotal)) then n_vr <= VBACK;
else n_vr <= VSYNC;
end if;
when VBACK =>
VS <= '1';
if ((vpos = vactive_pos) and (hpos = htotal)) then n_vr <= VACTIVE;
else n_vr <= VBACK;
end if;
when VACTIVE =>
-- VS <= '0';
if ((vpos = vfront_pos) and (hpos = htotal)) then n_vr <= VFRONT;
else n_vr <= VACTIVE;
end if;
when VFRONT =>
-- VS <= '0';
if ((vpos = vtotal) and (hpos = htotal)) then n_vr <= VSYNC;
else n_vr <= VFRONT;
end if;
end case;
end process vs_process;
de_process:
process (c_hr, c_vr)
begin
case c_vr is
when VACTIVE =>
case c_hr is
when HACTIVE =>
DE <= '1';
when others =>
DE <= '0';
end case;
when others =>
DE <= '0';
end case;
end process de_process;
end behavioral;
|
<filename>fpga/ip_export/eth100_link_tx_v3/src/bytestream_to_rmii.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- Encodes MAC bytestream to RMII
--
entity bytestream_to_rmii is
port (
clk : in std_logic; -- RMII ref_clk
rst : in std_logic;
-- RMII
txen : out std_logic;
txdt : out std_logic_vector(1 downto 0);
-- internal byte stream
t_dv : in std_logic; -- kept high so long as we are transmitting a frame
t_str_dt : in std_logic; -- a pulse when t_dt is valid
t_dt : in std_logic_vector(7 downto 0) -- 1-byte send data, valid only during r_str_dt is active
);
end entity bytestream_to_rmii;
architecture rtl of bytestream_to_rmii is
subtype count_t is integer range 0 to 3;
-- internal register type
type registers_t is record
en : std_logic;
dt : std_logic_vector(7 downto 0);
dv : std_logic_vector(3 downto 0);
end record;
signal r, rin : registers_t;
begin
comb: process (r, rst, t_dv, t_str_dt, t_dt)
variable v : registers_t;
begin
v := r;
if v.en = '0' then
-- quiet, not sending
v.dv := (others => '0');
-- startup if t_dv and strobe are active at the same time
if (t_dv and t_str_dt) = '1' then
-- startup!
v.dt := t_dt;
v.dv := (others => '1');
v.en := '1';
end if;
else
-- ongoing transmission
-- shift data - move bits to LSB
v.dt := "00" & v.dt(7 downto 2);
v.dv := '0' & v.dv(3 downto 1);
if t_str_dt = '1' then
v.dt := t_dt;
v.dv := (others => '1');
end if;
if t_dv = '0' then
-- end of byte stream; finish current byte first
if v.dv = "0000" then
-- last byte finished, go idle
v.en := '0';
end if;
end if;
end if;
if rst = '1' then
v.en := '0';
v.dt := (others => '0');
v.dv := (others => '0');
end if;
rin <= v;
end process;
ff: process (clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- set output signals:
-- TX data - LSB of the internal buffer
txdt <= r.dt(1 downto 0);
txen <= r.en;
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- File Name: /home/ts/Dokumente/ultrazohm_testbench/ultrazohm_test/ultrazohm_sw/ip_cores/simscapeHDL_example_v1_0/hdlsrc/gmStateSpaceHDL_HalfWaveRectifier_HDL/uz_simscapeExample_src_nfp_relop_single.vhd
-- Created: 2021-04-19 11:33:22
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: uz_simscapeExample_src_nfp_relop_single
-- Source Path: gmStateSpaceHDL_HalfWaveRectifier_HDL/Simscape_system/HDL Subsystem/nfp_relop_single
-- Hierarchy Level: 1
--
-- {Latency Strategy = "Min"}
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY uz_simscapeExample_src_nfp_relop_single IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
nfp_in1 : IN std_logic_vector(31 DOWNTO 0); -- ufix32
nfp_in2 : IN std_logic_vector(31 DOWNTO 0); -- ufix32
nfp_out1 : OUT std_logic -- ufix1
);
END uz_simscapeExample_src_nfp_relop_single;
ARCHITECTURE rtl OF uz_simscapeExample_src_nfp_relop_single IS
-- Signals
SIGNAL Constant8_out1 : std_logic; -- ufix1
SIGNAL Constant7_out1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Relational_Operator_relop1 : std_logic;
SIGNAL Delay13_out1 : std_logic;
SIGNAL Logical_Operator2_out1 : std_logic;
SIGNAL Logical_Operator_out1 : std_logic; -- ufix1
SIGNAL Add_out1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Delay12_out1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Add_add_cast : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL nfp_in1_unsigned : unsigned(31 DOWNTO 0); -- ufix32
SIGNAL AS : std_logic; -- ufix1
SIGNAL AE : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL AM : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL Delay2_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Constant2_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Relational_Operator5_relop1 : std_logic;
SIGNAL Constant1_out1 : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL Delay3_out1 : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL Relational_Operator4_relop1 : std_logic;
SIGNAL nfp_in2_unsigned : unsigned(31 DOWNTO 0); -- ufix32
SIGNAL BS : std_logic; -- ufix1
SIGNAL BE : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL BM : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL Delay4_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Relational_Operator6_relop1 : std_logic;
SIGNAL Delay5_out1 : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL Relational_Operator2_relop1 : std_logic;
SIGNAL Constant_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Relational_Operator3_relop1 : std_logic;
SIGNAL Relational_Operator1_relop1 : std_logic;
SIGNAL Logical_Operator_out1_1 : std_logic;
SIGNAL Delay_out1 : std_logic; -- ufix1
SIGNAL Delay1_out1 : std_logic; -- ufix1
SIGNAL Relational_Operator2_relop1_1 : std_logic;
SIGNAL Relational_Operator4_relop1_1 : std_logic;
SIGNAL Relational_Operator6_relop1_1 : std_logic;
SIGNAL Relational_Operator5_relop1_1 : std_logic;
SIGNAL Compare_To_Constant_out1 : std_logic;
SIGNAL Logical_Operator3_out1 : std_logic;
SIGNAL switch_compare_1 : std_logic;
SIGNAL Relational_Operator1_relop1_1 : std_logic;
SIGNAL Relational_Operator3_relop1_1 : std_logic;
SIGNAL Logical_Operator1_out1 : std_logic;
SIGNAL Logical_Operator2_out1_1 : std_logic;
SIGNAL Logical_Operator7_out1 : std_logic;
SIGNAL Logical_Operator5_out1 : std_logic;
SIGNAL Logical_Operator1_out1_1 : std_logic;
SIGNAL Logical_Operator4_out1 : std_logic;
SIGNAL Logical_Operator1_out1_2 : std_logic;
SIGNAL Logical_Operator5_out1_1 : std_logic;
SIGNAL Logical_Operator2_out1_2 : std_logic;
SIGNAL Logical_Operator3_out1_1 : std_logic;
SIGNAL Logical_Operator_out1_2 : std_logic;
SIGNAL Logical_Operator6_out1 : std_logic;
SIGNAL Logical_Operator4_out1_1 : std_logic;
SIGNAL Logical_Operator6_out1_1 : std_logic;
SIGNAL Switch_out1 : std_logic;
SIGNAL Logical_Operator4_out1_2 : std_logic;
SIGNAL Logical_Operator5_out1_2 : std_logic;
SIGNAL Constant1_out1_1 : std_logic;
SIGNAL Switch1_out1 : std_logic;
BEGIN
Constant8_out1 <= '1';
Constant7_out1 <= to_unsigned(16#1#, 3);
Delay13_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay13_out1 <= '0';
ELSIF enb = '1' THEN
Delay13_out1 <= Relational_Operator_relop1;
END IF;
END IF;
END PROCESS Delay13_process;
Logical_Operator2_out1 <= NOT Delay13_out1;
Logical_Operator_out1 <= Constant8_out1 AND Logical_Operator2_out1;
Delay12_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay12_out1 <= to_unsigned(16#0#, 3);
ELSIF enb = '1' THEN
Delay12_out1 <= Add_out1;
END IF;
END IF;
END PROCESS Delay12_process;
Add_add_cast <= '0' & '0' & Logical_Operator_out1;
Add_out1 <= Delay12_out1 + Add_add_cast;
Relational_Operator_relop1 <= '1' WHEN Add_out1 > Constant7_out1 ELSE
'0';
nfp_in1_unsigned <= unsigned(nfp_in1);
-- Split 32 bit word into FP sign, exponent, mantissa
AS <= nfp_in1_unsigned(31);
AE <= nfp_in1_unsigned(30 DOWNTO 23);
AM <= nfp_in1_unsigned(22 DOWNTO 0);
Delay2_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay2_out1 <= to_unsigned(16#00#, 8);
ELSIF enb = '1' THEN
Delay2_out1 <= AE;
END IF;
END IF;
END PROCESS Delay2_process;
Constant2_out1 <= to_unsigned(16#FF#, 8);
Relational_Operator5_relop1 <= '1' WHEN Delay2_out1 = Constant2_out1 ELSE
'0';
Constant1_out1 <= to_unsigned(16#000000#, 23);
Delay3_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay3_out1 <= to_unsigned(16#000000#, 23);
ELSIF enb = '1' THEN
Delay3_out1 <= AM;
END IF;
END IF;
END PROCESS Delay3_process;
Relational_Operator4_relop1 <= '1' WHEN Constant1_out1 = Delay3_out1 ELSE
'0';
nfp_in2_unsigned <= unsigned(nfp_in2);
-- Split 32 bit word into FP sign, exponent, mantissa
BS <= nfp_in2_unsigned(31);
BE <= nfp_in2_unsigned(30 DOWNTO 23);
BM <= nfp_in2_unsigned(22 DOWNTO 0);
Delay4_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay4_out1 <= to_unsigned(16#00#, 8);
ELSIF enb = '1' THEN
Delay4_out1 <= BE;
END IF;
END IF;
END PROCESS Delay4_process;
Relational_Operator6_relop1 <= '1' WHEN Delay4_out1 = Constant2_out1 ELSE
'0';
Delay5_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay5_out1 <= to_unsigned(16#000000#, 23);
ELSIF enb = '1' THEN
Delay5_out1 <= BM;
END IF;
END IF;
END PROCESS Delay5_process;
Relational_Operator2_relop1 <= '1' WHEN Constant1_out1 = Delay5_out1 ELSE
'0';
Constant_out1 <= to_unsigned(16#00#, 8);
Relational_Operator3_relop1 <= '1' WHEN Constant_out1 = Delay4_out1 ELSE
'0';
Relational_Operator1_relop1 <= '1' WHEN Constant_out1 = Delay2_out1 ELSE
'0';
Logical_Operator_out1_1 <= Relational_Operator4_relop1 AND (Relational_Operator1_relop1 AND (Relational_Operator2_relop1 AND Relational_Operator3_relop1));
Delay_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay_out1 <= '0';
ELSIF enb = '1' THEN
Delay_out1 <= AS;
END IF;
END IF;
END PROCESS Delay_process;
Delay1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay1_out1 <= '0';
ELSIF enb = '1' THEN
Delay1_out1 <= BS;
END IF;
END IF;
END PROCESS Delay1_process;
Relational_Operator2_relop1_1 <= '1' WHEN Delay_out1 = Delay1_out1 ELSE
'0';
Relational_Operator4_relop1_1 <= '1' WHEN Delay2_out1 = Delay4_out1 ELSE
'0';
Relational_Operator6_relop1_1 <= '1' WHEN Delay3_out1 = Delay5_out1 ELSE
'0';
Relational_Operator5_relop1_1 <= '1' WHEN Delay_out1 < Delay1_out1 ELSE
'0';
Compare_To_Constant_out1 <= '1' WHEN Delay1_out1 = '1' ELSE
'0';
Logical_Operator3_out1 <= Compare_To_Constant_out1 AND Relational_Operator2_relop1_1;
switch_compare_1 <= '1' WHEN Logical_Operator3_out1 > '0' ELSE
'0';
Relational_Operator1_relop1_1 <= '1' WHEN Delay2_out1 > Delay4_out1 ELSE
'0';
Relational_Operator3_relop1_1 <= '1' WHEN Delay3_out1 > Delay5_out1 ELSE
'0';
Logical_Operator1_out1 <= Relational_Operator4_relop1_1 AND Relational_Operator3_relop1_1;
Logical_Operator2_out1_1 <= Relational_Operator1_relop1_1 OR Logical_Operator1_out1;
Logical_Operator7_out1 <= Relational_Operator2_relop1_1 AND Logical_Operator2_out1_1;
Logical_Operator5_out1 <= NOT Logical_Operator7_out1;
Logical_Operator1_out1_1 <= NOT Relational_Operator_relop1;
Logical_Operator4_out1 <= NOT Relational_Operator4_relop1;
Logical_Operator1_out1_2 <= Relational_Operator5_relop1 AND Logical_Operator4_out1;
Logical_Operator5_out1_1 <= NOT Relational_Operator2_relop1;
Logical_Operator2_out1_2 <= Relational_Operator6_relop1 AND Logical_Operator5_out1_1;
Logical_Operator3_out1_1 <= Logical_Operator1_out1_2 OR Logical_Operator2_out1_2;
Logical_Operator_out1_2 <= Logical_Operator1_out1_1 OR Logical_Operator3_out1_1;
Logical_Operator6_out1 <= Relational_Operator6_relop1_1 AND (Relational_Operator2_relop1_1 AND Relational_Operator4_relop1_1);
Logical_Operator4_out1_1 <= Logical_Operator_out1_1 OR Logical_Operator6_out1;
Logical_Operator6_out1_1 <= NOT Logical_Operator4_out1_1;
Switch_out1 <= Logical_Operator7_out1 WHEN switch_compare_1 = '0' ELSE
Logical_Operator5_out1;
Logical_Operator4_out1_2 <= Relational_Operator5_relop1_1 OR Switch_out1;
Logical_Operator5_out1_2 <= Logical_Operator6_out1_1 AND Logical_Operator4_out1_2;
Constant1_out1_1 <= '0';
Switch1_out1 <= Logical_Operator5_out1_2 WHEN Logical_Operator_out1_2 = '0' ELSE
Constant1_out1_1;
nfp_out1 <= Switch1_out1;
END rtl;
|
--
-- tapram.vhd
-- Tap-RAM for filters
-- Revision 1.00
--
-- Copyright (c) 2006 <NAME> (ESE Artists' factory)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tapram is
generic (
MSBI : integer
);
port (
clk : in std_logic;
tapidx : in integer range 0 to 4;
wr : in std_logic;
tapin : in std_logic_vector(MSBI downto 0);
tapout : out std_logic_vector(MSBI downto 0)
);
end tapram;
architecture RTL of tapram is
type Mem is array (0 to 4) of std_logic_vector(MSBI downto 0);
signal TapMem : Mem;
begin
process (clk)
begin
if clk'event and clk ='1' then
tapout <= TapMem(tapidx);
if wr = '1' then
TapMem(tapidx) <= tapin;
end if;
end if;
end process;
end RTL;
|
<filename>mainpll_inst.vhd
mainpll_inst : mainpll PORT MAP (
areset => areset_sig,
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
c2 => c2_sig,
locked => locked_sig
);
|
<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library pck_lib;
use pck_lib.constants.all;
entity digit_selector is
generic (
cnt_bits : integer := digit_sel_cnt_bits
);
port (
clk : in std_logic;
rst : in std_logic;
digit_sel : out std_logic
);
end digit_selector;
architecture rtl of digit_selector is
-- Clock cycle counter for alternating between digits
-- refresh_rate = clk_frequency / (2 ** cnt_bits)
signal clk_cnt : unsigned(cnt_bits - 1 downto 0);
begin
digit_sel <= clk_cnt(clk_cnt'high);
COUNT_PROC : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
clk_cnt <= (others => '0');
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
end architecture;
|
-- pixel generator
--
-- it represents the logic to generate a sigal
-- for the RGB output to the VGA monitor, given
-- an input signal of "zero" or "one",
-- and considering the value of `video_on`
--
-- if `video_on` its "zero" it returns "zero"
-- and in the other case it converts the input
-- into a RGB valid signal value
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pixel_generator is
generic(
DATA_SIZE : natural := 1
);
port(
data : in std_logic_vector(DATA_SIZE - 1 downto 0);
red_out : out std_logic_vector(2 downto 0);
green_out : out std_logic_vector(2 downto 0);
blue_out : out std_logic_vector(1 downto 0);
video_on : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity pixel_generator;
architecture pixel_generator_arq of pixel_generator is
signal red_reg: std_logic_vector(2 downto 0);
signal green_reg: std_logic_vector(2 downto 0);
signal blue_reg: std_logic_vector(1 downto 0);
begin
translator: process(clk, rst)
begin
if rst = '1' then
red_reg <= (others => '0');
green_reg <= (others => '0');
blue_reg <= (others => '0');
elsif rising_edge(clk) then
if data = "1" then
red_reg <= (others => '1');
green_reg <= (others => '1');
blue_reg <= (others => '1');
else
red_reg <= (others => '0');
green_reg <= (others => '0');
blue_reg <= (others => '0');
end if;
end if;
end process;
red_out <= red_reg when video_on = '1' else (others => '0');
green_out <= green_reg when video_on = '1' else (others => '0');
blue_out <= blue_reg when video_on = '1' else (others => '0');
end architecture pixel_generator_arq;
|
----------------------------------------------------------------------------------
-- MIT License
--
-- Copyright (c) 2022 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
-- Company: University of Southern Denmark
-- Engineer: <NAME>
-- Contact: <EMAIL>
--
-- Description:
-- MMCME2 clk for HEIST
--
----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
-- Libraries
-----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-----------------------------------------------------------------------------------------------------
-- Ports
-----------------------------------------------------------------------------------------------------
entity my_clk is
Port (
clk_in : in STD_LOGIC;
clk_high_speed_out : out STD_LOGIC;
clk_locked_out : out STD_LOGIC
);
end my_clk;
architecture Behavioral of my_clk is
signal feedback_clk : std_logic;
begin
-----------------------------------------------------------------------------------------------------
-- Clk instantiation
-----------------------------------------------------------------------------------------------------
-- input clk 50 MHz
-- Multiply 4.0
-----------------------------------------------------------------------------------------------------
MMCME2_BASE_inst : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => 6.0, -- 8* 100M = 800MHZ -- 6* 100M = 600MHZ -- Multiply value for all CLKOUT (2.000-64.000). (600-1200MHz)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => 10.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 2,--2, -- 800MHz
CLKOUT2_DIVIDE => 4,--8, -- 200MHz
CLKOUT3_DIVIDE => 24, -- 50MHz
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 1.000,--2.000, -- -- 800 M -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5, -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => TRUE -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_high_speed_out, -- 1-bit output: CLKOUT0
-- CLKOUT0B => clk800M_180deg_out, -- 1-bit output: Inverted CLKOUT0
-- CLKOUT1 => clk800M_180deg_out, --clk800M_90deg_out, -- 1-bit output: CLKOUT1
-- CLKOUT1B => clk800M_270deg_out, -- 1-bit output: Inverted CLKOUT1
-- CLKOUT2 => clk200M_out, -- 1-bit output: CLKOUT2
-- CLKOUT2B => clk200M_180deg_out, -- 1-bit output: Inverted CLKOUT2
-- CLKOUT3 => clk_2div_out, -- 1-bit output: CLKOUT3
-- CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3
-- CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
-- CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
-- CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => feedback_clk, -- 1-bit output: Feedback clock
-- CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
LOCKED => clk_locked_out, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => clk_in, -- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => feedback_clk -- 1-bit input: Feedback clock
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: TU Delft, ESA
-- Engineer: wubinyi, <NAME>
--
-- Create Date: 05/18/2021 10:23:59 PM
-- Design Name:
-- Module Name: conv_buffer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Based on an SNN model implementation in VHDL by wubinyi
-- https://github.com/wubinyi/Spiking-Neural-Network. Individual neuron testbench.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: MIT Licensed
-- N.B.: Functional tested, but still needs removal of stuff like spike time dependent
-- plasticity and other stuff that's not relevant
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use IEEE.math_real.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use work.common_package.all;
entity neuron_tb is
end entity neuron_tb;
architecture tb_vhdl of neuron_tb is
component neuron is
generic (
address_0 : unsigned(5 downto 0):= "000000";
address_1 : unsigned(5 downto 0):= "000000";
post_spike_address : unsigned(5 downto 0) := "000000"
);
port(
clk_in : in std_logic;
reset_in : in std_logic;
address_in : in unsigned(5 downto 0);
pre_spike : in std_logic;
address_out : out unsigned(5 downto 0);
post_spike : out std_logic
);
end component;
constant CLKPERIODE : time := 50 us;
constant address_in_0 : unsigned(5 downto 0) := "000001";
constant address_in_1 : unsigned(5 downto 0) := "011000";
constant address_in_2 : unsigned(5 downto 0) := "011010";
constant address_in_3 : unsigned(5 downto 0) := "011011";
signal clk_in : std_logic := '1';
signal reset_in : std_logic := '0';
signal address_in : unsigned(5 downto 0) := "000000";
signal pre_spike : std_logic := '0';
signal post_spike : std_logic := '0';
signal address_out : unsigned(5 downto 0) := "000000";
signal temp_counter : integer := 0;
begin
neuron_1 : neuron
generic map(
address_0 => "000001",
address_1 => "000010",
post_spike_address => "110000"
)
port map(
clk_in => clk_in,
reset_in => reset_in,
address_in => address_in,
pre_spike => pre_spike,
address_out => address_out,
post_spike => post_spike
);
clk_gen : process
begin
wait for CLKPERIODE/2;
clk_in <= not clk_in;
end process clk_gen;
reset_gen : process
begin
reset_in <= '1';
wait for CLKPERIODE/2;
reset_in <= '0';
wait;
end process reset_gen;
spike_gen : process
begin
wait for CLKPERIODE;
temp_counter <= temp_counter + 1;
if temp_counter = 12 then
address_in <= address_in_0;
elsif temp_counter mod 29 = 0 then
address_in <= address_in_1;
elsif temp_counter mod 43 = 0 then
address_in <= address_in_2;
elsif temp_counter mod 58 = 0 then
address_in <= address_in_3;
elsif temp_counter mod 72 = 0 then
address_in <= address_in_0;
elsif temp_counter mod 80 = 0 then
address_in <= address_in_2;
elsif temp_counter > 4321 then
temp_counter <= 0;
else
address_in <= "000000";
end if;
end process spike_gen;
end architecture tb_vhdl;
|
<filename>Arke/src/NoC.vhd<gh_stars>1-10
--------------------------------------------------------------------------------------
-- DESIGN UNIT : NoC Arke --
-- DESCRIPTION : --
-- AUTHOR : <NAME>, <NAME> & <NAME> --
-- CREATED : Apr 8th, 2015 --
-- VERSION : v1.0 --
-- HISTORY : Version 1.0 - Jan 22th, 2019 --
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Arke_pkg.all;
entity NoC is
port(
clk : in std_logic;
rst : in std_logic;
-- LOCAL input and output port for each node
data_in : in Array3D_data(0 to DIM_X-1, 0 to DIM_Y-1, 0 to DIM_Z-1);
control_in : in Array3D_control(0 to DIM_X-1, 0 to DIM_Y-1, 0 to DIM_Z-1);
data_out : out Array3D_data(0 to DIM_X-1, 0 to DIM_Y-1, 0 to DIM_Z-1);
control_out : out Array3D_control(0 to DIM_X-1, 0 to DIM_Y-1, 0 to DIM_Z-1)
);
end NoC;
architecture structural of NoC is
-- Router component declaration
component Router is
generic(address: std_logic_vector(DATA_WIDTH-1 downto 0));
port(
clk : in std_logic;
rst : in std_logic;
data_in : in Array1D_data(0 to PORTS-1);
control_in : in Array1D_control(0 to PORTS-1);
data_out : out Array1D_data(0 to PORTS-1);
control_out : out Array1D_control(0 to PORTS-1)
);
end component;
-- Connections between routers inputs/outputs
signal data : Array4D_data(0 to DIM_X-1, 0 to DIM_Y-1, 0 to DIM_Z-1, 0 to 6);
signal control : array4D_control(0 to DIM_X-1, 0 to DIM_Y-1, 0 to DIM_Z-1, 0 to 6);
-- Signals for unused ports
signal data_dump : std_logic_vector(DATA_WIDTH-1 downto 0);
signal control_dump : std_logic_vector(CONTROL_WIDTH-1 downto 0);
begin
data_dump <= (others => '0');
control_dump <= (others => '0');
assert (DIM_X > 1)
report "DIM_X in NoC_Package must be greater than one"
severity FAILURE;
assert (DIM_Y > 1)
report "DIM_Y in NoC_Package must be greater than one"
severity FAILURE;
-- Loop to generate a 2D mesh NoC
MESH_2D: if (DIM_X>1 AND DIM_Y>1 AND DIM_Z=1) generate
Z_COORD: for z in 0 to (DIM_Z-1) generate
Y_COORD: for y in 0 to (DIM_Y-1) generate
X_COORD: for x in 0 to (DIM_X-1) generate
CENTRAL_ROUTER: if ((x-1>=0) AND (x+1<DIM_X) AND (y-1>=0) AND (y+1<DIM_Y)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data(x+1,y,z,WEST),
data_in(SOUTH) => data(x,y-1,z,NORTH),
data_in(WEST) => data(x-1,y,z,EAST),
data_in(NORTH) => data(x,y+1,z,SOUTH),
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control(x+1,y,z,WEST),
control_in(SOUTH) => control(x,y-1,z,NORTH),
control_in(WEST) => control(x-1,y,z,EAST),
control_in(NORTH) => control(x,y+1,z,SOUTH),
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate CENTRAL_ROUTER;
BOTTON_LEFT_CORNER: if ((x=0) AND (y=0)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data(x+1,y,z,WEST),
data_in(SOUTH) => data_dump,
data_in(WEST) => data_dump,
data_in(NORTH) => data(x,y+1,z,SOUTH),
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control(x+1,y,z,WEST),
control_in(SOUTH) => control_dump,
control_in(WEST) => control_dump,
control_in(NORTH) => control(x,y+1,z,SOUTH),
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate BOTTON_LEFT_CORNER;
BOTTON_RIGHT_CORNER: if ((x=DIM_X-1) AND (y=0)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data_dump,
data_in(SOUTH) => data_dump,
data_in(WEST) => data(x-1,y,z,EAST),
data_in(NORTH) => data(x,y+1,z,SOUTH),
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control_dump,
control_in(SOUTH) => control_dump,
control_in(WEST) => control(x-1,y,z,EAST),
control_in(NORTH) => control(x,y+1,z,SOUTH),
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate BOTTON_RIGHT_CORNER;
TOP_LEFT_CORNER: if ((x=0) AND (y=DIM_Y-1)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data(x+1,y,z,WEST),
data_in(SOUTH) => data(x,y-1,z,NORTH),
data_in(WEST) => data_dump,
data_in(NORTH) => data_dump,
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control(x+1,y,z,WEST),
control_in(SOUTH) => control(x,y-1,z,NORTH),
control_in(WEST) => control_dump,
control_in(NORTH) => control_dump,
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate TOP_LEFT_CORNER;
TOP_RIGHT_CORNER: if ((x=DIM_X-1) AND (y=DIM_Y-1)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data_dump,
data_in(SOUTH) => data(x,y-1,z,NORTH),
data_in(WEST) => data(x-1,y,z,EAST),
data_in(NORTH) => data_dump,
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control_dump,
control_in(SOUTH) => control(x,y-1,z,NORTH),
control_in(WEST) => control(x-1,y,z,EAST),
control_in(NORTH) => control_dump,
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate TOP_RIGHT_CORNER;
BOTTON_BORDER: if ((x>0) AND (x<DIM_X-1) AND (y=0)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data(x+1,y,z,WEST),
data_in(SOUTH) => data_dump,
data_in(WEST) => data(x-1,y,z,EAST),
data_in(NORTH) => data(x,y+1,z,SOUTH),
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control(x+1,y,z,WEST),
control_in(SOUTH) => control_dump,
control_in(WEST) => control(x-1,y,z,EAST),
control_in(NORTH) => control(x,y+1,z,SOUTH),
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate BOTTON_BORDER;
LEFT_BORDER: if ((x=0) AND (y>0) AND (y<DIM_Y-1)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data(x+1,y,z,WEST),
data_in(SOUTH) => data(x,y-1,z,NORTH),
data_in(WEST) => data_dump,
data_in(NORTH) => data(x,y+1,z,SOUTH),
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control(x+1,y,z,WEST),
control_in(SOUTH) => control(x,y-1,z,NORTH),
control_in(WEST) => control_dump,
control_in(NORTH) => control(x,y+1,z,SOUTH),
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate LEFT_BORDER;
TOP_BORDER: if ((x>0) AND (x<DIM_X-1) AND (y=DIM_Y-1)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data(x+1,y,z,WEST),
data_in(SOUTH) => data(x,y-1,z,NORTH),
data_in(WEST) => data(x-1,y,z,EAST),
data_in(NORTH) => data_dump,
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control(x+1,y,z,WEST),
control_in(SOUTH) => control(x,y-1,z,NORTH),
control_in(WEST) => control(x-1,y,z,EAST),
control_in(NORTH) => control_dump,
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate TOP_BORDER;
RIGHT_BORDER: if ((x=DIM_X-1) AND (y>0) AND (y<DIM_Y-1)) generate
ROUTER_XYZ: Router
generic map(address => Address(x,y,z))
port map(
clk => clk,
rst => rst,
data_in(LOCAL) => data_in(x,y,z),
data_in(EAST) => data_dump,
data_in(SOUTH) => data(x,y-1,z,NORTH),
data_in(WEST) => data(x-1,y,z,EAST),
data_in(NORTH) => data(x,y+1,z,SOUTH),
control_in(LOCAL) => control_in(x,y,z),
control_in(EAST) => control_dump,
control_in(SOUTH) => control(x,y-1,z,NORTH),
control_in(WEST) => control(x-1,y,z,EAST),
control_in(NORTH) => control(x,y+1,z,SOUTH),
data_out(LOCAL) => data_out(x,y,z),
data_out(EAST) => data(x,y,z,EAST),
data_out(SOUTH) => data(x,y,z,SOUTH),
data_out(WEST) => data(x,y,z,WEST),
data_out(NORTH) => data(x,y,z,NORTH),
control_out(LOCAL) => control_out(x,y,z),
control_out(EAST) => control(x,y,z,EAST),
control_out(SOUTH) => control(x,y,z,SOUTH),
control_out(WEST) => control(x,y,z,WEST),
control_out(NORTH) => control(x,y,z,NORTH)
);
end generate RIGHT_BORDER;
end generate X_COORD;
end generate Y_COORD;
end generate Z_COORD;
end generate MESH_2D;
---- Loop to generate a 3D mesh NoC
--MESH_3D: if (DIM_X>1 AND DIM_Y>1 AND DIM_Z>1) generate
-- Z_COORD: for z in 0 to (DIM_Z-1) generate
-- Y_COORD: for y in 0 to (DIM_Y-1) generate
-- X_COORD: for x in 0 to (DIM_X-1) generate
--
-- -- Nodes connections according to their position inside the cube-shaped NoC
-- CENTRAL_ROUTER: if ((x-1>=0) AND (x+1<DIM_X) AND (y-1>=0) AND (y+1<DIM_Y) AND (z-1>=0) AND (z+1<DIM_Z)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate CENTRAL_ROUTER;
--
-- LEFT_FRONT_BOTTOM_CORNER: if ((x=0) AND (y=0) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data_dump,
-- --data_in(WEST) => x"1234",
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_FRONT_BOTTOM_CORNER;
--
-- RIGHT_FRONT_BOTTOM_CORNER: if ((x=DIM_X-1) AND (y=0) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_FRONT_BOTTOM_CORNER;
--
-- LEFT_BACK_BOTTOM_CORNER: if ((x=0) AND (y=DIM_Y-1) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_BACK_BOTTOM_CORNER;
--
-- RIGHT_BACK_BOTTOM_CORNER: if ((x=DIM_X-1) AND (y=DIM_Y-1) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_BACK_BOTTOM_CORNER;
--
-- LEFT_FRONT_TOP_CORNER: if ((x=0) AND (y=0) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_FRONT_TOP_CORNER;
--
-- RIGHT_FRONT_TOP_CORNER: if ((x=DIM_X-1) AND (y=0) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_FRONT_TOP_CORNER;
--
-- LEFT_BACK_TOP_CORNER: if ((x=0) AND (y=DIM_Y-1) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_BACK_TOP_CORNER;
--
-- RIGHT_BACK_TOP_CORNER: if ((x=DIM_X-1) AND (y=DIM_Y-1) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP), -- altas aventuras
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_BACK_TOP_CORNER;
--
-- FRONT_BOTTOM_BORDER: if ((x>0) AND (x<DIM_X-1) AND (y=0) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate FRONT_BOTTOM_BORDER;
--
-- LEFT_BOTTOM_BORDER: if ((x=0) AND (y>0) AND (y<DIM_Y-1) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_BOTTOM_BORDER;
--
-- BACK_BOTTOM_BORDER: if ((x>0) AND (x<DIM_X-1) AND (y=DIM_Y-1) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate BACK_BOTTOM_BORDER;
--
-- RIGHT_BOTTOM_BORDER: if ((x=DIM_X-1) AND (y>0) AND (y<DIM_Y-1) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_BOTTOM_BORDER;
--
-- FRONT_TOP_BORDER: if ((x>0) AND (x<DIM_X-1) AND (y=0) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate FRONT_TOP_BORDER;
--
-- LEFT_TOP_BORDER: if ((x=0) AND (y>0) AND (y<DIM_Y-1) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_TOP_BORDER;
--
-- BACK_TOP_BORDER: if ((x>0) AND (x<DIM_X-1) AND (y=DIM_Y-1) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate BACK_TOP_BORDER;
--
-- RIGHT_TOP_BORDER: if ((x=DIM_X-1) AND (y>0) AND (y<DIM_Y-1) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_TOP_BORDER;
--
-- LEFT_FRONT_BORDER: if ((x=0) AND (y=0) AND (z>0) AND (z<DIM_Z-1)) generate
-- gROUT: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_FRONT_BORDER;
--
-- RIGHT_FRONT_BORDER: if ((x=DIM_X-1) AND (y=0) AND (z>0) AND (z<DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_FRONT_BORDER;
--
-- LEFT_BACK_BORDER: if ((x=0) AND (y=DIM_Y-1) AND (z>0) AND (z<DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_BACK_BORDER;
--
-- RIGHT_BACK_BORDER: if ((x=DIM_X-1) AND (y=DIM_Y-1) AND (z>0) AND (z<DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_BACK_BORDER;
--
-- FRONT_FACE: if ((x>0) AND (x<DIM_X-1) AND (y=0) AND (z>0) AND (z<DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data_dump,
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control_dump,
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate FRONT_FACE;
--
-- LEFT_FACE: if ((x=0) AND (y>0) AND (y<DIM_Y-1) AND (z>0) AND (z<DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data_dump,
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control_dump,
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate LEFT_FACE;
--
-- RIGHT_FACE: if ((x>0) AND (x<DIM_X-1) AND (y=DIM_Y-1) AND (z>0) AND (z<DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data_dump,
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control_dump,
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate RIGHT_FACE;
--
-- BACK_FACE: if ((x=DIM_X-1) AND (y>0) AND (y<DIM_Y-1) AND (z>0) AND (z<DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data_dump,
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control_dump,
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate BACK_FACE;
--
-- BOTTOM_FACE: if ((x>0) AND (x<DIM_X-1) AND (y>0) AND (y<DIM_Y-1) AND (z=0)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data(x,y,z+1,DOWN),
-- data_in(DOWN) => data_dump,
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control(x,y,z+1,DOWN),
-- control_in(DOWN) => control_dump,
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate BOTTOM_FACE;
--
-- TOP_FACE: if ((x>0) AND (x<DIM_X-1) AND (y>0) AND (y<DIM_Y-1) AND (z=DIM_Z-1)) generate
-- ROUTER_XYZ: Router
-- generic map(address => Address(x,y,z))
-- port map(
-- clk => clk,
-- rst => rst,
-- data_in(LOCAL) => data_in(x,y,z),
-- data_in(EAST) => data(x+1,y,z,WEST),
-- data_in(SOUTH) => data(x,y-1,z,NORTH),
-- data_in(WEST) => data(x-1,y,z,EAST),
-- data_in(NORTH) => data(x,y+1,z,SOUTH),
-- data_in(UP) => data_dump,
-- data_in(DOWN) => data(x,y,z-1,UP),
-- control_in(LOCAL) => control_in(x,y,z),
-- control_in(EAST) => control(x+1,y,z,WEST),
-- control_in(SOUTH) => control(x,y-1,z,NORTH),
-- control_in(WEST) => control(x-1,y,z,EAST),
-- control_in(NORTH) => control(x,y+1,z,SOUTH),
-- control_in(UP) => control_dump,
-- control_in(DOWN) => control(x,y,z-1,UP),
-- data_out(LOCAL) => data_out(x,y,z),
-- data_out(EAST) => data(x,y,z,EAST),
-- data_out(SOUTH) => data(x,y,z,SOUTH),
-- data_out(WEST) => data(x,y,z,WEST),
-- data_out(NORTH) => data(x,y,z,NORTH),
-- data_out(UP) => data(x,y,z,UP),
-- data_out(DOWN) => data(x,y,z,DOWN),
-- control_out(LOCAL) => control_out(x,y,z),
-- control_out(EAST) => control(x,y,z,EAST),
-- control_out(SOUTH) => control(x,y,z,SOUTH),
-- control_out(WEST) => control(x,y,z,WEST),
-- control_out(NORTH) => control(x,y,z,NORTH),
-- control_out(UP) => control(x,y,z,UP),
-- control_out(DOWN) => control(x,y,z,DOWN)
-- );
-- end generate TOP_FACE;
--
-- end generate X_COORD;
-- end generate Y_COORD;
-- end generate Z_COORD;
--end generate MESH_3D;
end structural;
|
<reponame>luizcartolano2/mc613
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity valida_clique is
port
(
clock_50mhz : in STD_LOGIC;
ps2_data : inout STD_LOGIC;
ps2_clock : inout STD_LOGIC;
resetn : in std_logic;
position_x : in std_logic_vector(7 downto 0);
position_y : in std_logic_vector(7 downto 0);
comando : out std_logic_vector(3 downto 0);
estado_mouse : in std_logic_vector(1 downto 0);
grid_jogo : in std_logic_vector(17 downto 0)
);
end;
architecture struct of valida_clique is
component mouse_ctrl
generic(
clkfreq : integer
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
newdata : out std_logic;
bt_on : out std_logic_vector(2 downto 0);
ox, oy : out std_logic;
dx, dy : out std_logic_vector(8 downto 0);
wheel : out std_logic_vector(3 downto 0)
);
end component;
signal signewdata : std_logic;
signal ox, oy : std_logic;
signal bt_on : std_logic_vector(2 downto 0);
signal wheel : std_logic_vector(3 downto 0);
signal x, y : std_logic_vector(7 downto 0);
signal dx, dy : std_logic_vector(8 downto 0);
signal mouse_x_tmp : integer range 0 to 128 - 1;
signal mouse_y_tmp : integer range 0 to 96 - 1;
CONSTANT HORZ_SIZE : INTEGER := 128;
CONSTANT VERT_SIZE : INTEGER := 96;
begin
mousectrl : mouse_ctrl generic map (50000) port map(
ps2_data, ps2_clock, clock_50mhz, '1', resetn,
signewdata, bt_on, ox, oy, dx, dy, wheel
);
with position_x select
mouse_x_tmp <= 127 when "00111111",
126 when "00111110",
125 when "00111101",
124 when "00111100",
123 when "00111011",
122 when "00111010",
121 when "00111001",
120 when "00111000",
119 when "00110111",
118 when "00110110",
117 when "00110101",
116 when "00110100",
115 when "00110011",
114 when "00110010",
113 when "00110001",
112 when "00110000",
111 when "00101111",
110 when "00101110",
109 when "00101101",
108 when "00101100",
107 when "00101011",
106 when "00101010",
105 when "00101001",
104 when "00101000",
103 when "00100111",
102 when "00100110",
101 when "00100101",
100 when "00100100",
99 when "00100011",
98 when "00100010",
97 when "00100001",
96 when "00100000",
95 when "00011111",
94 when "00011110",
93 when "00011101",
92 when "00011100",
91 when "00011011",
90 when "00011010",
89 when "00011001",
88 when "00011000",
87 when "00010111",
86 when "00010110",
85 when "00010101",
84 when "00010100",
83 when "00010011",
82 when "00010010",
81 when "00010001",
80 when "00010000",
79 when "00001111",
78 when "00001110",
77 when "00001101",
76 when "00001100",
75 when "00001011",
74 when "00001010",
73 when "00001001",
72 when "00001000",
71 when "00000111",
70 when "00000110",
69 when "00000101",
68 when "00000100",
67 when "00000011",
66 when "00000010",
65 when "00000001",
64 when "00000000",
63 when "11111111",
62 when "11111110",
61 when "11111101",
60 when "11111100",
59 when "11111011",
58 when "11111010",
57 when "11111001",
56 when "11111000",
55 when "11110111",
54 when "11110110",
53 when "11110101",
52 when "11110100",
51 when "11110011",
50 when "11110010",
49 when "11110001",
48 when "11110000",
47 when "11101111",
46 when "11101110",
45 when "11101101",
44 when "11101100",
43 when "11101011",
42 when "11101010",
41 when "11101001",
40 when "11101000",
39 when "11100111",
38 when "11100110",
37 when "11100101",
36 when "11100100",
35 when "11100011",
34 when "11100010",
33 when "11100001",
32 when "11100000",
31 when "11011111",
30 when "11011110",
29 when "11011101",
28 when "11011100",
27 when "11011011",
26 when "11011010",
25 when "11011001",
24 when "11011000",
23 when "11010111",
22 when "11010110",
21 when "11010101",
20 when "11010100",
19 when "11010011",
18 when "11010010",
17 when "11010001",
16 when "11010000",
15 when "11001111",
14 when "11001110",
13 when "11001101",
12 when "11001100",
11 when "11001011",
10 when "11001010",
9 when "11001001",
8 when "11001000",
7 when "11000111",
6 when "11000110",
5 when "11000101",
4 when "11000100",
3 when "11000011",
2 when "11000010",
1 when "11000001",
0 when "11000000",
mouse_x_tmp when others;
with position_y select
mouse_y_tmp <= 95 when "11010001",
94 when "11010010",
93 when "11010011",
92 when "11010100",
91 when "11010101",
90 when "11010110",
89 when "11010111",
88 when "11011000",
87 when "11011001",
86 when "11011010",
85 when "11011011",
84 when "11011100",
83 when "11011101",
82 when "11011110",
81 when "11011111",
80 when "11100000",
79 when "11100001",
78 when "11100010",
77 when "11100011",
76 when "11100100",
75 when "11100101",
74 when "11100110",
73 when "11100111",
72 when "11101000",
71 when "11101001",
70 when "11101010",
69 when "11101011",
68 when "11101100",
67 when "11101101",
66 when "11101110",
65 when "11101111",
64 when "11110000",
63 when "11110001",
62 when "11110010",
61 when "11110011",
60 when "11110100",
59 when "11110101",
58 when "11110110",
57 when "11110111",
56 when "11111000",
55 when "11111001",
54 when "11111010",
53 when "11111011",
52 when "11111100",
51 when "11111101",
50 when "11111110",
49 when "11111111",
48 when "00000000",
47 when "00000001",
46 when "00000010",
45 when "00000011",
44 when "00000100",
43 when "00000101",
42 when "00000110",
41 when "00000111",
40 when "00001000",
39 when "00001001",
38 when "00001010",
37 when "00001011",
36 when "00001100",
35 when "00001101",
34 when "00001110",
33 when "00001111",
32 when "00010000",
31 when "00010001",
30 when "00010010",
29 when "00010011",
28 when "00010100",
27 when "00010101",
26 when "00010110",
25 when "00010111",
24 when "00011000",
23 when "00011001",
22 when "00011010",
21 when "00011011",
20 when "00011100",
19 when "00011101",
18 when "00011110",
17 when "00011111",
16 when "00100000",
15 when "00100001",
14 when "00100010",
13 when "00100011",
12 when "00100100",
11 when "00100101",
10 when "00100110",
9 when "00100111",
8 when "00101000",
7 when "00101001",
6 when "00101010",
5 when "00101011",
4 when "00101100",
3 when "00101101",
2 when "00101110",
1 when "00101111",
0 when "00110000",
mouse_y_tmp when others;
process(signewdata, resetn)
variable mouse_position : integer range 0 to (128 * 96) - 1;
begin
if(rising_edge(signewdata)) then
if bt_on(0) = '1' then
mouse_position := (128 * mouse_y_tmp) + mouse_x_tmp;
if estado_mouse = "00" then
if mouse_position = ((HORZ_SIZE*(26))+31) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(26))+32) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(26))+33) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(27))+31) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(27))+32) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(27))+33) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(28))+31) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(28))+32) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(28))+33) then
comando <= "0001";
elsif mouse_position = ((HORZ_SIZE*(26))+76) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(26))+77) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(26))+78) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(27))+76) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(27))+77) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(27))+78) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(28))+76) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(28))+77) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(28))+78) then
comando <= "0010";
elsif mouse_position = ((HORZ_SIZE*(60))+22) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(60))+23) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(60))+24) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(61))+22) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(61))+23) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(61))+24) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(62))+22) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(62))+23) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(62))+24) then
comando <= "0011";
elsif mouse_position = ((HORZ_SIZE*(60))+85) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(60))+86) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(60))+87) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(61))+85) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(61))+86) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(61))+87) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(62))+85) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(62))+86) then
comando <= "0100";
elsif mouse_position = ((HORZ_SIZE*(62))+87) then
comando <= "0100";
elsif mouse_y_tmp >= 84 and mouse_y_tmp <= 92 and mouse_x_tmp > 51 and mouse_x_tmp <= 77 then
comando <= "1111";
else
comando <= "0000";
end if;
else
if estado_mouse = "01" then
--case mouse_position is
if mouse_y_tmp < 34 and mouse_x_tmp < 50 then
comando <= "0001";
elsif mouse_y_tmp < 34 and mouse_x_tmp > 50 and mouse_x_tmp < 77 then
comando <= "0010";
elsif mouse_y_tmp < 34 and mouse_x_tmp > 77 then
comando <= "0011";
elsif mouse_y_tmp < 62 and mouse_y_tmp > 34 and mouse_x_tmp < 50 then
comando <= "0100";
elsif mouse_y_tmp < 62 and mouse_y_tmp > 34 and mouse_x_tmp < 77 and mouse_x_tmp > 50 then
comando <= "0101";
elsif mouse_y_tmp < 62 and mouse_y_tmp > 34 and mouse_x_tmp > 77 then
comando <= "0110";
elsif mouse_y_tmp > 62 and mouse_y_tmp < 82 and mouse_x_tmp < 50 then
comando <= "0111";
elsif mouse_y_tmp > 62 and mouse_y_tmp < 82 and mouse_x_tmp < 77 and mouse_x_tmp > 50 then
comando <= "1000";
elsif mouse_y_tmp > 62 and mouse_y_tmp < 82 and mouse_x_tmp > 77 then
comando <= "1001";
else
comando <= "0000";
end if;
else
if estado_mouse = "10" then
end if;
end if;
end if;
else
comando <= "0000";
end if;
end if;
if resetn = '0' then
comando <= "0000";
end if;
end process;
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_on_off is
-- Port ( );
end tb_on_off;
architecture Behavioral of tb_on_off is
signal s_start_i : std_logic;
signal s_start_o : std_logic;
begin
uut_on_off : entity work.on_off
port map(
start_i => s_start_i,
start_o => s_start_o
);
--------------------------------------------------------------------
-- Data generation process
--------------------------------------------------------------------
p_stimulus : process
begin
report "Stimulus process started" severity note;
s_start_i <= '0';
wait for 100 ns;
s_start_i <= '1';
wait for 200 ns;
s_start_i <= '0';
wait for 20 ns;
s_start_i <= '1';
wait for 300 ns;
s_start_i <= '0';
wait for 200 ns;
s_start_i <= '1';
wait for 150 ns;
report "Stimulus process finished" severity note;
wait;
end process p_stimulus;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;
entity g42_FIR_tb is
end g42_FIR_tb;
architecture testbench of g42_FIR_tb is
component g42_FIR is
port (
x : in std_logic_vector(15 downto 0); --input signal
clk : in std_logic; -- clock
rst : in std_logic; -- asynchronous active-high reset
y : out std_logic_vector(16 downto 0) -- output signal
);
end component g42_FIR;
file file_IN : text;
file file_RESULTS : text;
constant clk_PERIOD : time := 60 ns;
signal x_in : std_logic_vector(15 downto 0);
signal clk_in : std_logic;
signal rst_in : std_logic;
signal y_out : std_logic_vector(16 downto 0);
begin
g42_FIR_test : g42_FIR
port map (
x => x_in,
clk => clk_in,
rst => rst_in,
y => y_out
);
--CLOCK GENERATION
clk_gen : process
begin
clk_in <= '1';
wait for clk_PERIOD / 2;
clk_in <= '0';
wait for clk_PERIOD / 2;
end process clk_gen;
feeding_instr : process is
variable v_lline1 : line;
variable v_lline2 : line;
variable v_Oline : line;
variable v_x_in : std_logic_vector(15 downto 0);
begin
rst_in <= '1';
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
rst_in <= '0';
file_open(file_IN, "C:\Users\sli196.CAMPUS\ECSE325\scripts\lab3\lab3-In-fixedOutput.txt", read_mode);
file_open(file_RESULTS, "C:\Users\sli196.CAMPUS\ECSE325\scripts\lab3\lab3-out.txt", write_mode);
while not endfile (file_IN) loop
readline(file_IN, v_lline1);
read(v_lline1, v_x_in);
x_in <= v_x_in;
write(v_Oline, y_out);
writeline(file_RESULTS, v_Oline);
wait until rising_edge(clk_in);
end loop;
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
wait;
end process feeding_instr;
end testbench;
|
---------------------------------------------------------------------------------------------------
-- Author: <NAME>
-- Company: University Bonn
-- Date:
-- Description: Control-unit, which handles HOST-FPGA information communication
-- Version: 0.1
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils.all;
use work.transceiver_128bit_types.all;
use work.cfg_channel_types.all;
entity cfg_channel_controller is
port(
clk : in std_ulogic;
rst_host_channel : out std_ulogic := '0';
rst_fpga_channel : out std_ulogic := '0';
rst_endpoint : out std_ulogic := '0';
-- decoder input ports
op_code : in op_code_t;
op_addr : in cfg_reg_addr_t := 0;
op_data : in std_ulogic_vector(31 downto 0) := (others => '0');
op_vld : in std_ulogic := '0';
op_tag : in std_ulogic_vector( 7 downto 0);
op_ready : out std_ulogic := '0'; -- enables cfg_decoder input ports
-- memory input/output ports
mem_addr : out cfg_reg_addr_t := 0;
mem_wr_data : out std_ulogic_vector(31 downto 0) := (others => '0');
mem_wr_en : out std_ulogic := '0';
mem_rd_data : in std_ulogic_vector(31 downto 0) := (others => '0');
mem_rd_en : out std_ulogic := '0';
-- completer output ports
cpld_payload : out std_ulogic_vector(31 downto 0);
cpld_lo_addr : out std_ulogic_vector( 6 downto 0);
cpld_tag : out std_ulogic_vector( 7 downto 0);
cpld_vld : out std_ulogic := '0';
cpld_done : in std_ulogic
);
end cfg_channel_controller;
architecture arch of cfg_channel_controller is
type state_t is (RESET, IDLE, READ_MEM_AND_SEND_CPLD, EXEC_INSTR);
signal state : state_t := IDLE;
constant rst_cc : positive := 10;
signal rst_counter : integer range 0 to rst_cc := rst_cc;
signal host_instruction : std_ulogic_vector(31 downto 0);
begin
cpld_tag <= op_tag;
cpld_lo_addr <= '0' & std_logic_vector(to_unsigned(op_addr, 4)) & "00"; -- this is channel 0
cpld_payload <= mem_rd_data;
mem_addr <= op_addr;
mem_wr_data <= op_data;
mem_wr_en <= '1' when op_code = WR_REG or op_code = INSTR else '0';
mem_rd_en <= '1' when op_code = RD_REG else '0';
-- disable output register of decoder if host wants to read a register while
-- FSM is busy with a previous read instruction.
-- Writing a register is always possible
op_ready <= '1' when state = IDLE or op_code = WR_REG else '0';
main: process
begin
wait until rising_edge(clk);
host_instruction <= op_data;
case state is
when IDLE =>
if op_vld = '1' then
case op_code is
when RD_REG =>
state <= READ_MEM_AND_SEND_CPLD;
cpld_vld <= '1';
when INSTR =>
state <= EXEC_INSTR;
when others => null;
end case;
end if;
-- fsm freezes current state of "op" input signal
-- until completer finishes with responding to host
when READ_MEM_AND_SEND_CPLD =>
if cpld_done = '1' then
state <= IDLE;
cpld_vld <= '0';
end if;
-- execute host instruction
when EXEC_INSTR =>
if host_instruction(RESET_TRANSCEIVER) = '1' then
rst_endpoint <= '1';
rst_host_channel <= '1';
rst_fpga_channel <= '1';
state <= RESET;
end if;
if host_instruction(RESET_HOST_CHANNEL) = '1' then
rst_host_channel <= '1';
state <= RESET;
end if;
if host_instruction(RESET_FPGA_CHANNEL) = '1' then
rst_fpga_channel <= '1';
state <= RESET;
end if;
when RESET =>
rst_counter <= rst_counter - 1;
cpld_vld <= '0';
if rst_counter = 0 then
state <= IDLE;
rst_counter <= rst_cc;
-- defaults:
rst_endpoint <= '0';
rst_host_channel <= '0';
rst_fpga_channel <= '0';
end if;
end case;
end process;
end architecture;
|
<filename>Extra/extra_pkg.vhdl<gh_stars>10-100
--
-- USB Full-Speed/Hi-Speed Device Controller core - extra_pkg.vhdl
--
-- Copyright (c) 2015 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
package USBExtra is
component blk_ep_out_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
axis_tdata : out std_logic_vector(7 downto 0);
axis_tvalid : out std_logic;
axis_tready : in std_logic;
axis_tlast : out std_logic
);
end component;
component blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end component;
component sync_fifo
generic (
constant FIFO_WIDTH : positive;
constant FIFO_DEPTH : positive;
constant PROG_FULL_VALUE: positive
);
port (
clk : in std_logic;
rst : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : out std_logic;
prog_full : out std_logic
);
end component;
end USBExtra;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ex_comp1 IS
PORT(
what_fib_in : IN std_logic_vector (4 downto 0);
seg_out_out : OUT std_logic_vector (6 downto 0); --- HEX0
seg_out_out2 : OUT std_logic_vector (6 downto 0) --- HEX1
);
END ex_comp1;
ARCHITECTURE HEX2_out OF ex_comp1 IS
BEGIN
with what_fib_in select
seg_out_out <= "1000000" when "00000", --- 0 ---HEX0
"1111001" when "00001", --- 1
"0100100" when "00010", --- 2 | 0 1 6 3
"0110000" when "00011", --- 3 | 0 1 2 3 6
"0010010" when "00101", --- 5 | 0 5 6 2 3
"0000000" when "01000", --- 8 | 6543210
"0110000" when "01101", --- 13 | 3==>
"1111001" when "10101",--- 21 |
"0000110" when others; --- E | 0 5 6 4 3
---HEX1
with what_fib_in select
seg_out_out2 <=
"1111001" when "01101", --- 13 | 1==>
"0100100" when "10101", --- 21 | 2==>
"1111111" when others;
END HEX2_out;
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #625)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from busSlaveFabric_DSPB_MMSE_dut_2puidkqw3flrx06e69646s6u0qu5xajz
-- VHDL created on Mon Aug 16 17:44:01 2021
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_sim_library_package.all;
entity busSlaveFabric_DSPB_MMSE_dut_2puidkqw3flrx06e69646s6u0qu5xajz_atb is
end;
architecture normal of busSlaveFabric_DSPB_MMSE_dut_2puidkqw3flrx06e69646s6u0qu5xajz_atb is
component busSlaveFabric_DSPB_MMSE_dut_2puidkqw3flrx06e69646s6u0qu5xajz is
port (
busIn_writedata : in std_logic_vector(15 downto 0); -- ufix16
busIn_address : in std_logic_vector(9 downto 0); -- ufix10
busIn_write : in std_logic_vector(0 downto 0); -- ufix1
busIn_read : in std_logic_vector(0 downto 0); -- ufix1
busOut_readdatavalid : out std_logic_vector(0 downto 0); -- ufix1
busOut_readdata : out std_logic_vector(15 downto 0); -- ufix16
in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x : in std_logic_vector(15 downto 0); -- sfix16_en8
in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x : in std_logic_vector(0 downto 0); -- ufix1
in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x : in std_logic_vector(8 downto 0); -- ufix9
in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x : in std_logic_vector(8 downto 0); -- ufix9
in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x : in std_logic_vector(15 downto 0); -- sfix16_en11
in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x : in std_logic_vector(15 downto 0); -- sfix16_en14
in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x : in std_logic_vector(0 downto 0); -- ufix1
in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x : in std_logic_vector(0 downto 0); -- ufix1
out_sharedMemWireData_DSPB_MMSE_dut_input_IF_input_fifo_x : out std_logic_vector(15 downto 0); -- sfix16_en14
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
component busSlaveFabric_DSPB_MMSE_dut_2puidkqw3flrx06e69646s6u0qu5xajz_stm is
port (
busIn_writedata_stm : out std_logic_vector(15 downto 0);
busIn_address_stm : out std_logic_vector(9 downto 0);
busIn_write_stm : out std_logic_vector(0 downto 0);
busIn_read_stm : out std_logic_vector(0 downto 0);
busOut_readdatavalid_stm : out std_logic_vector(0 downto 0);
busOut_readdata_stm : out std_logic_vector(15 downto 0);
in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x_stm : out std_logic_vector(15 downto 0);
in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x_stm : out std_logic_vector(0 downto 0);
in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm : out std_logic_vector(8 downto 0);
in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : out std_logic_vector(8 downto 0);
in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm : out std_logic_vector(15 downto 0);
in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : out std_logic_vector(15 downto 0);
in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm : out std_logic_vector(0 downto 0);
in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : out std_logic_vector(0 downto 0);
out_sharedMemWireData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : out std_logic_vector(15 downto 0);
clk : out std_logic;
areset : out std_logic;
h_areset : out std_logic
);
end component;
signal busIn_writedata_stm : STD_LOGIC_VECTOR (15 downto 0);
signal busIn_address_stm : STD_LOGIC_VECTOR (9 downto 0);
signal busIn_write_stm : STD_LOGIC_VECTOR (0 downto 0);
signal busIn_read_stm : STD_LOGIC_VECTOR (0 downto 0);
signal busOut_readdatavalid_stm : STD_LOGIC_VECTOR (0 downto 0);
signal busOut_readdata_stm : STD_LOGIC_VECTOR (15 downto 0);
signal in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x_stm : STD_LOGIC_VECTOR (15 downto 0);
signal in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x_stm : STD_LOGIC_VECTOR (0 downto 0);
signal in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm : STD_LOGIC_VECTOR (8 downto 0);
signal in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : STD_LOGIC_VECTOR (8 downto 0);
signal in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm : STD_LOGIC_VECTOR (15 downto 0);
signal in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : STD_LOGIC_VECTOR (15 downto 0);
signal in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm : STD_LOGIC_VECTOR (0 downto 0);
signal in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : STD_LOGIC_VECTOR (0 downto 0);
signal out_sharedMemWireData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm : STD_LOGIC_VECTOR (15 downto 0);
signal busIn_writedata_dut : STD_LOGIC_VECTOR (15 downto 0);
signal busIn_address_dut : STD_LOGIC_VECTOR (9 downto 0);
signal busIn_write_dut : STD_LOGIC_VECTOR (0 downto 0);
signal busIn_read_dut : STD_LOGIC_VECTOR (0 downto 0);
signal busOut_readdatavalid_dut : STD_LOGIC_VECTOR (0 downto 0);
signal busOut_readdata_dut : STD_LOGIC_VECTOR (15 downto 0);
signal in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x_dut : STD_LOGIC_VECTOR (15 downto 0);
signal in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x_dut : STD_LOGIC_VECTOR (0 downto 0);
signal in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x_dut : STD_LOGIC_VECTOR (8 downto 0);
signal in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x_dut : STD_LOGIC_VECTOR (8 downto 0);
signal in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x_dut : STD_LOGIC_VECTOR (15 downto 0);
signal in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x_dut : STD_LOGIC_VECTOR (15 downto 0);
signal in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x_dut : STD_LOGIC_VECTOR (0 downto 0);
signal in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x_dut : STD_LOGIC_VECTOR (0 downto 0);
signal out_sharedMemWireData_DSPB_MMSE_dut_input_IF_input_fifo_x_dut : STD_LOGIC_VECTOR (15 downto 0);
signal clk : std_logic;
signal areset : std_logic;
signal h_areset : std_logic;
begin
-- General Purpose data in real output
checkin_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x : process (clk, areset, in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x_dut, in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x_stm)
begin
END PROCESS;
-- General Purpose data in real output
checkin_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x : process (clk, areset, in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x_dut, in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x_stm)
begin
END PROCESS;
-- General Purpose data in real output
checkin_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x : process (clk, areset, in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x_dut, in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm)
begin
END PROCESS;
-- General Purpose data in real output
checkin_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x : process (clk, areset, in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x_dut, in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x_stm)
begin
END PROCESS;
-- General Purpose data in real output
checkin_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x : process (clk, areset, in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x_dut, in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm)
begin
END PROCESS;
-- General Purpose data in real output
checkin_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x : process (clk, areset, in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x_dut, in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm)
begin
END PROCESS;
-- General Purpose data in real output
checkin_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x : process (clk, areset, in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x_dut, in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm)
begin
END PROCESS;
-- General Purpose data in real output
checkin_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x : process (clk, areset, in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x_dut, in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x_stm)
begin
END PROCESS;
dut : busSlaveFabric_DSPB_MMSE_dut_2puidkqw3flrx06e69646s6u0qu5xajz port map (
busIn_writedata_stm,
busIn_address_stm,
busIn_write_stm,
busIn_read_stm,
busOut_readdatavalid_dut,
busOut_readdata_dut,
in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x_stm,
in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x_stm,
in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm,
in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x_stm,
in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm,
in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm,
in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm,
in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x_stm,
out_sharedMemWireData_DSPB_MMSE_dut_input_IF_input_fifo_x_dut,
clk,
areset,
h_areset
);
sim : busSlaveFabric_DSPB_MMSE_dut_2puidkqw3flrx06e69646s6u0qu5xajz_stm port map (
busIn_writedata_stm,
busIn_address_stm,
busIn_write_stm,
busIn_read_stm,
busOut_readdatavalid_stm,
busOut_readdata_stm,
in_AMMregisterPortData_DSPB_MMSE_dut_Output_IF_RegOut_x_stm,
in_AMMregisterPortWriteEn_DSPB_MMSE_dut_Output_IF_RegOut_x_stm,
in_sharedMemPortAddr_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm,
in_sharedMemPortAddr_DSPB_MMSE_dut_input_IF_input_fifo_x_stm,
in_sharedMemPortData_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm,
in_sharedMemPortData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm,
in_sharedMemPortWriteEn_DSPB_MMSE_dut_Output_IF_output_fifo_x_stm,
in_sharedMemPortWriteEn_DSPB_MMSE_dut_input_IF_input_fifo_x_stm,
out_sharedMemWireData_DSPB_MMSE_dut_input_IF_input_fifo_x_stm,
clk,
areset,
h_areset
);
end normal;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.libproc.all;
use work.libeu.all;
entity fetch_stage is
port(
clk : in std_logic;
rst_n : in std_logic;
csro : in csrfile_out_type;
ico : in icache_out_type;
ici : out icache_in_type;
d : in fetch_in_type;
a : in fetch_in_type;
q : out fetch_out_type;
y : out fetch_out_type;
global_stall : in std_logic
);
end entity fetch_stage;
architecture rtl of fetch_stage is
alias fetch_reg_type is fetch_out_type;
signal r, rin : fetch_reg_type;
begin
comb : process(a, d, r, ico, csro) -- combinational process
variable v : fetch_reg_type;
begin
v := r;
v.pc := r.pc;
if d.w.exception = '1' then
v.pc := csro.evec;
elsif d.e.jump = '0' then
v.pc := r.pc4;
else
v.pc := d.e.pcjump;
end if;
v.pc4 := std_logic_vector(unsigned(v.pc) + 4);
ici.addr <= v.pc;
v.inst := ico.data;
-- ignore all changes
if d.d.stall_m = '1' or a.d.stall_csr = '1' then
v := r;
end if;
v.exception.cause := EXC_INST_ADDR_MISALIGNED;
v.exception.epc := v.pc;
if v.pc(1 downto 0) = "00" then
v.exception.valid := '0';
else
v.exception.valid := '1';
end if;
-- something up the pipe is throwing or we are jumping
if r.exception.valid = '1' -- we are currently throwing (nop next input)
or d.d.exception.valid = '1' -- decode stage
or d.e.exception.valid = '1' -- execute stage
or d.m.exception.valid = '1' -- memory stage
then
v.inst := x"00000013";
v.exception.valid := '0';
end if;
-- we are throwing
if v.exception.valid = '1' then
v.inst := x"00000013";
end if;
rin <= v;
q <= r;
y <= v;
end process;
reg : process(clk, rst_n) -- sequential process
begin
if rst_n = '0' then
r.pc <= x"0000000000000000";
r.pc4 <= x"0000000000000000";
r.inst <= x"00000013";
r.exception.epc <= (others => '0');
r.exception.cause <= (others => '0');
r.exception.valid <= '0';
elsif rising_edge(clk) then
if global_stall = '0' then
r <= rin;
end if;
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pixel_generator_tb is
end entity pixel_generator_tb;
architecture pixel_generator_tb_arq of pixel_generator_tb is
constant DATA_SIZE_TB : natural := 1;
signal clk_aux : std_logic := '0';
signal rst_aux : std_logic := '1';
signal data_aux : std_logic_vector(DATA_SIZE_TB - 1 downto 0) := "0";
signal video_on_aux : std_logic := '1';
signal red_out_aux : std_logic_vector(2 downto 0);
signal green_out_aux : std_logic_vector(2 downto 0);
signal blue_out_aux : std_logic_vector(1 downto 0);
begin
rst_aux <= '0' after 10 ns;
clk_aux <= not clk_aux after 20 ns;
data_aux <= "1" after 40 ns;
video_on_aux <= '0' after 100 ns;
DUT: entity work.pixel_generator
port map (
clk => clk_aux,
rst => rst_aux,
video_on => video_on_aux,
red_out => red_out_aux,
green_out => green_out_aux,
blue_out => blue_out_aux,
data => data_aux
);
end architecture pixel_generator_tb_arq;
|
<filename>simulation/modelsim/rtl_work/@decode4to16/_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Decode4to16 is
port(
data : in vl_logic_vector(3 downto 0);
eq0 : out vl_logic;
eq1 : out vl_logic;
eq10 : out vl_logic;
eq11 : out vl_logic;
eq12 : out vl_logic;
eq13 : out vl_logic;
eq14 : out vl_logic;
eq15 : out vl_logic;
eq2 : out vl_logic;
eq3 : out vl_logic;
eq4 : out vl_logic;
eq5 : out vl_logic;
eq6 : out vl_logic;
eq7 : out vl_logic;
eq8 : out vl_logic;
eq9 : out vl_logic
);
end Decode4to16;
|
<reponame>teratide/tydi-json<filename>test/schemas/battery_status/battery_status_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library work;
use work.UtilInt_pkg.all;
use work.Json_pkg.all;
package battery_status_pkg is
component BattSchemaParser is
generic (
EPC : natural := 8;
INT_WIDTH : natural := 16;
INT_P_PIPELINE_STAGES : natural := 1;
END_REQ_EN : boolean := false
);
port (
clk : in std_logic;
reset : in std_logic;
-- Stream(
-- Bits(8),
-- t=EPC,
-- d=NESTING_LEVEL,
-- c=8
-- )
in_valid : in std_logic;
in_ready : out std_logic;
in_data : in std_logic_vector(8*EPC-1 downto 0);
in_last : in std_logic_vector(2*EPC-1 downto 0);
in_stai : in std_logic_vector(log2ceil(EPC)-1 downto 0) := (others => '0');
in_endi : in std_logic_vector(log2ceil(EPC)-1 downto 0) := (others => '1');
in_strb : in std_logic_vector(EPC-1 downto 0);
end_req : in std_logic := '0';
end_ack : out std_logic;
-- Stream(
-- Bits(64),
-- d=NESTING_LEVEL,
-- c=2
-- )
out_valid : out std_logic;
out_ready : in std_logic;
out_data : out std_logic_vector(INT_WIDTH-1 downto 0);
out_strb : out std_logic;
out_last : out std_logic_vector(2 downto 0)
);
end component;
end battery_status_pkg;
|
-- #################################################################################################
-- # << NEORV32 - Example setup including the bootloader, for the AlhambraII (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, <NAME>. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) <NAME>olting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_AlhambraII_BoardTop_MinimalBoot is
port (
-- external clock (12 MHz)
AlhambraII_CLK : in std_logic;
-- LED outputs
AlhambraII_LED0 : out std_logic;
AlhambraII_LED1 : out std_logic;
AlhambraII_LED2 : out std_logic;
AlhambraII_LED3 : out std_logic;
AlhambraII_LED4 : out std_logic;
AlhambraII_LED5 : out std_logic;
AlhambraII_LED6 : out std_logic;
AlhambraII_LED7 : out std_logic;
-- UART0
AlhambraII_RX : in std_logic;
AlhambraII_TX : out std_logic
);
end entity;
architecture neorv32_AlhambraII_BoardTop_MinimalBoot_rtl of neorv32_AlhambraII_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 12000000; -- clock frequency in Hz
-- reset generator --
signal rst_cnt : std_logic_vector(8 downto 0) := (others => '0'); -- initialized by bitstream
signal sys_rstn : std_logic;
-- internal IO connection --
signal con_gpio_o : std_ulogic_vector(3 downto 0);
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- Reset Generator ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
reset_generator: process(AlhambraII_CLK)
begin
if rising_edge(AlhambraII_CLK) then
if (rst_cnt(rst_cnt'left) = '0') then
rst_cnt <= std_logic_vector(unsigned(rst_cnt) + 1);
end if;
end if;
end process reset_generator;
sys_rstn <= rst_cnt(rst_cnt'left);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
MEM_INT_IMEM_SIZE => 4*1024, -- size of processor-internal instruction memory in bytes
MEM_INT_DMEM_SIZE => 2*1024 -- size of processor-internal data memory in bytes
)
port map (
-- Global control --
clk_i => std_ulogic(AlhambraII_CLK),
rstn_i => std_ulogic(sys_rstn),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => AlhambraII_TX, -- UART0 send data
uart_rxd_i => AlhambraII_RX, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
AlhambraII_LED0 <= con_gpio_o(0);
AlhambraII_LED1 <= con_gpio_o(1);
AlhambraII_LED2 <= con_gpio_o(2);
AlhambraII_LED3 <= con_gpio_o(3);
AlhambraII_LED4 <= '0'; -- unused
AlhambraII_LED5 <= con_pwm(0);
AlhambraII_LED6 <= con_pwm(1);
AlhambraII_LED7 <= con_pwm(2);
end architecture;
|
<gh_stars>1-10
--
-- Copyright (c) 2013, 2014 <NAME>, University of Zagreb
-- Copyright (c) 2015 <NAME>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-- SUCH DAMAGE.
--
-- $Id$
--
-- asynchronous FIFO adapter from system memory
-- running at CPU clock (around 100 MHz) with
-- unpredictable access time to
-- to video system, running at pixel clock (25 MHz)
-- which must have constant data rate
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity videofifo is
generic (
C_bram: boolean := false; -- true: use bram as fifo storage, false: use luts
C_synclen: integer := 3; -- bits in cpu-to-pixel clock synchronizer
-- (0: disable rewind and be ordinary sequential fifo)
-- (>0: fifo will be loaded from RAM in full steps
-- each full step is a count of 32-bit words.
-- rewind signal can again output data stream from fifo
-- starting from last full step it was filled from RAM,
-- saves RAM bandwidth during text mode or bitmap vertial line doubling
C_step: integer := 0;
-- postpone step fetch by N 32-bit words
-- set it to 1-3 for bandwidth saving with soft scroll
C_postpone_step: integer := 0;
-- defines the length of the FIFO: 4 * 2^C_length bytes
-- default value of 4: length = 16 * 32 bits = 16 * 4 bytes = 64 bytes
C_width: integer := 4 -- bits width of fifo address
);
port (
clk, clk_pixel: in std_logic;
addr_strobe: out std_logic;
addr_out: out std_logic_vector(29 downto 2);
base_addr: in std_logic_vector(29 downto 2);
-- debug_rd_addr: out std_logic_vector(29 downto 2);
data_ready: in std_logic;
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
start: in std_logic; -- rising edge sensitive will reset fifo RAM to base address, value 1 allows start of reading
frame: out std_logic; -- output CPU clock synchronous start edge detection (1 CPU-clock wide pulse for FB interrupt)
rewind: in std_logic := '0'; -- rising edge sets output data pointer to the start of last full step
-- rewind is useful to re-read text line, saving RAM bandwidth.
-- rewind is possible at any time but is be normally issued
-- during H-blank period - connected to hsync signal.
fetch_next: in std_logic -- edge sensitive fetch next value (current data consumed)
);
end videofifo;
architecture behavioral of videofifo is
-- Types
constant C_length: integer := 2**C_width; -- 1 sll C_width - shift logical left
type pixbuf_dpram_type is array(0 to C_length-1) of std_logic_vector(31 downto 0);
-- Internal state
signal R_pixbuf: pixbuf_dpram_type;
signal R_sram_addr: std_logic_vector(29 downto 2);
signal R_pixbuf_rd_addr, R_pixbuf_wr_addr, S_pixbuf_wr_addr_next: std_logic_vector(C_width-1 downto 0);
signal S_pixbuf_out_mem_addr: std_logic_vector(C_width-1 downto 0);
signal S_pixbuf_in_mem_addr: std_logic_vector(C_width-1 downto 0);
signal S_bram_write, S_data_write: std_logic;
signal S_bram_data_in: std_logic_vector(31 downto 0);
signal R_bram_in_addr: std_logic_vector(C_width-1 downto 0);
signal R_pixbuf_out_addr: std_logic_vector(C_width-1 downto 0);
signal R_delay_fetch: integer range 0 to 2*C_step;
signal need_refill: std_logic;
signal toggle_read_complete: std_logic;
signal clksync, startsync, rewindsync: std_logic_vector(C_synclen-1 downto 0);
-- clean start: '1' will reset fifo to its base address
-- '0' will allow fifo normal sequential operation
signal clean_start, clean_fetch: std_logic;
-- clean rewind: '1' will rewind fifo to its last full step
-- '0' will allow fifo normal sequential operation
signal clean_rewind: std_logic;
begin
S_pixbuf_wr_addr_next <= R_pixbuf_wr_addr + 1;
-- clk-to-clk_pixel synchronizer:
-- clk_pixel rising edge is detected using shift register
-- edge detection happens after delay (clk * synclen)
-- then rd is set high for one clk cycle
-- intiating fetch of new data from RAM fifo
process(clk_pixel)
begin
if rising_edge(clk_pixel) and fetch_next = '1' then
toggle_read_complete <= not toggle_read_complete;
end if;
end process;
-- start signal which resets fifo
-- can be clock asynchronous and may
-- lead to unclean or partial fifo reset which results
-- in early fetch and visually whole picure flickers
-- by shifting one byte left
-- input start is passed it through a flip-flop
-- it generates clean_start and we got rid of the flicker
process(clk)
begin
if rising_edge(clk) then
-- synchronize clk_pixel to clk with shift register
clksync <= clksync(C_synclen-2 downto 0) & toggle_read_complete;
startsync <= startsync(C_synclen-2 downto 0) & start;
rewindsync <= rewindsync(C_synclen-2 downto 0) & rewind;
end if;
end process;
-- XOR: difference in 2 consecutive clksync values
-- create a short pulse that lasts one CPU clk period.
-- This signal is request to fetch new data
clean_fetch <= clksync(C_synclen-2) xor clksync(C_synclen-1);
-- clean start produced from a delay thru clock synchronous shift register
-- clean_start <= startsync(C_synclen-1); -- level
clean_start <= startsync(C_synclen-2) and not startsync(C_synclen-1); -- rising edge
-- at start of frame generate pulse of 1 CPU clock
-- rising edge detection of start signal
-- useful for VSYNC frame interrupt
frame <= clean_start; -- must be rising edge for CPU interrupt, not level
--
-- Refill the circular buffer with fresh data from SRAM-a
--
process(clk)
begin
if rising_edge(clk) then
if clean_start = '1' then
R_sram_addr <= base_addr;
R_pixbuf_wr_addr <= (others => '0');
else
if data_ready = '1' and need_refill = '1' then -- BRAM must use this
-- if data_ready = '1' then -- may work with SDRAM?
if not C_bram then
R_pixbuf(TO_INTEGER(UNSIGNED(R_pixbuf_wr_addr))) <= data_in;
end if;
R_sram_addr <= R_sram_addr + 1;
R_pixbuf_wr_addr <= S_pixbuf_wr_addr_next;
end if;
end if;
end if;
end process;
need_refill <='1' when clean_start = '0' and S_pixbuf_wr_addr_next /= R_pixbuf_rd_addr else '0';
addr_strobe <= '1' when need_refill = '1' else '0';
addr_out <= R_sram_addr;
-- Dequeue pixel data from the circular buffer
-- by incrementing R_pixbuf_rd_addr on rising edge of clk
--
process(clk)
begin
if rising_edge(clk) then
if clean_start = '1' then
R_pixbuf_rd_addr <= (others => '0'); -- this will read data from RAM
if C_step /= 0 then
R_pixbuf_out_addr <= (others => '0'); -- this will output buffered data
R_delay_fetch <= 2*C_step-1;
end if;
else
if clean_fetch = '1' then
if C_step = 0 then
R_pixbuf_rd_addr <= R_pixbuf_rd_addr + 1; -- R_pixbuf_out_addr + 1 ??
end if;
if C_step /= 0 then
R_pixbuf_out_addr <= R_pixbuf_out_addr + 1;
if R_delay_fetch = 0 then
R_delay_fetch <= C_step - 1; -- delay fetch will actually delay C_step+1 steps
else
R_delay_fetch <= R_delay_fetch - 1;
end if;
if R_delay_fetch = C_step - 2 - C_postpone_step then
-- C_step-2 will fetch at begin of new line
-- C_step-3 will fetch 1 word after begin of new line.
-- that is for soft scroll bandiwdth saving.
-- old line consumed, new line currently displayed
-- rd_addr is also rewind point,
-- incrementing it will discard old data from fifo
R_pixbuf_rd_addr <= R_pixbuf_rd_addr + C_step; -- R_pixbuf_out_addr + 1 ??
end if;
end if;
end if;
if C_step /= 0 then
if clean_rewind = '1' then
R_pixbuf_out_addr <= R_pixbuf_rd_addr; -- R_pixbuf_rd_addr-1 ??
R_delay_fetch <= 2 * C_step - 1;
-- delay fetch will actually delay C_step+1 steps
-- we should be allowed to rewind after we fetch complete line
-- and fifo pointer jumps to next line
-- take care not to discard old data immediately after we jump
-- I'm not sure where to put correct +1 now...
end if;
end if;
end if;
end if;
end process;
G_no_bram: if not C_bram generate
rewind_disabled_no_bram: if C_step = 0 generate
data_out <= R_pixbuf(TO_INTEGER(UNSIGNED(R_pixbuf_rd_addr)));
end generate; -- rewind_disabled_no_bram
rewind_enabled_no_bram: if C_step /= 0 generate
clean_rewind <= rewindsync(C_synclen-2) and not rewindsync(C_synclen-1); -- rising edge
data_out <= R_pixbuf(TO_INTEGER(UNSIGNED(R_pixbuf_out_addr)));
end generate; -- rewind_enabled_no_bram
end generate; -- G_no_bram
G_bram: if C_bram generate
-- S_compositing_erase <= '0'; -- never erase (allows rewind to used data)
S_data_write <= data_ready and need_refill and not clean_start;
-- writing to buffer sequentially
S_pixbuf_in_mem_addr <= R_pixbuf_wr_addr;
S_bram_data_in <= data_in;
S_bram_write <= S_data_write;
R_bram_in_addr <= S_pixbuf_in_mem_addr; -- not a register but pass-thru signal
rewind_disabled: if C_step = 0 generate
S_pixbuf_out_mem_addr <= R_pixbuf_rd_addr;
end generate;
rewind_enabled: if C_step /= 0 generate
clean_rewind <= rewindsync(C_synclen-2) and not rewindsync(C_synclen-1); -- rising edge
S_pixbuf_out_mem_addr <= R_pixbuf_out_addr;
end generate;
linememory: entity work.bram_true2p_1clk
generic map (
dual_port => True, -- one port takes data from RAM, other port outputs to video
data_width => 32,
addr_width => C_width
)
port map (
clk => clk,
we_a => S_bram_write,
-- we_b => '0',
addr_a => R_bram_in_addr,
addr_b => S_pixbuf_out_mem_addr,
data_in_a => S_bram_data_in,
-- data_in_b => (others => '0'),
data_out_a => open,
data_out_b => data_out
);
end generate; -- G_bram
end;
|
<reponame>XarkLabs/BenEaterVHDL
--
-- Based on <NAME>'s build of the SAP breadboard computer and his excellent videos.
-- https://eater.net/
--
-- Copyright (c) 2017 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tx_uart is
generic (
C_SYSTEM_HZ: integer := 12_000_000; -- FPGA clock in Hz
C_BPS: integer := 9600; -- UART transmition rate in bits per second (aka baud)
C_AUTOBAUD: boolean := false
);
port (
rst_i: IN STD_LOGIC; -- reset
clk_i: IN STD_LOGIC; -- FPGA clock
we_i: IN STD_LOGIC; -- pulse high to send byte (when busy_o is low)
data_i: IN STD_LOGIC_VECTOR(7 downto 0); -- data to send
busy_o: OUT STD_LOGIC; -- high when UART busy transmitting
tx_o: OUT STD_LOGIC; -- TX pin output
rx_i: IN STD_LOGIC -- TX pin output
);
end tx_uart;
architecture RTL of tx_uart is
CONSTANT bits_for_clock: INTEGER := 16;
CONSTANT clocks_per_bit: UNSIGNED(bits_for_clock-1 downto 0) := to_unsigned((C_SYSTEM_HZ / C_BPS) - 1, bits_for_clock); -- determine number of FPGA clocks that will be one bit for UART bits per second
SIGNAL bps_count: UNSIGNED(bits_for_clock-1 downto 0) := clocks_per_bit;
SIGNAL bps_counter: UNSIGNED(bits_for_clock-1 downto 0) := (others => '0');
SIGNAL shift_out: STD_LOGIC_VECTOR(10 downto 0) := (others => '0');
SIGNAL busy_r: STD_LOGIC := '0';
SIGNAL bit_ff: STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
SIGNAL bit_time: UNSIGNED(bits_for_clock-1 downto 0) := (others => '0');
SIGNAL bit_time_count: UNSIGNED(bits_for_clock-1 downto 0) := (others => '0');
BEGIN
PROCESS(clk_i, rst_i)
BEGIN
if rst_i='1' then
bps_counter <= (others => '0');
shift_out <= "00000000001";
elsif rising_edge(clk_i) then
if (busy_r = '0') then
if (we_i = '1') then
shift_out <= "11" & data_i & "0"; -- stop bit & data & start bit
bps_counter <= bps_count;
end if;
else
if (bps_counter = 0) then
bps_counter <= bps_count;
shift_out <= "0" & shift_out(10 downto 1);
else
bps_counter <= bps_counter - 1;
end if;
end if;
end if;
END PROCESS;
busy_r <= '1' when (shift_out /= "00000000001") else '0';
busy_o <= busy_r OR we_i;
tx_o <= shift_out(0);
autobaud: IF C_AUTOBAUD GENERATE
PROCESS(clk_i, rst_i)
BEGIN
if rst_i='1' then
bit_ff <= "1111";
bit_time <= (others => '1');
bit_time_count <= (others => '0');
bps_count <= clocks_per_bit;
else
if rising_edge(clk_i) then
bit_ff <= bit_ff(2 downto 0) & rx_i;
if (bit_ff(3 downto 0) = "1100") then
bit_time_count <= (others => '0');
elsif (bit_ff(3 downto 0) = "0011") then
if (bit_time_count < bit_time) then
bit_time <= bit_time_count;
bps_count <= bit_time_count;
end if;
else
bit_time_count <= bit_time_count + 1;
end if;
end if;
end if;
END PROCESS;
END GENERATE;
END architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--USE ieee.math_real.ceil;
--USE ieee.math_real.log2;
use work.kernel_pkg.all;
use work.clogb2_Pkg.all;
use work.Kernel3x3;
entity ConvChannelTemplate is
generic(
BIT_WIDTH_IN : integer := 8;
KERNEL_WIDTH_OUT : integer := 20;
BIT_WIDTH_OUT : integer := 8;
N : integer := 2;
OUTPUT_MSB : integer := 15;
BIAS : integer := 0
);
port(
Clk_i : in std_logic;
n_Res_i : in std_logic;
Valid_i : in std_logic;
Valid_o : out std_logic;
Last_i : in std_logic;
Last_o : out std_logic;
Ready_i : in std_logic;
Ready_o : out std_logic;
X_i : in std_logic_vector(N*BIT_WIDTH_IN*KERNEL_SIZE - 1 downto 0);
Y_o : out unsigned(BIT_WIDTH_OUT - 1 downto 0)
);
end ConvChannelTemplate;
architecture beh of ConvChannelTemplate is
--constant SUM_WIDTH : integer := KERNEL_WIDTH_OUT + integer(ceil(log2(real(N)))) + 1;
constant SUM_WIDTH : integer := KERNEL_WIDTH_OUT + clogb2(N)+ 1;
signal K_out : signed(N*KERNEL_WIDTH_OUT - 1 downto 0);
type term_vector_t is array (integer range <>) of signed(SUM_WIDTH - 1 downto 0);
signal term_vector : term_vector_t(0 to N-1);
type kernel_array_t is array (0 to N-1) of weight_array_t;
constant KERNELS : kernel_array_t := ((-90,80,-70,-60,50,-40,30,-20,-10), (10,20,-30,-40,50,-60,-70,80,90));
function ternary_adder_tree
(
input_term_vector : term_vector_t
)
return signed is
constant N_t : natural := input_term_vector'length;
constant t_vec : term_vector_t(0 to (N_t - 1)) := input_term_vector;
constant LEFT_TREE_N : natural := ((N_t + 2) / 3);
constant MIDDLE_TREE_N : natural := (((N_t - LEFT_TREE_N) + 1) / 2);
constant RIGHT_TREE_N : natural := (N_t - LEFT_TREE_N - MIDDLE_TREE_N);
constant LEFT_TREE_LOW_INDEX : natural := 0;
constant LEFT_TREE_HIGH_INDEX : natural := (LEFT_TREE_LOW_INDEX + LEFT_TREE_N - 1);
constant MIDDLE_TREE_LOW_INDEX : natural := (LEFT_TREE_HIGH_INDEX + 1);
constant MIDDLE_TREE_HIGH_INDEX : natural := (MIDDLE_TREE_LOW_INDEX + MIDDLE_TREE_N - 1);
constant RIGHT_TREE_LOW_INDEX : natural := (MIDDLE_TREE_HIGH_INDEX + 1);
constant RIGHT_TREE_HIGH_INDEX : natural := (RIGHT_TREE_LOW_INDEX + RIGHT_TREE_N - 1);
begin
if (N_t = 1) then
return t_vec(0);
elsif (N_t = 2) then
return t_vec(0) + t_vec(1);
else
return ternary_adder_tree(t_vec(LEFT_TREE_LOW_INDEX to LEFT_TREE_HIGH_INDEX ))
+ternary_adder_tree(t_vec(MIDDLE_TREE_LOW_INDEX to MIDDLE_TREE_HIGH_INDEX))
+ternary_adder_tree(t_vec(RIGHT_TREE_LOW_INDEX to RIGHT_TREE_HIGH_INDEX ));
end if;
end function ternary_adder_tree;
signal start_addition : std_logic := '0';
signal is_last : std_logic := '0';
begin
Ready_o <= not(Valid_i) and Ready_i and not(start_addition);
kernels_gen : for I in 0 to N-1 generate
krnl : entity Kernel3x3 generic map(
BIT_WIDTH_IN,
KERNEL_WIDTH_OUT,
KERNELS(I)
) port map(
Clk_i,
n_Res_i,
Valid_i,
X_i((I+1)*BIT_WIDTH_IN*KERNEL_SIZE - 1 downto I*BIT_WIDTH_IN*3*3),
K_out((I+1)*KERNEL_WIDTH_OUT - 1 downto I*KERNEL_WIDTH_OUT)
);
term_vector(I) <= resize(K_out((I+1)*KERNEL_WIDTH_OUT - 1 downto I*KERNEL_WIDTH_OUT), SUM_WIDTH);
end generate;
adder : process(Clk_i, n_Res_i)
variable add_out : signed(SUM_WIDTH-1 downto 0);
begin
if n_Res_i = '0' then
Y_o <= (others => '0');
Valid_o <= '0';
Last_o <= '0';
start_addition <= '0';
is_last <= '0';
elsif rising_edge(Clk_i) then
Valid_o <= '0';
Last_o <= '0';
if start_addition = '1' and Ready_i = '1' then
add_out := ternary_adder_tree(term_vector) + to_signed(BIAS, SUM_WIDTH);
if add_out(SUM_WIDTH-1) = '1' then
Y_o <= (others => '0');
elsif add_out(SUM_WIDTH-1 downto OUTPUT_MSB+1) /= (add_out(SUM_WIDTH-1 downto OUTPUT_MSB+1)'range => '0') then
Y_o <= (others => '1');
else
Y_o <= unsigned(std_logic_vector(add_out(OUTPUT_MSB downto OUTPUT_MSB-BIT_WIDTH_OUT+1)));
end if;
Valid_o <= '1';
if is_last = '1' then
Last_o <= '1';
else
Last_o <= '0';
end if;
is_last <= '0';
start_addition <= '0';
end if;
if Valid_i = '1' then
is_last <= Last_i;
start_addition <= '1';
end if;
end if;
end process;
end beh;
|
-----------------------------------------------------------------
-- --
-----------------------------------------------------------------
--
-- Max11202Master.vhd -
--
-- Copyright(c) SLAC National Accelerator Laboratory 2000
--
-- Author: <NAME>
-- Created on: 7/18/2017 3:10:01 PM
-- Last change: JO 4/27/2018 9:08:38 AM
--
-------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- Max11202Master.vhd
-- From
-- File : SpiMaster.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : SLAC National Accelerator Laboratory
-- Created : 2013-05-24
-- Last update: 2018-04-19
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--use ieee.math_real.all;
use work.StdRtlPkg.all;
entity max11202Master is
generic (
TPD_G : time := 1 ns;
CLK_PERIOD_G : real := 8.0E-9;
SERIAL_SCLK_PERIOD_G : real := 1.0E-6); -- 1 MHz
port (
--Global Signals
clk : in sl;
Rst : in sl;
-- Parallel interface
StartConv : in sl;
rdDataA : out slv(31 downto 0);
rdDataB : out slv(31 downto 0);
rdDataC : out slv(31 downto 0);
Sclk : out sl;
Sdin : in slv(2 downto 0)
);
end max11202Master;
architecture rtl of max11202Master is
constant SERIAL_CLK_PERIOD_DIV2_CYCLES_C : integer := integer(SERIAL_SCLK_PERIOD_G / (2.0*CLK_PERIOD_G));
constant SCLK_COUNTER_SIZE_C : integer := bitSize(SERIAL_CLK_PERIOD_DIV2_CYCLES_C);
-- Types
type data24 is array (2 downto 0) of slv(23 downto 0);
type StateType is (
IDLE_S,
WAIT_READY_S,
SHIFT_S,
SAMPLE_S,
DONE_S);
type RegType is record
state : StateType;
syncSdin : slv(2 downto 0);
rdData : data24;
rdDataA : slv(31 downto 0);
rdDataB : slv(31 downto 0);
rdDataC : slv(31 downto 0);
dataCounter : slv(25 downto 0);
sclkCounter : slv(SCLK_COUNTER_SIZE_C-1 downto 0);
Sclk : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
syncSdin => "000",
rdData => (others => x"0000000"),
rdDataA => (others => '0'),
rdDataB => (others => '0'),
rdDataC => (others => '0'),
dataCounter => (others => '0'),
sclkCounter => (others => '0'),
Sclk => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
begin
comb : process (r, Rst, sdin, startConv) is
variable v : RegType;
begin
v := r;
v.SyncSdin := Sdin;
case (r.state) is
when IDLE_S =>
v.dataCounter := (others => '0');
v.sclkCounter := (others => '0');
v.rdData(0) := (others => '0');
v.rdData(1) := (others => '0');
v.rdData(2) := (others => '0');
if (StartConv = '1') then
-- Exit from sleep state by dropping clock, start convert
v.Sclk := '0';
v.state := WAIT_READY_S;
end if;
when WAIT_READY_S =>
-- wait for all three ADC to be ready
if (r.SyncSdin = "000") then -- All ADCs are ready
v.state := Shift_S;
end if;
when SHIFT_S =>
-- Wait half a clock period then shift out the next data bit
v.sclkCounter := r.sclkCounter + 1;
if (r.sclkCounter = SERIAL_CLK_PERIOD_DIV2_CYCLES_C) then
v.sclkCounter := (others => '0');
v.Sclk := '1';
v.state := SAMPLE_S;
end if;
when SAMPLE_S =>
-- Wait half a clock period then sample the next data bit
v.sclkCounter := r.sclkCounter + 1;
if (r.sclkCounter = SERIAL_CLK_PERIOD_DIV2_CYCLES_C) then
v.sclkCounter := (others => '0');
v.rdData(0) := r.rdData(0)(22 downto 0) & SDin(0);
v.rdData(1) := r.rdData(1)(22 downto 0) & SDin(1);
v.rdData(2) := r.rdData(2)(22 downto 0) & SDin(2);
v.dataCounter := r.dataCounter + 1;
if (r.dataCounter = 23) then
v.Sclk := '1';
v.state := DONE_S;
else
v.Sclk := '0';
v.state := SHIFT_S;
end if;
end if;
when DONE_S =>
v.sclkCounter := r.sclkCounter + 1;
if (r.sclkCounter = SERIAL_CLK_PERIOD_DIV2_CYCLES_C) then
v.sclkCounter := (others => '0');
-- sign extend 24 bits to 32 bits
v.rdDataA := r.rdData(0)(23) & r.rdData(0)(23) & r.rdData(0)(23) & r.rdData(0)(23) &
r.rdData(0)(23) & r.rdData(0)(23) & r.rdData(0)(23) & r.rdData(0)(23) &
r.rdData(0);
v.rdDataB := r.rdData(1)(23) & r.rdData(1)(23) & r.rdData(1)(23) & r.rdData(1)(23) &
r.rdData(1)(23) & r.rdData(1)(23) & r.rdData(1)(23) & r.rdData(1)(23) &
r.rdData(1);
v.rdDataC := r.rdData(2)(23) & r.rdData(2)(23) & r.rdData(2)(23) & r.rdData(2)(23) &
r.rdData(2)(23) & r.rdData(2)(23) & r.rdData(2)(23) & r.rdData(2)(23) &
r.rdData(2);
v.state := IDLE_S;
end if;
when others => null;
end case;
rdDataA <= r.rdDataA;
rdDataB <= r.rdDataB;
rdDataC <= r.rdDataC;
if (Rst = '1') then
v := REG_INIT_C;
end if;
rin <= v;
Sclk <= r.Sclk;
end process comb;
seq : process (clk) is
begin
if (rising_edge(clk)) then
r <= rin after TPD_G;
end if;
end process seq;
end rtl;
|
-------------------------------------------------------------------------------
-- TOP
-- This top level component is designed for the Spartan 6 LX9 Microboard
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
generic (
baud : positive;
clock_frequency : positive
);
port (
clock_y3 : in std_logic;
user_reset : in std_logic;
usb_rs232_rxd : in std_logic;
usb_rs232_txd : out std_logic
);
end top;
architecture rtl of top is
component loopback is
generic (
baud : positive;
clock_frequency : positive
);
port(
clock : in std_logic;
reset : in std_logic;
rx : in std_logic;
tx : out std_logic
);
end component loopback;
signal tx, rx, rx_sync, reset, reset_sync : std_logic;
begin
----------------------------------------------------------------------------
-- Loopback instantiation
----------------------------------------------------------------------------
loopback_inst1 : loopback
generic map (
baud => baud,
clock_frequency => clock_frequency
)
port map (
clock => clock_y3,
reset => reset,
rx => rx,
tx => tx
);
----------------------------------------------------------------------------
-- Deglitch inputs
----------------------------------------------------------------------------
deglitch : process (clock_y3)
begin
if rising_edge(clock_y3) then
rx_sync <= usb_rs232_rxd;
rx <= rx_sync;
reset_sync <= user_reset;
reset <= reset_sync;
usb_rs232_txd <= tx;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:11:10 04/17/2011
-- Design Name:
-- Module Name: ball - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ball is
port ( x: out std_logic_vector(3 downto 0);
y: out std_logic_vector(4 downto 0);
ad: in std_logic;
padup,padwn: in std_logic_vector(2 downto 0):="100";
nthitup,nthitdwn: out std_logic:='0';
breset: in std_logic
);
end ball;
architecture Behavioral of ball is
signal leftright,updwn : std_logic :='0';
signal ballx : std_logic_vector(3 downto 0) := "0100";
signal bally : std_logic_vector(4 downto 0) := "01000";
begin
process(ad)
begin
if(ad='1')
then
if(breset = '1')
then
ballx <= "0100";
bally <= "01000";
leftright <= '0';
nthitup <='0';
updwn <= '0';
else
if (leftright = '1' and updwn = '1')
then
if ( ballx = "0111")
then bally <= bally +"01";
ballx<=ballx - "01";
leftright <= '0';
nthitup <='0';
nthitdwn <='0';
else
if(bally = "01110")
then
if(padup = ballx or padup = ballx - 1)
then ballx <= ballx +"01";
bally <= bally - "01";
updwn <= '0';
nthitup <='0';
nthitdwn <='0';
else ballx <= "0100";
bally <= "01000";
leftright <= '0';
nthitup <='1';
updwn <= '0';
end if;
else ballx <= ballx + "01";
bally <= bally + "01";
nthitup <='0';
nthitdwn <='0';
end if;
end if;
end if;
if (leftright = '1' and updwn = '0')
then
if ( ballx = "0111")
then bally <= bally -"01";
ballx<=ballx - "01";
leftright <= '0';
nthitup <='0';
nthitdwn <='0';
else
if(bally = "00001")
then
if(padup = ballx or padup = ballx - 1)
then ballx <= ballx +"01";
bally <= bally + "01";
updwn <= '1';
nthitup <='0';
nthitdwn <='0';
else ballx <= "0100";
bally <= "01000";
leftright <= '1';
nthitdwn <='1';
updwn <= '0';
end if;
else ballx <= ballx + "01";
bally <= bally - "01";
nthitup <='0';
nthitdwn <='0';
end if;
end if;
end if;
if (leftright = '0' and updwn = '1')
then
if ( ballx = "0000")
then bally <= bally +"01";
ballx<=ballx + "01";
leftright <= '1';
nthitup <='0';
nthitdwn <='0';
else
if(bally = "01110")
then
if(padup = ballx or padup = ballx - "01")
then ballx <= ballx -"01";
bally <= bally - "01";
updwn <= '0';
nthitup <='0';
nthitdwn <='0';
else ballx <= "0100";
bally <= "01000";
leftright <= '0';
nthitup <='1';
updwn <= '0';
end if;
else ballx <= ballx - "01";
bally <= bally + "01";
nthitup <='0';
nthitdwn <='0';
end if;
end if;
end if;
if (leftright = '0' and updwn = '0')
then
if ( ballx = "0000")
then bally <= bally -"01";
ballx<=ballx + "01";
leftright <= '1';
nthitup <='0';
nthitdwn <='0';
else
if(bally = "00001")
then
if(padup = ballx or padup = ballx - "01")
then ballx <= ballx -"01";
bally <= bally + "01";
updwn <= '1';
nthitup <='0';
nthitdwn <='0';
else ballx <= "0100";
bally <= "01000";
leftright <= '1';
nthitdwn <='1';
updwn <= '0';
end if;
else ballx <= ballx - "01";
bally <= bally - "01";
nthitup <='0';
nthitdwn <='0';
end if;
end if;
end if;
end if;
end if;
end process;
x<=ballx;
y<=bally;
end Behavioral;
|
<reponame>Kur1su0/Computer-Arch-and-Design
--
-- VHDL Architecture CAD_lib.rst_syn.behav
--
-- Created:
-- by - W.UNKNOWN (DESKTOP-86TQKQ1)
-- at - 02:05:44 02/23/2021
--
-- using Mentor Graphics HDL Designer(TM) 2018.2 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY rst_syn IS
GENERIC(width : NATURAL RANGE 1 TO 64 := 8);
PORT(
Din0,Din1: IN std_logic_vector(width-1 downto 0);
rst: IN std_logic;
Dout: OUT std_logic_vector(width-1 downto 0)
);
END ENTITY rst_syn;
--
ARCHITECTURE behav OF rst_syn IS
BEGIN
process(Din0,Din1,rst)
begin
end process;
END ARCHITECTURE behav;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity tb_datacounter is
end tb_datacounter ;
architecture arc_tb_datacounter of tb_datacounter is
component datacounter is
port ( resetN : in std_logic ;
clk : in std_logic ;
ena_dcount : in std_logic ;
clr_dcount : in std_logic ;
eoc : out std_logic ;
dcount : inout std_logic_vector(2 downto 0) ) ;
end component datacounter ;
signal resetN : std_logic ;
signal clk : std_logic ;
signal ena_dcount : std_logic ;
signal clr_dcount : std_logic ;
signal eoc : std_logic ;
signal dcount : std_logic_vector(2 downto 0) ;
begin
eut: datacounter
port map ( resetN, clk, ena_dcount, clr_dcount, eoc, dcount ) ;
resetN <= '0' , '1' after 100 ns ;
process
begin
clk <= '0' ; wait for 50 ns ;
clk <= '1' ; wait for 50 ns ;
end process ;
process
begin
ena_dcount <= '0'; clr_dcount <= '0'; wait for 100 ns ;
ena_dcount <= '0'; clr_dcount <= '1'; wait for 100 ns ;
ena_dcount <= '1'; clr_dcount <= '0'; wait for 900 ns ;
ena_dcount <= '1'; clr_dcount <= '1'; wait for 100 ns ;
report "End of test";
wait ;
end process ;
end arc_tb_datacounter ;
--assert ( q = '1' and q_bar = '0')
--report "loading '1' to latch"
--severity error;
|
<filename>FlexGripPlus_4.4/RTL/SMP/WarpUnit/fence_registers.vhd
----------------------------------------------------------------------------------
-- Company: Univerity of Massachusetts
-- Engineer: <NAME>
--
-- Create Date: 17:50:27 09/19/2010
-- Module Name: fence_registers - arch
-- Project Name: GPGPU
-- Target Devices:
-- Tool versions: ISE 10.1
-- Description:
--
----------------------------------------------------------------------------
-- Revisions:
-- REV: Date: Description:
-- 0.1.a 9/13/2010 Created Top level file
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.gpgpu_package.all;
entity fence_registers is
port(
clk_in : in std_logic;
host_reset : in std_logic;
cta_id_in : in std_logic_vector(3 downto 0);
cta_id_ld : in std_logic;
fence_en_in : in std_logic;
fence_en_ld : in std_logic;
cta_id_out : out std_logic_vector(3 downto 0);
fence_en_out : out std_logic
);
end fence_registers;
architecture arch of fence_registers is
begin
process(clk_in, host_reset)
begin
if host_reset = '1' then
cta_id_out <= (others => '0');
fence_en_out <= '0';
elsif rising_edge(clk_in) then
if fence_en_ld = '1' then
fence_en_out <= fence_en_in;
end if;
if cta_id_ld = '1' then
cta_id_out <= cta_id_in;
end if;
end if;
end process;
end arch;
|
<filename>ConwayFinal_tb.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:16 01/17/2015
-- Design Name:
-- Module Name: D:/Docs/Xilinx/ConwayFinal/ConwayFinal_tb.vhd
-- Project Name: ConwayFinal
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ConwayFinal
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ConwayFinal_tb IS
END ConwayFinal_tb;
ARCHITECTURE behavior OF ConwayFinal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ConwayFinal
PORT(
clkin : IN std_logic;
dout : OUT std_logic_vector(7 downto 0);
hsync : OUT std_logic;
vsync : OUT std_logic
);
END COMPONENT;
--Inputs
signal clkin : std_logic := '0';
--Outputs
signal dout : std_logic_vector(7 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
-- Clock period definitions
constant clkin_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ConwayFinal PORT MAP (
clkin => clkin,
dout => dout,
hsync => hsync,
vsync => vsync
);
-- Clock process definitions
clkin_process :process
begin
clkin <= '0';
wait for clkin_period/2;
clkin <= '1';
wait for clkin_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clkin_period*10;
-- insert stimulus here
wait;
end process;
process (clkin)
file file_pointer: text is out "write.txt";
variable line_el: line;
begin
if rising_edge(clkin) then
-- Write the time
write(line_el, now); -- write the line.
write(line_el, ":"); -- write the line.
-- Write the hsync
write(line_el, " ");
write(line_el, hsync); -- write the line.
-- Write the vsync
write(line_el, " ");
write(line_el, vsync); -- write the line.
-- Write the red
write(line_el, " ");
write(line_el, dout(7 downto 5)); -- write the line.
-- Write the green
write(line_el, " ");
write(line_el, dout(5 downto 2)); -- write the line.
-- Write the blue
write(line_el, " ");
write(line_el, dout(2 downto 0)); -- write the line.
writeline(file_pointer, line_el); -- write the contents into the file.
end if;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: ENSEA
-- Engineer: <NAME>, <NAME>, <NAME>
--
-- Create Date: 25.02.2019 07:19:00
-- Design Name:
-- Module Name: CtrlPortail - Behavioral
-- Project Name: Portail
-- Target Devices:
-- Tool Versions:
-- Description: ce module gère le fonctionnement du portail (moteur, éclairage, normes...)
-- Il s'agit d'une bonne grosse machine à états des familles.
--
-- Dependencies:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CtrlPortail is
Port (
--Temporisations:
Attente : out STD_LOGIC; -- Attente = '1' <=> Une temporisation (30s) est en cours
Attente2s : out STD_LOGIC; -- Attente2s = '1' <=> Une temporisation (2s) est en cours
FinAttente : in STD_LOGIC; -- FinAttente = '1' <=> Fin de la temporisation (30s)
FinAttente2s : in STD_LOGIC; -- FinAttente2s = '1' <=> Fin de la temporisation (2s)
--ENTREES DIVERSES:
CLK : in STD_LOGIC; -- Horloge
FinDeCourse : in STD_LOGIC_VECTOR (1 downto 0); --Capteur de fin de course
-- FinDeCourse(1) = '1' <=> Portail Ferme ; FinDeCourse(0) = '1' <=> Portail Ouvert
ControlSignal : in STD_LOGIC; --Demande de changement d'état du portail (comme si on avait une télécommande à 1 bouton) (activé que pendant une période d'horloge)
ForceOuverture : in STD_LOGIC; --Demande d'ouverture du portail (activé que pendant une période d'horloge)
ForceFermeture : in STD_LOGIC; --Demande de fermeture du portail (activé que pendant une période d'horloge)
Stop : in STD_LOGIC; --Demande d'arrêt du portail
Collision : in STD_LOGIC; -- Collision = '1' <=> Collision détectée
--SORTIES DIVERSES:
Clignottant : out STD_LOGIC; -- ..=1 <=> Le clignottant doit clignotter (ce signal est continu et sera traité par un autre module pour permettre à la LED de clignotter)
Eclairage : out STD_LOGIC; -- ..=1 <=> Lampe puissante allumée
--Contrôle du moteur:
SensMoteur : out STD_LOGIC; -- SensMoteur = '1' <=> Ouverture
NonSensMoteur : out STD_LOGIC; -- NonSensMoteur = '0' <=> Ouverture
SignalMoteur : out STD_LOGIC -- SignalMoteur = '1' <=> Moteur en marche
);
end CtrlPortail;
architecture Behavioral of CtrlPortail is
--Liste des états: (l'utilité de chaque état est décrite dans le calcul de l'état futur)
type liste_etat is (Ferme, AttenteAvantOuverture, Ouverture, Ouvert, StopOuverture, StopFermeture, ObstacleDetecte, VerifObstacle, AttenteAvantFermeture, Fermeture);
signal ETAT_PR, ETAT_FU : liste_etat:=Ferme; --état par défaut
begin
--Actualisation de l'état présent:
process(CLK) begin
if rising_edge(CLK) then
ETAT_PR <= ETAT_FU;
end if;
end process;
--Calcul de l'état futur:
process(ETAT_PR, FinDeCourse, FinAttente, FinAttente2s, Collision, ControlSignal, ForceOuverture, ForceFermeture, Stop) begin
case ETAT_PR is
when Ferme => --Portail fermé
if ControlSignal = '1' or ForceOuverture = '1' then --Ouverture demandée
ETAT_FU <= AttenteAvantOuverture;
elsif FinDeCourse(1) = '0' then --Le portail est ouvert alors qu'il ne le dervait pas : on le ferme
ETAT_FU <= AttenteAvantFermeture;
else
ETAT_FU <= Ferme;
end if;
when AttenteAvantOuverture => --2 secondes d'attente obligatoire avant l'activation du moteur (dans le sens ouverture)
if ControlSignal = '1' or Stop = '1' then --Arrêt demandé
ETAT_FU <= StopFermeture;
elsif FinAttente2s = '1' then --On a fini d'attendre les 2 secondes
ETAT_FU <= Ouverture;
elsif FinDeCourse(0) = '1' then --Le portail est déjà ouvert, rien à faire
ETAT_FU <= Ouvert;
else
ETAT_FU <= AttenteAvantOuverture;
end if;
when Ouverture => --Portail en ouverture
if ControlSignal = '1' or Stop = '1' then --Arrêt demandé
ETAT_FU <= StopFermeture;
elsif Collision = '1' then --Obstacle détecté !!
ETAT_FU <= ObstacleDetecte;
elsif FinDeCourse(0) = '1' then --C'est bon, le portail est ouvert
ETAT_FU <= Ouvert;
elsif ForceFermeture = '1' then --Fermeture demandée
ETAT_FU <= AttenteAvantFermeture;
else
ETAT_FU <= Ouverture;
end if;
when Ouvert => --Portail ouvert
if ControlSignal = '1' or FinAttente = '1' or ForceFermeture = '1' then --On a fini d'attendre 30 secondes, ou la fermeture est demandée
ETAT_FU <= AttenteAvantFermeture;
elsif FinDeCourse(1) = '1' then --Portail fermé. Bizarre, soit.
ETAT_FU <= Ferme;
else
ETAT_FU <= Ouvert;
end if;
when StopOuverture => --Le portail est à l'arrêt, et si on clique sur le bouton principal il va s'ouvrir
if ControlSignal = '1' or ForceOuverture = '1' then --Ouverture demandée
ETAT_FU <= AttenteAvantOuverture;
elsif FinAttente = '1' or ForceFermeture = '1' then --Fermeture demandée, ou 30 secondes sont passées
ETAT_FU <= AttenteAvantFermeture;
elsif FinDeCourse(1) = '1' then
ETAT_FU <= Ferme;
else
ETAT_FU <= StopOuverture;
end if;
when StopFermeture => --Le portail est à l'arrêt, et si on clique sur le bouton principal il va se fermer
if ControlSignal = '1' or FinAttente = '1' or ForceFermeture = '1' then --Fermeture demandée, ou 30 secondes sont passées
ETAT_FU <= AttenteAvantFermeture;
elsif ForceOuverture = '1' then --Ouverture demandée
ETAT_FU <= AttenteAvantOuverture;
elsif FinDeCourse(1) = '1' then --Portail fermé.
ETAT_FU <= Ferme;
else
ETAT_FU <= StopFermeture;
end if;
when ObstacleDetecte => --Un obstacle a été detecté il y a moins de 2 secondes
if FinAttente2s = '1' then --On a fini d'attendre 2 secondes
ETAT_FU <= VerifObstacle;
elsif FinDeCourse(1) = '1' then --Portail fermé.
ETAT_FU <= Ferme;
else
ETAT_FU <= ObstacleDetecte;
end if;
when VerifObstacle => --On vérifie si l'obstacle est toujours présent
if Collision = '0' then --Plus d'obstacle, tout va bien
ETAT_FU <= AttenteAvantOuverture;
elsif FinDeCourse(1) = '1' then --Portail fermé.
ETAT_FU <= Ferme;
else --Il y a encore un obstacle, on attend encore 2 secondes supplémentaires
ETAT_FU <= ObstacleDetecte;
end if;
when AttenteAvantFermeture => --2 secondes d'attente obligatoire avant l'activation du moteur (dans le sens fermeture)
if ControlSignal = '1' or Stop = '1' then --Arrêt demandé
ETAT_FU <= StopOuverture;
elsif ForceOuverture = '1' then --Ouverture demandée
ETAT_FU <= AttenteAvantOuverture;
elsif FinAttente2s = '1' then --On a fini d'attendre 2 secondes, on peut fermer le portail
ETAT_FU <= Fermeture;
elsif FinDeCourse(1) = '1' then --Portail fermé.
ETAT_FU <= Ferme;
else
ETAT_FU <= AttenteAvantFermeture;
end if;
when Fermeture => --Portail en fermeture
if ControlSignal = '1' or Stop = '1' then --Arrêt demandé
ETAT_FU <= StopOuverture;
elsif Collision = '1' then --Obstacle détecté !!
ETAT_FU <= ObstacleDetecte;
elsif ForceOuverture = '1' then --Ouverture demandée
ETAT_FU <= AttenteAvantOuverture;
elsif FinDeCourse(1) = '1' then --Portail fermé
ETAT_FU <= Ferme;
else
ETAT_FU <= Fermeture;
end if;
when others =>
ETAT_FU <= Ferme;
end case;
end process;
--Calcul des sorties:
process(ETAT_PR) begin
case ETAT_PR is
when Ferme =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '0';
Clignottant <= '0';
Attente <= '0';
Attente2s <= '0';
when AttenteAvantOuverture =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '1';
Attente <= '0';
Attente2s <= '1';
when Ouverture =>
SignalMoteur <= '1';
SensMoteur <= '1';
NonSensMoteur <= '0';
Eclairage <= '1';
Clignottant <= '1';
Attente <= '0';
Attente2s <= '0';
when Ouvert =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '0';
Attente <= '1';
Attente2s <= '0';
when StopOuverture =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '0';
Attente <= '1';
Attente2s <= '0';
when StopFermeture =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '0';
Attente <= '1';
Attente2s <= '0';
when AttenteAvantFermeture =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '1';
Attente <= '0';
Attente2s <= '1';
when Fermeture =>
SignalMoteur <= '1';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '1';
Attente <= '0';
Attente2s <= '0';
when ObstacleDetecte =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '0';
Attente <= '0';
Attente2s <= '1';
when VerifObstacle =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '1';
Eclairage <= '1';
Clignottant <= '0';
Attente <= '0';
Attente2s <= '0';
when others =>
SignalMoteur <= '0';
SensMoteur <= '0';
NonSensMoteur <= '0';
Eclairage <= '0';
Clignottant <= '0';
Attente <= '0';
Attente2s <= '0';
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/27/2020 05:45:56 PM
-- Design Name:
-- Module Name: reset_sw - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reset_sw is
Port ( btn_in : in STD_LOGIC;
clock : in STD_LOGIC;
reset_out : out STD_LOGIC );
end reset_sw;
architecture Behavioral of reset_sw is
begin
process(clock)
begin
if rising_edge(clock) then
if btn_in = '1' then
reset_out <= '1'; -- If the reset button is pressed, hold the reset line for one input clock.
else
reset_out <= '0';
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity EntDeco is
port( entry: in std_logic_vector(1 downto 0);
display: out std_logic_vector(6 downto 0));
end;
architecture ArqDeco of EntDeco is
begin
with entry select
display <= "0000001" when "00",
"1001111" when "01",
"0010010" when "10",
"0000110" when "11",
"1111111" when others;
end ArqDeco;
|
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity cpu_with_control_tb is
end cpu_with_control_tb;
architecture TB_ARCHITECTURE of cpu_with_control_tb is
-- Component declaration of the tested unit
component cpu_with_control
port(
CLOCK : in STD_LOGIC;
RST : in STD_LOGIC;
mem_content : out STD_LOGIC_VECTOR(5 downto 0);
out0 : out STD_LOGIC_VECTOR(5 downto 0);
out1 : out STD_LOGIC_VECTOR(5 downto 0);
out2 : out STD_LOGIC_VECTOR(5 downto 0);
out3 : out STD_LOGIC_VECTOR(5 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal CLOCK : STD_LOGIC;
signal RST : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal mem_content : STD_LOGIC_VECTOR(5 downto 0);
signal out0 : STD_LOGIC_VECTOR(5 downto 0);
signal out1 : STD_LOGIC_VECTOR(5 downto 0);
signal out2 : STD_LOGIC_VECTOR(5 downto 0);
signal out3 : STD_LOGIC_VECTOR(5 downto 0);
-- Add your code here ...
constant clk_period : time := 10 ns;
begin
-- Unit Under Test port map
UUT : cpu_with_control
port map (
CLOCK => CLOCK,
RST => RST,
mem_content => mem_content,
out0 => out0,
out1 => out1,
out2 => out2,
out3 => out3
);
clk_process :process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;
rSt <= '1','0' after 6ns;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_cpu_with_control of cpu_with_control_tb is
for TB_ARCHITECTURE
for UUT : cpu_with_control
use entity work.cpu_with_control(cpu_with_control);
end for;
end for;
end TESTBENCH_FOR_cpu_with_control;
|
<filename>examples/vhdl/axi_dma/src/test/tb_axi_dma.vhd<gh_stars>10-100
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2014-2019, <NAME> <EMAIL>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library osvvm;
use osvvm.RandomPkg.all;
use work.axil_pkg.all;
use work.axi_pkg.all;
use work.axi_dma_regs_pkg.all;
entity tb_axi_dma is
generic (runner_cfg : string);
end entity;
architecture tb of tb_axi_dma is
constant clk_period : time := 1 ns;
constant axil_bus : bus_master_t := new_bus(data_length => 32,
address_length => 32,
logger => get_logger("axil_bus"));
constant memory : memory_t := new_memory;
constant axi_rd_slave : axi_slave_t := new_axi_slave(memory => memory,
logger => get_logger("axi_rd_slave"));
constant axi_wr_slave : axi_slave_t := new_axi_slave(memory => memory,
logger => get_logger("axi_wr_slave"));
signal clk : std_logic := '0';
signal axil_m2s : axil_m2s_t := axil_m2s_init;
signal axil_s2m : axil_s2m_t;
signal axi_rd_m2s : axi_rd_m2s_t;
signal axi_rd_s2m : axi_rd_s2m_t := axi_rd_s2m_init;
signal axi_wr_m2s : axi_wr_m2s_t;
signal axi_wr_s2m : axi_wr_s2m_t := axi_wr_s2m_init;
constant max_burst_length : natural := 256;
constant bytes_per_beat : natural := axi_rd_s2m.r.data'length / 8;
impure function to_reg_data(value : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(value, data_length(axil_bus)));
end;
begin
main : process
variable rnd : RandomPType;
procedure perform_transfer(rbuffer, wbuffer : buffer_t;
reg_sample_period : delay_length := 100 * clk_period) is
variable rdata : std_logic_vector(axil_s2m.r.data'range);
variable byte : natural;
begin
info("perform_transfer(num_bytes => " & to_string(num_bytes(rbuffer)) & ")");
assert num_bytes(rbuffer) = num_bytes(wbuffer) report "buffer size must be equal";
-- Provide random stimuli to read data buffer
-- Set expected data on write data buffer
for i in 0 to num_bytes(rbuffer)-1 loop
byte := rnd.RandInt(0, 255);
write_byte(memory, base_address(rbuffer) + i, byte);
set_expected_byte(memory, base_address(wbuffer) + i, byte);
end loop;
write_bus(net, axil_bus, src_address_reg_addr, to_reg_data(base_address(rbuffer)));
write_bus(net, axil_bus, dst_address_reg_addr, to_reg_data(base_address(wbuffer)));
write_bus(net, axil_bus, num_bytes_reg_addr, to_reg_data(num_bytes(rbuffer)));
write_bus(net, axil_bus, command_reg_addr, start_transfer_command);
loop
read_bus(net, axil_bus, status_reg_addr, rdata);
exit when rdata(transfer_done_status_bit) = '1';
wait for reg_sample_period;
end loop;
-- This checks that all data has been correctly written to the write
-- buffer at this point
check_expected_was_written(wbuffer);
end;
procedure perform_transfer(num_bytes : natural;
reg_sample_period : delay_length := 100 * clk_period) is
variable rbuffer, wbuffer : buffer_t;
begin
rbuffer := allocate(memory,
num_bytes => num_bytes,
name => rbuffer'simple_name,
permissions => read_only,
alignment => 4096);
wbuffer := allocate(memory,
num_bytes => num_bytes,
name => wbuffer'simple_name,
permissions => write_only,
alignment => 4096);
perform_transfer(rbuffer, wbuffer, reg_sample_period);
end;
variable stat : axi_statistics_t;
variable unnused_buffer, rbuffer, wbuffer : buffer_t;
begin
test_runner_setup(runner, runner_cfg);
rnd.InitSeed(rnd'instance_name);
show(display_handler, debug);
if run("Perform simple transfers") then
-- Perform transfer that are a multiple of the max_burst_length and
-- do not cross 4k boundaries
perform_transfer(num_bytes => max_burst_length * bytes_per_beat);
perform_transfer(num_bytes => 10 * max_burst_length * bytes_per_beat);
elsif run("Perform split transfers") then
-- Perform transfers where the max_burst_length cannot be used for the
-- entire transfer
perform_transfer(num_bytes => bytes_per_beat);
get_statistics(net, axi_rd_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, 1), 1);
check_equal(num_bursts(stat), 1);
get_statistics(net, axi_wr_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, 1), 1);
check_equal(num_bursts(stat), 1);
clear(memory);
perform_transfer(num_bytes => (max_burst_length - 1) * bytes_per_beat);
get_statistics(net, axi_rd_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, max_burst_length - 1), 1);
check_equal(num_bursts(stat), 1);
get_statistics(net, axi_wr_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, max_burst_length - 1), 1);
check_equal(num_bursts(stat), 1);
clear(memory);
perform_transfer(num_bytes => (max_burst_length + 1) * bytes_per_beat);
get_statistics(net, axi_rd_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, max_burst_length), 1);
check_equal(get_num_burst_with_length(stat, 1), 1);
check_equal(num_bursts(stat), 2);
get_statistics(net, axi_wr_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, max_burst_length), 1);
check_equal(get_num_burst_with_length(stat, 1), 1);
check_equal(num_bursts(stat), 2);
clear(memory);
perform_transfer(num_bytes => (2*max_burst_length - 1) * bytes_per_beat);
get_statistics(net, axi_rd_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, max_burst_length), 1);
check_equal(get_num_burst_with_length(stat, max_burst_length - 1), 1);
check_equal(num_bursts(stat), 2);
get_statistics(net, axi_wr_slave, stat, clear => true);
check_equal(get_num_burst_with_length(stat, max_burst_length), 1);
check_equal(get_num_burst_with_length(stat, max_burst_length - 1), 1);
check_equal(num_bursts(stat), 2);
elsif run("Check transfer done comes after write response") then
-- Set a very large response latency to ensure that the
-- dut does not signal transfer_done until the write reponse has been received
set_response_latency(net, axi_wr_slave, 100 * clk_period);
perform_transfer(num_bytes => max_burst_length * bytes_per_beat,
reg_sample_period => 10 * clk_period);
elsif run("Check read burst is split on 4KByte boundary") then
for i in 1 to 5 loop
clear(memory);
unnused_buffer := allocate(memory, num_bytes => 4096 - i * bytes_per_beat);
rbuffer := allocate(memory,
num_bytes => 1024,
name => rbuffer'simple_name,
permissions => read_only);
info("base_address(rbuffer) = " & to_string(base_address(rbuffer)));
check_equal(base_address(rbuffer), 4096 - i * bytes_per_beat);
wbuffer := allocate(memory,
num_bytes => 1024,
name => wbuffer'simple_name,
permissions => write_only,
alignment => 4096);
perform_transfer(rbuffer, wbuffer);
end loop;
elsif run("Check write burst is split on 4KByte boundary") then
for i in 1 to 5 loop
clear(memory);
unnused_buffer := allocate(memory, num_bytes => 4096 - i * bytes_per_beat);
wbuffer := allocate(memory,
num_bytes => 1024,
name => wbuffer'simple_name,
permissions => write_only);
info("base_address(wbuffer) = " & to_string(base_address(wbuffer)));
check_equal(base_address(wbuffer), 4096 - i * bytes_per_beat);
rbuffer := allocate(memory,
num_bytes => 1024,
name => rbuffer'simple_name,
permissions => read_only,
alignment => 4096);
perform_transfer(rbuffer, wbuffer);
end loop;
elsif run("Slow data read") then
set_address_fifo_depth(net, axi_rd_slave, 16);
set_address_stall_probability(net, axi_rd_slave, 0.99);
set_data_stall_probability(net, axi_rd_slave, 0.95);
for i in 0 to 15 loop
perform_transfer(num_bytes => rnd.RandInt(1, 3 * max_burst_length) * bytes_per_beat);
end loop;
elsif run("Slow data write") then
set_address_fifo_depth(net, axi_wr_slave, 16);
set_address_stall_probability(net, axi_wr_slave, 0.99);
set_data_stall_probability(net, axi_wr_slave, 0.95);
for i in 0 to 15 loop
perform_transfer(num_bytes => rnd.RandInt(1, 3 * max_burst_length) * bytes_per_beat);
end loop;
elsif run("Random AXI configuration") then
for idx in 0 to 15 loop
set_address_fifo_depth(net, axi_wr_slave, rnd.RandInt(1, 16));
set_address_stall_probability(net, axi_wr_slave, rnd.Uniform(0.0, 0.99));
set_data_stall_probability(net, axi_wr_slave, rnd.Uniform(0.0, 0.95));
set_write_response_fifo_depth(net, axi_wr_slave, rnd.RandInt(1, 16));
set_write_response_stall_probability(net, axi_wr_slave, rnd.Uniform(0.0, 0.99));
set_response_latency(net, axi_wr_slave, rnd.Uniform(1.0, 100.0) * 1 ns);
set_address_fifo_depth(net, axi_rd_slave, rnd.RandInt(1, 16));
set_address_stall_probability(net, axi_rd_slave, rnd.Uniform(0.0, 0.99));
set_data_stall_probability(net, axi_rd_slave, rnd.Uniform(0.0, 0.95));
set_response_latency(net, axi_rd_slave, rnd.Uniform(1.0, 100.0) * 1 ns);
for i in 0 to 3 loop
clear(memory);
perform_transfer(num_bytes => rnd.RandInt(1, 3 * max_burst_length) * bytes_per_beat);
end loop;
end loop;
end if;
test_runner_cleanup(runner);
end process;
test_runner_watchdog(runner, 10 ms);
dut: entity work.axi_dma
generic map (
max_burst_length => max_burst_length
)
port map (
clk => clk,
axils_m2s => axil_m2s,
axils_s2m => axil_s2m,
axi_rd_m2s => axi_rd_m2s,
axi_rd_s2m => axi_rd_s2m,
axi_wr_m2s => axi_wr_m2s,
axi_wr_s2m => axi_wr_s2m);
clk <= not clk after clk_period/2;
axi_lite_master_inst: entity vunit_lib.axi_lite_master
generic map (
bus_handle => axil_bus)
port map (
aclk => clk,
arready => axil_s2m.ar.ready,
arvalid => axil_m2s.ar.valid,
araddr => axil_m2s.ar.addr,
rready => axil_m2s.r.ready,
rvalid => axil_s2m.r.valid,
rdata => axil_s2m.r.data,
rresp => axil_s2m.r.resp,
awready => axil_s2m.aw.ready,
awvalid => axil_m2s.aw.valid,
awaddr => axil_m2s.aw.addr,
wready => axil_s2m.w.ready,
wvalid => axil_m2s.w.valid,
wdata => axil_m2s.w.data,
wstrb => axil_m2s.w.strb,
bvalid => axil_s2m.b.valid,
bready => axil_m2s.b.ready,
bresp => axil_s2m.b.resp);
axi_read_slave_inst: entity vunit_lib.axi_read_slave
generic map (
axi_slave => axi_rd_slave)
port map (
aclk => clk,
arvalid => axi_rd_m2s.ar.valid,
arready => axi_rd_s2m.ar.ready,
arid => axi_rd_m2s.ar.id,
araddr => axi_rd_m2s.ar.addr,
arlen => axi_rd_m2s.ar.len,
arsize => axi_rd_m2s.ar.size,
arburst => axi_rd_m2s.ar.burst,
rvalid => axi_rd_s2m.r.valid,
rready => axi_rd_m2s.r.ready,
rid => axi_rd_s2m.r.id,
rdata => axi_rd_s2m.r.data,
rresp => axi_rd_s2m.r.resp,
rlast => axi_rd_s2m.r.last);
axi_write_slave_inst: entity vunit_lib.axi_write_slave
generic map (
axi_slave => axi_wr_slave)
port map (
aclk => clk,
awvalid => axi_wr_m2s.aw.valid,
awready => axi_wr_s2m.aw.ready,
awid => axi_wr_m2s.aw.id,
awaddr => axi_wr_m2s.aw.addr,
awlen => axi_wr_m2s.aw.len,
awsize => axi_wr_m2s.aw.size,
awburst => axi_wr_m2s.aw.burst,
wvalid => axi_wr_m2s.w.valid,
wready => axi_wr_s2m.w.ready,
wdata => axi_wr_m2s.w.data,
wstrb => axi_wr_m2s.w.strb,
wlast => axi_wr_m2s.w.last,
bvalid => axi_wr_s2m.b.valid,
bready => axi_wr_m2s.b.ready,
bid => axi_wr_s2m.b.id,
bresp => axi_wr_s2m.b.resp);
end architecture;
|
<reponame>veeYceeY/SCiV
----------------------------------------------------------------------------------
-- Company: SCiMOS
-- Engineer: veeYceeY
--
-- Create Date: 24.05.2020 12:49:36
-- Design Name:
-- Module Name: sciv_core - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--RIsc V instruction decoder with microcode memory
--Must be changed to hard coded decoder after debugging
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decode_uc is
port (
i_clk : in std_logic;
i_rst : in std_logic;
i_stall : in std_logic;
i_flush : in std_logic;
i_instr_valid : in std_logic;
i_instr : in std_logic_vector(31 downto 0);
i_pc : in std_logic_vector(31 downto 0);
o_uc_addr : out std_logic_vector(7 downto 0);
i_data : in std_logic_vector(31 downto 0);
--i_stall : in std_logic;
--i_br_en : in std_logic;
--i_br_addr : in std_logic_vector(31 downto 0);
o_src1_addr : out std_logic_vector(4 downto 0);
o_src2_addr : out std_logic_vector(4 downto 0);
i_src1 : in std_logic_vector(31 downto 0);
i_src2 : in std_logic_vector(31 downto 0);
o_rs1 : out std_logic_vector(31 downto 0);
o_rs2 : out std_logic_vector(31 downto 0);
o_imm : out std_logic_vector(31 downto 0);
o_pc : out std_logic_vector(31 downto 0);
o_instr_valid :out std_logic;
o_rs1_fwsel : out std_logic_vector(1 downto 0);
o_rs2_fwsel : out std_logic_vector(1 downto 0);
o_mem_fwsel : out std_logic;
o_cmp_op1sel : out std_logic;
o_op1_sel : out std_logic_vector(1 downto 0);
o_op2_sel : out std_logic_vector(1 downto 0);
o_br_en : out std_logic;
o_br_type : out std_logic_vector(2 downto 0);
--o_br_addr_sel : out std_logic;
o_alu_opsel : out std_logic_vector(3 downto 0);
o_op_sign : out std_logic;
o_exe_res_sel : out std_logic_vector(1 downto 0);
o_mem_store_type : out std_logic_vector(1 downto 0);
o_mem_load_type: out std_logic_vector(2 downto 0);
o_wb_en : out std_logic;
o_wb_reg : out std_logic_vector(4 downto 0);
o_wb_data_sel: out std_logic;
o_mem_en : out std_logic;
o_mem_we : out std_logic;
--o_mem_addr : out std_logic_vector(31 downto 0);
o_mem_data : out std_logic_vector(31 downto 0);
o_stall: out std_logic;
o_except_ill_instr : out std_logic;
o_csr_sel : out std_logic;
o_csr_rd : out std_logic;
o_csr_we : out std_logic;
--o_csr_wr_data : out std_logic_vector(31 downto 0);
o_csr_wr_addr : out std_logic_vector(11 downto 0);
o_csr_rd_addr : out std_logic_vector(11 downto 0);
o_csr_op : out std_logic_vector(1 downto 0)
--i_csr_data : in std_logic_vector(31 downto 0)
);
end entity;
architecture behave of decode_uc is
signal instr : std_logic_vector(31 downto 0);
signal imm : std_logic_vector(31 downto 0);
signal funct : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(6 downto 0);
signal funct3 : std_logic_vector(2 downto 0);
signal funct7 : std_logic_vector(6 downto 0);
signal rs1 : std_logic_vector(4 downto 0);
signal rs2 : std_logic_vector(4 downto 0);
signal imms_u : std_logic_vector(31 downto 0);
signal imms_i : std_logic_vector(31 downto 0);
signal imms_j : std_logic_vector(31 downto 0);
signal imms_b : std_logic_vector(31 downto 0);
signal imms_s : std_logic_vector(31 downto 0);
signal imm_u : std_logic_vector(31 downto 0);
signal imm_i : std_logic_vector(31 downto 0);
signal imm_j : std_logic_vector(31 downto 0);
signal imm_b : std_logic_vector(31 downto 0);
signal imm_s : std_logic_vector(31 downto 0);
signal imm_r : std_logic_vector(31 downto 0);
signal immu_u : std_logic_vector(31 downto 0);
signal immu_i : std_logic_vector(31 downto 0);
signal immu_j : std_logic_vector(31 downto 0);
signal immu_b : std_logic_vector(31 downto 0);
signal immu_s : std_logic_vector(31 downto 0);
signal rd : std_logic_vector(4 downto 0);
signal uc_addr : std_logic_vector(7 downto 0);
signal uc : std_logic_vector(31 downto 0);
signal store_type : std_logic_vector(1 downto 0);
signal wb_we : std_logic;
signal wb_data_sel : std_logic;
signal mem_en : std_logic;
signal mem_we : std_logic;
signal mem_load_type : std_logic_vector(2 downto 0);
signal br_en : std_logic;
signal br_type : std_logic_vector(2 downto 0);
signal cmp_op1sel : std_logic;
signal exe_res_sel : std_logic_vector(1 downto 0);
signal alu_op_sel : std_logic_vector(3 downto 0);
signal op2_sel : std_logic_vector(1 downto 0);
signal op1_sel : std_logic_vector(1 downto 0);
signal imm_sel : std_logic_vector(2 downto 0);
signal op_sign : std_logic;
type bu00_type is array(2 downto 0) of std_logic_vector(4 downto 0);
type src_bu_type is array(1 downto 0) of std_logic_vector(4 downto 0);
signal fw_bu00 : bu00_type;
signal src_bu : src_bu_type;
signal wb_we_buff : std_logic_vector(2 downto 0);
signal wb_wr_buff : std_logic_vector(2 downto 0);
signal wb_rd_buff : std_logic_vector(2 downto 0);
signal mem_fwsel: std_logic;
signal rs1_fwsel : std_logic_vector(1 downto 0);
signal rs2_fwsel: std_logic_vector(1 downto 0);
signal fw_mm: std_logic;
signal bubble_end: std_logic;
signal bubble: std_logic;
signal mem_wr: std_logic;
signal stall: std_logic;
signal stall_d: std_logic;
signal bubble_count: std_logic_vector(3 downto 0);
signal csr_sel : std_logic;
signal csr_we : std_logic;
signal csr_data : std_logic_vector(31 downto 0);
signal csr_address : std_logic_vector(11 downto 0);
signal csr_d_type : std_logic;
signal csr_rd : std_logic;
signal csr_op : std_logic_vector(1 downto 0);
signal rs1_csr : std_logic_vector(31 downto 0);
signal rs1_csr_t : std_logic_vector(31 downto 0);
signal except_ill_instr : std_logic;
signal stall_d1 : std_logic;
begin
instr<= i_instr when i_flush='0' else x"00000033";
opcode <= instr(6 downto 0);
rd <= instr(11 downto 7);
funct3 <= instr(14 downto 12);
rs1 <= instr(19 downto 15);
rs2 <= instr(24 downto 20);
funct7 <= instr(31 downto 25);
imms_i <= x"00000" & instr(31 downto 20) when instr(31) = '0' else
x"fffff" & instr(31 downto 20);
imms_s <= x"00000" & instr(31 downto 25) & instr(11 downto 7) when instr(31) = '0' else
x"fffff" & instr(31 downto 25) & instr(11 downto 7);
imms_u <= instr(31 downto 12) & x"000";
imms_b <= "000" & x"0000" & instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8) & '0' when instr(31) = '0' else
"111" & x"ffff" & instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8) & '0';
imms_j <= "000" & x"00" & instr(31 ) & instr(19 downto 12) & instr(20) & instr( 30 downto 21) & '0' when instr(31) = '0' else
"111" & x"ff" & instr(31 ) & instr(19 downto 12) & instr(20) & instr( 30 downto 21) & '0';
immu_i <= x"00000" & instr(31 downto 20);
immu_s <= x"00000" & instr(31 downto 25) & instr(11 downto 7) ;
immu_u <= x"000" & instr(31 downto 12);
immu_b <= "000" & x"0000" & instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8) & '0';
immu_j <= "000" & x"00" & instr(31) & instr(19 downto 12) & instr(20) & instr( 30 downto 21) & '0';
imm_r <= x"000000" & "000" & rs2;
csr_address<=x"341" when uc_addr = x"30" else instr(31 downto 20) ;
o_uc_addr <= uc_addr;--
--uc <= i_data;
store_type <=uc(1 downto 0);
wb_we <=uc(2);
wb_data_sel <=uc(3);
mem_en <=uc(4);
mem_we <=uc(5);
mem_load_type <=uc(8 downto 6);
br_en <=uc(9);
br_type <=uc(12 downto 10);
cmp_op1sel <=uc(13);
exe_res_sel <=uc(15 downto 14);
alu_op_sel <=uc(19 downto 16);
op2_sel <=uc(21 downto 20);
op1_sel <=uc(23 downto 22);
imm_sel <=uc(26 downto 24);
op_sign <=uc(27);
csr_op <= uc(29 downto 28);
csr_d_type <= uc(30);
csr_sel <= uc(31);
rs1_csr<= csr_data when csr_sel = '1' else i_src1;
--rs1_csr<=rs1_csr_t when rising_edge(i_clk);
--10001110111000000001001000000000
csr_we <= '1' when csr_sel = '1' and ((csr_op = "01" and rs1 /="00000") or csr_op(1) = '1') else '0';
csr_rd <= '1' when csr_sel = '1' and ((csr_op(1) = '1' and rd /="00000")or csr_op = "01"or csr_op = "00") else '0';
--csr_wb_en <= csr_en;
csr_data <= i_src1 when csr_d_type = '0' else x"000000"&"000"&rs1;
--o_csr_sel <=csr_sel;
--o_csr_rd <=csr_rd ;
--o_csr_we <=csr_we ;
--o_csr_data <=csr_data ;
--o_csr_op <=csr_op ;
--o_csr_rd_addr<= csr_address; -- after 1 ns;
--o_csr_wr_addr<= csr_address; -- after 1 ns;
process(i_clk,i_rst)
begin
if i_rst = '1' then
o_csr_sel <='0' ;
o_csr_rd <='0' ;
o_csr_we <='0' ;
--o_csr_wr_data <=(others => '0') ;
o_csr_wr_addr <=(others => '0') ;
o_csr_rd_addr <=(others => '0') ;
o_csr_op <=(others => '0') ;
o_except_ill_instr <='0' ;
elsif rising_edge(i_clk) then
if i_stall='0' then
o_except_ill_instr<=except_ill_instr;
o_csr_sel <=csr_sel ;
o_csr_rd <=csr_rd ;
o_csr_we <=csr_we ;
o_csr_wr_addr <=csr_address ;
o_csr_rd_addr <=csr_address ;
o_csr_op <=csr_op ;
end if;
end if;
end process;
imm_u <= imms_u when op_sign = '1' else immu_u;
imm_i <= imms_i when op_sign = '1' else immu_i;
imm_j <= imms_j when op_sign = '1' else immu_j;
imm_b <= imms_b when op_sign = '1' else immu_b;
imm_s <= imms_s when op_sign = '1' else immu_s;
imm <= imm_u when imm_sel = x"0" else
imm_i when imm_sel = x"1" else
imm_j when imm_sel = x"2" else
imm_b when imm_sel = x"3" else
imm_r when imm_sel = x"4" else
imm_s when imm_sel = x"5" else
x"00000000" when imm_sel = x"6" else
x"00000000" ;
-----------------------data forwardingc exec---------------
process(i_clk,i_rst)
begin
if i_rst ='1' then
fw_bu00(0) <= (others => '0');
fw_bu00(1) <= (others => '0');
fw_bu00(2) <= (others => '0');
wb_we_buff <= (others=> '0');
elsif rising_edge(i_clk) then
if i_stall = '0' then
if i_flush = '1' then
fw_bu00(0) <= (others => '0');
fw_bu00(1) <= (others => '0');
fw_bu00(2) <= (others => '0');
wb_we_buff <= (others=> '0');
wb_wr_buff <= (others=> '0');
else
fw_bu00(0) <= rd ;
if mem_en = '1' and mem_we='1' then
fw_bu00(1) <= "00000";
else
fw_bu00(1) <= fw_bu00(0);
end if;
fw_bu00(2) <= fw_bu00(1);
wb_we_buff(0) <= wb_we;
wb_we_buff(1) <= wb_we_buff(0);
wb_we_buff(2) <= wb_we_buff(1);
wb_wr_buff(0) <= mem_en and (mem_we);
wb_wr_buff(1) <= wb_wr_buff(0);
wb_wr_buff(2) <= wb_wr_buff(1);
wb_rd_buff(0) <= mem_en and (not mem_we);
wb_rd_buff(1) <= wb_rd_buff(0);
wb_rd_buff(2) <= wb_rd_buff(1);
end if;
end if;
end if;
end process;
mem_fwsel<= '1' when mem_en ='1' and rs2 = fw_bu00(0) and wb_we_buff(0) ='1' and rs2 /=x"00000000" else '0';
--wb_fwsel<= '1' when (mem_en and (not mem_we))='1' and rs2 = fw_bu00(0) and wb_rd_buff(1) = '1' and wb_we_buff(0) ='1' and rs2 /=x"00000000" else '0';
--process(i_clk,i_rst)
--begin
--if i_rst ='1' then
-- src_bu(0) <= (others => '0');
-- src_bu(1) <= (others => '0');
--elsif rising_edge(i_clk) then
-- if i_stall = '0' then
-- src_bu(0) <= rd;
-- src_bu(1) <= src_bu(0);
-- src_bu(2) <= src_bu(1);
-- end if;
--end if;
--end process;
stall_d1<= i_stall when rising_edge(i_clk);
rs1_fwsel <= "01" when fw_bu00(0) = rs1 and wb_we_buff(0) ='1' and rs1 /=x"00000000" else --and stall_d1 ='0' else
--"10" when fw_bu00(0) = rs1 and wb_we_buff(0) ='1' and rs1 /=x"00000000" and stall_d1 ='1' else
"10" when fw_bu00(1) = rs1 and wb_we_buff(1) ='1'and rs1 /=x"00000000" else
"11" when fw_bu00(2) = rs1 and wb_we_buff(2) ='1'and rs1 /=x"00000000" else
"00";
rs2_fwsel <= "01" when fw_bu00(0) = rs2 and wb_we_buff(0) ='1'and rs2 /=x"00000000" else --and stall_d1 ='0' else
--"10" when fw_bu00(0) = rs2 and wb_we_buff(0) ='1'and rs2 /=x"00000000" and stall_d1 ='1' else
"10" when fw_bu00(1) = rs2 and wb_we_buff(1) ='1'and rs2 /=x"00000000" else
"11" when fw_bu00(2) = rs2 and wb_we_buff(2) ='1'and rs2 /=x"00000000" else
"00";
--mem_fwsel <= "01" when fw_bu00(0)(5 downto 1) = rs2 and fw_bu00(0)(0) ='1'else
-- "10" when fw_bu00(1)(5 downto 1) = rs2 and fw_bu00(1)(0) ='1'else
-- "11" when fw_bu00(2)(5 downto 1) = rs2 and fw_bu00(2)(0) ='1'else
-- "00";
mem_wr<='1' when mem_en='1' else '0'; --and mem_we='0'else '0';
--stall<='0';
o_stall<='0';
-----------------------data forwardingc memaccess---------------
--process(i_clk,i_rst)
--begin
--if i_rst ='1' then
-- fw_bu00(0) <= (others => '0');
-- fw_bu00(1) <= (others => '0');
-- fw_bu00(2) <= (others => '0');
--elsif rising_edge(i_clk) then
-- if i_stall = '0' then
-- fw_bu00(0) <= rd & wb_we;
-- fw_bu00(1) <= fw_bu00(0);
-- fw_bu00(2) <= fw_bu00(1);
-- end if;
--end if;
--end process;
-- rs1_fwsel <= "01" when fw_bu00(0)(5 downto 1) = rs1 else --and fw_bu00(0)(0) ='1'else
-- "10" when fw_bu00(1)(5 downto 1) = rs1 else --and fw_bu00(1)(0) ='1'else
-- "11" when fw_bu00(2)(5 downto 1) = rs1 else --and fw_bu00(2)(0) ='1'else
-- "00";
-- rs2_fwsel <= "01" when fw_bu00(0)(5 downto 1) = rs2 else --and fw_bu00(0)(0) ='1'else
-- "10" when fw_bu00(1)(5 downto 1) = rs2 else --and fw_bu00(1)(0) ='1'else
-- "11" when fw_bu00(2)(5 downto 1) = rs2 else --and fw_bu00(2)(0) ='1'else
--rs1_fwsel <= "01" when fw_bu00(0)(5 downto 1) = rs1 and op1_sel = 0 and fw_bu00(0)(0) ='1'else
-- "10" when fw_bu00(1)(5 downto 1) = rs1 and op1_sel = 0 and fw_bu00(1)(0) ='1'else
-- "11" when fw_bu00(2)(5 downto 1) = rs1 and op1_sel = 0 and fw_bu00(2)(0) ='1'else
-- "00";
--rs2_fwsel <= "01" when fw_bu00(0)(5 downto 1) = rs2 and (op2_sel = 0 or cmp_op1sel = '0') and fw_bu00(0)(0) ='1'else
-- "10" when fw_bu00(1)(5 downto 1) = rs2 and (op2_sel = 0 or cmp_op1sel = '0') and fw_bu00(1)(0) ='1'else
-- "11" when fw_bu00(2)(5 downto 1) = rs2 and (op2_sel = 0 or cmp_op1sel = '0') and fw_bu00(2)(0) ='1'else
-- "00";
--fw_mm <= '1' when fw_bu00(1)(19 downto 15) = fw_bu00(0)(1 downto 15) and op2_sel = 0 and fw_bu00(0)(0) ='1'else
-- '0';
------------------------------------------------------
process(opcode,funct3,funct7)
begin
if opcode = "0110111" then
uc_addr <= x"01";
uc <= "00001000111000000000000000000100";
elsif opcode = "0010111" then
uc_addr <= x"02";
uc <= "00001000101000000000000000000100";
elsif opcode = "1101111" then
uc_addr <= x"03";
uc <= "00001010101000000101001000000100";
elsif opcode = "1100111" then
uc_addr <= x"04";
uc <= "00001001001000000101001000000100";
elsif opcode = "1100011" then
if funct3 = "000" then
uc_addr <= x"05";
uc <= "00001011101000000000001000000000";
elsif funct3 = "001" then
uc_addr <= x"06";
uc <= "00001011101000000000011000000000";
elsif funct3 = "100" then
uc_addr <= x"07";
uc <= "00001011101000000000101000000000";
elsif funct3 = "101" then
uc_addr <= x"08";
uc <= "00001011101000000000111000000000";
elsif funct3 = "110" then
uc_addr <= x"09";
uc <= "00000011101000000000101000000000";
elsif funct3 = "111" then
uc_addr <= x"0a";
uc <= "00000011101000000000111000000000";
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
elsif opcode = "0000011" then
if funct3 = "000" then
uc_addr <= x"0b";
uc <= "00001001001000000000000000011100";
elsif funct3 = "001" then
uc_addr <= x"0c";
uc <= "00001001001000000000000001011100";
elsif funct3 = "010" then
uc_addr <= x"0d";
uc <= "00001001001000000000000010011100";
elsif funct3 = "100" then
uc_addr <= x"0e";
uc <= "00000001001000000000000011011100";
elsif funct3 = "101" then
uc_addr <= x"0f";
uc <= "00000001001000000000000100011100";
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
elsif opcode = "0100011" then
if funct3 = "000" then
uc_addr <= x"10";
uc <= "00001101001000000000000000110000";
elsif funct3 = "001" then
uc_addr <= x"11";
uc <= "00001101001000000000000000110001";
elsif funct3 = "010" then
uc_addr <= x"12";
uc <= "00001101001000000000000000110010";
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
elsif opcode = "0010011" then
if funct3 = "000" then
uc_addr <= x"13";
uc <= "00001001001000000000000000000100";
elsif funct3 = "001" then
uc_addr <= x"19";
uc <= "00001100001001010000000000000100";
elsif funct3 = "010" then
uc_addr <= x"14";
uc <= "00001001001000011010000000000100";
elsif funct3 = "011" then
uc_addr <= x"15";
uc <= "00000001001000011010000000000100";
elsif funct3 = "100" then
uc_addr <= x"16";
uc <= "00001001001000100000000000000100";
elsif funct3 = x"110" then
uc_addr <= x"17";
uc <= "00001001001000110000000000000100";
elsif funct3 = "111" then
uc_addr <= x"18";
uc <= "00001001001000110000000000000100";
elsif funct3 = "101" then
if funct7(5) = '0' then
uc_addr <= x"1b";
uc <= "00001100001001110000000000000100";
else
uc_addr <= x"1a";
uc <= "00001100001001100000000000000100";
end if;
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
elsif opcode = "0110011" then
if funct3 = "000" then
if funct7(5) = '0' then
uc_addr <= x"1c";
uc <= "00001000000000000000000000000100";
else
uc_addr <= x"1d";
uc <= "00001000000000010000000000000100";
end if;
elsif funct3 = "001" then
uc_addr <= x"1e";
uc <= "00001000000001010000000000000100";
elsif funct3 = "010" then
uc_addr <= x"1f";
uc <= "00001000000000001000000000000100";
elsif funct3 = "011" then
uc_addr <= x"20";
uc <= "00000000000000001000000000000100";
elsif funct3 = "100" then
uc_addr <= x"21";
uc <= "00001000000000100000000000000100";
elsif funct3 = "101" then
if funct7(5) = '0' then
uc_addr <= x"22";
uc <= "00001000000001100000000000000100";
else
uc_addr <= x"23";
uc <= "00001000000001110000000000000100";
end if;
elsif funct3 = "110" then
uc_addr <= x"24";
uc <= "00001000000001000000000000000100";
elsif funct3 = "111" then
uc_addr <= x"25";
uc <= "00001000000000110000000000000100";
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
elsif opcode = "0001111" then
if funct3 = "000" then
uc_addr <= x"26";
uc <= "00001000101000000000000000000000";
elsif funct3 = "001" then
uc_addr <= x"27";
uc <= "00001000101000000000000000000000";
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
elsif opcode = "1110011" then
if funct3 = "000" then
if immu_i = x"00000000" then
uc_addr <= x"28";
uc <= "00001000101000000000000000000000";
elsif immu_i = x"00000001" then
uc_addr <= x"29";
uc <= "00001000101000000000000000000000";
elsif immu_i = x"00000302" then
uc_addr <= x"30";
uc <= "10001110111000000001001000000000";
end if;
elsif funct3 = "001" then
uc <= "10011110111000000000000000000100";
uc_addr <= x"2a";
elsif funct3 = "010" then
uc <= "10101110111000000000000000000100";
uc_addr <= x"2b";
elsif funct3 = "011" then
uc <= "10111110111000000000000000000100";
uc_addr <= x"2c";
elsif funct3 = "101" then
uc <= "11011110111000000000000000000100";
uc_addr <= x"2d";
elsif funct3 = "110" then
uc <= "11101110111000000000000000000100";
uc_addr <= x"2e";
elsif funct3 = "111" then
uc <= "11111110111000000000000000000100";
uc_addr <= x"2f";
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
else
uc_addr <= x"00";
uc <= "00000000000000000000000000000000";
end if;
end process;
except_ill_instr<='1' when uc_addr <= x"00" and i_rst='0' else '0';
--00001000111000000000000000000100
--10010000000000000000000000000100
--10100000000000000000000000000100
--10110000000000000000000000000100
--11010000000000000000000000000100
--11100000000000000000000000000100
--11110000000000000000000000000100
--o_rs1 <= (others =>'0') when i_rst = '1' else i_src1 when rising_edge(i_clk);
--o_rs2 <= (others =>'0') when i_rst = '1' else i_src2 when rising_edge(i_clk);
--o_imm <= (others =>'0') when i_rst = '1' else imm when rising_edge(i_clk);
--o_pc <= (others =>'0') when i_rst = '1' else i_pc when rising_edge(i_clk);
--o_op1_sel <= (others =>'0') when i_rst = '1' else op1_sel when rising_edge(i_clk);
--o_op2_sel <= (others =>'0') when i_rst = '1' else op2_sel when rising_edge(i_clk);
--o_br_en <= '0' when i_rst = '1' else br_en when rising_edge(i_clk);
--o_br_type <= (others =>'0') when i_rst = '1' else br_type when rising_edge(i_clk);
--o_cmp_op1sel <= '0' when i_rst = '1' else cmp_op1sel when rising_edge(i_clk);
--o_alu_opsel <= (others =>'0') when i_rst = '1' else alu_op_sel when rising_edge(i_clk);
--o_exe_res_sel <= (others =>'0') when i_rst = '1' else exe_res_sel when rising_edge(i_clk);
--o_mem_store_type<= (others =>'0') when i_rst = '1' else store_type when rising_edge(i_clk);
--o_mem_load_type <= (others =>'0') when i_rst = '1' else mem_load_type when rising_edge(i_clk);
--o_wb_en <= '0' when i_rst = '1' else wb_we when rising_edge(i_clk);
--o_wb_reg <= (others =>'0') when i_rst = '1' else rd when rising_edge(i_clk);
--o_wb_data_sel <= '0' when i_rst = '1' else wb_data_sel when rising_edge(i_clk);
--o_mem_en <= '0' when i_rst = '1' else mem_en when rising_edge(i_clk);
--o_mem_we <= '0' when i_rst = '1' else mem_we when rising_edge(i_clk);
--o_mem_data <= (others =>'0') when i_rst = '1' else i_src2 when rising_edge(i_clk);
--o_op_sign <= '0' when i_rst = '1' else op_sign when rising_edge(i_clk);
--o_rs1_fwsel <= (others => '0') when i_rst='1' else rs1_fwsel when rising_edge(i_clk);
--o_rs2_fwsel <= (others => '0') when i_rst='1' else rs2_fwsel when rising_edge(i_clk);
process(i_clk,i_rst)
begin
if i_rst = '1' then
--o_rs1 <= (others =>'0') ;
--o_rs2 <= (others =>'0') ;
o_imm <= (others =>'0') ;
o_pc <= (others =>'0') ;
o_op1_sel <= (others =>'0') ;
o_op2_sel <= (others =>'0') ;
o_br_en <= '0' ;
o_br_type <= (others =>'0') ;
o_cmp_op1sel <= '0' ;
o_alu_opsel <= (others =>'0') ;
o_exe_res_sel <= (others =>'0') ;
o_mem_store_type<= (others =>'0') ;
o_mem_load_type <= (others =>'0') ;
o_wb_en <= '0' ;
o_wb_reg <= (others =>'0') ;
o_wb_data_sel <= '0' ;
o_mem_en <= '0' ;
o_mem_we <= '0' ;
--o_mem_data <= (others =>'0') ;
o_op_sign <= '0' ;
o_rs1_fwsel <= (others => '0') ;
o_rs2_fwsel <= (others => '0') ;
o_src1_addr <= (others => '0') ;
o_src2_addr <= (others => '0') ;
o_instr_valid <= '0' ;
elsif rising_edge(i_clk) then
if i_stall = '0' then
o_imm <= imm ;
o_pc <= i_pc ;
o_op1_sel <= op1_sel ;
o_op2_sel <= op2_sel ;
o_br_en <= br_en ;
o_br_type <= br_type ;
o_cmp_op1sel <= cmp_op1sel ;
o_alu_opsel <= alu_op_sel ;
o_exe_res_sel <= exe_res_sel ;
o_mem_store_type<= store_type ;
o_mem_load_type <= mem_load_type ;
o_wb_en <= wb_we ;
o_wb_reg <= rd ;
o_wb_data_sel <= wb_data_sel ;
o_mem_en <= mem_en ;
o_mem_we <= mem_we ;
o_op_sign <= op_sign ;
o_rs1_fwsel <= rs1_fwsel ;
o_rs2_fwsel <= rs2_fwsel ;
o_mem_fwsel <= mem_fwsel ;
o_src1_addr <= rs1;
o_src2_addr <= rs2;
o_instr_valid <= i_instr_valid;
end if;
end if;
end process;
o_rs1 <= rs1_csr ;
o_rs2 <= i_src2 ;
o_mem_data <= i_src2 ;
end behave;
|
entity inline_01 is
end entity inline_01;
architecture test of inline_01 is
component computer_system is
port ( other_port : in bit := '0' );
end component computer_system;
begin
system_under_test : component computer_system
port map ( other_port => open );
end architecture test;
configuration inline_01_test of inline_01 is
for test
-- code from book (in text)
for system_under_test : computer_system
use entity work.computer_system(block_level)
generic map ( instrumented => true )
-- . . .
-- not in book
;
-- end not in book
end for;
-- end code from book
end for;
end configuration inline_01_test;
|
<reponame>mrfreedeer/Arquitectura-Computadores
----------------------------------------------------------------------------------
-- Company: iMacLinDows
-- Engineers: <NAME>
-- <NAME>
--
-- Create Date: 15:58:29 04/28/2018
-- Design Name: Windows Manager Testbench File Design
-- Module Name: Tb_Windows_Manager - Behavioral
-- Project Name: Segmented Processor
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tb_Windows_Manager IS
END Tb_Windows_Manager;
ARCHITECTURE behavior OF Tb_Windows_Manager IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Windows_Manager
PORT(
RS1 : IN std_logic_vector(4 downto 0);
RS2 : IN std_logic_vector(4 downto 0);
RD : IN std_logic_vector(4 downto 0);
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic;
nRS1 : OUT std_logic_vector(5 downto 0);
nRS2 : OUT std_logic_vector(5 downto 0);
nRD : OUT std_logic_vector(5 downto 0);
nCWP : OUT std_logic
);
END COMPONENT;
--Inputs
signal RS1 : std_logic_vector(4 downto 0) := (others => '0');
signal RS2 : std_logic_vector(4 downto 0) := (others => '0');
signal RD : std_logic_vector(4 downto 0) := (others => '0');
signal OP : std_logic_vector(1 downto 0) := (others => '0');
signal OP3 : std_logic_vector(5 downto 0) := (others => '0');
signal CWP : std_logic := '0';
--Outputs
signal nRS1 : std_logic_vector(5 downto 0);
signal nRS2 : std_logic_vector(5 downto 0);
signal nRD : std_logic_vector(5 downto 0);
signal nCWP : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Windows_Manager PORT MAP (
RS1 => RS1,
RS2 => RS2,
RD => RD,
OP => OP,
OP3 => OP3,
CWP => CWP,
nRS1 => nRS1,
nRS2 => nRS2,
nRD => nRD,
nCWP => nCWP
);
-- Stimulus process
stim_proc: process
begin
CWP <= '0';
RS1 <= "00000";
RS2 <= "01000";
RD <= "10000";
OP <= "10";
OP3 <= "000000";
wait for 40 ns;
CWP <= '0';
RS1 <= "11100";
RS2 <= "01101";
RD <= "10101";
OP <= "10";
OP3 <= "111101";
wait for 40 ns;
CWP <= '0';
RS1 <= "11100";
RS2 <= "01101";
RD <= "10101";
OP <= "10";
OP3 <= "111100";
wait for 40 ns;
CWP <= '1';
RS1 <= "00000";
RS2 <= "01000";
RD <= "10000";
OP <= "10";
OP3 <= "000000";
wait for 40 ns;
CWP <= '1';
RS1 <= "11100";
RS2 <= "01101";
RD <= "10101";
OP <= "10";
OP3 <= "111101";
wait for 40 ns;
CWP <= '1';
RS1 <= "11100";
RS2 <= "01101";
RD <= "10101";
OP <= "10";
OP3 <= "111100";
wait for 40 ns;
-- insert stimulus here
wait;
end process;
END;
|
<filename>IFIDRegister.vhd
library ieee;
use ieee.std_logic_1164.all;
entity IFIDRegister is
port(
clk: in std_logic;
AddressIn, InstructionIn: in std_logic_vector(31 downto 0);
AddressOut, InstructionOut: out std_logic_vector(31 downto 0)
);
end IFIDRegister;
architecture Structural of IFIDRegister is
signal Address, Instruction: std_logic_vector(31 downto 0) := X"00000000";
begin
AddressOut <= Address;
InstructionOut <= Instruction;
process(clk)
begin
if rising_edge(clk) then
Address <= AddressIn;
Instruction <= InstructionIn;
end if;
end process;
end Structural;
|
library IEEE;
library work;
use work.commonPackage.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity ImgGenModule is
Port ( clk : in STD_LOGIC;
x_counter : in STD_LOGIC_VECTOR (11 downto 0);
y_counter : in STD_LOGIC_VECTOR (11 downto 0);
VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR ( 3 downto 0);
reg : in rpn_type_register;
output_string : in string(3 downto 1) := " ";
error_out_of_bound : in std_logic;
error_division_by_zero : in std_logic
-- error_out_of_bound_output : in std_logic
);
-- operation : in STD_LOGIC_VECTOR(1 downto 0);
-- inputData : in STD_LOGIC_VECTOR(DATA_SIZE - 1 downto 0);
-- outputData: in STD_LOGIC_VECTOR(DATA_SIZE - 1 downto 0));
-- plus_btn : in STD_LOGIC;
-- minus_btn : in STD_LOGIC;
-- mul_btn : in STD_LOGIC;
-- div_btn : in STD_LOGIC;
-- eql_btn : in STD_LOGIC);
end ImgGenModule;
architecture Behavioral of ImgGenModule is
constant BIG_OFFSET_W : INTEGER := 550;
CONSTANT BIG_OFFSET_H : INTEGER := 450;
signal x : std_logic_vector(11 downto 0) ;
signal y : std_logic_vector(11 downto 0) ;
signal v : std_logic;
-- will enable or disable RGB at certain times
signal pixel_active : std_logic;
-- dummy variables
signal vga_red_o : std_logic_vector(3 downto 0);
signal vga_green_o : std_logic_vector(3 downto 0);
signal vga_blue_o : std_logic_vector(3 downto 0);
-- VGA R, G and B signals to connect output with the design
signal vga_red_comb : std_logic_vector(3 downto 0);
signal vga_green_comb : std_logic_vector(3 downto 0);
signal vga_blue_comb : std_logic_vector(3 downto 0);
signal wid : std_logic;
-- signal op_signal : STD_LOGIC_VECTOR (1 downto 0);
-- signal test_led_signal : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal horizontal_int_counter : integer := to_integer(signed(x_counter));
signal vertical_int_counter : integer := to_integer(signed(y_counter));
-- results
signal d1 : std_logic := '0';
signal d2 : std_logic := '0';
signal d3 : std_logic := '0';
signal d4 : std_logic := '0';
signal d5 : std_logic := '0';
signal d6 : std_logic := '0';
signal d7 : std_logic := '0';
signal d8 : std_logic := '0';
signal d9 : std_logic := '0'; -- test
signal d10 : std_logic := '0';
signal d_error_out_of_bound : std_logic := '0';
signal d_error_division_by_zero : std_logic := '0';
-- signal d11 : std_logic := '0'; -- error Overflow!
-- signal lastButtonState : std_logic := '0';
-- signal color : std_logic_vector(1 downto 0) := "00";
-- button debounce code
-- signal flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
-- signal counter_set : STD_LOGIC; --sync reset to zero
-- signal counter_out : STD_LOGIC_VECTOR(20 DOWNTO 0) := (OTHERS => '0'); --counter output
-- signal debounce_result : std_logic;
--signal test_led_signal : std_logic_vector(1 downto 0);
-- constant clk_period : time := 20 ns; -- clock period
-- constant debounce_time : time := 20 ms; -- time after which the signal is considered stable
-- constant on_state : std_logic := '0'; -- pushed state (vs rest state)
-- constant deb_cycles : integer := debounce_time / clk_period; -- number of clock cycles in the debounce time
-- signal count : integer range 0 to (deb_cycles + 1) := 0;
-- signal state : std_logic := '0';
-- signal output : std_logic := '1';
-- last states
-- signal lastPlusBtnState : std_logic := '0';
-- signal lastMinusBtnState : std_logic := '0';
-- signal lastMulBtnState : std_logic := '0';
-- signal lastDivBtnState : std_logic := '0';
-- signal lastEqlBtnState : std_logic := '0';
-- signal led_signal : std_logic_vector(1 downto 0) := "00";
-- signal operation_char : string := " ";
signal reg0_string : string(1 to STRING_DATA_SIZE) := DATA_SIZED_NULL_STRING;
signal reg1_string : string(1 to STRING_DATA_SIZE) := DATA_SIZED_NULL_STRING;
signal reg2_string : string(1 to STRING_DATA_SIZE) := DATA_SIZED_NULL_STRING;
signal reg3_string : string(1 to STRING_DATA_SIZE) := DATA_SIZED_NULL_STRING;
signal temp_string : string(1 to 3) := " ";
signal reg0_int : integer;
signal reg1_int : integer;
signal reg2_int : integer;
signal reg3_int : integer;
-- signal error_out_of_bound_signal : std_logic;
component stringROM is
Port
(
reg0_int : in integer;
reg1_int : in integer;
reg2_int : in integer;
reg3_int : in integer;
reg0_string : out string(1 to 4);
reg1_string : out string(1 to 4);
reg2_string : out string(1 to 4);
reg3_string : out string(1 to 4)
);
end component;
-- signal test_string : string(1 to STRING_DATA_SIZE) := " ";
begin
textElement1: entity work.Pixel_On_Text
generic map (
textLength => 7
)
port map(
clk => clk,
displayText => "1 2 3 +",
position => (BIG_OFFSET_W + 50 , 50 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d1
);
textElement2: entity work.Pixel_On_Text
generic map (
textLength => 7
)
port map(
clk => clk,
displayText => "4 5 6 -",
position => (BIG_OFFSET_W + 50, 66 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d2
);
textElement3: entity work.Pixel_On_Text
generic map (
textLength => 7
)
port map(
clk => clk,
displayText => "7 8 9 =",
position => (BIG_OFFSET_W + 50, 82 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d3
);
textElement4: entity work.Pixel_On_Text
generic map (
textLength => 1
)
port map(
clk => clk,
displayText => "0",
position => (BIG_OFFSET_W + 50, 98 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d4
);
-- reg3Text: entity work.Pixel_On_Text
-- generic map (
-- textLength => STRING_DATA_SIZE
-- )
-- port map(
-- clk => clk,
-- displayText => reg3_string,
-- position => (50, 114),
-- horzCoord => horizontal_int_counter,
-- vertCoord => vertical_int_counter,
-- pixel => d5
-- );
-- reg2Text: entity work.Pixel_On_Text
-- generic map (
-- textLength => STRING_DATA_SIZE
-- )
-- port map(
-- clk => clk,
-- displayText => reg2_string,
-- position => (50, 130),
-- horzCoord => horizontal_int_counter,
-- vertCoord => vertical_int_counter,
-- pixel => d6
-- );
-- reg1Text: entity work.Pixel_On_Text
-- generic map (
-- textLength => STRING_DATA_SIZE
-- )
-- port map(
-- clk => clk,
-- displayText => reg1_string,
-- position => (50, 146),
-- horzCoord => horizontal_int_counter,
-- vertCoord => vertical_int_counter,
-- pixel => d7
-- );
reg0Text: entity work.Pixel_On_Text
generic map (
textLength => STRING_DATA_SIZE
)
port map(
clk => clk,
displayText => reg0_string,
position => (BIG_OFFSET_W + 50, 162 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d8
);
temp_string <= output_string;
temp_Text: entity work.Pixel_On_Text
generic map (
3
)
port map(
clk => clk,
displayText => temp_string,
position => (BIG_OFFSET_W + 50, 178 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d10
);
-- d_error_out_of_bound <= error_out_of_bound;
-- d_error_division_by_zero <= error_division_by_zero;
-- d_error_out_of_bound <= '1';
-- d_error_division_by_zero <= '1';
error_bound_txt: entity work.Pixel_On_Text
generic map (
9
)
port map(
clk => clk,
displayText => "Overflow!",
position => (BIG_OFFSET_W + 50, 194 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d_error_out_of_bound
);
error_div_txt: entity work.Pixel_On_Text
generic map (
17
)
port map(
clk => clk,
displayText => "Division by Zero!",
position => (BIG_OFFSET_W + 50, 210 + BIG_OFFSET_H),
horzCoord => horizontal_int_counter,
vertCoord => vertical_int_counter,
pixel => d_error_division_by_zero
);
-- process(d_error_out_of_bound, d_error_division_by_zero, error_out_of_bound, error_division_by_zero)
-- begin
-- if
-- end process;
-- test_string <= integer'image(to_integer(reg(0)));
-- testText: entity work.Pixel_On_Text
-- generic map (
-- textLength => 4
-- )
-- port map(
-- clk => clk,
-- displayText => test_string,
-- position => (50, 200),
-- horzCoord => horizontal_int_counter,
-- vertCoord => vertical_int_counter,
-- pixel => d9
-- );
-- operationText: entity work.Pixel_On_Text
-- generic map (
-- textLength => 1
-- )
-- port map(
-- clk => clk,
-- displayText => operation_char,
-- position => (130, 114),
-- horzCoord => horizontal_int_counter,
-- vertCoord => vertical_int_counter,
-- pixel => d5
-- );
-- reg0_string <= to_string(reg(0));
-- reg1_string <= to_string(reg(1));
-- reg2_string <= to_string(reg(2));
-- reg3_string <= to_string(reg(3));
reg0_int <= to_integer(reg(0));
reg1_int <= to_integer(reg(1));
reg2_int <= to_integer(reg(2));
reg3_int <= to_integer(reg(3));
string_rom_uut : stringROM port map
(
reg0_int => reg0_int,
reg1_int => reg1_int,
reg2_int => reg2_int,
reg3_int => reg3_int,
reg0_string => reg0_string,
reg1_string => reg1_string,
reg2_string => reg2_string,
reg3_string => reg3_string
);
-- d11 <= error_out_of_bound_output;
-- error_outofbound_text :
-- entity work.Pixel_On_Text
-- generic map (
-- 17
-- )
-- port map(
-- clk => clk,
-- displayText => "Error : Overflow!",
-- position => (60, 162),
-- horzCoord => horizontal_int_counter,
-- vertCoord => vertical_int_counter,
-- pixel => d11
-- );
-- process(reg) --, outputData
-- begin
---- reg0_string <= integer'image(reg0_int);
---- reg1_string <= integer'image(reg1_int);
---- reg2_string <= integer'image(reg2_int);
---- reg3_string <= integer'image(reg3_int);
-- case(reg0_int) is
-- when 999 => reg0_string <= " 999";
-- when 998 => reg0_string <= " 998";
-- case reg(0) is
-- when "0000" => reg0_string <= "0000";
-- when "0001" => reg0_string <= "0001";
-- when "0010" => reg0_string <= "0010";
-- when "0011" => reg0_string <= "0011";
-- when "0100" => reg0_string <= "0100";
-- when "0101" => reg0_string <= "0101";
-- when "0110" => reg0_string <= "0110";
-- when "0111" => reg0_string <= "0111";
-- when "1000" => reg0_string <= "1000";
-- when "1001" => reg0_string <= "1001";
-- when "1010" => reg0_string <= "1010";
-- when "1011" => reg0_string <= "1011";
-- when "1100" => reg0_string <= "1100";
-- when "1101" => reg0_string <= "1101";
-- when "1110" => reg0_string <= "1110";
-- when "1111" => reg0_string <= "1111";
-- when others => reg0_string <= "xxxx";
-- end case;
-- case reg(1) is
-- when "0000" => reg1_string <= "0000";
-- when "0001" => reg1_string <= "0001";
-- when "0010" => reg1_string <= "0010";
-- when "0011" => reg1_string <= "0011";
-- when "0100" => reg1_string <= "0100";
-- when "0101" => reg1_string <= "0101";
-- when "0110" => reg1_string <= "0110";
-- when "0111" => reg1_string <= "0111";
-- when "1000" => reg1_string <= "1000";
-- when "1001" => reg1_string <= "1001";
-- when "1010" => reg1_string <= "1010";
-- when "1011" => reg1_string <= "1011";
-- when "1100" => reg1_string <= "1100";
-- when "1101" => reg1_string <= "1101";
-- when "1110" => reg1_string <= "1110";
-- when "1111" => reg1_string <= "1111";
-- when others => reg1_string <= "xxxx";
-- end case;
-- case reg(2) is
-- when "0000" => reg2_string <= "0000";
-- when "0001" => reg2_string <= "0001";
-- when "0010" => reg2_string <= "0010";
-- when "0011" => reg2_string <= "0011";
-- when "0100" => reg2_string <= "0100";
-- when "0101" => reg2_string <= "0101";
-- when "0110" => reg2_string <= "0110";
-- when "0111" => reg2_string <= "0111";
-- when "1000" => reg2_string <= "1000";
-- when "1001" => reg2_string <= "1001";
-- when "1010" => reg2_string <= "1010";
-- when "1011" => reg2_string <= "1011";
-- when "1100" => reg2_string <= "1100";
-- when "1101" => reg2_string <= "1101";
-- when "1110" => reg2_string <= "1110";
-- when "1111" => reg2_string <= "1111";
-- when others => reg2_string <= "xxxx";
-- end case;
-- case reg(3) is
-- when "0000" => reg3_string <= "0000";
-- when "0001" => reg3_string <= "0001";
-- when "0010" => reg3_string <= "0010";
-- when "0011" => reg3_string <= "0011";
-- when "0100" => reg3_string <= "0100";
-- when "0101" => reg3_string <= "0101";
-- when "0110" => reg3_string <= "0110";
-- when "0111" => reg3_string <= "0111";
-- when "1000" => reg3_string <= "1000";
-- when "1001" => reg3_string <= "1001";
-- when "1010" => reg3_string <= "1010";
-- when "1011" => reg3_string <= "1011";
-- when "1100" => reg3_string <= "1100";
-- when "1101" => reg3_string <= "1101";
-- when "1110" => reg3_string <= "1110";
-- when "1111" => reg3_string <= "1111";
-- when others => reg3_string <= "xxxx";
-- end case;
-- end process;
-- process(x, op_signal)
-- begin
-- end process;
-- if (op_signal = "00" and (((x > 200 and x < 230) and(( y > 0 and y < 420))) or ((x > 0 and x < 420) and (y > 220 and y < (1080-830)))))
-- then
-- pixel_active <= '1';
-- elsif (op_signal = "01" and (x > 0 and x < 420) and (y > 220 and y < (1080-830))) then
-- pixel_active <= '1';
-- elsif (op_signal = "10" and (((x > 0 and x < 70 ) and (y > 0 and y < 70 )) -- main diogonal
-- or ((x > 70 and x < 140) and (y > 70 and y < 140))
-- or ((x > 140 and x < 210) and (y > 140 and y < 210))
-- or ((x > 210 and x < 280) and (y > 210 and y < 280))
-- or ((x > 280 and x < 350) and (y > 280 and y < 350))
-- or ((x > 350 and x < 420) and (y > 350 and y < 420))
-- or ((x > 350 and x < 420) and (y > 0 and y < 70 )) -- secondary diogonal
-- or ((x > 280 and x < 350) and (y > 70 and y < 140))
-- or ((x > 210 and x < 280) and (y > 140 and y < 210))
-- or ((x > 140 and x < 210) and (y > 210 and y < 280))
-- or ((x > 70 and x < 140) and (y > 280 and y < 350))
-- or ((x > 0 and x < 70 ) and (y > 350 and y < 420)) )) then
-- pixel_active <= '1';
-- elsif (op_signal = "11" and ( ((x > 0 and x < 420 ) and (y > 220 and y < (1080-830)))
-- or ((x > 170 and x < 240) and (y > 120 and y < 190 ))
-- or ((x > 170 and x < 240) and (y > 280 and y < 350 )) )) then
-- pixel_active <= '1';
-- else
-- pixel_active <= '0';
-- end if ;
-- end process ;
-- debounce code
-- counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
-- PROCESS(clk)
-- BEGIN
-- IF(clk'EVENT and clk = '1') THEN
-- flipflops(0) <= test_pushbutton;
-- flipflops(1) <= flipflops(0);
-- If(counter_set = '1') THEN --reset counter because input is changing
-- counter_out <= (OTHERS => '0');
-- ELSIF(counter_out(20) = '0') THEN --stable input time is not yet met
-- counter_out <= counter_out + 1;
-- ELSE --stable input time is met
-- debounce_result <= flipflops(1);
-- END IF;
-- END IF;
-- END PROCESS;
-- end debounce code
-- process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(test_pushbutton = '1') then
-- color <= color + "01";
-- else
-- color <= "00";
-- end if;
-- end if;
-- end process;
-- process(color)
-- begin
-- if color = "00" then
-- vga_red_o <= "1111";
-- vga_green_o <= "0000";
-- vga_blue_o <= "0000";
-- elsif color = "01" then
-- vga_red_o <= "0000";
-- vga_green_o <= "1111";
-- vga_blue_o <= "0000";
-- elsif color = "10" then
-- vga_red_o <= "0000";
-- vga_green_o <= "0000";
-- vga_blue_o <= "1111";
-- else
-- vga_red_o <= "1111";
-- vga_green_o <= "1111";
-- vga_blue_o <= "0000";
-- end if;
-- end process;
-- process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(debounce_result = '1' and lastButtonState = '0') then --assuming active-high
-- test_led_signal(1) <= not test_led_signal(1);
-- end if;
-- lastButtonState <= debounce_result;
-- end if;
-- end process;
-- process(test_pushbutton, clk)
-- begin
-- if(rising_edge(clk)) then
-- if (test_pushbutton /= state) then -- if the state changed reset the counter
-- count <= 0;
-- output <= not on_state;
-- elsif (count < deb_cycles) then -- if the change isn't changed and 20 ms aren't passed increase the counter
-- count <= count + 1;
-- output <= not on_state;
-- elsif (count = deb_cycles and test_pushbutton = on_state) then -- 20 ms of stability!
-- --> output the "on state"
-- count <= count + 1;
-- output <= on_state;
-- else -- If the button is not pressed or the 20 ms
-- output <= not on_state; -- are passed and the button is still pressed
-- -- keep it in off state.
-- end if;
-- state <= test_pushbutton;
-- end if;
-- end process;
-- with output select test_led_signal <= "01" when '0', "10" when '1';
-- test_led <= test_led_signal;
-- process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(plus_btn = '1' and lastPlusBtnState = '0') then --assuming active-high
-- operation_char <= "+";
-- end if;
-- if(minus_btn = '1' and lastMinusBtnState = '0') then --assuming active-high
-- operation_char <= "-";
-- end if;
-- if(mul_btn = '1' and lastMulBtnState = '0') then --assuming active-high
-- operation_char <= "*";
-- end if;
-- if(div_btn = '1' and lastDivBtnState = '0') then --assuming active-high
-- operation_char <= "/";
-- end if;
-- if(eql_btn = '1' and lastEqlBtnState = '0') then --assuming active-high
-- operation_char <= "=";
-- end if;
-- lastPlusBtnState <= plus_btn;
-- lastMinusBtnState <= minus_btn;
-- lastMulBtnState <= mul_btn;
-- lastDivBtnState <= div_btn;
-- lastEqlBtnState <= eql_btn;
-- end if;
-- end process;
vga_red_o <= "1111";
vga_green_o <= "1111";
vga_blue_o <= "0000";
x <= x_counter;
y <= y_counter;
v <= pixel_active or d1 or d2 or d3 or d4 or d5 or d6 or d7 or d8 or d10
or (d_error_division_by_zero and error_division_by_zero)
or (d_error_out_of_bound and error_out_of_bound);
vga_red_comb <= (v & v & v & v) and vga_red_o ;
vga_green_comb <= (v & v & v & v) and vga_green_o;
vga_blue_comb <= (v & v & v & v) and vga_blue_o;
-- op_signal <= op_input;
process (clk)
begin
if (rising_edge(clk)) then
VGA_RED <= vga_red_comb;
VGA_GREEN <= vga_green_comb;
VGA_BLUE <= vga_blue_comb;
end if;
end process;
end Behavioral;
|
<gh_stars>100-1000
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.wishbone_types.all;
use work.utils.all;
use work.helpers.all;
entity litedram_wrapper is
generic (
DRAM_ABITS : positive;
DRAM_ALINES : natural;
DRAM_DLINES : natural;
DRAM_PORT_WIDTH : positive;
-- Pseudo-ROM payload
PAYLOAD_SIZE : natural;
PAYLOAD_FILE : string;
-- L2 cache --
-- Line size in bytes
LINE_SIZE : positive := 128;
-- Number of lines in a set
NUM_LINES : positive := 64;
-- Number of ways
NUM_WAYS : positive := 4;
-- Max number of stores in the queue
STOREQ_DEPTH : positive := 8;
-- Don't send loads until all pending stores acked in litedram
NO_LS_OVERLAP : boolean := false;
-- Debug
LITEDRAM_TRACE : boolean := false;
TRACE : boolean := false
);
port(
-- LiteDRAM generates the system clock and reset
-- from the input clkin
clk_in : in std_ulogic;
rst : in std_ulogic;
system_clk : out std_ulogic;
system_reset : out std_ulogic;
core_alt_reset : out std_ulogic;
pll_locked : out std_ulogic;
-- Wishbone ports:
wb_in : in wishbone_master_out;
wb_out : out wishbone_slave_out;
wb_ctrl_in : in wb_io_master_out;
wb_ctrl_out : out wb_io_slave_out;
wb_ctrl_is_csr : in std_ulogic;
wb_ctrl_is_init : in std_ulogic;
-- Misc
init_done : out std_ulogic;
init_error : out std_ulogic;
-- DRAM wires
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic
);
end entity litedram_wrapper;
architecture behaviour of litedram_wrapper is
component litedram_core port (
clk : in std_ulogic;
rst : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
wb_ctrl_cyc : in std_ulogic;
wb_ctrl_stb : in std_ulogic;
wb_ctrl_ack : out std_ulogic;
wb_ctrl_we : in std_ulogic;
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
wb_ctrl_err : out std_ulogic;
user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic;
user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
user_port_native_0_wdata_valid : in std_ulogic;
user_port_native_0_wdata_ready : out std_ulogic;
user_port_native_0_wdata_we : in std_ulogic_vector(DRAM_PORT_WIDTH/8-1 downto 0);
user_port_native_0_wdata_data : in std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0);
user_port_native_0_rdata_valid : out std_ulogic;
user_port_native_0_rdata_ready : in std_ulogic;
user_port_native_0_rdata_data : out std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0)
);
end component;
signal user_port0_cmd_valid : std_ulogic;
signal user_port0_cmd_ready : std_ulogic;
signal user_port0_cmd_we : std_ulogic;
signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
signal user_port0_wdata_valid : std_ulogic;
signal user_port0_wdata_ready : std_ulogic;
signal user_port0_wdata_we : std_ulogic_vector(DRAM_PORT_WIDTH/8-1 downto 0);
signal user_port0_wdata_data : std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0);
signal user_port0_rdata_valid : std_ulogic;
signal user_port0_rdata_ready : std_ulogic;
signal user_port0_rdata_data : std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0);
signal wb_ctrl_adr : std_ulogic_vector(29 downto 0);
signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0);
signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0);
signal wb_ctrl_sel : std_ulogic_vector(3 downto 0);
signal wb_ctrl_cyc : std_ulogic := '0';
signal wb_ctrl_stb : std_ulogic;
signal wb_ctrl_ack : std_ulogic;
signal wb_ctrl_we : std_ulogic;
signal wb_init_in : wb_io_master_out;
signal wb_init_out : wb_io_slave_out;
-- DRAM data port width
constant DRAM_DBITS : natural := DRAM_PORT_WIDTH;
-- DRAM data port sel bits
constant DRAM_SBITS : natural := (DRAM_DBITS / 8);
-- WB geometry (just a few shortcuts)
constant WBL : positive := wb_in.dat'length;
constant WBSL : positive := wb_in.sel'length;
-- Select a WB word inside DRAM port width
constant WB_WORD_COUNT : positive := DRAM_DBITS/WBL;
constant WB_WSEL_BITS : positive := log2(WB_WORD_COUNT);
-- BRAM organisation: We never access more than wishbone_data_bits at
-- a time so to save resources we make the array only that wide, and
-- use consecutive indices for to make a cache "line"
--
-- ROW_SIZE is the width in bytes of the BRAM, ie, litedram port width
constant ROW_SIZE : natural := DRAM_DBITS / 8;
-- ROW_PER_LINE is the number of row (litedram transactions) in a line
constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
-- BRAM_ROWS is the number of rows in BRAM needed to represent the full
-- dcache
constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
-- Bit fields counts in the address
-- ROW_BITS is the number of bits to select a row
constant ROW_BITS : natural := log2(BRAM_ROWS);
-- ROW_LINEBITS is the number of bits to select a row within a line
constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
-- LINE_OFF_BITS is the number of bits for the offset in a cache line
constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
-- ROW_OFF_BITS is the number of bits for the offset in a row
constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
-- REAL_ADDR_BITS is the number of real address bits that we store
constant REAL_ADDR_BITS : positive := DRAM_ABITS + ROW_OFF_BITS;
-- INDEX_BITS is the number if bits to select a cache line
constant INDEX_BITS : natural := log2(NUM_LINES);
-- SET_SIZE_BITS is the log base 2 of the set size
constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
-- TAG_BITS is the number of bits of the tag part of the address
constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
-- WAY_BITS is the number of bits to select a way
constant WAY_BITS : natural := log2(NUM_WAYS);
subtype row_t is integer range 0 to BRAM_ROWS-1;
subtype index_t is integer range 0 to NUM_LINES-1;
subtype way_t is integer range 0 to NUM_WAYS-1;
subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
-- The cache data BRAM organized as described above for each way
subtype cache_row_t is std_ulogic_vector(DRAM_DBITS-1 downto 0);
-- The cache tags LUTRAM has a row per set. Vivado is a pain and will
-- not handle a clean (commented) definition of the cache tags as a 3d
-- memory. For now, work around it by putting all the tags
subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
-- type cache_tags_set_t is array(way_t) of cache_tag_t;
-- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
type cache_tags_array_t is array(index_t) of cache_tags_set_t;
-- The cache valid bits
subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
type cache_valids_t is array(index_t) of cache_way_valids_t;
-- "Temporary" valid bits for the rows of the currently refilled line
type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
-- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
signal cache_tags : cache_tags_array_t;
signal cache_valids : cache_valids_t;
attribute ram_style : string;
attribute ram_style of cache_tags : signal is "distributed";
--
-- Store queue signals
--
-- We store a single wishbone dword per entry (64-bit)
-- along with the wishbone sel bits and the necessary address
-- bits to select which part of DRAM port to write to.
constant STOREQ_BITS : positive := WBL + WBSL + WB_WSEL_BITS;
signal storeq_rd_ready : std_ulogic;
signal storeq_rd_valid : std_ulogic;
signal storeq_rd_data : std_ulogic_vector(STOREQ_BITS-1 downto 0);
signal storeq_wr_ready : std_ulogic;
signal storeq_wr_valid : std_ulogic;
signal storeq_wr_data : std_ulogic_vector(STOREQ_BITS-1 downto 0);
--
-- Cache management signals
--
-- Cache state machine
type state_t is (IDLE, -- Normal load hit processing
REFILL_CLR_TAG, -- Cache refill clear tag
REFILL_WAIT_ACK); -- Cache refill wait ack
signal state : state_t;
-- Latched WB request
signal wb_req : wishbone_master_out := wishbone_master_out_init;
-- Stashed WB request
signal wb_stash : wishbone_master_out := wishbone_master_out_init;
-- Read pipeline (to handle cache RAM latency)
signal read_ack_0 : std_ulogic := '0';
signal read_ack_1 : std_ulogic := '0';
signal read_wsl_0 : std_ulogic_vector(WB_WSEL_BITS-1 downto 0) := (others => '0');
signal read_wsl_1 : std_ulogic_vector(WB_WSEL_BITS-1 downto 0) := (others => '0');
signal read_way_0 : way_t;
signal read_way_1 : way_t;
-- Store ack pipeline
signal store_ack_0 : std_ulogic := '0';
signal store_ack_1 : std_ulogic := '0';
-- Async signals decoding latched request
type req_op_t is (OP_NONE,
OP_LOAD_HIT,
OP_LOAD_MISS,
OP_STORE_HIT,
OP_STORE_MISS,
OP_STORE_DELAYED);
signal req_index : index_t;
signal req_row : row_t;
signal req_hit_way : way_t;
signal req_tag : cache_tag_t;
signal req_op : req_op_t;
signal req_laddr : std_ulogic_vector(REAL_ADDR_BITS-1 downto 0);
signal req_wsl : std_ulogic_vector(WB_WSEL_BITS-1 downto 0);
signal req_we : std_ulogic_vector(DRAM_SBITS-1 downto 0);
signal req_wdata : std_ulogic_vector(DRAM_DBITS-1 downto 0);
signal stall : std_ulogic;
-- Line refill command signals and latches
signal refill_cmd_valid : std_ulogic;
signal refill_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
signal refill_way : way_t;
signal refill_index : index_t;
signal refill_row : row_t;
signal refill_end_row : row_in_line_t;
signal refill_rows_vlid : row_per_line_valid_t;
-- Cache RAM interface
type cache_ram_out_t is array(way_t) of cache_row_t;
signal cache_out : cache_ram_out_t;
-- PLRU output interface
type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
signal plru_victim : plru_out_t;
--
-- Helper functions to decode incoming requests
--
-- Return the DRAM real address from a wishbone address
function get_real_addr(addr: wishbone_addr_type) return std_ulogic_vector is
variable ra: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0) := (others => '0');
begin
ra(REAL_ADDR_BITS - 1 downto wishbone_log2_width) :=
addr(REAL_ADDR_BITS - wishbone_log2_width - 1 downto 0);
return ra;
end;
-- Return the cache line index (tag index) for an address
function get_index(addr: wishbone_addr_type) return index_t is
begin
return to_integer(unsigned(addr(SET_SIZE_BITS - wishbone_log2_width - 1 downto
LINE_OFF_BITS - wishbone_log2_width)));
end;
-- Return the cache row index (data memory) for an address
function get_row(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto 0)) return row_t is
begin
return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
end;
-- Return the index of a row within a line
function get_row_of_line(row: row_t) return row_in_line_t is
variable row_v : unsigned(ROW_BITS-1 downto 0);
begin
row_v := to_unsigned(row, ROW_BITS);
return row_v(ROW_LINEBITS-1 downto 0);
end;
-- Returns whether this is the last row of a line. It takes a DRAM address
function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS);
last: row_in_line_t)
return boolean is
begin
return unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
end;
-- Returns whether this is the last row of a line
function is_last_row(row: row_t; last: row_in_line_t) return boolean is
begin
return get_row_of_line(row) = last;
end;
-- Return the address of the next row in the current cache line. It takes a
-- DRAM address
function next_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS))
return std_ulogic_vector is
variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
variable result : std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS);
begin
-- Is there no simpler way in VHDL to generate that 3 bits adder ?
row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
result := addr;
result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
return result;
end;
-- Return the next row in the current cache line. We use a dedicated
-- function in order to limit the size of the generated adder to be
-- only the bits within a cache line (3 bits with default settings)
--
function next_row(row: row_t) return row_t is
variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
begin
row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
row_idx := row_v(ROW_LINEBITS-1 downto 0);
row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
return to_integer(unsigned(row_v));
end;
-- Get the tag value from the address
function get_tag(addr: wishbone_addr_type) return cache_tag_t is
begin
return addr(REAL_ADDR_BITS - wishbone_log2_width - 1 downto
SET_SIZE_BITS - wishbone_log2_width);
end;
-- Read a tag from a tag memory row
function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
begin
return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
end;
-- Write a tag to tag memory row
procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
tag: cache_tag_t) is
begin
tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
end;
begin
-- Sanity checks
assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
report "geometry bits don't add up" severity FAILURE;
assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
report "geometry bits don't add up" severity FAILURE;
assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
report "geometry bits don't add up" severity FAILURE;
assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
report "geometry bits don't add up" severity FAILURE;
-- alternate core reset address set when DRAM is not initialized.
core_alt_reset <= not init_done;
-- Init code BRAM memory slave
init_ram_0: entity work.dram_init_mem
generic map(
EXTRA_PAYLOAD_FILE => PAYLOAD_FILE,
EXTRA_PAYLOAD_SIZE => PAYLOAD_SIZE
)
port map(
clk => system_clk,
wb_in => wb_init_in,
wb_out => wb_init_out
);
--
-- Control bus wishbone: This muxes the wishbone to the CSRs
-- and an internal small one to the init BRAM
--
-- Init DRAM wishbone IN signals
wb_init_in.adr <= wb_ctrl_in.adr;
wb_init_in.dat <= wb_ctrl_in.dat;
wb_init_in.sel <= wb_ctrl_in.sel;
wb_init_in.we <= wb_ctrl_in.we;
wb_init_in.stb <= wb_ctrl_in.stb;
wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
-- DRAM CSR IN signals. Extra latch to help with timing
csr_latch: process(system_clk)
begin
if rising_edge(system_clk) then
if system_reset = '1' then
wb_ctrl_cyc <= '0';
wb_ctrl_stb <= '0';
else
-- XXX Maybe only update addr when cyc = '1' to save power ?
wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(13 downto 0);
wb_ctrl_dat_w <= wb_ctrl_in.dat;
wb_ctrl_sel <= wb_ctrl_in.sel;
wb_ctrl_we <= wb_ctrl_in.we;
wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr;
-- Clear stb on ack otherwise the memory will latch
-- the write twice which breaks levelling. On the next
-- cycle we will latch an updated stb that takes the
-- ack into account.
if wb_ctrl_ack = '1' then
wb_ctrl_stb <= '0';
end if;
end if;
end if;
end process;
-- Ctrl bus wishbone OUT signals. XXX Consider adding latch on
-- CSR response to help timing
wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
else wb_init_out.ack;
wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
else wb_init_out.dat;
wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
'0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
-- Generate a cache RAM for each way
rams: for i in 0 to NUM_WAYS-1 generate
signal do_read : std_ulogic;
signal do_write : std_ulogic;
signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
signal wr_data : std_ulogic_vector(DRAM_DBITS-1 downto 0);
signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
signal dout : cache_row_t;
begin
way: entity work.cache_ram
generic map (
ROW_BITS => ROW_BITS,
WIDTH => DRAM_DBITS,
ADD_BUF => true
)
port map (
clk => system_clk,
rd_en => do_read,
rd_addr => rd_addr,
rd_data => dout,
wr_sel => wr_sel_m,
wr_addr => wr_addr,
wr_data => wr_data
);
process(all)
begin
--
-- Read port
--
do_read <= '1';
cache_out(i) <= dout;
rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
--
-- Write mux: cache refills from DRAM or writes from Wishbone
--
if req_op = OP_STORE_HIT and req_hit_way = i then
-- Write from wishbone
wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
wr_data <= req_wdata;
wr_sel <= req_we;
else
-- Refill from DRAM
wr_data <= user_port0_rdata_data;
wr_sel <= (others => '1');
wr_addr <= std_ulogic_vector(to_unsigned(refill_row, ROW_BITS));
end if;
--
-- Write enable logic
--
do_write <= '0';
if req_op = OP_STORE_HIT and req_hit_way = i then
do_write <= '1';
elsif user_port0_rdata_valid = '1' and refill_way = i then
do_write <= '1';
end if;
-- Mask write selects with do_write since BRAM doesn't always
-- have a global write-enable (Vivado generates TDP instead
-- of SDP when using one, thus doubling cache BRAM usage).
for i in 0 to ROW_SIZE-1 loop
wr_sel_m(i) <= wr_sel(i) and do_write;
end loop;
if TRACE and rising_edge(system_clk) then
if do_write = '1' then
report "cache write way:" & integer'image(i) &
" addr:" & to_hstring(wr_addr) &
" sel:" & to_hstring(wr_sel_m) &
" data:" & to_hstring(wr_data);
end if;
end if;
end process;
end generate;
-- Generate PLRUs
maybe_plrus: if NUM_WAYS > 1 generate
begin
plrus: for i in 0 to NUM_LINES-1 generate
-- PLRU interface
signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
signal plru_acc_en : std_ulogic;
signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
begin
plru : entity work.plru
generic map (
BITS => WAY_BITS
)
port map (
clk => system_clk,
rst => system_reset,
acc => plru_acc,
acc_en => plru_acc_en,
lru => plru_out
);
process(req_index, req_op, req_hit_way, plru_out)
begin
-- PLRU interface
if (req_op = OP_LOAD_HIT or
req_op = OP_STORE_HIT) and req_index = i then
plru_acc_en <= '1';
else
plru_acc_en <= '0';
end if;
plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
plru_victim(i) <= plru_out;
end process;
end generate;
end generate;
--
-- Wishbone request interface:
--
-- - Incoming wishbone request latch (to help with timing)
-- - Read response pipeline (to match BRAM output buffer delay)
-- - Stall generation
--
-- XXX TODO: Properly handle cyc drops before all acks are sent...
--
request_latch: process(system_clk)
begin
if rising_edge(system_clk) then
-- Implement a stash buffer. If we are stalled and stash is
-- free, fill it up. This will generate a WB stall on the
-- next cycle.
if stall = '1' and wb_out.stall = '0' and wb_in.cyc = '1' and wb_in.stb = '1' then
wb_stash <= wb_in;
if TRACE then
report "stashed wb req ! addr:" & to_hstring(wb_in.adr & "000") &
" we:" & std_ulogic'image(wb_in.we) &
" sel:" & to_hstring(wb_in.sel);
end if;
end if;
-- We aren't stalled, see what we can do
if stall = '0' then
if wb_stash.cyc = '1' then
-- Something in stash ! use it and clear stash
wb_req <= wb_stash;
wb_stash.cyc <= '0';
if TRACE then
report "unstashed wb req ! addr:" & to_hstring(wb_stash.adr & "000") &
" we:" & std_ulogic'image(wb_stash.we) &
" sel:" & to_hstring(wb_stash.sel);
end if;
else
-- Grab request from WB
if wb_in.cyc = '1' then
wb_req <= wb_in;
else
wb_req.cyc <= wb_in.cyc;
wb_req.stb <= wb_in.stb;
end if;
if TRACE then
if wb_in.cyc = '1' and wb_in.stb = '1' then
report "latch new wb req ! addr:" & to_hstring(wb_in.adr & "000") &
" we:" & std_ulogic'image(wb_in.we) &
" sel:" & to_hstring(wb_in.sel);
end if;
end if;
end if;
end if;
end if;
end process;
-- Stall when stash is full
wb_out.stall <= wb_stash.cyc;
--
-- Read response pipeline
--
read_pipe: process(system_clk)
begin
if rising_edge(system_clk) then
read_ack_0 <= '1' when req_op = OP_LOAD_HIT else '0';
read_wsl_0 <= req_wsl;
read_way_0 <= req_hit_way;
read_ack_1 <= read_ack_0;
read_wsl_1 <= read_wsl_0;
read_way_1 <= read_way_0;
if TRACE then
if req_op = OP_LOAD_HIT then
report "Load hit addr:" & to_hstring(wb_req.adr & "000") &
" idx:" & integer'image(req_index) &
" tag:" & to_hstring(req_tag) &
" way:" & integer'image(req_hit_way);
elsif req_op = OP_LOAD_MISS then
report "Load miss addr:" & to_hstring(wb_req.adr & "000");
end if;
if read_ack_0 = '1' then
report "read data:" & to_hstring(cache_out(read_way_0));
end if;
end if;
end if;
end process;
--
-- Store acks pipeline
--
store_ack_pipe: process(system_clk)
begin
if rising_edge(system_clk) then
store_ack_1 <= store_ack_0;
end if;
end process;
--
-- Wishbone response generation
--
wb_rseponse: process(all)
variable rdata : std_ulogic_vector(DRAM_DBITS-1 downto 0);
variable store_done : std_ulogic;
variable accept_store : std_ulogic;
variable wsel : natural range 0 to WB_WORD_COUNT-1;
begin
-- Can we accept a store ? This is set when the store queue & command
-- queue are not full.
--
-- This does *not* mean that we will accept the store, there are other
-- reasons to delay them (see OP_STORE_DELAYED).
--
-- A store is fully accepted when *both* req_op is not OP_STORE_DELAYED
-- and accept_store is '1'.
--
-- The reason for this split is to avoid a circular dependency inside
-- LiteDRAM, since cmd_ready from litedram is driven from cmd_valid (*)
-- we don't want to generate cmd_valid from cmd_ready. So we generate
-- it instead from all the *other* conditions that make a store valid.
--
-- (*) It's my understanding that user_port0_cmd_ready from LiteDRAM is
-- ombinational from user_port0_cmd_valid along with a bunch of other
-- internal signals. IE. we won't know that LiteDRAM cannot accept a
-- command until we try to send one.
--
accept_store := user_port0_cmd_ready and storeq_wr_ready;
-- Generate stalls. For stores we stall if we can't accept it.
-- For loads, we stall if we are going to take a load miss or
-- are in the middle of a refill and it isn't a partial hit.
if req_op = OP_STORE_MISS or req_op = OP_STORE_HIT then
stall <= not accept_store;
elsif req_op = OP_LOAD_MISS or req_op = OP_STORE_DELAYED then
stall <= '1';
else
stall <= '0';
end if;
-- Data out mux
rdata := cache_out(read_way_1);
-- Hard wired for 64-bit wishbone
wsel := to_integer(unsigned(read_wsl_1));
wb_out.dat <= rdata((wsel+1)*WBL-1 downto wsel*WBL);
-- Early-complete stores on wishbone.
if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
store_done := accept_store;
else
store_done := '0';
end if;
-- Pipeline store acks
store_ack_0 <= store_done;
-- Generate Wishbone ACKs on read hits and store complete
--
-- This can happen on store right behind loads ! This is why
-- we delay a store when a load ack is in the pipeline in the
-- request decoder below.
--
wb_out.ack <= read_ack_1 or store_ack_1;
assert read_ack_1 = '0' or store_ack_1 = '0' report
"Read ack and store ack collision !"
severity failure;
end process;
--
-- Cache request decode
--
request_decode: process(all)
variable valid : boolean;
variable is_hit : boolean;
variable store_delay : boolean;
variable hit_way : way_t;
begin
-- Extract line, row and tag from request
req_index <= get_index(wb_req.adr);
req_row <= get_row(get_real_addr(wb_req.adr));
req_tag <= get_tag(wb_req.adr);
-- Calculate address of beginning of cache row, will be
-- used for cache miss processing if needed
req_laddr <= get_real_addr(wb_req.adr);
-- Do we have a valid request in the WB latch ?
valid := wb_req.cyc = '1' and wb_req.stb = '1';
-- Store signals (hard wired for 64-bit wishbone at the moment)
req_wsl <= wb_req.adr(WB_WSEL_BITS-1 downto 0);
for i in 0 to WB_WORD_COUNT-1 loop
if to_integer(unsigned(req_wsl)) = i then
req_we(WBSL*(i+1)-1 downto WBSL*i) <= wb_req.sel;
else
req_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00";
end if;
req_wdata(WBL*(i+1)-1 downto WBL*i) <= wb_req.dat;
end loop;
-- Test if pending request is a hit on any way
hit_way := 0;
is_hit := false;
for i in way_t loop
if valid and
(cache_valids(req_index)(i) = '1' or
(state = REFILL_WAIT_ACK and
req_index = refill_index and i = refill_way and
refill_rows_vlid(req_row mod ROW_PER_LINE) = '1')) then
if read_tag(i, cache_tags(req_index)) = req_tag then
hit_way := i;
is_hit := true;
end if;
end if;
end loop;
-- We need to delay stores under some circumstances to avoid
-- collisions with the refill machine.
--
-- Corner case !!! The read acks pipeline takes two extra cycles
-- which means a store ack can collide with a previous load hit
-- ack. Thus we stall stores if we have a load ack pending.
--
if read_ack_0 = '1' or read_ack_1 = '1' then
-- Clash with pending read acks, delay..
store_delay := true;
elsif state /= IDLE then
-- If the reload machine is active, we cannot accept a store
-- for now.
--
-- We could improve this a bit by allowing stores if we have sent
-- all the requests down to litedram (we are only waiting for the
-- responses) *and* either of those conditions is true:
--
-- * It's a miss (doesn't require a write to BRAM) and isn't
-- for the line being reloaded (otherwise we might reload
-- stale data into the cache).
-- * It's a hit on a different way than the one being reloaded
-- in which case there is no conflict for BRAM access.
--
-- Otherwise we delay it...
--
store_delay := true;
else
store_delay := false;
end if;
-- Generate the req op. We only allow OP_LOAD_* when in the
-- IDLE state as our PLRU and ACK generation rely on this,
-- stores are allowed in IDLE state.
--
req_op <= OP_NONE;
if valid then
if wb_req.we = '1' then
if store_delay then
req_op <= OP_STORE_DELAYED;
elsif is_hit then
req_op <= OP_STORE_HIT;
else
req_op <= OP_STORE_MISS;
end if;
else
if is_hit then
req_op <= OP_LOAD_HIT;
else
req_op <= OP_LOAD_MISS;
end if;
end if;
end if;
req_hit_way <= hit_way;
end process;
--
-- Store queue
--
-- For now, queue up to 16 stores
store_queue: entity work.sync_fifo
generic map (
DEPTH => STOREQ_DEPTH,
WIDTH => STOREQ_BITS
)
port map (
clk => system_clk,
reset => system_reset,
rd_ready => storeq_rd_ready,
rd_valid => storeq_rd_valid,
rd_data => storeq_rd_data,
wr_ready => storeq_wr_ready,
wr_valid => storeq_wr_valid,
wr_data => storeq_wr_data
);
storeq_control : process(all)
variable stq_data : wishbone_data_type;
variable stq_sel : wishbone_sel_type;
variable stq_wsl : std_ulogic_vector(WB_WSEL_BITS-1 downto 0);
begin
storeq_wr_data <= wb_req.dat & wb_req.sel &
wb_req.adr(WB_WSEL_BITS-1 downto 0);
-- Only queue stores if we can also send a command
if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
storeq_wr_valid <= user_port0_cmd_ready;
else
storeq_wr_valid <= '0';
end if;
-- Store signals (hard wired for 64-bit wishbone at the moment)
stq_data := storeq_rd_data(storeq_rd_data'left downto WBSL+WB_WSEL_BITS);
stq_sel := storeq_rd_data(WBSL+WB_WSEL_BITS-1 downto WB_WSEL_BITS);
stq_wsl := storeq_rd_data(WB_WSEL_BITS-1 downto 0);
for i in 0 to WB_WORD_COUNT-1 loop
if to_integer(unsigned(stq_wsl)) = i then
user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= stq_sel;
else
user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00";
end if;
user_port0_wdata_data(WBL*(i+1)-1 downto WBL*i) <= stq_data;
end loop;
-- Note: Current litedram ignores user_port0_wdata_valid. We
-- must make sure to always have the data available at the
-- output of the store queue when we send the write command.
--
-- Thankfully this is always the case with this design.
--
user_port0_wdata_valid <= storeq_rd_valid;
storeq_rd_ready <= user_port0_wdata_ready;
if TRACE then
if rising_edge(system_clk) then
if req_op = OP_STORE_HIT then
report "Store hit to:" &
to_hstring(wb_req.adr(DRAM_ABITS downto 0) & "000") &
" data:" & to_hstring(req_wdata) &
" we:" & to_hstring(req_we) &
" V:" & std_ulogic'image(user_port0_cmd_ready);
else
report "Store miss to:" &
to_hstring(wb_req.adr(DRAM_ABITS downto 0) & "000") &
" data:" & to_hstring(req_wdata) &
" we:" & to_hstring(req_we) &
" V:" & std_ulogic'image(user_port0_cmd_ready);
end if;
if storeq_wr_valid = '1' and storeq_wr_ready = '1' then
report "storeq push " & to_hstring(storeq_wr_data);
end if;
if storeq_rd_valid = '1' and storeq_rd_ready = '1' then
report "storeq pop " & to_hstring(storeq_rd_data);
end if;
end if;
end if;
end process;
-- LiteDRAM command mux
dram_commands: process(all)
begin
if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
-- For stores, forward signals directly. Only send command if
-- the FIFO can accept a store.
user_port0_cmd_addr <= wb_req.adr(DRAM_ABITS + ROW_OFF_BITS - wishbone_log2_width - 1 downto
ROW_OFF_BITS - wishbone_log2_width);
user_port0_cmd_we <= '1';
user_port0_cmd_valid <= storeq_wr_ready;
else
-- For loads, we route via a latch controlled by the refill machine
user_port0_cmd_addr <= refill_cmd_addr;
user_port0_cmd_valid <= refill_cmd_valid;
user_port0_cmd_we <= '0';
end if;
-- Note: litedram ignores this signal and assumes we are
-- always ready to accept read data.
user_port0_rdata_ready <= '1'; -- Always 1
end process;
-- LiteDRAM refill machine
--
-- This handles the cache line refills
--
refill_machine : process(system_clk)
variable tagset : cache_tags_set_t;
variable cmds_done : boolean;
variable wait_qdrain : boolean;
begin
if rising_edge(system_clk) then
-- On reset, clear all valid bits to force misses
if system_reset = '1' then
for i in index_t loop
cache_valids(i) <= (others => '0');
end loop;
state <= IDLE;
refill_cmd_valid <= '0';
else
-- Main state machine
case state is
when IDLE =>
assert refill_cmd_valid = '0' report "refill cmd valid in IDLE state !"
severity failure;
-- Reset per-row valid flags, only used in WAIT_ACK
for i in 0 to ROW_PER_LINE - 1 loop
refill_rows_vlid(i) <= '0';
end loop;
-- If NO_LS_OVERLAP is set, disallow a load miss if the store
-- queue still has data in it.
wait_qdrain := false;
if NO_LS_OVERLAP then
wait_qdrain := storeq_rd_valid = '1';
end if;
-- We need to read a cache line
if req_op = OP_LOAD_MISS and not wait_qdrain then
-- Grab way to replace
refill_way <= to_integer(unsigned(plru_victim(req_index)));
-- Keep track of our index and way for subsequent stores
refill_index <= req_index;
refill_row <= get_row(req_laddr);
refill_end_row <= get_row_of_line(get_row(req_laddr)) - 1;
-- Prep for first DRAM read
--
-- XXX TODO: We could start a cycle early here by using
-- combo logic to generate the first command in
-- "dram_commands". In fact, we could make refill_cmd_addr
-- only contain the "counter" bits and wire it with the
-- other bits from req_laddr.
refill_cmd_addr <= req_laddr(DRAM_ABITS+ROW_OFF_BITS-1 downto ROW_OFF_BITS);
refill_cmd_valid <= '1';
if TRACE then
report "refill addr " & to_hstring(req_laddr);
end if;
-- Track that we had one request sent
state <= REFILL_CLR_TAG;
end if;
when REFILL_CLR_TAG | REFILL_WAIT_ACK =>
-- Delayed tag clearing to help timing on PLRU output
if state = REFILL_CLR_TAG then
-- Force misses on that way while refilling that line
cache_valids(req_index)(refill_way) <= '0';
-- Store new tag in selected way
for i in 0 to NUM_WAYS-1 loop
if i = refill_way then
tagset := cache_tags(refill_index);
write_tag(i, tagset, req_tag);
cache_tags(refill_index) <= tagset;
end if;
end loop;
state <= REFILL_WAIT_ACK;
end if;
-- Commands are all sent if user_port0_cmd_valid is 0
cmds_done := refill_cmd_valid = '0';
-- If we are still sending requests, was one accepted ?
if user_port0_cmd_ready = '1' and not cmds_done then
-- That was the last word ? We are done sending. Clear
-- command valid and set cmds_done so we can handle an
-- eventual last ack on the same cycle.
--
if TRACE then
report "got refill cmd ack !";
end if;
if is_last_row_addr(refill_cmd_addr, refill_end_row) then
refill_cmd_valid <= '0';
cmds_done := true;
if TRACE then
report "all refill cmds done !";
end if;
else
-- Calculate the next row address
refill_cmd_addr <= next_row_addr(refill_cmd_addr);
if TRACE then
report "refill addr " &
to_hstring(next_row_addr(refill_cmd_addr));
end if;
end if;
end if;
-- Incoming read data processing
if user_port0_rdata_valid = '1' then
if TRACE then
report "got refill data ack !";
end if;
-- Mark partial line valid
refill_rows_vlid(refill_row mod ROW_PER_LINE) <= '1';
-- Check for completion
if cmds_done and is_last_row(refill_row, refill_end_row) then
if TRACE then
report "all refill data done !";
end if;
-- Cache line is now valid
cache_valids(refill_index)(refill_way) <= '1';
-- We are done
state <= IDLE;
end if;
-- Increment store row counter
refill_row <= next_row(refill_row);
end if;
end case;
end if;
end if;
end process;
may_trace: if LITEDRAM_TRACE generate
component litedram_trace_stub
end component;
begin
litedram_trace: litedram_trace_stub;
end generate;
litedram: litedram_core
port map(
clk => clk_in,
rst => rst,
pll_locked => pll_locked,
ddram_a => ddram_a,
ddram_ba => ddram_ba,
ddram_ras_n => ddram_ras_n,
ddram_cas_n => ddram_cas_n,
ddram_we_n => ddram_we_n,
ddram_cs_n => ddram_cs_n,
ddram_dm => ddram_dm,
ddram_dq => ddram_dq,
ddram_dqs_p => ddram_dqs_p,
ddram_dqs_n => ddram_dqs_n,
ddram_clk_p => ddram_clk_p,
ddram_clk_n => ddram_clk_n,
ddram_cke => ddram_cke,
ddram_odt => ddram_odt,
ddram_reset_n => ddram_reset_n,
init_done => init_done,
init_error => init_error,
user_clk => system_clk,
user_rst => system_reset,
wb_ctrl_adr => wb_ctrl_adr,
wb_ctrl_dat_w => wb_ctrl_dat_w,
wb_ctrl_dat_r => wb_ctrl_dat_r,
wb_ctrl_sel => wb_ctrl_sel,
wb_ctrl_cyc => wb_ctrl_cyc,
wb_ctrl_stb => wb_ctrl_stb,
wb_ctrl_ack => wb_ctrl_ack,
wb_ctrl_we => wb_ctrl_we,
wb_ctrl_cti => "000",
wb_ctrl_bte => "00",
wb_ctrl_err => open,
user_port_native_0_cmd_valid => user_port0_cmd_valid,
user_port_native_0_cmd_ready => user_port0_cmd_ready,
user_port_native_0_cmd_we => user_port0_cmd_we,
user_port_native_0_cmd_addr => user_port0_cmd_addr,
user_port_native_0_wdata_valid => user_port0_wdata_valid,
user_port_native_0_wdata_ready => user_port0_wdata_ready,
user_port_native_0_wdata_we => user_port0_wdata_we,
user_port_native_0_wdata_data => user_port0_wdata_data,
user_port_native_0_rdata_valid => user_port0_rdata_valid,
user_port_native_0_rdata_ready => user_port0_rdata_ready,
user_port_native_0_rdata_data => user_port0_rdata_data
);
end architecture behaviour;
|
<gh_stars>100-1000
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: <NAME>
-- <NAME>
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_global.all;
use PoC.sim_types.all;
use PoC.sim_protected.all;
package simulation is
-- Legacy interface for pre VHDL-2002
-- ===========================================================================
-- prepared aliases, if GHDL gets the aliases fixed. Reported on 08.02.2015 as Issue #38
-- alias simmInitialize is globalSimulationStatus.initialize[NATURAL, TIME];
-- alias simmFinalize is globalSimulationStatus.finalize[];
-- alias simmCreateTest is globalSimulationStatus.createTest[STRING return T_SIM_TEST_ID];
-- alias simmFinalizeTest is globalSimulationStatus.finalizeTest[T_SIM_TEST_ID];
-- alias simmRegisterProcess is globalSimulationStatus.registerProcess[T_SIM_TEST_ID, STRING, BOOLEAN return T_SIM_PROCESS_ID];
-- alias simmRegisterProcess is globalSimulationStatus.registerProcess[STRING, BOOLEAN return T_SIM_PROCESS_ID];
-- alias simmDeactivateProcess is globalSimulationStatus.deactivateProcess[T_SIM_PROCESS_ID];
-- alias simmIsStopped is globalSimulationStatus.isStopped[T_SIM_TEST_ID return BOOLEAN];
-- alias simmIsFinalized is globalSimulationStatus.isFinalized[T_SIM_TEST_ID return BOOLEAN];
-- alias simmIsAllFinalized is globalSimulationStatus.isAllFinalized [return BOOLEAN];
-- alias simmAssertion is globalSimulationStatus.assertion[BOOLEAN, STRING];
-- alias simmFail is globalSimulationStatus.fail[STRING];
-- alias simmWriteMessage is globalSimulationStatus.writeMessage[STRING];
procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high);
procedure simFinalize;
impure function simCreateTest(Name : string) return T_SIM_TEST_ID;
procedure simFinalizeTest(constant TestID : T_SIM_TEST_ID);
impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID;
impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID);
impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean;
impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean;
impure function simIsAllFinalized return boolean;
procedure simAssertion(cond : in boolean; Message : in string := "");
procedure simFail(Message : in string := "");
procedure simWriteMessage(Message : in string := "");
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package;
package body simulation is
-- legacy procedures
-- ===========================================================================
-- TODO: undocumented group
procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is
begin
globalSimulationStatus.initialize(MaxAssertFailures, MaxSimulationRuntime);
if C_SIM_VERBOSE then report "simInitialize:" severity NOTE; end if;
if (MaxSimulationRuntime /= time'high) then
wait for MaxSimulationRuntime;
report "simInitialize: TIMEOUT" severity ERROR;
globalSimulationStatus.finalize;
end if;
end procedure;
procedure simFinalize is
begin
globalSimulationStatus.finalize;
end procedure;
impure function simCreateTest(Name : string) return T_SIM_TEST_ID is
begin
return globalSimulationStatus.createTest(Name);
end function;
procedure simFinalizeTest(constant TestID : T_SIM_TEST_ID) is
begin
globalSimulationStatus.finalizeTest(TestID);
end procedure;
impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is
begin
return globalSimulationStatus.registerProcess(Name, IsLowPriority);
end function;
impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is
begin
return globalSimulationStatus.registerProcess(TestID, Name, IsLowPriority);
end function;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID) is
begin
globalSimulationStatus.deactivateProcess(ProcID);
end procedure;
impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is
begin
return globalSimulationStatus.isStopped(TestID);
end function;
impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is
begin
return globalSimulationStatus.isFinalized(TestID);
end function;
impure function simIsAllFinalized return boolean is
begin
return globalSimulationStatus.isAllFinalized;
end function;
-- TODO: undocumented group
procedure simWriteMessage(Message : in string := "") is
begin
globalSimulationStatus.writeMessage(Message);
end procedure;
procedure simFail(Message : in string := "") is
begin
globalSimulationStatus.fail(Message);
end procedure;
procedure simAssertion(cond : in boolean; Message : in string := "") is
begin
globalSimulationStatus.assertion(cond, Message);
end procedure;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
|
<reponame>maanjum95/VHDL_System_Design_Lab<filename>submit/rcs1/tb_mux2x1.vhd
--------------------------------------------------------------------------------
-- Engineer: <NAME>
--
-- Create Date: 10:53:27 12/05/2019
-- Module Name: /nas/ei/share/TUEIEDA/LabHDL/2019w/ge46bod/submit/rcs1/tb_mux2x1.vhd
-- Project Name: idea_rcs1
--
-- VHDL Test Bench Created by ISE for module: mux2x1
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mux2x1 IS
END tb_mux2x1;
ARCHITECTURE behavior OF tb_mux2x1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux2x1
PORT(
D0 : IN std_logic_vector(15 downto 0);
D1 : IN std_logic_vector(15 downto 0);
S : IN std_logic;
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal D0 : std_logic_vector(15 downto 0) := (others => '0');
signal D1 : std_logic_vector(15 downto 0) := (others => '0');
signal S : std_logic := '0';
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux2x1 PORT MAP (
D0 => D0,
D1 => D1,
S => S,
O => O
);
testing: process is
begin
-- Setup
D0 <= x"0000";
D1 <= x"0000";
S <= '0';
wait for 10ns;
-- 1
D0 <= x"1234";
wait for 10ns;
-- 2
D0 <= x"4321";
wait for 10ns;
-- 3
D1 <= x"ABCD";
wait for 10ns;
-- 4
S <= '1';
wait for 10ns;
-- 5
D1 <= x"DCBA";
D0 <= x"1234";
wait for 10ns;
-- 6
S <= '0';
wait for 10ns;
-- 7
S <= 'X';
wait for 10ns;
end process testing;
END;
|
<reponame>daxadal/computer-102
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity maquina_divisor is
generic (
N: natural := 6;
M: natural := 3
);
port (
clk : in std_logic;
reset : in std_logic;
divisor : in std_logic_vector(M-1 downto 0); -- dividendo
dividendo : in std_logic_vector(N-1 downto 0); -- divisor
inicio : in std_logic;
ready : out std_logic;
cociente : out std_logic_vector(N-1 downto 0) -- cociente
);
end maquina_divisor;
architecture Behavioral of maquina_divisor is
type estados is (S0, carga, resta, comp_resta, cociente0, cociente1, sig_div, comp_fin);
signal est_act, est_sig: estados;
signal rdn, rds, rdn_sig, rds_sig: std_logic_vector(N downto 0); -- entrada y salida de registros dividendo y divisor
signal rc, rc_sig: std_logic_vector(N-1 downto 0); -- entrada y salida del registro cociente
signal rk, rk_sig: std_logic_vector(N-M downto 0); -- entrada y salida del registro incremento
signal ceros: std_logic_vector(N-M-1 downto 0);
begin
cociente <= rc;
ceros <= (others=>'0');
registros: process (reset, clk)
begin
if reset = '1' then
est_act <= S0;
elsif clk'event and clk = '1' then
est_act <= est_sig;
rdn <= rdn_sig;
rds <= rds_sig;
rc <= rc_sig;
rk <= rk_sig;
end if;
end process registros;
comb: process (est_act, inicio, rdn, rds, rc, rk, dividendo, divisor)
begin
case est_act is
when S0 =>
ready <= '1';
rdn_sig <= rdn;
rds_sig <= rds;
rc_sig <= rc;
rk_sig <= rk;
if inicio = '1' then
est_sig <= carga;
else
est_sig <= S0;
end if;
when carga =>
ready <= '0';
rdn_sig <= '0' & dividendo;
rds_sig <= '0' & divisor & ceros;
rc_sig <= (others => '0');
rk_sig <= (others => '0');
est_sig <= resta;
when resta =>
ready <= '0';
rdn_sig <= rdn - rds;
rds_sig <= rds;
rc_sig <= rc;
rk_sig <= rk;
est_sig <= comp_resta;
when comp_resta =>
ready <= '0';
rdn_sig <= rdn;
rds_sig <= rds;
rc_sig <= rc;
rk_sig <= rk;
if rdn(N-1) = '1' then
est_sig <= cociente0;
else
est_sig <= cociente1;
end if;
when cociente0 =>
ready <= '0';
rdn_sig <= rdn + rds;
rds_sig <= rds;
rc_sig <= rc(N-2 downto 0) & '0';
rk_sig <= rk;
est_sig <= sig_div;
when cociente1 =>
ready <= '0';
rdn_sig <= rdn;
rds_sig <= rds;
rc_sig <= rc(N-2 downto 0) & '1';
rk_sig <= rk;
est_sig <= sig_div;
when sig_div =>
ready <= '0';
rdn_sig <= rdn;
rds_sig <= '0' & rds(N downto 1);
rc_sig <= rc;
rk_sig <= rk + 1;
est_sig <= comp_fin;
when comp_fin =>
ready <= '0';
rdn_sig <= rdn;
rds_sig <= rds;
rc_sig <= rc;
rk_sig <= rk;
if rk <= N-M then
est_sig <= resta;
else
est_sig <= S0;
end if;
end case;
end process comb;
end Behavioral;
|
<filename>SysPy_ver/Python_script/paramsocs/Leon3_comps_Gill_top/Leon3_comps/libs/gaisler/ata/atactrl_nodma.vhd
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2010, <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atactrl_nodma
-- File: atactrl_nodma.vhd
-- Author: <NAME>, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.ata.all;
library opencores;
use opencores.occomp.all;
entity atactrl_nodma is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cfo : out cf_out_type;
-- ATA signals
ddin : in std_logic_vector(15 downto 0);
iordy : in std_logic;
intrq : in std_logic;
ata_resetn : out std_logic;
ddout : out std_logic_vector(15 downto 0);
ddoe : out std_logic;
da : out std_logic_vector(2 downto 0);
cs0n : out std_logic;
cs1n : out std_logic;
diorn : out std_logic;
diown : out std_logic;
dmack : out std_logic
);
end;
architecture rtl of atactrl_nodma is
-- Device ID
constant DeviceId : integer := 2;
constant RevisionNo : integer := 0;
constant VERSION : integer := 0;
component ocidec2_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0)
);
end component;
-- asynchronous reset signal
signal arst_signal : std_logic;
-- primary address decoder
signal PIOsel : std_logic; -- controller select, IDE devices select
-- control signal
signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic;
-- compatible mode timing
signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : std_logic_vector(7 downto 0);
signal PIO_cmdport_IORDYen : std_logic;
-- data port0 timing
signal PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc : std_logic_vector(7 downto 0);
signal PIO_dport0_IORDYen : std_logic;
-- data port1 timing
signal PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc : std_logic_vector(7 downto 0);
signal PIO_dport1_IORDYen : std_logic;
signal PIOack : std_logic;
signal PIOq : std_logic_vector(15 downto 0);
signal PIOa : std_logic_vector(3 downto 0);
signal PIOd : std_logic_vector(15 downto 0);
signal PIOwe : std_logic;
signal irq : std_logic; -- ATA bus IRQ signal
signal reset : std_logic;
signal gnd,vcc : std_logic;
signal gnd32 : std_logic_vector(31 downto 0);
begin
gnd <= '0';vcc <= '1'; gnd32 <= zero32;
-- generate asynchronous reset level
arst_signal <= arst;-- xor ARST_LVL;
reset <= not rst;
dmack <= vcc; -- Disable DMA
-- Generate CompactFlash signals
--cfo.power connected to bit 31 of the control register
cfo.atasel <= gnd;
cfo.we <= vcc;
cfo.csel <= gnd;
cfo.da <= (others => gnd);
u0: ocidec2_amba_slave
generic map(
hindex => hindex,
haddr => haddr,
hmask => hmask,
pirq => pirq,
DeviceID => DeviceID,
RevisionNo => RevisionNo,
-- PIO mode 0 settings
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
-- Multiword DMA mode 0 settings
-- OCIDEC-1 does not support DMA, set registers to zero
DMA_mode0_Tm => 0,
DMA_mode0_Td => 0,
DMA_mode0_Teoc => 0
)
port map(
arst => arst_signal,
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
cf_power => cfo.power, -- power switch for compactflash
-- PIO control input
-- PIOtip is only asserted during a PIO transfer (No shit! ;)
-- Since it is impossible to read the status register and access the PIO registers at the same time
-- this bit is useless (besides using-up resources)
PIOtip => gnd,
PIOack => PIOack,
PIOq => PIOq,
PIOsel => PIOsel,
PIOpp_full => gnd, -- OCIDEC-1 does not support PIO-write PingPong, negate signal
irq => irq,
PIOa => PIOa,
PIOd => PIOd,
PIOwe => PIOwe,
-- DMA control inputs (negate all of them)
DMAtip => gnd,
DMAack => gnd,
DMARxEmpty => gnd,
DMATxFull => gnd,
DMA_dmarq => gnd,
DMAq => gnd32,
-- outputs
-- control register outputs
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
-- CMD port timing registers
PIO_cmdport_T1 => PIO_cmdport_T1,
PIO_cmdport_T2 => PIO_cmdport_T2,
PIO_cmdport_T4 => PIO_cmdport_T4,
PIO_cmdport_Teoc => PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => PIO_cmdport_IORDYen,
-- data-port0 timing registers
PIO_dport0_T1 => PIO_dport0_T1,
PIO_dport0_T2 => PIO_dport0_T2,
PIO_dport0_T4 => PIO_dport0_T4,
PIO_dport0_Teoc => PIO_dport0_Teoc,
PIO_dport0_IORDYen => PIO_dport0_IORDYen,
-- data-port1 timing registers
PIO_dport1_T1 => PIO_dport1_T1,
PIO_dport1_T2 => PIO_dport1_T2,
PIO_dport1_T4 => PIO_dport1_T4,
PIO_dport1_Teoc => PIO_dport1_Teoc,
PIO_dport1_IORDYen => PIO_dport1_IORDYen
);
u1: ocidec2_controller
generic map(
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map(
clk => clk,
nReset => arst_signal,
rst => reset,
irq => irq,
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
cmdport_T1 => PIO_cmdport_T1,
cmdport_T2 => PIO_cmdport_T2,
cmdport_T4 => PIO_cmdport_T4,
cmdport_Teoc => PIO_cmdport_Teoc,
cmdport_IORDYen => PIO_cmdport_IORDYen,
dport0_T1 => PIO_dport0_T1,
dport0_T2 => PIO_dport0_T2,
dport0_T4 => PIO_dport0_T4,
dport0_Teoc => PIO_dport0_Teoc,
dport0_IORDYen => PIO_dport0_IORDYen,
dport1_T1 => PIO_dport1_T1,
dport1_T2 => PIO_dport1_T2,
dport1_T4 => PIO_dport1_T4,
dport1_Teoc => PIO_dport1_Teoc,
dport1_IORDYen => PIO_dport1_IORDYen,
PIOreq => PIOsel,
PIOack => PIOack,
PIOa => PIOa,
PIOd => PIOd,
PIOq => PIOq,
PIOwe => PIOwe,
RESETn => ata_resetn,
DDi => ddin,
DDo => ddout,
DDoe => ddoe,
DA => da,
CS0n => cs0n,
CS1n => cs1n,
DIORn => diorn,
DIOWn => diown,
IORDY => iordy,
INTRQ => intrq
);
-- pragma translate_off
bootmsg : report_version
generic map ("atactrl" & tost(hindex) &
": ATA controller rev " & tost(VERSION) & ", no DMA, irq " & tost(pirq));
-- pragma translate_on
end;
|
#include <orcapp_head>
library ieee;
use ieee.std_logic_1164.all;
entity USERNAME_top is port (
--INPUTS
clk : in std_logic; -- system clock
rstn : in std_logic; -- system reset
--OUTPUTS
#ifdef CLKEN
ce : in std_logic; -- clock enable
#endif
#ifdef SYNCRST
sr : in std_logic; -- synchronous reset
#endif
#ifdef BYPASSEN
gcen : in std_logic; -- gamma enable
#endif
inpvalid : in std_logic; -- input data valid signal
din0 : in std_logic_vector(DATA0_WIDTH-1 downto 0); -- first input color plane
#ifdef LUT0WRITEPORT
lut0wren : in std_logic; -- first color plane LUT write enable
lut0val : in std_logic_vector(DATA0_WIDTH-1 downto 0); -- first color plane LUT write value
#endif
#ifdef INPUT_SERIAL
cpsel : in std_logic_vector(CPSEL_WIDTH-1 downto 0); -- color plane select for the inputs
#endif
#ifndef INPUT_SERIAL
#ifdef NUMCP2
din1 : in std_logic_vector(DATA1_WIDTH-1 downto 0); -- second input color plane
#ifdef LUT1WRITEPORT
lut1wren : in std_logic; -- second color plane LUT write enable
lut1val : in std_logic_vector(DATA1_WIDTH-1 downto 0); -- second color plane LUT write value
#endif
#endif
#ifdef NUMCP3
din2 : in std_logic_vector(DATA2_WIDTH-1 downto 0); -- third input color plane
#ifdef LUT2WRITEPORT
lut2wren : in std_logic; -- third color plane LUT write enable
lut2val : in std_logic_vector(DATA2_WIDTH-1 downto 0); -- third color plane LUT write value
#endif
#endif
#endif
--=====OUTPUTS
#ifdef BYPASSEN
gcvalid : out std_logic; -- valid gamma correction output indicator
#endif
outvalid : out std_logic; -- output data valid signal
#ifdef INPUT_SERIAL
cpout : out std_logic_vector(CPSEL_WIDTH-1 downto 0); -- color plane select for the outputs
#endif
#ifndef INPUT_SERIAL
#ifdef NUMCP2
dout1: out std_logic_vector(DATA1_WIDTH-1 downto 0); -- second output color plane
#endif
#ifdef NUMCP3
dout2: out std_logic_vector(DATA2_WIDTH-1 downto 0); -- third output color plane
#endif
#endif
dout0 : out std_logic_vector(DATA0_WIDTH-1 downto 0) -- first output color plane
);
end USERNAME_top;
architecture arch of USERNAME_top is
#ifdef DEVICE_ECP5
--component ecp5_pll
--port (
-- CLKI : in std_logic;
-- RST : in std_logic;
-- CLKOP : out std_logic;
-- LOCK : out std_logic
--);
--end component;
#endif
#ifdef DEVICE_ECP3
--component ecp3_pll
-- CLK : in std_logic;
-- RESET : in std_logic;
-- CLKOP : out std_logic;
-- LOCK : out std_logic
--);
--end component;
#endif
#ifdef DEVICE_XP2
--component xp2_pll
-- CLK : in std_logic;
-- RESET : in std_logic;
-- CLKOP : out std_logic;
-- LOCK : out std_logic
--);
--end component;
#endif
component USERNAME
port (
--INPUTS
clk : in std_logic; -- system clock
rstn : in std_logic; -- system reset
--OUTPUTS
#ifdef CLKEN
ce : in std_logic; -- clock enable
#endif
#ifdef SYNCRST
sr : in std_logic; -- synchronous reset
#endif
#ifdef BYPASSEN
gcen : in std_logic; -- gamma enable
#endif
inpvalid : in std_logic; -- input data valid signal
din0 : in std_logic_vector(DATA0_WIDTH-1 downto 0); -- first input color plane
#ifdef LUT0WRITEPORT
lut0wren : in std_logic; -- first color plane LUT write enable
lut0val : in std_logic_vector(DATA0_WIDTH-1 downto 0); -- first color plane LUT write value
#endif
#ifdef INPUT_SERIAL
cpsel : in std_logic_vector(CPSEL_WIDTH-1 downto 0); -- color plane select for the inputs
#endif
#ifndef INPUT_SERIAL
#ifdef NUMCP2
din1 : in std_logic_vector(DATA1_WIDTH-1 downto 0); -- second input color plane
#ifdef LUT1WRITEPORT
lut1wren : in std_logic; -- second color plane LUT write enable
lut1val : in std_logic_vector(DATA1_WIDTH-1 downto 0); -- second color plane LUT write value
#endif
#endif
#ifdef NUMCP3
din2 : in std_logic_vector(DATA2_WIDTH-1 downto 0); -- third input color plane
#ifdef LUT2WRITEPORT
lut2wren : in std_logic; -- third color plane LUT write enable
lut2val : in std_logic_vector(DATA2_WIDTH-1 downto 0); -- third color plane LUT write value
#endif
#endif
#endif
--=====OUTPUTS
#ifdef BYPASSEN
gcvalid : out std_logic; -- valid gamma correction output indicator
#endif
outvalid : out std_logic; -- output data valid signal
#ifdef INPUT_SERIAL
cpout : out std_logic_vector(CPSEL_WIDTH-1 downto 0); -- color plane select for the outputs
#endif
#ifndef INPUT_SERIAL
#ifdef NUMCP2
dout1: out std_logic_vector(DATA1_WIDTH-1 downto 0); -- second output color plane
#endif
#ifdef NUMCP3
dout2: out std_logic_vector(DATA2_WIDTH-1 downto 0); -- third output color plane
#endif
#endif
dout0 : out std_logic_vector(DATA0_WIDTH-1 downto 0) -- first output color plane
);
end component;
signal clkin : std_logic;
begin
--Add PLL Instance for timing simulation---------
#ifdef DEVICE_ECP5
--u1_pll : ecp5_pll
-- port map (
-- CLK => clk,
-- RESET => '0',
-- CLKOP => clkin,
-- LOCK => open
-- );
#endif
#ifdef DEVICE_ECP3
--u1_pll : ecp3_pll
-- port map (
-- CLKI => clk,
-- RST => '0',
-- CLKOP => clkin,
-- LOCK => open
-- );
#endif
#ifdef DEVICE_XP2
--u1_pll : xp2_pll
-- port map (
-- CLKI => clk,
-- RST => '0',
-- CLKOP => clkin,
-- LOCK => open
-- );
#endif
u1_USERNAME : USERNAME
port map (
-- INPUTS
-- clk => clkin, -- system clock (for timing simulation)
clk => clk, -- system clock
rstn => rstn, -- system reset
#ifdef CLKEN
ce => ce, -- clock enable
#endif
#ifdef SYNCRST
sr => sr, -- synchronous reset
#endif
#ifdef BYPASSEN
gcen => gcen, -- gamma enable
#endif
inpvalid => inpvalid, -- input data valid signal
din0 => din0, -- first input color plane
#ifdef LUT0WRITEPORT
lut0wren => lut0wren, -- first color plane LUT write enable
lut0val => lut0val , -- first color plane LUT write value
#endif
#ifdef INPUT_SERIAL
cpsel => cpsel, -- color plane select for the inputs
#endif
#ifndef INPUT_SERIAL
#ifdef NUMCP2
din1 => din1, -- second input color plane
#ifdef LUT1WRITEPORT
lut1wren=> lut1wren, -- second color plane LUT write enable
lut1val => lut1val, -- second color plane LUT write value
#endif
#endif
#ifdef NUMCP3
din2 => din2, -- third input color plane
#ifdef LUT2WRITEPORT
lut2wren=> lut2wren, -- third color plane LUT write enable
lut2val => lut2val, -- third color plane LUT write value
#endif
#endif
#endif
--=====OUTPUTS
#ifdef BYPASSEN
gcvalid => gcvalid, -- valid gamma correction output indicator
#endif
outvalid => outvalid, -- output data valid signal
#ifdef INPUT_SERIAL
cpout => cpout, -- color plane select for the outputs
#endif
#ifndef INPUT_SERIAL
#ifdef NUMCP2
dout1 => dout1, -- second output color plane
#endif
#ifdef NUMCP3
dout2 => dout2, -- third output color plane
#endif
#endif
dout0 => dout0 -- first output color plane
);
end arch;
|
<reponame>IceColors/E-piano<filename>epiano7.srcs/sources_1/imports/epiano7/RAM_Counter.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM_Counter is
generic(ADDR_WIDTH: integer := 10);
port(
clk, rst: in std_logic;
inc, clr: in std_logic;
addr: out std_logic_vector(ADDR_WIDTH-1 downto 0));
end RAM_Counter;
architecture arch of RAM_Counter is
signal r_reg, r_nxt: unsigned(ADDR_WIDTH-1 downto 0);
begin process(clk,rst)
begin
if rst='1' then
r_reg <= (others=>'0');
elsif(rising_edge(clk)) then
r_reg <= r_nxt;
end if;
end process;
r_nxt <= (others=>'0') when clr='1' else
r_reg+1 when inc='1' else
r_reg;
addr <= std_logic_vector(r_reg);
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.work_package.all;
entity top_module is
port (
clk_100mhz : in std_logic;
reset : in std_logic;
capture : in std_logic;
pause : in std_logic;
pause_en : in std_logic;
next_addr : in std_logic;
next_addr_dir : in std_logic;
next_index : in std_logic;
next_index_dir : in std_logic;
next_pixel : in std_logic;
next_pixel_ori : in std_logic;
next_pixel_dir : in std_logic;
threshold_nextval : in std_logic;
threshold_nextval_dir : in std_logic;
ov7670_sioc : out std_logic;
ov7670_siod : inout std_logic;
ov7670_pclk : in std_logic;
ov7670_xclk : out std_logic;
ov7670_vsync : in std_logic;
ov7670_href : in std_logic;
ov7670_data : in std_logic_vector(7 downto 0);
ov7670_reset_1 : out std_logic;
ov7670_pwdn : out std_logic;
vga_r : out std_logic_vector(2 downto 0);
vga_g : out std_logic_vector(2 downto 0);
vga_b : out std_logic_vector(2 downto 1);
vga_hs : out std_logic;
vga_vs : out std_logic;
config_finished : out std_logic
);
end top_module;
architecture behavioral of top_module is
component anpr_module is
port (
clk_100mhz : in std_logic;
reset : in std_logic;
capture : in std_logic;
pause : in std_logic;
pause_en : in std_logic;
next_addr : in std_logic;
next_addr_dir : in std_logic;
threshold_nextval : in std_logic;
threshold_nextval_dir : in std_logic;
ov7670_vsync : in std_logic;
state_capture_image : out std_logic;
cntx : out unsigned(9 downto 0);
cnty : out unsigned(8 downto 0);
ov7670_capture_ce_cntx : in std_logic;
ov7670_capture_r_acc : in std_logic;
ov7670_capture_dout1 : in std_logic_vector(2 downto 0);
ov7670_capture_we1 : in std_logic;
ov7670_capture_dout2 : in std_logic;
ov7670_capture_we2 : in std_logic;
ov7670_capture_finished : in std_logic;
vga_driver_addr1 : in std_logic_vector(16 downto 0);
vga_driver_din1 : out std_logic_vector(2 downto 0);
vga_driver_addr2 : in std_logic_vector(16 downto 0);
vga_driver_din2 : out std_logic;
vga_driver_addr_py1 : in std_logic_vector(7 downto 0);
vga_driver_din_py1 : out std_logic_vector(8 downto 0);
ym1 : out std_logic_vector(7 downto 0);
y0_1 : out std_logic_vector(7 downto 0);
y1_1 : out std_logic_vector(7 downto 0);
vga_driver_addr_px1 : in std_logic_vector(8 downto 0);
vga_driver_din_px1 : out std_logic_vector(7 downto 0);
xm1 : out std_logic_vector(8 downto 0);
xmw1 : out std_logic_vector(8 downto 0);
x0_1 : out std_logic_vector(8 downto 0);
x1_1 : out std_logic_vector(8 downto 0);
vga_driver_addr_px2 : in std_logic_vector(8 downto 0);
vga_driver_din_px2 : out std_logic_vector(7 downto 0);
vga_driver_addr_py2 : in std_logic_vector(11 downto 0);
vga_driver_din_py2 : out std_logic_vector(8 downto 0);
vga_driver_ym2 : out std_logic_vector(7 downto 0);
bounds_addr : out std_logic_vector(3 downto 0);
bounds_count : out std_logic_vector(3 downto 0);
vga_driver_addr_b : in std_logic_vector(3 downto 0);
vga_driver_din_bx0 : out std_logic_vector(8 downto 0);
vga_driver_din_bx1 : out std_logic_vector(8 downto 0);
vga_driver_din_by0 : out std_logic_vector(7 downto 0);
vga_driver_din_by1 : out std_logic_vector(7 downto 0);
vga_driver_addr_f : in std_logic_vector(9 downto 0);
vga_driver_din_f : out std_logic_vector(15 downto 0);
vga_driver_addr_c : in std_logic_vector(3 downto 0);
vga_driver_din_c : out std_logic_vector(5 downto 0);
vga_driver_addr_ci : in std_logic_vector(7 downto 0);
vga_driver_din_ci : out std_logic_vector(15 downto 0);
vga_driver_addr_d : in std_logic_vector(8 downto 0);
vga_driver_din_d : out std_logic_vector(8 downto 0);
state : out state_type;
ce : out std_logic;
threshold : out std_logic_vector(9 downto 0);
processing_time : out std_logic_vector(31 downto 0);
capture_time : out std_logic_vector(31 downto 0);
icr_btn : in std_logic
);
end component;
component ov7670_capture is
port (
clk_100mhz : in std_logic;
pclk : in std_logic;
reset : in std_logic;
vsync : in std_logic;
href : in std_logic;
capture : in std_logic;
threshold : in std_logic_vector(9 downto 0);
din : in std_logic_vector(7 downto 0);
cntx : in unsigned(9 downto 0);
cnty : in unsigned(8 downto 0);
ce_cntx : out std_logic;
r_acc : out std_logic;
dout1 : out std_logic_vector(2 downto 0);
we1 : out std_logic;
dout2 : out std_logic;
we2 : out std_logic;
finished : out std_logic;
pixel_clock : out std_logic_vector(7 downto 0)
);
end component;
component ov7670_controller is
port (
clk_100mhz : in std_logic;
sccb_busy : in std_logic;
start_config : in std_logic;
reset : in std_logic;
send : out std_logic;
rw : out std_logic;
addr : out std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0);
busy : out std_logic;
config_finished : out std_logic
);
end component;
component ov7670_sccb is
port (
clk_100mhz : in std_logic;
reset : in std_logic;
pwdn_trig : in std_logic;
send : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(7 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
sioc : out std_logic;
siod : inout std_logic;
busy : out std_logic;
pwdn : out std_logic
);
end component;
component vga_driver is
port (
clk_100mhz : in std_logic;
reset : in std_logic;
next_index : in std_logic;
next_index_dir : in std_logic;
next_pixel : in std_logic;
next_pixel_ori : in std_logic;
next_pixel_dir : in std_logic;
r : out std_logic_vector(2 downto 0);
g : out std_logic_vector(2 downto 0);
b : out std_logic_vector(2 downto 1);
addr1 : out std_logic_vector(16 downto 0);
din1 : in std_logic_vector(2 downto 0);
addr2 : out std_logic_vector(16 downto 0);
din2 : in std_logic;
addr_py1 : out std_logic_vector(7 downto 0);
din_py1 : in std_logic_vector(8 downto 0);
ym1 : in std_logic_vector(7 downto 0);
y0_1 : in std_logic_vector(7 downto 0);
y1_1 : in std_logic_vector(7 downto 0);
addr_px1 : out std_logic_vector(8 downto 0);
din_px1 : in std_logic_vector(7 downto 0);
xm1 : in std_logic_vector(8 downto 0);
xmw1 : in std_logic_vector(8 downto 0);
x0_1 : in std_logic_vector(8 downto 0);
x1_1 : in std_logic_vector(8 downto 0);
addr_px2 : out std_logic_vector(8 downto 0);
din_px2 : in std_logic_vector(7 downto 0);
addr_py2 : out std_logic_vector(11 downto 0);
din_py2 : in std_logic_vector(8 downto 0);
ym2 : in std_logic_vector(7 downto 0);
bounds_addr : in std_logic_vector(3 downto 0);
bounds_count : in std_logic_vector(3 downto 0);
addr_b : out std_logic_vector(3 downto 0);
din_bx0 : in std_logic_vector(8 downto 0);
din_bx1 : in std_logic_vector(8 downto 0);
din_by0 : in std_logic_vector(7 downto 0);
din_by1 : in std_logic_vector(7 downto 0);
addr_f : out std_logic_vector(9 downto 0);
din_f : in std_logic_vector(15 downto 0);
addr_c : out std_logic_vector(3 downto 0);
din_c : in std_logic_vector(5 downto 0);
addr_ci : out std_logic_vector(7 downto 0);
din_ci : in std_logic_vector(15 downto 0);
addr_d : out std_logic_vector(8 downto 0);
din_d : in std_logic_vector(8 downto 0);
state : in state_type;
ce : in std_logic;
capture : in std_logic;
threshold : in std_logic_vector(9 downto 0);
processing_time : in std_logic_vector(31 downto 0);
capture_time : in std_logic_vector(31 downto 0);
icr_btn : out std_logic;
pixel_clock : in std_logic_vector(7 downto 0);
hs : out std_logic;
vs : out std_logic;
active : out std_logic
);
end component;
signal ov7670_sccb_send : std_logic;
signal ov7670_sccb_rw : std_logic;
signal ov7670_sccb_addr : std_logic_vector(7 downto 0);
signal ov7670_sccb_din : std_logic_vector(7 downto 0);
signal ov7670_sccb_busy : std_logic;
signal start_config : std_logic;
signal ov7670_capture_ce_cntx : std_logic;
signal ov7670_capture_r_acc : std_logic;
signal ov7670_capture_dout1 : std_logic_vector(2 downto 0);
signal ov7670_capture_we1 : std_logic;
signal ov7670_capture_dout2 : std_logic;
signal ov7670_capture_we2 : std_logic;
signal ov7670_capture_finished : std_logic;
signal ov7670_controller_config_finished : std_logic;
signal ov7670_controller_busy : std_logic;
signal clk_25mhz : std_logic := '0';
signal clk_50mhz : std_logic := '0';
signal pixel_clock : std_logic_vector(7 downto 0);
signal state_capture_image : std_logic;
signal cntx : unsigned(9 downto 0);
signal cnty : unsigned(8 downto 0);
signal vga_driver_addr1 : std_logic_vector(16 downto 0);
signal vga_driver_din1 : std_logic_vector(2 downto 0);
signal vga_driver_addr2 : std_logic_vector(16 downto 0);
signal vga_driver_din2 : std_logic;
signal vga_driver_addr_py1 : std_logic_vector(7 downto 0);
signal vga_driver_din_py1 : std_logic_vector(8 downto 0);
signal ym1 : std_logic_vector(7 downto 0);
signal y0_1 : std_logic_vector(7 downto 0);
signal y1_1 : std_logic_vector(7 downto 0);
signal vga_driver_addr_px1 : std_logic_vector(8 downto 0);
signal vga_driver_din_px1 : std_logic_vector(7 downto 0);
signal xm1 : std_logic_vector(8 downto 0);
signal xmw1 : std_logic_vector(8 downto 0);
signal x0_1 : std_logic_vector(8 downto 0);
signal x1_1 : std_logic_vector(8 downto 0);
signal vga_driver_addr_px2 : std_logic_vector(8 downto 0);
signal vga_driver_din_px2 : std_logic_vector(7 downto 0);
signal vga_driver_addr_py2 : std_logic_vector(11 downto 0);
signal vga_driver_din_py2 : std_logic_vector(8 downto 0);
signal vga_driver_ym2 : std_logic_vector(7 downto 0);
signal bounds_addr : std_logic_vector(3 downto 0);
signal bounds_count : std_logic_vector(3 downto 0);
signal vga_driver_addr_b : std_logic_vector(3 downto 0);
signal vga_driver_din_bx0 : std_logic_vector(8 downto 0);
signal vga_driver_din_bx1 : std_logic_vector(8 downto 0);
signal vga_driver_din_by0 : std_logic_vector(7 downto 0);
signal vga_driver_din_by1 : std_logic_vector(7 downto 0);
signal vga_driver_addr_f : std_logic_vector(9 downto 0);
signal vga_driver_din_f : std_logic_vector(15 downto 0);
signal vga_driver_addr_c : std_logic_vector(3 downto 0);
signal vga_driver_din_c : std_logic_vector(5 downto 0);
signal vga_driver_addr_ci : std_logic_vector(7 downto 0);
signal vga_driver_din_ci : std_logic_vector(15 downto 0);
signal vga_driver_addr_d : std_logic_vector(8 downto 0);
signal vga_driver_din_d : std_logic_vector(8 downto 0);
signal state : state_type;
signal ce : std_logic;
signal threshold : std_logic_vector(9 downto 0);
signal processing_time : std_logic_vector(31 downto 0);
signal capture_time : std_logic_vector(31 downto 0);
signal icr_btn : std_logic;
begin
inst_anpr_module: anpr_module port map (
clk_100mhz => clk_100mhz,
reset => reset,
capture => capture,
pause => pause,
pause_en => pause_en,
next_addr => next_addr,
next_addr_dir => next_addr_dir,
threshold_nextval => threshold_nextval,
threshold_nextval_dir => threshold_nextval_dir,
ov7670_vsync => ov7670_vsync,
state_capture_image => state_capture_image,
cntx => cntx,
cnty => cnty,
ov7670_capture_ce_cntx => ov7670_capture_ce_cntx,
ov7670_capture_r_acc => ov7670_capture_r_acc,
ov7670_capture_dout1 => ov7670_capture_dout1,
ov7670_capture_we1 => ov7670_capture_we1,
ov7670_capture_dout2 => ov7670_capture_dout2,
ov7670_capture_we2 => ov7670_capture_we2,
ov7670_capture_finished => ov7670_capture_finished,
vga_driver_addr1 => vga_driver_addr1,
vga_driver_din1 => vga_driver_din1,
vga_driver_addr2 => vga_driver_addr2,
vga_driver_din2 => vga_driver_din2,
vga_driver_addr_py1 => vga_driver_addr_py1,
vga_driver_din_py1 => vga_driver_din_py1,
ym1 => ym1,
y0_1 => y0_1,
y1_1 => y1_1,
vga_driver_addr_px1 => vga_driver_addr_px1,
vga_driver_din_px1 => vga_driver_din_px1,
xm1 => xm1,
xmw1 => xmw1,
x0_1 => x0_1,
x1_1 => x1_1,
vga_driver_addr_px2 => vga_driver_addr_px2,
vga_driver_din_px2 => vga_driver_din_px2,
vga_driver_addr_py2 => vga_driver_addr_py2,
vga_driver_din_py2 => vga_driver_din_py2,
vga_driver_ym2 => vga_driver_ym2,
bounds_addr => bounds_addr,
bounds_count => bounds_count,
vga_driver_addr_b => vga_driver_addr_b,
vga_driver_din_bx0 => vga_driver_din_bx0,
vga_driver_din_bx1 => vga_driver_din_bx1,
vga_driver_din_by0 => vga_driver_din_by0,
vga_driver_din_by1 => vga_driver_din_by1,
vga_driver_addr_f => vga_driver_addr_f,
vga_driver_din_f => vga_driver_din_f,
vga_driver_addr_c => vga_driver_addr_c,
vga_driver_din_c => vga_driver_din_c,
vga_driver_addr_ci => vga_driver_addr_ci,
vga_driver_din_ci => vga_driver_din_ci,
vga_driver_addr_d => vga_driver_addr_d,
vga_driver_din_d => vga_driver_din_d,
state => state,
ce => ce,
threshold => threshold,
processing_time => processing_time,
capture_time => capture_time,
icr_btn => icr_btn
);
inst_ov7670_capture: ov7670_capture port map (
clk_100mhz => clk_100mhz,
pclk => ov7670_pclk,
reset => reset,
vsync => ov7670_vsync,
href => ov7670_href,
capture => state_capture_image,
threshold => threshold,
din => ov7670_data,
cntx => cntx,
cnty => cnty,
ce_cntx => ov7670_capture_ce_cntx,
r_acc => ov7670_capture_r_acc,
dout1 => ov7670_capture_dout1,
we1 => ov7670_capture_we1,
dout2 => ov7670_capture_dout2,
we2 => ov7670_capture_we2,
finished => ov7670_capture_finished,
pixel_clock => pixel_clock
);
inst_ov7670_controller: ov7670_controller port map (
clk_100mhz => clk_100mhz,
reset => reset,
send => ov7670_sccb_send,
rw => ov7670_sccb_rw,
addr => ov7670_sccb_addr,
data => ov7670_sccb_din,
sccb_busy => ov7670_sccb_busy,
start_config => start_config,
busy => ov7670_controller_busy,
config_finished => ov7670_controller_config_finished
);
inst_ov7670_sccb: ov7670_sccb port map (
clk_100mhz => clk_100mhz,
reset => reset,
send => ov7670_sccb_send,
rw => ov7670_sccb_rw,
addr => ov7670_sccb_addr,
din => ov7670_sccb_din,
busy => ov7670_sccb_busy,
pwdn_trig => '0',
dout => open,
sioc => ov7670_sioc,
siod => ov7670_siod,
pwdn => ov7670_pwdn
);
inst_vga_driver: vga_driver port map (
clk_100mhz => clk_100mhz,
reset => reset,
next_index => next_index,
next_index_dir => next_index_dir,
next_pixel => next_pixel,
next_pixel_ori => next_pixel_ori,
next_pixel_dir => next_pixel_dir,
r => vga_r,
g => vga_g,
b => vga_b,
addr1 => vga_driver_addr1,
din1 => vga_driver_din1,
addr2 => vga_driver_addr2,
din2 => vga_driver_din2,
addr_py1 => vga_driver_addr_py1,
din_py1 => vga_driver_din_py1,
ym1 => ym1,
y0_1 => y0_1,
y1_1 => y1_1,
addr_px1 => vga_driver_addr_px1,
din_px1 => vga_driver_din_px1,
xm1 => xm1,
xmw1 => xmw1,
x0_1 => x0_1,
x1_1 => x1_1,
addr_px2 => vga_driver_addr_px2,
din_px2 => vga_driver_din_px2,
addr_py2 => vga_driver_addr_py2,
din_py2 => vga_driver_din_py2,
ym2 => vga_driver_ym2,
bounds_addr => bounds_addr,
bounds_count => bounds_count,
addr_b => vga_driver_addr_b,
din_bx0 => vga_driver_din_bx0,
din_bx1 => vga_driver_din_bx1,
din_by0 => vga_driver_din_by0,
din_by1 => vga_driver_din_by1,
addr_f => vga_driver_addr_f,
din_f => vga_driver_din_f,
addr_c => vga_driver_addr_c,
din_c => vga_driver_din_c,
addr_ci => vga_driver_addr_ci,
din_ci => vga_driver_din_ci,
addr_d => vga_driver_addr_d,
din_d => vga_driver_din_d,
state => state,
ce => ce,
capture => capture,
threshold => threshold,
processing_time => processing_time,
capture_time => capture_time,
icr_btn => icr_btn,
pixel_clock => pixel_clock,
hs => vga_hs,
vs => vga_vs,
active => open
);
ov7670_reset_1 <= not reset;
start_config <= (not ov7670_controller_config_finished) and (not ov7670_controller_busy);
config_finished <= ov7670_controller_config_finished;
ov7670_xclk <= clk_25mhz;
clock_process: process(clk_100mhz)
begin
if rising_edge(clk_100mhz) then
if clk_50mhz = '0' then
clk_25mhz <= not clk_25mhz;
end if;
clk_50mhz <= not clk_50mhz;
end if;
end process;
end behavioral;
|
<filename>hw/vhdl/paranut/marbiter.vhd
--------------------------------------------------------------------------------
-- This file is part of the ParaNut project.
--
-- Copyright (C) 2013 <NAME>, <<EMAIL>>
-- Hochschule Augsburg, University of Applied Sciences
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation and/or
-- other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Description:
-- This is the arbiter for the MEMU. See description below for details.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library paranut;
use paranut.paranut_config.all;
use paranut.types.all;
use paranut.memu_lib.all;
use paranut.paranut_lib.all;
use paranut.lfsr.all;
entity selector is
generic (
DWIDTH : integer := 1; -- Width of the data that gets arbitrated
SEL_MAX : integer := 1; -- Maximum value for sel (usually RPORTS+WPORTS)
FAST_INDEX : integer := 0 -- If prio < FAST_INDEX the fast inputs have priority else the slow inputs
);
port (
clk : in std_logic;
reset : in std_logic;
f_dat_in : in std_logic_vector(DWIDTH-1 downto 0);
f_sel_in : in integer range 0 to SEL_MAX;
f_sel_valid_in : in std_logic;
s_dat_in : in std_logic_vector(DWIDTH-1 downto 0);
s_sel_in : in integer range 0 to SEL_MAX;
s_sel_valid_in : in std_logic;
prio : in unsigned(MAX(0, CFG_NUT_CPU_CORES_LD-1) downto 0);
--hold : in std_logic;
dat_out : out std_logic_vector(DWIDTH-1 downto 0);
sel_out : out integer range 0 to SEL_MAX;
sel_valid_out : out std_logic
);
end selector;
architecture rtl of selector is
type registers is record
s_dat_in : std_logic_vector(DWIDTH-1 downto 0);
s_sel_in : integer range 0 to SEL_MAX;
s_sel_valid_in : std_logic;
--last_sel : std_logic;
end record;
signal r, rin : registers;
begin
-- Combinatorial process
comb : process (reset, r, f_dat_in, f_sel_in, f_sel_valid_in, s_sel_in, s_sel_valid_in, prio) --, hold)
variable v : registers;
variable sel : std_logic;
variable slow_sel_valid : std_logic;
begin
v := r;
-- Set defaults...
--sel := r.last_sel;
if (r.s_sel_in = s_sel_in) then
slow_sel_valid := (r.s_sel_valid_in and s_sel_valid_in);
else
slow_sel_valid := '0';
end if;
--if (hold = '0') then
v.s_dat_in := s_dat_in;
v.s_sel_in := s_sel_in;
v.s_sel_valid_in := s_sel_valid_in;
if (prio <= FAST_INDEX) then
-- Fast input has priority
if (f_sel_valid_in = '1') then
sel := '0';
else
sel := '1';
end if;
else
-- Slow input has priority
if (slow_sel_valid = '1') then
sel := '1';
else
sel := '0';
end if;
end if;
-- Save last selected output
--v.last_sel := sel;
--end if;
-- Write results...
rin <= v;
case sel is
when '0' => dat_out <= f_dat_in; sel_out <= f_sel_in;
when others => dat_out <= r.s_dat_in; sel_out <= r.s_sel_in;
end case;
sel_valid_out <= slow_sel_valid or f_sel_valid_in;
end process;
-- Register process
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
--r.last_sel <= '0';
r.s_sel_valid_in <= '0';
else
r <= rin;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library paranut;
use paranut.paranut_config.all;
use paranut.types.all;
use paranut.memu_lib.all;
use paranut.paranut_lib.all;
use paranut.lfsr.all;
entity marbiter is
--generic (
-- CFG_MEMU_CACHE_BANKS : integer := 1;
-- RPORTS : integer := 1;
-- WPORTS : integer := 1
-- );
port (
clk : in std_logic;
reset : in std_logic;
ai : in arbiter_in_type;
ao : out arbiter_out_type;
bifai : out busif_arbiter_in_type;
bifao : in busif_arbiter_out_type;
rpai : out readport_arbiter_in_vector(0 to RPORTS-1);
rpao : in readport_arbiter_out_vector(0 to RPORTS-1);
wpai : out writeport_arbiter_in_vector(0 to WPORTS-1);
wpao : in writeport_arbiter_out_vector(0 to WPORTS-1)
);
end marbiter;
architecture rtl of marbiter is
component selector is
generic (
DWIDTH : integer := 1; -- Width of the data that gets arbitrated
SEL_MAX : integer := 1; -- Maximum value for sel (usually RPORTS+WPORTS)
FAST_INDEX : integer := 0 -- If prio < FAST_INDEX the fast inputs have priority else the slow inputs
);
port (
clk : in std_logic;
reset : in std_logic;
f_dat_in : in std_logic_vector(DWIDTH-1 downto 0);
f_sel_in : in integer range 0 to SEL_MAX;
f_sel_valid_in : in std_logic;
s_dat_in : in std_logic_vector(DWIDTH-1 downto 0);
s_sel_in : in integer range 0 to SEL_MAX;
s_sel_valid_in : in std_logic;
prio : in unsigned(MAX(0, CFG_NUT_CPU_CORES_LD-1) downto 0);
--hold : in std_logic;
dat_out : out std_logic_vector(DWIDTH-1 downto 0);
sel_out : out integer range 0 to SEL_MAX;
sel_valid_out : out std_logic
);
end component;
-- Line lock...
-- - Implements mutex for a single cache line (tag + all data banks).
-- - Writers are supposed to acquire a line lock.
-- - Readers do not acquire anything => Writers must perform their actions in a safe order.
-- - if a line lock request is held, the associated address must not change
-- - A line lock may be released during the clock cycle that the last bank/tag access is made,
-- given that the bank/tag lock is still held. This allows faster write cycles without write port
-- monopolizing a line lock (keeping it permanently up).
-- Tag RAM...
-- - Tag RAM must have CFG_NUT_CPU_CORES ports.
-- - Each port is reserved for one CPU (three ports: RP #n, RP $CFG_NUT_CPU_CORES+n, WP #n).
-- - BUSIF uses port #CFG_NUT_CPU_CORES-1.
-- - Arbiter provides:
-- a) Write-/Read-Lock (a write-lock excludes all readers)
-- b) Port arbitration: Multiple readers are allowed, but only one per port (see above)
-- c) Priority selection among a port: 0. BUSIF (if applicable), 1. Data read, 2. Insn Read, 3. Data Write
-- EXAMINE: Would two ports/CPU bring speed improvement? Would a separate port for BUSIF bring speed improvement?
-- - The tag RAM arbitration is also used to prevent writers from replacing/changing a cache line
-- while it is read during a cache read hit. Hence, a reader must keep its 'tagr' lock until its bank access
-- is completed, too. This is not necessary, if a line lock is held (i.e. for cache line reading during a write miss).
-- Bank RAMs...
-- - All ports of CPU n must be linked to port n % CFG_MEMU_BANK_RAM_PORTS of each bank RAM.
-- - The BUSIF is linked to port #(CFG_MEMU_BANK_RAM_PORTS-1).
-- - Multiple usually conflicting grant signals may be set, if the addresses match.
-- - As long as a request signal is set, the address must not chage!
-- - Among write ports and the BUSIF, only one grant will be given to avoid writing conflicts.
-- BUSIF
-- select/routing information can be derived from grant lines (only one is set at a time)
-- Note on deadlock prevention:
-- 1. Requests/grants must always be in the following order (-> break cyclic wait condition):
-- busif < linelock < tagr/tagw < bank
-- 2. (corollary to 1.) R/W ports must not request anything when waiting for BusIF (i.e. 'busif_busy')
-- 3. tag/bank access may never be requested in a hold-and-wait manner: Either request simultaneously or use & complete serially.
-- Mappings for the bank ports to the 'req_bank'/'gnt_bank' bus ...
constant SINGLE_CPU : integer := 1 / CFG_NUT_CPU_CORES; -- TBD: is this really the only way to generate a 1 for CFG_NUT_CPU_CORES_LD == 0
constant NOT_SINGLE_CPU : integer := CONDITIONAL(CFG_NUT_CPU_CORES > 1, 1, 0);
constant IDX_RP_OFF : integer := 0; -- data read ports
constant IDX_IP_OFF : integer := 1; -- insn read ports
constant IDX_WP_OFF : integer := 2; -- write ports
constant IDX_BUSIF : integer := (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS; -- BusIF port
constant RAMPORT_BUSIF : integer := CFG_MEMU_BANK_RAM_PORTS-1;
constant COUNTER_INIT : std_logic_vector(15 downto 0) := (others => '1');
constant COUNTER_POLY : std_logic_vector(15 downto 0) := get_prime_poly(16, 0);
subtype read_req_gnt_type is std_logic_vector(0 to RPORTS+WPORTS);
type read_req_gnt_vector is array (natural range <>) of read_req_gnt_type;
subtype bank_gnt_type is std_logic_vector(0 to (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS);
type bank_gnt_vector is array (natural range <>) of bank_gnt_type;
type bank_gnt_vector_2 is array (natural range <>) of bank_gnt_vector(0 to CFG_MEMU_BANK_RAM_PORTS-1);
type registers is record
counter : unsigned(MAX(0, CFG_NUT_CPU_CORES_LD+CFG_MEMU_ARBITER_METHOD-1) downto 0);
lfsr_counter : std_logic_vector(15 downto 0);
linelock : std_logic_vector(0 to WPORTS);
tagr : read_req_gnt_type;
req_tagw : std_logic_vector(0 to WPORTS);
tagw : std_logic_vector(0 to WPORTS);
bank : bank_gnt_vector_2(0 to CFG_MEMU_CACHE_BANKS-1);
busif : std_logic_vector(0 to RPORTS+WPORTS-1);
end record;
function "and" (op1 : bank_gnt_vector; op2 : bank_gnt_vector) return bank_gnt_vector is
variable vec_out : bank_gnt_vector(0 to CFG_MEMU_BANK_RAM_PORTS-1);
begin
-- result is and of subvectors
for i in 0 to CFG_MEMU_BANK_RAM_PORTS-1 loop
vec_out(i) := op1(i) and op2(i);
end loop;
return (vec_out);
end;
function get_prio_cpu (r : registers) return integer is
variable index : unsigned(MAX(0, CFG_NUT_CPU_CORES_LD-1) downto 0);
begin
if (CFG_NUT_CPU_CORES_LD > 0) then
if (CFG_MEMU_ARBITER_METHOD >= 0) then
index := r.counter(CFG_MEMU_ARBITER_METHOD+CFG_NUT_CPU_CORES_LD-1 downto CFG_MEMU_ARBITER_METHOD);
else
index := unsigned(r.lfsr_counter(CFG_NUT_CPU_CORES_LD-1 downto 0));
end if;
else
index := "0";
end if;
return (conv_integer(index));
end;
function ram_port (i : integer) return integer is
variable index : integer range 0 to CFG_MEMU_BANK_RAM_PORTS-1;
begin
index := CFG_MEMU_BANK_RAM_PORTS-1;
if (i /= IDX_BUSIF) then
index := (i mod CFG_NUT_CPU_CORES) mod CFG_MEMU_BANK_RAM_PORTS;
end if;
return (index);
end;
function ram_index (i : integer) return integer is
variable index : integer range 0 to (RPORTS+WPORTS)/CFG_MEMU_BANK_RAM_PORTS;
variable slv : std_logic_vector((log2x(RPORTS+WPORTS)+CFG_MEMU_BANK_RAM_PORTS-1)/CFG_MEMU_BANK_RAM_PORTS downto 0); -- (M+N-1)/N to ceil
begin
if CFG_MEMU_BANK_RAM_PORTS = 2 then
-- remove rightmost bit
slv := std_logic_vector(to_unsigned(i, slv'length));
index := to_integer(unsigned(slv(slv'left downto 1)));
-- index * 3 (2 RP + 1 WP) is final index
index := index*3;
else
index := i*3;
end if;
return (index);
end;
function cpu_index (i : integer) return integer is
variable index : integer range 0 to (CFG_NUT_CPU_CORES/CFG_MEMU_BANK_RAM_PORTS)-1;
variable slv : std_logic_vector((CFG_NUT_CPU_CORES_LD+CFG_MEMU_BANK_RAM_PORTS-1)/CFG_MEMU_BANK_RAM_PORTS downto 0); -- (M+N-1)/N to ceil
begin
if CFG_MEMU_BANK_RAM_PORTS = 2 then
-- remove rightmost bit
slv := std_logic_vector(to_unsigned(i, slv'length));
index := to_integer(unsigned(slv(slv'left downto 1))); -- (M+N-1)/N to ceil
else
index := i;
end if;
return (index);
end;
signal r, rin : registers;
-- Bank Arbitration Types and Signals
-- --------------------------------------
-- per Bank and Port inputs
type bank_sel_3d_type is array (natural range <>, natural range <>, natural range <>) of integer range 0 to (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS;
type bank_sel_valid_3d_type is array (natural range <>, natural range <>, natural range <>) of std_logic;
type bank_sel_wiadr_3d_type is array (natural range <>, natural range <>, natural range <>) of way_index_addr_type;
signal bank_sel_in : bank_sel_3d_type (0 to CFG_MEMU_CACHE_BANKS-1, 0 to CFG_MEMU_BANK_RAM_PORTS-1, 0 to 1);
signal bank_sel_valid_in : bank_sel_valid_3d_type (0 to CFG_MEMU_CACHE_BANKS-1, 0 to CFG_MEMU_BANK_RAM_PORTS-1, 0 to 1);
signal bank_wiadr_in : bank_sel_wiadr_3d_type (0 to CFG_MEMU_CACHE_BANKS-1, 0 to CFG_MEMU_BANK_RAM_PORTS-1, 0 to 1);
-- per Bank and Port outputs
type bank_sel_2d_type is array (natural range <>, natural range <>) of integer range 0 to (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS;
type bank_sel_valid_2d_type is array (natural range <>, natural range <>) of std_logic;
type bank_sel_wiadr_2d_type is array (natural range <>, natural range <>) of way_index_addr_type;
signal bank_sel_out : bank_sel_2d_type (0 to CFG_MEMU_CACHE_BANKS-1, 0 to CFG_MEMU_BANK_RAM_PORTS-1);
signal bank_sel_valid_out : bank_sel_valid_2d_type (0 to CFG_MEMU_CACHE_BANKS-1, 0 to CFG_MEMU_BANK_RAM_PORTS-1);
signal bank_wiadr_out : bank_sel_wiadr_2d_type (0 to CFG_MEMU_CACHE_BANKS-1, 0 to CFG_MEMU_BANK_RAM_PORTS-1);
-- BusIf Arbitration Types and Signals
-- --------------------------------------
-- per CPU select and select_valid (request) inputs...
type busif_sel_type is array (natural range <>) of integer range 0 to (RPORTS+WPORTS);
type busif_sel_valid_type is array (natural range <>) of std_logic;
signal busif_sel_in : busif_sel_type (0 to 1);
signal busif_sel_valid_in : busif_sel_valid_type (0 to 1);
-- per Arbitration step sel output
signal busif_sel_out : integer range 0 to (RPORTS+WPORTS);
signal busif_sel_valid_out : std_logic;
-- Linelock Arbitration Types and Signals
-- --------------------------------------
-- per WPORT select and select_valid (request) inputs...
type linelock_sel_type is array (natural range <>) of integer range 0 to (WPORTS-1);
type linelock_sel_valid_type is array (natural range <>) of std_logic;
signal linelock_sel_in : linelock_sel_type (0 to 1);
signal linelock_sel_valid_in : linelock_sel_valid_type (0 to 1);
-- per Arbitration step sel output
signal linelock_sel_out : integer range 0 to (WPORTS-1);
signal linelock_sel_valid_out : std_logic;
signal cpu_prio : unsigned(MAX(0, CFG_NUT_CPU_CORES_LD-1) downto 0);
constant BANK_SEL_STEPS : natural := MAX(0, CFG_NUT_CPU_CORES/CFG_MEMU_BANK_RAM_PORTS-2);
begin
-- Generate the Arbitration steps for the Bank Arbitration
-- ------------------------------------------------------------
Banks : for b in 0 to CFG_MEMU_CACHE_BANKS-1 generate
BankBusIfSel: if (CFG_NUT_CPU_CORES > 1 or CFG_MEMU_BANK_RAM_PORTS = 1) generate -- Needed if we only have 1 BRAM port or more than 1 CPU
-- BusIf gets fastest grants
BankBusIfSel : selector
generic map (
DWIDTH => CFG_MEMU_CACHE_WAYS_LD+CFG_MEMU_CACHE_SETS_LD, -- way_index_addr_type
SEL_MAX => (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS,
FAST_INDEX => CFG_NUT_CPU_CORES
)
port map (
clk => clk,
reset => reset,
f_dat_in => bank_wiadr_in(b, RAMPORT_BUSIF, 0),
f_sel_in => bank_sel_in(b, RAMPORT_BUSIF, 0),
f_sel_valid_in => bank_sel_valid_in(b, RAMPORT_BUSIF, 0),
s_dat_in => bank_wiadr_in(b, RAMPORT_BUSIF, 1),
s_sel_in => bank_sel_in(b, RAMPORT_BUSIF, 1),
s_sel_valid_in => bank_sel_valid_in(b, RAMPORT_BUSIF, 1),
prio => cpu_prio,
--hold => '0', -- No need to hold for bank arbitration (all accesses take 1 cycle)
dat_out => bank_wiadr_out(b, RAMPORT_BUSIF),
sel_out => bank_sel_out(b, RAMPORT_BUSIF),
sel_valid_out => bank_sel_valid_out(b, RAMPORT_BUSIF)
);
end generate; -- BankBusIfSel
-- If we have only 1 CPU with more than 1 BRAM port the BusIf gets exclusive access through the second BRAM port...
BankBusIfPassthrough: if (CFG_NUT_CPU_CORES = 1 and CFG_MEMU_BANK_RAM_PORTS > 1) generate
-- Passthrough has BusIf as input
bank_wiadr_out(b, RAMPORT_BUSIF) <= bank_wiadr_in(b, RAMPORT_BUSIF, 0);
bank_sel_out(b, RAMPORT_BUSIF) <= bank_sel_in(b, RAMPORT_BUSIF, 0);
bank_sel_valid_out(b, RAMPORT_BUSIF) <= bank_sel_valid_in(b, RAMPORT_BUSIF, 0);
end generate; -- BankBusIfPassthrough
BankCPUSel: if (CFG_MEMU_BANK_RAM_PORTS > 1 and CFG_NUT_CPU_CORES >= 4) generate
-- CePU gets fastest grants
BankCPUSel : selector
generic map (
DWIDTH => CFG_MEMU_CACHE_WAYS_LD+CFG_MEMU_CACHE_SETS_LD, -- way_index_addr_type
SEL_MAX => (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS,
FAST_INDEX => 0
)
port map (
clk => clk,
reset => reset,
f_dat_in => bank_wiadr_in(b, 0, 0),
f_sel_in => bank_sel_in(b, 0, 0),
f_sel_valid_in => bank_sel_valid_in(b, 0, 0),
s_dat_in => bank_wiadr_in(b, 0, 1),
s_sel_in => bank_sel_in(b, 0, 1),
s_sel_valid_in => bank_sel_valid_in(b, 0, 1),
prio => cpu_prio,
--hold => '0', -- No need to hold for bank arbitration (all accesses take 1 cycle)
dat_out => bank_wiadr_out(b, 0),
sel_out => bank_sel_out(b, 0),
sel_valid_out => bank_sel_valid_out(b, 0)
);
end generate; -- BankCPUSel
-- If we have less than 4 CPUs with more than 1 BRAM port the CePU gets exclusive access through the first BRAM port...
BankCPUPassthrough: if (CFG_MEMU_BANK_RAM_PORTS > 1 and CFG_NUT_CPU_CORES < 4) generate
-- Passthrough has CePU as input
bank_wiadr_out(b, 0) <= bank_wiadr_in(b, 0, 0);
bank_sel_out(b, 0) <= bank_sel_in(b, 0, 0);
bank_sel_valid_out(b, 0) <= bank_sel_valid_in(b, 0, 0);
end generate; -- BankCPUPassthrough
end generate; -- Banks
-- Generate the Arbitration steps for the BusIf Arbitration
-- ------------------------------------------------------------
BusIfSel : if (CFG_NUT_CPU_CORES >= 2) generate
-- The step has the CePU and all other CoPUs as input
BusIfSel : selector
generic map (
DWIDTH => 1,
SEL_MAX => (RPORTS+WPORTS+1),
FAST_INDEX => 0
)
port map (
clk => clk,
reset => reset,
f_dat_in => "0",
f_sel_in => busif_sel_in(0),
f_sel_valid_in => busif_sel_valid_in(0),
s_dat_in => "0",
s_sel_in => busif_sel_in(1),
s_sel_valid_in => busif_sel_valid_in(1),
prio => cpu_prio,
--hold => busif_step_hold,
dat_out => open,
sel_out => busif_sel_out,
sel_valid_out => busif_sel_valid_out
);
end generate; -- LastStep
-- If there is only 1 CPU we do not need any arbitration, just passthrough input signals...
BusIfPassthrough : if (CFG_NUT_CPU_CORES < 2) generate
-- Passthrough has 1 CPU as input
busif_sel_out <= busif_sel_in(0);
busif_sel_valid_out <= busif_sel_valid_in(0);
end generate; -- LastStep
-- Generate the Arbitration steps for the LineLock Arbitration
-- ------------------------------------------------------------
LineLockSel : if (CFG_NUT_CPU_CORES >= 2) generate
-- The step has the CePU WPORT and all other CoPUs WPORTs as input
LineLockSel : selector
generic map (
DWIDTH => 1,
SEL_MAX => WPORTS,
FAST_INDEX => 0
)
port map (
clk => clk,
reset => reset,
f_dat_in => "0",
f_sel_in => linelock_sel_in(0),
f_sel_valid_in => linelock_sel_valid_in(0),
s_dat_in => "0",
s_sel_in => linelock_sel_in(1),
s_sel_valid_in => linelock_sel_valid_in(1),
prio => cpu_prio,
--hold => linelock_step_hold,
dat_out => open,
sel_out => linelock_sel_out,
sel_valid_out => linelock_sel_valid_out
);
end generate; -- LastStep
-- If there is only 1 CPU we do not need any arbitration, just passthrough input signals...
LineLockPassthrough : if (CFG_NUT_CPU_CORES < 2) generate
-- Passthrough has 1 CPU as input
linelock_sel_out <= linelock_sel_in(0);
linelock_sel_valid_out <= linelock_sel_valid_in(0);
end generate; -- LastStep
comb : process (reset, r, bifao, rpao, wpao, ai, bank_wiadr_out, bank_sel_out, bank_sel_valid_out, busif_sel_out, busif_sel_valid_out, linelock_sel_out, linelock_sel_valid_out)
variable v : registers;
-- LineLockMethod
variable req_linelock, gnt_linelock : std_logic_vector(0 to WPORTS);
variable linelock_wport_sel : linelock_sel_type(0 to WPORTS-1-NOT_SINGLE_CPU); -- -2 because these are without CePU
variable linelock_wport_sel_valid : linelock_sel_valid_type(0 to WPORTS-1-NOT_SINGLE_CPU);
-- TagMethod
variable req_tagr, gnt_tagr : read_req_gnt_type;
variable req_tagw, gnt_tagw : std_logic_vector(0 to WPORTS);
-- BankMethod
variable req_bank, gnt_bank : bank_gnt_vector(0 to CFG_MEMU_BANK_RAM_PORTS-1);
variable sel_wiadr : way_index_addr_vector(0 to CFG_MEMU_BANK_RAM_PORTS-1);
variable sel_cpu_wiadr : way_index_addr_type;
constant BANK_CPU_NUM : integer := CFG_NUT_CPU_CORES/CFG_MEMU_BANK_RAM_PORTS - NOT_SINGLE_CPU;
-- variable wiadr : way_index_addr_2d_vector(0 to CFG_MEMU_BANK_RAM_PORTS-1, 0 to (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS);
variable bank_cpu_wiadr_in : bank_sel_wiadr_2d_type(0 to CFG_MEMU_BANK_RAM_PORTS-1, 0 to BANK_CPU_NUM);
variable bank_cpu_sel_in : bank_sel_2d_type(0 to CFG_MEMU_BANK_RAM_PORTS-1, 0 to BANK_CPU_NUM);
variable bank_cpu_sel_valid_in : bank_sel_valid_2d_type(0 to CFG_MEMU_BANK_RAM_PORTS-1, 0 to BANK_CPU_NUM);
-- type sel_port_type is array (natural range <>) of integer range 0 to (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS;
-- variable sel_port : sel_port_type (0 to CFG_NUT_CPU_CORES-1);
variable sel_port : integer range 0 to (RPORTS+WPORTS+SINGLE_CPU)/CFG_MEMU_BANK_RAM_PORTS;
-- variable sel_port_valid : std_logic_vector(0 to CFG_NUT_CPU_CORES-1);
variable sel_port_valid : std_logic;
-- type sel_br_type is array (natural range <>) of integer range 0 to CFG_NUT_CPU_CORES-1;
-- variable sel_br : sel_port_type(0 to CFG_MEMU_BANK_RAM_PORTS-1);
-- variable sel_br_valid : std_logic_vector(0 to CFG_MEMU_BANK_RAM_PORTS-1);
-- BusifMethod
variable req_busif, gnt_busif : std_logic_vector(0 to RPORTS+WPORTS-1);
variable busif_cpu_sel : busif_sel_type(0 to CFG_NUT_CPU_CORES-1-NOT_SINGLE_CPU); -- -2 because these are without CePU
variable busif_cpu_sel_valid : busif_sel_valid_type(0 to CFG_NUT_CPU_CORES-1-NOT_SINGLE_CPU);
variable busif_sel : integer range 0 to (RPORTS+WPORTS);
variable cpu_sel : integer range 0 to (RPORTS+WPORTS);
-- variable cpu_sel : busif_sel_type(0 to CFG_NUT_CPU_CORES-1);
variable cpu_sel_valid : std_logic;
variable i : integer range 0 to (RPORTS+WPORTS)/CFG_MEMU_BANK_RAM_PORTS;
-- SnoopMethod
variable write : boolean;
variable writer : integer range 0 to WPORTS-1;
begin
v := r;
cpu_prio <= to_unsigned(get_prio_cpu(r) mod CFG_NUT_CPU_CORES, cpu_prio'length);
--------------------------------------------------------------------------------------
-- LineLockMethod
-- Current policy (to save area):
-- - WPORT requests always exclude each other, independent of the index address
-- - concurrent BUSIF and WPORT grants are possible, if they address different lines
--------------------------------------------------------------------------------------
-- Collect all request signals...
req_linelock(WPORTS) := bifao.req_linelock;
for n in 0 to WPORTS-1 loop
req_linelock(n) := wpao(n).req_linelock;
end loop;
-- Determine existing & to-keep grants...
gnt_linelock := r.linelock and req_linelock;
-- Handle BUSIF request (highest priority)...
if (req_linelock(WPORTS) = '1' and gnt_linelock(WPORTS) = '0') then
gnt_linelock(WPORTS) := '1';
for n in 0 to WPORTS-1 loop
if (gnt_linelock(n) = '1' and ai.adr_wp(n)(INDEX_OF_ADDR_RANGE) = ai.wiadr_busif(INDEX_OF_WAY_INDEX_RANGE)) then
gnt_linelock(WPORTS) := '0';
end if;
end loop;
end if;
-- Set selector inputs for CePU...
linelock_sel_in(0) <= 0;
if (req_linelock(0) = '1' and (gnt_linelock(WPORTS) = '0' or ai.adr_wp(0)(INDEX_OF_ADDR_RANGE) /= ai.wiadr_busif(INDEX_OF_WAY_INDEX_RANGE))) then
linelock_sel_valid_in(0) <= '1';
else
linelock_sel_valid_in(0) <= '0';
end if;
-- Set local inputs for slow selector input
for n in 1 to WPORTS-1 loop
linelock_wport_sel(n-1) := n;
-- Make sure to only request a grant if the cache line is different from the BusIf line...
if (req_linelock(n) = '1' and (gnt_linelock(WPORTS) = '0' or ai.adr_wp(n)(INDEX_OF_ADDR_RANGE) /= ai.wiadr_busif(INDEX_OF_WAY_INDEX_RANGE))) then
linelock_wport_sel_valid(n-1) := '1';
else
linelock_wport_sel_valid(n-1) := '0';
end if;
end loop;
-- Select slow input...
linelock_sel_in(1) <= linelock_wport_sel(0);
linelock_sel_valid_in(1) <= linelock_wport_sel_valid(0);
for n in 0 to WPORTS-2 loop
-- i := (n + get_prio_cpu(r)) mod WPORTS-1;
i := n;
if (linelock_wport_sel_valid(i) = '1') then
linelock_sel_in(1) <= linelock_wport_sel(i);
linelock_sel_valid_in(1) <= '1';
exit;
end if;
end loop;
-- Handle result of write port requests...
if (gnt_linelock(0 to WPORTS-1) = zero64(WPORTS-1 downto 0)) then
-- New grant...
if (linelock_sel_valid_out = '1') then
gnt_linelock(linelock_sel_out) := '1';
end if;
end if;
-- Write results...
v.linelock := gnt_linelock;
bifai.gnt_linelock <= gnt_linelock(WPORTS);
for n in 0 to WPORTS-1 loop
wpai(n).gnt_linelock <= gnt_linelock(n);
end loop;
--------------------------------------------------------------------------------------
-- TagMethod
-- - Read access is granted per CPU
-- - Write access is global
--------------------------------------------------------------------------------------
-- Collect all request signals...
for n in 0 to RPORTS-1 loop req_tagr(n) := rpao(n).req_tagr; end loop;
for n in 0 to WPORTS-1 loop
req_tagr(n+RPORTS) := wpao(n).req_tagr;
req_tagw(n) := wpao(n).req_tagw;
end loop;
req_tagr(RPORTS+WPORTS) := bifao.req_tagr;
req_tagw(WPORTS) := bifao.req_tagw;
-- Wait for tagram_ready...
if (ai.tagram_ready = '0') then
gnt_tagr := (others => '0');
gnt_tagw := (others => '0');
else
-- Determine existing & to-keep grants...
gnt_tagr := r.tagr and req_tagr;
gnt_tagw := r.tagw and req_tagw;
-- Handle read requests...
if (unsigned(r.req_tagw) = 0) then -- Writer priority: only accept new reader if no write request waited for more than one cycle ...
for n in 0 to CFG_NUT_CPU_CORES-1 loop -- Select highest priority acquired bit for each CPU
if ((gnt_tagr(n) or gnt_tagr(n+WPORTS) or gnt_tagr(n+2*WPORTS)) = '0'
and (n /= CFG_NUT_CPU_CORES-1 or gnt_tagr(RPORTS+WPORTS) = '0')) then
-- no existing grant...
if (n = CFG_NUT_CPU_CORES-1 and req_tagr(RPORTS+WPORTS) = '1') then
-- Prio 0: BUSIF (shares port with last CPU)
gnt_tagr(RPORTS+WPORTS) := '1';
elsif (req_tagr(n) = '1') then
-- Prio 1: Data read
gnt_tagr(n) := '1';
elsif (req_tagr(n+WPORTS) = '1') then
-- Prio 2: Insn read
gnt_tagr(n+WPORTS) := '1';
elsif (req_tagr(n+RPORTS) = '1') then
-- Prio 3: Data write
gnt_tagr(n+RPORTS) := '1';
end if;
end if;
end loop;
end if;
-- Handle write requests...
-- can only accept new writers if no other writer active
if ( unsigned(gnt_tagw) = 0) then
if (req_tagw(WPORTS) = '1') then
gnt_tagw(WPORTS) := '1'; -- give BUSIF highest priority
else
for n in 0 to WPORTS-1 loop
i := (n + get_prio_cpu(r)) mod WPORTS;
if (req_tagw(i) = '1') then
gnt_tagw(i) := '1';
exit;
end if;
end loop;
end if;
end if;
end if;
-- Write results...
v.req_tagw := req_tagw;
v.tagr := gnt_tagr;
v.tagw := gnt_tagw;
for n in 0 to RPORTS-1 loop
rpai(n).gnt_tagr <= gnt_tagr(n);
end loop;
wpai(0).gnt_tagr <= gnt_tagr(0+RPORTS);
wpai(0).gnt_tagw <= gnt_tagw(0);
for n in 1 to WPORTS-1 loop
wpai(n).gnt_tagr <= gnt_tagr(n+RPORTS);
wpai(n).gnt_tagw <= r.tagw(n);
end loop;
bifai.gnt_tagr <= gnt_tagr(RPORTS+WPORTS);
bifai.gnt_tagw <= gnt_tagw(WPORTS);
--------------------------------------------------------------------------------------
-- BankMethod
-- - Arbitration per Bank and Port
-- - CPUs are assigned to specific one specific port to reduce routing overhead
-- - Each CPU decides which of its 3 Ports has priority, after that the CPU index
-- determines priority
--------------------------------------------------------------------------------------
-- Collect all way & index addresses...
-- for n in 0 to CFG_NUT_CPU_CORES-1 loop
-- -- Sort input addresses into wiadr (optimized for 2 BRAM ports)
-- wiadr(ram_port(n), ram_index(n)+IDX_RP_OFF) := ai.wiadr_rp(n);
-- wiadr(ram_port(n), ram_index(n)+IDX_IP_OFF) := ai.wiadr_rp(n+CFG_NUT_CPU_CORES);
-- wiadr(ram_port(n), ram_index(n)+IDX_WP_OFF) := get_way_index_of_addr(ai.adr_wp(n), ai.way_wp(n));
-- end loop;
-- if SINGLE_CPU = 0 then wiadr(0, IDX_BUSIF) := (others => '-'); end if; -- Port 0, has one less input
-- wiadr(ram_port(IDX_BUSIF), IDX_BUSIF) := ai.wiadr_busif;
for b in 0 to CFG_MEMU_CACHE_BANKS-1 loop
-- Collect all request signals...
for n in 0 to CFG_NUT_CPU_CORES-1 loop
-- Sort request signals same as wiadr (optimized for 2 BRAM ports)
req_bank(ram_port(n))(ram_index(n)+IDX_RP_OFF) := rpao(n).req_bank(b);
req_bank(ram_port(n))(ram_index(n)+IDX_IP_OFF) := rpao(n+CFG_NUT_CPU_CORES).req_bank(b);
req_bank(ram_port(n))(ram_index(n)+IDX_WP_OFF) := wpao(n).req_bank(b);
end loop;
if SINGLE_CPU = 0 then req_bank(0)(IDX_BUSIF) := '-'; end if; -- Port 0, has one less input
req_bank(ram_port(IDX_BUSIF))(IDX_BUSIF) := bifao.req_bank(b);
-- Preset sel_port
-- sel_port := (others => 0);
-- sel_port_valid := (others => '0');
-- Preset sel_br
-- sel_br := (others => 0);
-- sel_br_valid := (others => '0');
-- All bank accesses are done in 1 cycle, no need to keep track of already granted ports...
gnt_bank := (others => (others => '0'));
-- Set selector input signals per CPU...
for n in 0 to CFG_NUT_CPU_CORES-1 loop
i := ram_index(n); -- i is the ram_index of CPU n
sel_cpu_wiadr := (others => '-');
sel_port := i+IDX_RP_OFF;
sel_port_valid := req_bank(ram_port(n))(i+IDX_RP_OFF) or req_bank(ram_port(n))(i+IDX_IP_OFF) or req_bank(ram_port(n))(i+IDX_WP_OFF);
if (req_bank(ram_port(n))(i+IDX_RP_OFF) = '1') then
-- Prio 1: Data read
sel_port := i+IDX_RP_OFF;
sel_cpu_wiadr := ai.wiadr_rp(n);
elsif (req_bank(ram_port(n))(i+IDX_IP_OFF) = '1') then
-- Prio 2: Insn read
sel_port := i+IDX_IP_OFF;
sel_cpu_wiadr := ai.wiadr_rp(n+CFG_NUT_CPU_CORES);
elsif (req_bank(ram_port(n))(i+IDX_WP_OFF) = '1') then
-- Prio 3: Data write
sel_port := i+IDX_WP_OFF;
sel_cpu_wiadr := get_way_index_of_addr(ai.adr_wp(n), ai.way_wp(n));
end if;
-- Write back sel_ports
if (n = 0 and CFG_MEMU_BANK_RAM_PORTS > 1) then
-- At 2 ports CePU gets its own selector...
bank_wiadr_in(b, 0, 0) <= sel_cpu_wiadr;
bank_sel_in(b, 0, 0) <= sel_port;
bank_sel_valid_in(b, 0, 0) <= sel_port_valid;
else
bank_cpu_wiadr_in(ram_port(n), cpu_index(n) - CONDITIONAL(CFG_MEMU_BANK_RAM_PORTS > 1 and ram_port(n) = 0, 1, 0)) := sel_cpu_wiadr;
bank_cpu_sel_in(ram_port(n), cpu_index(n) - CONDITIONAL(CFG_MEMU_BANK_RAM_PORTS > 1 and ram_port(n) = 0, 1, 0)) := sel_port;
bank_cpu_sel_valid_in(ram_port(n), cpu_index(n) - CONDITIONAL(CFG_MEMU_BANK_RAM_PORTS > 1 and ram_port(n) = 0, 1, 0)) := sel_port_valid;
end if;
end loop;
-- BusIf always gets fast input of BankBusIfSel...
bank_wiadr_in(b, RAMPORT_BUSIF, 0) <= ai.wiadr_busif;
bank_sel_in(b, RAMPORT_BUSIF, 0 ) <= IDX_BUSIF;
bank_sel_valid_in(b, RAMPORT_BUSIF, 0) <= req_bank(RAMPORT_BUSIF)(IDX_BUSIF);
-- Select slow input...
for p in 0 to CFG_MEMU_BANK_RAM_PORTS-1 loop
bank_wiadr_in(b, p, 1) <= bank_cpu_wiadr_in(p, BANK_CPU_NUM);
bank_sel_in(b, p, 1) <= bank_cpu_sel_in(p, BANK_CPU_NUM);
bank_sel_valid_in(b, p, 1) <= bank_cpu_sel_valid_in(p, BANK_CPU_NUM);
for n in 0 to CFG_NUT_CPU_CORES/CFG_MEMU_BANK_RAM_PORTS - CONDITIONAL(CFG_MEMU_BANK_RAM_PORTS > 1 and p = 0, 1, 0) - 1 loop
-- i := (n + get_prio_cpu(r)) mod CFG_NUT_CPU_CORES/CFG_MEMU_BANK_RAM_PORTS - CONDITIONAL(CFG_MEMU_BANK_RAM_PORTS > 1 and p = 0, 1, 0);
i := n;
if (bank_cpu_sel_valid_in(p, i) = '1') then
bank_wiadr_in(b, p, 1) <= bank_cpu_wiadr_in(p, i);
bank_sel_in(b, p, 1) <= bank_cpu_sel_in(p, i);
bank_sel_valid_in(b, p, 1) <= '1';
exit;
end if;
end loop;
end loop;
-- Find selected 'wiadr's & determine all possible grant lines...
for p in 0 to CFG_MEMU_BANK_RAM_PORTS-1 loop
sel_wiadr(p) := (others => '-');
if (bank_sel_valid_out(b, p) = '1') then
gnt_bank(p)(bank_sel_out(b, p)) := '1';
sel_wiadr(p) := bank_wiadr_out(b, p);
end if;
end loop;
-- Deactivated parallel execution for now
--for n in 0 to RPORTS+WPORTS loop
--if (sel_port_valid(ram_port(n)) = '1' and req_bank(n) = '1' and wiadr(n) = sel_wiadr(ram_port(n))) then
--gnt_bank(n) := '1';
--end if;
--end loop;
-- Write results...
v.bank(b) := gnt_bank;
for n in 0 to CFG_NUT_CPU_CORES-1 loop
rpai(n).gnt_bank(b) <= gnt_bank(ram_port(n))(ram_index(n)+IDX_RP_OFF);
rpai(n+CFG_NUT_CPU_CORES).gnt_bank(b) <= gnt_bank(ram_port(n))(ram_index(n)+IDX_IP_OFF);
wpai(n).gnt_bank(b) <= gnt_bank(ram_port(n))(ram_index(n)+IDX_WP_OFF);
end loop;
bifai.gnt_bank(b) <= gnt_bank(RAMPORT_BUSIF)(IDX_BUSIF);
for p in 0 to CFG_MEMU_BANK_RAM_PORTS-1 loop
ao.wiadr_bank(b)(p) <= sel_wiadr(p);
end loop;
end loop; -- for b in 0 to CFG_MEMU_CACHE_BANKS-1 loop
--------------------------------------------------------------------------------------
-- BusifMethod
-- - Each CPU decides which of its 3 Ports has priority, after that the CPU index
-- determines priority
--------------------------------------------------------------------------------------
-- Collect all request signals...
for n in 0 to RPORTS-1 loop req_busif(n) := rpao(n).req_busif; end loop;
for n in 0 to WPORTS-1 loop req_busif(RPORTS+n) := wpao(n).req_busif; end loop;
-- Determine existing & to-keep grants...
gnt_busif := r.busif and req_busif;
-- Set default select value...
busif_sel := RPORTS+WPORTS;
-- Pio 4: Default value
-- TBD: Still needed?
cpu_sel := RPORTS+WPORTS;
cpu_sel_valid := '0';
-- Prio 0: Granted ports
if (gnt_busif(0) = '1') then
-- data read port
busif_sel := 0;
cpu_sel := 0;
cpu_sel_valid := '1';
elsif (gnt_busif(CFG_NUT_CPU_CORES) = '1') then
-- insn read port
busif_sel := CFG_NUT_CPU_CORES;
cpu_sel := CFG_NUT_CPU_CORES;
cpu_sel_valid := '1';
elsif (gnt_busif(RPORTS) = '1') then
-- data write port
busif_sel := RPORTS;
cpu_sel := RPORTS;
cpu_sel_valid := '1';
else
-- Handle new requests...
if (req_busif(0) = '1') then
-- Prio 1: Data read
cpu_sel := 0;
cpu_sel_valid := '1';
elsif (req_busif(CFG_NUT_CPU_CORES) = '1') then
-- Prio 2: Instruction read
cpu_sel := CFG_NUT_CPU_CORES;
cpu_sel_valid := '1';
elsif (req_busif(RPORTS) = '1') then
-- Prio 3: Data write
cpu_sel := RPORTS;
cpu_sel_valid := '1';
end if;
end if;
busif_sel_in(0) <= cpu_sel;
busif_sel_valid_in(0) <= cpu_sel_valid;
-- Handle new requests...
for n in 1 to CFG_NUT_CPU_CORES-1 loop
-- Pio 4: Default value
-- TBD: Still needed?
busif_cpu_sel(n-1) := RPORTS+WPORTS;
busif_cpu_sel_valid(n-1) := '0';
-- Prio 0: Granted ports
if (gnt_busif(n) = '1') then
-- data read port
busif_sel := n;
busif_cpu_sel(n-1) := n;
busif_cpu_sel_valid(n-1) := '1';
elsif (gnt_busif(CFG_NUT_CPU_CORES+n) = '1') then
-- insn read port
busif_sel := CFG_NUT_CPU_CORES + n;
busif_cpu_sel(n-1) := CFG_NUT_CPU_CORES + n;
busif_cpu_sel_valid(n-1) := '1';
elsif (gnt_busif(RPORTS+n) = '1') then
-- data write port
busif_sel := RPORTS + n;
busif_cpu_sel(n-1) := RPORTS + n;
busif_cpu_sel_valid(n-1) := '1';
else
-- Handle new requests...
if (req_busif(n) = '1') then
-- Prio 1: Data read
busif_cpu_sel(n-1) := n;
busif_cpu_sel_valid(n-1) := '1';
elsif (req_busif(CFG_NUT_CPU_CORES+n) = '1') then
-- Prio 2: Instruction read
busif_cpu_sel(n-1) := CFG_NUT_CPU_CORES + n;
busif_cpu_sel_valid(n-1) := '1';
elsif (req_busif(RPORTS+n) = '1') then
-- Prio 3: Data write
busif_cpu_sel(n-1) := RPORTS + n;
busif_cpu_sel_valid(n-1) := '1';
end if;
end if;
end loop;
-- Select slow input...
busif_sel_in(1) <= busif_cpu_sel(0);
busif_sel_valid_in(1) <= busif_cpu_sel_valid(0);
for n in 0 to CFG_NUT_CPU_CORES-2 loop
-- i := (n + get_prio_cpu(r)) mod CFG_NUT_CPU_CORES-1;
i := n;
if (busif_cpu_sel_valid(i) = '1') then
busif_sel_in(1) <= busif_cpu_sel(i);
busif_sel_valid_in(1) <= busif_cpu_sel_valid(i);
exit;
end if;
end loop;
-- Find selected port & grant...
if (busif_sel = RPORTS+WPORTS) then
-- New grant...
if (busif_sel_valid_out = '1') then
busif_sel := busif_sel_out;
gnt_busif(busif_sel) := '1';
end if;
end if;
--Write results...
v.busif := gnt_busif;
ao.busif_sel <= busif_sel;
for n in 0 to RPORTS-1 loop rpai(n).gnt_busif <= gnt_busif(n); end loop;
for n in 0 to WPORTS-1 loop wpai(n).gnt_busif <= gnt_busif(n+RPORTS); end loop;
--------------------------------------------------------------------------------------
-- SnoopMethod
-- - Determine a/the writer...
-- - NOTE: only cached writes are supported for snooping (LL/SC)
--------------------------------------------------------------------------------------
write := false;
writer := WPORTS-1;
--if (v.linelock(0) = '1') then
--write := true;
--writer := 0;
--end if;
for n in 0 to WPORTS-1 loop
if (r.linelock(n) = '1') then -- to catch a writer to the cache
--pragma translate_off
-- there should be only one!
assert not write report "more than 1 writers" severity error;
--pragma translate_on
write := true;
writer := n;
end if;
end loop;
-- Generate output signals...
if (write) then
for n in 0 to WPORTS-1 loop
rpai(n).snoop_stb <= '1'; -- signal to all CPUs...
rpai(n).snoop_adr <= ai.adr_wp(writer);
end loop;
rpai(writer).snoop_stb <= '0'; -- ... except to the one that caused the write to avoid race condition
else
for n in 0 to WPORTS-1 loop
rpai(n).snoop_stb <= '0';
rpai(n).snoop_adr <= (others => '-'); -- don't care
end loop;
end if;
if (CFG_MEMU_ARBITER_METHOD >= 0) then
-- round robin...
v.counter := r.counter + 1;
else
-- LFSR...
v.lfsr_counter := get_next_lfsr_state(r.lfsr_counter, COUNTER_POLY);
end if;
if (reset = '1') then
if (CFG_MEMU_ARBITER_METHOD >= 0) then
v.counter := (others => '1');
else
v.lfsr_counter := (others => '1');
end if;
v.linelock := (others => '0');
end if;
rin <= v;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
r <= rin;
end if;
end process;
end rtl;
|
--MIT License
--
--Copyright (c) 2017 <NAME>
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
-- ############################################################################
-- The official specifications of the SHA-256 algorithm can be found here:
-- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sha_512_pkg is
constant WORD_SIZE : natural := 64; --SHA-512 uses 64-bit words
--array types for SHA-512
type K_DATA is array (0 to 79) of std_logic_vector(WORD_SIZE-1 downto 0);
type M_DATA is array (0 to 15) of std_logic_vector(WORD_SIZE-1 downto 0);
type H_DATA is array (0 to 7) of std_logic_vector(WORD_SIZE-1 downto 0);
--function definitions
function ROTR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector;
function ROTL (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector;
function SHR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector;
function CH (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function MAJ (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_UCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_UCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_LCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_LCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
end package;
package body sha_512_pkg is
function ROTR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector is
--result : std_logic_vector(WORD_SIZE-1 downto 0);
begin
--signal result : std_logic_vector(WORD_SIZE-1 downto 0);
return (std_logic_vector(shift_right(unsigned(a), n))) or std_logic_vector((shift_left(unsigned(a), (WORD_SIZE-n))));
end function;
function ROTL (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector is
--result : std_logic_vector(WORD_SIZE-1 downto 0);
begin
--signal result : std_logic_vector(WORD_SIZE-1 downto 0);
return (std_logic_vector(shift_left(unsigned(a), n))) or std_logic_vector((shift_right(unsigned(a), (WORD_SIZE-n))));
end function;
function SHR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector is
begin
return std_logic_vector(shift_right(unsigned(a), n));
end function;
function CH (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return (x and y) xor (not(x) and z);
end function;
function MAJ (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return (x and y) xor (x and z) xor (y and z);
end function;
function SIGMA_UCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 28) xor ROTR(x, 34) xor ROTR(x, 39);
end function;
function SIGMA_UCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 14) xor ROTR(x, 18) xor ROTR(x, 41);
end function;
function SIGMA_LCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 1) xor ROTR(x, 8) xor SHR(x, 7);
end function;
function SIGMA_LCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 19) xor ROTR(x, 61) xor SHR(x, 6);
end function;
end package body;
|
-- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Sign Extension unit for TTA
-- Project :
-------------------------------------------------------------------------------
-- File : zxhw.vhdl
-- Author : <NAME> <<EMAIL>>
-- Company :
-- Created : 2002-06-24
-- Last update: 2003-08-28
-- Platform :
-------------------------------------------------------------------------------
-- Description: sign extension functional unit
-- sign extends half-word into a word
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Entity declaration for zxhw unit internals
----------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
entity fu_zxhw is
generic (
dataw : integer := 32; -- Operand Width
busw : integer := 32); -- Bus Width
port(
t1data : in std_logic_vector(dataw-1 downto 0);
t1load : in std_logic;
r1data : out std_logic_vector(busw-1 downto 0);
glock : in std_logic;
rstx : in std_logic;
clk : in std_logic);
end fu_zxhw;
architecture rtl_0_stage_gated_clock of fu_zxhw is
signal t1reg : std_logic_vector(dataw/2-1 downto 0);
begin
regs : process (clk, rstx)
begin -- process regs
if rstx = '0' then -- asynchronous reset (active low)
t1reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if (glock = '0') then
if t1load = '1' then
t1reg <= t1data(dataw/2-1 downto 0);
end if;
end if;
end if;
end process regs;
r1data <= EXT(t1reg, r1data'length);
end rtl_0_stage_gated_clock;
-------------------------------------------------------------------------------
-- The entities and architectures employing new naming conventions start here
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
entity fu_zxhw_always_1 is
generic (
dataw : integer := 32; -- Operand Width
busw : integer := 32); -- Bus Width
port(
t1data : in std_logic_vector(dataw-1 downto 0);
t1load : in std_logic;
r1data : out std_logic_vector(busw-1 downto 0);
glock : in std_logic;
rstx : in std_logic;
clk : in std_logic);
end fu_zxhw_always_1;
architecture rtl of fu_zxhw_always_1 is
signal t1reg : std_logic_vector(dataw/2-1 downto 0);
begin
regs : process (clk, rstx)
begin -- process regs
if rstx = '0' then -- asynchronous reset (active low)
t1reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if (glock = '0') then
if t1load = '1' then
t1reg <= t1data(dataw/2-1 downto 0);
end if;
end if;
end if;
end process regs;
r1data <= EXT(t1reg, r1data'length);
end rtl;
|
<filename>ip/orca/hdl/cache_controller.vhd
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
entity cache_controller is
generic (
CACHE_SIZE : natural;
LINE_SIZE : positive range 16 to 256;
ADDRESS_WIDTH : positive;
INTERNAL_WIDTH : positive;
EXTERNAL_WIDTH : positive;
LOG2_BURSTLENGTH : positive;
POLICY : cache_policy;
REGION_OPTIMIZATIONS : boolean;
WRITE_FIRST_SUPPORTED : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
--Cache control (Invalidate/flush/writeback)
from_cache_control_ready : out std_logic;
to_cache_control_valid : in std_logic;
to_cache_control_command : in cache_control_command;
to_cache_control_base : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
to_cache_control_last : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
precache_idle : in std_logic;
cache_idle : out std_logic;
--Cache interface ORCA-internal memory-mapped slave
cacheint_oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
cacheint_oimm_byteenable : in std_logic_vector((INTERNAL_WIDTH/8)-1 downto 0);
cacheint_oimm_requestvalid : in std_logic;
cacheint_oimm_readnotwrite : in std_logic;
cacheint_oimm_writedata : in std_logic_vector(INTERNAL_WIDTH-1 downto 0);
cacheint_oimm_readdata : out std_logic_vector(INTERNAL_WIDTH-1 downto 0);
cacheint_oimm_readdatavalid : out std_logic;
cacheint_oimm_waitrequest : buffer std_logic;
--Cached ORCA-internal memory-mapped master
c_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
c_oimm_burstlength : out std_logic_vector(LOG2_BURSTLENGTH downto 0);
c_oimm_burstlength_minus1 : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
c_oimm_byteenable : out std_logic_vector((EXTERNAL_WIDTH/8)-1 downto 0);
c_oimm_requestvalid : out std_logic;
c_oimm_readnotwrite : out std_logic;
c_oimm_writedata : out std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
c_oimm_writelast : out std_logic;
c_oimm_readdata : in std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
c_oimm_readdatavalid : in std_logic;
c_oimm_waitrequest : in std_logic
);
end entity cache_controller;
architecture rtl of cache_controller is
constant DIRTY_BITS : natural := conditional(POLICY = WRITE_BACK, 1, 0);
constant NUM_LINES : positive := CACHE_SIZE/LINE_SIZE;
constant TAG_BITS : positive := ADDRESS_WIDTH-log2(CACHE_SIZE);
constant TAG_LEFT : natural := ADDRESS_WIDTH-1;
constant TAG_RIGHT : natural := log2(NUM_LINES)+log2(LINE_SIZE);
constant CACHELINE_BITS : positive := log2(NUM_LINES);
constant CACHELINE_RIGHT : natural := log2(LINE_SIZE);
constant INTERNAL_WORDS_PER_EXTERNAL_WORD : positive := EXTERNAL_WIDTH/INTERNAL_WIDTH;
alias to_cache_control_base_tag_line : std_logic_vector(TAG_BITS+CACHELINE_BITS-1 downto 0) is
to_cache_control_base(TAG_LEFT downto CACHELINE_RIGHT);
alias to_cache_control_last_tag_line : std_logic_vector(TAG_BITS+CACHELINE_BITS-1 downto 0) is
to_cache_control_last(TAG_LEFT downto CACHELINE_RIGHT);
signal to_cache_control_base_partial : std_logic;
signal to_cache_control_last_partial : std_logic;
signal cache_walker_read_tag_line : std_logic_vector(TAG_BITS+CACHELINE_BITS-1 downto 0);
signal read_region_base_hit : std_logic;
signal read_region_inner_hit : std_logic;
signal read_region_last_hit : std_logic;
signal read_region_hit : std_logic;
signal read_region_hit_partial : std_logic;
function compute_burst_length
return positive is
begin -- function compute_burst_length
if LINE_SIZE/(EXTERNAL_WIDTH/8) > (2**LOG2_BURSTLENGTH) then
return 2**LOG2_BURSTLENGTH;
end if;
return LINE_SIZE/(EXTERNAL_WIDTH/8);
end function compute_burst_length;
constant BYTES_PER_BEAT : positive := EXTERNAL_WIDTH/8;
constant BEATS_PER_BURST : positive range 1 to (2**LOG2_BURSTLENGTH) := compute_burst_length;
constant BYTES_PER_BURST : positive := BYTES_PER_BEAT*BEATS_PER_BURST;
constant BEATS_PER_LINE : positive := LINE_SIZE/BYTES_PER_BEAT;
constant BURSTS_PER_LINE : positive := LINE_SIZE/BYTES_PER_BURST;
signal read_miss : std_logic;
signal read_requestinflight : std_logic;
signal read_lastaddress : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal read_lastline : unsigned(log2(NUM_LINES)-1 downto 0);
type control_state_type is (WALK_CACHE, IDLE, CACHE_MISSED, WAIT_FOR_HIT);
signal control_state : control_state_type;
signal next_control_state : control_state_type;
signal write_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal write_byteenable : std_logic_vector((EXTERNAL_WIDTH/8)-1 downto 0);
signal write_writedata : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal write_requestvalid : std_logic;
signal write_tag_update : std_logic;
signal write_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
alias write_tag_valid : std_logic is write_dirty_valid(0);
signal cache_mgt_tag_update : std_logic;
signal cache_mgt_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
alias cache_mgt_tag_valid : std_logic is cache_mgt_dirty_valid(0);
signal cache_walker_tag_update : std_logic;
signal cache_walker_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
alias cache_walker_tag_valid : std_logic is cache_walker_dirty_valid(0);
signal start_to_cache_walker : std_logic;
signal ready_from_cache_walker : std_logic;
signal done_from_cache_walker : std_logic;
signal cache_walking : std_logic;
signal cache_walker_command : cache_control_command;
signal cache_walker_line : unsigned(log2(NUM_LINES)-1 downto 0);
signal cache_walker_line_increment : std_logic;
signal cache_walker_line_last : std_logic;
signal write_hit : std_logic;
signal write_hit_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
signal filling : std_logic;
signal fill_reading : std_logic;
signal start_to_filler : std_logic;
signal ready_from_filler : std_logic;
signal done_from_filler : std_logic;
signal fill_external_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal fill_external_offset_increment : std_logic;
signal fill_external_offset_last : std_logic;
signal fill_internal_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal fill_internal_offset_increment : std_logic;
signal fill_internal_offset_last : std_logic;
signal write_idle : std_logic;
signal write_ready : std_logic;
signal write_on_hit : std_logic;
signal read_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal read_requestvalid : std_logic;
signal read_speculative : std_logic;
signal read_readdata : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal read_readdatavalid : std_logic;
signal read_readabort : std_logic;
signal read_tag : std_logic_vector(TAG_BITS-1 downto 0);
signal read_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
begin
--Idle when no reads in flight (either hit or miss), not waiting on a
--writeback/writethrough, and not walking the cache.
--Idle is state-only; do not check for incoming requests
cache_idle <= (not read_requestinflight) and write_idle and (not cache_walking);
cacheint_oimm_waitrequest <= read_miss or
(not write_ready) or
cache_walking;
c_oimm_address(log2(BYTES_PER_BEAT)-1 downto 0) <= (others => '0');
read_requestvalid <= cacheint_oimm_requestvalid and (not cacheint_oimm_waitrequest);
cacheint_oimm_readdatavalid <= read_readdatavalid and (not write_on_hit);
single_internal_word_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD = 1 generate
cacheint_oimm_readdata <= read_readdata;
end generate single_internal_word_gen;
multiple_internal_words_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD > 1 generate
type internal_word_vector is array (natural range <>) of std_logic_vector(INTERNAL_WIDTH-1 downto 0);
signal read_readdata_word : internal_word_vector(INTERNAL_WORDS_PER_EXTERNAL_WORD-1 downto 0);
begin
internal_word_gen : for gword in INTERNAL_WORDS_PER_EXTERNAL_WORD-1 downto 0 generate
read_readdata_word(gword) <= read_readdata(((gword+1)*INTERNAL_WIDTH)-1 downto gword*INTERNAL_WIDTH);
end generate internal_word_gen;
cacheint_oimm_readdata <=
read_readdata_word(to_integer(unsigned(read_lastaddress(log2(EXTERNAL_WIDTH/8)-1 downto
log2(INTERNAL_WIDTH/8)))));
end generate multiple_internal_words_gen;
------------------------------------------------------------------------------
-- Cache Contol FSM
------------------------------------------------------------------------------
process(control_state, cache_walker_tag_update, cache_walker_dirty_valid, done_from_cache_walker, read_miss, ready_from_filler, precache_idle, cacheint_oimm_requestvalid, write_idle, to_cache_control_valid, ready_from_cache_walker, to_cache_control_command, done_from_filler)
begin
next_control_state <= control_state;
cache_mgt_tag_update <= '0';
cache_mgt_dirty_valid <= (others => '0');
start_to_filler <= '0';
from_cache_control_ready <= '0';
start_to_cache_walker <= '0';
case control_state is
when WALK_CACHE =>
cache_mgt_tag_update <= cache_walker_tag_update;
cache_mgt_dirty_valid <= cache_walker_dirty_valid;
if done_from_cache_walker = '1' then
next_control_state <= IDLE;
end if;
when IDLE =>
--Could make this combinational to reduce miss latency by one cycle at
--the expense of a longer path to external memory.
if read_miss = '1' then
start_to_filler <= '1';
if ready_from_filler = '1' then
next_control_state <= CACHE_MISSED;
cache_mgt_tag_update <= '1';
cache_mgt_tag_valid <= '0';
end if;
else
if precache_idle = '1' and cacheint_oimm_requestvalid = '0' and write_idle = '1' then
if ready_from_cache_walker = '1' then
from_cache_control_ready <= '1';
if to_cache_control_valid = '1' then
case to_cache_control_command is
when WRITEBACK =>
--Skip writeback commands for read_only and writethrough caches
if POLICY = WRITE_BACK then
start_to_cache_walker <= '1';
next_control_state <= WALK_CACHE;
end if;
when others =>
--Initialize/Invalidate/Flush
start_to_cache_walker <= '1';
next_control_state <= WALK_CACHE;
end case;
end if;
end if;
end if;
end if;
when CACHE_MISSED =>
if done_from_filler = '1' then
cache_mgt_tag_update <= '1';
cache_mgt_tag_valid <= '1';
next_control_state <= WAIT_FOR_HIT;
end if;
when WAIT_FOR_HIT =>
if read_miss = '0' then
next_control_state <= IDLE;
end if;
when others =>
null;
end case;
end process;
ready_from_cache_walker <= '1';
cache_walker_line_last <= '1' when cache_walker_line = to_unsigned(NUM_LINES-1, log2(NUM_LINES)) else '0';
process(clk)
begin
if rising_edge(clk) then
control_state <= next_control_state;
if done_from_cache_walker = '1' then
cache_walking <= '0';
end if;
if start_to_cache_walker = '1' and ready_from_cache_walker = '1' then
cache_walking <= '1';
cache_walker_command <= to_cache_control_command;
end if;
if cache_walker_line_increment = '1' then
cache_walker_line <= cache_walker_line + to_unsigned(1, cache_walker_line'length);
end if;
if reset = '1' then
control_state <= WALK_CACHE;
cache_walker_command <= INITIALIZE;
cache_walking <= '1';
cache_walker_line <= to_unsigned(0, cache_walker_line'length);
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Cache Filler FSM
------------------------------------------------------------------------------
done_from_filler <= filling and (fill_internal_offset_increment and fill_internal_offset_last);
process(clk)
begin
if rising_edge(clk) then
if fill_external_offset_increment = '1' and fill_external_offset_last = '1' then
fill_reading <= '0';
end if;
if done_from_filler = '1' then
filling <= '0';
end if;
if start_to_filler = '1' and ready_from_filler = '1' then
fill_reading <= '1';
filling <= '1';
end if;
if reset = '1' then
fill_reading <= '0';
filling <= '0';
end if;
end if;
end process;
fill_internal_offset_increment <= c_oimm_readdatavalid;
fill_external_offset_increment <= (not c_oimm_waitrequest) and fill_reading;
one_beat_per_line_gen : if BEATS_PER_LINE = 1 generate
fill_internal_offset_last <= '1';
fill_internal_offset <= to_unsigned(0, fill_internal_offset'length);
end generate one_beat_per_line_gen;
multiple_beats_per_line_gen : if BEATS_PER_LINE > 1 generate
fill_internal_offset_last <= '1' when (fill_internal_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) =
to_unsigned(BEATS_PER_LINE-1, log2(BEATS_PER_LINE))) else
'0';
process(clk)
begin
if rising_edge(clk) then
if fill_internal_offset_increment = '1' then
fill_internal_offset <= fill_internal_offset + to_unsigned(BYTES_PER_BEAT, fill_internal_offset'length);
end if;
if reset = '1' then
fill_internal_offset <= to_unsigned(0, fill_internal_offset'length);
end if;
end if;
end process;
end generate multiple_beats_per_line_gen;
one_burst_per_line_gen : if BURSTS_PER_LINE = 1 generate
fill_external_offset_last <= '1';
fill_external_offset <= to_unsigned(0, fill_external_offset'length);
end generate one_burst_per_line_gen;
multiple_bursts_per_line_gen : if BURSTS_PER_LINE > 1 generate
fill_external_offset_last <= '1' when (fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST)) =
to_unsigned(BURSTS_PER_LINE-1, log2(BURSTS_PER_LINE))) else
'0';
process(clk)
begin
if rising_edge(clk) then
if fill_external_offset_increment = '1' then
fill_external_offset <= fill_external_offset + to_unsigned(BYTES_PER_BURST, fill_external_offset'length);
end if;
if reset = '1' then
fill_external_offset <= to_unsigned(0, fill_external_offset'length);
end if;
end if;
end process;
end generate multiple_bursts_per_line_gen;
--Write if filling a cacheline (c_oimm_readdatavalid) or a write has caused a
--tag check (write_on_hit) and that write has hit an existing cacheline
--(read_readdatavalid)
write_hit <= write_on_hit and read_readdatavalid;
write_hit_dirty_valid(0) <= '1';
write_requestvalid <= c_oimm_readdatavalid or write_hit;
write_tag_update <= cache_mgt_tag_update or write_hit;
write_dirty_valid <= write_hit_dirty_valid when write_hit = '1' else cache_mgt_dirty_valid;
------------------------------------------------------------------------------
-- Cache Internals
------------------------------------------------------------------------------
the_cache : cache
generic map (
NUM_LINES => NUM_LINES,
LINE_SIZE => LINE_SIZE,
ADDRESS_WIDTH => ADDRESS_WIDTH,
WIDTH => EXTERNAL_WIDTH,
DIRTY_BITS => DIRTY_BITS,
WRITE_FIRST_SUPPORTED => WRITE_FIRST_SUPPORTED
)
port map (
clk => clk,
reset => reset,
read_address => read_address,
read_requestvalid => read_requestvalid,
read_speculative => read_speculative,
read_readdata => read_readdata,
read_readdatavalid => read_readdatavalid,
read_readabort => read_readabort,
read_miss => read_miss,
read_requestinflight => read_requestinflight,
read_lastaddress => read_lastaddress,
read_tag => read_tag,
read_dirty_valid => read_dirty_valid,
write_address => write_address,
write_byteenable => write_byteenable,
write_requestvalid => write_requestvalid,
write_writedata => write_writedata,
write_tag_update => write_tag_update,
write_dirty_valid => write_dirty_valid
);
read_lastline <= unsigned(read_lastaddress(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)));
cache_walker_read_tag_line <= read_tag & std_logic_vector(cache_walker_line);
to_cache_control_base_partial <=
'1' when to_cache_control_base(log2(LINE_SIZE)-1 downto 0) /= replicate_slv("0", log2(LINE_SIZE)) else '0';
read_region_base_hit <= '1' when cache_walker_read_tag_line = to_cache_control_base_tag_line else '0';
read_region_inner_hit <= '1' when (unsigned(cache_walker_read_tag_line) > unsigned(to_cache_control_base_tag_line) and
unsigned(cache_walker_read_tag_line) < unsigned(to_cache_control_last_tag_line)) else '0';
to_cache_control_last_partial <=
'1' when to_cache_control_last(log2(LINE_SIZE)-1 downto 0) /= replicate_slv("1", log2(LINE_SIZE)) else '0';
read_region_last_hit <= '1' when cache_walker_read_tag_line = to_cache_control_last_tag_line else '0';
--If REGION_OPTIMIZATIONS are off then everything hits and we treat all hits
--as partial hits (i.e. requiring a writeback before invalidating).
read_region_hit <=
read_region_base_hit or read_region_inner_hit or read_region_last_hit when REGION_OPTIMIZATIONS else '1';
read_region_hit_partial <= ((read_region_base_hit and to_cache_control_base_partial) or
(read_region_last_hit and to_cache_control_last_partial)) when REGION_OPTIMIZATIONS else
'1';
------------------------------------------------------------------------------
-- Read-only
------------------------------------------------------------------------------
read_only_gen : if POLICY = READ_ONLY generate
--Cache walking 'FSM'; just invalidate every line (not entered on Writeback/Flush)
cache_walker_tag_update <= cache_walking;
cache_walker_tag_valid <= '0';
cache_walker_line_increment <= cache_walking;
done_from_cache_walker <= cache_walker_line_last and cache_walking;
write_idle <= '1';
write_ready <= '1';
write_on_hit <= '0';
write_writedata <= c_oimm_readdata;
write_byteenable <= (others => '1');
c_oimm_byteenable <= (others => '1');
c_oimm_writedata <= (others => '-');
c_oimm_burstlength <= std_logic_vector(to_unsigned(BEATS_PER_BURST, c_oimm_burstlength'length));
c_oimm_burstlength_minus1 <=
std_logic_vector(to_unsigned(BEATS_PER_BURST-1, c_oimm_burstlength_minus1'length));
c_oimm_writelast <= '1';
ready_from_filler <= (not filling) or done_from_filler;
c_oimm_requestvalid <= fill_reading;
c_oimm_readnotwrite <= '1';
c_oimm_address(ADDRESS_WIDTH-1 downto log2(LINE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(LINE_SIZE));
multiple_beats_per_line_gen : if BEATS_PER_LINE > 1 generate
c_oimm_address(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) <=
std_logic_vector(fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)));
end generate multiple_beats_per_line_gen;
read_address <= cacheint_oimm_address when read_miss = '0' else
read_lastaddress;
read_speculative <= '0';
--On a cacheline fill use the last address (which caused the miss).
write_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
write_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(cache_walker_line) when cache_walking = '1' else
std_logic_vector(read_lastline);
write_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(fill_internal_offset) when read_miss = '1' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
end generate read_only_gen;
------------------------------------------------------------------------------
-- Not Read-only
------------------------------------------------------------------------------
not_read_only_gen : if POLICY /= READ_ONLY generate
signal write_hit_byteenable : std_logic_vector((EXTERNAL_WIDTH/8)-1 downto 0);
signal last_writedata : std_logic_vector(INTERNAL_WIDTH-1 downto 0);
signal done_to_write_on_hit : std_logic;
begin
process (clk) is
begin
if rising_edge(clk) then
if cacheint_oimm_waitrequest = '0' then
last_writedata <= cacheint_oimm_writedata;
end if;
if done_to_write_on_hit = '1' then
write_on_hit <= '0';
end if;
if (cacheint_oimm_requestvalid = '1' and
cacheint_oimm_readnotwrite = '0' and
cacheint_oimm_waitrequest = '0') then
write_on_hit <= '1';
end if;
if reset = '1' then
write_on_hit <= '0';
end if;
end if;
end process;
single_internal_word_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD = 1 generate
process (clk) is
begin
if rising_edge(clk) then
if cacheint_oimm_waitrequest = '0' then
write_hit_byteenable <= cacheint_oimm_byteenable;
end if;
end if;
end process;
end generate single_internal_word_gen;
multiple_internal_words_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD > 1 generate
process (clk) is
begin
if rising_edge(clk) then
if cacheint_oimm_waitrequest = '0' then
write_hit_byteenable <= (others => '0');
for iword in INTERNAL_WORDS_PER_EXTERNAL_WORD-1 downto 0 loop
if (unsigned(cacheint_oimm_address(log2(BYTES_PER_BEAT)-1 downto log2(INTERNAL_WIDTH/8))) =
to_unsigned(iword, log2(INTERNAL_WORDS_PER_EXTERNAL_WORD))) then
write_hit_byteenable(((iword+1)*(INTERNAL_WIDTH/8))-1 downto iword*(INTERNAL_WIDTH/8)) <=
cacheint_oimm_byteenable;
end if;
end loop; -- iword
end if;
end if;
end process;
end generate multiple_internal_words_gen;
write_writedata <= c_oimm_readdata when read_miss = '1' else
replicate_slv(last_writedata, INTERNAL_WORDS_PER_EXTERNAL_WORD);
write_byteenable <= (others => '1') when read_miss = '1' else write_hit_byteenable;
----------------------------------------------------------------------------
-- Write-through
----------------------------------------------------------------------------
writethrough_gen : if POLICY = WRITE_THROUGH generate
signal writing_through : std_logic;
signal start_to_write_through : std_logic;
signal ready_from_write_through : std_logic;
signal done_from_write_through : std_logic;
begin
--Cache walking 'FSM'; just invalidate every line (not entered on Writeback/Flush)
cache_walker_tag_update <= cache_walking;
cache_walker_tag_valid <= '0';
cache_walker_line_increment <= cache_walking;
done_from_cache_walker <= cache_walker_line_last and cache_walking;
write_idle <= not writing_through;
write_ready <= ready_from_write_through;
--In write-through mode all writes are single cycle, all reads are BEATS_PER_BURST
c_oimm_burstlength <=
std_logic_vector(to_unsigned(1, c_oimm_burstlength'length)) when writing_through = '1' else
std_logic_vector(to_unsigned(BEATS_PER_BURST, c_oimm_burstlength'length));
c_oimm_burstlength_minus1 <=
std_logic_vector(to_unsigned(0, c_oimm_burstlength_minus1'length)) when writing_through = '1' else
std_logic_vector(to_unsigned(BEATS_PER_BURST-1, c_oimm_burstlength_minus1'length));
c_oimm_writedata <= replicate_slv(last_writedata, INTERNAL_WORDS_PER_EXTERNAL_WORD);
c_oimm_byteenable <= write_hit_byteenable when writing_through = '1' else (others => '1');
c_oimm_writelast <= '1';
ready_from_filler <= ((not filling) or done_from_filler) and ready_from_write_through;
c_oimm_requestvalid <= fill_reading or writing_through;
c_oimm_readnotwrite <= not writing_through;
c_oimm_address(ADDRESS_WIDTH-1 downto log2(LINE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(LINE_SIZE));
multiple_beats_per_line_gen : if BEATS_PER_LINE > 1 generate
c_oimm_address(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) <=
read_lastaddress(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) when writing_through = '1' else
std_logic_vector(fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)));
end generate multiple_beats_per_line_gen;
read_address <= cacheint_oimm_address when read_miss = '0' else
read_lastaddress;
read_speculative <= not cacheint_oimm_readnotwrite;
done_to_write_on_hit <= read_readdatavalid or read_readabort;
--On a cacheline fill use the last address (which caused the miss). On a
--write hit, use the last address (which caused the hit).
write_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
write_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(cache_walker_line) when cache_walking = '1' else
std_logic_vector(read_lastline);
write_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(fill_internal_offset) when read_miss = '1' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
done_from_write_through <= (not c_oimm_waitrequest);
ready_from_write_through <= (not writing_through) or done_from_write_through;
start_to_write_through <=
cacheint_oimm_requestvalid and (not cacheint_oimm_readnotwrite) and (not cacheint_oimm_waitrequest);
process (clk) is
begin
if rising_edge(clk) then
if done_from_write_through = '1' then
writing_through <= '0';
end if;
if start_to_write_through = '1' and ready_from_write_through = '1' then
writing_through <= '1';
end if;
if reset = '1' then
writing_through <= '0';
end if;
end if;
end process;
end generate writethrough_gen;
----------------------------------------------------------------------------
-- Write-back
----------------------------------------------------------------------------
writeback_gen : if POLICY = WRITE_BACK generate
signal start_to_spiller : std_logic;
signal spilling : std_logic;
signal spill_reading_into_buffer : std_logic;
signal spill_reading_from_buffer : std_logic;
signal spill_writing_to_memory : std_logic;
signal spill_skipping : std_logic;
signal ready_from_spiller : std_logic;
signal done_from_spiller : std_logic;
signal spill_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal next_spill_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal spill_offset_increment : std_logic;
signal spill_offset_last : std_logic;
signal next_spill_offset_last : std_logic;
signal spill_burst_last : std_logic;
signal spill_buffer_read_data : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal spill_buffer_write_enable : std_logic;
signal spill_buffer_write_data : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal spill_tag : std_logic_vector(TAG_BITS-1 downto 0);
signal spill_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
signal spill_region_hit : std_logic;
signal spill_line : unsigned(log2(NUM_LINES)-1 downto 0);
type cache_walker_state_type is (IDLE, START_SPILLER, WAIT_ON_SPILLER);
signal cache_walker_state : cache_walker_state_type;
signal next_cache_walker_state : cache_walker_state_type;
signal cache_walker_start_to_spiller : std_logic;
begin
--Cache walking FSM. Note that this may add an extra cycle per line for
--spilling vs. integrating with the spiller FSM; done this way for
--simplicity and can be optimized later.
process (cache_walker_state, cache_walking, cache_walker_command, cache_walker_line_last, ready_from_spiller, done_from_spiller, spill_dirty_valid) is
begin
next_cache_walker_state <= cache_walker_state;
cache_walker_tag_update <= '0';
cache_walker_dirty_valid <= (others => '0');
done_from_cache_walker <= '0';
cache_walker_line_increment <= '0';
cache_walker_start_to_spiller <= '0';
case cache_walker_state is
when IDLE =>
if cache_walking = '1' then
case cache_walker_command is
when INITIALIZE =>
--Write every line until done
cache_walker_tag_update <= '1';
cache_walker_tag_valid <= '0';
cache_walker_line_increment <= '1';
if cache_walker_line_last = '1' then
done_from_cache_walker <= '1';
end if;
when others => --INVALIDATE/WRITEBACK/FLUSH
--Loading in line address to spill
next_cache_walker_state <= START_SPILLER;
end case;
end if;
when START_SPILLER =>
--Address loaded; wait for spiller to ack
cache_walker_start_to_spiller <= '1';
if ready_from_spiller = '1' then
next_cache_walker_state <= WAIT_ON_SPILLER;
end if;
when WAIT_ON_SPILLER =>
--Spiller FSM in progress
if done_from_spiller = '1' then
cache_walker_tag_update <= spill_region_hit;
if cache_walker_command = WRITEBACK then
--Set to clean, valid if previously valid
cache_walker_tag_valid <= spill_dirty_valid(0);
else
--FLUSH, set to invalid
cache_walker_tag_valid <= '0';
end if;
cache_walker_line_increment <= '1';
next_cache_walker_state <= IDLE;
if cache_walker_line_last = '1' then
done_from_cache_walker <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
process (clk) is
begin
if rising_edge(clk) then
cache_walker_state <= next_cache_walker_state;
if reset = '1' then
cache_walker_state <= IDLE;
end if;
end if;
end process;
write_idle <= not spilling;
write_ready <= ready_from_spiller;
--In write-back mode writes and reads are all BEATS_PER_BURST
c_oimm_burstlength <= std_logic_vector(to_unsigned(BEATS_PER_BURST, c_oimm_burstlength'length));
c_oimm_burstlength_minus1 <=
std_logic_vector(to_unsigned(BEATS_PER_BURST-1, c_oimm_burstlength_minus1'length));
c_oimm_writedata <= spill_buffer_read_data;
c_oimm_byteenable <= (others => '1');
c_oimm_writelast <= spill_burst_last;
ready_from_filler <= ((not filling) or done_from_filler) and ready_from_spiller;
c_oimm_requestvalid <= fill_reading or spill_writing_to_memory;
c_oimm_readnotwrite <= fill_reading;
c_oimm_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) when fill_reading = '1' else
spill_tag;
c_oimm_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(read_lastline) when fill_reading = '1' else
std_logic_vector(spill_line);
multiple_bursts_per_line_address_gen : if BURSTS_PER_LINE > 1 generate
c_oimm_address(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST)) <=
std_logic_vector(fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST))) when
fill_reading = '1' else
std_logic_vector(spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST)));
end generate multiple_bursts_per_line_address_gen;
multiple_beats_per_burst_line_address_gen : if BEATS_PER_BURST > 1 generate
c_oimm_address(log2(BYTES_PER_BURST)-1 downto log2(BYTES_PER_BEAT)) <= (others => '0');
end generate multiple_beats_per_burst_line_address_gen;
read_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
spill_tag when spill_reading_into_buffer = '1' else
cacheint_oimm_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) when read_miss = '0' else
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
read_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(spill_line) when spill_reading_into_buffer = '1' else
std_logic_vector(cache_walker_line) when cache_walking = '1' else
cacheint_oimm_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) when read_miss = '0' else
std_logic_vector(read_lastline);
read_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(spill_offset) when spill_reading_into_buffer = '1' else
cacheint_oimm_address(log2(LINE_SIZE)-1 downto 0) when read_miss = '0' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
read_speculative <= '0';
done_to_write_on_hit <= read_readdatavalid;
write_hit_dirty_valid(write_hit_dirty_valid'left) <= '1';
--On a cacheline fill use the last address (which caused the miss). On a
--write hit, use the last address (which caused the hit). When spilling
--a line use the same tag so that the WRITEBACK command correctly sets
--the line to clean after writing it out to memory.
write_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
spill_tag when cache_walking = '1' else
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
write_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(cache_walker_line) when cache_walking = '1' else
std_logic_vector(read_lastline);
write_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(fill_internal_offset) when read_miss = '1' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
--------------------------------------------------------------------------
-- Cache Spiller FSM
--------------------------------------------------------------------------
start_to_spiller <= (start_to_filler and ready_from_filler) or cache_walker_start_to_spiller;
ready_from_spiller <= ((not spilling) or done_from_spiller);
done_from_spiller <= (spill_writing_to_memory and
(not c_oimm_waitrequest) and
(not fill_reading) and
spill_offset_last) or
spill_skipping;
process(clk)
begin
if rising_edge(clk) then
if done_from_spiller = '1' then
spilling <= '0';
spill_writing_to_memory <= '0';
spill_skipping <= '0';
end if;
if spill_offset_increment = '1' then
if spill_offset_last = '1' then
spill_reading_from_buffer <= spill_reading_into_buffer;
spill_reading_into_buffer <= '0';
end if;
if next_spill_offset_last = '1' then
if spill_reading_into_buffer = '0' then
spill_reading_from_buffer <= '0';
end if;
end if;
end if;
if spill_reading_from_buffer = '1' then
spill_writing_to_memory <= '1';
end if;
--Set spilling to indicate the line needs to be spilled
if start_to_spiller = '1' and ready_from_spiller = '1' then
spilling <= '1';
spill_tag <= read_tag;
spill_line <= unsigned(read_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)));
spill_dirty_valid <= read_dirty_valid;
spill_region_hit <= read_region_hit;
--Spill for real only if valid, within the region, dirty, and not
--invalidating (except partial cachelines, which must be flushed on
--invalidate).
--
--Note that INITIALIZE command does not call the spiller so we
--don't have to check for it here.
if (read_dirty_valid(0) = '1' and
read_dirty_valid(read_dirty_valid'left) = '1' and
(cache_walking = '0' or (read_region_hit = '1' and
(cache_walker_command /= INVALIDATE or read_region_hit_partial = '1')))) then
spill_reading_into_buffer <= '1';
else
spill_skipping <= '1';
end if;
end if;
if reset = '1' then
spilling <= '0';
spill_reading_into_buffer <= '0';
spill_reading_from_buffer <= '0';
spill_writing_to_memory <= '0';
spill_skipping <= '0';
end if;
end if;
end process;
spill_offset_increment <= spill_reading_into_buffer or
(spill_writing_to_memory and ((not c_oimm_waitrequest) and (not fill_reading)));
one_beat_per_line_offset_gen : if BEATS_PER_LINE = 1 generate
next_spill_offset <= to_unsigned(0, next_spill_offset'length);
spill_offset <= to_unsigned(0, spill_offset'length);
next_spill_offset_last <= '1';
spill_offset_last <= '1';
end generate one_beat_per_line_offset_gen;
multiple_beats_per_line_offset_gen : if BEATS_PER_LINE > 1 generate
next_spill_offset <=
spill_offset + to_unsigned(BYTES_PER_BEAT, spill_offset'length) when spill_offset_increment = '1' else
spill_offset;
next_spill_offset_last <= '1' when (next_spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) =
to_unsigned(BEATS_PER_LINE-1, log2(BEATS_PER_LINE))) else
'0';
process(clk)
begin
if rising_edge(clk) then
spill_offset <= next_spill_offset;
spill_offset_last <= next_spill_offset_last;
if reset = '1' then
spill_offset <= to_unsigned(0, spill_offset'length);
end if;
end if;
end process;
end generate multiple_beats_per_line_offset_gen;
one_beat_per_burst_gen : if BEATS_PER_BURST = 1 generate
spill_burst_last <= '1';
end generate one_beat_per_burst_gen;
multiple_beats_per_burst_gen : if BEATS_PER_BURST > 1 generate
spill_burst_last <= '1' when (spill_offset(log2(BYTES_PER_BURST)-1 downto log2(BYTES_PER_BEAT)) =
to_unsigned(BEATS_PER_BURST-1, log2(BEATS_PER_BURST))) else
'0';
end generate multiple_beats_per_burst_gen;
--------------------------------------------------------------------------
-- Spill Buffer
--------------------------------------------------------------------------
process (clk) is
begin
if rising_edge(clk) then
--Readdata comes back one cycle after fill address changes
spill_buffer_write_enable <= spill_offset_increment and spill_reading_into_buffer;
end if;
end process;
spill_buffer_write_data <= read_readdata;
one_beat_per_line_buffer_gen : if BEATS_PER_LINE = 1 generate
process (clk) is
begin
if rising_edge(clk) then
if spill_buffer_write_enable = '1' then
spill_buffer_read_data <= spill_buffer_write_data;
end if;
end if;
end process;
end generate one_beat_per_line_buffer_gen;
multiple_beats_per_line_buffer_gen : if BEATS_PER_LINE > 1 generate
signal spill_buffer_read_address : unsigned(log2(BEATS_PER_LINE)-1 downto 0);
signal spill_buffer_write_address : unsigned(log2(BEATS_PER_LINE)-1 downto 0);
begin
process (clk) is
begin
if rising_edge(clk) then
--Readdata comes back one cycle after fill address changes
spill_buffer_write_address <= spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT));
end if;
end process;
spill_buffer_read_address <= next_spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT));
spill_buffer : bram_sdp_write_first
generic map (
DEPTH => BEATS_PER_LINE,
WIDTH => EXTERNAL_WIDTH,
WRITE_FIRST_SUPPORTED => WRITE_FIRST_SUPPORTED
)
port map (
clk => clk,
read_address => spill_buffer_read_address,
read_data => spill_buffer_read_data,
write_address => spill_buffer_write_address,
write_enable => spill_buffer_write_enable,
write_data => spill_buffer_write_data
);
end generate multiple_beats_per_line_buffer_gen;
end generate writeback_gen;
end generate not_read_only_gen;
------------------------------------------------------------------------------
-- Assertions
------------------------------------------------------------------------------
assert (CACHE_SIZE mod LINE_SIZE) = 0
report "Error in cache: CACHE_SIZE (" &
integer'image(CACHE_SIZE) &
") must be an even mulitple of LINE_SIZE (" &
integer'image(LINE_SIZE) &
")."
severity failure;
assert 2**log2(CACHE_SIZE) = CACHE_SIZE
report "Error in cache: CACHE_SIZE (" &
integer'image(CACHE_SIZE) &
") must be a power of 2."
severity failure;
assert EXTERNAL_WIDTH >= INTERNAL_WIDTH
report "Error in cache: EXTERNAL_WIDTH (" &
integer'image(EXTERNAL_WIDTH) &
") must be greater than or equal to INTERNAL_WIDTH (" &
integer'image(INTERNAL_WIDTH) &
")."
severity failure;
--pragma translate_off
-------------------------------------------------------------------------------
-- Simulation debug
-------------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then
assert write_hit /= '1' or cache_mgt_tag_update /= '1' report "Multiple simultaneous tag updates" severity failure;
end if;
end if;
end process;
--pragma translate_on
end architecture;
|
<reponame>muhammedtarikyildiz/fractional-order-msbl-fpga
--Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
--Date : Fri Jun 25 23:10:56 2021
--Host : DESKTOP-BJG36E9 running 64-bit major release (build 9200)
--Command : generate_target func1_bd.bd
--Design : func1_bd
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity func1_bd is
port (
clk : in STD_LOGIC;
gateway_out2 : out STD_LOGIC_VECTOR ( 63 downto 0 );
signal_with_noise1 : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of func1_bd : entity is "func1_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=func1_bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=1,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SYSGEN,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of func1_bd : entity is "func1_bd.hwdef";
end func1_bd;
architecture STRUCTURE of func1_bd is
component func1_bd_func1_1_0 is
port (
signal_with_noise1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
clk : in STD_LOGIC;
gateway_out2 : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end component func1_bd_func1_1_0;
signal clk_1 : STD_LOGIC;
signal func1_1_gateway_out2 : STD_LOGIC_VECTOR ( 63 downto 0 );
signal signal_with_noise1_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN func1_bd_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of gateway_out2 : signal is "xilinx.com:signal:data:1.0 DATA.GATEWAY_OUT2 DATA";
attribute X_INTERFACE_PARAMETER of gateway_out2 : signal is "XIL_INTERFACENAME DATA.GATEWAY_OUT2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of signal_with_noise1 : signal is "xilinx.com:signal:data:1.0 DATA.SIGNAL_WITH_NOISE1 DATA";
attribute X_INTERFACE_PARAMETER of signal_with_noise1 : signal is "XIL_INTERFACENAME DATA.SIGNAL_WITH_NOISE1, LAYERED_METADATA undef";
begin
clk_1 <= clk;
gateway_out2(63 downto 0) <= func1_1_gateway_out2(63 downto 0);
signal_with_noise1_1(31 downto 0) <= signal_with_noise1(31 downto 0);
func1_1: component func1_bd_func1_1_0
port map (
clk => clk_1,
gateway_out2(63 downto 0) => func1_1_gateway_out2(63 downto 0),
signal_with_noise1(31 downto 0) => signal_with_noise1_1(31 downto 0)
);
end STRUCTURE;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity call_Loop_LB2D_shift is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
slice_stream_V_value_V_dout : IN STD_LOGIC_VECTOR (23 downto 0);
slice_stream_V_value_V_empty_n : IN STD_LOGIC;
slice_stream_V_value_V_read : OUT STD_LOGIC;
out_stream_V_value_V_din : OUT STD_LOGIC_VECTOR (71 downto 0);
out_stream_V_value_V_full_n : IN STD_LOGIC;
out_stream_V_value_V_write : OUT STD_LOGIC );
end;
architecture behav of call_Loop_LB2D_shift is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal slice_stream_V_value_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal out_stream_V_value_V_blk_n : STD_LOGIC;
signal icmp_reg_298 : STD_LOGIC_VECTOR (0 downto 0);
signal i_0_i_i_reg_102 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_1_fu_113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal n1_1_fu_119_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal n1_1_reg_284 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_3_fu_125_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_289 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal i_fu_131_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal icmp_fu_147_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal n1_reg_91 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00001001 : BOOLEAN;
signal buffer_1_value_V_fu_70 : STD_LOGIC_VECTOR (23 downto 0);
signal buffer_0_value_V_fu_74 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_fu_137_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal p_Result_6_2_2_fu_221_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_6_2_1_fu_211_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_6_2_fu_201_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_6_1_2_fu_191_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_6_1_1_fu_181_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_6_1_fu_171_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_fu_167_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_fu_163_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_fu_159_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_1_fu_113_p2 = ap_const_lv1_1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_1_fu_113_p2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state3 xor ap_const_logic_1);
elsif ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_1_fu_113_p2))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_0_i_i_reg_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_lv1_0 = tmp_3_fu_125_p2))) then
i_0_i_i_reg_102 <= i_fu_131_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_1_fu_113_p2))) then
i_0_i_i_reg_102 <= ap_const_lv3_0;
end if;
end if;
end process;
n1_reg_91_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
n1_reg_91 <= ap_const_lv2_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
n1_reg_91 <= n1_1_reg_284;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_3_reg_289))) then
buffer_0_value_V_fu_74 <= buffer_1_value_V_fu_70;
buffer_1_value_V_fu_70 <= slice_stream_V_value_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_3_fu_125_p2))) then
icmp_reg_298 <= icmp_fu_147_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
n1_1_reg_284 <= n1_1_fu_119_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_3_reg_289 <= tmp_3_fu_125_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, tmp_1_fu_113_p2, ap_CS_fsm_state2, tmp_3_fu_125_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_1_fu_113_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_3_fu_125_p2 = ap_const_lv1_1)))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_3_fu_125_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state5 <= ap_CS_fsm(3);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00001001_assign_proc : process(slice_stream_V_value_V_empty_n, out_stream_V_value_V_full_n, ap_enable_reg_pp0_iter1, icmp_reg_298)
begin
ap_block_pp0_stage0_flag00001001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and ((ap_const_logic_0 = slice_stream_V_value_V_empty_n) or ((icmp_reg_298 = ap_const_lv1_0) and (ap_const_logic_0 = out_stream_V_value_V_full_n))));
end process;
ap_block_pp0_stage0_flag00011001_assign_proc : process(slice_stream_V_value_V_empty_n, out_stream_V_value_V_full_n, ap_enable_reg_pp0_iter1, icmp_reg_298)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and ((ap_const_logic_0 = slice_stream_V_value_V_empty_n) or ((icmp_reg_298 = ap_const_lv1_0) and (ap_const_logic_0 = out_stream_V_value_V_full_n))));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(slice_stream_V_value_V_empty_n, out_stream_V_value_V_full_n, ap_enable_reg_pp0_iter1, icmp_reg_298)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and ((ap_const_logic_0 = slice_stream_V_value_V_empty_n) or ((icmp_reg_298 = ap_const_lv1_0) and (ap_const_logic_0 = out_stream_V_value_V_full_n))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(slice_stream_V_value_V_empty_n, out_stream_V_value_V_full_n, icmp_reg_298)
begin
ap_block_state4_pp0_stage0_iter1 <= ((ap_const_logic_0 = slice_stream_V_value_V_empty_n) or ((icmp_reg_298 = ap_const_lv1_0) and (ap_const_logic_0 = out_stream_V_value_V_full_n)));
end process;
ap_condition_pp0_exit_iter0_state3_assign_proc : process(tmp_3_fu_125_p2)
begin
if ((tmp_3_fu_125_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, tmp_1_fu_113_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_1_fu_113_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(tmp_1_fu_113_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_1_fu_113_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
i_fu_131_p2 <= std_logic_vector(unsigned(i_0_i_i_reg_102) + unsigned(ap_const_lv3_1));
icmp_fu_147_p2 <= "1" when (tmp_fu_137_p4 = ap_const_lv2_0) else "0";
n1_1_fu_119_p2 <= std_logic_vector(unsigned(n1_reg_91) + unsigned(ap_const_lv2_1));
out_stream_V_value_V_blk_n_assign_proc : process(out_stream_V_value_V_full_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, icmp_reg_298)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (icmp_reg_298 = ap_const_lv1_0))) then
out_stream_V_value_V_blk_n <= out_stream_V_value_V_full_n;
else
out_stream_V_value_V_blk_n <= ap_const_logic_1;
end if;
end process;
out_stream_V_value_V_din <= ((((((((p_Result_6_2_2_fu_221_p4 & p_Result_6_2_1_fu_211_p4) & p_Result_6_2_fu_201_p4) & p_Result_6_1_2_fu_191_p4) & p_Result_6_1_1_fu_181_p4) & p_Result_6_1_fu_171_p4) & tmp_9_fu_167_p1) & tmp_7_fu_163_p1) & tmp_6_fu_159_p1);
out_stream_V_value_V_write_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, icmp_reg_298, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (icmp_reg_298 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
out_stream_V_value_V_write <= ap_const_logic_1;
else
out_stream_V_value_V_write <= ap_const_logic_0;
end if;
end process;
p_Result_6_1_1_fu_181_p4 <= buffer_1_value_V_fu_70(15 downto 8);
p_Result_6_1_2_fu_191_p4 <= slice_stream_V_value_V_dout(15 downto 8);
p_Result_6_1_fu_171_p4 <= buffer_0_value_V_fu_74(15 downto 8);
p_Result_6_2_1_fu_211_p4 <= buffer_1_value_V_fu_70(23 downto 16);
p_Result_6_2_2_fu_221_p4 <= slice_stream_V_value_V_dout(23 downto 16);
p_Result_6_2_fu_201_p4 <= buffer_0_value_V_fu_74(23 downto 16);
slice_stream_V_value_V_blk_n_assign_proc : process(slice_stream_V_value_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
slice_stream_V_value_V_blk_n <= slice_stream_V_value_V_empty_n;
else
slice_stream_V_value_V_blk_n <= ap_const_logic_1;
end if;
end process;
slice_stream_V_value_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
slice_stream_V_value_V_read <= ap_const_logic_1;
else
slice_stream_V_value_V_read <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_113_p2 <= "1" when (n1_reg_91 = ap_const_lv2_2) else "0";
tmp_3_fu_125_p2 <= "1" when (i_0_i_i_reg_102 = ap_const_lv3_4) else "0";
tmp_6_fu_159_p1 <= buffer_0_value_V_fu_74(8 - 1 downto 0);
tmp_7_fu_163_p1 <= buffer_1_value_V_fu_70(8 - 1 downto 0);
tmp_9_fu_167_p1 <= slice_stream_V_value_V_dout(8 - 1 downto 0);
tmp_fu_137_p4 <= i_0_i_i_reg_102(2 downto 1);
end behav;
|
<gh_stars>0
library IEEE;
use IEEE.std_logic_1164.all;
package blink_pkg is
component Blink is
generic (
FREQ : positive:=25e6;
SECS : positive:=1
);
port (
clk_i : in std_logic;
led_o : out std_logic
);
end component Blink;
end package blink_pkg;
|
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