system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<stdio.h>
__global__ void end()
{
if(threadIdx.x==31 && blockIdx.x == 1023)
{
printf("end\n");
}
}
int main()
{
end<<<1024,32>>>();
cudaDeviceSynchronize();
}
|
.file "tmpxft_000db2df_00000000-6_threadIdx_blockIdx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z3endvv
.type _Z21__device_stub__Z3endvv, @function
_Z21__device_stub__Z3endvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3endv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z21__device_stub__Z3endvv, .-_Z21__device_stub__Z3endvv
.globl _Z3endv
.type _Z3endv, @function
_Z3endv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3endvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3endv, .-_Z3endv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z21__device_stub__Z3endvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3endv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3endv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<stdio.h>
__global__ void end()
{
if(threadIdx.x==31 && blockIdx.x == 1023)
{
printf("end\n");
}
}
int main()
{
end<<<1024,32>>>();
cudaDeviceSynchronize();
}
|
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void end()
{
if(threadIdx.x==31 && blockIdx.x == 1023)
{
printf("end\n");
}
}
int main()
{
end<<<1024,32>>>();
hipDeviceSynchronize();
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void end()
{
if(threadIdx.x==31 && blockIdx.x == 1023)
{
printf("end\n");
}
}
int main()
{
end<<<1024,32>>>();
hipDeviceSynchronize();
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3endv
.globl _Z3endv
.p2align 8
.type _Z3endv,@function
_Z3endv:
v_cmp_eq_u32_e32 vcc_lo, 31, v0
s_cmpk_eq_i32 s15, 0x3ff
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_133
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_6
s_mov_b32 s5, 0
.p2align 6
.LBB0_4:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s5
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_13
s_mov_b32 s9, 0
.LBB0_12:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_12
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_15
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_17
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_21
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_20
s_sleep 1
s_cbranch_execnz .LBB0_21
s_branch .LBB0_23
.p2align 6
.LBB0_20:
s_branch .LBB0_23
.LBB0_21:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_18
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_18
.LBB0_23:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_27
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_27
s_mov_b32 s0, 0
.LBB0_26:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_26
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_106
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 5
s_branch .LBB0_30
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_105
.LBB0_30:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_35
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_34
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_33:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_33
.LBB0_34:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_35:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_37
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_37:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_42
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_41
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_40:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_40
.LBB0_41:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_43
s_branch .LBB0_44
.LBB0_42:
.LBB0_43:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_44:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_49
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_48
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_47:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_47
.LBB0_48:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_50
s_branch .LBB0_51
.LBB0_49:
.LBB0_50:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_51:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_56
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_55
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_54:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_54
.LBB0_55:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_57
s_branch .LBB0_58
.LBB0_56:
.LBB0_57:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_58:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_63
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_62
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_61:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_61
.LBB0_62:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_64
s_branch .LBB0_65
.LBB0_63:
.LBB0_64:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_65:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_70
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_69
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_68:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_68
.LBB0_69:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_71
s_branch .LBB0_72
.LBB0_70:
.LBB0_71:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_72:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_77
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_76
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_75:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_75
.LBB0_76:
s_cbranch_execz .LBB0_78
s_branch .LBB0_79
.LBB0_77:
.LBB0_78:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_79:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_85
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_84
s_mov_b32 s11, 0
.p2align 6
.LBB0_82:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_82
s_or_b32 exec_lo, exec_lo, s11
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_85:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_87
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_87:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_91
s_mov_b32 s15, 0
.LBB0_90:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_90
.LBB0_91:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_93
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_93:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_95
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_99
.p2align 6
.LBB0_96:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_98
s_sleep 1
s_cbranch_execnz .LBB0_99
s_branch .LBB0_101
.p2align 6
.LBB0_98:
s_branch .LBB0_101
.LBB0_99:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_96
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_96
.LBB0_101:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_29
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_29
s_mov_b32 s0, 0
.LBB0_104:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_104
s_branch .LBB0_29
.LBB0_105:
s_mov_b32 s0, 0
.LBB0_106:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_133
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_113
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_112
s_mov_b32 s5, 0
.p2align 6
.LBB0_110:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_110
s_or_b32 exec_lo, exec_lo, s5
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_113:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_115
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_115:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_119
s_mov_b32 s9, 0
.LBB0_118:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_118
.LBB0_119:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_121
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_121:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_123
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_127
.p2align 6
.LBB0_124:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_126
s_sleep 1
s_cbranch_execnz .LBB0_127
s_branch .LBB0_129
.p2align 6
.LBB0_126:
s_branch .LBB0_129
.LBB0_127:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_124
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_124
.LBB0_129:
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_133
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_133
s_mov_b32 s0, 0
.LBB0_132:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_132
.LBB0_133:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3endv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3endv, .Lfunc_end0-_Z3endv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "end\n"
.size .str, 5
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3endv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z3endv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void end()
{
if(threadIdx.x==31 && blockIdx.x == 1023)
{
printf("end\n");
}
}
int main()
{
end<<<1024,32>>>();
hipDeviceSynchronize();
}
|
.text
.file "threadIdx_blockIdx.hip"
.globl _Z18__device_stub__endv # -- Begin function _Z18__device_stub__endv
.p2align 4, 0x90
.type _Z18__device_stub__endv,@function
_Z18__device_stub__endv: # @_Z18__device_stub__endv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3endv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z18__device_stub__endv, .Lfunc_end0-_Z18__device_stub__endv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 992(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3endv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3endv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3endv,@object # @_Z3endv
.section .rodata,"a",@progbits
.globl _Z3endv
.p2align 3, 0x0
_Z3endv:
.quad _Z18__device_stub__endv
.size _Z3endv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3endv"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__endv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3endv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3endv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.AND P0, PT, R2, 0x3ff, PT ; /* 0x000003ff0200780c */
/* 0x001fc80003f05270 */
/*0040*/ ISETP.NE.OR P0, PT, R0, 0x1f, P0 ; /* 0x0000001f0000780c */
/* 0x002fda0000705670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3endv
.globl _Z3endv
.p2align 8
.type _Z3endv,@function
_Z3endv:
v_cmp_eq_u32_e32 vcc_lo, 31, v0
s_cmpk_eq_i32 s15, 0x3ff
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_133
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_6
s_mov_b32 s5, 0
.p2align 6
.LBB0_4:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s5
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_13
s_mov_b32 s9, 0
.LBB0_12:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_12
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_15
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_17
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_21
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_20
s_sleep 1
s_cbranch_execnz .LBB0_21
s_branch .LBB0_23
.p2align 6
.LBB0_20:
s_branch .LBB0_23
.LBB0_21:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_18
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_18
.LBB0_23:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_27
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_27
s_mov_b32 s0, 0
.LBB0_26:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_26
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_106
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 5
s_branch .LBB0_30
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_105
.LBB0_30:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_35
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_34
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_33:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_33
.LBB0_34:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_35:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_37
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_37:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_42
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_41
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_40:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_40
.LBB0_41:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_43
s_branch .LBB0_44
.LBB0_42:
.LBB0_43:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_44:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_49
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_48
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_47:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_47
.LBB0_48:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_50
s_branch .LBB0_51
.LBB0_49:
.LBB0_50:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_51:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_56
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_55
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_54:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_54
.LBB0_55:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_57
s_branch .LBB0_58
.LBB0_56:
.LBB0_57:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_58:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_63
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_62
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_61:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_61
.LBB0_62:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_64
s_branch .LBB0_65
.LBB0_63:
.LBB0_64:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_65:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_70
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_69
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_68:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_68
.LBB0_69:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_71
s_branch .LBB0_72
.LBB0_70:
.LBB0_71:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_72:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_77
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_76
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_75:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_75
.LBB0_76:
s_cbranch_execz .LBB0_78
s_branch .LBB0_79
.LBB0_77:
.LBB0_78:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_79:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_85
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_84
s_mov_b32 s11, 0
.p2align 6
.LBB0_82:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_82
s_or_b32 exec_lo, exec_lo, s11
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_85:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_87
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_87:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_91
s_mov_b32 s15, 0
.LBB0_90:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_90
.LBB0_91:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_93
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_93:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_95
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_99
.p2align 6
.LBB0_96:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_98
s_sleep 1
s_cbranch_execnz .LBB0_99
s_branch .LBB0_101
.p2align 6
.LBB0_98:
s_branch .LBB0_101
.LBB0_99:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_96
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_96
.LBB0_101:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_29
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_29
s_mov_b32 s0, 0
.LBB0_104:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_104
s_branch .LBB0_29
.LBB0_105:
s_mov_b32 s0, 0
.LBB0_106:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_133
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_113
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_112
s_mov_b32 s5, 0
.p2align 6
.LBB0_110:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_110
s_or_b32 exec_lo, exec_lo, s5
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_113:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_115
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_115:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_119
s_mov_b32 s9, 0
.LBB0_118:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_118
.LBB0_119:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_121
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_121:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_123
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_127
.p2align 6
.LBB0_124:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_126
s_sleep 1
s_cbranch_execnz .LBB0_127
s_branch .LBB0_129
.p2align 6
.LBB0_126:
s_branch .LBB0_129
.LBB0_127:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_124
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_124
.LBB0_129:
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_133
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_133
s_mov_b32 s0, 0
.LBB0_132:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_132
.LBB0_133:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3endv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3endv, .Lfunc_end0-_Z3endv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "end\n"
.size .str, 5
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3endv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z3endv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000db2df_00000000-6_threadIdx_blockIdx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z3endvv
.type _Z21__device_stub__Z3endvv, @function
_Z21__device_stub__Z3endvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3endv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z21__device_stub__Z3endvv, .-_Z21__device_stub__Z3endvv
.globl _Z3endv
.type _Z3endv, @function
_Z3endv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3endvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3endv, .-_Z3endv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z21__device_stub__Z3endvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3endv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3endv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "threadIdx_blockIdx.hip"
.globl _Z18__device_stub__endv # -- Begin function _Z18__device_stub__endv
.p2align 4, 0x90
.type _Z18__device_stub__endv,@function
_Z18__device_stub__endv: # @_Z18__device_stub__endv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3endv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z18__device_stub__endv, .Lfunc_end0-_Z18__device_stub__endv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 992(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3endv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3endv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3endv,@object # @_Z3endv
.section .rodata,"a",@progbits
.globl _Z3endv
.p2align 3, 0x0
_Z3endv:
.quad _Z18__device_stub__endv
.size _Z3endv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3endv"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__endv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3endv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
#define THREADS 5
#define BLOCKS 1
__global__ void testFunction(float *dev_a, float *dev_b, float dev_c)
{
int thread = threadIdx.x;
if(thread == 0)
{
printf("dev[%d] = %.2f;\n", thread, dev_a[thread]);
printf("b = %.2f;\n", *dev_b);
printf("c 1 = %.2f;\n", dev_c);
dev_c = dev_c*dev_c;
printf("c 2 = %.2f;\n", dev_c);
}
}
int main()
{
float a[THREADS] = { 1, 2, 3, 4, 5 };
printf("BEFORE START\n");
for(int i = 0; i<THREADS; i++)
{
printf("a[%d] = %.2f; ", i, a[i]);
}
printf("\nBEFORE END\n");
float *dev_a;
cudaMalloc((void**)&dev_a, THREADS*sizeof(float));
cudaMemcpy(dev_a, a, THREADS*sizeof(float), cudaMemcpyHostToDevice);
float b = 25;
float *dev_b;
cudaMalloc((void**)&dev_b, sizeof(float));
cudaMemcpy(dev_b, &b, sizeof(float), cudaMemcpyHostToDevice);
float c = 77;
testFunction<<<BLOCKS, THREADS>>>(dev_a, dev_b, c);
cudaFree(dev_a);
cudaFree(dev_b);
printf("after kernel free: c = %.2f;\n", c);
return 0;
}
|
code for sm_80
Function : _Z12testFunctionPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc80007ffe0ff */
/*0030*/ IADD3 R2, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe40007f3e0ff */
/*0040*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0b7624 */
/* 0x000fca00078e00ff */
/*0090*/ LDG.E R10, [R10.64] ; /* 0x000000240a0a7981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R16, 0x0 ; /* 0x0000000000107802 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.X R17, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff117624 */
/* 0x000fe400008e06ff */
/*00c0*/ STL [R1], RZ ; /* 0x000000ff01007387 */
/* 0x0001e20000100800 */
/*00d0*/ LDC.64 R8, c[0x4][R16] ; /* 0x0100000010087b82 */
/* 0x0000620000000a00 */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0002 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*0120*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */
/* 0x004ea40000201800 */
/*0130*/ STL.64 [R1+0x8], R12 ; /* 0x0000080c01007387 */
/* 0x0041e80000100a00 */
/*0140*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*0150*/ MOV R3, 0x1c0 ; /* 0x000001c000037802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01a0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*01b0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fca00078e00ff */
/*01e0*/ LDG.E R10, [R10.64] ; /* 0x000000240a0a7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ LDC.64 R8, c[0x4][R16] ; /* 0x0100000010087b82 */
/* 0x0000620000000a00 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0230*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*0240*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */
/* 0x004ea40000201800 */
/*0250*/ STL.64 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0041e80000100a00 */
/*0260*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*0270*/ MOV R3, 0x2e0 ; /* 0x000002e000037802 */
/* 0x000fe40000000f00 */
/*0280*/ MOV R20, 0x260 ; /* 0x0000026000147802 */
/* 0x000fc40000000f00 */
/*0290*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*02b0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*02c0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*02d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*02e0*/ F2F.F64.F32 R10, c[0x0][0x170] ; /* 0x00005c00000a7b10 */
/* 0x000e220000201800 */
/*02f0*/ LDC.64 R8, c[0x4][R16] ; /* 0x0100000010087b82 */
/* 0x0002a20000000a00 */
/*0300*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0330*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*0340*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0013e80000100a00 */
/*0350*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*0360*/ MOV R3, 0x3d0 ; /* 0x000003d000037802 */
/* 0x000fe40000000f00 */
/*0370*/ MOV R20, 0x350 ; /* 0x0000035000147802 */
/* 0x000fc40000000f00 */
/*0380*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0390*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03a0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*03b0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*03c0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*03d0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*03e0*/ LDC.64 R8, c[0x4][R16] ; /* 0x0100000010087b82 */
/* 0x0000620000000a00 */
/*03f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0400*/ FMUL R0, R0, c[0x0][0x170] ; /* 0x00005c0000007a20 */
/* 0x000fe40000400000 */
/*0410*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0011 */
/*0420*/ F2F.F64.F32 R10, R0 ; /* 0x00000000000a7310 */
/* 0x000ea20000201800 */
/*0430*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff047624 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff057624 */
/* 0x000fe200078e00ff */
/*0450*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*0460*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x000fe40000000000 */
/*0470*/ MOV R11, 0x4e0 ; /* 0x000004e0000b7802 */
/* 0x001fe40000000f00 */
/*0480*/ MOV R20, 0x460 ; /* 0x0000046000147802 */
/* 0x000fc40000000f00 */
/*0490*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*04a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*04b0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*04c0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*04d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
#define THREADS 5
#define BLOCKS 1
__global__ void testFunction(float *dev_a, float *dev_b, float dev_c)
{
int thread = threadIdx.x;
if(thread == 0)
{
printf("dev[%d] = %.2f;\n", thread, dev_a[thread]);
printf("b = %.2f;\n", *dev_b);
printf("c 1 = %.2f;\n", dev_c);
dev_c = dev_c*dev_c;
printf("c 2 = %.2f;\n", dev_c);
}
}
int main()
{
float a[THREADS] = { 1, 2, 3, 4, 5 };
printf("BEFORE START\n");
for(int i = 0; i<THREADS; i++)
{
printf("a[%d] = %.2f; ", i, a[i]);
}
printf("\nBEFORE END\n");
float *dev_a;
cudaMalloc((void**)&dev_a, THREADS*sizeof(float));
cudaMemcpy(dev_a, a, THREADS*sizeof(float), cudaMemcpyHostToDevice);
float b = 25;
float *dev_b;
cudaMalloc((void**)&dev_b, sizeof(float));
cudaMemcpy(dev_b, &b, sizeof(float), cudaMemcpyHostToDevice);
float c = 77;
testFunction<<<BLOCKS, THREADS>>>(dev_a, dev_b, c);
cudaFree(dev_a);
cudaFree(dev_b);
printf("after kernel free: c = %.2f;\n", c);
return 0;
}
|
.file "tmpxft_0001f249_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12testFunctionPfS_fPfS_f
.type _Z35__device_stub__Z12testFunctionPfS_fPfS_f, @function
_Z35__device_stub__Z12testFunctionPfS_fPfS_f:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12testFunctionPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z12testFunctionPfS_fPfS_f, .-_Z35__device_stub__Z12testFunctionPfS_fPfS_f
.globl _Z12testFunctionPfS_f
.type _Z12testFunctionPfS_f, @function
_Z12testFunctionPfS_f:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12testFunctionPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12testFunctionPfS_f, .-_Z12testFunctionPfS_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "BEFORE START\n"
.LC6:
.string "a[%d] = %.2f; "
.LC7:
.string "\nBEFORE END\n"
.LC11:
.string "after kernel free: c = %.2f;\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x3f800000, 48(%rsp)
movl $0x40000000, 52(%rsp)
movl $0x40400000, 56(%rsp)
movl $0x40800000, 60(%rsp)
movl $0x40a00000, 64(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L12:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L12
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x41c80000, 4(%rsp)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movss .LC9(%rip), %xmm0
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z12testFunctionPfS_fPfS_f
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12testFunctionPfS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12testFunctionPfS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1117388800
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1079197696
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
#define THREADS 5
#define BLOCKS 1
__global__ void testFunction(float *dev_a, float *dev_b, float dev_c)
{
int thread = threadIdx.x;
if(thread == 0)
{
printf("dev[%d] = %.2f;\n", thread, dev_a[thread]);
printf("b = %.2f;\n", *dev_b);
printf("c 1 = %.2f;\n", dev_c);
dev_c = dev_c*dev_c;
printf("c 2 = %.2f;\n", dev_c);
}
}
int main()
{
float a[THREADS] = { 1, 2, 3, 4, 5 };
printf("BEFORE START\n");
for(int i = 0; i<THREADS; i++)
{
printf("a[%d] = %.2f; ", i, a[i]);
}
printf("\nBEFORE END\n");
float *dev_a;
cudaMalloc((void**)&dev_a, THREADS*sizeof(float));
cudaMemcpy(dev_a, a, THREADS*sizeof(float), cudaMemcpyHostToDevice);
float b = 25;
float *dev_b;
cudaMalloc((void**)&dev_b, sizeof(float));
cudaMemcpy(dev_b, &b, sizeof(float), cudaMemcpyHostToDevice);
float c = 77;
testFunction<<<BLOCKS, THREADS>>>(dev_a, dev_b, c);
cudaFree(dev_a);
cudaFree(dev_b);
printf("after kernel free: c = %.2f;\n", c);
return 0;
}
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define THREADS 5
#define BLOCKS 1
__global__ void testFunction(float *dev_a, float *dev_b, float dev_c)
{
int thread = threadIdx.x;
if(thread == 0)
{
printf("dev[%d] = %.2f;\n", thread, dev_a[thread]);
printf("b = %.2f;\n", *dev_b);
printf("c 1 = %.2f;\n", dev_c);
dev_c = dev_c*dev_c;
printf("c 2 = %.2f;\n", dev_c);
}
}
int main()
{
float a[THREADS] = { 1, 2, 3, 4, 5 };
printf("BEFORE START\n");
for(int i = 0; i<THREADS; i++)
{
printf("a[%d] = %.2f; ", i, a[i]);
}
printf("\nBEFORE END\n");
float *dev_a;
hipMalloc((void**)&dev_a, THREADS*sizeof(float));
hipMemcpy(dev_a, a, THREADS*sizeof(float), hipMemcpyHostToDevice);
float b = 25;
float *dev_b;
hipMalloc((void**)&dev_b, sizeof(float));
hipMemcpy(dev_b, &b, sizeof(float), hipMemcpyHostToDevice);
float c = 77;
testFunction<<<BLOCKS, THREADS>>>(dev_a, dev_b, c);
hipFree(dev_a);
hipFree(dev_b);
printf("after kernel free: c = %.2f;\n", c);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define THREADS 5
#define BLOCKS 1
__global__ void testFunction(float *dev_a, float *dev_b, float dev_c)
{
int thread = threadIdx.x;
if(thread == 0)
{
printf("dev[%d] = %.2f;\n", thread, dev_a[thread]);
printf("b = %.2f;\n", *dev_b);
printf("c 1 = %.2f;\n", dev_c);
dev_c = dev_c*dev_c;
printf("c 2 = %.2f;\n", dev_c);
}
}
int main()
{
float a[THREADS] = { 1, 2, 3, 4, 5 };
printf("BEFORE START\n");
for(int i = 0; i<THREADS; i++)
{
printf("a[%d] = %.2f; ", i, a[i]);
}
printf("\nBEFORE END\n");
float *dev_a;
hipMalloc((void**)&dev_a, THREADS*sizeof(float));
hipMemcpy(dev_a, a, THREADS*sizeof(float), hipMemcpyHostToDevice);
float b = 25;
float *dev_b;
hipMalloc((void**)&dev_b, sizeof(float));
hipMemcpy(dev_b, &b, sizeof(float), hipMemcpyHostToDevice);
float c = 77;
testFunction<<<BLOCKS, THREADS>>>(dev_a, dev_b, c);
hipFree(dev_a);
hipFree(dev_b);
printf("after kernel free: c = %.2f;\n", c);
return 0;
}
|
.text
.file "main.hip"
.globl _Z27__device_stub__testFunctionPfS_f # -- Begin function _Z27__device_stub__testFunctionPfS_f
.p2align 4, 0x90
.type _Z27__device_stub__testFunctionPfS_f,@function
_Z27__device_stub__testFunctionPfS_f: # @_Z27__device_stub__testFunctionPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12testFunctionPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__testFunctionPfS_f, .Lfunc_end0-_Z27__device_stub__testFunctionPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x4053400000000000 # double 77
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $160, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 96(%rsp)
movl $1084227584, 112(%rsp) # imm = 0x40A00000
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movl $1103626240, 24(%rsp) # imm = 0x41C80000
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1117388800, 28(%rsp) # imm = 0x429A0000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12testFunctionPfS_f, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12testFunctionPfS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12testFunctionPfS_f,@object # @_Z12testFunctionPfS_f
.section .rodata,"a",@progbits
.globl _Z12testFunctionPfS_f
.p2align 3, 0x0
_Z12testFunctionPfS_f:
.quad _Z27__device_stub__testFunctionPfS_f
.size _Z12testFunctionPfS_f, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "a[%d] = %.2f
.size .L.str.1, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "after kernel free: c = %.2f
.size .L.str.3, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12testFunctionPfS_f"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "BEFORE START"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nBEFORE END"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__testFunctionPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12testFunctionPfS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0001f249_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12testFunctionPfS_fPfS_f
.type _Z35__device_stub__Z12testFunctionPfS_fPfS_f, @function
_Z35__device_stub__Z12testFunctionPfS_fPfS_f:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12testFunctionPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z12testFunctionPfS_fPfS_f, .-_Z35__device_stub__Z12testFunctionPfS_fPfS_f
.globl _Z12testFunctionPfS_f
.type _Z12testFunctionPfS_f, @function
_Z12testFunctionPfS_f:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12testFunctionPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12testFunctionPfS_f, .-_Z12testFunctionPfS_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "BEFORE START\n"
.LC6:
.string "a[%d] = %.2f; "
.LC7:
.string "\nBEFORE END\n"
.LC11:
.string "after kernel free: c = %.2f;\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x3f800000, 48(%rsp)
movl $0x40000000, 52(%rsp)
movl $0x40400000, 56(%rsp)
movl $0x40800000, 60(%rsp)
movl $0x40a00000, 64(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L12:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L12
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x41c80000, 4(%rsp)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movss .LC9(%rip), %xmm0
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z12testFunctionPfS_fPfS_f
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12testFunctionPfS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12testFunctionPfS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1117388800
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1079197696
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.globl _Z27__device_stub__testFunctionPfS_f # -- Begin function _Z27__device_stub__testFunctionPfS_f
.p2align 4, 0x90
.type _Z27__device_stub__testFunctionPfS_f,@function
_Z27__device_stub__testFunctionPfS_f: # @_Z27__device_stub__testFunctionPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12testFunctionPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__testFunctionPfS_f, .Lfunc_end0-_Z27__device_stub__testFunctionPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x4053400000000000 # double 77
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $160, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 96(%rsp)
movl $1084227584, 112(%rsp) # imm = 0x40A00000
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movl $1103626240, 24(%rsp) # imm = 0x41C80000
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1117388800, 28(%rsp) # imm = 0x429A0000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12testFunctionPfS_f, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12testFunctionPfS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12testFunctionPfS_f,@object # @_Z12testFunctionPfS_f
.section .rodata,"a",@progbits
.globl _Z12testFunctionPfS_f
.p2align 3, 0x0
_Z12testFunctionPfS_f:
.quad _Z27__device_stub__testFunctionPfS_f
.size _Z12testFunctionPfS_f, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "a[%d] = %.2f
.size .L.str.1, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "after kernel free: c = %.2f
.size .L.str.3, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12testFunctionPfS_f"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "BEFORE START"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nBEFORE END"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__testFunctionPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12testFunctionPfS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
* Face Factor Distance
* (MP3, Fall 2019, GPU Programming/Yifan Liu)
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
#include <fstream>
#include <ctime>
#include <string>
#include <sstream>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP3 takes a (m x k) matrix M \n" \
"and compute the distance betwen rows and save teh result if two rows' distance is smaller than 0.3\n" \
"The values of m, k must be >= 1.\n" \
"\n" \
"Usage: mp3 m k\n"
/* Tile size*/
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
cudaError_t err = (e); \
if (err != cudaSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/*getDistance calculate the distance among rows*/
__global__ static void getDistance_gpu(float *d_M, float *d_P, int m, int k) {
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
if(row >= m || col >= m)
return;
if(row == col){
d_P[row*m+col] = 100;
return;
}
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += pow(d_M[row*k+i] - d_M[col*k+i], 2);
}
expected = sqrt(expected);
d_P[row*m+col] = expected;
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. */
int main()
{
/* read in m and k here */
std::cout << "Loading matrices...\n";
clock_t begin = clock();
int m, k;
std::ifstream in1;
in1.open("descriptor.txt");
if(in1.is_open())
printf("File opened successfully\n");
else
printf("File opened unsuccessfully\n");
std::string line, temp;
// read in m and k
while ((std::getline(in1, line))){
if (line == "end header")
break;
std::istringstream ss(line);
std::cout << line << std::endl;
if(line.find("line_number")!=-1)
ss >> temp >> m;
else if(line.find("vector_dimension")!=-1)
ss >> temp >> k;
}
printf("The matrix is %d x %d\n", m, k);
if (m < 1 || k < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m or k (%d, %d)\n", m, k);
system("Pause");
return EXIT_FAILURE;
}
size_t bytesForM = m * k * sizeof(float);
float *h_M = (float *)malloc(bytesForM);
/* Fill M (on host) */
for (int i = 0; i < m*k; ++i)
in1 >> h_M[i];
in1.close();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Reading input file took %f seconds\n", elapsed_secs);
printf("M =\n"); printMatrix(h_M, m, k);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), P is (m x m) */
/********************************************/
size_t bytesForP = m * m * sizeof(float);
float *h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
system("Pause");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_P;
CUDA_CHECK(cudaMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(cudaMalloc((void **)&d_P, bytesForP));
/* Copy M to device global memory */
CUDA_CHECK(cudaMemcpy(d_M, h_M, bytesForM, cudaMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((m+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host\n");
getDistance_gpu<<<dimGrid, dimBlock>>>(d_M, d_P, m, k);
CUDA_CHECK(cudaDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(cudaMemcpy(h_P, d_P, bytesForP, cudaMemcpyDeviceToHost));
printf(" product received from host\n");
printf("P =\n"); printMatrix(h_P, m, m);
printf("Saving result\n");
std::ofstream out;
out.open("matrix.txt");
for (int i = 0; i < m; i++){
for (int j = 0; j < m; j++){
if (h_P[i*m+j] < 0.3)
out << j+1 << " ";
}
out << std::endl;
}
out.close();
/* Free device global memory */
CUDA_CHECK(cudaFree(d_M));
CUDA_CHECK(cudaFree(d_P));
/* Free host memory */
free(h_M);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(cudaDeviceReset());
printf("Done\n");
system("Pause");
return EXIT_SUCCESS;
}
|
.file "tmpxft_000c4c8b_00000000-6_vector_distance_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL15getDistance_gpuPfS_ii, @function
_ZL15getDistance_gpuPfS_ii:
.LFB3886:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL15getDistance_gpuPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3886:
.size _ZL15getDistance_gpuPfS_ii, .-_ZL15getDistance_gpuPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "["
.LC1:
.string " %3.3f"
.LC2:
.string " ..."
.LC3:
.string " ]\n"
.text
.type _ZL8printRowiPfi, @function
_ZL8printRowiPfi:
.LFB3857:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r12d
movq %rsi, %rbp
movl %edx, %ebx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jg .L15
.L13:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %r14d
imull %r12d, %r14d
movslq %r14d, %r13
leaq 0(,%r13,4), %r15
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r13,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $1, %ebx
jle .L13
pxor %xmm0, %xmm0
cvtss2sd 4(%rbp,%r15), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $2, %ebx
jle .L13
pxor %xmm0, %xmm0
cvtss2sd 8(%rbp,%r13,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $5, %ebx
jg .L16
jne .L11
.L10:
leal -2(%r14,%rbx), %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rax,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L12:
movl %r12d, %eax
imull %ebx, %eax
leal -1(%rbx,%rax), %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rax,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L13
.L16:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L11:
cmpl $3, %ebx
jle .L13
jmp .L12
.cfi_endproc
.LFE3857:
.size _ZL8printRowiPfi, .-_ZL8printRowiPfi
.section .rodata.str1.1
.LC4:
.string " ...\n"
.text
.type _ZL11printMatrixPfii, @function
_ZL11printMatrixPfii:
.LFB3858:
.cfi_startproc
testl %esi, %esi
jg .L28
ret
.L28:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r12d
movq %rdi, %rsi
movl $0, %edi
call _ZL8printRowiPfi
cmpl $1, %ebx
jle .L17
movl %r12d, %edx
movq %rbp, %rsi
movl $1, %edi
call _ZL8printRowiPfi
cmpl $2, %ebx
jle .L17
movl %r12d, %edx
movq %rbp, %rsi
movl $2, %edi
call _ZL8printRowiPfi
cmpl $5, %ebx
jg .L29
jne .L21
.L20:
leal -2(%rbx), %edi
movl %r12d, %edx
movq %rbp, %rsi
call _ZL8printRowiPfi
.L22:
leal -1(%rbx), %edi
movl %r12d, %edx
movq %rbp, %rsi
call _ZL8printRowiPfi
.L17:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L21:
cmpl $3, %ebx
jle .L17
jmp .L22
.cfi_endproc
.LFE3858:
.size _ZL11printMatrixPfii, .-_ZL11printMatrixPfii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC5:
.string "_Z15getDistance_gpuPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3888:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15getDistance_gpuPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3888:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC6:
.string "Loading matrices...\n"
.LC7:
.string "descriptor.txt"
.LC8:
.string "File opened successfully\n"
.LC9:
.string "File opened unsuccessfully\n"
.LC10:
.string "end header"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1
.LC12:
.string "line_number"
.LC13:
.string "vector_dimension"
.LC14:
.string "The matrix is %d x %d\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "MP3 takes a (m x k) matrix M \nand compute the distance betwen rows and save teh result if two rows' distance is smaller than 0.3\nThe values of m, k must be >= 1.\n\nUsage: mp3 m k\n"
.align 8
.LC16:
.string "Invalid value for m or k (%d, %d)\n"
.section .rodata.str1.1
.LC17:
.string "Pause"
.section .rodata.str1.8
.align 8
.LC19:
.string "Reading input file took %f seconds\n"
.section .rodata.str1.1
.LC20:
.string "M =\n"
.LC21:
.string "using (%d x %d) tiles.\n"
.section .rodata.str1.8
.align 8
.LC22:
.string "Unable to allocate host memory\n"
.align 8
.LC23:
.string "cudaMalloc((void **)&d_M, bytesForM)"
.align 8
.LC24:
.string "/home/ubuntu/Datasets/stackv2/train-structured/goldenpartner/Face-recognition/master/vector_distance_gpu.cu"
.align 8
.LC25:
.string "CUDA error: %s, line %d, %s: %s\n"
.align 8
.LC26:
.string "cudaMalloc((void **)&d_P, bytesForP)"
.align 8
.LC27:
.string "cudaMemcpy(d_M, h_M, bytesForM, cudaMemcpyHostToDevice)"
.section .rodata.str1.1
.LC28:
.string "matMul called from host\n"
.LC29:
.string "cudaDeviceSynchronize()"
.section .rodata.str1.8
.align 8
.LC30:
.string "cudaMemcpy(h_P, d_P, bytesForP, cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC31:
.string " product received from host\n"
.LC32:
.string "P =\n"
.LC33:
.string "Saving result\n"
.LC34:
.string "matrix.txt"
.LC36:
.string " "
.LC37:
.string "cudaFree(d_M)"
.LC38:
.string "cudaFree(d_P)"
.LC39:
.string "cudaDeviceReset()"
.LC40:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB3859:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3859
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1192, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq %rax, -1224(%rbp)
leaq -576(%rbp), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $8, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq -456(%rbp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L35
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L35:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE1:
.L36:
leaq -1136(%rbp), %rax
movq %rax, -1152(%rbp)
movq $0, -1144(%rbp)
movb $0, -1136(%rbp)
leaq -1104(%rbp), %rax
movq %rax, -1120(%rbp)
movq $0, -1112(%rbp)
movb $0, -1104(%rbp)
movq -576(%rbp), %rax
movq -24(%rax), %rax
movq -336(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L37
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %r13
leaq 24+_ZTVNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
leaq 40(%r14), %r15
jmp .L38
.L134:
movl $10, %edx
leaq .LC10(%rip), %rsi
movq -1152(%rbp), %rdi
call memcmp@PLT
testl %eax, %eax
jne .L39
.L63:
movl -1204(%rbp), %ecx
movl -1208(%rbp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
.LEHE2:
jmp .L122
.L135:
movq %r14, -1088(%rbp)
movq %r15, -968(%rbp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -1072(%rbp)
movq $0, -1064(%rbp)
movq $0, -1056(%rbp)
movq $0, -1048(%rbp)
movq $0, -1040(%rbp)
movq $0, -1032(%rbp)
movq $0, -1024(%rbp)
leaq -1016(%rbp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -1072(%rbp)
movl $0, -1008(%rbp)
movq -1144(%rbp), %rbx
movq -1152(%rbp), %r12
leaq -984(%rbp), %rax
movq %rax, -1000(%rbp)
testq %r12, %r12
jne .L41
testq %rbx, %rbx
jne .L123
.L41:
movq %rbx, -1168(%rbp)
cmpq $15, %rbx
ja .L124
cmpq $1, %rbx
jne .L45
movzbl (%r12), %eax
movb %al, -984(%rbp)
.L46:
movq -1168(%rbp), %rax
movq %rax, -992(%rbp)
movq -1000(%rbp), %rdx
movb $0, (%rdx,%rax)
movl $8, -1008(%rbp)
leaq -1072(%rbp), %rdi
movl $0, %ecx
movl $0, %edx
movq -1000(%rbp), %rsi
.LEHB3:
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@PLT
.LEHE3:
jmp .L125
.L123:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L126
leaq .LC11(%rip), %rdi
.LEHB4:
call _ZSt19__throw_logic_errorPKc@PLT
.L108:
endbr64
movq %rax, %rbx
jmp .L49
.L126:
call __stack_chk_fail@PLT
.L124:
leaq -1168(%rbp), %rsi
leaq -1000(%rbp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE4:
movq %rax, %rdi
movq %rax, -1000(%rbp)
movq -1168(%rbp), %rax
movq %rax, -984(%rbp)
.L44:
movq %rbx, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L46
.L45:
testq %rbx, %rbx
je .L46
leaq -984(%rbp), %rdi
jmp .L44
.L109:
endbr64
movq %rax, %rbx
leaq -1000(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L49:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -1072(%rbp)
leaq -1016(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
.L50:
movq 8+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -1088(%rbp)
movq -24(%rax), %rax
movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, -1088(%rbp,%rax)
movq $0, -1080(%rbp)
.L54:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -968(%rbp)
leaq -968(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L55:
leaq -1120(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq -1152(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L95:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L96
call __stack_chk_fail@PLT
.L125:
leaq -1072(%rbp), %rsi
leaq -968(%rbp), %rdi
.LEHB5:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE5:
jmp .L127
.L107:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -1072(%rbp)
movq -1000(%rbp), %rdi
leaq -984(%rbp), %rax
cmpq %rax, %rdi
je .L53
movq -984(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L53:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -1072(%rbp)
leaq -1016(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
jmp .L50
.L106:
endbr64
movq %rax, %rbx
jmp .L54
.L127:
movq -1144(%rbp), %rdx
movq -1152(%rbp), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB6:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L128
cmpb $0, 56(%r12)
je .L58
movzbl 67(%r12), %esi
.L59:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L129
.L128:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L130
call _ZSt16__throw_bad_castv@PLT
.L103:
endbr64
movq %rax, %rbx
leaq -1088(%rbp), %rdi
call _ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L55
.L130:
call __stack_chk_fail@PLT
.L58:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L59
.L129:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq -1152(%rbp), %rdi
movl $11, %ecx
movl $0, %edx
leaq .LC12(%rip), %rsi
call _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@PLT
cmpq $-1, %rax
je .L60
leaq -1120(%rbp), %rsi
leaq -1088(%rbp), %rdi
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
movq %rax, %rdi
leaq -1208(%rbp), %rsi
call _ZNSirsERi@PLT
.LEHE6:
jmp .L61
.L60:
leaq -1152(%rbp), %rdi
movl $16, %ecx
movl $0, %edx
leaq .LC13(%rip), %rsi
call _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@PLT
cmpq $-1, %rax
jne .L131
.L61:
movq %r14, -1088(%rbp)
movq %r15, -968(%rbp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -1072(%rbp)
movq -1000(%rbp), %rdi
leaq -984(%rbp), %rax
cmpq %rax, %rdi
je .L62
movq -984(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L62:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -1072(%rbp)
leaq -1016(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -1088(%rbp)
movq -24(%rax), %rax
movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, -1088(%rbp,%rax)
movq $0, -1080(%rbp)
movq %r13, -968(%rbp)
leaq -968(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq -576(%rbp), %rax
movq -24(%rax), %rax
movq -336(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L37
.L38:
cmpb $0, 56(%rbx)
je .L65
movzbl 67(%rbx), %edx
.L66:
movsbl %dl, %edx
leaq -1152(%rbp), %rsi
leaq -576(%rbp), %rdi
.LEHB7:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
.LEHE7:
jmp .L132
.L131:
leaq -1120(%rbp), %rsi
leaq -1088(%rbp), %rdi
.LEHB8:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
movq %rax, %rdi
leaq -1204(%rbp), %rsi
call _ZNSirsERi@PLT
.LEHE8:
jmp .L61
.L37:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L133
.LEHB9:
call _ZSt16__throw_bad_castv@PLT
.L104:
endbr64
movq %rax, %rbx
jmp .L55
.L133:
call __stack_chk_fail@PLT
.L65:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE9:
movl %eax, %edx
jmp .L66
.L132:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L63
cmpq $10, -1144(%rbp)
je .L134
.L39:
leaq -1088(%rbp), %rbx
leaq -968(%rbp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
movq %r13, -968(%rbp)
movq $0, -752(%rbp)
movb $0, -744(%rbp)
movb $0, -743(%rbp)
movq $0, -736(%rbp)
movq $0, -728(%rbp)
movq $0, -720(%rbp)
movq $0, -712(%rbp)
movq 8+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -1088(%rbp)
movq -24(%rax), %rax
movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, -1088(%rbp,%rax)
movq $0, -1080(%rbp)
movq -1088(%rbp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB10:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE10:
jmp .L135
.L122:
movl -1208(%rbp), %eax
testl %eax, %eax
jle .L68
movl -1204(%rbp), %edx
testl %edx, %edx
jle .L68
imull %edx, %eax
movslq %eax, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, %rcx
movl $0, %ebx
leaq -576(%rbp), %r12
jmp .L71
.L68:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.LEHB11:
call __fprintf_chk@PLT
movl -1204(%rbp), %r8d
movl -1208(%rbp), %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC17(%rip), %rdi
call system@PLT
jmp .L136
.L138:
addl $1, %ebx
movq %r15, %rax
addq $4, %rax
movq %rax, %rcx
movl -1208(%rbp), %eax
imull -1204(%rbp), %eax
cmpl %ebx, %eax
jle .L137
.L71:
movq %rcx, %r15
movq %rcx, %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L138
.L137:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
call clock@PLT
movq -1224(%rbp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC18(%rip), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -1204(%rbp), %edx
movl -1208(%rbp), %esi
movq %r14, %rdi
call _ZL11printMatrixPfii
movl $16, %ecx
movl $16, %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -1208(%rbp), %eax
imull %eax, %eax
movslq %eax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testq %r14, %r14
je .L110
testq %rax, %rax
je .L110
leaq -1200(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
jmp .L139
.L110:
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC17(%rip), %rdi
call system@PLT
jmp .L140
.L139:
testl %eax, %eax
jne .L141
leaq -1192(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
jmp .L142
.L141:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC23(%rip), %r9
movl $158, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L142:
testl %eax, %eax
jne .L143
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq -1200(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
jmp .L144
.L143:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC26(%rip), %r9
movl $159, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L144:
testl %eax, %eax
jne .L145
movl -1208(%rbp), %eax
addl $15, %eax
movl $16, %ecx
cltd
idivl %ecx
movl %eax, -1180(%rbp)
movl %eax, -1176(%rbp)
movl $1, -1172(%rbp)
movl $16, -1168(%rbp)
movl $16, -1164(%rbp)
movl $1, -1160(%rbp)
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
jmp .L146
.L145:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC27(%rip), %r9
movl $162, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L146:
movl -1160(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -1168(%rbp), %rdx
movq -1180(%rbp), %rdi
movl -1172(%rbp), %esi
.cfi_escape 0x2e,0
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L77
movl -1204(%rbp), %ecx
movl -1208(%rbp), %edx
movq -1192(%rbp), %rsi
movq -1200(%rbp), %rdi
call _ZL15getDistance_gpuPfS_ii
.L77:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L147
movl $2, %ecx
movq %rbx, %rdx
movq -1192(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
jmp .L148
.L147:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC29(%rip), %r9
movl $171, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L148:
testl %eax, %eax
jne .L149
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
jmp .L150
.L149:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC30(%rip), %r9
movl $174, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L150:
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
movl -1208(%rbp), %esi
movl %esi, %edx
movq %r12, %rdi
call _ZL11printMatrixPfii
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE11:
leaq -1088(%rbp), %rdi
movl $16, %edx
leaq .LC34(%rip), %rsi
.LEHB12:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl $0, -1224(%rbp)
cmpl $0, -1208(%rbp)
jle .L81
leaq -1088(%rbp), %r13
leaq .LC36(%rip), %r15
jmp .L80
.L151:
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L82:
addl $1, %ebx
movl -1208(%rbp), %eax
cmpl %ebx, %eax
jle .L89
.L84:
movl -1224(%rbp), %ecx
imull %ecx, %eax
addl %ebx, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rax,4), %xmm0
movsd .LC35(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L82
leal 1(%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
jmp .L151
.L153:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L152
call _ZSt16__throw_bad_castv@PLT
.L105:
endbr64
movq %rax, %rbx
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L55
.L152:
call __stack_chk_fail@PLT
.L87:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L88
.L154:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, -1224(%rbp)
movl -1224(%rbp), %eax
cmpl %eax, -1208(%rbp)
jle .L81
.L80:
movl -1208(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L84
.L89:
movq -1088(%rbp), %rax
movq -24(%rax), %rax
movq -848(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L153
cmpb $0, 56(%rbx)
je .L87
movzbl 67(%rbx), %esi
.L88:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
jmp .L154
.L81:
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq -1200(%rbp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L155
movq -1192(%rbp), %rdi
call cudaFree@PLT
jmp .L156
.L155:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC37(%rip), %r9
movl $193, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L156:
testl %eax, %eax
jne .L157
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
.cfi_escape 0x2e,0
call cudaDeviceReset@PLT
jmp .L158
.L157:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC38(%rip), %r9
movl $194, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L158:
testl %eax, %eax
jne .L159
leaq .LC40(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
jmp .L160
.L159:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC39(%rip), %r9
movl $201, %r8d
leaq .LC24(%rip), %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
movl $1, %edi
call exit@PLT
.L160:
leaq .LC17(%rip), %rdi
.cfi_escape 0x2e,0
call system@PLT
.LEHE12:
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movl $0, %ebx
jmp .L70
.L136:
movl $1, %ebx
.L70:
leaq -1120(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq -1152(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L161
movl %ebx, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L140:
.cfi_restore_state
movl $1, %ebx
jmp .L70
.L102:
endbr64
movq %rax, %rbx
jmp .L95
.L96:
movq %rbx, %rdi
.LEHB13:
call _Unwind_Resume@PLT
.LEHE13:
.L161:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3859:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3859:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3859-.LLSDACSB3859
.LLSDACSB3859:
.uleb128 .LEHB0-.LFB3859
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3859
.uleb128 .LEHE1-.LEHB1
.uleb128 .L102-.LFB3859
.uleb128 0
.uleb128 .LEHB2-.LFB3859
.uleb128 .LEHE2-.LEHB2
.uleb128 .L104-.LFB3859
.uleb128 0
.uleb128 .LEHB3-.LFB3859
.uleb128 .LEHE3-.LEHB3
.uleb128 .L109-.LFB3859
.uleb128 0
.uleb128 .LEHB4-.LFB3859
.uleb128 .LEHE4-.LEHB4
.uleb128 .L108-.LFB3859
.uleb128 0
.uleb128 .LEHB5-.LFB3859
.uleb128 .LEHE5-.LEHB5
.uleb128 .L107-.LFB3859
.uleb128 0
.uleb128 .LEHB6-.LFB3859
.uleb128 .LEHE6-.LEHB6
.uleb128 .L103-.LFB3859
.uleb128 0
.uleb128 .LEHB7-.LFB3859
.uleb128 .LEHE7-.LEHB7
.uleb128 .L104-.LFB3859
.uleb128 0
.uleb128 .LEHB8-.LFB3859
.uleb128 .LEHE8-.LEHB8
.uleb128 .L103-.LFB3859
.uleb128 0
.uleb128 .LEHB9-.LFB3859
.uleb128 .LEHE9-.LEHB9
.uleb128 .L104-.LFB3859
.uleb128 0
.uleb128 .LEHB10-.LFB3859
.uleb128 .LEHE10-.LEHB10
.uleb128 .L106-.LFB3859
.uleb128 0
.uleb128 .LEHB11-.LFB3859
.uleb128 .LEHE11-.LEHB11
.uleb128 .L104-.LFB3859
.uleb128 0
.uleb128 .LEHB12-.LFB3859
.uleb128 .LEHE12-.LEHB12
.uleb128 .L105-.LFB3859
.uleb128 0
.uleb128 .LEHB13-.LFB3859
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.LLSDACSE3859:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC18:
.long 0
.long 1093567616
.align 8
.LC35:
.long 858993459
.long 1070805811
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* Face Factor Distance
* (MP3, Fall 2019, GPU Programming/Yifan Liu)
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
#include <fstream>
#include <ctime>
#include <string>
#include <sstream>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP3 takes a (m x k) matrix M \n" \
"and compute the distance betwen rows and save teh result if two rows' distance is smaller than 0.3\n" \
"The values of m, k must be >= 1.\n" \
"\n" \
"Usage: mp3 m k\n"
/* Tile size*/
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
cudaError_t err = (e); \
if (err != cudaSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/*getDistance calculate the distance among rows*/
__global__ static void getDistance_gpu(float *d_M, float *d_P, int m, int k) {
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
if(row >= m || col >= m)
return;
if(row == col){
d_P[row*m+col] = 100;
return;
}
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += pow(d_M[row*k+i] - d_M[col*k+i], 2);
}
expected = sqrt(expected);
d_P[row*m+col] = expected;
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. */
int main()
{
/* read in m and k here */
std::cout << "Loading matrices...\n";
clock_t begin = clock();
int m, k;
std::ifstream in1;
in1.open("descriptor.txt");
if(in1.is_open())
printf("File opened successfully\n");
else
printf("File opened unsuccessfully\n");
std::string line, temp;
// read in m and k
while ((std::getline(in1, line))){
if (line == "end header")
break;
std::istringstream ss(line);
std::cout << line << std::endl;
if(line.find("line_number")!=-1)
ss >> temp >> m;
else if(line.find("vector_dimension")!=-1)
ss >> temp >> k;
}
printf("The matrix is %d x %d\n", m, k);
if (m < 1 || k < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m or k (%d, %d)\n", m, k);
system("Pause");
return EXIT_FAILURE;
}
size_t bytesForM = m * k * sizeof(float);
float *h_M = (float *)malloc(bytesForM);
/* Fill M (on host) */
for (int i = 0; i < m*k; ++i)
in1 >> h_M[i];
in1.close();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Reading input file took %f seconds\n", elapsed_secs);
printf("M =\n"); printMatrix(h_M, m, k);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), P is (m x m) */
/********************************************/
size_t bytesForP = m * m * sizeof(float);
float *h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
system("Pause");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_P;
CUDA_CHECK(cudaMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(cudaMalloc((void **)&d_P, bytesForP));
/* Copy M to device global memory */
CUDA_CHECK(cudaMemcpy(d_M, h_M, bytesForM, cudaMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((m+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host\n");
getDistance_gpu<<<dimGrid, dimBlock>>>(d_M, d_P, m, k);
CUDA_CHECK(cudaDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(cudaMemcpy(h_P, d_P, bytesForP, cudaMemcpyDeviceToHost));
printf(" product received from host\n");
printf("P =\n"); printMatrix(h_P, m, m);
printf("Saving result\n");
std::ofstream out;
out.open("matrix.txt");
for (int i = 0; i < m; i++){
for (int j = 0; j < m; j++){
if (h_P[i*m+j] < 0.3)
out << j+1 << " ";
}
out << std::endl;
}
out.close();
/* Free device global memory */
CUDA_CHECK(cudaFree(d_M));
CUDA_CHECK(cudaFree(d_P));
/* Free host memory */
free(h_M);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(cudaDeviceReset());
printf("Done\n");
system("Pause");
return EXIT_SUCCESS;
}
|
/*
* Face Factor Distance
* (MP3, Fall 2019, GPU Programming/Yifan Liu)
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
#include <fstream>
#include <ctime>
#include <string>
#include <sstream>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP3 takes a (m x k) matrix M \n" \
"and compute the distance betwen rows and save teh result if two rows' distance is smaller than 0.3\n" \
"The values of m, k must be >= 1.\n" \
"\n" \
"Usage: mp3 m k\n"
/* Tile size*/
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
hipError_t err = (e); \
if (err != hipSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/*getDistance calculate the distance among rows*/
__global__ static void getDistance_gpu(float *d_M, float *d_P, int m, int k) {
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
if(row >= m || col >= m)
return;
if(row == col){
d_P[row*m+col] = 100;
return;
}
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += pow(d_M[row*k+i] - d_M[col*k+i], 2);
}
expected = sqrt(expected);
d_P[row*m+col] = expected;
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. */
int main()
{
/* read in m and k here */
std::cout << "Loading matrices...\n";
clock_t begin = clock();
int m, k;
std::ifstream in1;
in1.open("descriptor.txt");
if(in1.is_open())
printf("File opened successfully\n");
else
printf("File opened unsuccessfully\n");
std::string line, temp;
// read in m and k
while ((std::getline(in1, line))){
if (line == "end header")
break;
std::istringstream ss(line);
std::cout << line << std::endl;
if(line.find("line_number")!=-1)
ss >> temp >> m;
else if(line.find("vector_dimension")!=-1)
ss >> temp >> k;
}
printf("The matrix is %d x %d\n", m, k);
if (m < 1 || k < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m or k (%d, %d)\n", m, k);
system("Pause");
return EXIT_FAILURE;
}
size_t bytesForM = m * k * sizeof(float);
float *h_M = (float *)malloc(bytesForM);
/* Fill M (on host) */
for (int i = 0; i < m*k; ++i)
in1 >> h_M[i];
in1.close();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Reading input file took %f seconds\n", elapsed_secs);
printf("M =\n"); printMatrix(h_M, m, k);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), P is (m x m) */
/********************************************/
size_t bytesForP = m * m * sizeof(float);
float *h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
system("Pause");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_P;
CUDA_CHECK(hipMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(hipMalloc((void **)&d_P, bytesForP));
/* Copy M to device global memory */
CUDA_CHECK(hipMemcpy(d_M, h_M, bytesForM, hipMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((m+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host\n");
getDistance_gpu<<<dimGrid, dimBlock>>>(d_M, d_P, m, k);
CUDA_CHECK(hipDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(hipMemcpy(h_P, d_P, bytesForP, hipMemcpyDeviceToHost));
printf(" product received from host\n");
printf("P =\n"); printMatrix(h_P, m, m);
printf("Saving result\n");
std::ofstream out;
out.open("matrix.txt");
for (int i = 0; i < m; i++){
for (int j = 0; j < m; j++){
if (h_P[i*m+j] < 0.3)
out << j+1 << " ";
}
out << std::endl;
}
out.close();
/* Free device global memory */
CUDA_CHECK(hipFree(d_M));
CUDA_CHECK(hipFree(d_P));
/* Free host memory */
free(h_M);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(hipDeviceReset());
printf("Done\n");
system("Pause");
return EXIT_SUCCESS;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
* Face Factor Distance
* (MP3, Fall 2019, GPU Programming/Yifan Liu)
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <iostream>
#include <fstream>
#include <ctime>
#include <string>
#include <sstream>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP3 takes a (m x k) matrix M \n" \
"and compute the distance betwen rows and save teh result if two rows' distance is smaller than 0.3\n" \
"The values of m, k must be >= 1.\n" \
"\n" \
"Usage: mp3 m k\n"
/* Tile size*/
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
hipError_t err = (e); \
if (err != hipSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/*getDistance calculate the distance among rows*/
__global__ static void getDistance_gpu(float *d_M, float *d_P, int m, int k) {
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
if(row >= m || col >= m)
return;
if(row == col){
d_P[row*m+col] = 100;
return;
}
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += pow(d_M[row*k+i] - d_M[col*k+i], 2);
}
expected = sqrt(expected);
d_P[row*m+col] = expected;
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. */
int main()
{
/* read in m and k here */
std::cout << "Loading matrices...\n";
clock_t begin = clock();
int m, k;
std::ifstream in1;
in1.open("descriptor.txt");
if(in1.is_open())
printf("File opened successfully\n");
else
printf("File opened unsuccessfully\n");
std::string line, temp;
// read in m and k
while ((std::getline(in1, line))){
if (line == "end header")
break;
std::istringstream ss(line);
std::cout << line << std::endl;
if(line.find("line_number")!=-1)
ss >> temp >> m;
else if(line.find("vector_dimension")!=-1)
ss >> temp >> k;
}
printf("The matrix is %d x %d\n", m, k);
if (m < 1 || k < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m or k (%d, %d)\n", m, k);
system("Pause");
return EXIT_FAILURE;
}
size_t bytesForM = m * k * sizeof(float);
float *h_M = (float *)malloc(bytesForM);
/* Fill M (on host) */
for (int i = 0; i < m*k; ++i)
in1 >> h_M[i];
in1.close();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Reading input file took %f seconds\n", elapsed_secs);
printf("M =\n"); printMatrix(h_M, m, k);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), P is (m x m) */
/********************************************/
size_t bytesForP = m * m * sizeof(float);
float *h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
system("Pause");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_P;
CUDA_CHECK(hipMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(hipMalloc((void **)&d_P, bytesForP));
/* Copy M to device global memory */
CUDA_CHECK(hipMemcpy(d_M, h_M, bytesForM, hipMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((m+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host\n");
getDistance_gpu<<<dimGrid, dimBlock>>>(d_M, d_P, m, k);
CUDA_CHECK(hipDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(hipMemcpy(h_P, d_P, bytesForP, hipMemcpyDeviceToHost));
printf(" product received from host\n");
printf("P =\n"); printMatrix(h_P, m, m);
printf("Saving result\n");
std::ofstream out;
out.open("matrix.txt");
for (int i = 0; i < m; i++){
for (int j = 0; j < m; j++){
if (h_P[i*m+j] < 0.3)
out << j+1 << " ";
}
out << std::endl;
}
out.close();
/* Free device global memory */
CUDA_CHECK(hipFree(d_M));
CUDA_CHECK(hipFree(d_P));
/* Free host memory */
free(h_M);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(hipDeviceReset());
printf("Done\n");
system("Pause");
return EXIT_SUCCESS;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL15getDistance_gpuPfS_ii,"axG",@progbits,_ZL15getDistance_gpuPfS_ii,comdat
.globl _ZL15getDistance_gpuPfS_ii
.p2align 8
.type _ZL15getDistance_gpuPfS_ii,@function
_ZL15getDistance_gpuPfS_ii:
s_load_b32 s3, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v1
v_lshl_add_u32 v0, s14, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v5, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v1, 0x42c80000
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e64 v5, v0
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b64 s[6:7], s[0:1], 0x0
v_mul_lo_u32 v1, v0, s2
v_mul_lo_u32 v3, v5, s2
v_mov_b32_e32 v6, 0
s_mov_b32 s5, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.LBB0_4:
global_load_b32 v7, v[3:4], off
global_load_b32 v8, v[1:2], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v7, v7, v8
v_frexp_mant_f32_e64 v8, |v7|
v_frexp_exp_i32_f32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v8
v_cndmask_b32_e64 v10, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v8, v8, v10
v_cvt_f32_i32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v10, 1.0, v8
v_mul_f32_e32 v14, 0x3f317218, v9
v_cmp_neq_f32_e64 s6, 0x7f800000, |v7|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, -1.0, v10
v_dual_add_f32 v11, -1.0, v8 :: v_dual_sub_f32 v8, v8, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, v9, 0x3f317218, -v14
v_fmac_f32_e32 v13, 0xb102e308, v9
v_rcp_f32_e32 v12, v10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v15, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v10, v15
v_fma_f32 v10, v15, v10, -v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v15, v8
v_add_f32_e32 v8, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v16, v11, v8
v_sub_f32_e32 v11, v11, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v8, v9 :: v_dual_sub_f32 v8, v11, v8
v_sub_f32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v9, v8
v_add_f32_e32 v8, v16, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v12, v8
v_add_f32_e32 v9, v15, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v9, v15
v_dual_mul_f32 v11, v9, v9 :: v_dual_sub_f32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v10, v9, v9, -v11
v_ldexp_f32 v12, v9, 1
v_add_f32_e32 v15, v8, v8
v_ldexp_f32 v16, v8, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v9, v15
v_add_f32_e32 v15, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v17, s5, v15, 0x3e91f4c4
v_fmaak_f32 v17, v15, v17, 0x3ecccdef
v_sub_f32_e32 v11, v15, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v18, v9, v15 :: v_dual_mul_f32 v19, v15, v17
v_sub_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, v15, v9, -v18
v_fmac_f32_e32 v11, v15, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, v15, v17, -v19
v_fmac_f32_e32 v11, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v17
v_add_f32_e32 v10, v19, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v17, v10, v19
v_sub_f32_e32 v8, v8, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, 0x31739010, v8 :: v_dual_add_f32 v9, v18, v11
v_sub_f32_e32 v15, v9, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v18, 0x3f2aaaaa, v10 :: v_dual_sub_f32 v11, v11, v15
v_add_f32_e32 v15, 0xbf2aaaaa, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v10, v15
v_add_f32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v18, v8
v_sub_f32_e32 v15, v18, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v17, v9, v10 :: v_dual_add_f32 v8, v8, v15
v_fma_f32 v15, v9, v10, -v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v9, v8
v_fmac_f32_e32 v15, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v17, v15
v_add_f32_e32 v9, v12, v8
v_sub_f32_e32 v10, v8, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v15, v10 :: v_dual_sub_f32 v11, v9, v12
v_add_f32_e32 v10, v16, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v8, v11 :: v_dual_add_f32 v11, v14, v13
v_add_f32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v11, v14
v_add_f32_e32 v12, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v13, v10 :: v_dual_add_f32 v13, v11, v12
v_dual_sub_f32 v9, v12, v9 :: v_dual_sub_f32 v14, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v9, v13, v14
v_dual_sub_f32 v9, v11, v9 :: v_dual_sub_f32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v14, v10, v8 :: v_dual_add_f32 v9, v12, v9
v_sub_f32_e32 v11, v14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v14, v9
v_sub_f32_e32 v12, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v8, v8, v11 :: v_dual_add_f32 v11, v13, v9
v_sub_f32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v11, v13
v_dual_sub_f32 v9, v9, v12 :: v_dual_add_f32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v8, v9
v_add_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v9, v11
v_dual_sub_f32 v8, v8, v10 :: v_dual_add_f32 v11, v9, v9
v_mul_f32_e32 v12, 0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, v9, 2.0, -v11
v_fmac_f32_e32 v12, 2.0, v8
v_cmp_class_f32_e64 vcc_lo, v11, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v9, v12
v_add_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v9, v11, vcc_lo
v_sub_f32_e32 v9, v9, v11
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v9
v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
v_sub_f32_e32 v13, v10, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_mul_f32_e32 v14, 0x3fb8aa3b, v13
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v8, v12, v8
v_fma_f32 v15, v13, 0x3fb8aa3b, -v14
v_rndne_f32_e32 v16, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v15, 0x32a5705f, v13 :: v_dual_sub_f32 v14, v14, v16
v_cvt_i32_f32_e32 v11, v16
v_add_f32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v14, v14
s_waitcnt_depctr 0xfff
v_ldexp_f32 v9, v14, v11
v_cndmask_b32_e32 v9, 0, v9, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
v_fma_f32 v8, v9, v8, v9
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v8, v8, v9, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_cndmask_b32_e64 v8, 0x7f800000, |v8|, s6
v_cmp_neq_f32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, 0, v8, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_f32_e32 v6, v6, v7
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v6, 0
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
v_mul_f32_e32 v1, 0x4f800000, v6
v_cndmask_b32_e32 v1, v6, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, 1, v2
v_add_nc_u32_e32 v3, -1, v2
v_fma_f32 v7, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v3, v2, v1
v_cmp_ge_f32_e64 s2, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v2, v2, v3, s2
v_cmp_lt_f32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, v4, s2
v_mul_f32_e32 v3, 0x37800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v5, s3, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL15getDistance_gpuPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL15getDistance_gpuPfS_ii,"axG",@progbits,_ZL15getDistance_gpuPfS_ii,comdat
.Lfunc_end0:
.size _ZL15getDistance_gpuPfS_ii, .Lfunc_end0-_ZL15getDistance_gpuPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL15getDistance_gpuPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL15getDistance_gpuPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
template<int nt, int vt, typename func_t>
__global__ void index_elementwise_kernel(int N, func_t f) {
int tid = threadIdx.x;
int nv = nt * vt;
int idx = nv * blockIdx.x + tid;
#pragma unroll
for (int i = 0; i < vt; i++) {
if (idx < N) {
f(idx);
idx += nt;
}
}
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
template<int nt, int vt, typename func_t>
__global__ void index_elementwise_kernel(int N, func_t f) {
int tid = threadIdx.x;
int nv = nt * vt;
int idx = nv * blockIdx.x + tid;
#pragma unroll
for (int i = 0; i < vt; i++) {
if (idx < N) {
f(idx);
idx += nt;
}
}
}
|
.file "tmpxft_0012110a_00000000-6_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
template<int nt, int vt, typename func_t>
__global__ void index_elementwise_kernel(int N, func_t f) {
int tid = threadIdx.x;
int nv = nt * vt;
int idx = nv * blockIdx.x + tid;
#pragma unroll
for (int i = 0; i < vt; i++) {
if (idx < N) {
f(idx);
idx += nt;
}
}
}
|
#include <hip/hip_runtime.h>
template<int nt, int vt, typename func_t>
__global__ void index_elementwise_kernel(int N, func_t f) {
int tid = threadIdx.x;
int nv = nt * vt;
int idx = nv * blockIdx.x + tid;
#pragma unroll
for (int i = 0; i < vt; i++) {
if (idx < N) {
f(idx);
idx += nt;
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
template<int nt, int vt, typename func_t>
__global__ void index_elementwise_kernel(int N, func_t f) {
int tid = threadIdx.x;
int nv = nt * vt;
int idx = nv * blockIdx.x + tid;
#pragma unroll
for (int i = 0; i < vt; i++) {
if (idx < N) {
f(idx);
idx += nt;
}
}
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
template<int nt, int vt, typename func_t>
__global__ void index_elementwise_kernel(int N, func_t f) {
int tid = threadIdx.x;
int nv = nt * vt;
int idx = nv * blockIdx.x + tid;
#pragma unroll
for (int i = 0; i < vt; i++) {
if (idx < N) {
f(idx);
idx += nt;
}
}
}
|
.text
.file "index.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0012110a_00000000-6_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "index.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
//cout<<"About to lock 1"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 1"<<endl;
ret = *ptr;
//cout<<"About to unlock 1"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 1"<<endl;
return ret;
}
void set_shared_var_value(int *ptr, int val) {
//cout<<"About to lock 2"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 2"<<endl;
(*ptr) = val;
//cout<<"About to unlock 2"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 2"<<endl;
}
void dec_shared_var_value(int *ptr) {
//cout<<"About to lock 3"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 3"<<endl;
(*ptr)--;
//cout<<"About to unlock 3"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 3"<<endl;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
//cout<<"About to lock 1"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 1"<<endl;
ret = *ptr;
//cout<<"About to unlock 1"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 1"<<endl;
return ret;
}
void set_shared_var_value(int *ptr, int val) {
//cout<<"About to lock 2"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 2"<<endl;
(*ptr) = val;
//cout<<"About to unlock 2"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 2"<<endl;
}
void dec_shared_var_value(int *ptr) {
//cout<<"About to lock 3"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 3"<<endl;
(*ptr)--;
//cout<<"About to unlock 3"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 3"<<endl;
}
|
.file "tmpxft_001a8933_00000000-6_atomic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20get_shared_var_valuePi
.type _Z20get_shared_var_valuePi, @function
_Z20get_shared_var_valuePi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
movl (%rbx), %ebx
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z20get_shared_var_valuePi, .-_Z20get_shared_var_valuePi
.globl _Z20set_shared_var_valuePii
.type _Z20set_shared_var_valuePii, @function
_Z20set_shared_var_valuePii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
leaq lock(%rip), %r12
movq %r12, %rdi
call pthread_mutex_lock@PLT
movl %ebp, (%rbx)
movq %r12, %rdi
call pthread_mutex_unlock@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z20set_shared_var_valuePii, .-_Z20set_shared_var_valuePii
.globl _Z20dec_shared_var_valuePi
.type _Z20dec_shared_var_valuePi, @function
_Z20dec_shared_var_valuePi:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
subl $1, (%rbx)
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z20dec_shared_var_valuePi, .-_Z20dec_shared_var_valuePi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
//cout<<"About to lock 1"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 1"<<endl;
ret = *ptr;
//cout<<"About to unlock 1"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 1"<<endl;
return ret;
}
void set_shared_var_value(int *ptr, int val) {
//cout<<"About to lock 2"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 2"<<endl;
(*ptr) = val;
//cout<<"About to unlock 2"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 2"<<endl;
}
void dec_shared_var_value(int *ptr) {
//cout<<"About to lock 3"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 3"<<endl;
(*ptr)--;
//cout<<"About to unlock 3"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 3"<<endl;
}
|
/*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <hip/hip_runtime.h>
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
//cout<<"About to lock 1"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 1"<<endl;
ret = *ptr;
//cout<<"About to unlock 1"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 1"<<endl;
return ret;
}
void set_shared_var_value(int *ptr, int val) {
//cout<<"About to lock 2"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 2"<<endl;
(*ptr) = val;
//cout<<"About to unlock 2"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 2"<<endl;
}
void dec_shared_var_value(int *ptr) {
//cout<<"About to lock 3"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 3"<<endl;
(*ptr)--;
//cout<<"About to unlock 3"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 3"<<endl;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <hip/hip_runtime.h>
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
//cout<<"About to lock 1"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 1"<<endl;
ret = *ptr;
//cout<<"About to unlock 1"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 1"<<endl;
return ret;
}
void set_shared_var_value(int *ptr, int val) {
//cout<<"About to lock 2"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 2"<<endl;
(*ptr) = val;
//cout<<"About to unlock 2"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 2"<<endl;
}
void dec_shared_var_value(int *ptr) {
//cout<<"About to lock 3"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 3"<<endl;
(*ptr)--;
//cout<<"About to unlock 3"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 3"<<endl;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <hip/hip_runtime.h>
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
//cout<<"About to lock 1"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 1"<<endl;
ret = *ptr;
//cout<<"About to unlock 1"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 1"<<endl;
return ret;
}
void set_shared_var_value(int *ptr, int val) {
//cout<<"About to lock 2"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 2"<<endl;
(*ptr) = val;
//cout<<"About to unlock 2"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 2"<<endl;
}
void dec_shared_var_value(int *ptr) {
//cout<<"About to lock 3"<<endl;
pthread_mutex_lock(&lock);
//cout<<"lock 3"<<endl;
(*ptr)--;
//cout<<"About to unlock 3"<<endl;
pthread_mutex_unlock(&lock);
//cout<<"unlocked 3"<<endl;
}
|
.text
.file "atomic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20get_shared_var_valuePi # -- Begin function _Z20get_shared_var_valuePi
.p2align 4, 0x90
.type _Z20get_shared_var_valuePi,@function
_Z20get_shared_var_valuePi: # @_Z20get_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
movl (%rbx), %ebx
movl $lock, %edi
callq pthread_mutex_unlock
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20get_shared_var_valuePi, .Lfunc_end0-_Z20get_shared_var_valuePi
.cfi_endproc
# -- End function
.globl _Z20set_shared_var_valuePii # -- Begin function _Z20set_shared_var_valuePii
.p2align 4, 0x90
.type _Z20set_shared_var_valuePii,@function
_Z20set_shared_var_valuePii: # @_Z20set_shared_var_valuePii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
movl $lock, %edi
callq pthread_mutex_lock
movl %ebx, (%r14)
movl $lock, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end1:
.size _Z20set_shared_var_valuePii, .Lfunc_end1-_Z20set_shared_var_valuePii
.cfi_endproc
# -- End function
.globl _Z20dec_shared_var_valuePi # -- Begin function _Z20dec_shared_var_valuePi
.p2align 4, 0x90
.type _Z20dec_shared_var_valuePi,@function
_Z20dec_shared_var_valuePi: # @_Z20dec_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
decl (%rbx)
movl $lock, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end2:
.size _Z20dec_shared_var_valuePi, .Lfunc_end2-_Z20dec_shared_var_valuePi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym lock
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001a8933_00000000-6_atomic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20get_shared_var_valuePi
.type _Z20get_shared_var_valuePi, @function
_Z20get_shared_var_valuePi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
movl (%rbx), %ebx
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z20get_shared_var_valuePi, .-_Z20get_shared_var_valuePi
.globl _Z20set_shared_var_valuePii
.type _Z20set_shared_var_valuePii, @function
_Z20set_shared_var_valuePii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
leaq lock(%rip), %r12
movq %r12, %rdi
call pthread_mutex_lock@PLT
movl %ebp, (%rbx)
movq %r12, %rdi
call pthread_mutex_unlock@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z20set_shared_var_valuePii, .-_Z20set_shared_var_valuePii
.globl _Z20dec_shared_var_valuePi
.type _Z20dec_shared_var_valuePi, @function
_Z20dec_shared_var_valuePi:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
subl $1, (%rbx)
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z20dec_shared_var_valuePi, .-_Z20dec_shared_var_valuePi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "atomic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20get_shared_var_valuePi # -- Begin function _Z20get_shared_var_valuePi
.p2align 4, 0x90
.type _Z20get_shared_var_valuePi,@function
_Z20get_shared_var_valuePi: # @_Z20get_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
movl (%rbx), %ebx
movl $lock, %edi
callq pthread_mutex_unlock
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20get_shared_var_valuePi, .Lfunc_end0-_Z20get_shared_var_valuePi
.cfi_endproc
# -- End function
.globl _Z20set_shared_var_valuePii # -- Begin function _Z20set_shared_var_valuePii
.p2align 4, 0x90
.type _Z20set_shared_var_valuePii,@function
_Z20set_shared_var_valuePii: # @_Z20set_shared_var_valuePii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
movl $lock, %edi
callq pthread_mutex_lock
movl %ebx, (%r14)
movl $lock, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end1:
.size _Z20set_shared_var_valuePii, .Lfunc_end1-_Z20set_shared_var_valuePii
.cfi_endproc
# -- End function
.globl _Z20dec_shared_var_valuePi # -- Begin function _Z20dec_shared_var_valuePi
.p2align 4, 0x90
.type _Z20dec_shared_var_valuePi,@function
_Z20dec_shared_var_valuePi: # @_Z20dec_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
decl (%rbx)
movl $lock, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end2:
.size _Z20dec_shared_var_valuePi, .Lfunc_end2-_Z20dec_shared_var_valuePi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym lock
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__device__ double min2(double a, double b)
{
if (b < a) return b;
return a;
}
__device__ double max2(double a, double b)
{
if (b > a) return b;
return a;
}
__global__ void ConditionCFLKernel2D1 (double *Rsup, double *Rinf, double *Rmed, int nsec, int nrad, double *Vresidual, double *Vtheta, double *Vmoy, int FastTransport, double *SoundSpeed, double *Vrad, double *DT2D)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxrad, dxtheta, invdt1, invdt2, invdt3, invdt4, dvr, dvt, dt;
if (i > 0 && i<nrad && j<nsec){
dxrad = Rsup[i]-Rinf[i];
dxtheta = Rmed[i]*2.0*PI/(double)nsec;
if (FastTransport) Vresidual[i*nsec + j] = Vtheta[i*nsec + j]-Vmoy[i]; /* Fargo algorithm */
else Vresidual[i*nsec + j] = Vtheta[i*nsec + j]; /* Standard algorithm */
//Vresidual[i*nsec + nsec] = Vresidual[i*nsec];
invdt1 = SoundSpeed[i*nsec + j]/(min2(dxrad,dxtheta));
invdt2 = fabs(Vrad[i*nsec + j])/dxrad;
invdt3 = fabs(Vresidual[i*nsec + j])/dxtheta;
dvr = Vrad[(i+1)*nsec + j]-Vrad[i*nsec + j];
dvt = Vtheta[i*nsec + (j+1)%nsec]-Vtheta[i*nsec + j];
if (dvr >= 0.0) dvr = 1e-10;
else dvr = -dvr;
if (dvt >= 0.0) dvt = 1e-10;
else dvt = -dvt;
invdt4 = max2(dvr/dxrad, dvt/dxtheta);
invdt4*= 4.0*CVNR*CVNR;
dt = CFLSECURITY/sqrt(invdt1*invdt1+invdt2*invdt2+invdt3*invdt3+invdt4*invdt4);
DT2D[i*nsec + j] = dt; // array nrad*nsec size dt
}
}
|
.file "tmpxft_0017efb6_00000000-6_ConditionCFLKernel2D1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4min2dd
.type _Z4min2dd, @function
_Z4min2dd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4min2dd, .-_Z4min2dd
.globl _Z4max2dd
.type _Z4max2dd, @function
_Z4max2dd:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z4max2dd, .-_Z4max2dd
.globl _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
.type _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_, @function
_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 52(%rsp)
movl %r8d, 48(%rsp)
movq %r9, 40(%rsp)
movq 272(%rsp), %rax
movq %rax, 32(%rsp)
movq 280(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq 304(%rsp), %rax
movq %rax, 8(%rsp)
movq 312(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_, .-_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
.globl _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.type _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, @function
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .-_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__device__ double min2(double a, double b)
{
if (b < a) return b;
return a;
}
__device__ double max2(double a, double b)
{
if (b > a) return b;
return a;
}
__global__ void ConditionCFLKernel2D1 (double *Rsup, double *Rinf, double *Rmed, int nsec, int nrad, double *Vresidual, double *Vtheta, double *Vmoy, int FastTransport, double *SoundSpeed, double *Vrad, double *DT2D)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxrad, dxtheta, invdt1, invdt2, invdt3, invdt4, dvr, dvt, dt;
if (i > 0 && i<nrad && j<nsec){
dxrad = Rsup[i]-Rinf[i];
dxtheta = Rmed[i]*2.0*PI/(double)nsec;
if (FastTransport) Vresidual[i*nsec + j] = Vtheta[i*nsec + j]-Vmoy[i]; /* Fargo algorithm */
else Vresidual[i*nsec + j] = Vtheta[i*nsec + j]; /* Standard algorithm */
//Vresidual[i*nsec + nsec] = Vresidual[i*nsec];
invdt1 = SoundSpeed[i*nsec + j]/(min2(dxrad,dxtheta));
invdt2 = fabs(Vrad[i*nsec + j])/dxrad;
invdt3 = fabs(Vresidual[i*nsec + j])/dxtheta;
dvr = Vrad[(i+1)*nsec + j]-Vrad[i*nsec + j];
dvt = Vtheta[i*nsec + (j+1)%nsec]-Vtheta[i*nsec + j];
if (dvr >= 0.0) dvr = 1e-10;
else dvr = -dvr;
if (dvt >= 0.0) dvt = 1e-10;
else dvt = -dvt;
invdt4 = max2(dvr/dxrad, dvt/dxtheta);
invdt4*= 4.0*CVNR*CVNR;
dt = CFLSECURITY/sqrt(invdt1*invdt1+invdt2*invdt2+invdt3*invdt3+invdt4*invdt4);
DT2D[i*nsec + j] = dt; // array nrad*nsec size dt
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__device__ double min2(double a, double b)
{
if (b < a) return b;
return a;
}
__device__ double max2(double a, double b)
{
if (b > a) return b;
return a;
}
__global__ void ConditionCFLKernel2D1 (double *Rsup, double *Rinf, double *Rmed, int nsec, int nrad, double *Vresidual, double *Vtheta, double *Vmoy, int FastTransport, double *SoundSpeed, double *Vrad, double *DT2D)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxrad, dxtheta, invdt1, invdt2, invdt3, invdt4, dvr, dvt, dt;
if (i > 0 && i<nrad && j<nsec){
dxrad = Rsup[i]-Rinf[i];
dxtheta = Rmed[i]*2.0*PI/(double)nsec;
if (FastTransport) Vresidual[i*nsec + j] = Vtheta[i*nsec + j]-Vmoy[i]; /* Fargo algorithm */
else Vresidual[i*nsec + j] = Vtheta[i*nsec + j]; /* Standard algorithm */
//Vresidual[i*nsec + nsec] = Vresidual[i*nsec];
invdt1 = SoundSpeed[i*nsec + j]/(min2(dxrad,dxtheta));
invdt2 = fabs(Vrad[i*nsec + j])/dxrad;
invdt3 = fabs(Vresidual[i*nsec + j])/dxtheta;
dvr = Vrad[(i+1)*nsec + j]-Vrad[i*nsec + j];
dvt = Vtheta[i*nsec + (j+1)%nsec]-Vtheta[i*nsec + j];
if (dvr >= 0.0) dvr = 1e-10;
else dvr = -dvr;
if (dvt >= 0.0) dvt = 1e-10;
else dvt = -dvt;
invdt4 = max2(dvr/dxrad, dvt/dxtheta);
invdt4*= 4.0*CVNR*CVNR;
dt = CFLSECURITY/sqrt(invdt1*invdt1+invdt2*invdt2+invdt3*invdt3+invdt4*invdt4);
DT2D[i*nsec + j] = dt; // array nrad*nsec size dt
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__device__ double min2(double a, double b)
{
if (b < a) return b;
return a;
}
__device__ double max2(double a, double b)
{
if (b > a) return b;
return a;
}
__global__ void ConditionCFLKernel2D1 (double *Rsup, double *Rinf, double *Rmed, int nsec, int nrad, double *Vresidual, double *Vtheta, double *Vmoy, int FastTransport, double *SoundSpeed, double *Vrad, double *DT2D)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxrad, dxtheta, invdt1, invdt2, invdt3, invdt4, dvr, dvt, dt;
if (i > 0 && i<nrad && j<nsec){
dxrad = Rsup[i]-Rinf[i];
dxtheta = Rmed[i]*2.0*PI/(double)nsec;
if (FastTransport) Vresidual[i*nsec + j] = Vtheta[i*nsec + j]-Vmoy[i]; /* Fargo algorithm */
else Vresidual[i*nsec + j] = Vtheta[i*nsec + j]; /* Standard algorithm */
//Vresidual[i*nsec + nsec] = Vresidual[i*nsec];
invdt1 = SoundSpeed[i*nsec + j]/(min2(dxrad,dxtheta));
invdt2 = fabs(Vrad[i*nsec + j])/dxrad;
invdt3 = fabs(Vresidual[i*nsec + j])/dxtheta;
dvr = Vrad[(i+1)*nsec + j]-Vrad[i*nsec + j];
dvt = Vtheta[i*nsec + (j+1)%nsec]-Vtheta[i*nsec + j];
if (dvr >= 0.0) dvr = 1e-10;
else dvr = -dvr;
if (dvt >= 0.0) dvt = 1e-10;
else dvt = -dvt;
invdt4 = max2(dvr/dxrad, dvt/dxtheta);
invdt4*= 4.0*CVNR*CVNR;
dt = CFLSECURITY/sqrt(invdt1*invdt1+invdt2*invdt2+invdt3*invdt3+invdt4*invdt4);
DT2D[i*nsec + j] = dt; // array nrad*nsec size dt
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.globl _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.p2align 8
.type _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@function
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s5, v3
v_cmp_lt_i32_e64 s3, 0, v3
v_cmp_gt_i32_e64 s2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
v_mov_b32_e32 v4, 0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x38
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 3, v[3:4]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v9, vcc_lo
global_load_b64 v[1:2], v[1:2], off
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[12:13], v[6:7], off
global_load_b64 v[6:7], v[14:15], off
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[10:11], v[10:11], off
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[6:7], -v[10:11]
.LBB0_3:
s_waitcnt vmcnt(1)
v_add_f64 v[10:11], v[12:13], v[12:13]
s_ashr_i32 s5, s4, 31
s_mov_b32 s7, 0x400921fb
s_add_i32 s6, s4, s5
v_add_nc_u32_e32 v15, 1, v0
s_xor_b32 s5, s6, s5
v_mul_lo_u32 v3, v3, s4
v_cvt_f32_u32_e32 v12, s5
s_sub_i32 s6, 0, s5
v_ashrrev_i32_e32 v20, 31, v15
s_load_b128 s[8:11], s[0:1], 0x40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v12, v12
v_add_nc_u32_e32 v15, v15, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v15, v15, v20
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
v_cvt_u32_f32_e32 v14, v12
v_cvt_f64_i32_e32 v[12:13], s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v16, s6, v14
s_mov_b32 s6, 0x54442d18
v_mul_f64 v[10:11], v[10:11], s[6:7]
s_load_b64 s[6:7], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v16, v14, v16
s_load_b64 s[0:1], s[0:1], 0x50
v_add_nc_u32_e32 v14, v14, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v14, v15, v14
v_mul_lo_u32 v14, v14, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v16, v15, v14
v_subrev_nc_u32_e32 v17, s5, v16
v_cmp_le_u32_e32 vcc_lo, s5, v16
v_div_scale_f64 v[14:15], null, v[12:13], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v17, v16, v17 :: v_dual_add_nc_u32 v16, v3, v0
v_subrev_nc_u32_e32 v18, s5, v17
v_cmp_le_u32_e32 vcc_lo, s5, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v0, v17, v18, vcc_lo
v_ashrrev_i32_e32 v17, 31, v16
v_add_nc_u32_e32 v18, s4, v16
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s6, v8
v_xor_b32_e32 v0, v0, v20
v_lshlrev_b64 v[16:17], 3, v[16:17]
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v20
v_lshlrev_b64 v[18:19], 3, v[18:19]
v_add_co_u32 v22, vcc_lo, s10, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v20, v0, v3
v_add_co_ci_u32_e32 v23, vcc_lo, s11, v17, vcc_lo
v_add_co_u32 v26, vcc_lo, s2, v16
v_ashrrev_i32_e32 v21, 31, v20
s_waitcnt vmcnt(0)
global_store_b64 v[8:9], v[6:7], off
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v17, vcc_lo
v_rcp_f64_e32 v[24:25], v[14:15]
v_lshlrev_b64 v[6:7], 3, v[20:21]
v_add_co_u32 v8, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v19, vcc_lo
v_add_f64 v[0:1], v[1:2], -v[4:5]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b64 v[18:19], v[22:23], off
global_load_b64 v[8:9], v[8:9], off
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[20:21], v[26:27], off
v_add_co_u32 v26, vcc_lo, s8, v16
v_add_co_ci_u32_e32 v27, vcc_lo, s9, v17, vcc_lo
global_load_b64 v[26:27], v[26:27], off
v_fma_f64 v[22:23], -v[14:15], v[24:25], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[22:23], v[24:25], v[22:23], v[24:25]
v_add_co_u32 v24, vcc_lo, s6, v16
v_add_co_ci_u32_e32 v25, vcc_lo, s7, v17, vcc_lo
v_div_scale_f64 v[30:31], vcc_lo, v[10:11], v[12:13], v[10:11]
global_load_b64 v[24:25], v[24:25], off
v_fma_f64 v[28:29], -v[14:15], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[22:23], v[22:23], v[28:29], v[22:23]
v_mul_f64 v[28:29], v[30:31], v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[14:15], v[28:29], v[30:31]
v_div_fmas_f64 v[14:15], v[14:15], v[22:23], v[28:29]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[14:15], v[12:13], v[10:11]
s_waitcnt vmcnt(5)
v_and_b32_e32 v10, 0x7fffffff, v19
s_waitcnt vmcnt(4)
v_add_f64 v[4:5], v[8:9], -v[18:19]
v_mov_b32_e32 v9, v18
s_waitcnt vmcnt(2)
v_add_f64 v[6:7], v[6:7], -v[20:21]
s_delay_alu instid0(VALU_DEP_2)
v_div_scale_f64 v[13:14], null, v[0:1], v[0:1], v[9:10]
v_cmp_lt_f64_e32 vcc_lo, v[2:3], v[0:1]
v_cmp_nle_f64_e64 s2, 0, v[4:5]
v_xor_b32_e32 v15, 0x80000000, v5
v_cmp_nle_f64_e64 s3, 0, v[6:7]
v_xor_b32_e32 v28, 0x80000000, v7
v_rcp_f64_e32 v[36:37], v[13:14]
v_dual_cndmask_b32 v8, v1, v3 :: v_dual_cndmask_b32 v7, v0, v2
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1)
v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[26:27]
v_div_scale_f64 v[54:55], vcc_lo, v[26:27], v[7:8], v[26:27]
v_cndmask_b32_e64 v5, 0x3ddb7cdf, v15, s2
s_waitcnt vmcnt(0)
v_dual_mov_b32 v20, v24 :: v_dual_and_b32 v21, 0x7fffffff, v25
v_cndmask_b32_e64 v4, 0xd9d7bdbb, v4, s2
v_cndmask_b32_e64 v29, 0x3ddb7cdf, v28, s3
v_cndmask_b32_e64 v28, 0xd9d7bdbb, v6, s3
v_div_scale_f64 v[9:10], s2, v[9:10], v[0:1], v[9:10]
v_div_scale_f64 v[22:23], null, v[2:3], v[2:3], v[20:21]
v_div_scale_f64 v[30:31], null, v[0:1], v[0:1], v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_1)
v_div_scale_f64 v[32:33], null, v[2:3], v[2:3], v[28:29]
v_fma_f64 v[46:47], -v[13:14], v[36:37], 1.0
v_div_scale_f64 v[20:21], s3, v[20:21], v[2:3], v[20:21]
v_rcp_f64_e32 v[34:35], v[11:12]
v_rcp_f64_e32 v[38:39], v[22:23]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_f64_e32 v[40:41], v[30:31]
v_rcp_f64_e32 v[42:43], v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_fma_f64 v[36:37], v[36:37], v[46:47], v[36:37]
v_fma_f64 v[44:45], -v[11:12], v[34:35], 1.0
v_fma_f64 v[48:49], -v[22:23], v[38:39], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[50:51], -v[30:31], v[40:41], 1.0
v_fma_f64 v[52:53], -v[32:33], v[42:43], 1.0
v_fma_f64 v[46:47], -v[13:14], v[36:37], 1.0
v_fma_f64 v[34:35], v[34:35], v[44:45], v[34:35]
v_fma_f64 v[38:39], v[38:39], v[48:49], v[38:39]
v_fma_f64 v[40:41], v[40:41], v[50:51], v[40:41]
v_fma_f64 v[42:43], v[42:43], v[52:53], v[42:43]
v_fma_f64 v[36:37], v[36:37], v[46:47], v[36:37]
v_div_scale_f64 v[46:47], s5, v[28:29], v[2:3], v[28:29]
v_fma_f64 v[44:45], -v[11:12], v[34:35], 1.0
v_fma_f64 v[48:49], -v[22:23], v[38:39], 1.0
v_fma_f64 v[50:51], -v[30:31], v[40:41], 1.0
v_fma_f64 v[52:53], -v[32:33], v[42:43], 1.0
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[34:35], v[34:35], v[44:45], v[34:35]
v_div_scale_f64 v[44:45], s4, v[4:5], v[0:1], v[4:5]
v_fma_f64 v[38:39], v[38:39], v[48:49], v[38:39]
v_fma_f64 v[40:41], v[40:41], v[50:51], v[40:41]
v_mul_f64 v[50:51], v[9:10], v[36:37]
v_fma_f64 v[42:43], v[42:43], v[52:53], v[42:43]
v_mul_f64 v[48:49], v[54:55], v[34:35]
v_mul_f64 v[52:53], v[20:21], v[38:39]
v_mul_f64 v[56:57], v[44:45], v[40:41]
v_fma_f64 v[9:10], -v[13:14], v[50:51], v[9:10]
v_mul_f64 v[58:59], v[46:47], v[42:43]
v_fma_f64 v[11:12], -v[11:12], v[48:49], v[54:55]
v_fma_f64 v[13:14], -v[22:23], v[52:53], v[20:21]
v_fma_f64 v[20:21], -v[30:31], v[56:57], v[44:45]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[22:23], -v[32:33], v[58:59], v[46:47]
v_div_fmas_f64 v[11:12], v[11:12], v[34:35], v[48:49]
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0xf212d772
v_div_fmas_f64 v[9:10], v[9:10], v[36:37], v[50:51]
s_mov_b32 vcc_lo, s3
s_mov_b32 s3, 0x401fcf41
v_div_fmas_f64 v[13:14], v[13:14], v[38:39], v[52:53]
s_mov_b32 vcc_lo, s4
v_div_fmas_f64 v[20:21], v[20:21], v[40:41], v[56:57]
s_mov_b32 vcc_lo, s5
v_div_fmas_f64 v[22:23], v[22:23], v[42:43], v[58:59]
v_div_fixup_f64 v[6:7], v[11:12], v[7:8], v[26:27]
v_div_fixup_f64 v[9:10], v[9:10], v[0:1], |v[18:19]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[0:1], v[20:21], v[0:1], v[4:5]
v_div_fixup_f64 v[4:5], v[22:23], v[2:3], v[28:29]
v_div_fixup_f64 v[2:3], v[13:14], v[2:3], |v[24:25]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[8:9], v[9:10], v[9:10]
v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[6:7], v[8:9]
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_mul_f64 v[0:1], v[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[2:3], v[6:7]
v_fma_f64 v[0:1], v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_lshlrev_b32_e32 v2, 8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[0:1], v[0:1], v2
v_rsq_f64_e32 v[2:3], v[0:1]
s_waitcnt_depctr 0xfff
v_mul_f64 v[4:5], v[0:1], v[2:3]
v_mul_f64 v[2:3], v[2:3], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
v_cndmask_b32_e64 v4, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[2:3], v[2:3], v4
v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 0.5
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_div_scale_f64 v[6:7], vcc_lo, 0.5, v[0:1], 0.5
v_mul_f64 v[8:9], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 0.5
v_add_co_u32 v2, vcc_lo, s0, v16
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v17, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 60
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .Lfunc_end0-_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 60
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__device__ double min2(double a, double b)
{
if (b < a) return b;
return a;
}
__device__ double max2(double a, double b)
{
if (b > a) return b;
return a;
}
__global__ void ConditionCFLKernel2D1 (double *Rsup, double *Rinf, double *Rmed, int nsec, int nrad, double *Vresidual, double *Vtheta, double *Vmoy, int FastTransport, double *SoundSpeed, double *Vrad, double *DT2D)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxrad, dxtheta, invdt1, invdt2, invdt3, invdt4, dvr, dvt, dt;
if (i > 0 && i<nrad && j<nsec){
dxrad = Rsup[i]-Rinf[i];
dxtheta = Rmed[i]*2.0*PI/(double)nsec;
if (FastTransport) Vresidual[i*nsec + j] = Vtheta[i*nsec + j]-Vmoy[i]; /* Fargo algorithm */
else Vresidual[i*nsec + j] = Vtheta[i*nsec + j]; /* Standard algorithm */
//Vresidual[i*nsec + nsec] = Vresidual[i*nsec];
invdt1 = SoundSpeed[i*nsec + j]/(min2(dxrad,dxtheta));
invdt2 = fabs(Vrad[i*nsec + j])/dxrad;
invdt3 = fabs(Vresidual[i*nsec + j])/dxtheta;
dvr = Vrad[(i+1)*nsec + j]-Vrad[i*nsec + j];
dvt = Vtheta[i*nsec + (j+1)%nsec]-Vtheta[i*nsec + j];
if (dvr >= 0.0) dvr = 1e-10;
else dvr = -dvr;
if (dvt >= 0.0) dvt = 1e-10;
else dvt = -dvt;
invdt4 = max2(dvr/dxrad, dvt/dxtheta);
invdt4*= 4.0*CVNR*CVNR;
dt = CFLSECURITY/sqrt(invdt1*invdt1+invdt2*invdt2+invdt3*invdt3+invdt4*invdt4);
DT2D[i*nsec + j] = dt; // array nrad*nsec size dt
}
}
|
.text
.file "ConditionCFLKernel2D1.hip"
.globl _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_ # -- Begin function _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.p2align 4, 0x90
.type _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@function
_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_: # @_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .Lfunc_end0-_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@object # @_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.section .rodata,"a",@progbits
.globl _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.p2align 3, 0x0
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_:
.quad _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.size _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0017efb6_00000000-6_ConditionCFLKernel2D1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4min2dd
.type _Z4min2dd, @function
_Z4min2dd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4min2dd, .-_Z4min2dd
.globl _Z4max2dd
.type _Z4max2dd, @function
_Z4max2dd:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z4max2dd, .-_Z4max2dd
.globl _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
.type _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_, @function
_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 52(%rsp)
movl %r8d, 48(%rsp)
movq %r9, 40(%rsp)
movq 272(%rsp), %rax
movq %rax, 32(%rsp)
movq 280(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq 304(%rsp), %rax
movq %rax, 8(%rsp)
movq 312(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_, .-_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
.globl _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.type _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, @function
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .-_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "ConditionCFLKernel2D1.hip"
.globl _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_ # -- Begin function _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.p2align 4, 0x90
.type _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@function
_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_: # @_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .Lfunc_end0-_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@object # @_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.section .rodata,"a",@progbits
.globl _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.p2align 3, 0x0
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_:
.quad _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.size _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void TanhBackKernel(float* Z, float* dZ, int size){
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < size){
float t = (Z[id]);
dZ[id] = dZ[id] * (1-t*t) ;
}
}
|
code for sm_80
Function : _Z14TanhBackKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ FFMA R0, -R2, R2, 1 ; /* 0x3f80000002007423 */
/* 0x004fc80000000102 */
/*00d0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x008fca0000400000 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void TanhBackKernel(float* Z, float* dZ, int size){
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < size){
float t = (Z[id]);
dZ[id] = dZ[id] * (1-t*t) ;
}
}
|
.file "tmpxft_000136e9_00000000-6_TanhBackKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i
.type _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i, @function
_Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14TanhBackKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i, .-_Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i
.globl _Z14TanhBackKernelPfS_i
.type _Z14TanhBackKernelPfS_i, @function
_Z14TanhBackKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14TanhBackKernelPfS_i, .-_Z14TanhBackKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14TanhBackKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14TanhBackKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void TanhBackKernel(float* Z, float* dZ, int size){
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < size){
float t = (Z[id]);
dZ[id] = dZ[id] * (1-t*t) ;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void TanhBackKernel(float* Z, float* dZ, int size){
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < size){
float t = (Z[id]);
dZ[id] = dZ[id] * (1-t*t) ;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void TanhBackKernel(float* Z, float* dZ, int size){
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < size){
float t = (Z[id]);
dZ[id] = dZ[id] * (1-t*t) ;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14TanhBackKernelPfS_i
.globl _Z14TanhBackKernelPfS_i
.p2align 8
.type _Z14TanhBackKernelPfS_i,@function
_Z14TanhBackKernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_fma_f32 v2, -v2, v2, 1.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14TanhBackKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14TanhBackKernelPfS_i, .Lfunc_end0-_Z14TanhBackKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14TanhBackKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14TanhBackKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void TanhBackKernel(float* Z, float* dZ, int size){
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < size){
float t = (Z[id]);
dZ[id] = dZ[id] * (1-t*t) ;
}
}
|
.text
.file "TanhBackKernel.hip"
.globl _Z29__device_stub__TanhBackKernelPfS_i # -- Begin function _Z29__device_stub__TanhBackKernelPfS_i
.p2align 4, 0x90
.type _Z29__device_stub__TanhBackKernelPfS_i,@function
_Z29__device_stub__TanhBackKernelPfS_i: # @_Z29__device_stub__TanhBackKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14TanhBackKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__TanhBackKernelPfS_i, .Lfunc_end0-_Z29__device_stub__TanhBackKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14TanhBackKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14TanhBackKernelPfS_i,@object # @_Z14TanhBackKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z14TanhBackKernelPfS_i
.p2align 3, 0x0
_Z14TanhBackKernelPfS_i:
.quad _Z29__device_stub__TanhBackKernelPfS_i
.size _Z14TanhBackKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14TanhBackKernelPfS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__TanhBackKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14TanhBackKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z14TanhBackKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ FFMA R0, -R2, R2, 1 ; /* 0x3f80000002007423 */
/* 0x004fc80000000102 */
/*00d0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x008fca0000400000 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14TanhBackKernelPfS_i
.globl _Z14TanhBackKernelPfS_i
.p2align 8
.type _Z14TanhBackKernelPfS_i,@function
_Z14TanhBackKernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_fma_f32 v2, -v2, v2, 1.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14TanhBackKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14TanhBackKernelPfS_i, .Lfunc_end0-_Z14TanhBackKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14TanhBackKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14TanhBackKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000136e9_00000000-6_TanhBackKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i
.type _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i, @function
_Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14TanhBackKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i, .-_Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i
.globl _Z14TanhBackKernelPfS_i
.type _Z14TanhBackKernelPfS_i, @function
_Z14TanhBackKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14TanhBackKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14TanhBackKernelPfS_i, .-_Z14TanhBackKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14TanhBackKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14TanhBackKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "TanhBackKernel.hip"
.globl _Z29__device_stub__TanhBackKernelPfS_i # -- Begin function _Z29__device_stub__TanhBackKernelPfS_i
.p2align 4, 0x90
.type _Z29__device_stub__TanhBackKernelPfS_i,@function
_Z29__device_stub__TanhBackKernelPfS_i: # @_Z29__device_stub__TanhBackKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14TanhBackKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__TanhBackKernelPfS_i, .Lfunc_end0-_Z29__device_stub__TanhBackKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14TanhBackKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14TanhBackKernelPfS_i,@object # @_Z14TanhBackKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z14TanhBackKernelPfS_i
.p2align 3, 0x0
_Z14TanhBackKernelPfS_i:
.quad _Z29__device_stub__TanhBackKernelPfS_i
.size _Z14TanhBackKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14TanhBackKernelPfS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__TanhBackKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14TanhBackKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
extern "C" {
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
}
|
code for sm_80
Function : Vector_Addition
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x63, PT ; /* 0x000000630600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
extern "C" {
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
}
|
.file "tmpxft_0010bdaf_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.type _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, @function
_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq Vector_Addition(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, .-_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.globl Vector_Addition
.type Vector_Addition, @function
Vector_Addition:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size Vector_Addition, .-Vector_Addition
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Vector_Addition"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq Vector_Addition(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
extern "C" {
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
}
|
#include <hip/hip_runtime.h>
extern "C" {
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
extern "C" {
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Vector_Addition
.globl Vector_Addition
.p2align 8
.type Vector_Addition,@function
Vector_Addition:
s_cmpk_gt_i32 s15, 0x63
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Vector_Addition
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Vector_Addition, .Lfunc_end0-Vector_Addition
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Vector_Addition
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: Vector_Addition.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
extern "C" {
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
}
|
.text
.file "kernel.hip"
.globl __device_stub__Vector_Addition # -- Begin function __device_stub__Vector_Addition
.p2align 4, 0x90
.type __device_stub__Vector_Addition,@function
__device_stub__Vector_Addition: # @__device_stub__Vector_Addition
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $Vector_Addition, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__Vector_Addition, .Lfunc_end0-__device_stub__Vector_Addition
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Vector_Addition, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Vector_Addition,@object # @Vector_Addition
.section .rodata,"a",@progbits
.globl Vector_Addition
.p2align 3, 0x0
Vector_Addition:
.quad __device_stub__Vector_Addition
.size Vector_Addition, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Vector_Addition"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Vector_Addition
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Vector_Addition
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : Vector_Addition
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x63, PT ; /* 0x000000630600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Vector_Addition
.globl Vector_Addition
.p2align 8
.type Vector_Addition,@function
Vector_Addition:
s_cmpk_gt_i32 s15, 0x63
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Vector_Addition
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Vector_Addition, .Lfunc_end0-Vector_Addition
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Vector_Addition
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: Vector_Addition.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0010bdaf_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.type _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, @function
_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq Vector_Addition(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, .-_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.globl Vector_Addition
.type Vector_Addition, @function
Vector_Addition:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size Vector_Addition, .-Vector_Addition
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Vector_Addition"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq Vector_Addition(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl __device_stub__Vector_Addition # -- Begin function __device_stub__Vector_Addition
.p2align 4, 0x90
.type __device_stub__Vector_Addition,@function
__device_stub__Vector_Addition: # @__device_stub__Vector_Addition
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $Vector_Addition, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__Vector_Addition, .Lfunc_end0-__device_stub__Vector_Addition
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Vector_Addition, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Vector_Addition,@object # @Vector_Addition
.section .rodata,"a",@progbits
.globl Vector_Addition
.p2align 3, 0x0
Vector_Addition:
.quad __device_stub__Vector_Addition
.size Vector_Addition, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Vector_Addition"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Vector_Addition
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Vector_Addition
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#define N 16
extern __global__
void cudaMatMul(int C[N][N], int A[N][N], int B[N][N], int n);
int main(int argc, char** argv)
{
int* A[N];
int* B[N];
// result
int* C[N];
// cuda guys
int* A_c[N];
int* B_c[N];
int* C_c[N];
// cuda result placed in this value
int* ret[N];
int i = 0;
int j = 0;
// malloc individual arrays
for(i = 0; i < N; i++)
{
//A[i] = (int*) malloc(N * sizeof(int));
A[i] = (int*) malloc(N * sizeof(int));
B[i] = (int*) malloc(N * sizeof(int));
C[i] = (int*) malloc(N * sizeof(int));
cudaMalloc((void**) &A_c[i], N * sizeof(int));
cudaMalloc((void**) &B_c[i], N * sizeof(int));
cudaMalloc((void**) &C_c[i], N * sizeof(int));
ret[i] = (int*) malloc(N * sizeof(int));
}
// init data
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
{
A[i][j] = i + j;
B[i][j] = i * j;
C[i][j] = 0;
//ret[i][j] = 0;
//printf("%d ", B[i][j]);
}
//printf("\n");
}
// COPY TO device memory
for(i = 0; i < N; i++)
{
cudaMemcpy(A_c[i], A[i], N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(B_c[i], B[i], N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(C_c[i], C[i], N * sizeof(int), cudaMemcpyHostToDevice);
}
//cudaMemcpy2D ( void* dst, size_t dpitch, const void* src, size_t spitch, size_t width, size_t height, cudaMemcpyKind kind )
//Copies data between host and device.
//dim3 dimBlock(N, N);
cudaMatMul<<<1, 1>>>((int (*) [16])C_c, (int (*) [16])A_c, (int (*) [16])B_c, N);
// for(i = 0; i < N; i++)
// {
// cudaMemcpy(ret[i], C_c[i], N * sizeof(int), cudaMemcpyDeviceToHost);
// }
cudaMemcpy2D(ret, N * sizeof(int), C_c, N * sizeof(int), N * sizeof(int), N * sizeof(int), cudaMemcpyDeviceToHost);
// printf("segfault before?\n");
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
printf("%d ", ret[i][j]);
printf("\n");
}
fflush(stdout);
// free arrays
for(i = 0; i < N; i++)
{
free(A[i]);
free(B[i]);
free(C[i]);
cudaFree(A_c[i]);
cudaFree(B_c[i]);
cudaFree(C_c[i]);
free(ret[i]);
}
return 0;
}
extern __global__
void cudaMatMul(int c[N][N], int a[N][N], int b[N][N], int n)
{
int i = 0;
int j = 0;
int k = 0;
// mat mul
for(i = 0; i < n; i++)
for(j = 0; j < n; j++)
for(k = 0; k < n; k++)
c[i][j] += a[i][k] * b[k][j];
}
|
code for sm_80
Function : _Z10cudaMatMulPA16_iS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0080*/ UIADD3 UR4, UP0, UR4, 0x80, URZ ; /* 0x0000008004047890 */
/* 0x000fe2000ff1e03f */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IADD3 R9, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a10 */
/* 0x000fe20007ffe1ff */
/*00c0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc800087fe43f */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x40 ; /* 0x00000040ff037424 */
/* 0x00ffe200078e00ff */
/*00e0*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011408 */
/*00f0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e00ff */
/*0100*/ IMAD.WIDE R2, R8, R3, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fca00078e0203 */
/*0110*/ IADD3 R10, P0, R2, 0x8, RZ ; /* 0x00000008020a7810 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R13, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0d7210 */
/* 0x020fe400007fe4ff */
/*0130*/ IMAD.SHL.U32 R16, R8.reuse, 0x40, RZ ; /* 0x0000004008107824 */
/* 0x040fe200078e00ff */
/*0140*/ SHF.L.U64.HI R21, R8, 0x6, R11 ; /* 0x0000000608157819 */
/* 0x000fe2000001020b */
/*0150*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0160*/ SHF.R.S32.HI R15, RZ, 0x1f, R12 ; /* 0x0000001fff0f7819 */
/* 0x000fe4000001140c */
/*0170*/ IADD3 R2, P0, R16, c[0x0][0x160], RZ ; /* 0x0000580010027a10 */
/* 0x00ffc80007f1e0ff */
/*0180*/ IADD3.X R3, R21, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590015037a10 */
/* 0x000fca00007fe4ff */
/*0190*/ IMAD.WIDE R2, R12, 0x4, R2 ; /* 0x000000040c027825 */
/* 0x000fe200078e0202 */
/*01a0*/ @!P1 BRA 0xba0 ; /* 0x000009f000009947 */
/* 0x020fea0003800000 */
/*01b0*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*01c0*/ LDG.E R19, [R2.64] ; /* 0x0000000602137981 */
/* 0x000162000c1e1900 */
/*01d0*/ LEA R4, P2, R12.reuse, UR4, 0x2 ; /* 0x000000040c047c11 */
/* 0x040fe2000f8410ff */
/*01e0*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*01f0*/ IMAD.MOV.U32 R17, RZ, RZ, R9 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0009 */
/*0200*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000a */
/*0220*/ LEA.HI.X R5, R12, UR5, R15, 0x2, P2 ; /* 0x000000050c057c11 */
/* 0x000fcc00090f140f */
/*0230*/ @!P0 BRA 0xa00 ; /* 0x000007c000008947 */
/* 0x001fea0003800000 */
/*0240*/ ISETP.GT.AND P2, PT, R17, 0xc, PT ; /* 0x0000000c1100780c */
/* 0x000fe40003f44270 */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0260*/ @!P2 BRA 0x720 ; /* 0x000004b00000a947 */
/* 0x000fea0003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ LDG.E R18, [R4.64+-0x80] ; /* 0xffff800604127981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R20, [R6.64+-0x8] ; /* 0xfffff80606147981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ IMAD R19, R18, R20, R19 ; /* 0x0000001412137224 */
/* 0x026fca00078e0213 */
/*02b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*02c0*/ LDG.E R18, [R4.64+-0x40] ; /* 0xffffc00604127981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R20, [R6.64+-0x4] ; /* 0xfffffc0606147981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x004fca00078e0213 */
/*02f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0300*/ LDG.E R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R20, [R6.64] ; /* 0x0000000606147981 */
/* 0x000ea4000c1e1900 */
/*0320*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0330*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0340*/ LDG.E R18, [R4.64+0x40] ; /* 0x0000400604127981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040606147981 */
/* 0x000e24000c1e1900 */
/*0360*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0380*/ LDG.E R18, [R4.64+0x80] ; /* 0x0000800604127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R20, [R6.64+0x8] ; /* 0x0000080606147981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*03b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*03c0*/ LDG.E R18, [R4.64+0xc0] ; /* 0x0000c00604127981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0606147981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*03f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0400*/ LDG.E R18, [R4.64+0x100] ; /* 0x0001000604127981 */
/* 0x000e28000c1e1900 */
/*0410*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100606147981 */
/* 0x000e24000c1e1900 */
/*0420*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*0430*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0440*/ LDG.E R18, [R4.64+0x140] ; /* 0x0001400604127981 */
/* 0x000e68000c1e1900 */
/*0450*/ LDG.E R20, [R6.64+0x14] ; /* 0x0000140606147981 */
/* 0x000e64000c1e1900 */
/*0460*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*0470*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0480*/ LDG.E R18, [R4.64+0x180] ; /* 0x0001800604127981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R20, [R6.64+0x18] ; /* 0x0000180606147981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*04b0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*04c0*/ LDG.E R18, [R4.64+0x1c0] ; /* 0x0001c00604127981 */
/* 0x000e28000c1e1900 */
/*04d0*/ LDG.E R20, [R6.64+0x1c] ; /* 0x00001c0606147981 */
/* 0x000e24000c1e1900 */
/*04e0*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*04f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0500*/ LDG.E R18, [R4.64+0x200] ; /* 0x0002000604127981 */
/* 0x000e68000c1e1900 */
/*0510*/ LDG.E R20, [R6.64+0x20] ; /* 0x0000200606147981 */
/* 0x000e64000c1e1900 */
/*0520*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*0530*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0540*/ LDG.E R18, [R4.64+0x240] ; /* 0x0002400604127981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R20, [R6.64+0x24] ; /* 0x0000240606147981 */
/* 0x000ea4000c1e1900 */
/*0560*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0570*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0580*/ LDG.E R18, [R4.64+0x280] ; /* 0x0002800604127981 */
/* 0x000e28000c1e1900 */
/*0590*/ LDG.E R20, [R6.64+0x28] ; /* 0x0000280606147981 */
/* 0x000e24000c1e1900 */
/*05a0*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*05b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*05c0*/ LDG.E R18, [R4.64+0x2c0] ; /* 0x0002c00604127981 */
/* 0x000e68000c1e1900 */
/*05d0*/ LDG.E R20, [R6.64+0x2c] ; /* 0x00002c0606147981 */
/* 0x000e64000c1e1900 */
/*05e0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0600*/ LDG.E R18, [R4.64+0x300] ; /* 0x0003000604127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R20, [R6.64+0x30] ; /* 0x0000300606147981 */
/* 0x000ea2000c1e1900 */
/*0620*/ IADD3 R17, R17, -0x10, RZ ; /* 0xfffffff011117810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101906 */
/*0650*/ LDG.E R18, [R4.64+0x340] ; /* 0x0003400604127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R20, [R6.64+0x34] ; /* 0x0000340606147981 */
/* 0x000e22000c1e1900 */
/*0670*/ ISETP.GT.AND P2, PT, R17, 0xc, PT ; /* 0x0000000c1100780c */
/* 0x000fe40003f44270 */
/*0680*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*0690*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fe200078e0219 */
/*06a0*/ IADD3 R18, P4, R4, 0x400, RZ ; /* 0x0000040004127810 */
/* 0x000fc40007f9e0ff */
/*06b0*/ IADD3 R20, P3, R6, 0x40, RZ ; /* 0x0000004006147810 */
/* 0x000fe40007f7e0ff */
/*06c0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e2000c101906 */
/*06d0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe200020e0605 */
/*06e0*/ MOV R4, R18 ; /* 0x0000001200047202 */
/* 0x000fe20000000f00 */
/*06f0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0607 */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0014 */
/*0710*/ @P2 BRA 0x280 ; /* 0xfffffb6000002947 */
/* 0x000fea000383ffff */
/*0720*/ ISETP.GT.AND P2, PT, R17, 0x4, PT ; /* 0x000000041100780c */
/* 0x000fda0003f44270 */
/*0730*/ @!P2 BRA 0x9e0 ; /* 0x000002a00000a947 */
/* 0x000fea0003800000 */
/*0740*/ LDG.E R18, [R4.64+-0x80] ; /* 0xffff800604127981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R20, [R6.64+-0x8] ; /* 0xfffff80606147981 */
/* 0x000ea4000c1e1900 */
/*0760*/ IMAD R19, R18, R20, R19 ; /* 0x0000001412137224 */
/* 0x026fca00078e0213 */
/*0770*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0780*/ LDG.E R18, [R4.64+-0x40] ; /* 0xffffc00604127981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R20, [R6.64+-0x4] ; /* 0xfffffc0606147981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x004fca00078e0213 */
/*07b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*07c0*/ LDG.E R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R20, [R6.64] ; /* 0x0000000606147981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*07f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0800*/ LDG.E R18, [R4.64+0x40] ; /* 0x0000400604127981 */
/* 0x000e28000c1e1900 */
/*0810*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040606147981 */
/* 0x000e24000c1e1900 */
/*0820*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0840*/ LDG.E R18, [R4.64+0x80] ; /* 0x0000800604127981 */
/* 0x000e68000c1e1900 */
/*0850*/ LDG.E R20, [R6.64+0x8] ; /* 0x0000080606147981 */
/* 0x000e64000c1e1900 */
/*0860*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*0870*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0880*/ LDG.E R18, [R4.64+0xc0] ; /* 0x0000c00604127981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0606147981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*08b0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*08c0*/ LDG.E R18, [R4.64+0x100] ; /* 0x0001000604127981 */
/* 0x000ee8000c1e1900 */
/*08d0*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100606147981 */
/* 0x000ee4000c1e1900 */
/*08e0*/ IMAD R27, R18, R20, R25 ; /* 0x00000014121b7224 */
/* 0x008fca00078e0219 */
/*08f0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101906 */
/*0900*/ LDG.E R18, [R4.64+0x140] ; /* 0x0001400604127981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R19, [R6.64+0x14] ; /* 0x0000140606137981 */
/* 0x0010e2000c1e1900 */
/*0920*/ IADD3 R20, P2, R6, 0x20, RZ ; /* 0x0000002006147810 */
/* 0x000fe40007f5e0ff */
/*0930*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0940*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe20007ffe0ff */
/*0950*/ IMAD.X R23, RZ, RZ, R7, P2 ; /* 0x000000ffff177224 */
/* 0x002fe200010e0607 */
/*0960*/ IADD3 R17, R17, -0x8, RZ ; /* 0xfffffff811117810 */
/* 0x000fe20007ffe0ff */
/*0970*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x001fc600078e0014 */
/*0980*/ MOV R7, R23 ; /* 0x0000001700077202 */
/* 0x000fe20000000f00 */
/*0990*/ IMAD R19, R18, R19, R27 ; /* 0x0000001312137224 */
/* 0x008fe200078e021b */
/*09a0*/ IADD3 R18, P3, R4, 0x200, RZ ; /* 0x0000020004127810 */
/* 0x000fc80007f7e0ff */
/*09b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e2000c101906 */
/*09c0*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20001ffe4ff */
/*09d0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0012 */
/*09e0*/ ISETP.NE.OR P0, PT, R17, RZ, P0 ; /* 0x000000ff1100720c */
/* 0x000fda0000705670 */
/*09f0*/ @!P0 BRA 0xba0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a00*/ LDG.E R18, [R4.64+-0x80] ; /* 0xffff800604127981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R20, [R6.64+-0x8] ; /* 0xfffff80606147981 */
/* 0x000ee4000c1e1900 */
/*0a20*/ IMAD R19, R18, R20, R19 ; /* 0x0000001412137224 */
/* 0x02efca00078e0213 */
/*0a30*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0a40*/ LDG.E R18, [R4.64+-0x40] ; /* 0xffffc00604127981 */
/* 0x000ea8000c1e1900 */
/*0a50*/ LDG.E R20, [R6.64+-0x4] ; /* 0xfffffc0606147981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x004fca00078e0213 */
/*0a70*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0a80*/ LDG.E R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ LDG.E R20, [R6.64] ; /* 0x0000000606147981 */
/* 0x000ea2000c1e1900 */
/*0aa0*/ IADD3 R17, R17, -0x4, RZ ; /* 0xfffffffc11117810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0ac0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101906 */
/*0ad0*/ LDG.E R18, [R4.64+0x40] ; /* 0x0000400604127981 */
/* 0x000e28000c1e1900 */
/*0ae0*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040606147981 */
/* 0x000e22000c1e1900 */
/*0af0*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f05270 */
/*0b00*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fe200078e0219 */
/*0b20*/ IADD3 R18, P3, R4, 0x100, RZ ; /* 0x0000010004127810 */
/* 0x000fc40007f7e0ff */
/*0b30*/ IADD3 R20, P2, R6, 0x10, RZ ; /* 0x0000001006147810 */
/* 0x000fe40007f5e0ff */
/*0b40*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e2000c101906 */
/*0b50*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0b60*/ MOV R4, R18 ; /* 0x0000001200047202 */
/* 0x000fe20000000f00 */
/*0b70*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0b80*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0014 */
/*0b90*/ @P0 BRA 0xa00 ; /* 0xfffffe6000000947 */
/* 0x002fea000383ffff */
/*0ba0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0bb0*/ @!P0 BRA 0xd40 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ HFMA2.MMA R5, -RZ, RZ, 0, 3.814697265625e-06 ; /* 0x00000040ff057435 */
/* 0x000fe200000001ff */
/*0bd0*/ IADD3 R16, P0, R16, c[0x0][0x168], RZ ; /* 0x00005a0010107a10 */
/* 0x000fc80007f1e0ff */
/*0be0*/ IADD3.X R17, R21, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0015117a10 */
/* 0x000fca00007fe4ff */
/*0bf0*/ IMAD.WIDE R4, R14, R5, c[0x0][0x170] ; /* 0x00005c000e047625 */
/* 0x000fca00078e0205 */
/*0c00*/ LEA R4, P0, R12, R4, 0x2 ; /* 0x000000040c047211 */
/* 0x000fc800078010ff */
/*0c10*/ LEA.HI.X R5, R12, R5, R15, 0x2, P0 ; /* 0x000000050c057211 */
/* 0x000fe200000f140f */
/*0c20*/ IMAD.WIDE R14, R14, 0x4, R16 ; /* 0x000000040e0e7825 */
/* 0x000fe400078e0210 */
/*0c30*/ LDG.E R16, [R2.64] ; /* 0x0000000602107981 */
/* 0x000ee8000c1e1900 */
/*0c40*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x000ee8000c1e1900 */
/*0c50*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ee2000c1e1900 */
/*0c60*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*0c70*/ IMAD R17, R6, R7, R16 ; /* 0x0000000706117224 */
/* 0x008fca00078e0210 */
/*0c80*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001ee000c101906 */
/*0c90*/ @!P0 BRA 0xd40 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ LDG.E R6, [R4.64+0x40] ; /* 0x0000400604067981 */
/* 0x000ee8000c1e1900 */
/*0cb0*/ LDG.E R7, [R14.64+0x4] ; /* 0x000004060e077981 */
/* 0x000ee2000c1e1900 */
/*0cc0*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*0cd0*/ IMAD R7, R6, R7, R17 ; /* 0x0000000706077224 */
/* 0x008fca00078e0211 */
/*0ce0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0007ee000c101906 */
/*0cf0*/ @!P0 BRA 0xd40 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0d00*/ LDG.E R4, [R4.64+0x80] ; /* 0x0000800604047981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R15, [R14.64+0x8] ; /* 0x000008060e0f7981 */
/* 0x000f24000c1e1900 */
/*0d20*/ IMAD R7, R4, R15, R7 ; /* 0x0000000f04077224 */
/* 0x018fca00078e0207 */
/*0d30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0007e4000c101906 */
/*0d40*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fda0003f06270 */
/*0d60*/ @!P0 BRA 0x130 ; /* 0xfffff3c000008947 */
/* 0x000fea000383ffff */
/*0d70*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0d80*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0d90*/ @!P0 BRA 0xd0 ; /* 0xfffff33000008947 */
/* 0x000fea000383ffff */
/*0da0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0db0*/ BRA 0xdb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#define N 16
extern __global__
void cudaMatMul(int C[N][N], int A[N][N], int B[N][N], int n);
int main(int argc, char** argv)
{
int* A[N];
int* B[N];
// result
int* C[N];
// cuda guys
int* A_c[N];
int* B_c[N];
int* C_c[N];
// cuda result placed in this value
int* ret[N];
int i = 0;
int j = 0;
// malloc individual arrays
for(i = 0; i < N; i++)
{
//A[i] = (int*) malloc(N * sizeof(int));
A[i] = (int*) malloc(N * sizeof(int));
B[i] = (int*) malloc(N * sizeof(int));
C[i] = (int*) malloc(N * sizeof(int));
cudaMalloc((void**) &A_c[i], N * sizeof(int));
cudaMalloc((void**) &B_c[i], N * sizeof(int));
cudaMalloc((void**) &C_c[i], N * sizeof(int));
ret[i] = (int*) malloc(N * sizeof(int));
}
// init data
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
{
A[i][j] = i + j;
B[i][j] = i * j;
C[i][j] = 0;
//ret[i][j] = 0;
//printf("%d ", B[i][j]);
}
//printf("\n");
}
// COPY TO device memory
for(i = 0; i < N; i++)
{
cudaMemcpy(A_c[i], A[i], N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(B_c[i], B[i], N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(C_c[i], C[i], N * sizeof(int), cudaMemcpyHostToDevice);
}
//cudaMemcpy2D ( void* dst, size_t dpitch, const void* src, size_t spitch, size_t width, size_t height, cudaMemcpyKind kind )
//Copies data between host and device.
//dim3 dimBlock(N, N);
cudaMatMul<<<1, 1>>>((int (*) [16])C_c, (int (*) [16])A_c, (int (*) [16])B_c, N);
// for(i = 0; i < N; i++)
// {
// cudaMemcpy(ret[i], C_c[i], N * sizeof(int), cudaMemcpyDeviceToHost);
// }
cudaMemcpy2D(ret, N * sizeof(int), C_c, N * sizeof(int), N * sizeof(int), N * sizeof(int), cudaMemcpyDeviceToHost);
// printf("segfault before?\n");
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
printf("%d ", ret[i][j]);
printf("\n");
}
fflush(stdout);
// free arrays
for(i = 0; i < N; i++)
{
free(A[i]);
free(B[i]);
free(C[i]);
cudaFree(A_c[i]);
cudaFree(B_c[i]);
cudaFree(C_c[i]);
free(ret[i]);
}
return 0;
}
extern __global__
void cudaMatMul(int c[N][N], int a[N][N], int b[N][N], int n)
{
int i = 0;
int j = 0;
int k = 0;
// mat mul
for(i = 0; i < n; i++)
for(j = 0; j < n; j++)
for(k = 0; k < n; k++)
c[i][j] += a[i][k] * b[k][j];
}
|
.file "tmpxft_0013fbe2_00000000-6_prac_cuda_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
.type _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i, @function
_Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10cudaMatMulPA16_iS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i, .-_Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
.globl _Z10cudaMatMulPA16_iS0_S0_i
.type _Z10cudaMatMulPA16_iS0_S0_i, @function
_Z10cudaMatMulPA16_iS0_S0_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cudaMatMulPA16_iS0_S0_i, .-_Z10cudaMatMulPA16_iS0_S0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $944, %rsp
.cfi_def_cfa_offset 992
movq %fs:40, %rax
movq %rax, 936(%rsp)
xorl %eax, %eax
movl $0, %ebx
leaq 416(%rsp), %rbp
.L12:
movl $64, %edi
call malloc@PLT
movq %rax, 32(%rsp,%rbx)
movl $64, %edi
call malloc@PLT
movq %rax, 160(%rsp,%rbx)
movl $64, %edi
call malloc@PLT
movq %rax, 288(%rsp,%rbx)
leaq 0(%rbp,%rbx), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 544(%rsp,%rbx), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 672(%rsp,%rbx), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $64, %edi
call malloc@PLT
movq %rax, 800(%rsp,%rbx)
addq $8, %rbx
cmpq $128, %rbx
jne .L12
movl $0, %r10d
.L13:
movq 32(%rsp,%r10,8), %r9
movq 160(%rsp,%r10,8), %r8
movq 288(%rsp,%r10,8), %rdi
movl %r10d, %ecx
movl $0, %edx
movl $0, %eax
.L14:
leal (%rcx,%rax), %esi
movl %esi, (%r9,%rax,4)
movl %edx, (%r8,%rax,4)
movl $0, (%rdi,%rax,4)
addq $1, %rax
addl %ecx, %edx
cmpq $16, %rax
jne .L14
addq $1, %r10
cmpq $16, %r10
jne .L13
movl $0, %ebx
.L15:
movq 32(%rsp,%rbx), %rsi
movq 416(%rsp,%rbx), %rdi
movl $1, %ecx
movl $64, %edx
call cudaMemcpy@PLT
movq 160(%rsp,%rbx), %rsi
movq 544(%rsp,%rbx), %rdi
movl $1, %ecx
movl $64, %edx
call cudaMemcpy@PLT
movq 288(%rsp,%rbx), %rsi
movq 672(%rsp,%rbx), %rdi
movl $1, %ecx
movl $64, %edx
call cudaMemcpy@PLT
addq $8, %rbx
cmpq $128, %rbx
jne .L15
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L16:
leaq 672(%rsp), %rdx
leaq 800(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 1000
pushq $2
.cfi_def_cfa_offset 1008
movl $64, %r9d
movl $64, %r8d
movl $64, %ecx
movl $64, %esi
movq %rbp, %rdi
call cudaMemcpy2D@PLT
leaq 944(%rsp), %r14
addq $16, %rsp
.cfi_def_cfa_offset 992
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L17:
movl $0, %ebx
.L18:
movq 0(%rbp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L18
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r14, %rbp
jne .L17
movq stdout(%rip), %rdi
call fflush@PLT
movl $0, %ebx
.L20:
movq 32(%rsp,%rbx), %rdi
call free@PLT
movq 160(%rsp,%rbx), %rdi
call free@PLT
movq 288(%rsp,%rbx), %rdi
call free@PLT
movq 416(%rsp,%rbx), %rdi
call cudaFree@PLT
movq 544(%rsp,%rbx), %rdi
call cudaFree@PLT
movq 672(%rsp,%rbx), %rdi
call cudaFree@PLT
movq 800(%rsp,%rbx), %rdi
call free@PLT
addq $8, %rbx
cmpq $128, %rbx
jne .L20
movq 936(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $944, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq 544(%rsp), %rdx
leaq 416(%rsp), %rsi
leaq 672(%rsp), %rdi
movl $16, %ecx
call _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
jmp .L16
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10cudaMatMulPA16_iS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudaMatMulPA16_iS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#define N 16
extern __global__
void cudaMatMul(int C[N][N], int A[N][N], int B[N][N], int n);
int main(int argc, char** argv)
{
int* A[N];
int* B[N];
// result
int* C[N];
// cuda guys
int* A_c[N];
int* B_c[N];
int* C_c[N];
// cuda result placed in this value
int* ret[N];
int i = 0;
int j = 0;
// malloc individual arrays
for(i = 0; i < N; i++)
{
//A[i] = (int*) malloc(N * sizeof(int));
A[i] = (int*) malloc(N * sizeof(int));
B[i] = (int*) malloc(N * sizeof(int));
C[i] = (int*) malloc(N * sizeof(int));
cudaMalloc((void**) &A_c[i], N * sizeof(int));
cudaMalloc((void**) &B_c[i], N * sizeof(int));
cudaMalloc((void**) &C_c[i], N * sizeof(int));
ret[i] = (int*) malloc(N * sizeof(int));
}
// init data
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
{
A[i][j] = i + j;
B[i][j] = i * j;
C[i][j] = 0;
//ret[i][j] = 0;
//printf("%d ", B[i][j]);
}
//printf("\n");
}
// COPY TO device memory
for(i = 0; i < N; i++)
{
cudaMemcpy(A_c[i], A[i], N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(B_c[i], B[i], N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(C_c[i], C[i], N * sizeof(int), cudaMemcpyHostToDevice);
}
//cudaMemcpy2D ( void* dst, size_t dpitch, const void* src, size_t spitch, size_t width, size_t height, cudaMemcpyKind kind )
//Copies data between host and device.
//dim3 dimBlock(N, N);
cudaMatMul<<<1, 1>>>((int (*) [16])C_c, (int (*) [16])A_c, (int (*) [16])B_c, N);
// for(i = 0; i < N; i++)
// {
// cudaMemcpy(ret[i], C_c[i], N * sizeof(int), cudaMemcpyDeviceToHost);
// }
cudaMemcpy2D(ret, N * sizeof(int), C_c, N * sizeof(int), N * sizeof(int), N * sizeof(int), cudaMemcpyDeviceToHost);
// printf("segfault before?\n");
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
printf("%d ", ret[i][j]);
printf("\n");
}
fflush(stdout);
// free arrays
for(i = 0; i < N; i++)
{
free(A[i]);
free(B[i]);
free(C[i]);
cudaFree(A_c[i]);
cudaFree(B_c[i]);
cudaFree(C_c[i]);
free(ret[i]);
}
return 0;
}
extern __global__
void cudaMatMul(int c[N][N], int a[N][N], int b[N][N], int n)
{
int i = 0;
int j = 0;
int k = 0;
// mat mul
for(i = 0; i < n; i++)
for(j = 0; j < n; j++)
for(k = 0; k < n; k++)
c[i][j] += a[i][k] * b[k][j];
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 16
extern __global__
void cudaMatMul(int C[N][N], int A[N][N], int B[N][N], int n);
int main(int argc, char** argv)
{
int* A[N];
int* B[N];
// result
int* C[N];
// cuda guys
int* A_c[N];
int* B_c[N];
int* C_c[N];
// cuda result placed in this value
int* ret[N];
int i = 0;
int j = 0;
// malloc individual arrays
for(i = 0; i < N; i++)
{
//A[i] = (int*) malloc(N * sizeof(int));
A[i] = (int*) malloc(N * sizeof(int));
B[i] = (int*) malloc(N * sizeof(int));
C[i] = (int*) malloc(N * sizeof(int));
hipMalloc((void**) &A_c[i], N * sizeof(int));
hipMalloc((void**) &B_c[i], N * sizeof(int));
hipMalloc((void**) &C_c[i], N * sizeof(int));
ret[i] = (int*) malloc(N * sizeof(int));
}
// init data
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
{
A[i][j] = i + j;
B[i][j] = i * j;
C[i][j] = 0;
//ret[i][j] = 0;
//printf("%d ", B[i][j]);
}
//printf("\n");
}
// COPY TO device memory
for(i = 0; i < N; i++)
{
hipMemcpy(A_c[i], A[i], N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(B_c[i], B[i], N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(C_c[i], C[i], N * sizeof(int), hipMemcpyHostToDevice);
}
//cudaMemcpy2D ( void* dst, size_t dpitch, const void* src, size_t spitch, size_t width, size_t height, cudaMemcpyKind kind )
//Copies data between host and device.
//dim3 dimBlock(N, N);
cudaMatMul<<<1, 1>>>((int (*) [16])C_c, (int (*) [16])A_c, (int (*) [16])B_c, N);
// for(i = 0; i < N; i++)
// {
// cudaMemcpy(ret[i], C_c[i], N * sizeof(int), cudaMemcpyDeviceToHost);
// }
hipMemcpy2D(ret, N * sizeof(int), C_c, N * sizeof(int), N * sizeof(int), N * sizeof(int), hipMemcpyDeviceToHost);
// printf("segfault before?\n");
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
printf("%d ", ret[i][j]);
printf("\n");
}
fflush(stdout);
// free arrays
for(i = 0; i < N; i++)
{
free(A[i]);
free(B[i]);
free(C[i]);
hipFree(A_c[i]);
hipFree(B_c[i]);
hipFree(C_c[i]);
free(ret[i]);
}
return 0;
}
extern __global__
void cudaMatMul(int c[N][N], int a[N][N], int b[N][N], int n)
{
int i = 0;
int j = 0;
int k = 0;
// mat mul
for(i = 0; i < n; i++)
for(j = 0; j < n; j++)
for(k = 0; k < n; k++)
c[i][j] += a[i][k] * b[k][j];
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 16
extern __global__
void cudaMatMul(int C[N][N], int A[N][N], int B[N][N], int n);
int main(int argc, char** argv)
{
int* A[N];
int* B[N];
// result
int* C[N];
// cuda guys
int* A_c[N];
int* B_c[N];
int* C_c[N];
// cuda result placed in this value
int* ret[N];
int i = 0;
int j = 0;
// malloc individual arrays
for(i = 0; i < N; i++)
{
//A[i] = (int*) malloc(N * sizeof(int));
A[i] = (int*) malloc(N * sizeof(int));
B[i] = (int*) malloc(N * sizeof(int));
C[i] = (int*) malloc(N * sizeof(int));
hipMalloc((void**) &A_c[i], N * sizeof(int));
hipMalloc((void**) &B_c[i], N * sizeof(int));
hipMalloc((void**) &C_c[i], N * sizeof(int));
ret[i] = (int*) malloc(N * sizeof(int));
}
// init data
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
{
A[i][j] = i + j;
B[i][j] = i * j;
C[i][j] = 0;
//ret[i][j] = 0;
//printf("%d ", B[i][j]);
}
//printf("\n");
}
// COPY TO device memory
for(i = 0; i < N; i++)
{
hipMemcpy(A_c[i], A[i], N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(B_c[i], B[i], N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(C_c[i], C[i], N * sizeof(int), hipMemcpyHostToDevice);
}
//cudaMemcpy2D ( void* dst, size_t dpitch, const void* src, size_t spitch, size_t width, size_t height, cudaMemcpyKind kind )
//Copies data between host and device.
//dim3 dimBlock(N, N);
cudaMatMul<<<1, 1>>>((int (*) [16])C_c, (int (*) [16])A_c, (int (*) [16])B_c, N);
// for(i = 0; i < N; i++)
// {
// cudaMemcpy(ret[i], C_c[i], N * sizeof(int), cudaMemcpyDeviceToHost);
// }
hipMemcpy2D(ret, N * sizeof(int), C_c, N * sizeof(int), N * sizeof(int), N * sizeof(int), hipMemcpyDeviceToHost);
// printf("segfault before?\n");
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
printf("%d ", ret[i][j]);
printf("\n");
}
fflush(stdout);
// free arrays
for(i = 0; i < N; i++)
{
free(A[i]);
free(B[i]);
free(C[i]);
hipFree(A_c[i]);
hipFree(B_c[i]);
hipFree(C_c[i]);
free(ret[i]);
}
return 0;
}
extern __global__
void cudaMatMul(int c[N][N], int a[N][N], int b[N][N], int n)
{
int i = 0;
int j = 0;
int k = 0;
// mat mul
for(i = 0; i < n; i++)
for(j = 0; j < n; j++)
for(k = 0; k < n; k++)
c[i][j] += a[i][k] * b[k][j];
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cudaMatMulPA16_iS0_S0_i
.globl _Z10cudaMatMulPA16_iS0_S0_i
.p2align 8
.type _Z10cudaMatMulPA16_iS0_S0_i,@function
_Z10cudaMatMulPA16_iS0_S0_i:
s_load_b32 s20, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s20, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, s3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mov_b64 s[8:9], s[2:3]
s_lshl_b64 s[10:11], s[2:3], 6
s_waitcnt lgkmcnt(0)
s_mov_b64 s[12:13], s[0:1]
s_mov_b32 s2, s3
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[2:3], 2
s_add_u32 s9, s4, s10
s_addc_u32 s16, s5, s11
s_add_u32 s14, s9, s14
s_addc_u32 s15, s16, s15
s_mov_b64 s[16:17], s[12:13]
global_load_b32 v1, v0, s[14:15]
s_mov_b64 s[18:19], s[6:7]
s_mov_b32 s9, s20
.LBB0_4:
s_clause 0x1
global_load_b32 v2, v0, s[18:19]
global_load_b32 v3, v0, s[16:17]
s_add_i32 s9, s9, -1
s_add_u32 s18, s18, 4
s_addc_u32 s19, s19, 0
s_add_u32 s16, s16, 64
s_addc_u32 s17, s17, 0
s_cmp_lg_u32 s9, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
global_store_b32 v0, v1, s[14:15]
s_cbranch_scc1 .LBB0_4
s_add_i32 s2, s2, 1
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s2, s20
s_cbranch_scc1 .LBB0_3
s_add_i32 s2, s8, 1
s_add_u32 s6, s6, 64
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s2, s20
s_cbranch_scc1 .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cudaMatMulPA16_iS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 21
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cudaMatMulPA16_iS0_S0_i, .Lfunc_end0-_Z10cudaMatMulPA16_iS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cudaMatMulPA16_iS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z10cudaMatMulPA16_iS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 16
extern __global__
void cudaMatMul(int C[N][N], int A[N][N], int B[N][N], int n);
int main(int argc, char** argv)
{
int* A[N];
int* B[N];
// result
int* C[N];
// cuda guys
int* A_c[N];
int* B_c[N];
int* C_c[N];
// cuda result placed in this value
int* ret[N];
int i = 0;
int j = 0;
// malloc individual arrays
for(i = 0; i < N; i++)
{
//A[i] = (int*) malloc(N * sizeof(int));
A[i] = (int*) malloc(N * sizeof(int));
B[i] = (int*) malloc(N * sizeof(int));
C[i] = (int*) malloc(N * sizeof(int));
hipMalloc((void**) &A_c[i], N * sizeof(int));
hipMalloc((void**) &B_c[i], N * sizeof(int));
hipMalloc((void**) &C_c[i], N * sizeof(int));
ret[i] = (int*) malloc(N * sizeof(int));
}
// init data
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
{
A[i][j] = i + j;
B[i][j] = i * j;
C[i][j] = 0;
//ret[i][j] = 0;
//printf("%d ", B[i][j]);
}
//printf("\n");
}
// COPY TO device memory
for(i = 0; i < N; i++)
{
hipMemcpy(A_c[i], A[i], N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(B_c[i], B[i], N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(C_c[i], C[i], N * sizeof(int), hipMemcpyHostToDevice);
}
//cudaMemcpy2D ( void* dst, size_t dpitch, const void* src, size_t spitch, size_t width, size_t height, cudaMemcpyKind kind )
//Copies data between host and device.
//dim3 dimBlock(N, N);
cudaMatMul<<<1, 1>>>((int (*) [16])C_c, (int (*) [16])A_c, (int (*) [16])B_c, N);
// for(i = 0; i < N; i++)
// {
// cudaMemcpy(ret[i], C_c[i], N * sizeof(int), cudaMemcpyDeviceToHost);
// }
hipMemcpy2D(ret, N * sizeof(int), C_c, N * sizeof(int), N * sizeof(int), N * sizeof(int), hipMemcpyDeviceToHost);
// printf("segfault before?\n");
for(i = 0; i < N; i++)
{
for(j = 0; j < N; j++)
printf("%d ", ret[i][j]);
printf("\n");
}
fflush(stdout);
// free arrays
for(i = 0; i < N; i++)
{
free(A[i]);
free(B[i]);
free(C[i]);
hipFree(A_c[i]);
hipFree(B_c[i]);
hipFree(C_c[i]);
free(ret[i]);
}
return 0;
}
extern __global__
void cudaMatMul(int c[N][N], int a[N][N], int b[N][N], int n)
{
int i = 0;
int j = 0;
int k = 0;
// mat mul
for(i = 0; i < n; i++)
for(j = 0; j < n; j++)
for(k = 0; k < n; k++)
c[i][j] += a[i][k] * b[k][j];
}
|
.text
.file "prac_cuda_matmul.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1016, %rsp # imm = 0x3F8
.cfi_def_cfa_offset 1040
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $64, %edi
callq malloc
movq %rax, 880(%rsp,%rbx)
movl $64, %edi
callq malloc
movq %rax, 752(%rsp,%rbx)
movl $64, %edi
callq malloc
movq %rax, 624(%rsp,%rbx)
leaq (%rsp,%rbx), %rdi
addq $496, %rdi # imm = 0x1F0
movl $64, %esi
callq hipMalloc
leaq (%rsp,%rbx), %rdi
addq $368, %rdi # imm = 0x170
movl $64, %esi
callq hipMalloc
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
movl $64, %esi
callq hipMalloc
movl $64, %edi
callq malloc
movq %rax, 240(%rsp,%rbx)
addq $8, %rbx
cmpq $128, %rbx
jne .LBB0_1
# %bb.2: # %.preheader54.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.preheader54
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq 880(%rsp,%rax,8), %rcx
movq 752(%rsp,%rax,8), %rdx
movq 624(%rsp,%rax,8), %rsi
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r8), %r9d
movl %r9d, (%rcx,%r8,4)
movl %edi, (%rdx,%r8,4)
movl $0, (%rsi,%r8,4)
incq %r8
addl %eax, %edi
cmpq $16, %r8
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
incq %rax
cmpq $16, %rax
jne .LBB0_3
# %bb.6: # %.preheader53.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_7: # %.preheader53
# =>This Inner Loop Header: Depth=1
movq 496(%rsp,%rbx), %rdi
movq 880(%rsp,%rbx), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 368(%rsp,%rbx), %rdi
movq 752(%rsp,%rbx), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 112(%rsp,%rbx), %rdi
movq 624(%rsp,%rbx), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
addq $8, %rbx
cmpq $128, %rbx
jne .LBB0_7
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
leaq 112(%rsp), %rax
movq %rax, 72(%rsp)
leaq 496(%rsp), %rax
movq %rax, 64(%rsp)
leaq 368(%rsp), %rax
movq %rax, 56(%rsp)
movl $16, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10cudaMatMulPA16_iS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 248(%rsp), %rdi
leaq 120(%rsp), %rdx
movl $64, %esi
movl $64, %ecx
movl $64, %r8d
movl $64, %r9d
pushq $2
.cfi_adjust_cfa_offset 8
callq hipMemcpy2D
addq $16, %rsp
.cfi_adjust_cfa_offset -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_12 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_12: # Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
movq 240(%rsp,%rbx,8), %rax
movl (%rax,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB0_12
# %bb.13: # in Loop: Header=BB0_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
cmpq $16, %rbx
jne .LBB0_11
# %bb.14:
movq stdout(%rip), %rdi
callq fflush
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_15: # =>This Inner Loop Header: Depth=1
movq 880(%rsp,%rbx), %rdi
callq free
movq 752(%rsp,%rbx), %rdi
callq free
movq 624(%rsp,%rbx), %rdi
callq free
movq 496(%rsp,%rbx), %rdi
callq hipFree
movq 368(%rsp,%rbx), %rdi
callq hipFree
movq 112(%rsp,%rbx), %rdi
callq hipFree
movq 240(%rsp,%rbx), %rdi
callq free
addq $8, %rbx
cmpq $128, %rbx
jne .LBB0_15
# %bb.16:
xorl %eax, %eax
addq $1016, %rsp # imm = 0x3F8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z25__device_stub__cudaMatMulPA16_iS0_S0_i # -- Begin function _Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.p2align 4, 0x90
.type _Z25__device_stub__cudaMatMulPA16_iS0_S0_i,@function
_Z25__device_stub__cudaMatMulPA16_iS0_S0_i: # @_Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10cudaMatMulPA16_iS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__cudaMatMulPA16_iS0_S0_i, .Lfunc_end1-_Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudaMatMulPA16_iS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cudaMatMulPA16_iS0_S0_i,@object # @_Z10cudaMatMulPA16_iS0_S0_i
.section .rodata,"a",@progbits
.globl _Z10cudaMatMulPA16_iS0_S0_i
.p2align 3, 0x0
_Z10cudaMatMulPA16_iS0_S0_i:
.quad _Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.size _Z10cudaMatMulPA16_iS0_S0_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudaMatMulPA16_iS0_S0_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cudaMatMulPA16_iS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10cudaMatMulPA16_iS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0080*/ UIADD3 UR4, UP0, UR4, 0x80, URZ ; /* 0x0000008004047890 */
/* 0x000fe2000ff1e03f */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IADD3 R9, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a10 */
/* 0x000fe20007ffe1ff */
/*00c0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc800087fe43f */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x40 ; /* 0x00000040ff037424 */
/* 0x00ffe200078e00ff */
/*00e0*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011408 */
/*00f0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e00ff */
/*0100*/ IMAD.WIDE R2, R8, R3, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fca00078e0203 */
/*0110*/ IADD3 R10, P0, R2, 0x8, RZ ; /* 0x00000008020a7810 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R13, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0d7210 */
/* 0x020fe400007fe4ff */
/*0130*/ IMAD.SHL.U32 R16, R8.reuse, 0x40, RZ ; /* 0x0000004008107824 */
/* 0x040fe200078e00ff */
/*0140*/ SHF.L.U64.HI R21, R8, 0x6, R11 ; /* 0x0000000608157819 */
/* 0x000fe2000001020b */
/*0150*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0160*/ SHF.R.S32.HI R15, RZ, 0x1f, R12 ; /* 0x0000001fff0f7819 */
/* 0x000fe4000001140c */
/*0170*/ IADD3 R2, P0, R16, c[0x0][0x160], RZ ; /* 0x0000580010027a10 */
/* 0x00ffc80007f1e0ff */
/*0180*/ IADD3.X R3, R21, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590015037a10 */
/* 0x000fca00007fe4ff */
/*0190*/ IMAD.WIDE R2, R12, 0x4, R2 ; /* 0x000000040c027825 */
/* 0x000fe200078e0202 */
/*01a0*/ @!P1 BRA 0xba0 ; /* 0x000009f000009947 */
/* 0x020fea0003800000 */
/*01b0*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*01c0*/ LDG.E R19, [R2.64] ; /* 0x0000000602137981 */
/* 0x000162000c1e1900 */
/*01d0*/ LEA R4, P2, R12.reuse, UR4, 0x2 ; /* 0x000000040c047c11 */
/* 0x040fe2000f8410ff */
/*01e0*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*01f0*/ IMAD.MOV.U32 R17, RZ, RZ, R9 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0009 */
/*0200*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000a */
/*0220*/ LEA.HI.X R5, R12, UR5, R15, 0x2, P2 ; /* 0x000000050c057c11 */
/* 0x000fcc00090f140f */
/*0230*/ @!P0 BRA 0xa00 ; /* 0x000007c000008947 */
/* 0x001fea0003800000 */
/*0240*/ ISETP.GT.AND P2, PT, R17, 0xc, PT ; /* 0x0000000c1100780c */
/* 0x000fe40003f44270 */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0260*/ @!P2 BRA 0x720 ; /* 0x000004b00000a947 */
/* 0x000fea0003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ LDG.E R18, [R4.64+-0x80] ; /* 0xffff800604127981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R20, [R6.64+-0x8] ; /* 0xfffff80606147981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ IMAD R19, R18, R20, R19 ; /* 0x0000001412137224 */
/* 0x026fca00078e0213 */
/*02b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*02c0*/ LDG.E R18, [R4.64+-0x40] ; /* 0xffffc00604127981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R20, [R6.64+-0x4] ; /* 0xfffffc0606147981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x004fca00078e0213 */
/*02f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0300*/ LDG.E R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R20, [R6.64] ; /* 0x0000000606147981 */
/* 0x000ea4000c1e1900 */
/*0320*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0330*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0340*/ LDG.E R18, [R4.64+0x40] ; /* 0x0000400604127981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040606147981 */
/* 0x000e24000c1e1900 */
/*0360*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0380*/ LDG.E R18, [R4.64+0x80] ; /* 0x0000800604127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R20, [R6.64+0x8] ; /* 0x0000080606147981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*03b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*03c0*/ LDG.E R18, [R4.64+0xc0] ; /* 0x0000c00604127981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0606147981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*03f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0400*/ LDG.E R18, [R4.64+0x100] ; /* 0x0001000604127981 */
/* 0x000e28000c1e1900 */
/*0410*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100606147981 */
/* 0x000e24000c1e1900 */
/*0420*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*0430*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0440*/ LDG.E R18, [R4.64+0x140] ; /* 0x0001400604127981 */
/* 0x000e68000c1e1900 */
/*0450*/ LDG.E R20, [R6.64+0x14] ; /* 0x0000140606147981 */
/* 0x000e64000c1e1900 */
/*0460*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*0470*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0480*/ LDG.E R18, [R4.64+0x180] ; /* 0x0001800604127981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R20, [R6.64+0x18] ; /* 0x0000180606147981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*04b0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*04c0*/ LDG.E R18, [R4.64+0x1c0] ; /* 0x0001c00604127981 */
/* 0x000e28000c1e1900 */
/*04d0*/ LDG.E R20, [R6.64+0x1c] ; /* 0x00001c0606147981 */
/* 0x000e24000c1e1900 */
/*04e0*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*04f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0500*/ LDG.E R18, [R4.64+0x200] ; /* 0x0002000604127981 */
/* 0x000e68000c1e1900 */
/*0510*/ LDG.E R20, [R6.64+0x20] ; /* 0x0000200606147981 */
/* 0x000e64000c1e1900 */
/*0520*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*0530*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0540*/ LDG.E R18, [R4.64+0x240] ; /* 0x0002400604127981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R20, [R6.64+0x24] ; /* 0x0000240606147981 */
/* 0x000ea4000c1e1900 */
/*0560*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0570*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0580*/ LDG.E R18, [R4.64+0x280] ; /* 0x0002800604127981 */
/* 0x000e28000c1e1900 */
/*0590*/ LDG.E R20, [R6.64+0x28] ; /* 0x0000280606147981 */
/* 0x000e24000c1e1900 */
/*05a0*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*05b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*05c0*/ LDG.E R18, [R4.64+0x2c0] ; /* 0x0002c00604127981 */
/* 0x000e68000c1e1900 */
/*05d0*/ LDG.E R20, [R6.64+0x2c] ; /* 0x00002c0606147981 */
/* 0x000e64000c1e1900 */
/*05e0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0600*/ LDG.E R18, [R4.64+0x300] ; /* 0x0003000604127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R20, [R6.64+0x30] ; /* 0x0000300606147981 */
/* 0x000ea2000c1e1900 */
/*0620*/ IADD3 R17, R17, -0x10, RZ ; /* 0xfffffff011117810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101906 */
/*0650*/ LDG.E R18, [R4.64+0x340] ; /* 0x0003400604127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R20, [R6.64+0x34] ; /* 0x0000340606147981 */
/* 0x000e22000c1e1900 */
/*0670*/ ISETP.GT.AND P2, PT, R17, 0xc, PT ; /* 0x0000000c1100780c */
/* 0x000fe40003f44270 */
/*0680*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*0690*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fe200078e0219 */
/*06a0*/ IADD3 R18, P4, R4, 0x400, RZ ; /* 0x0000040004127810 */
/* 0x000fc40007f9e0ff */
/*06b0*/ IADD3 R20, P3, R6, 0x40, RZ ; /* 0x0000004006147810 */
/* 0x000fe40007f7e0ff */
/*06c0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e2000c101906 */
/*06d0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe200020e0605 */
/*06e0*/ MOV R4, R18 ; /* 0x0000001200047202 */
/* 0x000fe20000000f00 */
/*06f0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0607 */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0014 */
/*0710*/ @P2 BRA 0x280 ; /* 0xfffffb6000002947 */
/* 0x000fea000383ffff */
/*0720*/ ISETP.GT.AND P2, PT, R17, 0x4, PT ; /* 0x000000041100780c */
/* 0x000fda0003f44270 */
/*0730*/ @!P2 BRA 0x9e0 ; /* 0x000002a00000a947 */
/* 0x000fea0003800000 */
/*0740*/ LDG.E R18, [R4.64+-0x80] ; /* 0xffff800604127981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R20, [R6.64+-0x8] ; /* 0xfffff80606147981 */
/* 0x000ea4000c1e1900 */
/*0760*/ IMAD R19, R18, R20, R19 ; /* 0x0000001412137224 */
/* 0x026fca00078e0213 */
/*0770*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0780*/ LDG.E R18, [R4.64+-0x40] ; /* 0xffffc00604127981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R20, [R6.64+-0x4] ; /* 0xfffffc0606147981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x004fca00078e0213 */
/*07b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*07c0*/ LDG.E R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R20, [R6.64] ; /* 0x0000000606147981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*07f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*0800*/ LDG.E R18, [R4.64+0x40] ; /* 0x0000400604127981 */
/* 0x000e28000c1e1900 */
/*0810*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040606147981 */
/* 0x000e24000c1e1900 */
/*0820*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fca00078e0219 */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0840*/ LDG.E R18, [R4.64+0x80] ; /* 0x0000800604127981 */
/* 0x000e68000c1e1900 */
/*0850*/ LDG.E R20, [R6.64+0x8] ; /* 0x0000080606147981 */
/* 0x000e64000c1e1900 */
/*0860*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x002fca00078e0213 */
/*0870*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0880*/ LDG.E R18, [R4.64+0xc0] ; /* 0x0000c00604127981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0606147981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*08b0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101906 */
/*08c0*/ LDG.E R18, [R4.64+0x100] ; /* 0x0001000604127981 */
/* 0x000ee8000c1e1900 */
/*08d0*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100606147981 */
/* 0x000ee4000c1e1900 */
/*08e0*/ IMAD R27, R18, R20, R25 ; /* 0x00000014121b7224 */
/* 0x008fca00078e0219 */
/*08f0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101906 */
/*0900*/ LDG.E R18, [R4.64+0x140] ; /* 0x0001400604127981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R19, [R6.64+0x14] ; /* 0x0000140606137981 */
/* 0x0010e2000c1e1900 */
/*0920*/ IADD3 R20, P2, R6, 0x20, RZ ; /* 0x0000002006147810 */
/* 0x000fe40007f5e0ff */
/*0930*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0940*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe20007ffe0ff */
/*0950*/ IMAD.X R23, RZ, RZ, R7, P2 ; /* 0x000000ffff177224 */
/* 0x002fe200010e0607 */
/*0960*/ IADD3 R17, R17, -0x8, RZ ; /* 0xfffffff811117810 */
/* 0x000fe20007ffe0ff */
/*0970*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x001fc600078e0014 */
/*0980*/ MOV R7, R23 ; /* 0x0000001700077202 */
/* 0x000fe20000000f00 */
/*0990*/ IMAD R19, R18, R19, R27 ; /* 0x0000001312137224 */
/* 0x008fe200078e021b */
/*09a0*/ IADD3 R18, P3, R4, 0x200, RZ ; /* 0x0000020004127810 */
/* 0x000fc80007f7e0ff */
/*09b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e2000c101906 */
/*09c0*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20001ffe4ff */
/*09d0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0012 */
/*09e0*/ ISETP.NE.OR P0, PT, R17, RZ, P0 ; /* 0x000000ff1100720c */
/* 0x000fda0000705670 */
/*09f0*/ @!P0 BRA 0xba0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a00*/ LDG.E R18, [R4.64+-0x80] ; /* 0xffff800604127981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R20, [R6.64+-0x8] ; /* 0xfffff80606147981 */
/* 0x000ee4000c1e1900 */
/*0a20*/ IMAD R19, R18, R20, R19 ; /* 0x0000001412137224 */
/* 0x02efca00078e0213 */
/*0a30*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0a40*/ LDG.E R18, [R4.64+-0x40] ; /* 0xffffc00604127981 */
/* 0x000ea8000c1e1900 */
/*0a50*/ LDG.E R20, [R6.64+-0x4] ; /* 0xfffffc0606147981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ IMAD R23, R18, R20, R19 ; /* 0x0000001412177224 */
/* 0x004fca00078e0213 */
/*0a70*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0a80*/ LDG.E R18, [R4.64] ; /* 0x0000000604127981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ LDG.E R20, [R6.64] ; /* 0x0000000606147981 */
/* 0x000ea2000c1e1900 */
/*0aa0*/ IADD3 R17, R17, -0x4, RZ ; /* 0xfffffffc11117810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ IMAD R25, R18, R20, R23 ; /* 0x0000001412197224 */
/* 0x004fca00078e0217 */
/*0ac0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101906 */
/*0ad0*/ LDG.E R18, [R4.64+0x40] ; /* 0x0000400604127981 */
/* 0x000e28000c1e1900 */
/*0ae0*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040606147981 */
/* 0x000e22000c1e1900 */
/*0af0*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f05270 */
/*0b00*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R19, R18, R20, R25 ; /* 0x0000001412137224 */
/* 0x001fe200078e0219 */
/*0b20*/ IADD3 R18, P3, R4, 0x100, RZ ; /* 0x0000010004127810 */
/* 0x000fc40007f7e0ff */
/*0b30*/ IADD3 R20, P2, R6, 0x10, RZ ; /* 0x0000001006147810 */
/* 0x000fe40007f5e0ff */
/*0b40*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e2000c101906 */
/*0b50*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0b60*/ MOV R4, R18 ; /* 0x0000001200047202 */
/* 0x000fe20000000f00 */
/*0b70*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0b80*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0014 */
/*0b90*/ @P0 BRA 0xa00 ; /* 0xfffffe6000000947 */
/* 0x002fea000383ffff */
/*0ba0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0bb0*/ @!P0 BRA 0xd40 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ HFMA2.MMA R5, -RZ, RZ, 0, 3.814697265625e-06 ; /* 0x00000040ff057435 */
/* 0x000fe200000001ff */
/*0bd0*/ IADD3 R16, P0, R16, c[0x0][0x168], RZ ; /* 0x00005a0010107a10 */
/* 0x000fc80007f1e0ff */
/*0be0*/ IADD3.X R17, R21, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0015117a10 */
/* 0x000fca00007fe4ff */
/*0bf0*/ IMAD.WIDE R4, R14, R5, c[0x0][0x170] ; /* 0x00005c000e047625 */
/* 0x000fca00078e0205 */
/*0c00*/ LEA R4, P0, R12, R4, 0x2 ; /* 0x000000040c047211 */
/* 0x000fc800078010ff */
/*0c10*/ LEA.HI.X R5, R12, R5, R15, 0x2, P0 ; /* 0x000000050c057211 */
/* 0x000fe200000f140f */
/*0c20*/ IMAD.WIDE R14, R14, 0x4, R16 ; /* 0x000000040e0e7825 */
/* 0x000fe400078e0210 */
/*0c30*/ LDG.E R16, [R2.64] ; /* 0x0000000602107981 */
/* 0x000ee8000c1e1900 */
/*0c40*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x000ee8000c1e1900 */
/*0c50*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ee2000c1e1900 */
/*0c60*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*0c70*/ IMAD R17, R6, R7, R16 ; /* 0x0000000706117224 */
/* 0x008fca00078e0210 */
/*0c80*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001ee000c101906 */
/*0c90*/ @!P0 BRA 0xd40 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ LDG.E R6, [R4.64+0x40] ; /* 0x0000400604067981 */
/* 0x000ee8000c1e1900 */
/*0cb0*/ LDG.E R7, [R14.64+0x4] ; /* 0x000004060e077981 */
/* 0x000ee2000c1e1900 */
/*0cc0*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*0cd0*/ IMAD R7, R6, R7, R17 ; /* 0x0000000706077224 */
/* 0x008fca00078e0211 */
/*0ce0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0007ee000c101906 */
/*0cf0*/ @!P0 BRA 0xd40 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0d00*/ LDG.E R4, [R4.64+0x80] ; /* 0x0000800604047981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R15, [R14.64+0x8] ; /* 0x000008060e0f7981 */
/* 0x000f24000c1e1900 */
/*0d20*/ IMAD R7, R4, R15, R7 ; /* 0x0000000f04077224 */
/* 0x018fca00078e0207 */
/*0d30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0007e4000c101906 */
/*0d40*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fda0003f06270 */
/*0d60*/ @!P0 BRA 0x130 ; /* 0xfffff3c000008947 */
/* 0x000fea000383ffff */
/*0d70*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0d80*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0d90*/ @!P0 BRA 0xd0 ; /* 0xfffff33000008947 */
/* 0x000fea000383ffff */
/*0da0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0db0*/ BRA 0xdb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cudaMatMulPA16_iS0_S0_i
.globl _Z10cudaMatMulPA16_iS0_S0_i
.p2align 8
.type _Z10cudaMatMulPA16_iS0_S0_i,@function
_Z10cudaMatMulPA16_iS0_S0_i:
s_load_b32 s20, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s20, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, s3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mov_b64 s[8:9], s[2:3]
s_lshl_b64 s[10:11], s[2:3], 6
s_waitcnt lgkmcnt(0)
s_mov_b64 s[12:13], s[0:1]
s_mov_b32 s2, s3
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[2:3], 2
s_add_u32 s9, s4, s10
s_addc_u32 s16, s5, s11
s_add_u32 s14, s9, s14
s_addc_u32 s15, s16, s15
s_mov_b64 s[16:17], s[12:13]
global_load_b32 v1, v0, s[14:15]
s_mov_b64 s[18:19], s[6:7]
s_mov_b32 s9, s20
.LBB0_4:
s_clause 0x1
global_load_b32 v2, v0, s[18:19]
global_load_b32 v3, v0, s[16:17]
s_add_i32 s9, s9, -1
s_add_u32 s18, s18, 4
s_addc_u32 s19, s19, 0
s_add_u32 s16, s16, 64
s_addc_u32 s17, s17, 0
s_cmp_lg_u32 s9, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
global_store_b32 v0, v1, s[14:15]
s_cbranch_scc1 .LBB0_4
s_add_i32 s2, s2, 1
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s2, s20
s_cbranch_scc1 .LBB0_3
s_add_i32 s2, s8, 1
s_add_u32 s6, s6, 64
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s2, s20
s_cbranch_scc1 .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cudaMatMulPA16_iS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 21
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cudaMatMulPA16_iS0_S0_i, .Lfunc_end0-_Z10cudaMatMulPA16_iS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cudaMatMulPA16_iS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z10cudaMatMulPA16_iS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0013fbe2_00000000-6_prac_cuda_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
.type _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i, @function
_Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10cudaMatMulPA16_iS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i, .-_Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
.globl _Z10cudaMatMulPA16_iS0_S0_i
.type _Z10cudaMatMulPA16_iS0_S0_i, @function
_Z10cudaMatMulPA16_iS0_S0_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cudaMatMulPA16_iS0_S0_i, .-_Z10cudaMatMulPA16_iS0_S0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $944, %rsp
.cfi_def_cfa_offset 992
movq %fs:40, %rax
movq %rax, 936(%rsp)
xorl %eax, %eax
movl $0, %ebx
leaq 416(%rsp), %rbp
.L12:
movl $64, %edi
call malloc@PLT
movq %rax, 32(%rsp,%rbx)
movl $64, %edi
call malloc@PLT
movq %rax, 160(%rsp,%rbx)
movl $64, %edi
call malloc@PLT
movq %rax, 288(%rsp,%rbx)
leaq 0(%rbp,%rbx), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 544(%rsp,%rbx), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 672(%rsp,%rbx), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $64, %edi
call malloc@PLT
movq %rax, 800(%rsp,%rbx)
addq $8, %rbx
cmpq $128, %rbx
jne .L12
movl $0, %r10d
.L13:
movq 32(%rsp,%r10,8), %r9
movq 160(%rsp,%r10,8), %r8
movq 288(%rsp,%r10,8), %rdi
movl %r10d, %ecx
movl $0, %edx
movl $0, %eax
.L14:
leal (%rcx,%rax), %esi
movl %esi, (%r9,%rax,4)
movl %edx, (%r8,%rax,4)
movl $0, (%rdi,%rax,4)
addq $1, %rax
addl %ecx, %edx
cmpq $16, %rax
jne .L14
addq $1, %r10
cmpq $16, %r10
jne .L13
movl $0, %ebx
.L15:
movq 32(%rsp,%rbx), %rsi
movq 416(%rsp,%rbx), %rdi
movl $1, %ecx
movl $64, %edx
call cudaMemcpy@PLT
movq 160(%rsp,%rbx), %rsi
movq 544(%rsp,%rbx), %rdi
movl $1, %ecx
movl $64, %edx
call cudaMemcpy@PLT
movq 288(%rsp,%rbx), %rsi
movq 672(%rsp,%rbx), %rdi
movl $1, %ecx
movl $64, %edx
call cudaMemcpy@PLT
addq $8, %rbx
cmpq $128, %rbx
jne .L15
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L16:
leaq 672(%rsp), %rdx
leaq 800(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 1000
pushq $2
.cfi_def_cfa_offset 1008
movl $64, %r9d
movl $64, %r8d
movl $64, %ecx
movl $64, %esi
movq %rbp, %rdi
call cudaMemcpy2D@PLT
leaq 944(%rsp), %r14
addq $16, %rsp
.cfi_def_cfa_offset 992
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L17:
movl $0, %ebx
.L18:
movq 0(%rbp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L18
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r14, %rbp
jne .L17
movq stdout(%rip), %rdi
call fflush@PLT
movl $0, %ebx
.L20:
movq 32(%rsp,%rbx), %rdi
call free@PLT
movq 160(%rsp,%rbx), %rdi
call free@PLT
movq 288(%rsp,%rbx), %rdi
call free@PLT
movq 416(%rsp,%rbx), %rdi
call cudaFree@PLT
movq 544(%rsp,%rbx), %rdi
call cudaFree@PLT
movq 672(%rsp,%rbx), %rdi
call cudaFree@PLT
movq 800(%rsp,%rbx), %rdi
call free@PLT
addq $8, %rbx
cmpq $128, %rbx
jne .L20
movq 936(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $944, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq 544(%rsp), %rdx
leaq 416(%rsp), %rsi
leaq 672(%rsp), %rdi
movl $16, %ecx
call _Z41__device_stub__Z10cudaMatMulPA16_iS0_S0_iPA16_iS0_S0_i
jmp .L16
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10cudaMatMulPA16_iS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudaMatMulPA16_iS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "prac_cuda_matmul.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1016, %rsp # imm = 0x3F8
.cfi_def_cfa_offset 1040
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $64, %edi
callq malloc
movq %rax, 880(%rsp,%rbx)
movl $64, %edi
callq malloc
movq %rax, 752(%rsp,%rbx)
movl $64, %edi
callq malloc
movq %rax, 624(%rsp,%rbx)
leaq (%rsp,%rbx), %rdi
addq $496, %rdi # imm = 0x1F0
movl $64, %esi
callq hipMalloc
leaq (%rsp,%rbx), %rdi
addq $368, %rdi # imm = 0x170
movl $64, %esi
callq hipMalloc
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
movl $64, %esi
callq hipMalloc
movl $64, %edi
callq malloc
movq %rax, 240(%rsp,%rbx)
addq $8, %rbx
cmpq $128, %rbx
jne .LBB0_1
# %bb.2: # %.preheader54.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.preheader54
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq 880(%rsp,%rax,8), %rcx
movq 752(%rsp,%rax,8), %rdx
movq 624(%rsp,%rax,8), %rsi
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r8), %r9d
movl %r9d, (%rcx,%r8,4)
movl %edi, (%rdx,%r8,4)
movl $0, (%rsi,%r8,4)
incq %r8
addl %eax, %edi
cmpq $16, %r8
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
incq %rax
cmpq $16, %rax
jne .LBB0_3
# %bb.6: # %.preheader53.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_7: # %.preheader53
# =>This Inner Loop Header: Depth=1
movq 496(%rsp,%rbx), %rdi
movq 880(%rsp,%rbx), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 368(%rsp,%rbx), %rdi
movq 752(%rsp,%rbx), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 112(%rsp,%rbx), %rdi
movq 624(%rsp,%rbx), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
addq $8, %rbx
cmpq $128, %rbx
jne .LBB0_7
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
leaq 112(%rsp), %rax
movq %rax, 72(%rsp)
leaq 496(%rsp), %rax
movq %rax, 64(%rsp)
leaq 368(%rsp), %rax
movq %rax, 56(%rsp)
movl $16, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10cudaMatMulPA16_iS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 248(%rsp), %rdi
leaq 120(%rsp), %rdx
movl $64, %esi
movl $64, %ecx
movl $64, %r8d
movl $64, %r9d
pushq $2
.cfi_adjust_cfa_offset 8
callq hipMemcpy2D
addq $16, %rsp
.cfi_adjust_cfa_offset -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_12 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_12: # Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
movq 240(%rsp,%rbx,8), %rax
movl (%rax,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB0_12
# %bb.13: # in Loop: Header=BB0_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
cmpq $16, %rbx
jne .LBB0_11
# %bb.14:
movq stdout(%rip), %rdi
callq fflush
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_15: # =>This Inner Loop Header: Depth=1
movq 880(%rsp,%rbx), %rdi
callq free
movq 752(%rsp,%rbx), %rdi
callq free
movq 624(%rsp,%rbx), %rdi
callq free
movq 496(%rsp,%rbx), %rdi
callq hipFree
movq 368(%rsp,%rbx), %rdi
callq hipFree
movq 112(%rsp,%rbx), %rdi
callq hipFree
movq 240(%rsp,%rbx), %rdi
callq free
addq $8, %rbx
cmpq $128, %rbx
jne .LBB0_15
# %bb.16:
xorl %eax, %eax
addq $1016, %rsp # imm = 0x3F8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z25__device_stub__cudaMatMulPA16_iS0_S0_i # -- Begin function _Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.p2align 4, 0x90
.type _Z25__device_stub__cudaMatMulPA16_iS0_S0_i,@function
_Z25__device_stub__cudaMatMulPA16_iS0_S0_i: # @_Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10cudaMatMulPA16_iS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__cudaMatMulPA16_iS0_S0_i, .Lfunc_end1-_Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudaMatMulPA16_iS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cudaMatMulPA16_iS0_S0_i,@object # @_Z10cudaMatMulPA16_iS0_S0_i
.section .rodata,"a",@progbits
.globl _Z10cudaMatMulPA16_iS0_S0_i
.p2align 3, 0x0
_Z10cudaMatMulPA16_iS0_S0_i:
.quad _Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.size _Z10cudaMatMulPA16_iS0_S0_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudaMatMulPA16_iS0_S0_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudaMatMulPA16_iS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cudaMatMulPA16_iS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/**
* Primality Testing with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements an algorithm to test for primality discussed in the methodology section
* of Optimizing CPU-GPU Interactions.
*
* The following code makes use of the kernel call is_prime(int n, char *factor, char *prime)
* to perform a parallel search for some factor of the value n. The kernel calls are
* seperated into r=20 streams amongst the multi-stream processors of the CUDA compatible GPU.
* This allows us to gather data via power analysis to find a relationship between
* execution speed and power dissipation for the Jetsion TK1.
*
* While the overhead of executing executing r streams slows down execution time,
* the performance of the parallel search itself is significantly faster than it's
* serial counterpart. We can see a significant improvement in the output displayed during runtime
* when r = 1.
*
* The output of the performance is displayed in seconds for verification.
*
* References:
* NVIDIA CUDA C Programming Guide Version 3.2
*/
// System includes
#include <stdio.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
#define THREADS_PER_BLOCK 1024
// Performs a parallel search for a factor of the value n
// When a multiple is found, prime is written to 1 and facter
// is written as the multiple to be read & verified by the caller
//
// The values are written to device memory and must be recovered by the caller
__global__ void is_prime(int n, int *d_factor, int *d_prime) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i > 1 && i < n && n % i == 0) {
*d_prime = 0;
*d_factor = i;
}
}
int main(void) {
//r can be modified to produce as much overhead as needed during testing
int *prime, *d_prime, n=900000006, r=20, *factor, *d_factor;
cudaError_t error;
/* Generate space on the device */
prime = (int *)calloc(1, sizeof(int));
*prime = 1;
cudaMalloc((void **)&d_prime, sizeof(int));
cudaMemcpy(d_prime, prime, sizeof(int), cudaMemcpyHostToDevice);
factor = (int *)calloc(1, sizeof(int));
cudaMalloc((void **)&d_factor, sizeof(int));
/* Launch encrypt() kernel on GPU */
cudaStream_t stream[r];
for (int i = 0; i < r; i++ )
cudaStreamCreate(&stream[i]);
/*******************************for testing purposes****************************************
*******************************************************************************************/
cudaDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Execute the kernel
// NEED TO PUT STREAMS FOR R VALUE IN HERE
for( int i = 0; i < r; i++){
is_prime<<<(n + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK,0,stream[i]>>>(n, d_factor, d_prime);
cudaStreamSynchronize(stream[i]);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Compute and print the performance
float msecPerisPrime = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerisPrime/1000.0 );
/*******************************************************************************************
****************************** for testing purposes ***************************************/
/* Destroy streams */
for (int j = 0; j < r; j++){
cudaStreamDestroy(stream[j]);
}
/* Copy results back to host */
error = cudaMemcpy(prime, d_prime, sizeof(int), cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (prime,d_prime) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(factor, d_factor, sizeof(int), cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (factor,d_factor) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/* IS IT PRIME??? */
if (*prime == 1) {
printf("%d is prime.\n", n);
} else {
printf("%d is NOT prime, %d is a factor!\n", n, *factor);
}
/* Cleanup */
free(prime); free(factor);
cudaFree(d_prime); cudaFree(d_factor);
return 0;
}
|
code for sm_80
Function : _Z8is_primeiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x160], PT ; /* 0x0000580005007a0c */
/* 0x000fc80003f06270 */
/*0050*/ ISETP.LT.OR P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000701670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IABS R4, R5.reuse ; /* 0x0000000500047213 */
/* 0x080fe40000000000 */
/*0080*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fe40000000000 */
/*0090*/ I2F.RP R0, R4 ; /* 0x0000000400007306 */
/* 0x000e220000209400 */
/*00a0*/ ISETP.LE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f43270 */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0a06 */
/*00c0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fe40007ffe0ff */
/*00e0*/ IABS R0, c[0x0][0x160] ; /* 0x0000580000007a13 */
/* 0x000fc80000000000 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0100*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0110*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0120*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x000fca00078e02ff */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R3, R3, R6, R0 ; /* 0x0000000603037224 */
/* 0x000fca00078e0200 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f04070 */
/*0170*/ @!P0 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a04 */
/*0180*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*0190*/ ISETP.GT.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f24070 */
/*01a0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a04 */
/*01b0*/ @!P2 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303a210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P0 LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff038212 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*0220*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*0240*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe8000c101904 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/**
* Primality Testing with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements an algorithm to test for primality discussed in the methodology section
* of Optimizing CPU-GPU Interactions.
*
* The following code makes use of the kernel call is_prime(int n, char *factor, char *prime)
* to perform a parallel search for some factor of the value n. The kernel calls are
* seperated into r=20 streams amongst the multi-stream processors of the CUDA compatible GPU.
* This allows us to gather data via power analysis to find a relationship between
* execution speed and power dissipation for the Jetsion TK1.
*
* While the overhead of executing executing r streams slows down execution time,
* the performance of the parallel search itself is significantly faster than it's
* serial counterpart. We can see a significant improvement in the output displayed during runtime
* when r = 1.
*
* The output of the performance is displayed in seconds for verification.
*
* References:
* NVIDIA CUDA C Programming Guide Version 3.2
*/
// System includes
#include <stdio.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
#define THREADS_PER_BLOCK 1024
// Performs a parallel search for a factor of the value n
// When a multiple is found, prime is written to 1 and facter
// is written as the multiple to be read & verified by the caller
//
// The values are written to device memory and must be recovered by the caller
__global__ void is_prime(int n, int *d_factor, int *d_prime) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i > 1 && i < n && n % i == 0) {
*d_prime = 0;
*d_factor = i;
}
}
int main(void) {
//r can be modified to produce as much overhead as needed during testing
int *prime, *d_prime, n=900000006, r=20, *factor, *d_factor;
cudaError_t error;
/* Generate space on the device */
prime = (int *)calloc(1, sizeof(int));
*prime = 1;
cudaMalloc((void **)&d_prime, sizeof(int));
cudaMemcpy(d_prime, prime, sizeof(int), cudaMemcpyHostToDevice);
factor = (int *)calloc(1, sizeof(int));
cudaMalloc((void **)&d_factor, sizeof(int));
/* Launch encrypt() kernel on GPU */
cudaStream_t stream[r];
for (int i = 0; i < r; i++ )
cudaStreamCreate(&stream[i]);
/*******************************for testing purposes****************************************
*******************************************************************************************/
cudaDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Execute the kernel
// NEED TO PUT STREAMS FOR R VALUE IN HERE
for( int i = 0; i < r; i++){
is_prime<<<(n + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK,0,stream[i]>>>(n, d_factor, d_prime);
cudaStreamSynchronize(stream[i]);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Compute and print the performance
float msecPerisPrime = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerisPrime/1000.0 );
/*******************************************************************************************
****************************** for testing purposes ***************************************/
/* Destroy streams */
for (int j = 0; j < r; j++){
cudaStreamDestroy(stream[j]);
}
/* Copy results back to host */
error = cudaMemcpy(prime, d_prime, sizeof(int), cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (prime,d_prime) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(factor, d_factor, sizeof(int), cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (factor,d_factor) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/* IS IT PRIME??? */
if (*prime == 1) {
printf("%d is prime.\n", n);
} else {
printf("%d is NOT prime, %d is a factor!\n", n, *factor);
}
/* Cleanup */
free(prime); free(factor);
cudaFree(d_prime); cudaFree(d_factor);
return 0;
}
|
.file "tmpxft_000f214b_00000000-6_is_prime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8is_primeiPiS_iPiS_
.type _Z30__device_stub__Z8is_primeiPiS_iPiS_, @function
_Z30__device_stub__Z8is_primeiPiS_iPiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8is_primeiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8is_primeiPiS_iPiS_, .-_Z30__device_stub__Z8is_primeiPiS_iPiS_
.globl _Z8is_primeiPiS_
.type _Z8is_primeiPiS_, @function
_Z8is_primeiPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8is_primeiPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8is_primeiPiS_, .-_Z8is_primeiPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to create start event (error code %s)!\n"
.align 8
.LC1:
.string "Failed to create stop event (error code %s)!\n"
.align 8
.LC2:
.string "Failed to record start event (error code %s)!\n"
.align 8
.LC3:
.string "Failed to record stop event (error code %s)!\n"
.align 8
.LC4:
.string "Failed to synchronize on the stop event (error code %s)!\n"
.align 8
.LC6:
.string "Failed to get time elapsed between events (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "Performance= %.06f sec\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaMemcpy (prime,d_prime) returned error code %d, line(%d)\n"
.align 8
.LC10:
.string "cudaMemcpy (factor,d_factor) returned error code %d, line(%d)\n"
.section .rodata.str1.1
.LC11:
.string "%d is prime.\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "%d is NOT prime, %d is a factor!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r13
movl $1, (%rax)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rbp
leaq 224(%rsp), %r12
movq %rbp, %rbx
.L12:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L12
call cudaDeviceSynchronize@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L31
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L32
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L33
movq %rbp, %rbx
jmp .L15
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movq (%r15), %rdi
call cudaStreamSynchronize@PLT
addq $8, %rbx
cmpq %r12, %rbx
je .L34
.L15:
movq %rbx, %r15
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $878907, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq (%rbx), %r9
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movl $900000006, %edi
call _Z30__device_stub__Z8is_primeiPiS_iPiS_
jmp .L16
.L34:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L35
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L36
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L37
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L20:
movq 0(%rbp), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbp
cmpq %r12, %rbp
jne .L20
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
cmpl $1, 0(%r13)
je .L40
movl (%r14), %ecx
movl $900000006, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $149, %ecx
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl $157, %ecx
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl $900000006, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8is_primeiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8is_primeiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/**
* Primality Testing with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements an algorithm to test for primality discussed in the methodology section
* of Optimizing CPU-GPU Interactions.
*
* The following code makes use of the kernel call is_prime(int n, char *factor, char *prime)
* to perform a parallel search for some factor of the value n. The kernel calls are
* seperated into r=20 streams amongst the multi-stream processors of the CUDA compatible GPU.
* This allows us to gather data via power analysis to find a relationship between
* execution speed and power dissipation for the Jetsion TK1.
*
* While the overhead of executing executing r streams slows down execution time,
* the performance of the parallel search itself is significantly faster than it's
* serial counterpart. We can see a significant improvement in the output displayed during runtime
* when r = 1.
*
* The output of the performance is displayed in seconds for verification.
*
* References:
* NVIDIA CUDA C Programming Guide Version 3.2
*/
// System includes
#include <stdio.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
#define THREADS_PER_BLOCK 1024
// Performs a parallel search for a factor of the value n
// When a multiple is found, prime is written to 1 and facter
// is written as the multiple to be read & verified by the caller
//
// The values are written to device memory and must be recovered by the caller
__global__ void is_prime(int n, int *d_factor, int *d_prime) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i > 1 && i < n && n % i == 0) {
*d_prime = 0;
*d_factor = i;
}
}
int main(void) {
//r can be modified to produce as much overhead as needed during testing
int *prime, *d_prime, n=900000006, r=20, *factor, *d_factor;
cudaError_t error;
/* Generate space on the device */
prime = (int *)calloc(1, sizeof(int));
*prime = 1;
cudaMalloc((void **)&d_prime, sizeof(int));
cudaMemcpy(d_prime, prime, sizeof(int), cudaMemcpyHostToDevice);
factor = (int *)calloc(1, sizeof(int));
cudaMalloc((void **)&d_factor, sizeof(int));
/* Launch encrypt() kernel on GPU */
cudaStream_t stream[r];
for (int i = 0; i < r; i++ )
cudaStreamCreate(&stream[i]);
/*******************************for testing purposes****************************************
*******************************************************************************************/
cudaDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Execute the kernel
// NEED TO PUT STREAMS FOR R VALUE IN HERE
for( int i = 0; i < r; i++){
is_prime<<<(n + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK,0,stream[i]>>>(n, d_factor, d_prime);
cudaStreamSynchronize(stream[i]);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Compute and print the performance
float msecPerisPrime = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerisPrime/1000.0 );
/*******************************************************************************************
****************************** for testing purposes ***************************************/
/* Destroy streams */
for (int j = 0; j < r; j++){
cudaStreamDestroy(stream[j]);
}
/* Copy results back to host */
error = cudaMemcpy(prime, d_prime, sizeof(int), cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (prime,d_prime) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(factor, d_factor, sizeof(int), cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (factor,d_factor) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/* IS IT PRIME??? */
if (*prime == 1) {
printf("%d is prime.\n", n);
} else {
printf("%d is NOT prime, %d is a factor!\n", n, *factor);
}
/* Cleanup */
free(prime); free(factor);
cudaFree(d_prime); cudaFree(d_factor);
return 0;
}
|
/**
* Primality Testing with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements an algorithm to test for primality discussed in the methodology section
* of Optimizing CPU-GPU Interactions.
*
* The following code makes use of the kernel call is_prime(int n, char *factor, char *prime)
* to perform a parallel search for some factor of the value n. The kernel calls are
* seperated into r=20 streams amongst the multi-stream processors of the CUDA compatible GPU.
* This allows us to gather data via power analysis to find a relationship between
* execution speed and power dissipation for the Jetsion TK1.
*
* While the overhead of executing executing r streams slows down execution time,
* the performance of the parallel search itself is significantly faster than it's
* serial counterpart. We can see a significant improvement in the output displayed during runtime
* when r = 1.
*
* The output of the performance is displayed in seconds for verification.
*
* References:
* NVIDIA CUDA C Programming Guide Version 3.2
*/
// System includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
#define THREADS_PER_BLOCK 1024
// Performs a parallel search for a factor of the value n
// When a multiple is found, prime is written to 1 and facter
// is written as the multiple to be read & verified by the caller
//
// The values are written to device memory and must be recovered by the caller
__global__ void is_prime(int n, int *d_factor, int *d_prime) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i > 1 && i < n && n % i == 0) {
*d_prime = 0;
*d_factor = i;
}
}
int main(void) {
//r can be modified to produce as much overhead as needed during testing
int *prime, *d_prime, n=900000006, r=20, *factor, *d_factor;
hipError_t error;
/* Generate space on the device */
prime = (int *)calloc(1, sizeof(int));
*prime = 1;
hipMalloc((void **)&d_prime, sizeof(int));
hipMemcpy(d_prime, prime, sizeof(int), hipMemcpyHostToDevice);
factor = (int *)calloc(1, sizeof(int));
hipMalloc((void **)&d_factor, sizeof(int));
/* Launch encrypt() kernel on GPU */
hipStream_t stream[r];
for (int i = 0; i < r; i++ )
hipStreamCreate(&stream[i]);
/*******************************for testing purposes****************************************
*******************************************************************************************/
hipDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Execute the kernel
// NEED TO PUT STREAMS FOR R VALUE IN HERE
for( int i = 0; i < r; i++){
is_prime<<<(n + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK,0,stream[i]>>>(n, d_factor, d_prime);
hipStreamSynchronize(stream[i]);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Compute and print the performance
float msecPerisPrime = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerisPrime/1000.0 );
/*******************************************************************************************
****************************** for testing purposes ***************************************/
/* Destroy streams */
for (int j = 0; j < r; j++){
hipStreamDestroy(stream[j]);
}
/* Copy results back to host */
error = hipMemcpy(prime, d_prime, sizeof(int), hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (prime,d_prime) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(factor, d_factor, sizeof(int), hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (factor,d_factor) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/* IS IT PRIME??? */
if (*prime == 1) {
printf("%d is prime.\n", n);
} else {
printf("%d is NOT prime, %d is a factor!\n", n, *factor);
}
/* Cleanup */
free(prime); free(factor);
hipFree(d_prime); hipFree(d_factor);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/**
* Primality Testing with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements an algorithm to test for primality discussed in the methodology section
* of Optimizing CPU-GPU Interactions.
*
* The following code makes use of the kernel call is_prime(int n, char *factor, char *prime)
* to perform a parallel search for some factor of the value n. The kernel calls are
* seperated into r=20 streams amongst the multi-stream processors of the CUDA compatible GPU.
* This allows us to gather data via power analysis to find a relationship between
* execution speed and power dissipation for the Jetsion TK1.
*
* While the overhead of executing executing r streams slows down execution time,
* the performance of the parallel search itself is significantly faster than it's
* serial counterpart. We can see a significant improvement in the output displayed during runtime
* when r = 1.
*
* The output of the performance is displayed in seconds for verification.
*
* References:
* NVIDIA CUDA C Programming Guide Version 3.2
*/
// System includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
#define THREADS_PER_BLOCK 1024
// Performs a parallel search for a factor of the value n
// When a multiple is found, prime is written to 1 and facter
// is written as the multiple to be read & verified by the caller
//
// The values are written to device memory and must be recovered by the caller
__global__ void is_prime(int n, int *d_factor, int *d_prime) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i > 1 && i < n && n % i == 0) {
*d_prime = 0;
*d_factor = i;
}
}
int main(void) {
//r can be modified to produce as much overhead as needed during testing
int *prime, *d_prime, n=900000006, r=20, *factor, *d_factor;
hipError_t error;
/* Generate space on the device */
prime = (int *)calloc(1, sizeof(int));
*prime = 1;
hipMalloc((void **)&d_prime, sizeof(int));
hipMemcpy(d_prime, prime, sizeof(int), hipMemcpyHostToDevice);
factor = (int *)calloc(1, sizeof(int));
hipMalloc((void **)&d_factor, sizeof(int));
/* Launch encrypt() kernel on GPU */
hipStream_t stream[r];
for (int i = 0; i < r; i++ )
hipStreamCreate(&stream[i]);
/*******************************for testing purposes****************************************
*******************************************************************************************/
hipDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Execute the kernel
// NEED TO PUT STREAMS FOR R VALUE IN HERE
for( int i = 0; i < r; i++){
is_prime<<<(n + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK,0,stream[i]>>>(n, d_factor, d_prime);
hipStreamSynchronize(stream[i]);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Compute and print the performance
float msecPerisPrime = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerisPrime/1000.0 );
/*******************************************************************************************
****************************** for testing purposes ***************************************/
/* Destroy streams */
for (int j = 0; j < r; j++){
hipStreamDestroy(stream[j]);
}
/* Copy results back to host */
error = hipMemcpy(prime, d_prime, sizeof(int), hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (prime,d_prime) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(factor, d_factor, sizeof(int), hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (factor,d_factor) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/* IS IT PRIME??? */
if (*prime == 1) {
printf("%d is prime.\n", n);
} else {
printf("%d is NOT prime, %d is a factor!\n", n, *factor);
}
/* Cleanup */
free(prime); free(factor);
hipFree(d_prime); hipFree(d_factor);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8is_primeiPiS_
.globl _Z8is_primeiPiS_
.p2align 8
.type _Z8is_primeiPiS_,@function
_Z8is_primeiPiS_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x0
v_cvt_f32_u32_e32 v0, v1
v_sub_nc_u32_e32 v2, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
v_mul_hi_u32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, v1
v_sub_nc_u32_e32 v0, s2, v0
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v0, v1
v_cmp_ge_u32_e32 vcc_lo, v0, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v0, v1
v_cmp_ge_u32_e32 vcc_lo, v0, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 1, v1
s_delay_alu instid0(VALU_DEP_2)
v_cmp_eq_u32_e64 s3, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v0, v0, s[2:3]
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8is_primeiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8is_primeiPiS_, .Lfunc_end0-_Z8is_primeiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8is_primeiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8is_primeiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/**
* Primality Testing with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements an algorithm to test for primality discussed in the methodology section
* of Optimizing CPU-GPU Interactions.
*
* The following code makes use of the kernel call is_prime(int n, char *factor, char *prime)
* to perform a parallel search for some factor of the value n. The kernel calls are
* seperated into r=20 streams amongst the multi-stream processors of the CUDA compatible GPU.
* This allows us to gather data via power analysis to find a relationship between
* execution speed and power dissipation for the Jetsion TK1.
*
* While the overhead of executing executing r streams slows down execution time,
* the performance of the parallel search itself is significantly faster than it's
* serial counterpart. We can see a significant improvement in the output displayed during runtime
* when r = 1.
*
* The output of the performance is displayed in seconds for verification.
*
* References:
* NVIDIA CUDA C Programming Guide Version 3.2
*/
// System includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
#define THREADS_PER_BLOCK 1024
// Performs a parallel search for a factor of the value n
// When a multiple is found, prime is written to 1 and facter
// is written as the multiple to be read & verified by the caller
//
// The values are written to device memory and must be recovered by the caller
__global__ void is_prime(int n, int *d_factor, int *d_prime) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i > 1 && i < n && n % i == 0) {
*d_prime = 0;
*d_factor = i;
}
}
int main(void) {
//r can be modified to produce as much overhead as needed during testing
int *prime, *d_prime, n=900000006, r=20, *factor, *d_factor;
hipError_t error;
/* Generate space on the device */
prime = (int *)calloc(1, sizeof(int));
*prime = 1;
hipMalloc((void **)&d_prime, sizeof(int));
hipMemcpy(d_prime, prime, sizeof(int), hipMemcpyHostToDevice);
factor = (int *)calloc(1, sizeof(int));
hipMalloc((void **)&d_factor, sizeof(int));
/* Launch encrypt() kernel on GPU */
hipStream_t stream[r];
for (int i = 0; i < r; i++ )
hipStreamCreate(&stream[i]);
/*******************************for testing purposes****************************************
*******************************************************************************************/
hipDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Execute the kernel
// NEED TO PUT STREAMS FOR R VALUE IN HERE
for( int i = 0; i < r; i++){
is_prime<<<(n + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK,0,stream[i]>>>(n, d_factor, d_prime);
hipStreamSynchronize(stream[i]);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Compute and print the performance
float msecPerisPrime = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerisPrime/1000.0 );
/*******************************************************************************************
****************************** for testing purposes ***************************************/
/* Destroy streams */
for (int j = 0; j < r; j++){
hipStreamDestroy(stream[j]);
}
/* Copy results back to host */
error = hipMemcpy(prime, d_prime, sizeof(int), hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (prime,d_prime) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(factor, d_factor, sizeof(int), hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (factor,d_factor) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/* IS IT PRIME??? */
if (*prime == 1) {
printf("%d is prime.\n", n);
} else {
printf("%d is NOT prime, %d is a factor!\n", n, *factor);
}
/* Cleanup */
free(prime); free(factor);
hipFree(d_prime); hipFree(d_factor);
return 0;
}
|
.text
.file "is_prime.hip"
.globl _Z23__device_stub__is_primeiPiS_ # -- Begin function _Z23__device_stub__is_primeiPiS_
.p2align 4, 0x90
.type _Z23__device_stub__is_primeiPiS_,@function
_Z23__device_stub__is_primeiPiS_: # @_Z23__device_stub__is_primeiPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8is_primeiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__is_primeiPiS_, .Lfunc_end0-_Z23__device_stub__is_primeiPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $1, (%rax)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, 88(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $1, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, 72(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $160, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $160, %rbx
jne .LBB1_1
# %bb.2:
callq hipDeviceSynchronize
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_3
# %bb.5:
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq %r14, 80(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_29
# %bb.8: # %.preheader
movabsq $4294968320, %r15 # imm = 0x100000400
xorl %ebp, %ebp
leaq 877883(%r15), %r12
leaq 104(%rsp), %r14
leaq 96(%rsp), %rbx
leaq 48(%rsp), %r13
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
movq 160(%rsp,%rbp,8), %rdi
callq hipStreamSynchronize
incq %rbp
cmpq $20, %rbp
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbp,8), %r9
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl $900000006, 36(%rsp) # imm = 0x35A4E906
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z8is_primeiPiS_, %edi
movq %r13, %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
movq 80(%rsp), %r14 # 8-byte Reload
jne .LBB1_15
# %bb.16:
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_19: # =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $20, %rbx
jne .LBB1_19
# %bb.20:
movq 8(%rsp), %rsi
movl $4, %edx
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_21
# %bb.23:
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_24
# %bb.25:
cmpl $1, (%rbx)
jne .LBB1_27
# %bb.26:
movl $.L.str.9, %edi
movl $900000006, %esi # imm = 0x35A4E906
xorl %eax, %eax
callq printf
jmp .LBB1_28
.LBB1_27:
movl (%r14), %edx
movl $.L.str.10, %edi
movl $900000006, %esi # imm = 0x35A4E906
xorl %eax, %eax
callq printf
.LBB1_28:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rsp # 8-byte Reload
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 384
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB1_4
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_4
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_4
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_4
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
.LBB1_4:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_21:
movl $.L.str.7, %edi
movl %eax, %esi
movl $151, %edx
jmp .LBB1_22
.LBB1_24:
movl $.L.str.8, %edi
movl %eax, %esi
movl $159, %edx
.LBB1_22:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8is_primeiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8is_primeiPiS_,@object # @_Z8is_primeiPiS_
.section .rodata,"a",@progbits
.globl _Z8is_primeiPiS_
.p2align 3, 0x0
_Z8is_primeiPiS_:
.quad _Z23__device_stub__is_primeiPiS_
.size _Z8is_primeiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to create start event (error code %s)!\n"
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to create stop event (error code %s)!\n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to record start event (error code %s)!\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to record stop event (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to synchronize on the stop event (error code %s)!\n"
.size .L.str.4, 58
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to get time elapsed between events (error code %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Performance= %.06f sec\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy (prime,d_prime) returned error code %d, line(%d)\n"
.size .L.str.7, 60
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy (factor,d_factor) returned error code %d, line(%d)\n"
.size .L.str.8, 62
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d is prime.\n"
.size .L.str.9, 14
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d is NOT prime, %d is a factor!\n"
.size .L.str.10, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8is_primeiPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__is_primeiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8is_primeiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z8is_primeiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x160], PT ; /* 0x0000580005007a0c */
/* 0x000fc80003f06270 */
/*0050*/ ISETP.LT.OR P0, PT, R5, 0x2, P0 ; /* 0x000000020500780c */
/* 0x000fda0000701670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IABS R4, R5.reuse ; /* 0x0000000500047213 */
/* 0x080fe40000000000 */
/*0080*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fe40000000000 */
/*0090*/ I2F.RP R0, R4 ; /* 0x0000000400007306 */
/* 0x000e220000209400 */
/*00a0*/ ISETP.LE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f43270 */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0a06 */
/*00c0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fe40007ffe0ff */
/*00e0*/ IABS R0, c[0x0][0x160] ; /* 0x0000580000007a13 */
/* 0x000fc80000000000 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0100*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0110*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0120*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x000fca00078e02ff */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R3, R3, R6, R0 ; /* 0x0000000603037224 */
/* 0x000fca00078e0200 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f04070 */
/*0170*/ @!P0 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a04 */
/*0180*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*0190*/ ISETP.GT.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f24070 */
/*01a0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a04 */
/*01b0*/ @!P2 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303a210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P0 LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff038212 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*0220*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*0240*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe8000c101904 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8is_primeiPiS_
.globl _Z8is_primeiPiS_
.p2align 8
.type _Z8is_primeiPiS_,@function
_Z8is_primeiPiS_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x0
v_cvt_f32_u32_e32 v0, v1
v_sub_nc_u32_e32 v2, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
v_mul_hi_u32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, v1
v_sub_nc_u32_e32 v0, s2, v0
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v0, v1
v_cmp_ge_u32_e32 vcc_lo, v0, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v0, v1
v_cmp_ge_u32_e32 vcc_lo, v0, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 1, v1
s_delay_alu instid0(VALU_DEP_2)
v_cmp_eq_u32_e64 s3, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v0, v0, s[2:3]
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8is_primeiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8is_primeiPiS_, .Lfunc_end0-_Z8is_primeiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8is_primeiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8is_primeiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000f214b_00000000-6_is_prime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8is_primeiPiS_iPiS_
.type _Z30__device_stub__Z8is_primeiPiS_iPiS_, @function
_Z30__device_stub__Z8is_primeiPiS_iPiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8is_primeiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8is_primeiPiS_iPiS_, .-_Z30__device_stub__Z8is_primeiPiS_iPiS_
.globl _Z8is_primeiPiS_
.type _Z8is_primeiPiS_, @function
_Z8is_primeiPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8is_primeiPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8is_primeiPiS_, .-_Z8is_primeiPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to create start event (error code %s)!\n"
.align 8
.LC1:
.string "Failed to create stop event (error code %s)!\n"
.align 8
.LC2:
.string "Failed to record start event (error code %s)!\n"
.align 8
.LC3:
.string "Failed to record stop event (error code %s)!\n"
.align 8
.LC4:
.string "Failed to synchronize on the stop event (error code %s)!\n"
.align 8
.LC6:
.string "Failed to get time elapsed between events (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "Performance= %.06f sec\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaMemcpy (prime,d_prime) returned error code %d, line(%d)\n"
.align 8
.LC10:
.string "cudaMemcpy (factor,d_factor) returned error code %d, line(%d)\n"
.section .rodata.str1.1
.LC11:
.string "%d is prime.\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "%d is NOT prime, %d is a factor!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r13
movl $1, (%rax)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rbp
leaq 224(%rsp), %r12
movq %rbp, %rbx
.L12:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L12
call cudaDeviceSynchronize@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L31
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L32
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L33
movq %rbp, %rbx
jmp .L15
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movq (%r15), %rdi
call cudaStreamSynchronize@PLT
addq $8, %rbx
cmpq %r12, %rbx
je .L34
.L15:
movq %rbx, %r15
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $878907, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movq (%rbx), %r9
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movl $900000006, %edi
call _Z30__device_stub__Z8is_primeiPiS_iPiS_
jmp .L16
.L34:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L35
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L36
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L37
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L20:
movq 0(%rbp), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbp
cmpq %r12, %rbp
jne .L20
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
cmpl $1, 0(%r13)
je .L40
movl (%r14), %ecx
movl $900000006, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $149, %ecx
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl $157, %ecx
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl $900000006, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8is_primeiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8is_primeiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "is_prime.hip"
.globl _Z23__device_stub__is_primeiPiS_ # -- Begin function _Z23__device_stub__is_primeiPiS_
.p2align 4, 0x90
.type _Z23__device_stub__is_primeiPiS_,@function
_Z23__device_stub__is_primeiPiS_: # @_Z23__device_stub__is_primeiPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8is_primeiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__is_primeiPiS_, .Lfunc_end0-_Z23__device_stub__is_primeiPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $1, (%rax)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, 88(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $1, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, 72(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $160, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $160, %rbx
jne .LBB1_1
# %bb.2:
callq hipDeviceSynchronize
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_3
# %bb.5:
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq %r14, 80(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_29
# %bb.8: # %.preheader
movabsq $4294968320, %r15 # imm = 0x100000400
xorl %ebp, %ebp
leaq 877883(%r15), %r12
leaq 104(%rsp), %r14
leaq 96(%rsp), %rbx
leaq 48(%rsp), %r13
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
movq 160(%rsp,%rbp,8), %rdi
callq hipStreamSynchronize
incq %rbp
cmpq $20, %rbp
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbp,8), %r9
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl $900000006, 36(%rsp) # imm = 0x35A4E906
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z8is_primeiPiS_, %edi
movq %r13, %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
movq 80(%rsp), %r14 # 8-byte Reload
jne .LBB1_15
# %bb.16:
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_19: # =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $20, %rbx
jne .LBB1_19
# %bb.20:
movq 8(%rsp), %rsi
movl $4, %edx
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_21
# %bb.23:
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_24
# %bb.25:
cmpl $1, (%rbx)
jne .LBB1_27
# %bb.26:
movl $.L.str.9, %edi
movl $900000006, %esi # imm = 0x35A4E906
xorl %eax, %eax
callq printf
jmp .LBB1_28
.LBB1_27:
movl (%r14), %edx
movl $.L.str.10, %edi
movl $900000006, %esi # imm = 0x35A4E906
xorl %eax, %eax
callq printf
.LBB1_28:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rsp # 8-byte Reload
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 384
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB1_4
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_4
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_4
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_4
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
.LBB1_4:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_21:
movl $.L.str.7, %edi
movl %eax, %esi
movl $151, %edx
jmp .LBB1_22
.LBB1_24:
movl $.L.str.8, %edi
movl %eax, %esi
movl $159, %edx
.LBB1_22:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8is_primeiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8is_primeiPiS_,@object # @_Z8is_primeiPiS_
.section .rodata,"a",@progbits
.globl _Z8is_primeiPiS_
.p2align 3, 0x0
_Z8is_primeiPiS_:
.quad _Z23__device_stub__is_primeiPiS_
.size _Z8is_primeiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to create start event (error code %s)!\n"
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to create stop event (error code %s)!\n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to record start event (error code %s)!\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to record stop event (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to synchronize on the stop event (error code %s)!\n"
.size .L.str.4, 58
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to get time elapsed between events (error code %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Performance= %.06f sec\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy (prime,d_prime) returned error code %d, line(%d)\n"
.size .L.str.7, 60
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy (factor,d_factor) returned error code %d, line(%d)\n"
.size .L.str.8, 62
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d is prime.\n"
.size .L.str.9, 14
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d is NOT prime, %d is a factor!\n"
.size .L.str.10, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8is_primeiPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__is_primeiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8is_primeiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "nne.cuh"
#include "cuda.h"
#include "cuda_runtime_api.h"
#include "device_launch_parameters.h"
#include <cstdlib>
__global__ void nodeCal(float* inList, float* wList, float* outList);
__global__ void nodeLog(float* outputList, float sigmoidConst);
__global__ void nodeGradCal(float* wList, float* outputList, float* gradList);
__global__ void nodeDelLog(float* inputList, float* gradList, float sigmoidConst);
__global__ void nodeLearn(float *inputList, float *delList, float *weightList, float learningFactor, int inputNum);
Node::Node() : output(0), input(0), localGrad(0) {
inputWeightList.push_back(0);
}
Node::Node(int inputNum) : output(0), input(0), localGrad(0) {
inputWeightList.push_back(0);
for (int i = 0; i < inputNum; i++) {
inputWeightList.push_back((float)rand() / RAND_MAX);
}
}
Node::Node(std::vector<float>& inputWeightList, int nodeIndex, int inputWeightLength) : output(0), input(0), localGrad(0) {
inputWeightLength++;
int offset = nodeIndex * inputWeightLength;
//inputWeightList.push_back(0);
for (int i = 0; i < inputWeightLength; i++) {
this->inputWeightList.push_back(inputWeightList[offset + i]);
}
}
Node::~Node() {}
Layer::Layer() : sigmoidConst(0.01) {}
Layer::Layer(int nodeListLength, int inputWeightLength, float sigmoidConst){
Node* newNode;
this->sigmoidConst = sigmoidConst;
for (int i = 0; i < nodeListLength; i++) {
newNode = new Node(inputWeightLength);
nodeList.push_back(newNode);
}
}
Layer::Layer(std::vector<float>& inputWeightList, int nodeListLength, int inputWeightLength, float sigmoidConst) {
Node* newNode;
this->sigmoidConst = sigmoidConst;
for (int i = 0; i < nodeListLength; i++) {
newNode = new Node(inputWeightList, i, inputWeightLength);
nodeList.push_back(newNode);
}
}
Layer::~Layer() {
int length = nodeList.size();
for (int i = 0; i < length; i++) {
delete nodeList[i];
}
}
void Layer::forwardCal(std::vector<float>& inputList) {
int inputNum = inputList.size() + 1;
int outputNum = nodeList.size();
std::vector<float> weightList;
float* outputList = new float[outputNum];
float *dInputList, *dWeightList, *dOutputList;
cudaMalloc(&dInputList, inputNum * sizeof(float));
cudaMalloc(&dWeightList, inputNum * outputNum * sizeof(float));
cudaMalloc(&dOutputList, outputNum * sizeof(float));
inputList.insert(inputList.begin(), 1);
cudaMemcpy(dInputList, inputList.data(), inputNum * sizeof(float), cudaMemcpyHostToDevice);
for (int i = 0; i < outputNum; i++) {
weightList.insert(weightList.end(), nodeList[i]->inputWeightList.begin(), nodeList[i]->inputWeightList.end());
}
cudaMemcpy(dWeightList, weightList.data(), inputNum * outputNum * sizeof(float), cudaMemcpyHostToDevice);
//cudaMemcpy(dOutputList, outputList, outputNum * sizeof(float), cudaMemcpyHostToDevice);
nodeCal <<<outputNum, inputNum, sizeof(float) * inputNum>>> (dInputList, dWeightList, dOutputList);
cudaMemcpy(outputList, dOutputList, outputNum * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < outputNum; i++) {
nodeList[i]->input = outputList[i];
}
nodeLog <<<1, outputNum >>> (dOutputList, sigmoidConst);
cudaMemcpy(outputList, dOutputList, outputNum * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dInputList);
cudaFree(dWeightList);
cudaFree(dOutputList);
for (int i = 0; i < outputNum; i++) {
nodeList[i]->output = outputList[i];
}
delete outputList;
inputList.erase(inputList.begin());
}
void Layer::forwardCal(Layer& bLayer){
std::vector<Node*> &bNodeList = bLayer.nodeList;
int inputNum = bNodeList.size();
int outputNum = nodeList.size();
std::vector<float> inputList;
std::vector<float> weightList;
float* outputList = new float[outputNum];
float *dInputList, *dWeightList, *dOutputList;
cudaMalloc(&dInputList, (inputNum + 1) * sizeof(float));
cudaMalloc(&dWeightList, (inputNum + 1) * outputNum * sizeof(float));
cudaMalloc(&dOutputList, outputNum * sizeof(float));
inputList.push_back(1);
for (int i = 0; i < inputNum; i++) {
inputList.push_back((*bNodeList[i]).output);
}
inputNum++;
cudaMemcpy(dInputList, inputList.data(), inputNum * sizeof(float), cudaMemcpyHostToDevice);
for (int i = 0; i < outputNum; i++) {
weightList.insert(weightList.end(), nodeList[i]->inputWeightList.begin(), nodeList[i]->inputWeightList.end());
}
cudaMemcpy(dWeightList, weightList.data(), inputNum * outputNum * sizeof(float), cudaMemcpyHostToDevice);
//cudaMemcpy(dOutputList, outputList, outputNum * sizeof(float), cudaMemcpyHostToDevice);
nodeCal <<<outputNum, inputNum, sizeof(float) * inputNum >>> (dInputList, dWeightList, dOutputList);
cudaMemcpy(outputList, dOutputList, outputNum * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < outputNum; i++) {
nodeList[i]->input = outputList[i];
}
nodeLog <<<1, outputNum >>> (dOutputList, sigmoidConst);
cudaMemcpy(outputList, dOutputList, outputNum * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dInputList);
cudaFree(dWeightList);
cudaFree(dOutputList);
for (int i = 0; i < outputNum; i++) {
nodeList[i]->output = outputList[i];
}
delete outputList;
}
void Layer::getGrad(Layer& fLayer) {
int inputNum = nodeList.size();
int outputNum = fLayer.nodeList.size();
std::vector<Node*> &fNodeList = fLayer.nodeList;
std::vector<float> inputList;
std::vector<float> weightList;
std::vector<float> outputList;
float *gradList = new float[inputNum];
float *dInputList, *dWeightList, *dOutputList, *dGradList;
cudaMalloc(&dInputList, inputNum * sizeof(float));
cudaMalloc(&dWeightList, inputNum * outputNum * sizeof(float));
cudaMalloc(&dOutputList, outputNum * sizeof(float));
cudaMalloc(&dGradList, inputNum * sizeof(float));
for (int i = 0; i < inputNum; i++) {
inputList.push_back(nodeList[i]->input);
}
cudaMemcpy(dInputList, inputList.data(), inputNum * sizeof(float), cudaMemcpyHostToDevice);
for (int i = 0; i < outputNum; i++) {
outputList.push_back(fNodeList[i]->localGrad);
weightList.insert(weightList.end(), ++(fNodeList[i]->inputWeightList.begin()), fNodeList[i]->inputWeightList.end());
}
cudaMemcpy(dOutputList, outputList.data(), outputNum * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dWeightList, weightList.data(), inputNum * outputNum * sizeof(float), cudaMemcpyHostToDevice);
nodeGradCal <<<inputNum, outputNum, sizeof(float) * outputNum >>> (dWeightList, dOutputList, dGradList);
cudaMemcpy(gradList, dGradList, inputNum * sizeof(float), cudaMemcpyDeviceToHost);
nodeDelLog <<<1, inputNum >>> (dInputList, dGradList, sigmoidConst);
cudaMemcpy(gradList, dGradList, inputNum * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dInputList);
cudaFree(dWeightList);
cudaFree(dOutputList);
cudaFree(dGradList);
for (int i = 0; i < inputNum; i++) {
nodeList[i]->localGrad = gradList[i];
}
delete gradList;
}
float Layer::getGrad(std::vector<float>& answerList) {
int inputNum = nodeList.size();
std::vector<float> inputList;
std::vector<float> outputList;
float *gradList = new float[inputNum];
float *dInputList, *dOutputList, *dGradList, mse = 0;
cudaMalloc(&dInputList, inputNum * sizeof(float));
cudaMalloc(&dOutputList, inputNum * sizeof(float));
cudaMalloc(&dGradList, inputNum * sizeof(float));
for (int i = 0; i < inputNum; i++) {
inputList.push_back(nodeList[i]->input);
outputList.push_back(answerList[i] - nodeList[i]->output);
}
memcpy(gradList, outputList.data(), inputNum * sizeof(float));
cudaMemcpy(dInputList, inputList.data(), inputNum * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dGradList, gradList, inputNum * sizeof(float), cudaMemcpyHostToDevice);
nodeDelLog <<<1, inputNum >>> (dInputList, dGradList, sigmoidConst);
cudaMemcpy(gradList, dGradList, inputNum * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < inputNum; i++) {
nodeList[i]->localGrad = gradList[i];
}
cudaFree(dInputList);
cudaFree(dOutputList);
cudaFree(dGradList);
delete gradList;
for (int i = 0; i < inputNum; i++) {
mse += outputList[i] * outputList[i];
}
mse /= inputNum;
return mse;
}
void Layer::learnWeight(Layer& bLayer, float learningFactor) {
std::vector<Node*> &bNodeList = bLayer.nodeList;
int inputNum = bNodeList.size();
int outputNum = nodeList.size();
std::vector<float> inputList;
std::vector<float> delList;
float *weightList = new float[(inputNum + 1) * outputNum];
float *dInputList, *dDelList, *dWeightList;
dim3 threadGrid(inputNum + 1, outputNum);
cudaMalloc(&dInputList, (inputNum + 1) * sizeof(float));
cudaMalloc(&dDelList, outputNum * sizeof(float));
cudaMalloc(&dWeightList, (inputNum + 1) * outputNum * sizeof(float));
inputList.push_back(1);
for (int i = 0; i < inputNum; i++) {
inputList.push_back(bNodeList[i]->output);
}
inputNum++;
cudaMemcpy(dInputList, inputList.data(), inputNum * sizeof(float), cudaMemcpyHostToDevice);
for (int i = 0; i < outputNum; i++) {
memcpy(weightList + i * inputNum, nodeList[i]->inputWeightList.data(), inputNum * sizeof(float));
delList.push_back(nodeList[i]->localGrad);
}
cudaMemcpy(dWeightList, weightList, inputNum * outputNum * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dDelList, delList.data(), outputNum * sizeof(float), cudaMemcpyHostToDevice);
nodeLearn <<<1, threadGrid >>> (dInputList, dDelList, dWeightList, learningFactor, inputNum);
cudaMemcpy(weightList, dWeightList, inputNum * outputNum * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < outputNum; i++) {
for (int j = 0; j < inputNum; j++) {
nodeList[i]->inputWeightList[j] = weightList[i * inputNum + j];
}
}
cudaFree(dInputList);
cudaFree(dDelList);
cudaFree(dWeightList);
delete weightList;
}
void Layer::learnWeight(std::vector<float>& inputList, float learningFactor){
int inputNum = inputList.size() + 1;
int outputNum = nodeList.size();
std::vector<float> delList;
float *weightList = new float[inputNum * outputNum];
float *dInputList, *dDelList, *dWeightList;
dim3 threadGrid(inputNum, outputNum);
cudaMalloc(&dInputList, inputNum * sizeof(float));
cudaMalloc(&dDelList, outputNum * sizeof(float));
cudaMalloc(&dWeightList, inputNum * outputNum * sizeof(float));
inputList.insert(inputList.begin(), 1);
cudaMemcpy(dInputList, inputList.data(), inputNum * sizeof(float), cudaMemcpyHostToDevice);
for (int i = 0; i < outputNum; i++) {
memcpy(weightList + i * inputNum, nodeList[i]->inputWeightList.data(), inputNum * sizeof(float));
delList.push_back(nodeList[i]->localGrad);
}
cudaMemcpy(dWeightList, weightList, inputNum * outputNum * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dDelList, delList.data(), outputNum * sizeof(float), cudaMemcpyHostToDevice);
nodeLearn <<<1, threadGrid >>> (dInputList, dDelList, dWeightList, learningFactor, inputNum);
cudaMemcpy(weightList, dWeightList, inputNum * outputNum * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < outputNum; i++) {
for (int j = 0; j < inputNum; j++) {
nodeList[i]->inputWeightList[j] = weightList[i * inputNum + j];
}
}
cudaFree(dInputList);
cudaFree(dDelList);
cudaFree(dWeightList);
delete weightList;
inputList.erase(inputList.begin());
}
__global__ void nodeCal(float* inputList, float* weightList, float* outputList){
//int outputIdx = blockIdx.x * inputNum + threadIdx.x ;
int outputIdx = blockIdx.x * blockDim.x + threadIdx.x;
float result = 0;
extern __shared__ float results[];
results[threadIdx.x] = inputList[threadIdx.x] * weightList[outputIdx];
__syncthreads();
//for (int i = 0; i < inputNum; i++) {
for (int i = 0; i < blockDim.x; i++) {
result += results[i];
}
outputList[blockIdx.x] = result;
}
__global__ void nodeLog(float* outputList, float sigmoidConst) {
outputList[threadIdx.x] = tanh(sigmoidConst * outputList[threadIdx.x]);
}
__global__ void nodeGradCal(float* wList, float* outputList, float* gradList) {
int weightIdx = blockIdx.x + threadIdx.x * gridDim.x;
extern __shared__ float results[];
float result = 0;
results[threadIdx.x] = outputList[threadIdx.x] * wList[weightIdx];
__syncthreads();
for (int i = 0; i < blockDim.x; i++) {
result += results[i];
}
gradList[blockIdx.x] = result;
}
__global__ void nodeDelLog(float* inputList, float* gradList, float sigmoidConst) {
float temp;
temp = cosh(sigmoidConst * inputList[threadIdx.x]);
temp *= temp;
temp = sigmoidConst / temp;
gradList[threadIdx.x] *= temp;
}
__global__ void nodeLearn(float *inputList, float *delList, float *weightList, float learningFactor, int inputNum) {
int weightIdx = threadIdx.x + threadIdx.y * inputNum;
//int weightIdx = threadIdx.x + threadIdx.y * blockDim.x;
weightList[weightIdx] += inputList[threadIdx.x] * delList[threadIdx.y] * learningFactor;
}
|
#pragma once
#include <vector>
#include "hip/hip_runtime.h"
class Node {
public:
Node();//first input: constant/offset = 0
Node(int inputNum);//inputNum: nuber of input (first input: constant/offset = 0)
Node(std::vector<float>& inputWeightList, int nodeIndex, int inputWeightLength);
~Node();
std::vector<float> inputWeightList;
float output;
float input;
float localGrad;
};
class Layer {
public:
Layer();
Layer(int nodeListLength, int inputWeightLength, float sigmoidConst = 0.01);
Layer(std::vector<float>& inputWeightList, int nodeListLength, int inputWeightLength, float sigmoidConst = 0.01);
~Layer();
std::vector<Node*> nodeList;
float sigmoidConst;
void forwardCal(Layer& bLayer);
void forwardCal(std::vector<float>& inputList);
void getGrad(Layer& fLayer);
float getGrad(std::vector<float>& answerList); // output: MSE
void learnWeight(Layer& bLayer, float learningFactor);
void learnWeight(std::vector<float>& inputList, float learningFactor);
};
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#pragma once
#include <vector>
#include "hip/hip_runtime.h"
class Node {
public:
Node();//first input: constant/offset = 0
Node(int inputNum);//inputNum: nuber of input (first input: constant/offset = 0)
Node(std::vector<float>& inputWeightList, int nodeIndex, int inputWeightLength);
~Node();
std::vector<float> inputWeightList;
float output;
float input;
float localGrad;
};
class Layer {
public:
Layer();
Layer(int nodeListLength, int inputWeightLength, float sigmoidConst = 0.01);
Layer(std::vector<float>& inputWeightList, int nodeListLength, int inputWeightLength, float sigmoidConst = 0.01);
~Layer();
std::vector<Node*> nodeList;
float sigmoidConst;
void forwardCal(Layer& bLayer);
void forwardCal(std::vector<float>& inputList);
void getGrad(Layer& fLayer);
float getGrad(std::vector<float>& answerList); // output: MSE
void learnWeight(Layer& bLayer, float learningFactor);
void learnWeight(std::vector<float>& inputList, float learningFactor);
};
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#pragma once
#include <vector>
#include "hip/hip_runtime.h"
class Node {
public:
Node();//first input: constant/offset = 0
Node(int inputNum);//inputNum: nuber of input (first input: constant/offset = 0)
Node(std::vector<float>& inputWeightList, int nodeIndex, int inputWeightLength);
~Node();
std::vector<float> inputWeightList;
float output;
float input;
float localGrad;
};
class Layer {
public:
Layer();
Layer(int nodeListLength, int inputWeightLength, float sigmoidConst = 0.01);
Layer(std::vector<float>& inputWeightList, int nodeListLength, int inputWeightLength, float sigmoidConst = 0.01);
~Layer();
std::vector<Node*> nodeList;
float sigmoidConst;
void forwardCal(Layer& bLayer);
void forwardCal(std::vector<float>& inputList);
void getGrad(Layer& fLayer);
float getGrad(std::vector<float>& answerList); // output: MSE
void learnWeight(Layer& bLayer, float learningFactor);
void learnWeight(std::vector<float>& inputList, float learningFactor);
};
|
.text
.file "nne.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#define N_MEMELEM 32
__global__ void init_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] = blockIdx.x*blockDim.x + threadIdx.x;
}
__global__ void double_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] *= 2;
}
void do_cuda_init(double *dev_mem)
{
init_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
void do_cuda_double(double *dev_mem)
{
double_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
cudaIpcMemHandle_t get_memhandle(void *devmem)
{
cudaError_t err_dev;
cudaIpcMemHandle_t dev_mem_handle;
err_dev = cudaIpcGetMemHandle(&dev_mem_handle, devmem);
std::cout << "getHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
return dev_mem_handle;
}
void *cuda_open_handle(cudaIpcMemHandle_t dev_mem_handle)
{
cudaError_t err_dev;
void *mem_ptr=NULL;
err_dev = cudaIpcOpenMemHandle(&mem_ptr, dev_mem_handle, cudaIpcMemLazyEnablePeerAccess);
std::cout << "openHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
return mem_ptr;
}
void cuda_close_handle(void *devmem)
{
cudaError_t err_dev;
err_dev = cudaIpcCloseMemHandle(devmem);
std::cout << "closeHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
}
|
code for sm_80
Function : _Z13double_devmemPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0080*/ DADD R4, R4, R4 ; /* 0x0000000004047229 */
/* 0x004e0e0000000004 */
/*0090*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11init_devmemPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ I2F.F64.U32 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e220000201800 */
/*0070*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#define N_MEMELEM 32
__global__ void init_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] = blockIdx.x*blockDim.x + threadIdx.x;
}
__global__ void double_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] *= 2;
}
void do_cuda_init(double *dev_mem)
{
init_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
void do_cuda_double(double *dev_mem)
{
double_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
cudaIpcMemHandle_t get_memhandle(void *devmem)
{
cudaError_t err_dev;
cudaIpcMemHandle_t dev_mem_handle;
err_dev = cudaIpcGetMemHandle(&dev_mem_handle, devmem);
std::cout << "getHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
return dev_mem_handle;
}
void *cuda_open_handle(cudaIpcMemHandle_t dev_mem_handle)
{
cudaError_t err_dev;
void *mem_ptr=NULL;
err_dev = cudaIpcOpenMemHandle(&mem_ptr, dev_mem_handle, cudaIpcMemLazyEnablePeerAccess);
std::cout << "openHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
return mem_ptr;
}
void cuda_close_handle(void *devmem)
{
cudaError_t err_dev;
err_dev = cudaIpcCloseMemHandle(devmem);
std::cout << "closeHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
}
|
.file "tmpxft_0012f8b5_00000000-6_cuda_ipcmemhandle.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "getHandle: "
.LC1:
.string ": "
.text
.globl _Z13get_memhandlePv
.type _Z13get_memhandlePv, @function
_Z13get_memhandlePv:
.LFB3671:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
call cudaIpcGetMemHandle@PLT
movl %eax, %ebp
movl $11, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorName@PLT
testq %rax, %rax
je .L12
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L5:
movl $2, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L13
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L7:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L14
cmpb $0, 56(%rbx)
je .L9
movzbl 67(%rbx), %esi
.L10:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L5
.L13:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L7
.L14:
call _ZSt16__throw_bad_castv@PLT
.L9:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L10
.cfi_endproc
.LFE3671:
.size _Z13get_memhandlePv, .-_Z13get_memhandlePv
.section .rodata.str1.1
.LC2:
.string "openHandle: "
.text
.globl _Z16cuda_open_handle19cudaIpcMemHandle_st
.type _Z16cuda_open_handle19cudaIpcMemHandle_st, @function
_Z16cuda_open_handle19cudaIpcMemHandle_st:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
subq $64, %rsp
.cfi_def_cfa_offset 112
movdqu 112(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 128(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 144(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movdqu 160(%rsp), %xmm3
movups %xmm3, 48(%rsp)
movl $1, %esi
call cudaIpcOpenMemHandle@PLT
movl %eax, %ebp
addq $64, %rsp
.cfi_def_cfa_offset 48
movl $12, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorName@PLT
testq %rax, %rax
je .L26
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L17:
movl $2, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L27
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L19:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L28
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %esi
.L23:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L29
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L17
.L27:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L19
.L28:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
call _ZSt16__throw_bad_castv@PLT
.L30:
call __stack_chk_fail@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L23
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z16cuda_open_handle19cudaIpcMemHandle_st, .-_Z16cuda_open_handle19cudaIpcMemHandle_st
.section .rodata.str1.1
.LC3:
.string "closeHandle: "
.text
.globl _Z17cuda_close_handlePv
.type _Z17cuda_close_handlePv, @function
_Z17cuda_close_handlePv:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
call cudaIpcCloseMemHandle@PLT
movl %eax, %ebp
movl $13, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorName@PLT
testq %rax, %rax
je .L40
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L33:
movl $2, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L41
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L35:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L42
cmpb $0, 56(%rbx)
je .L37
movzbl 67(%rbx), %esi
.L38:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L33
.L41:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L35
.L42:
call _ZSt16__throw_bad_castv@PLT
.L37:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L38
.cfi_endproc
.LFE3673:
.size _Z17cuda_close_handlePv, .-_Z17cuda_close_handlePv
.globl _Z31__device_stub__Z11init_devmemPdPd
.type _Z31__device_stub__Z11init_devmemPdPd, @function
_Z31__device_stub__Z11init_devmemPdPd:
.LFB3698:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11init_devmemPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z31__device_stub__Z11init_devmemPdPd, .-_Z31__device_stub__Z11init_devmemPdPd
.globl _Z11init_devmemPd
.type _Z11init_devmemPd, @function
_Z11init_devmemPd:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11init_devmemPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z11init_devmemPd, .-_Z11init_devmemPd
.globl _Z12do_cuda_initPd
.type _Z12do_cuda_initPd, @function
_Z12do_cuda_initPd:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L51:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movq %rbx, %rdi
call _Z31__device_stub__Z11init_devmemPdPd
jmp .L51
.cfi_endproc
.LFE3669:
.size _Z12do_cuda_initPd, .-_Z12do_cuda_initPd
.globl _Z33__device_stub__Z13double_devmemPdPd
.type _Z33__device_stub__Z13double_devmemPdPd, @function
_Z33__device_stub__Z13double_devmemPdPd:
.LFB3700:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13double_devmemPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z33__device_stub__Z13double_devmemPdPd, .-_Z33__device_stub__Z13double_devmemPdPd
.globl _Z13double_devmemPd
.type _Z13double_devmemPd, @function
_Z13double_devmemPd:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13double_devmemPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z13double_devmemPd, .-_Z13double_devmemPd
.globl _Z14do_cuda_doublePd
.type _Z14do_cuda_doublePd, @function
_Z14do_cuda_doublePd:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L63:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
movq %rbx, %rdi
call _Z33__device_stub__Z13double_devmemPdPd
jmp .L63
.cfi_endproc
.LFE3670:
.size _Z14do_cuda_doublePd, .-_Z14do_cuda_doublePd
.section .rodata.str1.1
.LC4:
.string "_Z13double_devmemPd"
.LC5:
.string "_Z11init_devmemPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13double_devmemPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_devmemPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#define N_MEMELEM 32
__global__ void init_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] = blockIdx.x*blockDim.x + threadIdx.x;
}
__global__ void double_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] *= 2;
}
void do_cuda_init(double *dev_mem)
{
init_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
void do_cuda_double(double *dev_mem)
{
double_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
cudaIpcMemHandle_t get_memhandle(void *devmem)
{
cudaError_t err_dev;
cudaIpcMemHandle_t dev_mem_handle;
err_dev = cudaIpcGetMemHandle(&dev_mem_handle, devmem);
std::cout << "getHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
return dev_mem_handle;
}
void *cuda_open_handle(cudaIpcMemHandle_t dev_mem_handle)
{
cudaError_t err_dev;
void *mem_ptr=NULL;
err_dev = cudaIpcOpenMemHandle(&mem_ptr, dev_mem_handle, cudaIpcMemLazyEnablePeerAccess);
std::cout << "openHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
return mem_ptr;
}
void cuda_close_handle(void *devmem)
{
cudaError_t err_dev;
err_dev = cudaIpcCloseMemHandle(devmem);
std::cout << "closeHandle: " << cudaGetErrorName(err_dev) << ": " << cudaGetErrorString(err_dev) << std::endl;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#define N_MEMELEM 32
__global__ void init_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] = blockIdx.x*blockDim.x + threadIdx.x;
}
__global__ void double_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] *= 2;
}
void do_cuda_init(double *dev_mem)
{
init_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
void do_cuda_double(double *dev_mem)
{
double_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
hipIpcMemHandle_t get_memhandle(void *devmem)
{
hipError_t err_dev;
hipIpcMemHandle_t dev_mem_handle;
err_dev = hipIpcGetMemHandle(&dev_mem_handle, devmem);
std::cout << "getHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
return dev_mem_handle;
}
void *cuda_open_handle(hipIpcMemHandle_t dev_mem_handle)
{
hipError_t err_dev;
void *mem_ptr=NULL;
err_dev = hipIpcOpenMemHandle(&mem_ptr, dev_mem_handle, hipIpcMemLazyEnablePeerAccess);
std::cout << "openHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
return mem_ptr;
}
void cuda_close_handle(void *devmem)
{
hipError_t err_dev;
err_dev = hipIpcCloseMemHandle(devmem);
std::cout << "closeHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#define N_MEMELEM 32
__global__ void init_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] = blockIdx.x*blockDim.x + threadIdx.x;
}
__global__ void double_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] *= 2;
}
void do_cuda_init(double *dev_mem)
{
init_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
void do_cuda_double(double *dev_mem)
{
double_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
hipIpcMemHandle_t get_memhandle(void *devmem)
{
hipError_t err_dev;
hipIpcMemHandle_t dev_mem_handle;
err_dev = hipIpcGetMemHandle(&dev_mem_handle, devmem);
std::cout << "getHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
return dev_mem_handle;
}
void *cuda_open_handle(hipIpcMemHandle_t dev_mem_handle)
{
hipError_t err_dev;
void *mem_ptr=NULL;
err_dev = hipIpcOpenMemHandle(&mem_ptr, dev_mem_handle, hipIpcMemLazyEnablePeerAccess);
std::cout << "openHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
return mem_ptr;
}
void cuda_close_handle(void *devmem)
{
hipError_t err_dev;
err_dev = hipIpcCloseMemHandle(devmem);
std::cout << "closeHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_devmemPd
.globl _Z11init_devmemPd
.p2align 8
.type _Z11init_devmemPd,@function
_Z11init_devmemPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_cvt_f64_u32_e32 v[3:4], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_devmemPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11init_devmemPd, .Lfunc_end0-_Z11init_devmemPd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13double_devmemPd
.globl _Z13double_devmemPd
.p2align 8
.type _Z13double_devmemPd,@function
_Z13double_devmemPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13double_devmemPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13double_devmemPd, .Lfunc_end1-_Z13double_devmemPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_devmemPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_devmemPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13double_devmemPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13double_devmemPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#define N_MEMELEM 32
__global__ void init_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] = blockIdx.x*blockDim.x + threadIdx.x;
}
__global__ void double_devmem(double *mem)
{
mem[blockIdx.x*blockDim.x + threadIdx.x] *= 2;
}
void do_cuda_init(double *dev_mem)
{
init_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
void do_cuda_double(double *dev_mem)
{
double_devmem<<<N_MEMELEM/32,32>>>(dev_mem);
}
hipIpcMemHandle_t get_memhandle(void *devmem)
{
hipError_t err_dev;
hipIpcMemHandle_t dev_mem_handle;
err_dev = hipIpcGetMemHandle(&dev_mem_handle, devmem);
std::cout << "getHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
return dev_mem_handle;
}
void *cuda_open_handle(hipIpcMemHandle_t dev_mem_handle)
{
hipError_t err_dev;
void *mem_ptr=NULL;
err_dev = hipIpcOpenMemHandle(&mem_ptr, dev_mem_handle, hipIpcMemLazyEnablePeerAccess);
std::cout << "openHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
return mem_ptr;
}
void cuda_close_handle(void *devmem)
{
hipError_t err_dev;
err_dev = hipIpcCloseMemHandle(devmem);
std::cout << "closeHandle: " << hipGetErrorName(err_dev) << ": " << hipGetErrorString(err_dev) << std::endl;
}
|
.text
.file "cuda_ipcmemhandle.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__init_devmemPd # -- Begin function _Z26__device_stub__init_devmemPd
.p2align 4, 0x90
.type _Z26__device_stub__init_devmemPd,@function
_Z26__device_stub__init_devmemPd: # @_Z26__device_stub__init_devmemPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11init_devmemPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__init_devmemPd, .Lfunc_end0-_Z26__device_stub__init_devmemPd
.cfi_endproc
# -- End function
.globl _Z28__device_stub__double_devmemPd # -- Begin function _Z28__device_stub__double_devmemPd
.p2align 4, 0x90
.type _Z28__device_stub__double_devmemPd,@function
_Z28__device_stub__double_devmemPd: # @_Z28__device_stub__double_devmemPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13double_devmemPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__double_devmemPd, .Lfunc_end1-_Z28__device_stub__double_devmemPd
.cfi_endproc
# -- End function
.globl _Z12do_cuda_initPd # -- Begin function _Z12do_cuda_initPd
.p2align 4, 0x90
.type _Z12do_cuda_initPd,@function
_Z12do_cuda_initPd: # @_Z12do_cuda_initPd
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z11init_devmemPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12do_cuda_initPd, .Lfunc_end2-_Z12do_cuda_initPd
.cfi_endproc
# -- End function
.globl _Z14do_cuda_doublePd # -- Begin function _Z14do_cuda_doublePd
.p2align 4, 0x90
.type _Z14do_cuda_doublePd,@function
_Z14do_cuda_doublePd: # @_Z14do_cuda_doublePd
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z13double_devmemPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14do_cuda_doublePd, .Lfunc_end3-_Z14do_cuda_doublePd
.cfi_endproc
# -- End function
.globl _Z13get_memhandlePv # -- Begin function _Z13get_memhandlePv
.p2align 4, 0x90
.type _Z13get_memhandlePv,@function
_Z13get_memhandlePv: # @_Z13get_memhandlePv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipIpcGetMemHandle
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB4_1
# %bb.2:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_3
.LBB4_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_4
# %bb.5:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_6
.LBB4_4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB4_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB4_10
.LBB4_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z13get_memhandlePv, .Lfunc_end4-_Z13get_memhandlePv
.cfi_endproc
# -- End function
.globl _Z16cuda_open_handle18hipIpcMemHandle_st # -- Begin function _Z16cuda_open_handle18hipIpcMemHandle_st
.p2align 4, 0x90
.type _Z16cuda_open_handle18hipIpcMemHandle_st,@function
_Z16cuda_open_handle18hipIpcMemHandle_st: # @_Z16cuda_open_handle18hipIpcMemHandle_st
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 64(%rsp)
movaps 96(%rsp), %xmm0
movaps 112(%rsp), %xmm1
movaps 128(%rsp), %xmm2
movaps 144(%rsp), %xmm3
movups %xmm3, 48(%rsp)
movups %xmm2, 32(%rsp)
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
leaq 64(%rsp), %rdi
movl $1, %esi
callq hipIpcOpenMemHandle
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB5_1
# %bb.2:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB5_3
.LBB5_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB5_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB5_4
# %bb.5:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB5_6
.LBB5_4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB5_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB5_10
.LBB5_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 64(%rsp), %rax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB5_11:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z16cuda_open_handle18hipIpcMemHandle_st, .Lfunc_end5-_Z16cuda_open_handle18hipIpcMemHandle_st
.cfi_endproc
# -- End function
.globl _Z17cuda_close_handlePv # -- Begin function _Z17cuda_close_handlePv
.p2align 4, 0x90
.type _Z17cuda_close_handlePv,@function
_Z17cuda_close_handlePv: # @_Z17cuda_close_handlePv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq hipIpcCloseMemHandle
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB6_1
# %bb.2:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB6_3
.LBB6_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB6_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB6_4
# %bb.5:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB6_6
.LBB6_4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB6_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB6_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB6_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB6_10
.LBB6_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB6_11:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size _Z17cuda_close_handlePv, .Lfunc_end6-_Z17cuda_close_handlePv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_devmemPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13double_devmemPd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_devmemPd,@object # @_Z11init_devmemPd
.section .rodata,"a",@progbits
.globl _Z11init_devmemPd
.p2align 3, 0x0
_Z11init_devmemPd:
.quad _Z26__device_stub__init_devmemPd
.size _Z11init_devmemPd, 8
.type _Z13double_devmemPd,@object # @_Z13double_devmemPd
.globl _Z13double_devmemPd
.p2align 3, 0x0
_Z13double_devmemPd:
.quad _Z28__device_stub__double_devmemPd
.size _Z13double_devmemPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "getHandle: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "openHandle: "
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "closeHandle: "
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11init_devmemPd"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13double_devmemPd"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_devmemPd
.addrsig_sym _Z28__device_stub__double_devmemPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_devmemPd
.addrsig_sym _Z13double_devmemPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z13double_devmemPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0080*/ DADD R4, R4, R4 ; /* 0x0000000004047229 */
/* 0x004e0e0000000004 */
/*0090*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11init_devmemPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ I2F.F64.U32 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e220000201800 */
/*0070*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_devmemPd
.globl _Z11init_devmemPd
.p2align 8
.type _Z11init_devmemPd,@function
_Z11init_devmemPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_cvt_f64_u32_e32 v[3:4], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_devmemPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11init_devmemPd, .Lfunc_end0-_Z11init_devmemPd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13double_devmemPd
.globl _Z13double_devmemPd
.p2align 8
.type _Z13double_devmemPd,@function
_Z13double_devmemPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13double_devmemPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13double_devmemPd, .Lfunc_end1-_Z13double_devmemPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_devmemPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_devmemPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13double_devmemPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13double_devmemPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0012f8b5_00000000-6_cuda_ipcmemhandle.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "getHandle: "
.LC1:
.string ": "
.text
.globl _Z13get_memhandlePv
.type _Z13get_memhandlePv, @function
_Z13get_memhandlePv:
.LFB3671:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
call cudaIpcGetMemHandle@PLT
movl %eax, %ebp
movl $11, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorName@PLT
testq %rax, %rax
je .L12
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L5:
movl $2, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L13
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L7:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L14
cmpb $0, 56(%rbx)
je .L9
movzbl 67(%rbx), %esi
.L10:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L5
.L13:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L7
.L14:
call _ZSt16__throw_bad_castv@PLT
.L9:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L10
.cfi_endproc
.LFE3671:
.size _Z13get_memhandlePv, .-_Z13get_memhandlePv
.section .rodata.str1.1
.LC2:
.string "openHandle: "
.text
.globl _Z16cuda_open_handle19cudaIpcMemHandle_st
.type _Z16cuda_open_handle19cudaIpcMemHandle_st, @function
_Z16cuda_open_handle19cudaIpcMemHandle_st:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
subq $64, %rsp
.cfi_def_cfa_offset 112
movdqu 112(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 128(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 144(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movdqu 160(%rsp), %xmm3
movups %xmm3, 48(%rsp)
movl $1, %esi
call cudaIpcOpenMemHandle@PLT
movl %eax, %ebp
addq $64, %rsp
.cfi_def_cfa_offset 48
movl $12, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorName@PLT
testq %rax, %rax
je .L26
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L17:
movl $2, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L27
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L19:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L28
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %esi
.L23:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L29
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L17
.L27:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L19
.L28:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
call _ZSt16__throw_bad_castv@PLT
.L30:
call __stack_chk_fail@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L23
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z16cuda_open_handle19cudaIpcMemHandle_st, .-_Z16cuda_open_handle19cudaIpcMemHandle_st
.section .rodata.str1.1
.LC3:
.string "closeHandle: "
.text
.globl _Z17cuda_close_handlePv
.type _Z17cuda_close_handlePv, @function
_Z17cuda_close_handlePv:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
call cudaIpcCloseMemHandle@PLT
movl %eax, %ebp
movl $13, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorName@PLT
testq %rax, %rax
je .L40
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L33:
movl $2, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L41
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L35:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L42
cmpb $0, 56(%rbx)
je .L37
movzbl 67(%rbx), %esi
.L38:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L33
.L41:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L35
.L42:
call _ZSt16__throw_bad_castv@PLT
.L37:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L38
.cfi_endproc
.LFE3673:
.size _Z17cuda_close_handlePv, .-_Z17cuda_close_handlePv
.globl _Z31__device_stub__Z11init_devmemPdPd
.type _Z31__device_stub__Z11init_devmemPdPd, @function
_Z31__device_stub__Z11init_devmemPdPd:
.LFB3698:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11init_devmemPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z31__device_stub__Z11init_devmemPdPd, .-_Z31__device_stub__Z11init_devmemPdPd
.globl _Z11init_devmemPd
.type _Z11init_devmemPd, @function
_Z11init_devmemPd:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11init_devmemPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z11init_devmemPd, .-_Z11init_devmemPd
.globl _Z12do_cuda_initPd
.type _Z12do_cuda_initPd, @function
_Z12do_cuda_initPd:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L51:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movq %rbx, %rdi
call _Z31__device_stub__Z11init_devmemPdPd
jmp .L51
.cfi_endproc
.LFE3669:
.size _Z12do_cuda_initPd, .-_Z12do_cuda_initPd
.globl _Z33__device_stub__Z13double_devmemPdPd
.type _Z33__device_stub__Z13double_devmemPdPd, @function
_Z33__device_stub__Z13double_devmemPdPd:
.LFB3700:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13double_devmemPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z33__device_stub__Z13double_devmemPdPd, .-_Z33__device_stub__Z13double_devmemPdPd
.globl _Z13double_devmemPd
.type _Z13double_devmemPd, @function
_Z13double_devmemPd:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13double_devmemPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z13double_devmemPd, .-_Z13double_devmemPd
.globl _Z14do_cuda_doublePd
.type _Z14do_cuda_doublePd, @function
_Z14do_cuda_doublePd:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L63:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
movq %rbx, %rdi
call _Z33__device_stub__Z13double_devmemPdPd
jmp .L63
.cfi_endproc
.LFE3670:
.size _Z14do_cuda_doublePd, .-_Z14do_cuda_doublePd
.section .rodata.str1.1
.LC4:
.string "_Z13double_devmemPd"
.LC5:
.string "_Z11init_devmemPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13double_devmemPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_devmemPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "cuda_ipcmemhandle.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__init_devmemPd # -- Begin function _Z26__device_stub__init_devmemPd
.p2align 4, 0x90
.type _Z26__device_stub__init_devmemPd,@function
_Z26__device_stub__init_devmemPd: # @_Z26__device_stub__init_devmemPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11init_devmemPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__init_devmemPd, .Lfunc_end0-_Z26__device_stub__init_devmemPd
.cfi_endproc
# -- End function
.globl _Z28__device_stub__double_devmemPd # -- Begin function _Z28__device_stub__double_devmemPd
.p2align 4, 0x90
.type _Z28__device_stub__double_devmemPd,@function
_Z28__device_stub__double_devmemPd: # @_Z28__device_stub__double_devmemPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13double_devmemPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__double_devmemPd, .Lfunc_end1-_Z28__device_stub__double_devmemPd
.cfi_endproc
# -- End function
.globl _Z12do_cuda_initPd # -- Begin function _Z12do_cuda_initPd
.p2align 4, 0x90
.type _Z12do_cuda_initPd,@function
_Z12do_cuda_initPd: # @_Z12do_cuda_initPd
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z11init_devmemPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12do_cuda_initPd, .Lfunc_end2-_Z12do_cuda_initPd
.cfi_endproc
# -- End function
.globl _Z14do_cuda_doublePd # -- Begin function _Z14do_cuda_doublePd
.p2align 4, 0x90
.type _Z14do_cuda_doublePd,@function
_Z14do_cuda_doublePd: # @_Z14do_cuda_doublePd
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z13double_devmemPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14do_cuda_doublePd, .Lfunc_end3-_Z14do_cuda_doublePd
.cfi_endproc
# -- End function
.globl _Z13get_memhandlePv # -- Begin function _Z13get_memhandlePv
.p2align 4, 0x90
.type _Z13get_memhandlePv,@function
_Z13get_memhandlePv: # @_Z13get_memhandlePv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipIpcGetMemHandle
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB4_1
# %bb.2:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_3
.LBB4_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_4
# %bb.5:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_6
.LBB4_4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB4_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB4_10
.LBB4_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z13get_memhandlePv, .Lfunc_end4-_Z13get_memhandlePv
.cfi_endproc
# -- End function
.globl _Z16cuda_open_handle18hipIpcMemHandle_st # -- Begin function _Z16cuda_open_handle18hipIpcMemHandle_st
.p2align 4, 0x90
.type _Z16cuda_open_handle18hipIpcMemHandle_st,@function
_Z16cuda_open_handle18hipIpcMemHandle_st: # @_Z16cuda_open_handle18hipIpcMemHandle_st
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 64(%rsp)
movaps 96(%rsp), %xmm0
movaps 112(%rsp), %xmm1
movaps 128(%rsp), %xmm2
movaps 144(%rsp), %xmm3
movups %xmm3, 48(%rsp)
movups %xmm2, 32(%rsp)
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
leaq 64(%rsp), %rdi
movl $1, %esi
callq hipIpcOpenMemHandle
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB5_1
# %bb.2:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB5_3
.LBB5_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB5_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB5_4
# %bb.5:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB5_6
.LBB5_4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB5_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB5_10
.LBB5_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 64(%rsp), %rax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB5_11:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z16cuda_open_handle18hipIpcMemHandle_st, .Lfunc_end5-_Z16cuda_open_handle18hipIpcMemHandle_st
.cfi_endproc
# -- End function
.globl _Z17cuda_close_handlePv # -- Begin function _Z17cuda_close_handlePv
.p2align 4, 0x90
.type _Z17cuda_close_handlePv,@function
_Z17cuda_close_handlePv: # @_Z17cuda_close_handlePv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq hipIpcCloseMemHandle
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB6_1
# %bb.2:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB6_3
.LBB6_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB6_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB6_4
# %bb.5:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB6_6
.LBB6_4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB6_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB6_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB6_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB6_10
.LBB6_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB6_11:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size _Z17cuda_close_handlePv, .Lfunc_end6-_Z17cuda_close_handlePv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_devmemPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13double_devmemPd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_devmemPd,@object # @_Z11init_devmemPd
.section .rodata,"a",@progbits
.globl _Z11init_devmemPd
.p2align 3, 0x0
_Z11init_devmemPd:
.quad _Z26__device_stub__init_devmemPd
.size _Z11init_devmemPd, 8
.type _Z13double_devmemPd,@object # @_Z13double_devmemPd
.globl _Z13double_devmemPd
.p2align 3, 0x0
_Z13double_devmemPd:
.quad _Z28__device_stub__double_devmemPd
.size _Z13double_devmemPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "getHandle: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "openHandle: "
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "closeHandle: "
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11init_devmemPd"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13double_devmemPd"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_devmemPd
.addrsig_sym _Z28__device_stub__double_devmemPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_devmemPd
.addrsig_sym _Z13double_devmemPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// $Smake: nvcc -O2 -o %F %f
//
// add-vectors.cu - addition of two arrays on GPU device
//
// This program follows a very standard pattern:
// 1) allocate memory on host
// 2) allocate memory on device
// 3) initialize memory on host
// 4) copy memory from host to device
// 5) execute kernel(s) on device
// 6) copy result(s) from device to host
//
// Note: it may be possible to initialize memory directly on the device,
// in which case steps 3 and 4 are not necessary, and step 1 is only
// necessary to allocate memory to hold results.
#include <stdio.h>
#include <cuda.h>
//-----------------------------------------------------------------------------
// Kernel that executes on CUDA device
__global__ void add_vectors(
float *c, // out - pointer to result vector c
float *a, // in - pointer to summand vector a
float *b, // in - pointer to summand vector b
int n // in - vector length
)
{
// Assume single block grid and 1-D block
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Only do calculation if we have real data to work with
if ( idx < n ) c[idx] = a[idx] + b[idx];
}
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Main program executes on host device
int main( int argc, char* argv[] )
{
// determine vector length
int n = 10; // set default length
if ( argc > 1 )
{
n = atoi( argv[1] ); // override default length
if ( n <= 0 )
{
fprintf( stderr, "Vector length must be positive\n" );
return EXIT_FAILURE;
}
}
// determine vector size in bytes
const size_t vector_size = n * sizeof( float );
// declare pointers to vectors in host memory and allocate memory
float *a, *b, *c;
a = (float*) malloc( vector_size );
b = (float*) malloc( vector_size );
c = (float*) malloc( vector_size );
// declare pointers to vectors in device memory and allocate memory
float *a_d, *b_d, *c_d;
cudaMalloc( (void**) &a_d, vector_size );
cudaMalloc( (void**) &b_d, vector_size );
cudaMalloc( (void**) &c_d, vector_size );
// initialize vectors and copy them to device
for ( int i = 0; i < n; i++ )
{
a[i] = 1.0 * i;
b[i] = 100.0 * i;
}
cudaMemcpy( a_d, a, vector_size, cudaMemcpyHostToDevice );
cudaMemcpy( b_d, b, vector_size, cudaMemcpyHostToDevice );
// do calculation on device
int block_size = 16;
int num_blocks = ( n - 1 + block_size ) / block_size;
add_vectors<<< num_blocks, block_size >>>( c_d, a_d, b_d, n );
// retrieve result from device and store on host
cudaMemcpy( c, c_d, vector_size, cudaMemcpyDeviceToHost );
// print results for vectors up to length 100
if ( n <= 100 )
{
for ( int i = 0; i < n; i++ )
{
printf( "%8.2f + %8.2f = %8.2f\n", a[i], b[i], c[i] );
}
}
// cleanup and quit
cudaFree( a_d );
cudaFree( b_d );
cudaFree( c_d );
free( a );
free( b );
free( c );
return 0;
}
|
code for sm_80
Function : _Z11add_vectorsPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// $Smake: nvcc -O2 -o %F %f
//
// add-vectors.cu - addition of two arrays on GPU device
//
// This program follows a very standard pattern:
// 1) allocate memory on host
// 2) allocate memory on device
// 3) initialize memory on host
// 4) copy memory from host to device
// 5) execute kernel(s) on device
// 6) copy result(s) from device to host
//
// Note: it may be possible to initialize memory directly on the device,
// in which case steps 3 and 4 are not necessary, and step 1 is only
// necessary to allocate memory to hold results.
#include <stdio.h>
#include <cuda.h>
//-----------------------------------------------------------------------------
// Kernel that executes on CUDA device
__global__ void add_vectors(
float *c, // out - pointer to result vector c
float *a, // in - pointer to summand vector a
float *b, // in - pointer to summand vector b
int n // in - vector length
)
{
// Assume single block grid and 1-D block
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Only do calculation if we have real data to work with
if ( idx < n ) c[idx] = a[idx] + b[idx];
}
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Main program executes on host device
int main( int argc, char* argv[] )
{
// determine vector length
int n = 10; // set default length
if ( argc > 1 )
{
n = atoi( argv[1] ); // override default length
if ( n <= 0 )
{
fprintf( stderr, "Vector length must be positive\n" );
return EXIT_FAILURE;
}
}
// determine vector size in bytes
const size_t vector_size = n * sizeof( float );
// declare pointers to vectors in host memory and allocate memory
float *a, *b, *c;
a = (float*) malloc( vector_size );
b = (float*) malloc( vector_size );
c = (float*) malloc( vector_size );
// declare pointers to vectors in device memory and allocate memory
float *a_d, *b_d, *c_d;
cudaMalloc( (void**) &a_d, vector_size );
cudaMalloc( (void**) &b_d, vector_size );
cudaMalloc( (void**) &c_d, vector_size );
// initialize vectors and copy them to device
for ( int i = 0; i < n; i++ )
{
a[i] = 1.0 * i;
b[i] = 100.0 * i;
}
cudaMemcpy( a_d, a, vector_size, cudaMemcpyHostToDevice );
cudaMemcpy( b_d, b, vector_size, cudaMemcpyHostToDevice );
// do calculation on device
int block_size = 16;
int num_blocks = ( n - 1 + block_size ) / block_size;
add_vectors<<< num_blocks, block_size >>>( c_d, a_d, b_d, n );
// retrieve result from device and store on host
cudaMemcpy( c, c_d, vector_size, cudaMemcpyDeviceToHost );
// print results for vectors up to length 100
if ( n <= 100 )
{
for ( int i = 0; i < n; i++ )
{
printf( "%8.2f + %8.2f = %8.2f\n", a[i], b[i], c[i] );
}
}
// cleanup and quit
cudaFree( a_d );
cudaFree( b_d );
cudaFree( c_d );
free( a );
free( b );
free( c );
return 0;
}
|
.file "tmpxft_0006ca38_00000000-6_add-vectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
.type _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i, @function
_Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11add_vectorsPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i, .-_Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
.globl _Z11add_vectorsPfS_S_i
.type _Z11add_vectorsPfS_S_i, @function
_Z11add_vectorsPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11add_vectorsPfS_S_i, .-_Z11add_vectorsPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Vector length must be positive\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%8.2f + %8.2f = %8.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L19
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r15d
testl %eax, %eax
jle .L23
.L12:
movslq %r15d, %r13
leaq 0(,%r13,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %eax
movsd .LC1(%rip), %xmm2
.L14:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movss %xmm1, 0(%rbp,%rax,4)
mulsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %r13
jne .L14
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $1, 48(%rsp)
leal 30(%r15), %eax
movl %r15d, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
cmpl $100, %r15d
jg .L16
movl $0, %r13d
leaq .LC2(%rip), %r15
.L17:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r13), %xmm0
pxor %xmm2, %xmm2
cvtss2sd (%r14,%r13), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%rbx,%r13), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r12, %r13
jne .L17
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movl $0, %eax
.L11:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L11
.L19:
movl $10, %r15d
jmp .L12
.L24:
movl %r15d, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
jmp .L15
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11add_vectorsPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11add_vectorsPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// $Smake: nvcc -O2 -o %F %f
//
// add-vectors.cu - addition of two arrays on GPU device
//
// This program follows a very standard pattern:
// 1) allocate memory on host
// 2) allocate memory on device
// 3) initialize memory on host
// 4) copy memory from host to device
// 5) execute kernel(s) on device
// 6) copy result(s) from device to host
//
// Note: it may be possible to initialize memory directly on the device,
// in which case steps 3 and 4 are not necessary, and step 1 is only
// necessary to allocate memory to hold results.
#include <stdio.h>
#include <cuda.h>
//-----------------------------------------------------------------------------
// Kernel that executes on CUDA device
__global__ void add_vectors(
float *c, // out - pointer to result vector c
float *a, // in - pointer to summand vector a
float *b, // in - pointer to summand vector b
int n // in - vector length
)
{
// Assume single block grid and 1-D block
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Only do calculation if we have real data to work with
if ( idx < n ) c[idx] = a[idx] + b[idx];
}
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Main program executes on host device
int main( int argc, char* argv[] )
{
// determine vector length
int n = 10; // set default length
if ( argc > 1 )
{
n = atoi( argv[1] ); // override default length
if ( n <= 0 )
{
fprintf( stderr, "Vector length must be positive\n" );
return EXIT_FAILURE;
}
}
// determine vector size in bytes
const size_t vector_size = n * sizeof( float );
// declare pointers to vectors in host memory and allocate memory
float *a, *b, *c;
a = (float*) malloc( vector_size );
b = (float*) malloc( vector_size );
c = (float*) malloc( vector_size );
// declare pointers to vectors in device memory and allocate memory
float *a_d, *b_d, *c_d;
cudaMalloc( (void**) &a_d, vector_size );
cudaMalloc( (void**) &b_d, vector_size );
cudaMalloc( (void**) &c_d, vector_size );
// initialize vectors and copy them to device
for ( int i = 0; i < n; i++ )
{
a[i] = 1.0 * i;
b[i] = 100.0 * i;
}
cudaMemcpy( a_d, a, vector_size, cudaMemcpyHostToDevice );
cudaMemcpy( b_d, b, vector_size, cudaMemcpyHostToDevice );
// do calculation on device
int block_size = 16;
int num_blocks = ( n - 1 + block_size ) / block_size;
add_vectors<<< num_blocks, block_size >>>( c_d, a_d, b_d, n );
// retrieve result from device and store on host
cudaMemcpy( c, c_d, vector_size, cudaMemcpyDeviceToHost );
// print results for vectors up to length 100
if ( n <= 100 )
{
for ( int i = 0; i < n; i++ )
{
printf( "%8.2f + %8.2f = %8.2f\n", a[i], b[i], c[i] );
}
}
// cleanup and quit
cudaFree( a_d );
cudaFree( b_d );
cudaFree( c_d );
free( a );
free( b );
free( c );
return 0;
}
|
// $Smake: nvcc -O2 -o %F %f
//
// add-vectors.cu - addition of two arrays on GPU device
//
// This program follows a very standard pattern:
// 1) allocate memory on host
// 2) allocate memory on device
// 3) initialize memory on host
// 4) copy memory from host to device
// 5) execute kernel(s) on device
// 6) copy result(s) from device to host
//
// Note: it may be possible to initialize memory directly on the device,
// in which case steps 3 and 4 are not necessary, and step 1 is only
// necessary to allocate memory to hold results.
#include <stdio.h>
#include <hip/hip_runtime.h>
//-----------------------------------------------------------------------------
// Kernel that executes on CUDA device
__global__ void add_vectors(
float *c, // out - pointer to result vector c
float *a, // in - pointer to summand vector a
float *b, // in - pointer to summand vector b
int n // in - vector length
)
{
// Assume single block grid and 1-D block
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Only do calculation if we have real data to work with
if ( idx < n ) c[idx] = a[idx] + b[idx];
}
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Main program executes on host device
int main( int argc, char* argv[] )
{
// determine vector length
int n = 10; // set default length
if ( argc > 1 )
{
n = atoi( argv[1] ); // override default length
if ( n <= 0 )
{
fprintf( stderr, "Vector length must be positive\n" );
return EXIT_FAILURE;
}
}
// determine vector size in bytes
const size_t vector_size = n * sizeof( float );
// declare pointers to vectors in host memory and allocate memory
float *a, *b, *c;
a = (float*) malloc( vector_size );
b = (float*) malloc( vector_size );
c = (float*) malloc( vector_size );
// declare pointers to vectors in device memory and allocate memory
float *a_d, *b_d, *c_d;
hipMalloc( (void**) &a_d, vector_size );
hipMalloc( (void**) &b_d, vector_size );
hipMalloc( (void**) &c_d, vector_size );
// initialize vectors and copy them to device
for ( int i = 0; i < n; i++ )
{
a[i] = 1.0 * i;
b[i] = 100.0 * i;
}
hipMemcpy( a_d, a, vector_size, hipMemcpyHostToDevice );
hipMemcpy( b_d, b, vector_size, hipMemcpyHostToDevice );
// do calculation on device
int block_size = 16;
int num_blocks = ( n - 1 + block_size ) / block_size;
add_vectors<<< num_blocks, block_size >>>( c_d, a_d, b_d, n );
// retrieve result from device and store on host
hipMemcpy( c, c_d, vector_size, hipMemcpyDeviceToHost );
// print results for vectors up to length 100
if ( n <= 100 )
{
for ( int i = 0; i < n; i++ )
{
printf( "%8.2f + %8.2f = %8.2f\n", a[i], b[i], c[i] );
}
}
// cleanup and quit
hipFree( a_d );
hipFree( b_d );
hipFree( c_d );
free( a );
free( b );
free( c );
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// $Smake: nvcc -O2 -o %F %f
//
// add-vectors.cu - addition of two arrays on GPU device
//
// This program follows a very standard pattern:
// 1) allocate memory on host
// 2) allocate memory on device
// 3) initialize memory on host
// 4) copy memory from host to device
// 5) execute kernel(s) on device
// 6) copy result(s) from device to host
//
// Note: it may be possible to initialize memory directly on the device,
// in which case steps 3 and 4 are not necessary, and step 1 is only
// necessary to allocate memory to hold results.
#include <stdio.h>
#include <hip/hip_runtime.h>
//-----------------------------------------------------------------------------
// Kernel that executes on CUDA device
__global__ void add_vectors(
float *c, // out - pointer to result vector c
float *a, // in - pointer to summand vector a
float *b, // in - pointer to summand vector b
int n // in - vector length
)
{
// Assume single block grid and 1-D block
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Only do calculation if we have real data to work with
if ( idx < n ) c[idx] = a[idx] + b[idx];
}
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Main program executes on host device
int main( int argc, char* argv[] )
{
// determine vector length
int n = 10; // set default length
if ( argc > 1 )
{
n = atoi( argv[1] ); // override default length
if ( n <= 0 )
{
fprintf( stderr, "Vector length must be positive\n" );
return EXIT_FAILURE;
}
}
// determine vector size in bytes
const size_t vector_size = n * sizeof( float );
// declare pointers to vectors in host memory and allocate memory
float *a, *b, *c;
a = (float*) malloc( vector_size );
b = (float*) malloc( vector_size );
c = (float*) malloc( vector_size );
// declare pointers to vectors in device memory and allocate memory
float *a_d, *b_d, *c_d;
hipMalloc( (void**) &a_d, vector_size );
hipMalloc( (void**) &b_d, vector_size );
hipMalloc( (void**) &c_d, vector_size );
// initialize vectors and copy them to device
for ( int i = 0; i < n; i++ )
{
a[i] = 1.0 * i;
b[i] = 100.0 * i;
}
hipMemcpy( a_d, a, vector_size, hipMemcpyHostToDevice );
hipMemcpy( b_d, b, vector_size, hipMemcpyHostToDevice );
// do calculation on device
int block_size = 16;
int num_blocks = ( n - 1 + block_size ) / block_size;
add_vectors<<< num_blocks, block_size >>>( c_d, a_d, b_d, n );
// retrieve result from device and store on host
hipMemcpy( c, c_d, vector_size, hipMemcpyDeviceToHost );
// print results for vectors up to length 100
if ( n <= 100 )
{
for ( int i = 0; i < n; i++ )
{
printf( "%8.2f + %8.2f = %8.2f\n", a[i], b[i], c[i] );
}
}
// cleanup and quit
hipFree( a_d );
hipFree( b_d );
hipFree( c_d );
free( a );
free( b );
free( c );
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11add_vectorsPfS_S_i
.globl _Z11add_vectorsPfS_S_i
.p2align 8
.type _Z11add_vectorsPfS_S_i,@function
_Z11add_vectorsPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11add_vectorsPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11add_vectorsPfS_S_i, .Lfunc_end0-_Z11add_vectorsPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11add_vectorsPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11add_vectorsPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// $Smake: nvcc -O2 -o %F %f
//
// add-vectors.cu - addition of two arrays on GPU device
//
// This program follows a very standard pattern:
// 1) allocate memory on host
// 2) allocate memory on device
// 3) initialize memory on host
// 4) copy memory from host to device
// 5) execute kernel(s) on device
// 6) copy result(s) from device to host
//
// Note: it may be possible to initialize memory directly on the device,
// in which case steps 3 and 4 are not necessary, and step 1 is only
// necessary to allocate memory to hold results.
#include <stdio.h>
#include <hip/hip_runtime.h>
//-----------------------------------------------------------------------------
// Kernel that executes on CUDA device
__global__ void add_vectors(
float *c, // out - pointer to result vector c
float *a, // in - pointer to summand vector a
float *b, // in - pointer to summand vector b
int n // in - vector length
)
{
// Assume single block grid and 1-D block
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Only do calculation if we have real data to work with
if ( idx < n ) c[idx] = a[idx] + b[idx];
}
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Main program executes on host device
int main( int argc, char* argv[] )
{
// determine vector length
int n = 10; // set default length
if ( argc > 1 )
{
n = atoi( argv[1] ); // override default length
if ( n <= 0 )
{
fprintf( stderr, "Vector length must be positive\n" );
return EXIT_FAILURE;
}
}
// determine vector size in bytes
const size_t vector_size = n * sizeof( float );
// declare pointers to vectors in host memory and allocate memory
float *a, *b, *c;
a = (float*) malloc( vector_size );
b = (float*) malloc( vector_size );
c = (float*) malloc( vector_size );
// declare pointers to vectors in device memory and allocate memory
float *a_d, *b_d, *c_d;
hipMalloc( (void**) &a_d, vector_size );
hipMalloc( (void**) &b_d, vector_size );
hipMalloc( (void**) &c_d, vector_size );
// initialize vectors and copy them to device
for ( int i = 0; i < n; i++ )
{
a[i] = 1.0 * i;
b[i] = 100.0 * i;
}
hipMemcpy( a_d, a, vector_size, hipMemcpyHostToDevice );
hipMemcpy( b_d, b, vector_size, hipMemcpyHostToDevice );
// do calculation on device
int block_size = 16;
int num_blocks = ( n - 1 + block_size ) / block_size;
add_vectors<<< num_blocks, block_size >>>( c_d, a_d, b_d, n );
// retrieve result from device and store on host
hipMemcpy( c, c_d, vector_size, hipMemcpyDeviceToHost );
// print results for vectors up to length 100
if ( n <= 100 )
{
for ( int i = 0; i < n; i++ )
{
printf( "%8.2f + %8.2f = %8.2f\n", a[i], b[i], c[i] );
}
}
// cleanup and quit
hipFree( a_d );
hipFree( b_d );
hipFree( c_d );
free( a );
free( b );
free( c );
return 0;
}
|
.text
.file "add-vectors.hip"
.globl _Z26__device_stub__add_vectorsPfS_S_i # -- Begin function _Z26__device_stub__add_vectorsPfS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__add_vectorsPfS_S_i,@function
_Z26__device_stub__add_vectorsPfS_S_i: # @_Z26__device_stub__add_vectorsPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11add_vectorsPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__add_vectorsPfS_S_i, .Lfunc_end0-_Z26__device_stub__add_vectorsPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4059000000000000 # double 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10, %ebx
cmpl $2, %edi
jl .LBB1_3
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
testl %ebx, %ebx
jle .LBB1_2
.LBB1_3:
movl %ebx, %r13d
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
cmpl $1, %ebx
movl %ebx, %eax
adcl $0, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
xorps %xmm2, %xmm2
cvtsi2ss %ecx, %xmm2
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm2, (%r14,%rcx,4)
movss %xmm1, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
# %bb.5:
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%rbx), %edi
shrl $4, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11add_vectorsPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $100, %ebx
ja .LBB1_10
# %bb.8: # %.preheader.preheader
cmpl $1, %ebx
adcl $0, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r12,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movb $3, %al
callq printf
incq %r13
cmpq %r13, %rbx
jne .LBB1_9
.LBB1_10: # %.loopexit
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
.LBB1_11:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $31, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_11
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11add_vectorsPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11add_vectorsPfS_S_i,@object # @_Z11add_vectorsPfS_S_i
.section .rodata,"a",@progbits
.globl _Z11add_vectorsPfS_S_i
.p2align 3, 0x0
_Z11add_vectorsPfS_S_i:
.quad _Z26__device_stub__add_vectorsPfS_S_i
.size _Z11add_vectorsPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Vector length must be positive\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%8.2f + %8.2f = %8.2f\n"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11add_vectorsPfS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__add_vectorsPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11add_vectorsPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11add_vectorsPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11add_vectorsPfS_S_i
.globl _Z11add_vectorsPfS_S_i
.p2align 8
.type _Z11add_vectorsPfS_S_i,@function
_Z11add_vectorsPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11add_vectorsPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11add_vectorsPfS_S_i, .Lfunc_end0-_Z11add_vectorsPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11add_vectorsPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11add_vectorsPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0006ca38_00000000-6_add-vectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
.type _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i, @function
_Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11add_vectorsPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i, .-_Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
.globl _Z11add_vectorsPfS_S_i
.type _Z11add_vectorsPfS_S_i, @function
_Z11add_vectorsPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11add_vectorsPfS_S_i, .-_Z11add_vectorsPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Vector length must be positive\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%8.2f + %8.2f = %8.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L19
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r15d
testl %eax, %eax
jle .L23
.L12:
movslq %r15d, %r13
leaq 0(,%r13,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %eax
movsd .LC1(%rip), %xmm2
.L14:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movss %xmm1, 0(%rbp,%rax,4)
mulsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %r13
jne .L14
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $1, 48(%rsp)
leal 30(%r15), %eax
movl %r15d, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
cmpl $100, %r15d
jg .L16
movl $0, %r13d
leaq .LC2(%rip), %r15
.L17:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r13), %xmm0
pxor %xmm2, %xmm2
cvtss2sd (%r14,%r13), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%rbx,%r13), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r12, %r13
jne .L17
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movl $0, %eax
.L11:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L11
.L19:
movl $10, %r15d
jmp .L12
.L24:
movl %r15d, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z11add_vectorsPfS_S_iPfS_S_i
jmp .L15
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11add_vectorsPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11add_vectorsPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "add-vectors.hip"
.globl _Z26__device_stub__add_vectorsPfS_S_i # -- Begin function _Z26__device_stub__add_vectorsPfS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__add_vectorsPfS_S_i,@function
_Z26__device_stub__add_vectorsPfS_S_i: # @_Z26__device_stub__add_vectorsPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11add_vectorsPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__add_vectorsPfS_S_i, .Lfunc_end0-_Z26__device_stub__add_vectorsPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4059000000000000 # double 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10, %ebx
cmpl $2, %edi
jl .LBB1_3
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
testl %ebx, %ebx
jle .LBB1_2
.LBB1_3:
movl %ebx, %r13d
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
cmpl $1, %ebx
movl %ebx, %eax
adcl $0, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
xorps %xmm2, %xmm2
cvtsi2ss %ecx, %xmm2
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm2, (%r14,%rcx,4)
movss %xmm1, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_4
# %bb.5:
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%rbx), %edi
shrl $4, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11add_vectorsPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $100, %ebx
ja .LBB1_10
# %bb.8: # %.preheader.preheader
cmpl $1, %ebx
adcl $0, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r12,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movb $3, %al
callq printf
incq %r13
cmpq %r13, %rbx
jne .LBB1_9
.LBB1_10: # %.loopexit
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
.LBB1_11:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $31, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_11
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11add_vectorsPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11add_vectorsPfS_S_i,@object # @_Z11add_vectorsPfS_S_i
.section .rodata,"a",@progbits
.globl _Z11add_vectorsPfS_S_i
.p2align 3, 0x0
_Z11add_vectorsPfS_S_i:
.quad _Z26__device_stub__add_vectorsPfS_S_i
.size _Z11add_vectorsPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Vector length must be positive\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%8.2f + %8.2f = %8.2f\n"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11add_vectorsPfS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__add_vectorsPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11add_vectorsPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void binZeros(int *d_bin_count, int bin_size){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < bin_size){
d_bin_count[i] = 0;
}
}
|
code for sm_80
Function : _Z8binZerosPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void binZeros(int *d_bin_count, int bin_size){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < bin_size){
d_bin_count[i] = 0;
}
}
|
.file "tmpxft_00169fae_00000000-6_binZeros.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8binZerosPiiPii
.type _Z28__device_stub__Z8binZerosPiiPii, @function
_Z28__device_stub__Z8binZerosPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8binZerosPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8binZerosPiiPii, .-_Z28__device_stub__Z8binZerosPiiPii
.globl _Z8binZerosPii
.type _Z8binZerosPii, @function
_Z8binZerosPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8binZerosPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8binZerosPii, .-_Z8binZerosPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8binZerosPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8binZerosPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void binZeros(int *d_bin_count, int bin_size){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < bin_size){
d_bin_count[i] = 0;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void binZeros(int *d_bin_count, int bin_size){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < bin_size){
d_bin_count[i] = 0;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void binZeros(int *d_bin_count, int bin_size){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < bin_size){
d_bin_count[i] = 0;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8binZerosPii
.globl _Z8binZerosPii
.p2align 8
.type _Z8binZerosPii,@function
_Z8binZerosPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8binZerosPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8binZerosPii, .Lfunc_end0-_Z8binZerosPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8binZerosPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8binZerosPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void binZeros(int *d_bin_count, int bin_size){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < bin_size){
d_bin_count[i] = 0;
}
}
|
.text
.file "binZeros.hip"
.globl _Z23__device_stub__binZerosPii # -- Begin function _Z23__device_stub__binZerosPii
.p2align 4, 0x90
.type _Z23__device_stub__binZerosPii,@function
_Z23__device_stub__binZerosPii: # @_Z23__device_stub__binZerosPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8binZerosPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__binZerosPii, .Lfunc_end0-_Z23__device_stub__binZerosPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8binZerosPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8binZerosPii,@object # @_Z8binZerosPii
.section .rodata,"a",@progbits
.globl _Z8binZerosPii
.p2align 3, 0x0
_Z8binZerosPii:
.quad _Z23__device_stub__binZerosPii
.size _Z8binZerosPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8binZerosPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__binZerosPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8binZerosPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z8binZerosPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8binZerosPii
.globl _Z8binZerosPii
.p2align 8
.type _Z8binZerosPii,@function
_Z8binZerosPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8binZerosPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8binZerosPii, .Lfunc_end0-_Z8binZerosPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8binZerosPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8binZerosPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00169fae_00000000-6_binZeros.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8binZerosPiiPii
.type _Z28__device_stub__Z8binZerosPiiPii, @function
_Z28__device_stub__Z8binZerosPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8binZerosPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8binZerosPiiPii, .-_Z28__device_stub__Z8binZerosPiiPii
.globl _Z8binZerosPii
.type _Z8binZerosPii, @function
_Z8binZerosPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8binZerosPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8binZerosPii, .-_Z8binZerosPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8binZerosPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8binZerosPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "binZeros.hip"
.globl _Z23__device_stub__binZerosPii # -- Begin function _Z23__device_stub__binZerosPii
.p2align 4, 0x90
.type _Z23__device_stub__binZerosPii,@function
_Z23__device_stub__binZerosPii: # @_Z23__device_stub__binZerosPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8binZerosPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__binZerosPii, .Lfunc_end0-_Z23__device_stub__binZerosPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8binZerosPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8binZerosPii,@object # @_Z8binZerosPii
.section .rodata,"a",@progbits
.globl _Z8binZerosPii
.p2align 3, 0x0
_Z8binZerosPii:
.quad _Z23__device_stub__binZerosPii
.size _Z8binZerosPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8binZerosPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__binZerosPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8binZerosPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
/**
*
* Copyright (C) Tyler Hackett 2016
*
* CUDA Triangle Counter
*
* A quickly-written program to determine all possible combinations of
* valid triangles from a grid, allowing for certain coordinates of the
* grid to be marked as unusable.
*
* main.cu
*
* */
__global__ void countTriangles(uint2 *validPoints, int *count)
{
/* Only allow operations on blocks where x < y < z, to prevent repeat triangles*/
if (blockIdx.x > blockIdx.y || blockIdx.y > blockIdx.z || blockIdx.x > blockIdx.z)
return;
uint2 x, y, z;
x = validPoints[blockIdx.x];
y = validPoints[blockIdx.y];
z = validPoints[blockIdx.z];
/*Check if the points are coplanar.*/
if ((x.x == y.x || x.y == y.y) && (y.x == z.x || y.y == z.y) && (x.x == z.x || x.y == z.y))
return;
/*Check for any coincident points.*/
if ((x.x == y.x && x.y == y.y) || (y.x == z.x && y.y == z.y) || (x.x == z.x && x.y == z.y))
return;
/*If the thread makes it this far, then we have a triangle that obeys the laws of geometry!*/
atomicAdd(count, 1);
}
|
code for sm_80
Function : _Z14countTrianglesP5uint2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002600 */
/*0020*/ S2R R6, SR_CTAID.Z ; /* 0x0000000000067919 */
/* 0x000e280000002700 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R4, R6, PT ; /* 0x000000060400720c */
/* 0x001fc80003f04070 */
/*0050*/ ISETP.GT.U32.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x002fc80000704470 */
/*0060*/ ISETP.GT.U32.OR P0, PT, R3, R6, P0 ; /* 0x000000060300720c */
/* 0x000fda0000704470 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE.U32 R2, R3, R7, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0007 */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R7.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e0007 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0007 */
/*00e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0100*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x004fc40003f05270 */
/*0110*/ ISETP.NE.AND P2, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x008fe40003f45270 */
/*0120*/ ISETP.NE.AND P0, PT, R2, R4, P0 ; /* 0x000000040200720c */
/* 0x000fe40000705270 */
/*0130*/ ISETP.EQ.OR P1, PT, R4, R6, !P2 ; /* 0x000000060400720c */
/* 0x000fda0005722670 */
/*0140*/ @P1 BRA !P0, 0x190 ; /* 0x0000004000001947 */
/* 0x000fea0004000000 */
/*0150*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fe40003f05270 */
/*0160*/ ISETP.EQ.AND P1, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x000fda0003f22270 */
/*0170*/ @!P0 EXIT P1 ; /* 0x000000000000894d */
/* 0x000fea0000800000 */
/*0180*/ BRA 0x1f0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.NE.AND P1, PT, R3.reuse, R7, PT ; /* 0x000000070300720c */
/* 0x040fe40003f25270 */
/*01a0*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fe40003f05270 */
/*01b0*/ ISETP.EQ.OR P1, PT, R2.reuse, R6, !P1 ; /* 0x000000060200720c */
/* 0x040fe40004f22670 */
/*01c0*/ ISETP.EQ.AND P0, PT, R2, R4, !P0 ; /* 0x000000040200720c */
/* 0x000fc80004702270 */
/*01d0*/ PLOP3.LUT P1, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000723570 */
/*01e0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.EQ.AND P0, PT, R4, R6, PT ; /* 0x000000060400720c */
/* 0x000fda0003f02270 */
/*0200*/ @!P2 EXIT P0 ; /* 0x000000000000a94d */
/* 0x000fea0000000000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, R7, PT ; /* 0x000000070300720c */
/* 0x000fe40003f05270 */
/*0220*/ ISETP.EQ.AND P1, PT, R2, R6, PT ; /* 0x000000060200720c */
/* 0x000fda0003f22270 */
/*0230*/ @!P0 EXIT P1 ; /* 0x000000000000894d */
/* 0x000fea0000800000 */
/*0240*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0250*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0270*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0280*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc800078e00ff */
/*02a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*02b0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
/**
*
* Copyright (C) Tyler Hackett 2016
*
* CUDA Triangle Counter
*
* A quickly-written program to determine all possible combinations of
* valid triangles from a grid, allowing for certain coordinates of the
* grid to be marked as unusable.
*
* main.cu
*
* */
__global__ void countTriangles(uint2 *validPoints, int *count)
{
/* Only allow operations on blocks where x < y < z, to prevent repeat triangles*/
if (blockIdx.x > blockIdx.y || blockIdx.y > blockIdx.z || blockIdx.x > blockIdx.z)
return;
uint2 x, y, z;
x = validPoints[blockIdx.x];
y = validPoints[blockIdx.y];
z = validPoints[blockIdx.z];
/*Check if the points are coplanar.*/
if ((x.x == y.x || x.y == y.y) && (y.x == z.x || y.y == z.y) && (x.x == z.x || x.y == z.y))
return;
/*Check for any coincident points.*/
if ((x.x == y.x && x.y == y.y) || (y.x == z.x && y.y == z.y) || (x.x == z.x && x.y == z.y))
return;
/*If the thread makes it this far, then we have a triangle that obeys the laws of geometry!*/
atomicAdd(count, 1);
}
|
.file "tmpxft_0011b8c8_00000000-6_countTriangles.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi
.type _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi, @function
_Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14countTrianglesP5uint2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi, .-_Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi
.globl _Z14countTrianglesP5uint2Pi
.type _Z14countTrianglesP5uint2Pi, @function
_Z14countTrianglesP5uint2Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14countTrianglesP5uint2Pi, .-_Z14countTrianglesP5uint2Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14countTrianglesP5uint2Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14countTrianglesP5uint2Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
/**
*
* Copyright (C) Tyler Hackett 2016
*
* CUDA Triangle Counter
*
* A quickly-written program to determine all possible combinations of
* valid triangles from a grid, allowing for certain coordinates of the
* grid to be marked as unusable.
*
* main.cu
*
* */
__global__ void countTriangles(uint2 *validPoints, int *count)
{
/* Only allow operations on blocks where x < y < z, to prevent repeat triangles*/
if (blockIdx.x > blockIdx.y || blockIdx.y > blockIdx.z || blockIdx.x > blockIdx.z)
return;
uint2 x, y, z;
x = validPoints[blockIdx.x];
y = validPoints[blockIdx.y];
z = validPoints[blockIdx.z];
/*Check if the points are coplanar.*/
if ((x.x == y.x || x.y == y.y) && (y.x == z.x || y.y == z.y) && (x.x == z.x || x.y == z.y))
return;
/*Check for any coincident points.*/
if ((x.x == y.x && x.y == y.y) || (y.x == z.x && y.y == z.y) || (x.x == z.x && x.y == z.y))
return;
/*If the thread makes it this far, then we have a triangle that obeys the laws of geometry!*/
atomicAdd(count, 1);
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
/**
*
* Copyright (C) Tyler Hackett 2016
*
* CUDA Triangle Counter
*
* A quickly-written program to determine all possible combinations of
* valid triangles from a grid, allowing for certain coordinates of the
* grid to be marked as unusable.
*
* main.cu
*
* */
__global__ void countTriangles(uint2 *validPoints, int *count)
{
/* Only allow operations on blocks where x < y < z, to prevent repeat triangles*/
if (blockIdx.x > blockIdx.y || blockIdx.y > blockIdx.z || blockIdx.x > blockIdx.z)
return;
uint2 x, y, z;
x = validPoints[blockIdx.x];
y = validPoints[blockIdx.y];
z = validPoints[blockIdx.z];
/*Check if the points are coplanar.*/
if ((x.x == y.x || x.y == y.y) && (y.x == z.x || y.y == z.y) && (x.x == z.x || x.y == z.y))
return;
/*Check for any coincident points.*/
if ((x.x == y.x && x.y == y.y) || (y.x == z.x && y.y == z.y) || (x.x == z.x && x.y == z.y))
return;
/*If the thread makes it this far, then we have a triangle that obeys the laws of geometry!*/
atomicAdd(count, 1);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
/**
*
* Copyright (C) Tyler Hackett 2016
*
* CUDA Triangle Counter
*
* A quickly-written program to determine all possible combinations of
* valid triangles from a grid, allowing for certain coordinates of the
* grid to be marked as unusable.
*
* main.cu
*
* */
__global__ void countTriangles(uint2 *validPoints, int *count)
{
/* Only allow operations on blocks where x < y < z, to prevent repeat triangles*/
if (blockIdx.x > blockIdx.y || blockIdx.y > blockIdx.z || blockIdx.x > blockIdx.z)
return;
uint2 x, y, z;
x = validPoints[blockIdx.x];
y = validPoints[blockIdx.y];
z = validPoints[blockIdx.z];
/*Check if the points are coplanar.*/
if ((x.x == y.x || x.y == y.y) && (y.x == z.x || y.y == z.y) && (x.x == z.x || x.y == z.y))
return;
/*Check for any coincident points.*/
if ((x.x == y.x && x.y == y.y) || (y.x == z.x && y.y == z.y) || (x.x == z.x && x.y == z.y))
return;
/*If the thread makes it this far, then we have a triangle that obeys the laws of geometry!*/
atomicAdd(count, 1);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.globl _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.p2align 8
.type _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi,@function
_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi:
s_cmp_gt_u32 s13, s14
s_cbranch_scc1 .LBB0_6
s_max_u32 s3, s14, s13
s_mov_b32 s8, s15
s_mov_b32 s2, s13
s_cmp_gt_u32 s3, s15
s_cbranch_scc1 .LBB0_6
s_load_b64 s[10:11], s[0:1], 0x0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 3
s_mov_b32 s15, s3
s_mov_b32 s9, s3
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s10, s4
s_addc_u32 s5, s11, s5
s_lshl_b64 s[6:7], s[14:15], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
s_clause 0x1
s_load_b64 s[4:5], s[4:5], 0x0
s_load_b64 s[6:7], s[6:7], 0x0
s_lshl_b64 s[8:9], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s10, s8
s_addc_u32 s9, s11, s9
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, s6
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s5, s7
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s2, s10
s_xor_b32 s12, s11, -1
s_mov_b32 s11, 0
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccz .LBB0_7
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccz .LBB0_8
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccz .LBB0_9
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_10
.LBB0_6:
s_endpgm
.LBB0_7:
s_cmp_lg_u32 s6, s8
s_cselect_b32 s11, -1, 0
s_cmp_lg_u32 s7, s9
s_cselect_b32 s12, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s12, s11, s12
s_mov_b32 s11, -1
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_4
.LBB0_8:
s_and_b32 s3, s2, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, s3, -1
s_cbranch_execnz .LBB0_5
.LBB0_9:
s_cmp_eq_u32 s4, s8
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s5, s9
s_cselect_b32 s11, -1, 0
s_and_b32 s2, s2, s10
s_or_b32 s3, s3, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_xor_b32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_6
.LBB0_10:
s_cmp_eq_u32 s6, s8
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s7, s9
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_6
s_cmp_eq_u32 s4, s8
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s5, s9
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_6
s_mov_b32 s2, exec_lo
s_mov_b32 s3, exec_lo
v_mbcnt_lo_u32_b32 v0, s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, .Lfunc_end0-_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
/**
*
* Copyright (C) Tyler Hackett 2016
*
* CUDA Triangle Counter
*
* A quickly-written program to determine all possible combinations of
* valid triangles from a grid, allowing for certain coordinates of the
* grid to be marked as unusable.
*
* main.cu
*
* */
__global__ void countTriangles(uint2 *validPoints, int *count)
{
/* Only allow operations on blocks where x < y < z, to prevent repeat triangles*/
if (blockIdx.x > blockIdx.y || blockIdx.y > blockIdx.z || blockIdx.x > blockIdx.z)
return;
uint2 x, y, z;
x = validPoints[blockIdx.x];
y = validPoints[blockIdx.y];
z = validPoints[blockIdx.z];
/*Check if the points are coplanar.*/
if ((x.x == y.x || x.y == y.y) && (y.x == z.x || y.y == z.y) && (x.x == z.x || x.y == z.y))
return;
/*Check for any coincident points.*/
if ((x.x == y.x && x.y == y.y) || (y.x == z.x && y.y == z.y) || (x.x == z.x && x.y == z.y))
return;
/*If the thread makes it this far, then we have a triangle that obeys the laws of geometry!*/
atomicAdd(count, 1);
}
|
.text
.file "countTriangles.hip"
.globl _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi # -- Begin function _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.p2align 4, 0x90
.type _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi,@function
_Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi: # @_Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi, .Lfunc_end0-_Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi,@object # @_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.section .rodata,"a",@progbits
.globl _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.p2align 3, 0x0
_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi:
.quad _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.size _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z14countTrianglesP5uint2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002600 */
/*0020*/ S2R R6, SR_CTAID.Z ; /* 0x0000000000067919 */
/* 0x000e280000002700 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R4, R6, PT ; /* 0x000000060400720c */
/* 0x001fc80003f04070 */
/*0050*/ ISETP.GT.U32.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x002fc80000704470 */
/*0060*/ ISETP.GT.U32.OR P0, PT, R3, R6, P0 ; /* 0x000000060300720c */
/* 0x000fda0000704470 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE.U32 R2, R3, R7, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0007 */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R7.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e0007 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0007 */
/*00e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0100*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x004fc40003f05270 */
/*0110*/ ISETP.NE.AND P2, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x008fe40003f45270 */
/*0120*/ ISETP.NE.AND P0, PT, R2, R4, P0 ; /* 0x000000040200720c */
/* 0x000fe40000705270 */
/*0130*/ ISETP.EQ.OR P1, PT, R4, R6, !P2 ; /* 0x000000060400720c */
/* 0x000fda0005722670 */
/*0140*/ @P1 BRA !P0, 0x190 ; /* 0x0000004000001947 */
/* 0x000fea0004000000 */
/*0150*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fe40003f05270 */
/*0160*/ ISETP.EQ.AND P1, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x000fda0003f22270 */
/*0170*/ @!P0 EXIT P1 ; /* 0x000000000000894d */
/* 0x000fea0000800000 */
/*0180*/ BRA 0x1f0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.NE.AND P1, PT, R3.reuse, R7, PT ; /* 0x000000070300720c */
/* 0x040fe40003f25270 */
/*01a0*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fe40003f05270 */
/*01b0*/ ISETP.EQ.OR P1, PT, R2.reuse, R6, !P1 ; /* 0x000000060200720c */
/* 0x040fe40004f22670 */
/*01c0*/ ISETP.EQ.AND P0, PT, R2, R4, !P0 ; /* 0x000000040200720c */
/* 0x000fc80004702270 */
/*01d0*/ PLOP3.LUT P1, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000723570 */
/*01e0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.EQ.AND P0, PT, R4, R6, PT ; /* 0x000000060400720c */
/* 0x000fda0003f02270 */
/*0200*/ @!P2 EXIT P0 ; /* 0x000000000000a94d */
/* 0x000fea0000000000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, R7, PT ; /* 0x000000070300720c */
/* 0x000fe40003f05270 */
/*0220*/ ISETP.EQ.AND P1, PT, R2, R6, PT ; /* 0x000000060200720c */
/* 0x000fda0003f22270 */
/*0230*/ @!P0 EXIT P1 ; /* 0x000000000000894d */
/* 0x000fea0000800000 */
/*0240*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0250*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0270*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0280*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc800078e00ff */
/*02a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*02b0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.globl _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.p2align 8
.type _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi,@function
_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi:
s_cmp_gt_u32 s13, s14
s_cbranch_scc1 .LBB0_6
s_max_u32 s3, s14, s13
s_mov_b32 s8, s15
s_mov_b32 s2, s13
s_cmp_gt_u32 s3, s15
s_cbranch_scc1 .LBB0_6
s_load_b64 s[10:11], s[0:1], 0x0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 3
s_mov_b32 s15, s3
s_mov_b32 s9, s3
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s10, s4
s_addc_u32 s5, s11, s5
s_lshl_b64 s[6:7], s[14:15], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
s_clause 0x1
s_load_b64 s[4:5], s[4:5], 0x0
s_load_b64 s[6:7], s[6:7], 0x0
s_lshl_b64 s[8:9], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s10, s8
s_addc_u32 s9, s11, s9
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, s6
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s5, s7
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s2, s10
s_xor_b32 s12, s11, -1
s_mov_b32 s11, 0
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccz .LBB0_7
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccz .LBB0_8
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccz .LBB0_9
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_10
.LBB0_6:
s_endpgm
.LBB0_7:
s_cmp_lg_u32 s6, s8
s_cselect_b32 s11, -1, 0
s_cmp_lg_u32 s7, s9
s_cselect_b32 s12, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s12, s11, s12
s_mov_b32 s11, -1
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_4
.LBB0_8:
s_and_b32 s3, s2, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, s3, -1
s_cbranch_execnz .LBB0_5
.LBB0_9:
s_cmp_eq_u32 s4, s8
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s5, s9
s_cselect_b32 s11, -1, 0
s_and_b32 s2, s2, s10
s_or_b32 s3, s3, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_xor_b32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_6
.LBB0_10:
s_cmp_eq_u32 s6, s8
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s7, s9
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_6
s_cmp_eq_u32 s4, s8
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s5, s9
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_6
s_mov_b32 s2, exec_lo
s_mov_b32 s3, exec_lo
v_mbcnt_lo_u32_b32 v0, s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, .Lfunc_end0-_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0011b8c8_00000000-6_countTriangles.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi
.type _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi, @function
_Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14countTrianglesP5uint2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi, .-_Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi
.globl _Z14countTrianglesP5uint2Pi
.type _Z14countTrianglesP5uint2Pi, @function
_Z14countTrianglesP5uint2Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14countTrianglesP5uint2PiP5uint2Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14countTrianglesP5uint2Pi, .-_Z14countTrianglesP5uint2Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14countTrianglesP5uint2Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14countTrianglesP5uint2Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "countTriangles.hip"
.globl _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi # -- Begin function _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.p2align 4, 0x90
.type _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi,@function
_Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi: # @_Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi, .Lfunc_end0-_Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi,@object # @_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.section .rodata,"a",@progbits
.globl _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.p2align 3, 0x0
_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi:
.quad _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.size _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14countTrianglesP15HIP_vector_typeIjLj2EEPi"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__countTrianglesP15HIP_vector_typeIjLj2EEPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14countTrianglesP15HIP_vector_typeIjLj2EEPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* d_vec1, int* d_vec2, int* d_vec3)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
d_vec3[idx] = d_vec2[idx] + d_vec1[idx];
}
int main()
{
int i ;
int num_blocks = 1000;
int num_threads = 512;
int SIZE = num_threads*num_blocks;
int BYTES = SIZE * sizeof(int);
// declare device and host variables
int h_vec1[SIZE],h_vec2[SIZE],h_vec3[SIZE];
int *d_vec1, *d_vec2, *d_vec3;
// allocate memory on the device
cudaMalloc((void**)&d_vec1,BYTES);
cudaMalloc((void**)&d_vec2,BYTES);
cudaMalloc((void**)&d_vec3,BYTES);
// generate array on host
for(i=0;i<SIZE;i++)
{
h_vec1[i] = rand()%20;
h_vec2[i] = rand()%20;
h_vec3[i] = 0;
}
// move variables from host to device
cudaMemcpy(d_vec1,h_vec1,BYTES,cudaMemcpyHostToDevice);
cudaMemcpy(d_vec2,h_vec2,BYTES,cudaMemcpyHostToDevice);
// lauch kernel
add<<<num_blocks,num_threads>>>(d_vec1,d_vec2,d_vec3);
// move result back to main memory
cudaMemcpy(h_vec3,d_vec3,BYTES,cudaMemcpyDeviceToHost);
//print result
for(i=0;i<SIZE;i++)
printf("%d ", h_vec3[i]);
}
|
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* d_vec1, int* d_vec2, int* d_vec3)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
d_vec3[idx] = d_vec2[idx] + d_vec1[idx];
}
int main()
{
int i ;
int num_blocks = 1000;
int num_threads = 512;
int SIZE = num_threads*num_blocks;
int BYTES = SIZE * sizeof(int);
// declare device and host variables
int h_vec1[SIZE],h_vec2[SIZE],h_vec3[SIZE];
int *d_vec1, *d_vec2, *d_vec3;
// allocate memory on the device
cudaMalloc((void**)&d_vec1,BYTES);
cudaMalloc((void**)&d_vec2,BYTES);
cudaMalloc((void**)&d_vec3,BYTES);
// generate array on host
for(i=0;i<SIZE;i++)
{
h_vec1[i] = rand()%20;
h_vec2[i] = rand()%20;
h_vec3[i] = 0;
}
// move variables from host to device
cudaMemcpy(d_vec1,h_vec1,BYTES,cudaMemcpyHostToDevice);
cudaMemcpy(d_vec2,h_vec2,BYTES,cudaMemcpyHostToDevice);
// lauch kernel
add<<<num_blocks,num_threads>>>(d_vec1,d_vec2,d_vec3);
// move result back to main memory
cudaMemcpy(h_vec3,d_vec3,BYTES,cudaMemcpyDeviceToHost);
//print result
for(i=0;i<SIZE;i++)
printf("%d ", h_vec3[i]);
}
|
.file "tmpxft_0006ffb4_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $64, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -2048000(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsp, %r13
leaq -2048000(%rsp), %rax
.L15:
cmpq %rax, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
movq %rsp, %r14
leaq -2048000(%rsp), %rax
.L18:
cmpq %rax, %rsp
je .L19
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L18
.L19:
movq %rsp, %r12
leaq -88(%rbp), %rdi
movl $2048000, %esi
call cudaMalloc@PLT
leaq -80(%rbp), %rdi
movl $2048000, %esi
call cudaMalloc@PLT
leaq -72(%rbp), %rdi
movl $2048000, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L21:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%r14,%rbx)
movl $0, (%r12,%rbx)
addq $4, %rbx
cmpq $2048000, %rbx
jne .L21
movl $1, %ecx
movl $2048000, %edx
movq %r13, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048000, %edx
movq %r14, %rsi
movq -80(%rbp), %rdi
call cudaMemcpy@PLT
movl $512, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1000, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
movl $2, %ecx
movl $2048000, %edx
movq -72(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbx
addq $2048000, %r12
leaq .LC0(%rip), %r13
.L23:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L23
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L28:
.cfi_restore_state
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
movq -88(%rbp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* d_vec1, int* d_vec2, int* d_vec3)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
d_vec3[idx] = d_vec2[idx] + d_vec1[idx];
}
int main()
{
int i ;
int num_blocks = 1000;
int num_threads = 512;
int SIZE = num_threads*num_blocks;
int BYTES = SIZE * sizeof(int);
// declare device and host variables
int h_vec1[SIZE],h_vec2[SIZE],h_vec3[SIZE];
int *d_vec1, *d_vec2, *d_vec3;
// allocate memory on the device
cudaMalloc((void**)&d_vec1,BYTES);
cudaMalloc((void**)&d_vec2,BYTES);
cudaMalloc((void**)&d_vec3,BYTES);
// generate array on host
for(i=0;i<SIZE;i++)
{
h_vec1[i] = rand()%20;
h_vec2[i] = rand()%20;
h_vec3[i] = 0;
}
// move variables from host to device
cudaMemcpy(d_vec1,h_vec1,BYTES,cudaMemcpyHostToDevice);
cudaMemcpy(d_vec2,h_vec2,BYTES,cudaMemcpyHostToDevice);
// lauch kernel
add<<<num_blocks,num_threads>>>(d_vec1,d_vec2,d_vec3);
// move result back to main memory
cudaMemcpy(h_vec3,d_vec3,BYTES,cudaMemcpyDeviceToHost);
//print result
for(i=0;i<SIZE;i++)
printf("%d ", h_vec3[i]);
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* d_vec1, int* d_vec2, int* d_vec3)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
d_vec3[idx] = d_vec2[idx] + d_vec1[idx];
}
int main()
{
int i ;
int num_blocks = 1000;
int num_threads = 512;
int SIZE = num_threads*num_blocks;
int BYTES = SIZE * sizeof(int);
// declare device and host variables
int h_vec1[SIZE],h_vec2[SIZE],h_vec3[SIZE];
int *d_vec1, *d_vec2, *d_vec3;
// allocate memory on the device
hipMalloc((void**)&d_vec1,BYTES);
hipMalloc((void**)&d_vec2,BYTES);
hipMalloc((void**)&d_vec3,BYTES);
// generate array on host
for(i=0;i<SIZE;i++)
{
h_vec1[i] = rand()%20;
h_vec2[i] = rand()%20;
h_vec3[i] = 0;
}
// move variables from host to device
hipMemcpy(d_vec1,h_vec1,BYTES,hipMemcpyHostToDevice);
hipMemcpy(d_vec2,h_vec2,BYTES,hipMemcpyHostToDevice);
// lauch kernel
add<<<num_blocks,num_threads>>>(d_vec1,d_vec2,d_vec3);
// move result back to main memory
hipMemcpy(h_vec3,d_vec3,BYTES,hipMemcpyDeviceToHost);
//print result
for(i=0;i<SIZE;i++)
printf("%d ", h_vec3[i]);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* d_vec1, int* d_vec2, int* d_vec3)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
d_vec3[idx] = d_vec2[idx] + d_vec1[idx];
}
int main()
{
int i ;
int num_blocks = 1000;
int num_threads = 512;
int SIZE = num_threads*num_blocks;
int BYTES = SIZE * sizeof(int);
// declare device and host variables
int h_vec1[SIZE],h_vec2[SIZE],h_vec3[SIZE];
int *d_vec1, *d_vec2, *d_vec3;
// allocate memory on the device
hipMalloc((void**)&d_vec1,BYTES);
hipMalloc((void**)&d_vec2,BYTES);
hipMalloc((void**)&d_vec3,BYTES);
// generate array on host
for(i=0;i<SIZE;i++)
{
h_vec1[i] = rand()%20;
h_vec2[i] = rand()%20;
h_vec3[i] = 0;
}
// move variables from host to device
hipMemcpy(d_vec1,h_vec1,BYTES,hipMemcpyHostToDevice);
hipMemcpy(d_vec2,h_vec2,BYTES,hipMemcpyHostToDevice);
// lauch kernel
add<<<num_blocks,num_threads>>>(d_vec1,d_vec2,d_vec3);
// move result back to main memory
hipMemcpy(h_vec3,d_vec3,BYTES,hipMemcpyDeviceToHost);
//print result
for(i=0;i<SIZE;i++)
printf("%d ", h_vec3[i]);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int* d_vec1, int* d_vec2, int* d_vec3)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
d_vec3[idx] = d_vec2[idx] + d_vec1[idx];
}
int main()
{
int i ;
int num_blocks = 1000;
int num_threads = 512;
int SIZE = num_threads*num_blocks;
int BYTES = SIZE * sizeof(int);
// declare device and host variables
int h_vec1[SIZE],h_vec2[SIZE],h_vec3[SIZE];
int *d_vec1, *d_vec2, *d_vec3;
// allocate memory on the device
hipMalloc((void**)&d_vec1,BYTES);
hipMalloc((void**)&d_vec2,BYTES);
hipMalloc((void**)&d_vec3,BYTES);
// generate array on host
for(i=0;i<SIZE;i++)
{
h_vec1[i] = rand()%20;
h_vec2[i] = rand()%20;
h_vec3[i] = 0;
}
// move variables from host to device
hipMemcpy(d_vec1,h_vec1,BYTES,hipMemcpyHostToDevice);
hipMemcpy(d_vec2,h_vec2,BYTES,hipMemcpyHostToDevice);
// lauch kernel
add<<<num_blocks,num_threads>>>(d_vec1,d_vec2,d_vec3);
// move result back to main memory
hipMemcpy(h_vec3,d_vec3,BYTES,hipMemcpyDeviceToHost);
//print result
for(i=0;i<SIZE;i++)
printf("%d ", h_vec3[i]);
}
|
.text
.file "q2.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $6144128, %rsp # imm = 0x5DC080
.cfi_def_cfa_offset 6144144
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $2048000, %esi # imm = 0x1F4000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048000, %esi # imm = 0x1F4000
callq hipMalloc
movq %rsp, %rdi
movl $2048000, %esi # imm = 0x1F4000
callq hipMalloc
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 4096128(%rsp,%rbx,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 2048128(%rsp,%rbx,4)
movl $0, 128(%rsp,%rbx,4)
incq %rbx
cmpq $512000, %rbx # imm = 0x7D000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 4096128(%rsp), %rsi
movl $2048000, %edx # imm = 0x1F4000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 2048128(%rsp), %rsi
movl $2048000, %edx # imm = 0x1F4000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 488(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $2048000, %edx # imm = 0x1F4000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $512000, %rbx # imm = 0x7D000
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $6144128, %rsp # imm = 0x5DC080
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0006ffb4_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $64, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -2048000(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsp, %r13
leaq -2048000(%rsp), %rax
.L15:
cmpq %rax, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
movq %rsp, %r14
leaq -2048000(%rsp), %rax
.L18:
cmpq %rax, %rsp
je .L19
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L18
.L19:
movq %rsp, %r12
leaq -88(%rbp), %rdi
movl $2048000, %esi
call cudaMalloc@PLT
leaq -80(%rbp), %rdi
movl $2048000, %esi
call cudaMalloc@PLT
leaq -72(%rbp), %rdi
movl $2048000, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L21:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%r14,%rbx)
movl $0, (%r12,%rbx)
addq $4, %rbx
cmpq $2048000, %rbx
jne .L21
movl $1, %ecx
movl $2048000, %edx
movq %r13, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048000, %edx
movq %r14, %rsi
movq -80(%rbp), %rdi
call cudaMemcpy@PLT
movl $512, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1000, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
movl $2, %ecx
movl $2048000, %edx
movq -72(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbx
addq $2048000, %r12
leaq .LC0(%rip), %r13
.L23:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L23
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L28:
.cfi_restore_state
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
movq -88(%rbp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "q2.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $6144128, %rsp # imm = 0x5DC080
.cfi_def_cfa_offset 6144144
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $2048000, %esi # imm = 0x1F4000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048000, %esi # imm = 0x1F4000
callq hipMalloc
movq %rsp, %rdi
movl $2048000, %esi # imm = 0x1F4000
callq hipMalloc
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 4096128(%rsp,%rbx,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 2048128(%rsp,%rbx,4)
movl $0, 128(%rsp,%rbx,4)
incq %rbx
cmpq $512000, %rbx # imm = 0x7D000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 4096128(%rsp), %rsi
movl $2048000, %edx # imm = 0x1F4000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 2048128(%rsp), %rsi
movl $2048000, %edx # imm = 0x1F4000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 488(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $2048000, %edx # imm = 0x1F4000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $512000, %rbx # imm = 0x7D000
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $6144128, %rsp # imm = 0x5DC080
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
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