system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
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You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <time.h>
#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)
__global__ void mergeSort(int *d1, int *d2, int width, int n){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int n_threads = gridDim.x * blockDim.x;
int start = tid * width;
int middle = min(start + (width >> 1), n);
int end = min(start + width, n);
// each thread may sort more than one tile (or zero tiles if start >= n)
while(start < n){
int a = start;
int b = middle;
//printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);
// merge
for (int k = start; k < end; k++) {
if (a < middle && (b >= end || d1[a] < d1[b])) {
d2[k] = d1[a];
a += 1;
} else {
d2[k] = d1[b];
b += 1;
}
}
start += n_threads * width;
middle = min(start + (width >> 1), n);
end = min(start + width, n);
}
}
int main(){
int n;
n = 100000;
int size = n * sizeof(int);
int *h_in = (int *)malloc(size);
int *h_out = (int *)malloc(size);
int *d_in, *d_out;
for (int i=0; i<n; i++){
h_in[i] = 100000 - i;
}
cudaMalloc((void **)&d_in, size);
cudaMalloc((void **)&d_out, size);
cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);
int *d1 = d_in;
int *d2 = d_out;
clock_t start_time = clock();
for (int width = 2; width < (n << 1); width <<= 1){
mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
cudaThreadSynchronize();
d1 = d1 == d_in ? d_out : d_in;
d2 = d2 == d_in ? d_out : d_in;
}
clock_t end_time = clock();
cudaMemcpy(h_out, d1, size, cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++)
printf("%d\n", h_out[i]);
printf("\n");
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
}
|
code for sm_80
Function : _Z9mergeSortPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0080*/ IADD3 R7, R0.reuse, c[0x0][0x170], RZ ; /* 0x00005c0000077a10 */
/* 0x040fe20007ffe0ff */
/*0090*/ USHF.R.S32.HI UR7, URZ, 0x1, UR5 ; /* 0x000000013f077899 */
/* 0x000fe20008011405 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*00d0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMNMX R7, R7, c[0x0][0x174], PT ; /* 0x00005d0007077a17 */
/* 0x000fe20003800200 */
/*00f0*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe2000f8e023f */
/*0100*/ IADD3 R6, R0, UR7, RZ ; /* 0x0000000700067c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc40000000a00 */
/*0120*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0130*/ IMNMX R6, R6, c[0x0][0x174], PT ; /* 0x00005d0006067a17 */
/* 0x000fe40003800200 */
/*0140*/ ISETP.GE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe20003f06270 */
/*0150*/ BSSY B1, 0xdb0 ; /* 0x00000c5000017945 */
/* 0x000fd80003800000 */
/*0160*/ @P0 BRA 0xda0 ; /* 0x00000c3000000947 */
/* 0x007fea0003800000 */
/*0170*/ UIADD3 UR5, -UR4, URZ, URZ ; /* 0x0000003f04057290 */
/* 0x000fe2000fffe13f */
/*0180*/ BSSY B0, 0x730 ; /* 0x000005a000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*01b0*/ IMAD R2, R5, UR5, -R0 ; /* 0x0000000505027c24 */
/* 0x000fe4000f8e0a00 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0004 */
/*01d0*/ IMAD.IADD R11, R2, 0x1, R7 ; /* 0x00000001020b7824 */
/* 0x000fca00078e0207 */
/*01e0*/ LOP3.LUT P0, R12, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0c7812 */
/* 0x000fda000780c0ff */
/*01f0*/ @!P0 BRA 0x720 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GE.AND P0, PT, R4, R6, PT ; /* 0x000000060400720c */
/* 0x000fe20003f06270 */
/*0210*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B2, 0x3d0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B3, 0x350 ; /* 0x0000011000037945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.S32.HI R9, RZ, 0x1f, R4 ; /* 0x0000001fff097819 */
/* 0x000fe20000011404 */
/*0250*/ IMAD.WIDE R14, R6, R13, c[0x0][0x160] ; /* 0x00005800060e7625 */
/* 0x000fc800078e020d */
/*0260*/ IMAD.WIDE R2, R4, R13, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e020d */
/*0270*/ @!P0 BRA 0x2a0 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0290*/ BRA 0x340 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*02a0*/ LEA R8, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004087a11 */
/* 0x000fc800078010ff */
/*02b0*/ LEA.HI.X R9, R4, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590004097a11 */
/* 0x000fca00000f1409 */
/*02c0*/ LDG.E R17, [R8.64] ; /* 0x0000000808117981 */
/* 0x000162000c1e1900 */
/*02d0*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fda0003f06270 */
/*02e0*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*02f0*/ @P0 BRA 0x390 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0300*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x001ea4000c1e1900 */
/*0310*/ ISETP.GE.AND P0, PT, R17, R15, PT ; /* 0x0000000f1100720c */
/* 0x024fda0003f06270 */
/*0320*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0330*/ @!P0 BRA 0x390 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0340*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0350*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0203e2000c101908 */
/*0360*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0380*/ BRA 0x3c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0211e2000c101908 */
/*03a0*/ IADD3 R9, R4, 0x1, RZ ; /* 0x0000000104097810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*03c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*03d0*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f05270 */
/*03e0*/ IADD3 R10, R4, 0x1, RZ ; /* 0x00000001040a7810 */
/* 0x000fd60007ffe0ff */
/*03f0*/ @!P0 BRA 0x720 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f06270 */
/*0410*/ BSSY B2, 0x570 ; /* 0x0000015000027945 */
/* 0x000fe20003800000 */
/*0420*/ BSSY B3, 0x510 ; /* 0x000000e000037945 */
/* 0x000fe20003800000 */
/*0430*/ IMAD.WIDE R16, R8, R13, c[0x0][0x160] ; /* 0x0000580008107625 */
/* 0x001fd400078e020d */
/*0440*/ @!P0 BRA 0x470 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R17, [R16.64] ; /* 0x0000000810117981 */
/* 0x000162000c1e1900 */
/*0460*/ BRA 0x500 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.WIDE R14, R9, R13, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x002fcc00078e020d */
/*0480*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0490*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06270 */
/*04a0*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*04b0*/ @P0 BRA 0x540 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E R17, [R16.64] ; /* 0x0000000810117981 */
/* 0x001ea4000c1e1900 */
/*04d0*/ ISETP.GE.AND P0, PT, R15, R17, PT ; /* 0x000000110f00720c */
/* 0x024fda0003f06270 */
/*04e0*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x540 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0500*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0510*/ STG.E [R2.64+0x4], R17 ; /* 0x0000041102007986 */
/* 0x0205e2000c101908 */
/*0520*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0530*/ BRA 0x560 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0540*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0211e2000c101908 */
/*0550*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0560*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.NE.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f05270 */
/*0580*/ IADD3 R10, R4, 0x2, RZ ; /* 0x00000002040a7810 */
/* 0x000fd60007ffe0ff */
/*0590*/ @!P0 BRA 0x720 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f06270 */
/*05b0*/ BSSY B2, 0x710 ; /* 0x0000015000027945 */
/* 0x000fe20003800000 */
/*05c0*/ BSSY B3, 0x6b0 ; /* 0x000000e000037945 */
/* 0x000fe20003800000 */
/*05d0*/ IMAD.WIDE R14, R8, R13, c[0x0][0x160] ; /* 0x00005800080e7625 */
/* 0x003fd400078e020d */
/*05e0*/ @!P0 BRA 0x610 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0600*/ BRA 0x6a0 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0610*/ IMAD.WIDE R12, R9, R13, c[0x0][0x160] ; /* 0x00005800090c7625 */
/* 0x000fcc00078e020d */
/*0620*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0630*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06270 */
/*0640*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*0650*/ @P0 BRA 0x6e0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x001ee4000c1e1900 */
/*0670*/ ISETP.GE.AND P0, PT, R13, R15, PT ; /* 0x0000000f0d00720c */
/* 0x028fda0003f06270 */
/*0680*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0690*/ @!P0 BRA 0x6e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*06a0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*06b0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x0203e2000c101908 */
/*06c0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ BRA 0x700 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06e0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0211e2000c101908 */
/*06f0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0700*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R10, R4, 0x3, RZ ; /* 0x00000003040a7810 */
/* 0x000fe40007ffe0ff */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R11, R11, -0x1, RZ ; /* 0xffffffff0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fda0003f06070 */
/*0750*/ @!P0 BRA 0xda0 ; /* 0x0000064000008947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x007fc800078e00ff */
/*0770*/ IMAD.WIDE R2, R10, R3, c[0x0][0x168] ; /* 0x00005a000a027625 */
/* 0x000fc800078e0203 */
/*0780*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0790*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*07a0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ BSSY B0, 0x920 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*07c0*/ BSSY B2, 0x8c0 ; /* 0x000000f000027945 */
/* 0x000fe20003800000 */
/*07d0*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x000fe200078e020b */
/*07e0*/ ISETP.GE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fce0003f06270 */
/*07f0*/ @!P1 BRA 0x820 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0810*/ BRA 0x8b0 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*0830*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0840*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*0850*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*0860*/ @P1 BRA 0x8f0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0870*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*0880*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0890*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*08a0*/ @!P1 BRA 0x8f0 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*08b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0203e2000c101908 */
/*08d0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ BRA 0x910 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0211e2000c101908 */
/*0900*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0910*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0930*/ BSSY B0, 0xa90 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0940*/ BSSY B2, 0xa30 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*0950*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x003fd400078e020b */
/*0960*/ @!P1 BRA 0x990 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0970*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0980*/ BRA 0xa20 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*09a0*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*09b0*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*09c0*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*09d0*/ @P1 BRA 0xa60 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*09f0*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0a00*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0a10*/ @!P1 BRA 0xa60 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0203e2000c101908 */
/*0a40*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ BRA 0xa80 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a60*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0211e2000c101908 */
/*0a70*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a90*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0aa0*/ BSSY B0, 0xc00 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0ab0*/ BSSY B2, 0xba0 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*0ac0*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x003fd400078e020b */
/*0ad0*/ @!P1 BRA 0xb00 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0ae0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0af0*/ BRA 0xb90 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0b00*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*0b10*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0b20*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*0b30*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*0b40*/ @P1 BRA 0xbd0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0b50*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*0b60*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0b70*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0b80*/ @!P1 BRA 0xbd0 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0b90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ba0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0203e2000c101908 */
/*0bb0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0bc0*/ BRA 0xbf0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x0211e2000c101908 */
/*0be0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0bf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0c10*/ BSSY B0, 0xd70 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0c20*/ BSSY B2, 0xd10 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*0c30*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x003fd400078e020b */
/*0c40*/ @!P1 BRA 0xc70 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0c50*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0c60*/ BRA 0xd00 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0c70*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*0c80*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0c90*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*0ca0*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*0cb0*/ @P1 BRA 0xd40 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0cc0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*0cd0*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0ce0*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0cf0*/ @!P1 BRA 0xd40 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0d00*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d10*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0203e2000c101908 */
/*0d20*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0d30*/ BRA 0xd60 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d40*/ STG.E [R2.64+0xc], R15 ; /* 0x00000c0f02007986 */
/* 0x0211e2000c101908 */
/*0d50*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0d60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d70*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x003fca0007f3e0ff */
/*0d80*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0d90*/ @!P0 BRA 0x780 ; /* 0xfffff9e000008947 */
/* 0x000fea000383ffff */
/*0da0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0db0*/ IADD3 R4, R4, UR4, RZ ; /* 0x0000000404047c10 */
/* 0x000fe4000fffe0ff */
/*0dc0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0dd0*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x040fe40003f06270 */
/*0de0*/ IADD3 R6, R4.reuse, UR7, RZ ; /* 0x0000000704067c10 */
/* 0x040fe4000fffe0ff */
/*0df0*/ IADD3 R7, R4, c[0x0][0x170], RZ ; /* 0x00005c0004077a10 */
/* 0x000fe40007ffe0ff */
/*0e00*/ IMNMX R6, R6, c[0x0][0x174], PT ; /* 0x00005d0006067a17 */
/* 0x000fc40003800200 */
/*0e10*/ IMNMX R7, R7, c[0x0][0x174], PT ; /* 0x00005d0007077a17 */
/* 0x000fca0003800200 */
/*0e20*/ @P0 CALL.REL.NOINC 0xe40 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0e30*/ BRA 0x140 ; /* 0xfffff30000007947 */
/* 0x000fea000383ffff */
/*0e40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e50*/ BRA 0xe50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <time.h>
#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)
__global__ void mergeSort(int *d1, int *d2, int width, int n){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int n_threads = gridDim.x * blockDim.x;
int start = tid * width;
int middle = min(start + (width >> 1), n);
int end = min(start + width, n);
// each thread may sort more than one tile (or zero tiles if start >= n)
while(start < n){
int a = start;
int b = middle;
//printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);
// merge
for (int k = start; k < end; k++) {
if (a < middle && (b >= end || d1[a] < d1[b])) {
d2[k] = d1[a];
a += 1;
} else {
d2[k] = d1[b];
b += 1;
}
}
start += n_threads * width;
middle = min(start + (width >> 1), n);
end = min(start + width, n);
}
}
int main(){
int n;
n = 100000;
int size = n * sizeof(int);
int *h_in = (int *)malloc(size);
int *h_out = (int *)malloc(size);
int *d_in, *d_out;
for (int i=0; i<n; i++){
h_in[i] = 100000 - i;
}
cudaMalloc((void **)&d_in, size);
cudaMalloc((void **)&d_out, size);
cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);
int *d1 = d_in;
int *d2 = d_out;
clock_t start_time = clock();
for (int width = 2; width < (n << 1); width <<= 1){
mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
cudaThreadSynchronize();
d1 = d1 == d_in ? d_out : d_in;
d2 = d2 == d_in ? d_out : d_in;
}
clock_t end_time = clock();
cudaMemcpy(h_out, d1, size, cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++)
printf("%d\n", h_out[i]);
printf("\n");
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
}
|
.file "tmpxft_000427d9_00000000-6_merge_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
.type _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii, @function
_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mergeSortPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii, .-_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
.globl _Z9mergeSortPiS_ii
.type _Z9mergeSortPiS_ii, @function
_Z9mergeSortPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9mergeSortPiS_ii, .-_Z9mergeSortPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.LC1:
.string "\n"
.LC3:
.string "total time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdx
movl $100000, %eax
.L12:
movl %eax, (%rdx)
addq $4, %rdx
subl $1, %eax
jne .L12
movq %rsp, %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %r12
movq 8(%rsp), %r15
call clock@PLT
movq %rax, %r13
movl $17, %ebx
movl $2, %r14d
jmp .L16
.L13:
call cudaThreadSynchronize@PLT
movq (%rsp), %rax
cmpq %r12, %rax
je .L25
movq %rax, %r12
.L14:
cmpq %r15, %rax
je .L26
movq %rax, %r15
.L15:
addl %r14d, %r14d
subl $1, %ebx
je .L27
.L16:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $8, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $100000, %ecx
movl %r14d, %edx
movq %r15, %rsi
movq %r12, %rdi
call _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
jmp .L13
.L25:
movq 8(%rsp), %r12
jmp .L14
.L26:
movq 8(%rsp), %r15
jmp .L15
.L27:
call clock@PLT
movq %rax, %r14
movl $2, %ecx
movl $400000, %edx
movq %r12, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $400000, %rbp
leaq .LC0(%rip), %r12
.L17:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq %r13, %r14
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9mergeSortPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mergeSortPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <time.h>
#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)
__global__ void mergeSort(int *d1, int *d2, int width, int n){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int n_threads = gridDim.x * blockDim.x;
int start = tid * width;
int middle = min(start + (width >> 1), n);
int end = min(start + width, n);
// each thread may sort more than one tile (or zero tiles if start >= n)
while(start < n){
int a = start;
int b = middle;
//printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);
// merge
for (int k = start; k < end; k++) {
if (a < middle && (b >= end || d1[a] < d1[b])) {
d2[k] = d1[a];
a += 1;
} else {
d2[k] = d1[b];
b += 1;
}
}
start += n_threads * width;
middle = min(start + (width >> 1), n);
end = min(start + width, n);
}
}
int main(){
int n;
n = 100000;
int size = n * sizeof(int);
int *h_in = (int *)malloc(size);
int *h_out = (int *)malloc(size);
int *d_in, *d_out;
for (int i=0; i<n; i++){
h_in[i] = 100000 - i;
}
cudaMalloc((void **)&d_in, size);
cudaMalloc((void **)&d_out, size);
cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);
int *d1 = d_in;
int *d2 = d_out;
clock_t start_time = clock();
for (int width = 2; width < (n << 1); width <<= 1){
mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
cudaThreadSynchronize();
d1 = d1 == d_in ? d_out : d_in;
d2 = d2 == d_in ? d_out : d_in;
}
clock_t end_time = clock();
cudaMemcpy(h_out, d1, size, cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++)
printf("%d\n", h_out[i]);
printf("\n");
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)
__global__ void mergeSort(int *d1, int *d2, int width, int n){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int n_threads = gridDim.x * blockDim.x;
int start = tid * width;
int middle = min(start + (width >> 1), n);
int end = min(start + width, n);
// each thread may sort more than one tile (or zero tiles if start >= n)
while(start < n){
int a = start;
int b = middle;
//printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);
// merge
for (int k = start; k < end; k++) {
if (a < middle && (b >= end || d1[a] < d1[b])) {
d2[k] = d1[a];
a += 1;
} else {
d2[k] = d1[b];
b += 1;
}
}
start += n_threads * width;
middle = min(start + (width >> 1), n);
end = min(start + width, n);
}
}
int main(){
int n;
n = 100000;
int size = n * sizeof(int);
int *h_in = (int *)malloc(size);
int *h_out = (int *)malloc(size);
int *d_in, *d_out;
for (int i=0; i<n; i++){
h_in[i] = 100000 - i;
}
hipMalloc((void **)&d_in, size);
hipMalloc((void **)&d_out, size);
hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);
int *d1 = d_in;
int *d2 = d_out;
clock_t start_time = clock();
for (int width = 2; width < (n << 1); width <<= 1){
mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
hipDeviceSynchronize();
d1 = d1 == d_in ? d_out : d_in;
d2 = d2 == d_in ? d_out : d_in;
}
clock_t end_time = clock();
hipMemcpy(h_out, d1, size, hipMemcpyDeviceToHost);
for(int i=0; i<n; i++)
printf("%d\n", h_out[i]);
printf("\n");
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)
__global__ void mergeSort(int *d1, int *d2, int width, int n){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int n_threads = gridDim.x * blockDim.x;
int start = tid * width;
int middle = min(start + (width >> 1), n);
int end = min(start + width, n);
// each thread may sort more than one tile (or zero tiles if start >= n)
while(start < n){
int a = start;
int b = middle;
//printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);
// merge
for (int k = start; k < end; k++) {
if (a < middle && (b >= end || d1[a] < d1[b])) {
d2[k] = d1[a];
a += 1;
} else {
d2[k] = d1[b];
b += 1;
}
}
start += n_threads * width;
middle = min(start + (width >> 1), n);
end = min(start + width, n);
}
}
int main(){
int n;
n = 100000;
int size = n * sizeof(int);
int *h_in = (int *)malloc(size);
int *h_out = (int *)malloc(size);
int *d_in, *d_out;
for (int i=0; i<n; i++){
h_in[i] = 100000 - i;
}
hipMalloc((void **)&d_in, size);
hipMalloc((void **)&d_out, size);
hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);
int *d1 = d_in;
int *d2 = d_out;
clock_t start_time = clock();
for (int width = 2; width < (n << 1); width <<= 1){
mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
hipDeviceSynchronize();
d1 = d1 == d_in ? d_out : d_in;
d2 = d2 == d_in ? d_out : d_in;
}
clock_t end_time = clock();
hipMemcpy(h_out, d1, size, hipMemcpyDeviceToHost);
for(int i=0; i<n; i++)
printf("%d\n", h_out[i]);
printf("\n");
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mergeSortPiS_ii
.globl _Z9mergeSortPiS_ii
.p2align 8
.type _Z9mergeSortPiS_ii,@function
_Z9mergeSortPiS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s2
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_14
s_load_b32 s9, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_ashr_i32 s1, s2, 1
v_add_nc_u32_e32 v3, s2, v0
v_add_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_min_i32_e32 v9, s3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, s3, v4
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s9, s2
v_add_co_u32 v1, vcc_lo, s6, v1
s_mul_i32 s8, s0, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[8:9], 2
s_mov_b32 s9, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v0, s8, v0
v_add_co_u32 v1, s0, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
v_add_nc_u32_e32 v3, s1, v0
v_add_nc_u32_e32 v4, s2, v0
v_cmp_le_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, s3, v3
v_min_i32_e32 v9, s3, v4
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_14
.LBB0_3:
s_mov_b32 s10, exec_lo
v_cmpx_lt_i32_e64 v0, v9
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_mov_b32_e32 v11, v0
v_mov_b32_e32 v7, v10
v_mov_b32_e32 v5, v0
s_mov_b32 s11, 0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v11, 1, v11
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_ge_i32_e32 vcc_lo, v11, v9
v_mov_b32_e32 v7, v6
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_2
.LBB0_6:
s_mov_b32 s13, -1
s_mov_b32 s12, 0
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e64 v5, v10
s_cbranch_execz .LBB0_10
v_cmp_ge_i32_e64 s12, v7, v9
s_mov_b32 s14, 0
s_mov_b32 s13, exec_lo
v_cmpx_lt_i32_e64 v7, v9
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_or_b32 s12, s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[5:6]
v_lshlrev_b64 v[14:15], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
s_clause 0x1
global_load_b32 v6, v[12:13], off
global_load_b32 v8, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v6, v8
s_and_b32 s14, vcc_lo, exec_lo
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s12, s12, exec_lo
s_or_not1_b32 s13, s14, exec_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v6, 1, v7
s_and_not1_b32 s12, s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v8, v[12:13], off
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v8, off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s12
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[5:6]
v_dual_mov_b32 v6, v7 :: v_dual_add_nc_u32 v5, 1, v5
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v8, v[12:13], off
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v8, off
s_branch .LBB0_5
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mergeSortPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mergeSortPiS_ii, .Lfunc_end0-_Z9mergeSortPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mergeSortPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mergeSortPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)
__global__ void mergeSort(int *d1, int *d2, int width, int n){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int n_threads = gridDim.x * blockDim.x;
int start = tid * width;
int middle = min(start + (width >> 1), n);
int end = min(start + width, n);
// each thread may sort more than one tile (or zero tiles if start >= n)
while(start < n){
int a = start;
int b = middle;
//printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);
// merge
for (int k = start; k < end; k++) {
if (a < middle && (b >= end || d1[a] < d1[b])) {
d2[k] = d1[a];
a += 1;
} else {
d2[k] = d1[b];
b += 1;
}
}
start += n_threads * width;
middle = min(start + (width >> 1), n);
end = min(start + width, n);
}
}
int main(){
int n;
n = 100000;
int size = n * sizeof(int);
int *h_in = (int *)malloc(size);
int *h_out = (int *)malloc(size);
int *d_in, *d_out;
for (int i=0; i<n; i++){
h_in[i] = 100000 - i;
}
hipMalloc((void **)&d_in, size);
hipMalloc((void **)&d_out, size);
hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);
int *d1 = d_in;
int *d2 = d_out;
clock_t start_time = clock();
for (int width = 2; width < (n << 1); width <<= 1){
mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
hipDeviceSynchronize();
d1 = d1 == d_in ? d_out : d_in;
d2 = d2 == d_in ? d_out : d_in;
}
clock_t end_time = clock();
hipMemcpy(h_out, d1, size, hipMemcpyDeviceToHost);
for(int i=0; i<n; i++)
printf("%d\n", h_out[i]);
printf("\n");
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
}
|
.text
.file "merge_sort.hip"
.globl _Z24__device_stub__mergeSortPiS_ii # -- Begin function _Z24__device_stub__mergeSortPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__mergeSortPiS_ii,@function
_Z24__device_stub__mergeSortPiS_ii: # @_Z24__device_stub__mergeSortPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mergeSortPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__mergeSortPiS_ii, .Lfunc_end0-_Z24__device_stub__mergeSortPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $100000, %eax # imm = 0x186A0
movq %r14, %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx)
addq $4, %rcx
decq %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967304, %r15 # imm = 0x100000008
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq (%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %r12
movq 16(%rsp), %rbp
movl $2, %r14d
callq clock
movq %rax, 24(%rsp) # 8-byte Spill
leaq 24(%r15), %r13
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
callq hipDeviceSynchronize
movq (%rsp), %rax
cmpq %rax, %r12
movq 16(%rsp), %rcx
movq %rax, %r12
cmoveq %rcx, %r12
cmpq %rax, %rbp
cmoveq %rcx, %rax
addl %r14d, %r14d
movq %rax, %rbp
cmpl $200000, %r14d # imm = 0x30D40
jge .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq %r12, 88(%rsp)
movq %rbp, 80(%rsp)
movl %r14d, 12(%rsp)
movl $100000, 8(%rsp) # imm = 0x186A0
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z9mergeSortPiS_ii, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq clock
movq %rax, %r14
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rdi
movq %r12, %rsi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $100000, %r15 # imm = 0x186A0
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
subq 24(%rsp), %r14 # 8-byte Folded Reload
cvtsi2sd %r14, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mergeSortPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mergeSortPiS_ii,@object # @_Z9mergeSortPiS_ii
.section .rodata,"a",@progbits
.globl _Z9mergeSortPiS_ii
.p2align 3, 0x0
_Z9mergeSortPiS_ii:
.quad _Z24__device_stub__mergeSortPiS_ii
.size _Z9mergeSortPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "total time: %f\n"
.size .L.str.2, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mergeSortPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mergeSortPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mergeSortPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9mergeSortPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0080*/ IADD3 R7, R0.reuse, c[0x0][0x170], RZ ; /* 0x00005c0000077a10 */
/* 0x040fe20007ffe0ff */
/*0090*/ USHF.R.S32.HI UR7, URZ, 0x1, UR5 ; /* 0x000000013f077899 */
/* 0x000fe20008011405 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*00d0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMNMX R7, R7, c[0x0][0x174], PT ; /* 0x00005d0007077a17 */
/* 0x000fe20003800200 */
/*00f0*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe2000f8e023f */
/*0100*/ IADD3 R6, R0, UR7, RZ ; /* 0x0000000700067c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc40000000a00 */
/*0120*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0130*/ IMNMX R6, R6, c[0x0][0x174], PT ; /* 0x00005d0006067a17 */
/* 0x000fe40003800200 */
/*0140*/ ISETP.GE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe20003f06270 */
/*0150*/ BSSY B1, 0xdb0 ; /* 0x00000c5000017945 */
/* 0x000fd80003800000 */
/*0160*/ @P0 BRA 0xda0 ; /* 0x00000c3000000947 */
/* 0x007fea0003800000 */
/*0170*/ UIADD3 UR5, -UR4, URZ, URZ ; /* 0x0000003f04057290 */
/* 0x000fe2000fffe13f */
/*0180*/ BSSY B0, 0x730 ; /* 0x000005a000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*01b0*/ IMAD R2, R5, UR5, -R0 ; /* 0x0000000505027c24 */
/* 0x000fe4000f8e0a00 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0004 */
/*01d0*/ IMAD.IADD R11, R2, 0x1, R7 ; /* 0x00000001020b7824 */
/* 0x000fca00078e0207 */
/*01e0*/ LOP3.LUT P0, R12, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0c7812 */
/* 0x000fda000780c0ff */
/*01f0*/ @!P0 BRA 0x720 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GE.AND P0, PT, R4, R6, PT ; /* 0x000000060400720c */
/* 0x000fe20003f06270 */
/*0210*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B2, 0x3d0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B3, 0x350 ; /* 0x0000011000037945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.S32.HI R9, RZ, 0x1f, R4 ; /* 0x0000001fff097819 */
/* 0x000fe20000011404 */
/*0250*/ IMAD.WIDE R14, R6, R13, c[0x0][0x160] ; /* 0x00005800060e7625 */
/* 0x000fc800078e020d */
/*0260*/ IMAD.WIDE R2, R4, R13, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e020d */
/*0270*/ @!P0 BRA 0x2a0 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0290*/ BRA 0x340 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*02a0*/ LEA R8, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004087a11 */
/* 0x000fc800078010ff */
/*02b0*/ LEA.HI.X R9, R4, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590004097a11 */
/* 0x000fca00000f1409 */
/*02c0*/ LDG.E R17, [R8.64] ; /* 0x0000000808117981 */
/* 0x000162000c1e1900 */
/*02d0*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fda0003f06270 */
/*02e0*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*02f0*/ @P0 BRA 0x390 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0300*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x001ea4000c1e1900 */
/*0310*/ ISETP.GE.AND P0, PT, R17, R15, PT ; /* 0x0000000f1100720c */
/* 0x024fda0003f06270 */
/*0320*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0330*/ @!P0 BRA 0x390 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0340*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0350*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0203e2000c101908 */
/*0360*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0380*/ BRA 0x3c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0211e2000c101908 */
/*03a0*/ IADD3 R9, R4, 0x1, RZ ; /* 0x0000000104097810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*03c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*03d0*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f05270 */
/*03e0*/ IADD3 R10, R4, 0x1, RZ ; /* 0x00000001040a7810 */
/* 0x000fd60007ffe0ff */
/*03f0*/ @!P0 BRA 0x720 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f06270 */
/*0410*/ BSSY B2, 0x570 ; /* 0x0000015000027945 */
/* 0x000fe20003800000 */
/*0420*/ BSSY B3, 0x510 ; /* 0x000000e000037945 */
/* 0x000fe20003800000 */
/*0430*/ IMAD.WIDE R16, R8, R13, c[0x0][0x160] ; /* 0x0000580008107625 */
/* 0x001fd400078e020d */
/*0440*/ @!P0 BRA 0x470 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R17, [R16.64] ; /* 0x0000000810117981 */
/* 0x000162000c1e1900 */
/*0460*/ BRA 0x500 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.WIDE R14, R9, R13, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x002fcc00078e020d */
/*0480*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0490*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06270 */
/*04a0*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*04b0*/ @P0 BRA 0x540 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E R17, [R16.64] ; /* 0x0000000810117981 */
/* 0x001ea4000c1e1900 */
/*04d0*/ ISETP.GE.AND P0, PT, R15, R17, PT ; /* 0x000000110f00720c */
/* 0x024fda0003f06270 */
/*04e0*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x540 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0500*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0510*/ STG.E [R2.64+0x4], R17 ; /* 0x0000041102007986 */
/* 0x0205e2000c101908 */
/*0520*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0530*/ BRA 0x560 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0540*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0211e2000c101908 */
/*0550*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0560*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.NE.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f05270 */
/*0580*/ IADD3 R10, R4, 0x2, RZ ; /* 0x00000002040a7810 */
/* 0x000fd60007ffe0ff */
/*0590*/ @!P0 BRA 0x720 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f06270 */
/*05b0*/ BSSY B2, 0x710 ; /* 0x0000015000027945 */
/* 0x000fe20003800000 */
/*05c0*/ BSSY B3, 0x6b0 ; /* 0x000000e000037945 */
/* 0x000fe20003800000 */
/*05d0*/ IMAD.WIDE R14, R8, R13, c[0x0][0x160] ; /* 0x00005800080e7625 */
/* 0x003fd400078e020d */
/*05e0*/ @!P0 BRA 0x610 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0600*/ BRA 0x6a0 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0610*/ IMAD.WIDE R12, R9, R13, c[0x0][0x160] ; /* 0x00005800090c7625 */
/* 0x000fcc00078e020d */
/*0620*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0630*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06270 */
/*0640*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*0650*/ @P0 BRA 0x6e0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x001ee4000c1e1900 */
/*0670*/ ISETP.GE.AND P0, PT, R13, R15, PT ; /* 0x0000000f0d00720c */
/* 0x028fda0003f06270 */
/*0680*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0690*/ @!P0 BRA 0x6e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*06a0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*06b0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x0203e2000c101908 */
/*06c0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ BRA 0x700 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06e0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0211e2000c101908 */
/*06f0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0700*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R10, R4, 0x3, RZ ; /* 0x00000003040a7810 */
/* 0x000fe40007ffe0ff */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R11, R11, -0x1, RZ ; /* 0xffffffff0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fda0003f06070 */
/*0750*/ @!P0 BRA 0xda0 ; /* 0x0000064000008947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x007fc800078e00ff */
/*0770*/ IMAD.WIDE R2, R10, R3, c[0x0][0x168] ; /* 0x00005a000a027625 */
/* 0x000fc800078e0203 */
/*0780*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0790*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*07a0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ BSSY B0, 0x920 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*07c0*/ BSSY B2, 0x8c0 ; /* 0x000000f000027945 */
/* 0x000fe20003800000 */
/*07d0*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x000fe200078e020b */
/*07e0*/ ISETP.GE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fce0003f06270 */
/*07f0*/ @!P1 BRA 0x820 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0810*/ BRA 0x8b0 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*0830*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0840*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*0850*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*0860*/ @P1 BRA 0x8f0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0870*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*0880*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0890*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*08a0*/ @!P1 BRA 0x8f0 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*08b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0203e2000c101908 */
/*08d0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ BRA 0x910 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0211e2000c101908 */
/*0900*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0910*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0930*/ BSSY B0, 0xa90 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0940*/ BSSY B2, 0xa30 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*0950*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x003fd400078e020b */
/*0960*/ @!P1 BRA 0x990 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0970*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0980*/ BRA 0xa20 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*09a0*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*09b0*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*09c0*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*09d0*/ @P1 BRA 0xa60 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*09f0*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0a00*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0a10*/ @!P1 BRA 0xa60 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0203e2000c101908 */
/*0a40*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ BRA 0xa80 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a60*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0211e2000c101908 */
/*0a70*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a90*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0aa0*/ BSSY B0, 0xc00 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0ab0*/ BSSY B2, 0xba0 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*0ac0*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x003fd400078e020b */
/*0ad0*/ @!P1 BRA 0xb00 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0ae0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0af0*/ BRA 0xb90 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0b00*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*0b10*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0b20*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*0b30*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*0b40*/ @P1 BRA 0xbd0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0b50*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*0b60*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0b70*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0b80*/ @!P1 BRA 0xbd0 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0b90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ba0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0203e2000c101908 */
/*0bb0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0bc0*/ BRA 0xbf0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x0211e2000c101908 */
/*0be0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0bf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.GE.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f26270 */
/*0c10*/ BSSY B0, 0xd70 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0c20*/ BSSY B2, 0xd10 ; /* 0x000000e000027945 */
/* 0x000fe20003800000 */
/*0c30*/ IMAD.WIDE R12, R8, R11, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x003fd400078e020b */
/*0c40*/ @!P1 BRA 0xc70 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0c50*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000162000c1e1900 */
/*0c60*/ BRA 0xd00 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*0c70*/ IMAD.WIDE R14, R9, R11, c[0x0][0x160] ; /* 0x00005800090e7625 */
/* 0x000fcc00078e020b */
/*0c80*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000162000c1e1900 */
/*0c90*/ ISETP.GE.AND P1, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f26270 */
/*0ca0*/ @P1 BREAK B2 ; /* 0x0000000000021942 */
/* 0x000fe20003800000 */
/*0cb0*/ @P1 BRA 0xd40 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0cc0*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x001ea4000c1e1900 */
/*0cd0*/ ISETP.GE.AND P1, PT, R15, R13, PT ; /* 0x0000000d0f00720c */
/* 0x024fda0003f26270 */
/*0ce0*/ @!P1 BREAK B2 ; /* 0x0000000000029942 */
/* 0x000fe20003800000 */
/*0cf0*/ @!P1 BRA 0xd40 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0d00*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d10*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0203e2000c101908 */
/*0d20*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0d30*/ BRA 0xd60 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d40*/ STG.E [R2.64+0xc], R15 ; /* 0x00000c0f02007986 */
/* 0x0211e2000c101908 */
/*0d50*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*0d60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d70*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x003fca0007f3e0ff */
/*0d80*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0d90*/ @!P0 BRA 0x780 ; /* 0xfffff9e000008947 */
/* 0x000fea000383ffff */
/*0da0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0db0*/ IADD3 R4, R4, UR4, RZ ; /* 0x0000000404047c10 */
/* 0x000fe4000fffe0ff */
/*0dc0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0dd0*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x040fe40003f06270 */
/*0de0*/ IADD3 R6, R4.reuse, UR7, RZ ; /* 0x0000000704067c10 */
/* 0x040fe4000fffe0ff */
/*0df0*/ IADD3 R7, R4, c[0x0][0x170], RZ ; /* 0x00005c0004077a10 */
/* 0x000fe40007ffe0ff */
/*0e00*/ IMNMX R6, R6, c[0x0][0x174], PT ; /* 0x00005d0006067a17 */
/* 0x000fc40003800200 */
/*0e10*/ IMNMX R7, R7, c[0x0][0x174], PT ; /* 0x00005d0007077a17 */
/* 0x000fca0003800200 */
/*0e20*/ @P0 CALL.REL.NOINC 0xe40 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0e30*/ BRA 0x140 ; /* 0xfffff30000007947 */
/* 0x000fea000383ffff */
/*0e40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e50*/ BRA 0xe50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mergeSortPiS_ii
.globl _Z9mergeSortPiS_ii
.p2align 8
.type _Z9mergeSortPiS_ii,@function
_Z9mergeSortPiS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s2
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_14
s_load_b32 s9, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_ashr_i32 s1, s2, 1
v_add_nc_u32_e32 v3, s2, v0
v_add_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_min_i32_e32 v9, s3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, s3, v4
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s9, s2
v_add_co_u32 v1, vcc_lo, s6, v1
s_mul_i32 s8, s0, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[8:9], 2
s_mov_b32 s9, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v0, s8, v0
v_add_co_u32 v1, s0, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
v_add_nc_u32_e32 v3, s1, v0
v_add_nc_u32_e32 v4, s2, v0
v_cmp_le_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, s3, v3
v_min_i32_e32 v9, s3, v4
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_14
.LBB0_3:
s_mov_b32 s10, exec_lo
v_cmpx_lt_i32_e64 v0, v9
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_mov_b32_e32 v11, v0
v_mov_b32_e32 v7, v10
v_mov_b32_e32 v5, v0
s_mov_b32 s11, 0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v11, 1, v11
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_ge_i32_e32 vcc_lo, v11, v9
v_mov_b32_e32 v7, v6
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_2
.LBB0_6:
s_mov_b32 s13, -1
s_mov_b32 s12, 0
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e64 v5, v10
s_cbranch_execz .LBB0_10
v_cmp_ge_i32_e64 s12, v7, v9
s_mov_b32 s14, 0
s_mov_b32 s13, exec_lo
v_cmpx_lt_i32_e64 v7, v9
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_or_b32 s12, s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[5:6]
v_lshlrev_b64 v[14:15], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
s_clause 0x1
global_load_b32 v6, v[12:13], off
global_load_b32 v8, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v6, v8
s_and_b32 s14, vcc_lo, exec_lo
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s12, s12, exec_lo
s_or_not1_b32 s13, s14, exec_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v6, 1, v7
s_and_not1_b32 s12, s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v8, v[12:13], off
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v8, off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s12
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[5:6]
v_dual_mov_b32 v6, v7 :: v_dual_add_nc_u32 v5, 1, v5
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v8, v[12:13], off
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v8, off
s_branch .LBB0_5
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mergeSortPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mergeSortPiS_ii, .Lfunc_end0-_Z9mergeSortPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mergeSortPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mergeSortPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000427d9_00000000-6_merge_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
.type _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii, @function
_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mergeSortPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii, .-_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
.globl _Z9mergeSortPiS_ii
.type _Z9mergeSortPiS_ii, @function
_Z9mergeSortPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9mergeSortPiS_ii, .-_Z9mergeSortPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.LC1:
.string "\n"
.LC3:
.string "total time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdx
movl $100000, %eax
.L12:
movl %eax, (%rdx)
addq $4, %rdx
subl $1, %eax
jne .L12
movq %rsp, %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %r12
movq 8(%rsp), %r15
call clock@PLT
movq %rax, %r13
movl $17, %ebx
movl $2, %r14d
jmp .L16
.L13:
call cudaThreadSynchronize@PLT
movq (%rsp), %rax
cmpq %r12, %rax
je .L25
movq %rax, %r12
.L14:
cmpq %r15, %rax
je .L26
movq %rax, %r15
.L15:
addl %r14d, %r14d
subl $1, %ebx
je .L27
.L16:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $8, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $100000, %ecx
movl %r14d, %edx
movq %r15, %rsi
movq %r12, %rdi
call _Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
jmp .L13
.L25:
movq 8(%rsp), %r12
jmp .L14
.L26:
movq 8(%rsp), %r15
jmp .L15
.L27:
call clock@PLT
movq %rax, %r14
movl $2, %ecx
movl $400000, %edx
movq %r12, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $400000, %rbp
leaq .LC0(%rip), %r12
.L17:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq %r13, %r14
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9mergeSortPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mergeSortPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "merge_sort.hip"
.globl _Z24__device_stub__mergeSortPiS_ii # -- Begin function _Z24__device_stub__mergeSortPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__mergeSortPiS_ii,@function
_Z24__device_stub__mergeSortPiS_ii: # @_Z24__device_stub__mergeSortPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mergeSortPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__mergeSortPiS_ii, .Lfunc_end0-_Z24__device_stub__mergeSortPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $100000, %eax # imm = 0x186A0
movq %r14, %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx)
addq $4, %rcx
decq %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967304, %r15 # imm = 0x100000008
movq %rsp, %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq (%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %r12
movq 16(%rsp), %rbp
movl $2, %r14d
callq clock
movq %rax, 24(%rsp) # 8-byte Spill
leaq 24(%r15), %r13
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
callq hipDeviceSynchronize
movq (%rsp), %rax
cmpq %rax, %r12
movq 16(%rsp), %rcx
movq %rax, %r12
cmoveq %rcx, %r12
cmpq %rax, %rbp
cmoveq %rcx, %rax
addl %r14d, %r14d
movq %rax, %rbp
cmpl $200000, %r14d # imm = 0x30D40
jge .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq %r12, 88(%rsp)
movq %rbp, 80(%rsp)
movl %r14d, 12(%rsp)
movl $100000, 8(%rsp) # imm = 0x186A0
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z9mergeSortPiS_ii, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq clock
movq %rax, %r14
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rdi
movq %r12, %rsi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $100000, %r15 # imm = 0x186A0
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
subq 24(%rsp), %r14 # 8-byte Folded Reload
cvtsi2sd %r14, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mergeSortPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mergeSortPiS_ii,@object # @_Z9mergeSortPiS_ii
.section .rodata,"a",@progbits
.globl _Z9mergeSortPiS_ii
.p2align 3, 0x0
_Z9mergeSortPiS_ii:
.quad _Z24__device_stub__mergeSortPiS_ii
.size _Z9mergeSortPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "total time: %f\n"
.size .L.str.2, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mergeSortPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mergeSortPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mergeSortPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <cuda_runtime.h>
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
bool initCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0){
std::cout<<"There is no device."<<std::endl;
return false;
}
int i;
for(i=0;i<count;i++){
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop,i)==cudaSuccess){
if(prop.major>=1) break;
}
}
if(i==count){
std::cout<<"There is no device supporting CUDA 1.x/n"<<std::endl;
return false;
}
cudaSetDevice(i);
return true;
}
void generateNumbers(int* number, int size)
{
for(int i=0;i<size;i++){
number[i] = rand() % 10;
}
}
__global__
static void sumOfSquares(int* num, int* result, clock_t* time)
{
extern __shared__ int shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
int offset = 1, mask = 1;
//const int size = DATA_SIZE/THREAD_NUM;
if(tid == 0) time[bid] = clock();
shared[tid] = 0;
for(int i=bid*THREAD_NUM+tid;i<DATA_SIZE;i+=THREAD_NUM*BLOCK_NUM){
shared[tid] += num[i]*num[i];
}
__syncthreads();
while(offset<THREAD_NUM){
if((tid & mask) == 0){
shared[tid] += shared[tid+offset];
}
offset += offset;
mask = offset+mask;
__syncthreads();
}
if(tid == 0){
time[bid+BLOCK_NUM] = clock();
result[bid] = shared[0];
}
}
int sumOfSquared(int* data){
int sum = 0;
for(int i=0;i<DATA_SIZE;i++){
sum += data[i]*data[i];
}
return sum;
}
int main()
{
if(!initCUDA()) return 0;
std::cout<<"CUDA initialized"<<std::endl;
int data[DATA_SIZE];
generateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
cudaMalloc((void**)&gpudata, sizeof(int)*DATA_SIZE);
cudaMalloc((void**)&result, sizeof(int)*BLOCK_NUM);
cudaMalloc((void**)&time, sizeof(clock_t)*BLOCK_NUM*2);
cudaMemcpy(gpudata, data, sizeof(int)*DATA_SIZE, cudaMemcpyHostToDevice);
sumOfSquares<<<BLOCK_NUM,THREAD_NUM,THREAD_NUM*sizeof(int)>>>(gpudata, result, time);
int sum[THREAD_NUM*BLOCK_NUM];
clock_t time_used[BLOCK_NUM*2];
cudaMemcpy(sum, result, sizeof(int)*BLOCK_NUM, cudaMemcpyDeviceToHost);
cudaMemcpy(&time_used, time, sizeof(clock_t)*BLOCK_NUM*2, cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
cudaFree(time);
int final_sum = 0;
for(int i=0;i<BLOCK_NUM;i++){
final_sum += sum[i];
}
clock_t timeUsed;
for(int i=0;i<BLOCK_NUM;i++){
timeUsed += (time_used[i+BLOCK_NUM]-time_used[i]);
}
std::cout<<"sum (GPU): "<<final_sum<<"; time:"<<timeUsed<<std::endl;
clock_t start = clock();
int sumCpu = sumOfSquared(data);
clock_t usedTime = clock() - start;
std::cout<<"sum (CPU): "<<sumCpu<<"; time:"<<usedTime<<std::endl;
return 0;
}
|
code for sm_80
Function : _Z12sumOfSquaresPiS_Pl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fcc0003f25270 */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x002fce00078e0203 */
/*0070*/ @!P1 CS2R R4, SR_CLOCKLO ; /* 0x0000000000049805 */
/* 0x000fca0000015000 */
/*0080*/ @!P1 STG.E.64 [R2.64], R4 ; /* 0x0000000402009986 */
/* 0x0001e2000c101b04 */
/*0090*/ IMAD R6, R0, 0x100, R7 ; /* 0x0000010000067824 */
/* 0x000fe200078e0207 */
/*00a0*/ BSSY B0, 0x810 ; /* 0x0000076000007945 */
/* 0x000fe40003800000 */
/*00b0*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0001e40000004800 */
/*00c0*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x000fda0003f04270 */
/*00d0*/ @P0 BRA 0x800 ; /* 0x0000072000000947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x001fe20000000f00 */
/*00f0*/ BSSY B1, 0x260 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0110*/ IMNMX R4, R8, 0xfe000, !PT ; /* 0x000fe00008047817 */
/* 0x000fc80007800200 */
/*0120*/ IADD3 R5, -R7, 0x1fff, R4 ; /* 0x00001fff07057810 */
/* 0x000fca0007ffe104 */
/*0130*/ IMAD R5, R0, -0x100, R5 ; /* 0xffffff0000057824 */
/* 0x000fca00078e0205 */
/*0140*/ LEA.HI R4, R5.reuse, 0x1, RZ, 0x13 ; /* 0x0000000105047811 */
/* 0x040fe400078f98ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R5, 0x6000, PT ; /* 0x000060000500780c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT P2, R9, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304097812 */
/* 0x000fda000784c0ff */
/*0170*/ @!P2 BRA 0x250 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0180*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0190*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*01a0*/ IMAD.WIDE R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0205 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0005 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e000b */
/*01d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*01e0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R8, R8, 0x2000, RZ ; /* 0x0000200008087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0210*/ IADD3 R4, P3, R4, 0x8000, RZ ; /* 0x0000800004047810 */
/* 0x001fc80007f7e0ff */
/*0220*/ IADD3.X R11, RZ, R11, RZ, P3, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20001ffe4ff */
/*0230*/ IMAD R6, R5, R5, R6 ; /* 0x0000000505067224 */
/* 0x004fcc00078e0206 */
/*0240*/ @P2 BRA 0x1c0 ; /* 0xffffff7000002947 */
/* 0x000fea000383ffff */
/*0250*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0260*/ BSSY B1, 0x7f0 ; /* 0x0000058000017945 */
/* 0x000fe20003800000 */
/*0270*/ @!P0 BRA 0x7e0 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R18, R8.reuse, -0x8000, RZ ; /* 0xffff800008127810 */
/* 0x040fe20007ffe0ff */
/*02a0*/ BSSY B2, 0x590 ; /* 0x000002e000027945 */
/* 0x000fe40003800000 */
/*02b0*/ IMAD.WIDE R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe200078e0205 */
/*02c0*/ IADD3 R8, -R18, 0xf8000, RZ ; /* 0x000f800012087810 */
/* 0x000fc80007ffe1ff */
/*02d0*/ ISETP.GT.AND P2, PT, R8, 0x18000, PT ; /* 0x000180000800780c */
/* 0x000fe40003f44270 */
/*02e0*/ IADD3 R4, P0, R4, 0x10000, RZ ; /* 0x0001000004047810 */
/* 0x000fc80007f1e0ff */
/*02f0*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x000fe400007fe4ff */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0f070 */
/*0310*/ @!P2 BRA 0x580 ; /* 0x000002600000a947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*0330*/ LDG.E R19, [R4.64+-0x10000] ; /* 0xff00000404137981 */
/* 0x0000a8000c1e1900 */
/*0340*/ LDG.E R21, [R4.64+-0x8000] ; /* 0xff80000404157981 */
/* 0x0000e8000c1e1900 */
/*0350*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000128000c1e1900 */
/*0360*/ LDG.E R25, [R4.64+0x8000] ; /* 0x0080000404197981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R27, [R4.64+0x10000] ; /* 0x01000004041b7981 */
/* 0x000168000c1e1900 */
/*0380*/ LDG.E R29, [R4.64+0x18000] ; /* 0x01800004041d7981 */
/* 0x000168000c1e1900 */
/*0390*/ LDG.E R17, [R4.64+0x20000] ; /* 0x0200000404117981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R16, [R4.64+0x28000] ; /* 0x0280000404107981 */
/* 0x000168000c1e1900 */
/*03b0*/ LDG.E R15, [R4.64+0x30000] ; /* 0x03000004040f7981 */
/* 0x000168000c1e1900 */
/*03c0*/ LDG.E R14, [R4.64+0x38000] ; /* 0x03800004040e7981 */
/* 0x000168000c1e1900 */
/*03d0*/ LDG.E R13, [R4.64+0x40000] ; /* 0x04000004040d7981 */
/* 0x000168000c1e1900 */
/*03e0*/ LDG.E R12, [R4.64+0x48000] ; /* 0x04800004040c7981 */
/* 0x000168000c1e1900 */
/*03f0*/ LDG.E R11, [R4.64+0x50000] ; /* 0x05000004040b7981 */
/* 0x000168000c1e1900 */
/*0400*/ LDG.E R10, [R4.64+0x58000] ; /* 0x05800004040a7981 */
/* 0x000168000c1e1900 */
/*0410*/ LDG.E R8, [R4.64+0x60000] ; /* 0x0600000404087981 */
/* 0x000168000c1e1900 */
/*0420*/ LDG.E R9, [R4.64+0x68000] ; /* 0x0680000404097981 */
/* 0x000162000c1e1900 */
/*0430*/ IADD3 R18, R18, 0x20000, RZ ; /* 0x0002000012127810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.GE.AND P2, PT, R18, 0xe0000, PT ; /* 0x000e00001200780c */
/* 0x000fe40003f46270 */
/*0450*/ IADD3 R4, P3, R4, 0x80000, RZ ; /* 0x0008000004047810 */
/* 0x001fca0007f7e0ff */
/*0460*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe400018e0605 */
/*0470*/ IMAD R6, R19, R19, R6 ; /* 0x0000001313067224 */
/* 0x004fc800078e0206 */
/*0480*/ IMAD R6, R21, R21, R6 ; /* 0x0000001515067224 */
/* 0x008fc800078e0206 */
/*0490*/ IMAD R6, R23, R23, R6 ; /* 0x0000001717067224 */
/* 0x010fc800078e0206 */
/*04a0*/ IMAD R6, R25, R25, R6 ; /* 0x0000001919067224 */
/* 0x020fc800078e0206 */
/*04b0*/ IMAD R6, R27, R27, R6 ; /* 0x0000001b1b067224 */
/* 0x000fc800078e0206 */
/*04c0*/ IMAD R6, R29, R29, R6 ; /* 0x0000001d1d067224 */
/* 0x000fc800078e0206 */
/*04d0*/ IMAD R17, R17, R17, R6 ; /* 0x0000001111117224 */
/* 0x000fc800078e0206 */
/*04e0*/ IMAD R16, R16, R16, R17 ; /* 0x0000001010107224 */
/* 0x000fc800078e0211 */
/*04f0*/ IMAD R15, R15, R15, R16 ; /* 0x0000000f0f0f7224 */
/* 0x000fc800078e0210 */
/*0500*/ IMAD R14, R14, R14, R15 ; /* 0x0000000e0e0e7224 */
/* 0x000fc800078e020f */
/*0510*/ IMAD R13, R13, R13, R14 ; /* 0x0000000d0d0d7224 */
/* 0x000fc800078e020e */
/*0520*/ IMAD R12, R12, R12, R13 ; /* 0x0000000c0c0c7224 */
/* 0x000fc800078e020d */
/*0530*/ IMAD R11, R11, R11, R12 ; /* 0x0000000b0b0b7224 */
/* 0x000fc800078e020c */
/*0540*/ IMAD R11, R10, R10, R11 ; /* 0x0000000a0a0b7224 */
/* 0x000fc800078e020b */
/*0550*/ IMAD R6, R8, R8, R11 ; /* 0x0000000808067224 */
/* 0x000fc800078e020b */
/*0560*/ IMAD R6, R9, R9, R6 ; /* 0x0000000909067224 */
/* 0x000fe200078e0206 */
/*0570*/ @!P2 BRA 0x330 ; /* 0xfffffdb00000a947 */
/* 0x000fea000383ffff */
/*0580*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0590*/ IADD3 R8, -R18, 0xf8000, RZ ; /* 0x000f800012087810 */
/* 0x000fe20007ffe1ff */
/*05a0*/ BSSY B2, 0x740 ; /* 0x0000019000027945 */
/* 0x000fe60003800000 */
/*05b0*/ ISETP.GT.AND P2, PT, R8, 0x8000, PT ; /* 0x000080000800780c */
/* 0x000fda0003f44270 */
/*05c0*/ @!P2 BRA 0x730 ; /* 0x000001600000a947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R9, [R4.64+-0x10000] ; /* 0xff00000404097981 */
/* 0x0000a8000c1e1900 */
/*05e0*/ LDG.E R11, [R4.64+-0x8000] ; /* 0xff800004040b7981 */
/* 0x0000e8000c1e1900 */
/*05f0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R15, [R4.64+0x8000] ; /* 0x00800004040f7981 */
/* 0x000168000c1e1900 */
/*0610*/ LDG.E R17, [R4.64+0x10000] ; /* 0x0100000404117981 */
/* 0x000168000c1e1900 */
/*0620*/ LDG.E R19, [R4.64+0x18000] ; /* 0x0180000404137981 */
/* 0x000168000c1e1900 */
/*0630*/ LDG.E R21, [R4.64+0x20000] ; /* 0x0200000404157981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R23, [R4.64+0x28000] ; /* 0x0280000404177981 */
/* 0x000162000c1e1900 */
/*0650*/ IADD3 R8, P2, R4, 0x40000, RZ ; /* 0x0004000004087810 */
/* 0x000fc40007f5e0ff */
/*0660*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0670*/ IADD3 R18, R18, 0x10000, RZ ; /* 0x0001000012127810 */
/* 0x000fe20007ffe0ff */
/*0680*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*0690*/ IMAD R6, R9, R9, R6 ; /* 0x0000000909067224 */
/* 0x004fe200078e0206 */
/*06a0*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fc600017fe4ff */
/*06b0*/ IMAD R6, R11, R11, R6 ; /* 0x0000000b0b067224 */
/* 0x008fe200078e0206 */
/*06c0*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fc60000000f00 */
/*06d0*/ IMAD R6, R13, R13, R6 ; /* 0x0000000d0d067224 */
/* 0x010fc800078e0206 */
/*06e0*/ IMAD R6, R15, R15, R6 ; /* 0x0000000f0f067224 */
/* 0x020fc800078e0206 */
/*06f0*/ IMAD R6, R17, R17, R6 ; /* 0x0000001111067224 */
/* 0x000fc800078e0206 */
/*0700*/ IMAD R6, R19, R19, R6 ; /* 0x0000001313067224 */
/* 0x000fc800078e0206 */
/*0710*/ IMAD R6, R21, R21, R6 ; /* 0x0000001515067224 */
/* 0x000fc800078e0206 */
/*0720*/ IMAD R6, R23, R23, R6 ; /* 0x0000001717067224 */
/* 0x000fe400078e0206 */
/*0730*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.LT.OR P0, PT, R18, 0xf8000, P0 ; /* 0x000f80001200780c */
/* 0x000fda0000701670 */
/*0750*/ @!P0 BRA 0x7e0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R9, [R4.64+-0x10000] ; /* 0xff00000404097981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R11, [R4.64+-0x8000] ; /* 0xff800004040b7981 */
/* 0x000ee8000c1e1900 */
/*0780*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R15, [R4.64+0x8000] ; /* 0x00800004040f7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD R6, R9, R9, R6 ; /* 0x0000000909067224 */
/* 0x004fc800078e0206 */
/*07b0*/ IMAD R6, R11, R11, R6 ; /* 0x0000000b0b067224 */
/* 0x008fc800078e0206 */
/*07c0*/ IMAD R6, R13, R13, R6 ; /* 0x0000000d0d067224 */
/* 0x010fc800078e0206 */
/*07d0*/ IMAD R6, R15, R15, R6 ; /* 0x0000000f0f067224 */
/* 0x020fe400078e0206 */
/*07e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07f0*/ STS [R7.X4], R6 ; /* 0x0000000607007388 */
/* 0x0001e40000004800 */
/*0800*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0820*/ LOP3.LUT R4, R7.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107047812 */
/* 0x040fe400078ec0ff */
/*0830*/ LOP3.LUT P0, RZ, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307ff7812 */
/* 0x000fe4000780c0ff */
/*0840*/ ISETP.NE.U32.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f45070 */
/*0850*/ @P2 LDS R4, [R7.X4] ; /* 0x0000000007042984 */
/* 0x000fe80000004800 */
/*0860*/ @P2 LDS R5, [R7.X4+0x4] ; /* 0x0000040007052984 */
/* 0x000e240000004800 */
/*0870*/ @P2 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104042824 */
/* 0x001fca00078e0205 */
/*0880*/ @P2 STS [R7.X4], R4 ; /* 0x0000000407002388 */
/* 0x000fe80000004800 */
/*0890*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08a0*/ LOP3.LUT P2, RZ, R7, 0x7, RZ, 0xc0, !PT ; /* 0x0000000707ff7812 */
/* 0x000fca000784c0ff */
/*08b0*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe80000004800 */
/*08c0*/ @!P0 LDS R6, [R7.X4+0x8] ; /* 0x0000080007068984 */
/* 0x000e240000004800 */
/*08d0*/ @!P0 IADD3 R6, R5, R6, RZ ; /* 0x0000000605068210 */
/* 0x001fca0007ffe0ff */
/*08e0*/ @!P0 STS [R7.X4], R6 ; /* 0x0000000607008388 */
/* 0x000fe80000004800 */
/*08f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0900*/ LOP3.LUT P0, RZ, R7, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f07ff7812 */
/* 0x000fca000780c0ff */
/*0910*/ @!P2 LDS R5, [R7.X4] ; /* 0x000000000705a984 */
/* 0x000fe80000004800 */
/*0920*/ @!P2 LDS R8, [R7.X4+0x10] ; /* 0x000010000708a984 */
/* 0x000e240000004800 */
/*0930*/ @!P2 IMAD.IADD R8, R5, 0x1, R8 ; /* 0x000000010508a824 */
/* 0x001fca00078e0208 */
/*0940*/ @!P2 STS [R7.X4], R8 ; /* 0x000000080700a388 */
/* 0x000fe80000004800 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0960*/ LOP3.LUT P2, RZ, R7, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f07ff7812 */
/* 0x000fca000784c0ff */
/*0970*/ @!P0 LDS R4, [R7.X4] ; /* 0x0000000007048984 */
/* 0x000fe80000004800 */
/*0980*/ @!P0 LDS R5, [R7.X4+0x20] ; /* 0x0000200007058984 */
/* 0x000e240000004800 */
/*0990*/ @!P0 IADD3 R4, R4, R5, RZ ; /* 0x0000000504048210 */
/* 0x001fca0007ffe0ff */
/*09a0*/ @!P0 STS [R7.X4], R4 ; /* 0x0000000407008388 */
/* 0x000fe80000004800 */
/*09b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*09c0*/ LOP3.LUT P0, RZ, R7, 0x3f, RZ, 0xc0, !PT ; /* 0x0000003f07ff7812 */
/* 0x000fca000780c0ff */
/*09d0*/ @!P2 LDS R5, [R7.X4] ; /* 0x000000000705a984 */
/* 0x000fe80000004800 */
/*09e0*/ @!P2 LDS R6, [R7.X4+0x40] ; /* 0x000040000706a984 */
/* 0x000e240000004800 */
/*09f0*/ @!P2 IMAD.IADD R6, R5, 0x1, R6 ; /* 0x000000010506a824 */
/* 0x001fca00078e0206 */
/*0a00*/ @!P2 STS [R7.X4], R6 ; /* 0x000000060700a388 */
/* 0x000fe80000004800 */
/*0a10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a20*/ LOP3.LUT P2, RZ, R7, 0x7f, RZ, 0xc0, !PT ; /* 0x0000007f07ff7812 */
/* 0x000fca000784c0ff */
/*0a30*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe80000004800 */
/*0a40*/ @!P0 LDS R8, [R7.X4+0x80] ; /* 0x0000800007088984 */
/* 0x000e240000004800 */
/*0a50*/ @!P0 IADD3 R8, R5, R8, RZ ; /* 0x0000000805088210 */
/* 0x001fca0007ffe0ff */
/*0a60*/ @!P0 STS [R7.X4], R8 ; /* 0x0000000807008388 */
/* 0x000fe80000004800 */
/*0a70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a80*/ LOP3.LUT P0, RZ, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07ff7812 */
/* 0x000fca000780c0ff */
/*0a90*/ @!P2 LDS R4, [R7.X4] ; /* 0x000000000704a984 */
/* 0x000fe80000004800 */
/*0aa0*/ @!P2 LDS R5, [R7.X4+0x100] ; /* 0x000100000705a984 */
/* 0x000e240000004800 */
/*0ab0*/ @!P2 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x000000010404a824 */
/* 0x001fca00078e0205 */
/*0ac0*/ @!P2 STS [R7.X4], R4 ; /* 0x000000040700a388 */
/* 0x000fe80000004800 */
/*0ad0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ae0*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe80000004800 */
/*0af0*/ @!P0 LDS R6, [R7.X4+0x200] ; /* 0x0002000007068984 */
/* 0x000e240000004800 */
/*0b00*/ @!P0 IADD3 R6, R5, R6, RZ ; /* 0x0000000605068210 */
/* 0x001fca0007ffe0ff */
/*0b10*/ @!P0 STS [R7.X4], R6 ; /* 0x0000000607008388 */
/* 0x0001e80000004800 */
/*0b20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b30*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0b40*/ CS2R R6, SR_CLOCKLO ; /* 0x0000000000067805 */
/* 0x001fe40000015000 */
/*0b50*/ LDS R9, [RZ] ; /* 0x00000000ff097984 */
/* 0x000e220000000800 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0b70*/ STG.E.64 [R2.64+0x100], R6 ; /* 0x0001000602007986 */
/* 0x000fe2000c101b04 */
/*0b80*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0b90*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <cuda_runtime.h>
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
bool initCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0){
std::cout<<"There is no device."<<std::endl;
return false;
}
int i;
for(i=0;i<count;i++){
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop,i)==cudaSuccess){
if(prop.major>=1) break;
}
}
if(i==count){
std::cout<<"There is no device supporting CUDA 1.x/n"<<std::endl;
return false;
}
cudaSetDevice(i);
return true;
}
void generateNumbers(int* number, int size)
{
for(int i=0;i<size;i++){
number[i] = rand() % 10;
}
}
__global__
static void sumOfSquares(int* num, int* result, clock_t* time)
{
extern __shared__ int shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
int offset = 1, mask = 1;
//const int size = DATA_SIZE/THREAD_NUM;
if(tid == 0) time[bid] = clock();
shared[tid] = 0;
for(int i=bid*THREAD_NUM+tid;i<DATA_SIZE;i+=THREAD_NUM*BLOCK_NUM){
shared[tid] += num[i]*num[i];
}
__syncthreads();
while(offset<THREAD_NUM){
if((tid & mask) == 0){
shared[tid] += shared[tid+offset];
}
offset += offset;
mask = offset+mask;
__syncthreads();
}
if(tid == 0){
time[bid+BLOCK_NUM] = clock();
result[bid] = shared[0];
}
}
int sumOfSquared(int* data){
int sum = 0;
for(int i=0;i<DATA_SIZE;i++){
sum += data[i]*data[i];
}
return sum;
}
int main()
{
if(!initCUDA()) return 0;
std::cout<<"CUDA initialized"<<std::endl;
int data[DATA_SIZE];
generateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
cudaMalloc((void**)&gpudata, sizeof(int)*DATA_SIZE);
cudaMalloc((void**)&result, sizeof(int)*BLOCK_NUM);
cudaMalloc((void**)&time, sizeof(clock_t)*BLOCK_NUM*2);
cudaMemcpy(gpudata, data, sizeof(int)*DATA_SIZE, cudaMemcpyHostToDevice);
sumOfSquares<<<BLOCK_NUM,THREAD_NUM,THREAD_NUM*sizeof(int)>>>(gpudata, result, time);
int sum[THREAD_NUM*BLOCK_NUM];
clock_t time_used[BLOCK_NUM*2];
cudaMemcpy(sum, result, sizeof(int)*BLOCK_NUM, cudaMemcpyDeviceToHost);
cudaMemcpy(&time_used, time, sizeof(clock_t)*BLOCK_NUM*2, cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
cudaFree(time);
int final_sum = 0;
for(int i=0;i<BLOCK_NUM;i++){
final_sum += sum[i];
}
clock_t timeUsed;
for(int i=0;i<BLOCK_NUM;i++){
timeUsed += (time_used[i+BLOCK_NUM]-time_used[i]);
}
std::cout<<"sum (GPU): "<<final_sum<<"; time:"<<timeUsed<<std::endl;
clock_t start = clock();
int sumCpu = sumOfSquared(data);
clock_t usedTime = clock() - start;
std::cout<<"sum (CPU): "<<sumCpu<<"; time:"<<usedTime<<std::endl;
return 0;
}
|
.file "tmpxft_0002dc8c_00000000-6_first_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL12sumOfSquaresPiS_Pl, @function
_ZL12sumOfSquaresPiS_Pl:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _ZL12sumOfSquaresPiS_Pl, .-_ZL12sumOfSquaresPiS_Pl
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "There is no device."
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "There is no device supporting CUDA 1.x/n"
.text
.globl _Z8initCUDAv
.type _Z8initCUDAv, @function
_Z8initCUDAv:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L30
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L18
jmp .L20
.L30:
movl $19, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L31
cmpb $0, 56(%rbx)
je .L13
movzbl 67(%rbx), %eax
.L14:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
jmp .L9
.L31:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L13:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L14
.L16:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L19
.L18:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L16
cmpl $0, 376(%rsp)
jle .L16
.L19:
cmpl %ebx, 12(%rsp)
je .L33
.L20:
movl %ebx, %edi
call cudaSetDevice@PLT
movl $1, %eax
.L9:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L34
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $40, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L23
movzbl 67(%rbx), %esi
.L24:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
jmp .L9
.L35:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L36
call _ZSt16__throw_bad_castv@PLT
.L36:
call __stack_chk_fail@PLT
.L23:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8initCUDAv, .-_Z8initCUDAv
.globl _Z15generateNumbersPii
.type _Z15generateNumbersPii, @function
_Z15generateNumbersPii:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L42
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L39:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L39
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3670:
.size _Z15generateNumbersPii, .-_Z15generateNumbersPii
.globl _Z12sumOfSquaredPi
.type _Z12sumOfSquaredPi, @function
_Z12sumOfSquaredPi:
.LFB3671:
.cfi_startproc
endbr64
leaq 4194304(%rdi), %rcx
movl $0, %edx
.L46:
movl (%rdi), %eax
imull %eax, %eax
addl %eax, %edx
addq $4, %rdi
cmpq %rcx, %rdi
jne .L46
movl %edx, %eax
ret
.cfi_endproc
.LFE3671:
.size _Z12sumOfSquaredPi, .-_Z12sumOfSquaredPi
.section .rodata.str1.1
.LC2:
.string "CUDA initialized"
.LC3:
.string "sum (GPU): "
.LC4:
.string "; time:"
.LC5:
.string "sum (CPU): "
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq -4227072(%rsp), %r11
.cfi_def_cfa 11, 4227120
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $576, %rsp
.cfi_def_cfa_offset 4227696
movq %fs:40, %rax
movq %rax, 4227640(%rsp)
xorl %eax, %eax
call _Z8initCUDAv
testb %al, %al
jne .L57
.L49:
movq 4227640(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $4227648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 33328(%rsp), %rbx
movl $1048576, %esi
movq %rbx, %rdi
call _Z15generateNumbersPii
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $1024, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L50:
leaq 560(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 688(%rsp), %rcx
movl $0, %edx
.L51:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L51
leaq 48(%rsp), %rax
leaq 304(%rsp), %rdx
.L52:
addq 256(%rax), %rbp
subq (%rax), %rbp
addq $8, %rax
cmpq %rdx, %rax
jne .L52
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %r14
leaq 33328(%rsp), %rdi
call _Z12sumOfSquaredPi
movl %eax, %ebp
call clock@PLT
subq %r14, %rax
movq %rax, %rbx
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L59:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _ZL12sumOfSquaresPiS_Pl
jmp .L50
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12sumOfSquaresPiS_Pl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <cuda_runtime.h>
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
bool initCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0){
std::cout<<"There is no device."<<std::endl;
return false;
}
int i;
for(i=0;i<count;i++){
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop,i)==cudaSuccess){
if(prop.major>=1) break;
}
}
if(i==count){
std::cout<<"There is no device supporting CUDA 1.x/n"<<std::endl;
return false;
}
cudaSetDevice(i);
return true;
}
void generateNumbers(int* number, int size)
{
for(int i=0;i<size;i++){
number[i] = rand() % 10;
}
}
__global__
static void sumOfSquares(int* num, int* result, clock_t* time)
{
extern __shared__ int shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
int offset = 1, mask = 1;
//const int size = DATA_SIZE/THREAD_NUM;
if(tid == 0) time[bid] = clock();
shared[tid] = 0;
for(int i=bid*THREAD_NUM+tid;i<DATA_SIZE;i+=THREAD_NUM*BLOCK_NUM){
shared[tid] += num[i]*num[i];
}
__syncthreads();
while(offset<THREAD_NUM){
if((tid & mask) == 0){
shared[tid] += shared[tid+offset];
}
offset += offset;
mask = offset+mask;
__syncthreads();
}
if(tid == 0){
time[bid+BLOCK_NUM] = clock();
result[bid] = shared[0];
}
}
int sumOfSquared(int* data){
int sum = 0;
for(int i=0;i<DATA_SIZE;i++){
sum += data[i]*data[i];
}
return sum;
}
int main()
{
if(!initCUDA()) return 0;
std::cout<<"CUDA initialized"<<std::endl;
int data[DATA_SIZE];
generateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
cudaMalloc((void**)&gpudata, sizeof(int)*DATA_SIZE);
cudaMalloc((void**)&result, sizeof(int)*BLOCK_NUM);
cudaMalloc((void**)&time, sizeof(clock_t)*BLOCK_NUM*2);
cudaMemcpy(gpudata, data, sizeof(int)*DATA_SIZE, cudaMemcpyHostToDevice);
sumOfSquares<<<BLOCK_NUM,THREAD_NUM,THREAD_NUM*sizeof(int)>>>(gpudata, result, time);
int sum[THREAD_NUM*BLOCK_NUM];
clock_t time_used[BLOCK_NUM*2];
cudaMemcpy(sum, result, sizeof(int)*BLOCK_NUM, cudaMemcpyDeviceToHost);
cudaMemcpy(&time_used, time, sizeof(clock_t)*BLOCK_NUM*2, cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
cudaFree(time);
int final_sum = 0;
for(int i=0;i<BLOCK_NUM;i++){
final_sum += sum[i];
}
clock_t timeUsed;
for(int i=0;i<BLOCK_NUM;i++){
timeUsed += (time_used[i+BLOCK_NUM]-time_used[i]);
}
std::cout<<"sum (GPU): "<<final_sum<<"; time:"<<timeUsed<<std::endl;
clock_t start = clock();
int sumCpu = sumOfSquared(data);
clock_t usedTime = clock() - start;
std::cout<<"sum (CPU): "<<sumCpu<<"; time:"<<usedTime<<std::endl;
return 0;
}
|
#include <iostream>
#include <hip/hip_runtime.h>
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
bool initCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0){
std::cout<<"There is no device."<<std::endl;
return false;
}
int i;
for(i=0;i<count;i++){
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop,i)==hipSuccess){
if(prop.major>=1) break;
}
}
if(i==count){
std::cout<<"There is no device supporting CUDA 1.x/n"<<std::endl;
return false;
}
hipSetDevice(i);
return true;
}
void generateNumbers(int* number, int size)
{
for(int i=0;i<size;i++){
number[i] = rand() % 10;
}
}
__global__
static void sumOfSquares(int* num, int* result, clock_t* time)
{
extern __shared__ int shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
int offset = 1, mask = 1;
//const int size = DATA_SIZE/THREAD_NUM;
if(tid == 0) time[bid] = clock();
shared[tid] = 0;
for(int i=bid*THREAD_NUM+tid;i<DATA_SIZE;i+=THREAD_NUM*BLOCK_NUM){
shared[tid] += num[i]*num[i];
}
__syncthreads();
while(offset<THREAD_NUM){
if((tid & mask) == 0){
shared[tid] += shared[tid+offset];
}
offset += offset;
mask = offset+mask;
__syncthreads();
}
if(tid == 0){
time[bid+BLOCK_NUM] = clock();
result[bid] = shared[0];
}
}
int sumOfSquared(int* data){
int sum = 0;
for(int i=0;i<DATA_SIZE;i++){
sum += data[i]*data[i];
}
return sum;
}
int main()
{
if(!initCUDA()) return 0;
std::cout<<"CUDA initialized"<<std::endl;
int data[DATA_SIZE];
generateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
hipMalloc((void**)&gpudata, sizeof(int)*DATA_SIZE);
hipMalloc((void**)&result, sizeof(int)*BLOCK_NUM);
hipMalloc((void**)&time, sizeof(clock_t)*BLOCK_NUM*2);
hipMemcpy(gpudata, data, sizeof(int)*DATA_SIZE, hipMemcpyHostToDevice);
sumOfSquares<<<BLOCK_NUM,THREAD_NUM,THREAD_NUM*sizeof(int)>>>(gpudata, result, time);
int sum[THREAD_NUM*BLOCK_NUM];
clock_t time_used[BLOCK_NUM*2];
hipMemcpy(sum, result, sizeof(int)*BLOCK_NUM, hipMemcpyDeviceToHost);
hipMemcpy(&time_used, time, sizeof(clock_t)*BLOCK_NUM*2, hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
hipFree(time);
int final_sum = 0;
for(int i=0;i<BLOCK_NUM;i++){
final_sum += sum[i];
}
clock_t timeUsed;
for(int i=0;i<BLOCK_NUM;i++){
timeUsed += (time_used[i+BLOCK_NUM]-time_used[i]);
}
std::cout<<"sum (GPU): "<<final_sum<<"; time:"<<timeUsed<<std::endl;
clock_t start = clock();
int sumCpu = sumOfSquared(data);
clock_t usedTime = clock() - start;
std::cout<<"sum (CPU): "<<sumCpu<<"; time:"<<usedTime<<std::endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <iostream>
#include <hip/hip_runtime.h>
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
bool initCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0){
std::cout<<"There is no device."<<std::endl;
return false;
}
int i;
for(i=0;i<count;i++){
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop,i)==hipSuccess){
if(prop.major>=1) break;
}
}
if(i==count){
std::cout<<"There is no device supporting CUDA 1.x/n"<<std::endl;
return false;
}
hipSetDevice(i);
return true;
}
void generateNumbers(int* number, int size)
{
for(int i=0;i<size;i++){
number[i] = rand() % 10;
}
}
__global__
static void sumOfSquares(int* num, int* result, clock_t* time)
{
extern __shared__ int shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
int offset = 1, mask = 1;
//const int size = DATA_SIZE/THREAD_NUM;
if(tid == 0) time[bid] = clock();
shared[tid] = 0;
for(int i=bid*THREAD_NUM+tid;i<DATA_SIZE;i+=THREAD_NUM*BLOCK_NUM){
shared[tid] += num[i]*num[i];
}
__syncthreads();
while(offset<THREAD_NUM){
if((tid & mask) == 0){
shared[tid] += shared[tid+offset];
}
offset += offset;
mask = offset+mask;
__syncthreads();
}
if(tid == 0){
time[bid+BLOCK_NUM] = clock();
result[bid] = shared[0];
}
}
int sumOfSquared(int* data){
int sum = 0;
for(int i=0;i<DATA_SIZE;i++){
sum += data[i]*data[i];
}
return sum;
}
int main()
{
if(!initCUDA()) return 0;
std::cout<<"CUDA initialized"<<std::endl;
int data[DATA_SIZE];
generateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
hipMalloc((void**)&gpudata, sizeof(int)*DATA_SIZE);
hipMalloc((void**)&result, sizeof(int)*BLOCK_NUM);
hipMalloc((void**)&time, sizeof(clock_t)*BLOCK_NUM*2);
hipMemcpy(gpudata, data, sizeof(int)*DATA_SIZE, hipMemcpyHostToDevice);
sumOfSquares<<<BLOCK_NUM,THREAD_NUM,THREAD_NUM*sizeof(int)>>>(gpudata, result, time);
int sum[THREAD_NUM*BLOCK_NUM];
clock_t time_used[BLOCK_NUM*2];
hipMemcpy(sum, result, sizeof(int)*BLOCK_NUM, hipMemcpyDeviceToHost);
hipMemcpy(&time_used, time, sizeof(clock_t)*BLOCK_NUM*2, hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
hipFree(time);
int final_sum = 0;
for(int i=0;i<BLOCK_NUM;i++){
final_sum += sum[i];
}
clock_t timeUsed;
for(int i=0;i<BLOCK_NUM;i++){
timeUsed += (time_used[i+BLOCK_NUM]-time_used[i]);
}
std::cout<<"sum (GPU): "<<final_sum<<"; time:"<<timeUsed<<std::endl;
clock_t start = clock();
int sumCpu = sumOfSquared(data);
clock_t usedTime = clock() - start;
std::cout<<"sum (CPU): "<<sumCpu<<"; time:"<<usedTime<<std::endl;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.globl _ZL12sumOfSquaresPiS_Pl
.p2align 8
.type _ZL12sumOfSquaresPiS_Pl,@function
_ZL12sumOfSquaresPiS_Pl:
s_load_b64 s[6:7], s[0:1], 0x10
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s4, s15
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_getreg_b32 s3, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_ashr_i32 s5, s4, 31
v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, 0
s_lshl_b64 s[8:9], s[4:5], 3
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
global_store_b64 v3, v[1:2], s[8:9]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s3, s4, 8
v_lshl_add_u32 v6, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s3, v0
s_mov_b32 s5, exec_lo
ds_store_b32 v6, v2
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x0
ds_load_b32 v3, v6
v_ashrrev_i32_e32 v2, 31, v1
v_add3_u32 v7, v0, s3, 0xffffe000
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s2, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s9, v2, s2
s_mov_b32 s8, 0
.p2align 6
.LBB0_4:
global_load_b32 v8, v[1:2], off
v_add_nc_u32_e32 v7, 0x2000, v7
v_add_co_u32 v1, s2, v1, 0x8000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s2, 0, v2, s2
v_cmp_lt_i32_e64 s3, 0xfdfff, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s8, s3, s8
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v8, v8, v[3:4]
v_mov_b32_e32 v3, v4
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s8
ds_store_b32 v6, v4
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s3, 1
s_mov_b32 s5, 1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_lshl_b32 s2, s5, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, s3
s_cmpk_lt_u32 s5, 0x80
s_mov_b32 s5, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_8:
v_and_b32_e32 v1, s3, v0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
ds_load_b32 v2, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
ds_store_b32 v6, v1
s_branch .LBB0_7
.LBB0_10:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_ashr_i32 s5, s4, 31
ds_load_b32 v2, v0
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, 0
s_lshl_b64 s[2:3], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_clause 0x1
global_store_b64 v3, v[0:1], s[2:3] offset:256
global_store_b32 v3, v2, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL12sumOfSquaresPiS_Pl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.Lfunc_end0:
.size _ZL12sumOfSquaresPiS_Pl, .Lfunc_end0-_ZL12sumOfSquaresPiS_Pl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL12sumOfSquaresPiS_Pl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL12sumOfSquaresPiS_Pl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <iostream>
#include <hip/hip_runtime.h>
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
bool initCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0){
std::cout<<"There is no device."<<std::endl;
return false;
}
int i;
for(i=0;i<count;i++){
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop,i)==hipSuccess){
if(prop.major>=1) break;
}
}
if(i==count){
std::cout<<"There is no device supporting CUDA 1.x/n"<<std::endl;
return false;
}
hipSetDevice(i);
return true;
}
void generateNumbers(int* number, int size)
{
for(int i=0;i<size;i++){
number[i] = rand() % 10;
}
}
__global__
static void sumOfSquares(int* num, int* result, clock_t* time)
{
extern __shared__ int shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
int offset = 1, mask = 1;
//const int size = DATA_SIZE/THREAD_NUM;
if(tid == 0) time[bid] = clock();
shared[tid] = 0;
for(int i=bid*THREAD_NUM+tid;i<DATA_SIZE;i+=THREAD_NUM*BLOCK_NUM){
shared[tid] += num[i]*num[i];
}
__syncthreads();
while(offset<THREAD_NUM){
if((tid & mask) == 0){
shared[tid] += shared[tid+offset];
}
offset += offset;
mask = offset+mask;
__syncthreads();
}
if(tid == 0){
time[bid+BLOCK_NUM] = clock();
result[bid] = shared[0];
}
}
int sumOfSquared(int* data){
int sum = 0;
for(int i=0;i<DATA_SIZE;i++){
sum += data[i]*data[i];
}
return sum;
}
int main()
{
if(!initCUDA()) return 0;
std::cout<<"CUDA initialized"<<std::endl;
int data[DATA_SIZE];
generateNumbers(data, DATA_SIZE);
int* gpudata, *result;
clock_t* time;
hipMalloc((void**)&gpudata, sizeof(int)*DATA_SIZE);
hipMalloc((void**)&result, sizeof(int)*BLOCK_NUM);
hipMalloc((void**)&time, sizeof(clock_t)*BLOCK_NUM*2);
hipMemcpy(gpudata, data, sizeof(int)*DATA_SIZE, hipMemcpyHostToDevice);
sumOfSquares<<<BLOCK_NUM,THREAD_NUM,THREAD_NUM*sizeof(int)>>>(gpudata, result, time);
int sum[THREAD_NUM*BLOCK_NUM];
clock_t time_used[BLOCK_NUM*2];
hipMemcpy(sum, result, sizeof(int)*BLOCK_NUM, hipMemcpyDeviceToHost);
hipMemcpy(&time_used, time, sizeof(clock_t)*BLOCK_NUM*2, hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
hipFree(time);
int final_sum = 0;
for(int i=0;i<BLOCK_NUM;i++){
final_sum += sum[i];
}
clock_t timeUsed;
for(int i=0;i<BLOCK_NUM;i++){
timeUsed += (time_used[i+BLOCK_NUM]-time_used[i]);
}
std::cout<<"sum (GPU): "<<final_sum<<"; time:"<<timeUsed<<std::endl;
clock_t start = clock();
int sumCpu = sumOfSquared(data);
clock_t usedTime = clock() - start;
std::cout<<"sum (CPU): "<<sumCpu<<"; time:"<<usedTime<<std::endl;
return 0;
}
|
.text
.file "first_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initCUDAv # -- Begin function _Z8initCUDAv
.p2align 4, 0x90
.type _Z8initCUDAv,@function
_Z8initCUDAv: # @_Z8initCUDAv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB0_10
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_15
# %bb.2: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_4 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_6
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_3
# %bb.5: # in Loop: Header=BB0_4 Depth=1
cmpl $0, 368(%rsp)
jle .LBB0_3
.LBB0_6: # %._crit_edge
cmpl 4(%rsp), %ebx
jne .LBB0_16
.LBB0_7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_18
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%rbx)
jne .LBB0_12
.LBB0_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_14
.LBB0_10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_18
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_13
.LBB0_12:
movzbl 67(%rbx), %eax
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
jmp .LBB0_17
.LBB0_15:
xorl %ebx, %ebx
cmpl 4(%rsp), %ebx
je .LBB0_7
.LBB0_16:
movl %ebx, %edi
callq hipSetDevice
movb $1, %al
.LBB0_17:
# kill: def $al killed $al killed $eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_18:
.cfi_def_cfa_offset 1504
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z8initCUDAv, .Lfunc_end0-_Z8initCUDAv
.cfi_endproc
# -- End function
.globl _Z15generateNumbersPii # -- Begin function _Z15generateNumbersPii
.p2align 4, 0x90
.type _Z15generateNumbersPii,@function
_Z15generateNumbersPii: # @_Z15generateNumbersPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15generateNumbersPii, .Lfunc_end1-_Z15generateNumbersPii
.cfi_endproc
# -- End function
.globl _Z12sumOfSquaredPi # -- Begin function _Z12sumOfSquaredPi
.p2align 4, 0x90
.type _Z12sumOfSquaredPi,@function
_Z12sumOfSquaredPi: # @_Z12sumOfSquaredPi
.cfi_startproc
# %bb.0:
xorl %ecx, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl (%rdi,%rcx,4), %edx
imull %edx, %edx
addl %edx, %eax
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB2_1
# %bb.2:
retq
.Lfunc_end2:
.size _Z12sumOfSquaredPi, .Lfunc_end2-_Z12sumOfSquaredPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $4227664, %rsp # imm = 0x408250
.cfi_def_cfa_offset 4227696
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z8initCUDAv
testb %al, %al
je .LBB3_24
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_25
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB3_5
.LBB3_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 33360(%rsp,%rbx,4)
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB3_6
# %bb.7: # %_Z15generateNumbersPii.exit
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 16(%rsp), %rdi
leaq 33360(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
xorl %ebx, %ebx
movl $1024, %r8d # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 592(%rsp)
leaq 64(%rsp), %rax
movq %rax, 600(%rsp)
leaq 56(%rsp), %rax
movq %rax, 608(%rsp)
leaq 80(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 592(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 8(%rsp), %rsi
leaq 592(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_10: # =>This Inner Loop Header: Depth=1
addl 592(%rsp,%rax,4), %ebx
incq %rax
cmpq $32, %rax
jne .LBB3_10
# %bb.11: # %.preheader.preheader
xorl %eax, %eax
# implicit-def: $r14
.p2align 4, 0x90
.LBB3_12: # %.preheader
# =>This Inner Loop Header: Depth=1
addq 336(%rsp,%rax,8), %r14
subq 80(%rsp,%rax,8), %r14
incq %rax
cmpq $32, %rax
jne .LBB3_12
# %bb.13:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.4, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_25
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%rbx)
je .LBB3_16
# %bb.15:
movzbl 67(%rbx), %ecx
jmp .LBB3_17
.LBB3_16:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
callq clock
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_18: # =>This Inner Loop Header: Depth=1
movl 33360(%rsp,%r15,4), %eax
imull %eax, %eax
addl %eax, %ebx
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB3_18
# %bb.19: # %_Z12sumOfSquaredPi.exit
callq clock
movq %rax, %r15
subq %r14, %r15
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.4, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_25
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
cmpb $0, 56(%rbx)
je .LBB3_22
# %bb.21:
movzbl 67(%rbx), %ecx
jmp .LBB3_23
.LBB3_22:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_24:
xorl %eax, %eax
addq $4227664, %rsp # imm = 0x408250
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_25:
.cfi_def_cfa_offset 4227696
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL27__device_stub__sumOfSquaresPiS_Pl
.type _ZL27__device_stub__sumOfSquaresPiS_Pl,@function
_ZL27__device_stub__sumOfSquaresPiS_Pl: # @_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _ZL27__device_stub__sumOfSquaresPiS_Pl, .Lfunc_end4-_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL12sumOfSquaresPiS_Pl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There is no device."
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There is no device supporting CUDA 1.x/n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA initialized"
.size .L.str.2, 17
.type _ZL12sumOfSquaresPiS_Pl,@object # @_ZL12sumOfSquaresPiS_Pl
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL12sumOfSquaresPiS_Pl:
.quad _ZL27__device_stub__sumOfSquaresPiS_Pl
.size _ZL12sumOfSquaresPiS_Pl, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "sum (GPU): "
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "sum (CPU): "
.size .L.str.5, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL12sumOfSquaresPiS_Pl"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL27__device_stub__sumOfSquaresPiS_Pl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZL12sumOfSquaresPiS_Pl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12sumOfSquaresPiS_Pl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fcc0003f25270 */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x002fce00078e0203 */
/*0070*/ @!P1 CS2R R4, SR_CLOCKLO ; /* 0x0000000000049805 */
/* 0x000fca0000015000 */
/*0080*/ @!P1 STG.E.64 [R2.64], R4 ; /* 0x0000000402009986 */
/* 0x0001e2000c101b04 */
/*0090*/ IMAD R6, R0, 0x100, R7 ; /* 0x0000010000067824 */
/* 0x000fe200078e0207 */
/*00a0*/ BSSY B0, 0x810 ; /* 0x0000076000007945 */
/* 0x000fe40003800000 */
/*00b0*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0001e40000004800 */
/*00c0*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x000fda0003f04270 */
/*00d0*/ @P0 BRA 0x800 ; /* 0x0000072000000947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x001fe20000000f00 */
/*00f0*/ BSSY B1, 0x260 ; /* 0x0000016000017945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0110*/ IMNMX R4, R8, 0xfe000, !PT ; /* 0x000fe00008047817 */
/* 0x000fc80007800200 */
/*0120*/ IADD3 R5, -R7, 0x1fff, R4 ; /* 0x00001fff07057810 */
/* 0x000fca0007ffe104 */
/*0130*/ IMAD R5, R0, -0x100, R5 ; /* 0xffffff0000057824 */
/* 0x000fca00078e0205 */
/*0140*/ LEA.HI R4, R5.reuse, 0x1, RZ, 0x13 ; /* 0x0000000105047811 */
/* 0x040fe400078f98ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R5, 0x6000, PT ; /* 0x000060000500780c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT P2, R9, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304097812 */
/* 0x000fda000784c0ff */
/*0170*/ @!P2 BRA 0x250 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0180*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0190*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*01a0*/ IMAD.WIDE R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc800078e0205 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0005 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e000b */
/*01d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*01e0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R8, R8, 0x2000, RZ ; /* 0x0000200008087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0210*/ IADD3 R4, P3, R4, 0x8000, RZ ; /* 0x0000800004047810 */
/* 0x001fc80007f7e0ff */
/*0220*/ IADD3.X R11, RZ, R11, RZ, P3, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20001ffe4ff */
/*0230*/ IMAD R6, R5, R5, R6 ; /* 0x0000000505067224 */
/* 0x004fcc00078e0206 */
/*0240*/ @P2 BRA 0x1c0 ; /* 0xffffff7000002947 */
/* 0x000fea000383ffff */
/*0250*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0260*/ BSSY B1, 0x7f0 ; /* 0x0000058000017945 */
/* 0x000fe20003800000 */
/*0270*/ @!P0 BRA 0x7e0 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R18, R8.reuse, -0x8000, RZ ; /* 0xffff800008127810 */
/* 0x040fe20007ffe0ff */
/*02a0*/ BSSY B2, 0x590 ; /* 0x000002e000027945 */
/* 0x000fe40003800000 */
/*02b0*/ IMAD.WIDE R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe200078e0205 */
/*02c0*/ IADD3 R8, -R18, 0xf8000, RZ ; /* 0x000f800012087810 */
/* 0x000fc80007ffe1ff */
/*02d0*/ ISETP.GT.AND P2, PT, R8, 0x18000, PT ; /* 0x000180000800780c */
/* 0x000fe40003f44270 */
/*02e0*/ IADD3 R4, P0, R4, 0x10000, RZ ; /* 0x0001000004047810 */
/* 0x000fc80007f1e0ff */
/*02f0*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x000fe400007fe4ff */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0f070 */
/*0310*/ @!P2 BRA 0x580 ; /* 0x000002600000a947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*0330*/ LDG.E R19, [R4.64+-0x10000] ; /* 0xff00000404137981 */
/* 0x0000a8000c1e1900 */
/*0340*/ LDG.E R21, [R4.64+-0x8000] ; /* 0xff80000404157981 */
/* 0x0000e8000c1e1900 */
/*0350*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000128000c1e1900 */
/*0360*/ LDG.E R25, [R4.64+0x8000] ; /* 0x0080000404197981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R27, [R4.64+0x10000] ; /* 0x01000004041b7981 */
/* 0x000168000c1e1900 */
/*0380*/ LDG.E R29, [R4.64+0x18000] ; /* 0x01800004041d7981 */
/* 0x000168000c1e1900 */
/*0390*/ LDG.E R17, [R4.64+0x20000] ; /* 0x0200000404117981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R16, [R4.64+0x28000] ; /* 0x0280000404107981 */
/* 0x000168000c1e1900 */
/*03b0*/ LDG.E R15, [R4.64+0x30000] ; /* 0x03000004040f7981 */
/* 0x000168000c1e1900 */
/*03c0*/ LDG.E R14, [R4.64+0x38000] ; /* 0x03800004040e7981 */
/* 0x000168000c1e1900 */
/*03d0*/ LDG.E R13, [R4.64+0x40000] ; /* 0x04000004040d7981 */
/* 0x000168000c1e1900 */
/*03e0*/ LDG.E R12, [R4.64+0x48000] ; /* 0x04800004040c7981 */
/* 0x000168000c1e1900 */
/*03f0*/ LDG.E R11, [R4.64+0x50000] ; /* 0x05000004040b7981 */
/* 0x000168000c1e1900 */
/*0400*/ LDG.E R10, [R4.64+0x58000] ; /* 0x05800004040a7981 */
/* 0x000168000c1e1900 */
/*0410*/ LDG.E R8, [R4.64+0x60000] ; /* 0x0600000404087981 */
/* 0x000168000c1e1900 */
/*0420*/ LDG.E R9, [R4.64+0x68000] ; /* 0x0680000404097981 */
/* 0x000162000c1e1900 */
/*0430*/ IADD3 R18, R18, 0x20000, RZ ; /* 0x0002000012127810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.GE.AND P2, PT, R18, 0xe0000, PT ; /* 0x000e00001200780c */
/* 0x000fe40003f46270 */
/*0450*/ IADD3 R4, P3, R4, 0x80000, RZ ; /* 0x0008000004047810 */
/* 0x001fca0007f7e0ff */
/*0460*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe400018e0605 */
/*0470*/ IMAD R6, R19, R19, R6 ; /* 0x0000001313067224 */
/* 0x004fc800078e0206 */
/*0480*/ IMAD R6, R21, R21, R6 ; /* 0x0000001515067224 */
/* 0x008fc800078e0206 */
/*0490*/ IMAD R6, R23, R23, R6 ; /* 0x0000001717067224 */
/* 0x010fc800078e0206 */
/*04a0*/ IMAD R6, R25, R25, R6 ; /* 0x0000001919067224 */
/* 0x020fc800078e0206 */
/*04b0*/ IMAD R6, R27, R27, R6 ; /* 0x0000001b1b067224 */
/* 0x000fc800078e0206 */
/*04c0*/ IMAD R6, R29, R29, R6 ; /* 0x0000001d1d067224 */
/* 0x000fc800078e0206 */
/*04d0*/ IMAD R17, R17, R17, R6 ; /* 0x0000001111117224 */
/* 0x000fc800078e0206 */
/*04e0*/ IMAD R16, R16, R16, R17 ; /* 0x0000001010107224 */
/* 0x000fc800078e0211 */
/*04f0*/ IMAD R15, R15, R15, R16 ; /* 0x0000000f0f0f7224 */
/* 0x000fc800078e0210 */
/*0500*/ IMAD R14, R14, R14, R15 ; /* 0x0000000e0e0e7224 */
/* 0x000fc800078e020f */
/*0510*/ IMAD R13, R13, R13, R14 ; /* 0x0000000d0d0d7224 */
/* 0x000fc800078e020e */
/*0520*/ IMAD R12, R12, R12, R13 ; /* 0x0000000c0c0c7224 */
/* 0x000fc800078e020d */
/*0530*/ IMAD R11, R11, R11, R12 ; /* 0x0000000b0b0b7224 */
/* 0x000fc800078e020c */
/*0540*/ IMAD R11, R10, R10, R11 ; /* 0x0000000a0a0b7224 */
/* 0x000fc800078e020b */
/*0550*/ IMAD R6, R8, R8, R11 ; /* 0x0000000808067224 */
/* 0x000fc800078e020b */
/*0560*/ IMAD R6, R9, R9, R6 ; /* 0x0000000909067224 */
/* 0x000fe200078e0206 */
/*0570*/ @!P2 BRA 0x330 ; /* 0xfffffdb00000a947 */
/* 0x000fea000383ffff */
/*0580*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0590*/ IADD3 R8, -R18, 0xf8000, RZ ; /* 0x000f800012087810 */
/* 0x000fe20007ffe1ff */
/*05a0*/ BSSY B2, 0x740 ; /* 0x0000019000027945 */
/* 0x000fe60003800000 */
/*05b0*/ ISETP.GT.AND P2, PT, R8, 0x8000, PT ; /* 0x000080000800780c */
/* 0x000fda0003f44270 */
/*05c0*/ @!P2 BRA 0x730 ; /* 0x000001600000a947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R9, [R4.64+-0x10000] ; /* 0xff00000404097981 */
/* 0x0000a8000c1e1900 */
/*05e0*/ LDG.E R11, [R4.64+-0x8000] ; /* 0xff800004040b7981 */
/* 0x0000e8000c1e1900 */
/*05f0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R15, [R4.64+0x8000] ; /* 0x00800004040f7981 */
/* 0x000168000c1e1900 */
/*0610*/ LDG.E R17, [R4.64+0x10000] ; /* 0x0100000404117981 */
/* 0x000168000c1e1900 */
/*0620*/ LDG.E R19, [R4.64+0x18000] ; /* 0x0180000404137981 */
/* 0x000168000c1e1900 */
/*0630*/ LDG.E R21, [R4.64+0x20000] ; /* 0x0200000404157981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R23, [R4.64+0x28000] ; /* 0x0280000404177981 */
/* 0x000162000c1e1900 */
/*0650*/ IADD3 R8, P2, R4, 0x40000, RZ ; /* 0x0004000004087810 */
/* 0x000fc40007f5e0ff */
/*0660*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0670*/ IADD3 R18, R18, 0x10000, RZ ; /* 0x0001000012127810 */
/* 0x000fe20007ffe0ff */
/*0680*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*0690*/ IMAD R6, R9, R9, R6 ; /* 0x0000000909067224 */
/* 0x004fe200078e0206 */
/*06a0*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fc600017fe4ff */
/*06b0*/ IMAD R6, R11, R11, R6 ; /* 0x0000000b0b067224 */
/* 0x008fe200078e0206 */
/*06c0*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fc60000000f00 */
/*06d0*/ IMAD R6, R13, R13, R6 ; /* 0x0000000d0d067224 */
/* 0x010fc800078e0206 */
/*06e0*/ IMAD R6, R15, R15, R6 ; /* 0x0000000f0f067224 */
/* 0x020fc800078e0206 */
/*06f0*/ IMAD R6, R17, R17, R6 ; /* 0x0000001111067224 */
/* 0x000fc800078e0206 */
/*0700*/ IMAD R6, R19, R19, R6 ; /* 0x0000001313067224 */
/* 0x000fc800078e0206 */
/*0710*/ IMAD R6, R21, R21, R6 ; /* 0x0000001515067224 */
/* 0x000fc800078e0206 */
/*0720*/ IMAD R6, R23, R23, R6 ; /* 0x0000001717067224 */
/* 0x000fe400078e0206 */
/*0730*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.LT.OR P0, PT, R18, 0xf8000, P0 ; /* 0x000f80001200780c */
/* 0x000fda0000701670 */
/*0750*/ @!P0 BRA 0x7e0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R9, [R4.64+-0x10000] ; /* 0xff00000404097981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R11, [R4.64+-0x8000] ; /* 0xff800004040b7981 */
/* 0x000ee8000c1e1900 */
/*0780*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R15, [R4.64+0x8000] ; /* 0x00800004040f7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD R6, R9, R9, R6 ; /* 0x0000000909067224 */
/* 0x004fc800078e0206 */
/*07b0*/ IMAD R6, R11, R11, R6 ; /* 0x0000000b0b067224 */
/* 0x008fc800078e0206 */
/*07c0*/ IMAD R6, R13, R13, R6 ; /* 0x0000000d0d067224 */
/* 0x010fc800078e0206 */
/*07d0*/ IMAD R6, R15, R15, R6 ; /* 0x0000000f0f067224 */
/* 0x020fe400078e0206 */
/*07e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07f0*/ STS [R7.X4], R6 ; /* 0x0000000607007388 */
/* 0x0001e40000004800 */
/*0800*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0820*/ LOP3.LUT R4, R7.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107047812 */
/* 0x040fe400078ec0ff */
/*0830*/ LOP3.LUT P0, RZ, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307ff7812 */
/* 0x000fe4000780c0ff */
/*0840*/ ISETP.NE.U32.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f45070 */
/*0850*/ @P2 LDS R4, [R7.X4] ; /* 0x0000000007042984 */
/* 0x000fe80000004800 */
/*0860*/ @P2 LDS R5, [R7.X4+0x4] ; /* 0x0000040007052984 */
/* 0x000e240000004800 */
/*0870*/ @P2 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104042824 */
/* 0x001fca00078e0205 */
/*0880*/ @P2 STS [R7.X4], R4 ; /* 0x0000000407002388 */
/* 0x000fe80000004800 */
/*0890*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08a0*/ LOP3.LUT P2, RZ, R7, 0x7, RZ, 0xc0, !PT ; /* 0x0000000707ff7812 */
/* 0x000fca000784c0ff */
/*08b0*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe80000004800 */
/*08c0*/ @!P0 LDS R6, [R7.X4+0x8] ; /* 0x0000080007068984 */
/* 0x000e240000004800 */
/*08d0*/ @!P0 IADD3 R6, R5, R6, RZ ; /* 0x0000000605068210 */
/* 0x001fca0007ffe0ff */
/*08e0*/ @!P0 STS [R7.X4], R6 ; /* 0x0000000607008388 */
/* 0x000fe80000004800 */
/*08f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0900*/ LOP3.LUT P0, RZ, R7, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f07ff7812 */
/* 0x000fca000780c0ff */
/*0910*/ @!P2 LDS R5, [R7.X4] ; /* 0x000000000705a984 */
/* 0x000fe80000004800 */
/*0920*/ @!P2 LDS R8, [R7.X4+0x10] ; /* 0x000010000708a984 */
/* 0x000e240000004800 */
/*0930*/ @!P2 IMAD.IADD R8, R5, 0x1, R8 ; /* 0x000000010508a824 */
/* 0x001fca00078e0208 */
/*0940*/ @!P2 STS [R7.X4], R8 ; /* 0x000000080700a388 */
/* 0x000fe80000004800 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0960*/ LOP3.LUT P2, RZ, R7, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f07ff7812 */
/* 0x000fca000784c0ff */
/*0970*/ @!P0 LDS R4, [R7.X4] ; /* 0x0000000007048984 */
/* 0x000fe80000004800 */
/*0980*/ @!P0 LDS R5, [R7.X4+0x20] ; /* 0x0000200007058984 */
/* 0x000e240000004800 */
/*0990*/ @!P0 IADD3 R4, R4, R5, RZ ; /* 0x0000000504048210 */
/* 0x001fca0007ffe0ff */
/*09a0*/ @!P0 STS [R7.X4], R4 ; /* 0x0000000407008388 */
/* 0x000fe80000004800 */
/*09b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*09c0*/ LOP3.LUT P0, RZ, R7, 0x3f, RZ, 0xc0, !PT ; /* 0x0000003f07ff7812 */
/* 0x000fca000780c0ff */
/*09d0*/ @!P2 LDS R5, [R7.X4] ; /* 0x000000000705a984 */
/* 0x000fe80000004800 */
/*09e0*/ @!P2 LDS R6, [R7.X4+0x40] ; /* 0x000040000706a984 */
/* 0x000e240000004800 */
/*09f0*/ @!P2 IMAD.IADD R6, R5, 0x1, R6 ; /* 0x000000010506a824 */
/* 0x001fca00078e0206 */
/*0a00*/ @!P2 STS [R7.X4], R6 ; /* 0x000000060700a388 */
/* 0x000fe80000004800 */
/*0a10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a20*/ LOP3.LUT P2, RZ, R7, 0x7f, RZ, 0xc0, !PT ; /* 0x0000007f07ff7812 */
/* 0x000fca000784c0ff */
/*0a30*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe80000004800 */
/*0a40*/ @!P0 LDS R8, [R7.X4+0x80] ; /* 0x0000800007088984 */
/* 0x000e240000004800 */
/*0a50*/ @!P0 IADD3 R8, R5, R8, RZ ; /* 0x0000000805088210 */
/* 0x001fca0007ffe0ff */
/*0a60*/ @!P0 STS [R7.X4], R8 ; /* 0x0000000807008388 */
/* 0x000fe80000004800 */
/*0a70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a80*/ LOP3.LUT P0, RZ, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07ff7812 */
/* 0x000fca000780c0ff */
/*0a90*/ @!P2 LDS R4, [R7.X4] ; /* 0x000000000704a984 */
/* 0x000fe80000004800 */
/*0aa0*/ @!P2 LDS R5, [R7.X4+0x100] ; /* 0x000100000705a984 */
/* 0x000e240000004800 */
/*0ab0*/ @!P2 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x000000010404a824 */
/* 0x001fca00078e0205 */
/*0ac0*/ @!P2 STS [R7.X4], R4 ; /* 0x000000040700a388 */
/* 0x000fe80000004800 */
/*0ad0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ae0*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe80000004800 */
/*0af0*/ @!P0 LDS R6, [R7.X4+0x200] ; /* 0x0002000007068984 */
/* 0x000e240000004800 */
/*0b00*/ @!P0 IADD3 R6, R5, R6, RZ ; /* 0x0000000605068210 */
/* 0x001fca0007ffe0ff */
/*0b10*/ @!P0 STS [R7.X4], R6 ; /* 0x0000000607008388 */
/* 0x0001e80000004800 */
/*0b20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b30*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0b40*/ CS2R R6, SR_CLOCKLO ; /* 0x0000000000067805 */
/* 0x001fe40000015000 */
/*0b50*/ LDS R9, [RZ] ; /* 0x00000000ff097984 */
/* 0x000e220000000800 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0b70*/ STG.E.64 [R2.64+0x100], R6 ; /* 0x0001000602007986 */
/* 0x000fe2000c101b04 */
/*0b80*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0b90*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.globl _ZL12sumOfSquaresPiS_Pl
.p2align 8
.type _ZL12sumOfSquaresPiS_Pl,@function
_ZL12sumOfSquaresPiS_Pl:
s_load_b64 s[6:7], s[0:1], 0x10
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s4, s15
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_getreg_b32 s3, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_ashr_i32 s5, s4, 31
v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, 0
s_lshl_b64 s[8:9], s[4:5], 3
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
global_store_b64 v3, v[1:2], s[8:9]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s3, s4, 8
v_lshl_add_u32 v6, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s3, v0
s_mov_b32 s5, exec_lo
ds_store_b32 v6, v2
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x0
ds_load_b32 v3, v6
v_ashrrev_i32_e32 v2, 31, v1
v_add3_u32 v7, v0, s3, 0xffffe000
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s2, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s9, v2, s2
s_mov_b32 s8, 0
.p2align 6
.LBB0_4:
global_load_b32 v8, v[1:2], off
v_add_nc_u32_e32 v7, 0x2000, v7
v_add_co_u32 v1, s2, v1, 0x8000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s2, 0, v2, s2
v_cmp_lt_i32_e64 s3, 0xfdfff, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s8, s3, s8
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v8, v8, v[3:4]
v_mov_b32_e32 v3, v4
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s8
ds_store_b32 v6, v4
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s3, 1
s_mov_b32 s5, 1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_lshl_b32 s2, s5, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, s3
s_cmpk_lt_u32 s5, 0x80
s_mov_b32 s5, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_8:
v_and_b32_e32 v1, s3, v0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
ds_load_b32 v2, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
ds_store_b32 v6, v1
s_branch .LBB0_7
.LBB0_10:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_ashr_i32 s5, s4, 31
ds_load_b32 v2, v0
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, 0
s_lshl_b64 s[2:3], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_clause 0x1
global_store_b64 v3, v[0:1], s[2:3] offset:256
global_store_b32 v3, v2, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL12sumOfSquaresPiS_Pl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL12sumOfSquaresPiS_Pl,"axG",@progbits,_ZL12sumOfSquaresPiS_Pl,comdat
.Lfunc_end0:
.size _ZL12sumOfSquaresPiS_Pl, .Lfunc_end0-_ZL12sumOfSquaresPiS_Pl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL12sumOfSquaresPiS_Pl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL12sumOfSquaresPiS_Pl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0002dc8c_00000000-6_first_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL12sumOfSquaresPiS_Pl, @function
_ZL12sumOfSquaresPiS_Pl:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _ZL12sumOfSquaresPiS_Pl, .-_ZL12sumOfSquaresPiS_Pl
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "There is no device."
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "There is no device supporting CUDA 1.x/n"
.text
.globl _Z8initCUDAv
.type _Z8initCUDAv, @function
_Z8initCUDAv:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L30
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L18
jmp .L20
.L30:
movl $19, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L31
cmpb $0, 56(%rbx)
je .L13
movzbl 67(%rbx), %eax
.L14:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
jmp .L9
.L31:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L13:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L14
.L16:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L19
.L18:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L16
cmpl $0, 376(%rsp)
jle .L16
.L19:
cmpl %ebx, 12(%rsp)
je .L33
.L20:
movl %ebx, %edi
call cudaSetDevice@PLT
movl $1, %eax
.L9:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L34
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $40, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L23
movzbl 67(%rbx), %esi
.L24:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
jmp .L9
.L35:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L36
call _ZSt16__throw_bad_castv@PLT
.L36:
call __stack_chk_fail@PLT
.L23:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8initCUDAv, .-_Z8initCUDAv
.globl _Z15generateNumbersPii
.type _Z15generateNumbersPii, @function
_Z15generateNumbersPii:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L42
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L39:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L39
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3670:
.size _Z15generateNumbersPii, .-_Z15generateNumbersPii
.globl _Z12sumOfSquaredPi
.type _Z12sumOfSquaredPi, @function
_Z12sumOfSquaredPi:
.LFB3671:
.cfi_startproc
endbr64
leaq 4194304(%rdi), %rcx
movl $0, %edx
.L46:
movl (%rdi), %eax
imull %eax, %eax
addl %eax, %edx
addq $4, %rdi
cmpq %rcx, %rdi
jne .L46
movl %edx, %eax
ret
.cfi_endproc
.LFE3671:
.size _Z12sumOfSquaredPi, .-_Z12sumOfSquaredPi
.section .rodata.str1.1
.LC2:
.string "CUDA initialized"
.LC3:
.string "sum (GPU): "
.LC4:
.string "; time:"
.LC5:
.string "sum (CPU): "
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq -4227072(%rsp), %r11
.cfi_def_cfa 11, 4227120
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $576, %rsp
.cfi_def_cfa_offset 4227696
movq %fs:40, %rax
movq %rax, 4227640(%rsp)
xorl %eax, %eax
call _Z8initCUDAv
testb %al, %al
jne .L57
.L49:
movq 4227640(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $4227648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 33328(%rsp), %rbx
movl $1048576, %esi
movq %rbx, %rdi
call _Z15generateNumbersPii
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $1024, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L50:
leaq 560(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 688(%rsp), %rcx
movl $0, %edx
.L51:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L51
leaq 48(%rsp), %rax
leaq 304(%rsp), %rdx
.L52:
addq 256(%rax), %rbp
subq (%rax), %rbp
addq $8, %rax
cmpq %rdx, %rax
jne .L52
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %r14
leaq 33328(%rsp), %rdi
call _Z12sumOfSquaredPi
movl %eax, %ebp
call clock@PLT
subq %r14, %rax
movq %rax, %rbx
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L59:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _ZL12sumOfSquaresPiS_Pl
jmp .L50
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12sumOfSquaresPiS_Pl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12sumOfSquaresPiS_Pl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "first_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initCUDAv # -- Begin function _Z8initCUDAv
.p2align 4, 0x90
.type _Z8initCUDAv,@function
_Z8initCUDAv: # @_Z8initCUDAv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB0_10
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_15
# %bb.2: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_4 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_6
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_3
# %bb.5: # in Loop: Header=BB0_4 Depth=1
cmpl $0, 368(%rsp)
jle .LBB0_3
.LBB0_6: # %._crit_edge
cmpl 4(%rsp), %ebx
jne .LBB0_16
.LBB0_7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_18
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%rbx)
jne .LBB0_12
.LBB0_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_14
.LBB0_10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_18
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_13
.LBB0_12:
movzbl 67(%rbx), %eax
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
jmp .LBB0_17
.LBB0_15:
xorl %ebx, %ebx
cmpl 4(%rsp), %ebx
je .LBB0_7
.LBB0_16:
movl %ebx, %edi
callq hipSetDevice
movb $1, %al
.LBB0_17:
# kill: def $al killed $al killed $eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_18:
.cfi_def_cfa_offset 1504
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z8initCUDAv, .Lfunc_end0-_Z8initCUDAv
.cfi_endproc
# -- End function
.globl _Z15generateNumbersPii # -- Begin function _Z15generateNumbersPii
.p2align 4, 0x90
.type _Z15generateNumbersPii,@function
_Z15generateNumbersPii: # @_Z15generateNumbersPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15generateNumbersPii, .Lfunc_end1-_Z15generateNumbersPii
.cfi_endproc
# -- End function
.globl _Z12sumOfSquaredPi # -- Begin function _Z12sumOfSquaredPi
.p2align 4, 0x90
.type _Z12sumOfSquaredPi,@function
_Z12sumOfSquaredPi: # @_Z12sumOfSquaredPi
.cfi_startproc
# %bb.0:
xorl %ecx, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl (%rdi,%rcx,4), %edx
imull %edx, %edx
addl %edx, %eax
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB2_1
# %bb.2:
retq
.Lfunc_end2:
.size _Z12sumOfSquaredPi, .Lfunc_end2-_Z12sumOfSquaredPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $4227664, %rsp # imm = 0x408250
.cfi_def_cfa_offset 4227696
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z8initCUDAv
testb %al, %al
je .LBB3_24
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_25
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB3_5
.LBB3_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 33360(%rsp,%rbx,4)
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB3_6
# %bb.7: # %_Z15generateNumbersPii.exit
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 16(%rsp), %rdi
leaq 33360(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
xorl %ebx, %ebx
movl $1024, %r8d # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 592(%rsp)
leaq 64(%rsp), %rax
movq %rax, 600(%rsp)
leaq 56(%rsp), %rax
movq %rax, 608(%rsp)
leaq 80(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 592(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 8(%rsp), %rsi
leaq 592(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_10: # =>This Inner Loop Header: Depth=1
addl 592(%rsp,%rax,4), %ebx
incq %rax
cmpq $32, %rax
jne .LBB3_10
# %bb.11: # %.preheader.preheader
xorl %eax, %eax
# implicit-def: $r14
.p2align 4, 0x90
.LBB3_12: # %.preheader
# =>This Inner Loop Header: Depth=1
addq 336(%rsp,%rax,8), %r14
subq 80(%rsp,%rax,8), %r14
incq %rax
cmpq $32, %rax
jne .LBB3_12
# %bb.13:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.4, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_25
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%rbx)
je .LBB3_16
# %bb.15:
movzbl 67(%rbx), %ecx
jmp .LBB3_17
.LBB3_16:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
callq clock
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_18: # =>This Inner Loop Header: Depth=1
movl 33360(%rsp,%r15,4), %eax
imull %eax, %eax
addl %eax, %ebx
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB3_18
# %bb.19: # %_Z12sumOfSquaredPi.exit
callq clock
movq %rax, %r15
subq %r14, %r15
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.4, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_25
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
cmpb $0, 56(%rbx)
je .LBB3_22
# %bb.21:
movzbl 67(%rbx), %ecx
jmp .LBB3_23
.LBB3_22:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_24:
xorl %eax, %eax
addq $4227664, %rsp # imm = 0x408250
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_25:
.cfi_def_cfa_offset 4227696
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL27__device_stub__sumOfSquaresPiS_Pl
.type _ZL27__device_stub__sumOfSquaresPiS_Pl,@function
_ZL27__device_stub__sumOfSquaresPiS_Pl: # @_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL12sumOfSquaresPiS_Pl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _ZL27__device_stub__sumOfSquaresPiS_Pl, .Lfunc_end4-_ZL27__device_stub__sumOfSquaresPiS_Pl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL12sumOfSquaresPiS_Pl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There is no device."
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "There is no device supporting CUDA 1.x/n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA initialized"
.size .L.str.2, 17
.type _ZL12sumOfSquaresPiS_Pl,@object # @_ZL12sumOfSquaresPiS_Pl
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL12sumOfSquaresPiS_Pl:
.quad _ZL27__device_stub__sumOfSquaresPiS_Pl
.size _ZL12sumOfSquaresPiS_Pl, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "sum (GPU): "
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "sum (CPU): "
.size .L.str.5, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL12sumOfSquaresPiS_Pl"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL27__device_stub__sumOfSquaresPiS_Pl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZL12sumOfSquaresPiS_Pl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
============================================================================
Name : backpropagate.cu
Author : Christophoros Bekos ([email protected])
Version :
Copyright : @ copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#define work_per_block 100
#define threads_per_warp 32
#define threads_per_warp 32
__device__ void sigmoid(float& z) {
z = 1.0 / (1.0 + exp(-(z)));
}
__device__ void hadamard_product_small(float* sh_a, float* sh_b, float* sh_res,
int multiplier, int size, int mult) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
// start the computations
int cnt = 0;
for (int i = thread_id * multiplier;
i < thread_id * multiplier + multiplier; i++) {
sh_res[i * mult] = sh_b[i] * sh_a[i] * ((int) (i < size));
cnt++;
}
// result is stored in sh_b vector\
//done
}
__device__ void array_sum_small(float* sha, float& result, int size,
int start) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
// start the computations
for (int i = threads_per_warp; i < work_per_block; i = i * 2) {
// switch 1 : even warps add their's neighbors contents
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// add the "more next vector"
sha[thread_id] = sha[thread_id]
+ sha[i + thread_id]
* ((int) (start + thread_id + i < size));
break;
default:
// thread_id % i == odd
// do nothing
break;
}
__syncthreads();
// switch2 : odd warps clean up their content
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// do nothing
break;
default:
// thread_id % i == odd
// clean up
sha[thread_id] = 0;
//__syncthreads();
break;
}
__syncthreads();
}
// loop ended, sha[0:threads_per_warp] got the sum
if (thread_id == 0) {
for (int i = 0; i < threads_per_warp; i++) {
result = result + sha[i];
sha[i] = 0;
}
}
}
__device__ void backpropagate_some_cols(float* result, int rows_per_block,
int col_length, float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
// README :
// each block uses rows threads
// each block modifies rows columns ( cols columns per block)
// each thread modifies one column , column's length is col_length
// cols : number of columns that this block will modify
// one last block has less job to do, this one takes parameter last_block == 1
// and size (after index exceeds size in last block, no computation must be made)
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
extern __shared__ float shared[];
float* temp = shared;
float* m = &temp[rows_per_block];
float* v = &m[col_length * rows_per_block];
float* res = &v[col_length * rows_per_block];
// move data in shared memory
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = matrix[i];
}
v[thread_id] = 0;
v[thread_id] = vector[thread_id] * (thread_id < col_length);
__syncthreads();
int cnt = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = m[i] * v[cnt];
cnt++;
}
__syncthreads();
temp[thread_id] = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
temp[thread_id] += m[i];
}
__syncthreads();
result[thread_id] = temp[thread_id] * sigm_der[thread_id];
}
__global__ void backpropagate(float* result, int rows_per_block, int col_length,
float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
int block_id = blockIdx.y * gridDim.x + blockIdx.x;
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
backpropagate_some_cols(&result[block_id * rows_per_block], rows_per_block,
col_length, &matrix[block_id * rows_per_block], vector,
(block_id == last_block), size,
&sigm_der[block_id * rows_per_block]);
}
void initialize(float *data, unsigned size, float arg) {
for (unsigned i = 0; i < size; ++i) {
data[i] = arg;
}
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w);
int main(void) {
int rows = 783;
int cols = 30;
float *w = new float[rows * cols];
float *d_old = new float[cols];
float *delta = new float[rows];
float *delta_gpu = new float[rows];
float* sigm_der = new float[rows];
float *m, *v, *new_delta, *sigm_der_gpu;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
w[i * cols + j] = 1.2;
}
}
initialize(d_old, cols, 1.5);
initialize(sigm_der, rows, 1.6);
cudaMalloc((void**) &m, sizeof(float) * (rows * cols));
cudaMalloc((void**) &v, sizeof(float) * cols);
cudaMalloc((void**) &new_delta, sizeof(float) * rows);
cudaMalloc((void**) &sigm_der_gpu, sizeof(float) * rows);
cudaMemcpy(m, w, sizeof(float) * (rows * cols), cudaMemcpyHostToDevice);
cudaMemcpy(v, d_old, sizeof(float) * cols, cudaMemcpyHostToDevice);
cudaMemcpy(sigm_der_gpu, sigm_der, sizeof(float) * rows,
cudaMemcpyHostToDevice);
int numofthreads = work_per_block;
int rows_per_block = numofthreads;
int col_length = cols;
int last_block = floor(rows / work_per_block);
float cache = 11000 * sizeof(float);
int num_of_blocks = floor(rows / work_per_block) + 1;
int size_for_last_block = rows
- floor(rows / work_per_block) * numofthreads;
// printf("aaaa %d \n", num_of_blocks);
// BACKPROPAGATE FOR 1 ITERATION
// IN GPU
//printf("sadfa %d ",size_for_last_block);
backpropagate<<<num_of_blocks, rows_per_block, cache>>>(new_delta,
rows_per_block, col_length, m, v, last_block, size_for_last_block,
sigm_der_gpu);
cudaDeviceSynchronize();
cudaMemcpy(delta_gpu, new_delta, sizeof(float) * rows,
cudaMemcpyDeviceToHost);
// IN CPU
cpu_backpropagate(d_old, rows, cols, &delta, sigm_der, w);
// COMPARE RESULTS
int success = 1;
for (int i = 0; i < rows; i++) {
// printf("kappa %f \n", delta[i]);
if (delta[i] != delta_gpu[i]) {
printf("ERROR in a, cpu = %f, gpu = %f\n", delta[i], delta_gpu[i]);
success = 0;
}
}
/* Free memory */
cudaFree(new_delta);
cudaFree(m);
cudaFree(v);
if (success) {
printf("SUCCESS \n");
}
return 0;
}
float* hadamard_product(int size, float* a, float* b) {
// returns the datamard product for vectors a and b
// (return a.*b in matlab)
// size = length of arrays a and b
float* result = new float[size];
for (int i = 0; i < size; i++) {
result[i] = a[i] * b[i];
}
return result;
}
float* mull_backpropagate(int rows, int cols, float* matrix, float* vector) {
// TESTED
// returns "rows x 1" vector
float* temp = NULL;
float* res = new float[rows];
for (int j = 0; j < rows; j++) {
temp = hadamard_product(cols, &matrix[j * cols], vector);
res[j] = 0;
for (int i = 0; i < cols; i++) {
res[j] += temp[i];
}
delete[] temp;
}
return res;
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w) {
float* w_d;
w_d = mull_backpropagate(rows, cols, w, d_L);
d_new[0] = hadamard_product(rows, w_d, sigm_der);
delete[] w_d;
}
|
.file "tmpxft_001876f1_00000000-6_backpropagate.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3719:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3719:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sigmoidRf
.type _Z7sigmoidRf, @function
_Z7sigmoidRf:
.LFB3708:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3708:
.size _Z7sigmoidRf, .-_Z7sigmoidRf
.globl _Z22hadamard_product_smallPfS_S_iii
.type _Z22hadamard_product_smallPfS_S_iii, @function
_Z22hadamard_product_smallPfS_S_iii:
.LFB3709:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3709:
.size _Z22hadamard_product_smallPfS_S_iii, .-_Z22hadamard_product_smallPfS_S_iii
.globl _Z15array_sum_smallPfRfii
.type _Z15array_sum_smallPfRfii, @function
_Z15array_sum_smallPfRfii:
.LFB3710:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3710:
.size _Z15array_sum_smallPfRfii, .-_Z15array_sum_smallPfRfii
.globl _Z23backpropagate_some_colsPfiiS_S_iiS_
.type _Z23backpropagate_some_colsPfiiS_S_iiS_, @function
_Z23backpropagate_some_colsPfiiS_S_iiS_:
.LFB3711:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3711:
.size _Z23backpropagate_some_colsPfiiS_S_iiS_, .-_Z23backpropagate_some_colsPfiiS_S_iiS_
.globl _Z10initializePfjf
.type _Z10initializePfjf, @function
_Z10initializePfjf:
.LFB3712:
.cfi_startproc
endbr64
testl %esi, %esi
je .L11
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rdx
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE3712:
.size _Z10initializePfjf, .-_Z10initializePfjf
.globl _Z16hadamard_productiPfS_
.type _Z16hadamard_productiPfS_, @function
_Z16hadamard_productiPfS_:
.LFB3714:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movslq %edi, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L16
movl %edi, %r13d
movq %rsi, %rbp
movq %rdx, %r12
salq $2, %rbx
movq %rbx, %rdi
call _Znam@PLT
movl $0, %edx
testl %r13d, %r13d
jle .L15
.L17:
movss 0(%rbp,%rdx), %xmm0
mulss (%r12,%rdx), %xmm0
movss %xmm0, (%rax,%rdx)
addq $4, %rdx
cmpq %rdx, %rbx
jne .L17
.L15:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3714:
.size _Z16hadamard_productiPfS_, .-_Z16hadamard_productiPfS_
.globl _Z18mull_backpropagateiiPfS_
.type _Z18mull_backpropagateiiPfS_, @function
_Z18mull_backpropagateiiPfS_:
.LFB3715:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movslq %edi, %r14
movabsq $2305843009213693950, %rax
cmpq %r14, %rax
jb .L24
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, %rbp
movq %rcx, %r15
salq $2, %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L23
movslq %r12d, %r13
salq $2, %r13
movq 8(%rsp), %rax
movq %rax, %rbx
addq %rax, %r14
jmp .L30
.L24:
call __cxa_throw_bad_array_new_length@PLT
.L29:
addq %r13, %rbp
addq $4, %rbx
cmpq %r14, %rbx
je .L23
.L30:
movq %r15, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call _Z16hadamard_productiPfS_
movq %rbx, %rcx
movl $0x00000000, (%rbx)
testl %r12d, %r12d
jle .L27
movq %rax, %rdx
leaq (%rax,%r13), %rsi
.L28:
movss (%rcx), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rdx
cmpq %rsi, %rdx
jne .L28
.L27:
testq %rax, %rax
je .L29
movq %rax, %rdi
call _ZdaPv@PLT
jmp .L29
.L23:
movq 8(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3715:
.size _Z18mull_backpropagateiiPfS_, .-_Z18mull_backpropagateiiPfS_
.globl _Z17cpu_backpropagatePfiiPS_S_S_
.type _Z17cpu_backpropagatePfiiPS_S_S_, @function
_Z17cpu_backpropagatePfiiPS_S_S_:
.LFB3716:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %esi, %ebp
movl %edx, %esi
movq %rcx, %r12
movq %r8, %r13
movq %r9, %rdx
movq %rdi, %rcx
movl %ebp, %edi
call _Z18mull_backpropagateiiPfS_
movq %rax, %rbx
movq %r13, %rdx
movq %rax, %rsi
movl %ebp, %edi
call _Z16hadamard_productiPfS_
movq %rax, (%r12)
testq %rbx, %rbx
je .L34
movq %rbx, %rdi
call _ZdaPv@PLT
.L34:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3716:
.size _Z17cpu_backpropagatePfiiPS_S_S_, .-_Z17cpu_backpropagatePfiiPS_S_S_
.globl _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
.type _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_, @function
_Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_:
.LFB3741:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13backpropagatePfiiS_S_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3741:
.size _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_, .-_Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
.globl _Z13backpropagatePfiiS_S_iiS_
.type _Z13backpropagatePfiiS_S_iiS_, @function
_Z13backpropagatePfiiS_S_iiS_:
.LFB3742:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3742:
.size _Z13backpropagatePfiiS_S_iiS_, .-_Z13backpropagatePfiiS_S_iiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "ERROR in a, cpu = %f, gpu = %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "SUCCESS \n"
.text
.globl main
.type main, @function
main:
.LFB3713:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $93960, %edi
call _Znam@PLT
movq %rax, %rbp
movl $120, %edi
call _Znam@PLT
movq %rax, %r12
movl $3132, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $3132, %edi
call _Znam@PLT
movq %rax, %rbx
movl $3132, %edi
call _Znam@PLT
movq %rax, %r13
leaq 120(%rbp), %rdx
leaq 94080(%rbp), %rcx
movss .LC1(%rip), %xmm0
jmp .L46
.L59:
addq $120, %rdx
cmpq %rcx, %rdx
je .L48
.L46:
leaq -120(%rdx), %rax
.L47:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L47
jmp .L59
.L48:
movss .LC2(%rip), %xmm0
movl $30, %esi
movq %r12, %rdi
call _Z10initializePfjf
movss .LC3(%rip), %xmm0
movl $783, %esi
movq %r13, %rdi
call _Z10initializePfjf
leaq 16(%rsp), %rdi
movl $93960, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $120, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $3132, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $3132, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $93960, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $120, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $3132, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $44000, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L49:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $3132, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rcx
movq %rbp, %r9
movq %r13, %r8
movl $30, %edx
movl $783, %esi
movq %r12, %rdi
call _Z17cpu_backpropagatePfiiPS_S_S_
movl $0, %ebp
movl $1, %r13d
leaq .LC4(%rip), %r12
jmp .L52
.L60:
pushq 40(%rsp)
.cfi_def_cfa_offset 136
pushq $83
.cfi_def_cfa_offset 144
movl $7, %r9d
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movl $30, %edx
movl $100, %esi
movq 48(%rsp), %rdi
call _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L49
.L55:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %r13d
.L50:
addq $4, %rbp
cmpq $3132, %rbp
je .L61
.L52:
movq 8(%rsp), %rax
movss (%rax,%rbp), %xmm0
movss (%rbx,%rbp), %xmm1
ucomiss %xmm1, %xmm0
jp .L55
je .L50
jmp .L55
.L61:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %r13d, %r13d
jne .L62
.L53:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L53
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3713:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z13backpropagatePfiiS_S_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3744:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13backpropagatePfiiS_S_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3744:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1067030938
.align 4
.LC2:
.long 1069547520
.align 4
.LC3:
.long 1070386381
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
============================================================================
Name : backpropagate.cu
Author : Christophoros Bekos ([email protected])
Version :
Copyright : @ copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#define work_per_block 100
#define threads_per_warp 32
#define threads_per_warp 32
__device__ void sigmoid(float& z) {
z = 1.0 / (1.0 + exp(-(z)));
}
__device__ void hadamard_product_small(float* sh_a, float* sh_b, float* sh_res,
int multiplier, int size, int mult) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
// start the computations
int cnt = 0;
for (int i = thread_id * multiplier;
i < thread_id * multiplier + multiplier; i++) {
sh_res[i * mult] = sh_b[i] * sh_a[i] * ((int) (i < size));
cnt++;
}
// result is stored in sh_b vector\
//done
}
__device__ void array_sum_small(float* sha, float& result, int size,
int start) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
// start the computations
for (int i = threads_per_warp; i < work_per_block; i = i * 2) {
// switch 1 : even warps add their's neighbors contents
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// add the "more next vector"
sha[thread_id] = sha[thread_id]
+ sha[i + thread_id]
* ((int) (start + thread_id + i < size));
break;
default:
// thread_id % i == odd
// do nothing
break;
}
__syncthreads();
// switch2 : odd warps clean up their content
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// do nothing
break;
default:
// thread_id % i == odd
// clean up
sha[thread_id] = 0;
//__syncthreads();
break;
}
__syncthreads();
}
// loop ended, sha[0:threads_per_warp] got the sum
if (thread_id == 0) {
for (int i = 0; i < threads_per_warp; i++) {
result = result + sha[i];
sha[i] = 0;
}
}
}
__device__ void backpropagate_some_cols(float* result, int rows_per_block,
int col_length, float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
// README :
// each block uses rows threads
// each block modifies rows columns ( cols columns per block)
// each thread modifies one column , column's length is col_length
// cols : number of columns that this block will modify
// one last block has less job to do, this one takes parameter last_block == 1
// and size (after index exceeds size in last block, no computation must be made)
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
extern __shared__ float shared[];
float* temp = shared;
float* m = &temp[rows_per_block];
float* v = &m[col_length * rows_per_block];
float* res = &v[col_length * rows_per_block];
// move data in shared memory
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = matrix[i];
}
v[thread_id] = 0;
v[thread_id] = vector[thread_id] * (thread_id < col_length);
__syncthreads();
int cnt = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = m[i] * v[cnt];
cnt++;
}
__syncthreads();
temp[thread_id] = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
temp[thread_id] += m[i];
}
__syncthreads();
result[thread_id] = temp[thread_id] * sigm_der[thread_id];
}
__global__ void backpropagate(float* result, int rows_per_block, int col_length,
float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
int block_id = blockIdx.y * gridDim.x + blockIdx.x;
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
backpropagate_some_cols(&result[block_id * rows_per_block], rows_per_block,
col_length, &matrix[block_id * rows_per_block], vector,
(block_id == last_block), size,
&sigm_der[block_id * rows_per_block]);
}
void initialize(float *data, unsigned size, float arg) {
for (unsigned i = 0; i < size; ++i) {
data[i] = arg;
}
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w);
int main(void) {
int rows = 783;
int cols = 30;
float *w = new float[rows * cols];
float *d_old = new float[cols];
float *delta = new float[rows];
float *delta_gpu = new float[rows];
float* sigm_der = new float[rows];
float *m, *v, *new_delta, *sigm_der_gpu;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
w[i * cols + j] = 1.2;
}
}
initialize(d_old, cols, 1.5);
initialize(sigm_der, rows, 1.6);
cudaMalloc((void**) &m, sizeof(float) * (rows * cols));
cudaMalloc((void**) &v, sizeof(float) * cols);
cudaMalloc((void**) &new_delta, sizeof(float) * rows);
cudaMalloc((void**) &sigm_der_gpu, sizeof(float) * rows);
cudaMemcpy(m, w, sizeof(float) * (rows * cols), cudaMemcpyHostToDevice);
cudaMemcpy(v, d_old, sizeof(float) * cols, cudaMemcpyHostToDevice);
cudaMemcpy(sigm_der_gpu, sigm_der, sizeof(float) * rows,
cudaMemcpyHostToDevice);
int numofthreads = work_per_block;
int rows_per_block = numofthreads;
int col_length = cols;
int last_block = floor(rows / work_per_block);
float cache = 11000 * sizeof(float);
int num_of_blocks = floor(rows / work_per_block) + 1;
int size_for_last_block = rows
- floor(rows / work_per_block) * numofthreads;
// printf("aaaa %d \n", num_of_blocks);
// BACKPROPAGATE FOR 1 ITERATION
// IN GPU
//printf("sadfa %d ",size_for_last_block);
backpropagate<<<num_of_blocks, rows_per_block, cache>>>(new_delta,
rows_per_block, col_length, m, v, last_block, size_for_last_block,
sigm_der_gpu);
cudaDeviceSynchronize();
cudaMemcpy(delta_gpu, new_delta, sizeof(float) * rows,
cudaMemcpyDeviceToHost);
// IN CPU
cpu_backpropagate(d_old, rows, cols, &delta, sigm_der, w);
// COMPARE RESULTS
int success = 1;
for (int i = 0; i < rows; i++) {
// printf("kappa %f \n", delta[i]);
if (delta[i] != delta_gpu[i]) {
printf("ERROR in a, cpu = %f, gpu = %f\n", delta[i], delta_gpu[i]);
success = 0;
}
}
/* Free memory */
cudaFree(new_delta);
cudaFree(m);
cudaFree(v);
if (success) {
printf("SUCCESS \n");
}
return 0;
}
float* hadamard_product(int size, float* a, float* b) {
// returns the datamard product for vectors a and b
// (return a.*b in matlab)
// size = length of arrays a and b
float* result = new float[size];
for (int i = 0; i < size; i++) {
result[i] = a[i] * b[i];
}
return result;
}
float* mull_backpropagate(int rows, int cols, float* matrix, float* vector) {
// TESTED
// returns "rows x 1" vector
float* temp = NULL;
float* res = new float[rows];
for (int j = 0; j < rows; j++) {
temp = hadamard_product(cols, &matrix[j * cols], vector);
res[j] = 0;
for (int i = 0; i < cols; i++) {
res[j] += temp[i];
}
delete[] temp;
}
return res;
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w) {
float* w_d;
w_d = mull_backpropagate(rows, cols, w, d_L);
d_new[0] = hadamard_product(rows, w_d, sigm_der);
delete[] w_d;
}
|
/*
============================================================================
Name : backpropagate.cu
Author : Christophoros Bekos ([email protected])
Version :
Copyright : @ copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#define work_per_block 100
#define threads_per_warp 32
#define threads_per_warp 32
__device__ void sigmoid(float& z) {
z = 1.0 / (1.0 + exp(-(z)));
}
__device__ void hadamard_product_small(float* sh_a, float* sh_b, float* sh_res,
int multiplier, int size, int mult) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
// start the computations
int cnt = 0;
for (int i = thread_id * multiplier;
i < thread_id * multiplier + multiplier; i++) {
sh_res[i * mult] = sh_b[i] * sh_a[i] * ((int) (i < size));
cnt++;
}
// result is stored in sh_b vector\
//done
}
__device__ void array_sum_small(float* sha, float& result, int size,
int start) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
// start the computations
for (int i = threads_per_warp; i < work_per_block; i = i * 2) {
// switch 1 : even warps add their's neighbors contents
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// add the "more next vector"
sha[thread_id] = sha[thread_id]
+ sha[i + thread_id]
* ((int) (start + thread_id + i < size));
break;
default:
// thread_id % i == odd
// do nothing
break;
}
__syncthreads();
// switch2 : odd warps clean up their content
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// do nothing
break;
default:
// thread_id % i == odd
// clean up
sha[thread_id] = 0;
//__syncthreads();
break;
}
__syncthreads();
}
// loop ended, sha[0:threads_per_warp] got the sum
if (thread_id == 0) {
for (int i = 0; i < threads_per_warp; i++) {
result = result + sha[i];
sha[i] = 0;
}
}
}
__device__ void backpropagate_some_cols(float* result, int rows_per_block,
int col_length, float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
// README :
// each block uses rows threads
// each block modifies rows columns ( cols columns per block)
// each thread modifies one column , column's length is col_length
// cols : number of columns that this block will modify
// one last block has less job to do, this one takes parameter last_block == 1
// and size (after index exceeds size in last block, no computation must be made)
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
extern __shared__ float shared[];
float* temp = shared;
float* m = &temp[rows_per_block];
float* v = &m[col_length * rows_per_block];
float* res = &v[col_length * rows_per_block];
// move data in shared memory
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = matrix[i];
}
v[thread_id] = 0;
v[thread_id] = vector[thread_id] * (thread_id < col_length);
__syncthreads();
int cnt = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = m[i] * v[cnt];
cnt++;
}
__syncthreads();
temp[thread_id] = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
temp[thread_id] += m[i];
}
__syncthreads();
result[thread_id] = temp[thread_id] * sigm_der[thread_id];
}
__global__ void backpropagate(float* result, int rows_per_block, int col_length,
float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
int block_id = blockIdx.y * gridDim.x + blockIdx.x;
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
backpropagate_some_cols(&result[block_id * rows_per_block], rows_per_block,
col_length, &matrix[block_id * rows_per_block], vector,
(block_id == last_block), size,
&sigm_der[block_id * rows_per_block]);
}
void initialize(float *data, unsigned size, float arg) {
for (unsigned i = 0; i < size; ++i) {
data[i] = arg;
}
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w);
int main(void) {
int rows = 783;
int cols = 30;
float *w = new float[rows * cols];
float *d_old = new float[cols];
float *delta = new float[rows];
float *delta_gpu = new float[rows];
float* sigm_der = new float[rows];
float *m, *v, *new_delta, *sigm_der_gpu;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
w[i * cols + j] = 1.2;
}
}
initialize(d_old, cols, 1.5);
initialize(sigm_der, rows, 1.6);
hipMalloc((void**) &m, sizeof(float) * (rows * cols));
hipMalloc((void**) &v, sizeof(float) * cols);
hipMalloc((void**) &new_delta, sizeof(float) * rows);
hipMalloc((void**) &sigm_der_gpu, sizeof(float) * rows);
hipMemcpy(m, w, sizeof(float) * (rows * cols), hipMemcpyHostToDevice);
hipMemcpy(v, d_old, sizeof(float) * cols, hipMemcpyHostToDevice);
hipMemcpy(sigm_der_gpu, sigm_der, sizeof(float) * rows,
hipMemcpyHostToDevice);
int numofthreads = work_per_block;
int rows_per_block = numofthreads;
int col_length = cols;
int last_block = floor(rows / work_per_block);
float cache = 11000 * sizeof(float);
int num_of_blocks = floor(rows / work_per_block) + 1;
int size_for_last_block = rows
- floor(rows / work_per_block) * numofthreads;
// printf("aaaa %d \n", num_of_blocks);
// BACKPROPAGATE FOR 1 ITERATION
// IN GPU
//printf("sadfa %d ",size_for_last_block);
backpropagate<<<num_of_blocks, rows_per_block, cache>>>(new_delta,
rows_per_block, col_length, m, v, last_block, size_for_last_block,
sigm_der_gpu);
hipDeviceSynchronize();
hipMemcpy(delta_gpu, new_delta, sizeof(float) * rows,
hipMemcpyDeviceToHost);
// IN CPU
cpu_backpropagate(d_old, rows, cols, &delta, sigm_der, w);
// COMPARE RESULTS
int success = 1;
for (int i = 0; i < rows; i++) {
// printf("kappa %f \n", delta[i]);
if (delta[i] != delta_gpu[i]) {
printf("ERROR in a, cpu = %f, gpu = %f\n", delta[i], delta_gpu[i]);
success = 0;
}
}
/* Free memory */
hipFree(new_delta);
hipFree(m);
hipFree(v);
if (success) {
printf("SUCCESS \n");
}
return 0;
}
float* hadamard_product(int size, float* a, float* b) {
// returns the datamard product for vectors a and b
// (return a.*b in matlab)
// size = length of arrays a and b
float* result = new float[size];
for (int i = 0; i < size; i++) {
result[i] = a[i] * b[i];
}
return result;
}
float* mull_backpropagate(int rows, int cols, float* matrix, float* vector) {
// TESTED
// returns "rows x 1" vector
float* temp = NULL;
float* res = new float[rows];
for (int j = 0; j < rows; j++) {
temp = hadamard_product(cols, &matrix[j * cols], vector);
res[j] = 0;
for (int i = 0; i < cols; i++) {
res[j] += temp[i];
}
delete[] temp;
}
return res;
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w) {
float* w_d;
w_d = mull_backpropagate(rows, cols, w, d_L);
d_new[0] = hadamard_product(rows, w_d, sigm_der);
delete[] w_d;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
============================================================================
Name : backpropagate.cu
Author : Christophoros Bekos ([email protected])
Version :
Copyright : @ copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#define work_per_block 100
#define threads_per_warp 32
#define threads_per_warp 32
__device__ void sigmoid(float& z) {
z = 1.0 / (1.0 + exp(-(z)));
}
__device__ void hadamard_product_small(float* sh_a, float* sh_b, float* sh_res,
int multiplier, int size, int mult) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
// start the computations
int cnt = 0;
for (int i = thread_id * multiplier;
i < thread_id * multiplier + multiplier; i++) {
sh_res[i * mult] = sh_b[i] * sh_a[i] * ((int) (i < size));
cnt++;
}
// result is stored in sh_b vector\
//done
}
__device__ void array_sum_small(float* sha, float& result, int size,
int start) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
// start the computations
for (int i = threads_per_warp; i < work_per_block; i = i * 2) {
// switch 1 : even warps add their's neighbors contents
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// add the "more next vector"
sha[thread_id] = sha[thread_id]
+ sha[i + thread_id]
* ((int) (start + thread_id + i < size));
break;
default:
// thread_id % i == odd
// do nothing
break;
}
__syncthreads();
// switch2 : odd warps clean up their content
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// do nothing
break;
default:
// thread_id % i == odd
// clean up
sha[thread_id] = 0;
//__syncthreads();
break;
}
__syncthreads();
}
// loop ended, sha[0:threads_per_warp] got the sum
if (thread_id == 0) {
for (int i = 0; i < threads_per_warp; i++) {
result = result + sha[i];
sha[i] = 0;
}
}
}
__device__ void backpropagate_some_cols(float* result, int rows_per_block,
int col_length, float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
// README :
// each block uses rows threads
// each block modifies rows columns ( cols columns per block)
// each thread modifies one column , column's length is col_length
// cols : number of columns that this block will modify
// one last block has less job to do, this one takes parameter last_block == 1
// and size (after index exceeds size in last block, no computation must be made)
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
extern __shared__ float shared[];
float* temp = shared;
float* m = &temp[rows_per_block];
float* v = &m[col_length * rows_per_block];
float* res = &v[col_length * rows_per_block];
// move data in shared memory
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = matrix[i];
}
v[thread_id] = 0;
v[thread_id] = vector[thread_id] * (thread_id < col_length);
__syncthreads();
int cnt = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = m[i] * v[cnt];
cnt++;
}
__syncthreads();
temp[thread_id] = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
temp[thread_id] += m[i];
}
__syncthreads();
result[thread_id] = temp[thread_id] * sigm_der[thread_id];
}
__global__ void backpropagate(float* result, int rows_per_block, int col_length,
float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
int block_id = blockIdx.y * gridDim.x + blockIdx.x;
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
backpropagate_some_cols(&result[block_id * rows_per_block], rows_per_block,
col_length, &matrix[block_id * rows_per_block], vector,
(block_id == last_block), size,
&sigm_der[block_id * rows_per_block]);
}
void initialize(float *data, unsigned size, float arg) {
for (unsigned i = 0; i < size; ++i) {
data[i] = arg;
}
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w);
int main(void) {
int rows = 783;
int cols = 30;
float *w = new float[rows * cols];
float *d_old = new float[cols];
float *delta = new float[rows];
float *delta_gpu = new float[rows];
float* sigm_der = new float[rows];
float *m, *v, *new_delta, *sigm_der_gpu;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
w[i * cols + j] = 1.2;
}
}
initialize(d_old, cols, 1.5);
initialize(sigm_der, rows, 1.6);
hipMalloc((void**) &m, sizeof(float) * (rows * cols));
hipMalloc((void**) &v, sizeof(float) * cols);
hipMalloc((void**) &new_delta, sizeof(float) * rows);
hipMalloc((void**) &sigm_der_gpu, sizeof(float) * rows);
hipMemcpy(m, w, sizeof(float) * (rows * cols), hipMemcpyHostToDevice);
hipMemcpy(v, d_old, sizeof(float) * cols, hipMemcpyHostToDevice);
hipMemcpy(sigm_der_gpu, sigm_der, sizeof(float) * rows,
hipMemcpyHostToDevice);
int numofthreads = work_per_block;
int rows_per_block = numofthreads;
int col_length = cols;
int last_block = floor(rows / work_per_block);
float cache = 11000 * sizeof(float);
int num_of_blocks = floor(rows / work_per_block) + 1;
int size_for_last_block = rows
- floor(rows / work_per_block) * numofthreads;
// printf("aaaa %d \n", num_of_blocks);
// BACKPROPAGATE FOR 1 ITERATION
// IN GPU
//printf("sadfa %d ",size_for_last_block);
backpropagate<<<num_of_blocks, rows_per_block, cache>>>(new_delta,
rows_per_block, col_length, m, v, last_block, size_for_last_block,
sigm_der_gpu);
hipDeviceSynchronize();
hipMemcpy(delta_gpu, new_delta, sizeof(float) * rows,
hipMemcpyDeviceToHost);
// IN CPU
cpu_backpropagate(d_old, rows, cols, &delta, sigm_der, w);
// COMPARE RESULTS
int success = 1;
for (int i = 0; i < rows; i++) {
// printf("kappa %f \n", delta[i]);
if (delta[i] != delta_gpu[i]) {
printf("ERROR in a, cpu = %f, gpu = %f\n", delta[i], delta_gpu[i]);
success = 0;
}
}
/* Free memory */
hipFree(new_delta);
hipFree(m);
hipFree(v);
if (success) {
printf("SUCCESS \n");
}
return 0;
}
float* hadamard_product(int size, float* a, float* b) {
// returns the datamard product for vectors a and b
// (return a.*b in matlab)
// size = length of arrays a and b
float* result = new float[size];
for (int i = 0; i < size; i++) {
result[i] = a[i] * b[i];
}
return result;
}
float* mull_backpropagate(int rows, int cols, float* matrix, float* vector) {
// TESTED
// returns "rows x 1" vector
float* temp = NULL;
float* res = new float[rows];
for (int j = 0; j < rows; j++) {
temp = hadamard_product(cols, &matrix[j * cols], vector);
res[j] = 0;
for (int i = 0; i < cols; i++) {
res[j] += temp[i];
}
delete[] temp;
}
return res;
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w) {
float* w_d;
w_d = mull_backpropagate(rows, cols, w, d_L);
d_new[0] = hadamard_product(rows, w_d, sigm_der);
delete[] w_d;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13backpropagatePfiiS_S_iiS_
.globl _Z13backpropagatePfiiS_S_iiS_
.p2align 8
.type _Z13backpropagatePfiiS_S_iiS_,@function
_Z13backpropagatePfiiS_S_iiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x30
s_load_b64 s[6:7], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v3, v0, s2, v1
s_mul_i32 s2, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_mul_i32 s4, s2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v3, s7
s_ashr_i32 s5, s4, 31
s_cmp_gt_i32 s7, 0
s_cselect_b32 s3, -1, 0
s_cmp_lt_i32 s7, 1
v_add_nc_u32_e32 v4, s7, v0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[10:11], s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, v0
v_lshlrev_b32_e32 v5, 2, v0
s_lshl_b32 s2, s6, 2
s_lshl_b64 s[12:13], s[4:5], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add3_u32 v5, 0, s2, v5
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s10, s12
s_addc_u32 s9, s11, s13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
.LBB0_2:
global_load_b32 v7, v[1:2], off
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v6, v4
s_or_b32 s8, s2, s8
s_waitcnt vmcnt(0)
ds_store_b32 v5, v7
v_add_nc_u32_e32 v5, 4, v5
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_4:
s_load_b64 s[8:9], s[0:1], 0x18
v_cmp_gt_i32_e32 vcc_lo, s7, v3
s_mul_i32 s2, s7, s6
v_cndmask_b32_e64 v1, 0, 1, s3
s_lshl_b32 s2, s2, 2
v_cndmask_b32_e64 v6, 0, 1.0, vcc_lo
v_lshlrev_b32_e32 v2, 2, v3
s_and_not1_b32 vcc_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v2, s[8:9]
s_lshl_b32 s8, s6, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s8, 0
s_add_i32 s2, s9, s2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, v5, v6
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, s2, v2
ds_store_b32 v7, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_8
v_mul_lo_u32 v5, v3, s7
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v6, v0 :: v_dual_lshlrev_b32 v5, 2, v5
v_add3_u32 v5, 0, s8, v5
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v7, s2 :: v_dual_add_nc_u32 v6, 1, v6
s_add_i32 s2, s2, 4
ds_load_b32 v8, v5
ds_load_b32 v7, v7
v_cmp_ge_i32_e32 vcc_lo, v6, v4
s_or_b32 s3, vcc_lo, s3
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v7, v8, v7
ds_store_b32 v5, v7
v_add_nc_u32_e32 v5, 4, v5
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
v_cmp_ne_u32_e32 vcc_lo, 1, v1
v_lshl_add_u32 v1, v3, 2, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_store_b32 v1, v2
s_cbranch_vccnz .LBB0_12
v_mul_lo_u32 v2, v3, s7
s_lshl_b32 s3, s6, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 2, v2
v_add3_u32 v2, 0, s3, v2
.LBB0_10:
ds_load_b32 v6, v2
v_add_nc_u32_e32 v0, 1, v0
v_add_nc_u32_e32 v2, 4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v0, v4
ds_store_b32 v1, v5
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_10
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_load_b64 s[2:3], s[0:1], 0x28
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v1
v_lshlrev_b32_e32 v0, 2, v3
s_load_b64 s[0:1], s[0:1], 0x0
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
global_load_b32 v2, v0, s[2:3]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13backpropagatePfiiS_S_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13backpropagatePfiiS_S_iiS_, .Lfunc_end0-_Z13backpropagatePfiiS_S_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
- .offset: 168
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13backpropagatePfiiS_S_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13backpropagatePfiiS_S_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
============================================================================
Name : backpropagate.cu
Author : Christophoros Bekos ([email protected])
Version :
Copyright : @ copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#define work_per_block 100
#define threads_per_warp 32
#define threads_per_warp 32
__device__ void sigmoid(float& z) {
z = 1.0 / (1.0 + exp(-(z)));
}
__device__ void hadamard_product_small(float* sh_a, float* sh_b, float* sh_res,
int multiplier, int size, int mult) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
// start the computations
int cnt = 0;
for (int i = thread_id * multiplier;
i < thread_id * multiplier + multiplier; i++) {
sh_res[i * mult] = sh_b[i] * sh_a[i] * ((int) (i < size));
cnt++;
}
// result is stored in sh_b vector\
//done
}
__device__ void array_sum_small(float* sha, float& result, int size,
int start) {
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
// start the computations
for (int i = threads_per_warp; i < work_per_block; i = i * 2) {
// switch 1 : even warps add their's neighbors contents
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// add the "more next vector"
sha[thread_id] = sha[thread_id]
+ sha[i + thread_id]
* ((int) (start + thread_id + i < size));
break;
default:
// thread_id % i == odd
// do nothing
break;
}
__syncthreads();
// switch2 : odd warps clean up their content
switch ((int) floor(thread_id / (double) i) % 2) {
case 0:
// thread_id % i == even
// do nothing
break;
default:
// thread_id % i == odd
// clean up
sha[thread_id] = 0;
//__syncthreads();
break;
}
__syncthreads();
}
// loop ended, sha[0:threads_per_warp] got the sum
if (thread_id == 0) {
for (int i = 0; i < threads_per_warp; i++) {
result = result + sha[i];
sha[i] = 0;
}
}
}
__device__ void backpropagate_some_cols(float* result, int rows_per_block,
int col_length, float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
// README :
// each block uses rows threads
// each block modifies rows columns ( cols columns per block)
// each thread modifies one column , column's length is col_length
// cols : number of columns that this block will modify
// one last block has less job to do, this one takes parameter last_block == 1
// and size (after index exceeds size in last block, no computation must be made)
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
int block_id = blockIdx.x;
extern __shared__ float shared[];
float* temp = shared;
float* m = &temp[rows_per_block];
float* v = &m[col_length * rows_per_block];
float* res = &v[col_length * rows_per_block];
// move data in shared memory
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = matrix[i];
}
v[thread_id] = 0;
v[thread_id] = vector[thread_id] * (thread_id < col_length);
__syncthreads();
int cnt = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
m[i] = m[i] * v[cnt];
cnt++;
}
__syncthreads();
temp[thread_id] = 0;
for (int i = thread_id * col_length;
i < thread_id * col_length + col_length; i++) {
temp[thread_id] += m[i];
}
__syncthreads();
result[thread_id] = temp[thread_id] * sigm_der[thread_id];
}
__global__ void backpropagate(float* result, int rows_per_block, int col_length,
float* matrix, float* vector, int last_block, int size,
float* sigm_der) {
int block_id = blockIdx.y * gridDim.x + blockIdx.x;
int thread_id = threadIdx.y * blockDim.x + threadIdx.x;
backpropagate_some_cols(&result[block_id * rows_per_block], rows_per_block,
col_length, &matrix[block_id * rows_per_block], vector,
(block_id == last_block), size,
&sigm_der[block_id * rows_per_block]);
}
void initialize(float *data, unsigned size, float arg) {
for (unsigned i = 0; i < size; ++i) {
data[i] = arg;
}
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w);
int main(void) {
int rows = 783;
int cols = 30;
float *w = new float[rows * cols];
float *d_old = new float[cols];
float *delta = new float[rows];
float *delta_gpu = new float[rows];
float* sigm_der = new float[rows];
float *m, *v, *new_delta, *sigm_der_gpu;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
w[i * cols + j] = 1.2;
}
}
initialize(d_old, cols, 1.5);
initialize(sigm_der, rows, 1.6);
hipMalloc((void**) &m, sizeof(float) * (rows * cols));
hipMalloc((void**) &v, sizeof(float) * cols);
hipMalloc((void**) &new_delta, sizeof(float) * rows);
hipMalloc((void**) &sigm_der_gpu, sizeof(float) * rows);
hipMemcpy(m, w, sizeof(float) * (rows * cols), hipMemcpyHostToDevice);
hipMemcpy(v, d_old, sizeof(float) * cols, hipMemcpyHostToDevice);
hipMemcpy(sigm_der_gpu, sigm_der, sizeof(float) * rows,
hipMemcpyHostToDevice);
int numofthreads = work_per_block;
int rows_per_block = numofthreads;
int col_length = cols;
int last_block = floor(rows / work_per_block);
float cache = 11000 * sizeof(float);
int num_of_blocks = floor(rows / work_per_block) + 1;
int size_for_last_block = rows
- floor(rows / work_per_block) * numofthreads;
// printf("aaaa %d \n", num_of_blocks);
// BACKPROPAGATE FOR 1 ITERATION
// IN GPU
//printf("sadfa %d ",size_for_last_block);
backpropagate<<<num_of_blocks, rows_per_block, cache>>>(new_delta,
rows_per_block, col_length, m, v, last_block, size_for_last_block,
sigm_der_gpu);
hipDeviceSynchronize();
hipMemcpy(delta_gpu, new_delta, sizeof(float) * rows,
hipMemcpyDeviceToHost);
// IN CPU
cpu_backpropagate(d_old, rows, cols, &delta, sigm_der, w);
// COMPARE RESULTS
int success = 1;
for (int i = 0; i < rows; i++) {
// printf("kappa %f \n", delta[i]);
if (delta[i] != delta_gpu[i]) {
printf("ERROR in a, cpu = %f, gpu = %f\n", delta[i], delta_gpu[i]);
success = 0;
}
}
/* Free memory */
hipFree(new_delta);
hipFree(m);
hipFree(v);
if (success) {
printf("SUCCESS \n");
}
return 0;
}
float* hadamard_product(int size, float* a, float* b) {
// returns the datamard product for vectors a and b
// (return a.*b in matlab)
// size = length of arrays a and b
float* result = new float[size];
for (int i = 0; i < size; i++) {
result[i] = a[i] * b[i];
}
return result;
}
float* mull_backpropagate(int rows, int cols, float* matrix, float* vector) {
// TESTED
// returns "rows x 1" vector
float* temp = NULL;
float* res = new float[rows];
for (int j = 0; j < rows; j++) {
temp = hadamard_product(cols, &matrix[j * cols], vector);
res[j] = 0;
for (int i = 0; i < cols; i++) {
res[j] += temp[i];
}
delete[] temp;
}
return res;
}
void cpu_backpropagate(float* d_L, int rows, int cols, float** d_new,
float* sigm_der, float* w) {
float* w_d;
w_d = mull_backpropagate(rows, cols, w, d_L);
d_new[0] = hadamard_product(rows, w_d, sigm_der);
delete[] w_d;
}
|
.text
.file "backpropagate.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__backpropagatePfiiS_S_iiS_ # -- Begin function _Z28__device_stub__backpropagatePfiiS_S_iiS_
.p2align 4, 0x90
.type _Z28__device_stub__backpropagatePfiiS_S_iiS_,@function
_Z28__device_stub__backpropagatePfiiS_S_iiS_: # @_Z28__device_stub__backpropagatePfiiS_S_iiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13backpropagatePfiiS_S_iiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__backpropagatePfiiS_S_iiS_, .Lfunc_end0-_Z28__device_stub__backpropagatePfiiS_S_iiS_
.cfi_endproc
# -- End function
.globl _Z10initializePfjf # -- Begin function _Z10initializePfjf
.p2align 4, 0x90
.type _Z10initializePfjf,@function
_Z10initializePfjf: # @_Z10initializePfjf
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10initializePfjf, .Lfunc_end1-_Z10initializePfjf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $93960, %edi # imm = 0x16F08
callq _Znam
movq %rax, %r15
movl $120, %edi
callq _Znam
movq %rax, %r12
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %rbx
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %r14
xorl %eax, %eax
movq %r15, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1067030938, (%rcx,%rdx,4) # imm = 0x3F99999A
incq %rdx
cmpq $30, %rdx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $120, %rcx
cmpq $783, %rax # imm = 0x30F
jne .LBB2_1
# %bb.4: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1069547520, (%r12,%rax,4) # imm = 0x3FC00000
incq %rax
cmpq $30, %rax
jne .LBB2_5
# %bb.6: # %.lr.ph.i71.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i71
# =>This Inner Loop Header: Depth=1
movl $1070386381, (%r14,%rax,4) # imm = 0x3FCCCCCD
incq %rax
cmpq $783, %rax # imm = 0x30F
jne .LBB2_7
# %bb.8: # %_Z10initializePfjf.exit75
leaq 16(%rsp), %rdi
movl $93960, %esi # imm = 0x16F08
callq hipMalloc
leaq 8(%rsp), %rdi
movl $120, %esi
callq hipMalloc
movq %rsp, %rdi
movl $3132, %esi # imm = 0xC3C
callq hipMalloc
leaq 40(%rsp), %rdi
movl $3132, %esi # imm = 0xC3C
callq hipMalloc
movq 16(%rsp), %rdi
movl $93960, %edx # imm = 0x16F08
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $120, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $3132, %edx # imm = 0xC3C
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 92(%rdi), %rdx
movl $44000, %r8d # imm = 0xABE0
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rax, 120(%rsp)
movl $100, 36(%rsp)
movl $30, 32(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $7, 28(%rsp)
movl $83, 24(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13backpropagatePfiiS_S_iiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $3132, %edx # imm = 0xC3C
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_11: # =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
# Child Loop BB2_14 Depth 2
movl $120, %edi
callq _Znam
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_12: # %.lr.ph.i.i76
# Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r12,%rcx,4), %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $30, %rcx
jne .LBB2_12
# %bb.13: # %_Z16hadamard_productiPfS_.exit.i
# in Loop: Header=BB2_11 Depth=1
movl $0, (%r13,%rbp,4)
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rax,%rcx,4), %xmm0
incq %rcx
cmpq $30, %rcx
jne .LBB2_14
# %bb.15: # %._crit_edge.i
# in Loop: Header=BB2_11 Depth=1
movss %xmm0, (%r13,%rbp,4)
movq %rax, %rdi
callq _ZdaPv
incq %rbp
addq $120, %r15
cmpq $783, %rbp # imm = 0x30F
jne .LBB2_11
# %bb.16: # %_Z18mull_backpropagateiiPfS_.exit
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_17: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $783, %rax # imm = 0x30F
jne .LBB2_17
# %bb.18: # %_Z17cpu_backpropagatePfiiPS_S_S_.exit
movq %r13, %rdi
callq _ZdaPv
movl $1, %ebp
xorl %r14d, %r14d
jmp .LBB2_19
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_19 Depth=1
incq %r14
cmpq $783, %r14 # imm = 0x30F
je .LBB2_22
.LBB2_19: # =>This Inner Loop Header: Depth=1
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rbx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB2_20
jnp .LBB2_21
.LBB2_20: # in Loop: Header=BB2_19 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
xorl %ebp, %ebp
jmp .LBB2_21
.LBB2_22:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
testl %ebp, %ebp
je .LBB2_24
# %bb.23:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_24:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z17cpu_backpropagatePfiiPS_S_S_ # -- Begin function _Z17cpu_backpropagatePfiiPS_S_S_
.p2align 4, 0x90
.type _Z17cpu_backpropagatePfiiPS_S_S_,@function
_Z17cpu_backpropagatePfiiPS_S_S_: # @_Z17cpu_backpropagatePfiiPS_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, %rbx
movl %esi, %ebp
movq %rdi, %rcx
movl %esi, %edi
movl %edx, %esi
movq %r9, %rdx
callq _Z18mull_backpropagateiiPfS_
movq %rax, %r15
movslq %ebp, %r12
leaq (,%r12,4), %rax
testl %r12d, %r12d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
testl %r12d, %r12d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r15,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rdx,4), %xmm0
movss %xmm0, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_2
.LBB3_3: # %_Z16hadamard_productiPfS_.exit
movq %rax, (%rbx)
movq %r15, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.Lfunc_end3:
.size _Z17cpu_backpropagatePfiiPS_S_S_, .Lfunc_end3-_Z17cpu_backpropagatePfiiPS_S_S_
.cfi_endproc
# -- End function
.globl _Z16hadamard_productiPfS_ # -- Begin function _Z16hadamard_productiPfS_
.p2align 4, 0x90
.type _Z16hadamard_productiPfS_,@function
_Z16hadamard_productiPfS_: # @_Z16hadamard_productiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,4), %rax
testl %r15d, %r15d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
testl %r15d, %r15d
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rbx,%rdx,4), %xmm0
movss %xmm0, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16hadamard_productiPfS_, .Lfunc_end4-_Z16hadamard_productiPfS_
.cfi_endproc
# -- End function
.globl _Z18mull_backpropagateiiPfS_ # -- Begin function _Z18mull_backpropagateiiPfS_
.p2align 4, 0x90
.type _Z18mull_backpropagateiiPfS_,@function
_Z18mull_backpropagateiiPfS_: # @_Z18mull_backpropagateiiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r14
movl %esi, %ebp
movl %edi, %r13d
movslq %edi, %r15
leaq (,%r15,4), %rdi
testl %r15d, %r15d
movq $-1, %rax
movq $-1, (%rsp) # 8-byte Folded Spill
cmovsq %rax, %rdi
callq _Znam
movq %rax, %r12
testl %r15d, %r15d
jle .LBB5_10
# %bb.1: # %.lr.ph24
movslq %ebp, %rax
leaq (,%rax,4), %rdx
testl %eax, %eax
movq (%rsp), %rcx # 8-byte Reload
movq %rdx, 16(%rsp) # 8-byte Spill
cmovnsq %rdx, %rcx
movq %rcx, (%rsp) # 8-byte Spill
movl %eax, %r15d
movl %r13d, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_2 Depth=1
movq %rax, %rdi
callq _ZdaPv
incq %r13
addq 16(%rsp), %r14 # 8-byte Folded Reload
cmpq 8(%rsp), %r13 # 8-byte Folded Reload
je .LBB5_10
.LBB5_2: # =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_7 Depth 2
movq (%rsp), %rdi # 8-byte Reload
callq _Znam
testl %ebp, %ebp
jle .LBB5_5
# %bb.3: # %.lr.ph.i.preheader
# in Loop: Header=BB5_2 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rbx,%rcx,4), %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq %rcx, %r15
jne .LBB5_4
.LBB5_5: # %_Z16hadamard_productiPfS_.exit
# in Loop: Header=BB5_2 Depth=1
movl $0, (%r12,%r13,4)
testl %ebp, %ebp
jle .LBB5_9
# %bb.6: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_7: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rax,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %r15
jne .LBB5_7
# %bb.8: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
movss %xmm0, (%r12,%r13,4)
jmp .LBB5_9
.LBB5_10: # %._crit_edge25
movq %r12, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z18mull_backpropagateiiPfS_, .Lfunc_end5-_Z18mull_backpropagateiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13backpropagatePfiiS_S_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13backpropagatePfiiS_S_iiS_,@object # @_Z13backpropagatePfiiS_S_iiS_
.section .rodata,"a",@progbits
.globl _Z13backpropagatePfiiS_S_iiS_
.p2align 3, 0x0
_Z13backpropagatePfiiS_S_iiS_:
.quad _Z28__device_stub__backpropagatePfiiS_S_iiS_
.size _Z13backpropagatePfiiS_S_iiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR in a, cpu = %f, gpu = %f\n"
.size .L.str, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13backpropagatePfiiS_S_iiS_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "SUCCESS "
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__backpropagatePfiiS_S_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13backpropagatePfiiS_S_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001876f1_00000000-6_backpropagate.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3719:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3719:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sigmoidRf
.type _Z7sigmoidRf, @function
_Z7sigmoidRf:
.LFB3708:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3708:
.size _Z7sigmoidRf, .-_Z7sigmoidRf
.globl _Z22hadamard_product_smallPfS_S_iii
.type _Z22hadamard_product_smallPfS_S_iii, @function
_Z22hadamard_product_smallPfS_S_iii:
.LFB3709:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3709:
.size _Z22hadamard_product_smallPfS_S_iii, .-_Z22hadamard_product_smallPfS_S_iii
.globl _Z15array_sum_smallPfRfii
.type _Z15array_sum_smallPfRfii, @function
_Z15array_sum_smallPfRfii:
.LFB3710:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3710:
.size _Z15array_sum_smallPfRfii, .-_Z15array_sum_smallPfRfii
.globl _Z23backpropagate_some_colsPfiiS_S_iiS_
.type _Z23backpropagate_some_colsPfiiS_S_iiS_, @function
_Z23backpropagate_some_colsPfiiS_S_iiS_:
.LFB3711:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3711:
.size _Z23backpropagate_some_colsPfiiS_S_iiS_, .-_Z23backpropagate_some_colsPfiiS_S_iiS_
.globl _Z10initializePfjf
.type _Z10initializePfjf, @function
_Z10initializePfjf:
.LFB3712:
.cfi_startproc
endbr64
testl %esi, %esi
je .L11
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rdx
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE3712:
.size _Z10initializePfjf, .-_Z10initializePfjf
.globl _Z16hadamard_productiPfS_
.type _Z16hadamard_productiPfS_, @function
_Z16hadamard_productiPfS_:
.LFB3714:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movslq %edi, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L16
movl %edi, %r13d
movq %rsi, %rbp
movq %rdx, %r12
salq $2, %rbx
movq %rbx, %rdi
call _Znam@PLT
movl $0, %edx
testl %r13d, %r13d
jle .L15
.L17:
movss 0(%rbp,%rdx), %xmm0
mulss (%r12,%rdx), %xmm0
movss %xmm0, (%rax,%rdx)
addq $4, %rdx
cmpq %rdx, %rbx
jne .L17
.L15:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3714:
.size _Z16hadamard_productiPfS_, .-_Z16hadamard_productiPfS_
.globl _Z18mull_backpropagateiiPfS_
.type _Z18mull_backpropagateiiPfS_, @function
_Z18mull_backpropagateiiPfS_:
.LFB3715:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movslq %edi, %r14
movabsq $2305843009213693950, %rax
cmpq %r14, %rax
jb .L24
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, %rbp
movq %rcx, %r15
salq $2, %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L23
movslq %r12d, %r13
salq $2, %r13
movq 8(%rsp), %rax
movq %rax, %rbx
addq %rax, %r14
jmp .L30
.L24:
call __cxa_throw_bad_array_new_length@PLT
.L29:
addq %r13, %rbp
addq $4, %rbx
cmpq %r14, %rbx
je .L23
.L30:
movq %r15, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call _Z16hadamard_productiPfS_
movq %rbx, %rcx
movl $0x00000000, (%rbx)
testl %r12d, %r12d
jle .L27
movq %rax, %rdx
leaq (%rax,%r13), %rsi
.L28:
movss (%rcx), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rdx
cmpq %rsi, %rdx
jne .L28
.L27:
testq %rax, %rax
je .L29
movq %rax, %rdi
call _ZdaPv@PLT
jmp .L29
.L23:
movq 8(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3715:
.size _Z18mull_backpropagateiiPfS_, .-_Z18mull_backpropagateiiPfS_
.globl _Z17cpu_backpropagatePfiiPS_S_S_
.type _Z17cpu_backpropagatePfiiPS_S_S_, @function
_Z17cpu_backpropagatePfiiPS_S_S_:
.LFB3716:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %esi, %ebp
movl %edx, %esi
movq %rcx, %r12
movq %r8, %r13
movq %r9, %rdx
movq %rdi, %rcx
movl %ebp, %edi
call _Z18mull_backpropagateiiPfS_
movq %rax, %rbx
movq %r13, %rdx
movq %rax, %rsi
movl %ebp, %edi
call _Z16hadamard_productiPfS_
movq %rax, (%r12)
testq %rbx, %rbx
je .L34
movq %rbx, %rdi
call _ZdaPv@PLT
.L34:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3716:
.size _Z17cpu_backpropagatePfiiPS_S_S_, .-_Z17cpu_backpropagatePfiiPS_S_S_
.globl _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
.type _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_, @function
_Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_:
.LFB3741:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13backpropagatePfiiS_S_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3741:
.size _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_, .-_Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
.globl _Z13backpropagatePfiiS_S_iiS_
.type _Z13backpropagatePfiiS_S_iiS_, @function
_Z13backpropagatePfiiS_S_iiS_:
.LFB3742:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3742:
.size _Z13backpropagatePfiiS_S_iiS_, .-_Z13backpropagatePfiiS_S_iiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "ERROR in a, cpu = %f, gpu = %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "SUCCESS \n"
.text
.globl main
.type main, @function
main:
.LFB3713:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $93960, %edi
call _Znam@PLT
movq %rax, %rbp
movl $120, %edi
call _Znam@PLT
movq %rax, %r12
movl $3132, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $3132, %edi
call _Znam@PLT
movq %rax, %rbx
movl $3132, %edi
call _Znam@PLT
movq %rax, %r13
leaq 120(%rbp), %rdx
leaq 94080(%rbp), %rcx
movss .LC1(%rip), %xmm0
jmp .L46
.L59:
addq $120, %rdx
cmpq %rcx, %rdx
je .L48
.L46:
leaq -120(%rdx), %rax
.L47:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L47
jmp .L59
.L48:
movss .LC2(%rip), %xmm0
movl $30, %esi
movq %r12, %rdi
call _Z10initializePfjf
movss .LC3(%rip), %xmm0
movl $783, %esi
movq %r13, %rdi
call _Z10initializePfjf
leaq 16(%rsp), %rdi
movl $93960, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $120, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $3132, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $3132, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $93960, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $120, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $3132, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $44000, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L49:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $3132, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rcx
movq %rbp, %r9
movq %r13, %r8
movl $30, %edx
movl $783, %esi
movq %r12, %rdi
call _Z17cpu_backpropagatePfiiPS_S_S_
movl $0, %ebp
movl $1, %r13d
leaq .LC4(%rip), %r12
jmp .L52
.L60:
pushq 40(%rsp)
.cfi_def_cfa_offset 136
pushq $83
.cfi_def_cfa_offset 144
movl $7, %r9d
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movl $30, %edx
movl $100, %esi
movq 48(%rsp), %rdi
call _Z43__device_stub__Z13backpropagatePfiiS_S_iiS_PfiiS_S_iiS_
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L49
.L55:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %r13d
.L50:
addq $4, %rbp
cmpq $3132, %rbp
je .L61
.L52:
movq 8(%rsp), %rax
movss (%rax,%rbp), %xmm0
movss (%rbx,%rbp), %xmm1
ucomiss %xmm1, %xmm0
jp .L55
je .L50
jmp .L55
.L61:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %r13d, %r13d
jne .L62
.L53:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L53
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3713:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z13backpropagatePfiiS_S_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3744:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13backpropagatePfiiS_S_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3744:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1067030938
.align 4
.LC2:
.long 1069547520
.align 4
.LC3:
.long 1070386381
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "backpropagate.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__backpropagatePfiiS_S_iiS_ # -- Begin function _Z28__device_stub__backpropagatePfiiS_S_iiS_
.p2align 4, 0x90
.type _Z28__device_stub__backpropagatePfiiS_S_iiS_,@function
_Z28__device_stub__backpropagatePfiiS_S_iiS_: # @_Z28__device_stub__backpropagatePfiiS_S_iiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13backpropagatePfiiS_S_iiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__backpropagatePfiiS_S_iiS_, .Lfunc_end0-_Z28__device_stub__backpropagatePfiiS_S_iiS_
.cfi_endproc
# -- End function
.globl _Z10initializePfjf # -- Begin function _Z10initializePfjf
.p2align 4, 0x90
.type _Z10initializePfjf,@function
_Z10initializePfjf: # @_Z10initializePfjf
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10initializePfjf, .Lfunc_end1-_Z10initializePfjf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $93960, %edi # imm = 0x16F08
callq _Znam
movq %rax, %r15
movl $120, %edi
callq _Znam
movq %rax, %r12
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %rbx
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %r14
xorl %eax, %eax
movq %r15, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1067030938, (%rcx,%rdx,4) # imm = 0x3F99999A
incq %rdx
cmpq $30, %rdx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $120, %rcx
cmpq $783, %rax # imm = 0x30F
jne .LBB2_1
# %bb.4: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1069547520, (%r12,%rax,4) # imm = 0x3FC00000
incq %rax
cmpq $30, %rax
jne .LBB2_5
# %bb.6: # %.lr.ph.i71.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i71
# =>This Inner Loop Header: Depth=1
movl $1070386381, (%r14,%rax,4) # imm = 0x3FCCCCCD
incq %rax
cmpq $783, %rax # imm = 0x30F
jne .LBB2_7
# %bb.8: # %_Z10initializePfjf.exit75
leaq 16(%rsp), %rdi
movl $93960, %esi # imm = 0x16F08
callq hipMalloc
leaq 8(%rsp), %rdi
movl $120, %esi
callq hipMalloc
movq %rsp, %rdi
movl $3132, %esi # imm = 0xC3C
callq hipMalloc
leaq 40(%rsp), %rdi
movl $3132, %esi # imm = 0xC3C
callq hipMalloc
movq 16(%rsp), %rdi
movl $93960, %edx # imm = 0x16F08
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $120, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $3132, %edx # imm = 0xC3C
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 92(%rdi), %rdx
movl $44000, %r8d # imm = 0xABE0
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rax, 120(%rsp)
movl $100, 36(%rsp)
movl $30, 32(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $7, 28(%rsp)
movl $83, 24(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13backpropagatePfiiS_S_iiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $3132, %edx # imm = 0xC3C
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_11: # =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
# Child Loop BB2_14 Depth 2
movl $120, %edi
callq _Znam
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_12: # %.lr.ph.i.i76
# Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r12,%rcx,4), %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $30, %rcx
jne .LBB2_12
# %bb.13: # %_Z16hadamard_productiPfS_.exit.i
# in Loop: Header=BB2_11 Depth=1
movl $0, (%r13,%rbp,4)
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rax,%rcx,4), %xmm0
incq %rcx
cmpq $30, %rcx
jne .LBB2_14
# %bb.15: # %._crit_edge.i
# in Loop: Header=BB2_11 Depth=1
movss %xmm0, (%r13,%rbp,4)
movq %rax, %rdi
callq _ZdaPv
incq %rbp
addq $120, %r15
cmpq $783, %rbp # imm = 0x30F
jne .LBB2_11
# %bb.16: # %_Z18mull_backpropagateiiPfS_.exit
movl $3132, %edi # imm = 0xC3C
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_17: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $783, %rax # imm = 0x30F
jne .LBB2_17
# %bb.18: # %_Z17cpu_backpropagatePfiiPS_S_S_.exit
movq %r13, %rdi
callq _ZdaPv
movl $1, %ebp
xorl %r14d, %r14d
jmp .LBB2_19
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_19 Depth=1
incq %r14
cmpq $783, %r14 # imm = 0x30F
je .LBB2_22
.LBB2_19: # =>This Inner Loop Header: Depth=1
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rbx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB2_20
jnp .LBB2_21
.LBB2_20: # in Loop: Header=BB2_19 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
xorl %ebp, %ebp
jmp .LBB2_21
.LBB2_22:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
testl %ebp, %ebp
je .LBB2_24
# %bb.23:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_24:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z17cpu_backpropagatePfiiPS_S_S_ # -- Begin function _Z17cpu_backpropagatePfiiPS_S_S_
.p2align 4, 0x90
.type _Z17cpu_backpropagatePfiiPS_S_S_,@function
_Z17cpu_backpropagatePfiiPS_S_S_: # @_Z17cpu_backpropagatePfiiPS_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, %rbx
movl %esi, %ebp
movq %rdi, %rcx
movl %esi, %edi
movl %edx, %esi
movq %r9, %rdx
callq _Z18mull_backpropagateiiPfS_
movq %rax, %r15
movslq %ebp, %r12
leaq (,%r12,4), %rax
testl %r12d, %r12d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
testl %r12d, %r12d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r15,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rdx,4), %xmm0
movss %xmm0, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_2
.LBB3_3: # %_Z16hadamard_productiPfS_.exit
movq %rax, (%rbx)
movq %r15, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.Lfunc_end3:
.size _Z17cpu_backpropagatePfiiPS_S_S_, .Lfunc_end3-_Z17cpu_backpropagatePfiiPS_S_S_
.cfi_endproc
# -- End function
.globl _Z16hadamard_productiPfS_ # -- Begin function _Z16hadamard_productiPfS_
.p2align 4, 0x90
.type _Z16hadamard_productiPfS_,@function
_Z16hadamard_productiPfS_: # @_Z16hadamard_productiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,4), %rax
testl %r15d, %r15d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
testl %r15d, %r15d
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rbx,%rdx,4), %xmm0
movss %xmm0, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16hadamard_productiPfS_, .Lfunc_end4-_Z16hadamard_productiPfS_
.cfi_endproc
# -- End function
.globl _Z18mull_backpropagateiiPfS_ # -- Begin function _Z18mull_backpropagateiiPfS_
.p2align 4, 0x90
.type _Z18mull_backpropagateiiPfS_,@function
_Z18mull_backpropagateiiPfS_: # @_Z18mull_backpropagateiiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r14
movl %esi, %ebp
movl %edi, %r13d
movslq %edi, %r15
leaq (,%r15,4), %rdi
testl %r15d, %r15d
movq $-1, %rax
movq $-1, (%rsp) # 8-byte Folded Spill
cmovsq %rax, %rdi
callq _Znam
movq %rax, %r12
testl %r15d, %r15d
jle .LBB5_10
# %bb.1: # %.lr.ph24
movslq %ebp, %rax
leaq (,%rax,4), %rdx
testl %eax, %eax
movq (%rsp), %rcx # 8-byte Reload
movq %rdx, 16(%rsp) # 8-byte Spill
cmovnsq %rdx, %rcx
movq %rcx, (%rsp) # 8-byte Spill
movl %eax, %r15d
movl %r13d, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_2 Depth=1
movq %rax, %rdi
callq _ZdaPv
incq %r13
addq 16(%rsp), %r14 # 8-byte Folded Reload
cmpq 8(%rsp), %r13 # 8-byte Folded Reload
je .LBB5_10
.LBB5_2: # =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_7 Depth 2
movq (%rsp), %rdi # 8-byte Reload
callq _Znam
testl %ebp, %ebp
jle .LBB5_5
# %bb.3: # %.lr.ph.i.preheader
# in Loop: Header=BB5_2 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rbx,%rcx,4), %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq %rcx, %r15
jne .LBB5_4
.LBB5_5: # %_Z16hadamard_productiPfS_.exit
# in Loop: Header=BB5_2 Depth=1
movl $0, (%r12,%r13,4)
testl %ebp, %ebp
jle .LBB5_9
# %bb.6: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_7: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rax,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %r15
jne .LBB5_7
# %bb.8: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
movss %xmm0, (%r12,%r13,4)
jmp .LBB5_9
.LBB5_10: # %._crit_edge25
movq %r12, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z18mull_backpropagateiiPfS_, .Lfunc_end5-_Z18mull_backpropagateiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13backpropagatePfiiS_S_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13backpropagatePfiiS_S_iiS_,@object # @_Z13backpropagatePfiiS_S_iiS_
.section .rodata,"a",@progbits
.globl _Z13backpropagatePfiiS_S_iiS_
.p2align 3, 0x0
_Z13backpropagatePfiiS_S_iiS_:
.quad _Z28__device_stub__backpropagatePfiiS_S_iiS_
.size _Z13backpropagatePfiiS_S_iiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR in a, cpu = %f, gpu = %f\n"
.size .L.str, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13backpropagatePfiiS_S_iiS_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "SUCCESS "
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__backpropagatePfiiS_S_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13backpropagatePfiiS_S_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cooperative_groups.h>
#include <stdio.h>
#include "cuda.h"
#include "cuda_runtime.h"
#include <iostream>
#define ARRAYSIZE 10000
#define BLOCKSIZE 256
using namespace cooperative_groups;
// Basic reduction code found in the presentation; going to test on a variety of
// thread groups
__device__ float threadSum(float *x, int elements)
{
float thread_sum = 0.0;
int id = blockIdx.x*blockDim.x + threadIdx.x;
int step = blockDim.x*gridDim.x;
for (int i = id; i < elements / step; i += step)
{
thread_sum += x[i];
}
return thread_sum;
}
template <unsigned size>
__device__ float reduce(thread_block_tile<size> g, float val)
{
for (int i = g.size() / 2; i > 0; i /= 2) {
val += g.shfl_down(val, i);
}
return val;
}
// use this kernel to get sum
__global__ void sum_kernel(float *x, int elements, float *val)
{
float thread_sum = threadSum(x, elements);
thread_block_tile<32> g = tiled_partition<32>(this_thread_block());
float tile_sum = reduce<32>(g, thread_sum);
// first block and first warp in block
if (g.thread_rank() == 0)
{
atomicAdd(val, tile_sum);
}
}
int main(void)
{
float *x, *devX, *devSum; // pointers for local and device arrays
x = new float[ARRAYSIZE]; // make x the specified size
float local_sum = 0.0;
int grid_size = (ARRAYSIZE + BLOCKSIZE - 1)/BLOCKSIZE;
// compute sum of all array elements and fill x with the data where the ith
// element is i
for (int i = 0; i < ARRAYSIZE; i++)
{
x[i] = i/1000;
local_sum += i/1000;
}
// create an array on the device that contains X and copy over the data
cudaMalloc((void**)&devX, ARRAYSIZE*sizeof(float));
cudaMalloc((void**)&devSum, sizeof(float));
cudaMemcpy(devX, x, ARRAYSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(devSum, &local_sum, sizeof(float), cudaMemcpyHostToDevice);
// Setup timers to test different configurations
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start); // start timer
// run the kernel
sum_kernel<<<grid_size, BLOCKSIZE>>>(devX, ARRAYSIZE, devSum);
cudaEventRecord(stop); // stop timing
// get the runtime
cudaEventSynchronize(stop);
float milliseconds = 0.0;
cudaEventElapsedTime(&milliseconds, start, stop);
float device_sum = 0.0;
cudaMemcpy(&device_sum, devSum, sizeof(float), cudaMemcpyDeviceToHost); // print the runtime
std::cout << milliseconds << " milliseconds for parallel run" << std::endl;
std::cout << "Host sum: " << local_sum << std::endl;
std::cout << "Device sum: " << device_sum << std::endl;
// free memory
cudaFree(devX);
cudaFree(devSum);
delete[] x;
return 0;
}
|
code for sm_80
Function : _Z10sum_kernelPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ IABS R8, c[0x0][0x168] ; /* 0x00005a0000087a13 */
/* 0x000fe20000000000 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x5f0 ; /* 0x000005a000007945 */
/* 0x000fe20003800000 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*0060*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fc800000001ff */
/*0070*/ IABS R5, R0.reuse ; /* 0x0000000000057213 */
/* 0x080fe40000000000 */
/*0080*/ IABS R9, R0 ; /* 0x0000000000097213 */
/* 0x000fe40000000000 */
/*0090*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc40007ffe0ff */
/*00c0*/ IADD3 R4, RZ, -R9, RZ ; /* 0x80000009ff047210 */
/* 0x000fc80007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00f0*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*0130*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0140*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fe200078e00ff */
/*0150*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e260000002100 */
/*0160*/ IMAD R4, R3, R4, R6 ; /* 0x0000000403047224 */
/* 0x000fca00078e0206 */
/*0170*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0180*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*0190*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f26070 */
/*01b0*/ LOP3.LUT R4, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000047a12 */
/* 0x000fe400078e3cff */
/*01c0*/ LOP3.LUT R5, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff057212 */
/* 0x000fe400078e33ff */
/*01d0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f06270 */
/*01e0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0200*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R3, R7, c[0x0][0x0], R2 ; /* 0x0000000007037a24 */
/* 0x001fc800078e0202 */
/*0220*/ @!P0 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff048224 */
/* 0x000fca00078e0a04 */
/*0230*/ SEL R4, R5, R4, !P1 ; /* 0x0000000405047207 */
/* 0x000fc80004800000 */
/*0240*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f06270 */
/*0250*/ @P0 BRA 0x5e0 ; /* 0x0000038000000947 */
/* 0x000fea0003800000 */
/*0260*/ I2F.U32.RP R8, R0 ; /* 0x0000000000087306 */
/* 0x000e220000209000 */
/*0270*/ IADD3 R6, R0, R3, RZ ; /* 0x0000000300067210 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*0290*/ BSSY B1, 0x4c0 ; /* 0x0000022000017945 */
/* 0x000fe20003800000 */
/*02a0*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe40000000f00 */
/*02b0*/ LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff097212 */
/* 0x000fe200078e33ff */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*02d0*/ IADD3 R9, R9, R4, R0 ; /* 0x0000000409097210 */
/* 0x000fe20007ffe000 */
/*02e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*02f0*/ IADD3 R7, R8, 0xffffffe, RZ ; /* 0x0ffffffe08077810 */
/* 0x001fcc0007ffe0ff */
/*0300*/ F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000021f000 */
/*0310*/ IMAD R11, R11, R7, RZ ; /* 0x000000070b0b7224 */
/* 0x001fc800078e02ff */
/*0320*/ IMAD.HI.U32 R6, R7, R11, R6 ; /* 0x0000000b07067227 */
/* 0x000fcc00078e0006 */
/*0330*/ IMAD.HI.U32 R6, R6, R9, RZ ; /* 0x0000000906067227 */
/* 0x000fca00078e00ff */
/*0340*/ IADD3 R8, -R6, RZ, RZ ; /* 0x000000ff06087210 */
/* 0x000fca0007ffe1ff */
/*0350*/ IMAD R9, R0, R8, R9 ; /* 0x0000000800097224 */
/* 0x000fca00078e0209 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f06070 */
/*0370*/ @P0 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109090824 */
/* 0x000fe200078e0a00 */
/*0380*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*0390*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*03a0*/ ISETP.GE.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f26070 */
/*03b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ SEL R6, R5, R6, !P0 ; /* 0x0000000605067207 */
/* 0x000fc80004000000 */
/*03d0*/ IADD3 R5, R6.reuse, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x040fe40007ffe0ff */
/*03e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*03f0*/ LOP3.LUT P0, R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fda000780c0ff */
/*0400*/ @!P0 BRA 0x4b0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0420*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fc600000001ff */
/*0430*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0440*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0450*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fc600078e0203 */
/*0470*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0480*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*0490*/ FADD R14, R9, R14 ; /* 0x0000000e090e7221 */
/* 0x004fd00000000000 */
/*04a0*/ @P0 BRA 0x440 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*04b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04c0*/ @!P1 BRA 0x5e0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*04d0*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fcc00078e0206 */
/*04f0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe400078e0206 */
/*0500*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0510*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0208 */
/*0520*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee8000c1e1900 */
/*0530*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc400078e020a */
/*0540*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1900 */
/*0560*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0570*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0580*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe20003f06270 */
/*0590*/ FADD R14, R7, R14 ; /* 0x0000000e070e7221 */
/* 0x004fc80000000000 */
/*05a0*/ FADD R14, R14, R9 ; /* 0x000000090e0e7221 */
/* 0x008fc80000000000 */
/*05b0*/ FADD R14, R14, R11 ; /* 0x0000000b0e0e7221 */
/* 0x010fc80000000000 */
/*05c0*/ FADD R14, R14, R13 ; /* 0x0000000d0e0e7221 */
/* 0x020fe20000000000 */
/*05d0*/ @!P0 BRA 0x4d0 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ SHFL.DOWN PT, R3, R14, 0x10, 0x1f ; /* 0x0a001f000e037f89 */
/* 0x000e2800000e0000 */
/*0600*/ S2R R9, SR_TID.Z ; /* 0x0000000000097919 */
/* 0x000e680000002300 */
/*0610*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002200 */
/*0620*/ FADD R3, R3, R14 ; /* 0x0000000e03037221 */
/* 0x001fca0000000000 */
/*0630*/ SHFL.DOWN PT, R0, R3, 0x8, 0x1f ; /* 0x09001f0003007f89 */
/* 0x000e2200000e0000 */
/*0640*/ IMAD R9, R9, c[0x0][0x4], R6 ; /* 0x0000010009097a24 */
/* 0x002fc800078e0206 */
/*0650*/ IMAD R9, R9, c[0x0][0x0], R2 ; /* 0x0000000009097a24 */
/* 0x000fca00078e0202 */
/*0660*/ LOP3.LUT P0, RZ, R9, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f09ff7812 */
/* 0x000fe2000780c0ff */
/*0670*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x001fca0000000000 */
/*0680*/ SHFL.DOWN PT, R5, R0, 0x4, 0x1f ; /* 0x08801f0000057f89 */
/* 0x000e2400000e0000 */
/*0690*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x001fca0000000000 */
/*06a0*/ SHFL.DOWN PT, R4, R5, 0x2, 0x1f ; /* 0x08401f0005047f89 */
/* 0x000e2400000e0000 */
/*06b0*/ FADD R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x001fca0000000000 */
/*06c0*/ SHFL.DOWN PT, R7, R4, 0x1, 0x1f ; /* 0x08201f0004077f89 */
/* 0x000e2400000e0000 */
/*06d0*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x001fe20000000000 */
/*06e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0700*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0710*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e784 */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cooperative_groups.h>
#include <stdio.h>
#include "cuda.h"
#include "cuda_runtime.h"
#include <iostream>
#define ARRAYSIZE 10000
#define BLOCKSIZE 256
using namespace cooperative_groups;
// Basic reduction code found in the presentation; going to test on a variety of
// thread groups
__device__ float threadSum(float *x, int elements)
{
float thread_sum = 0.0;
int id = blockIdx.x*blockDim.x + threadIdx.x;
int step = blockDim.x*gridDim.x;
for (int i = id; i < elements / step; i += step)
{
thread_sum += x[i];
}
return thread_sum;
}
template <unsigned size>
__device__ float reduce(thread_block_tile<size> g, float val)
{
for (int i = g.size() / 2; i > 0; i /= 2) {
val += g.shfl_down(val, i);
}
return val;
}
// use this kernel to get sum
__global__ void sum_kernel(float *x, int elements, float *val)
{
float thread_sum = threadSum(x, elements);
thread_block_tile<32> g = tiled_partition<32>(this_thread_block());
float tile_sum = reduce<32>(g, thread_sum);
// first block and first warp in block
if (g.thread_rank() == 0)
{
atomicAdd(val, tile_sum);
}
}
int main(void)
{
float *x, *devX, *devSum; // pointers for local and device arrays
x = new float[ARRAYSIZE]; // make x the specified size
float local_sum = 0.0;
int grid_size = (ARRAYSIZE + BLOCKSIZE - 1)/BLOCKSIZE;
// compute sum of all array elements and fill x with the data where the ith
// element is i
for (int i = 0; i < ARRAYSIZE; i++)
{
x[i] = i/1000;
local_sum += i/1000;
}
// create an array on the device that contains X and copy over the data
cudaMalloc((void**)&devX, ARRAYSIZE*sizeof(float));
cudaMalloc((void**)&devSum, sizeof(float));
cudaMemcpy(devX, x, ARRAYSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(devSum, &local_sum, sizeof(float), cudaMemcpyHostToDevice);
// Setup timers to test different configurations
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start); // start timer
// run the kernel
sum_kernel<<<grid_size, BLOCKSIZE>>>(devX, ARRAYSIZE, devSum);
cudaEventRecord(stop); // stop timing
// get the runtime
cudaEventSynchronize(stop);
float milliseconds = 0.0;
cudaEventElapsedTime(&milliseconds, start, stop);
float device_sum = 0.0;
cudaMemcpy(&device_sum, devSum, sizeof(float), cudaMemcpyDeviceToHost); // print the runtime
std::cout << milliseconds << " milliseconds for parallel run" << std::endl;
std::cout << "Host sum: " << local_sum << std::endl;
std::cout << "Device sum: " << device_sum << std::endl;
// free memory
cudaFree(devX);
cudaFree(devSum);
delete[] x;
return 0;
}
|
.file "tmpxft_0013c77a_00000000-6_reduction_tests.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6871:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6871:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9threadSumPfi
.type _Z9threadSumPfi, @function
_Z9threadSumPfi:
.LFB6866:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6866:
.size _Z9threadSumPfi, .-_Z9threadSumPfi
.globl _Z33__device_stub__Z10sum_kernelPfiS_PfiS_
.type _Z33__device_stub__Z10sum_kernelPfiS_PfiS_, @function
_Z33__device_stub__Z10sum_kernelPfiS_PfiS_:
.LFB6893:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sum_kernelPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6893:
.size _Z33__device_stub__Z10sum_kernelPfiS_PfiS_, .-_Z33__device_stub__Z10sum_kernelPfiS_PfiS_
.globl _Z10sum_kernelPfiS_
.type _Z10sum_kernelPfiS_, @function
_Z10sum_kernelPfiS_:
.LFB6894:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10sum_kernelPfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6894:
.size _Z10sum_kernelPfiS_, .-_Z10sum_kernelPfiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " milliseconds for parallel run"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Host sum: "
.LC3:
.string "Device sum: "
.text
.globl main
.type main, @function
main:
.LFB6868:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $40000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $0, %edx
pxor %xmm1, %xmm1
.L14:
movslq %edx, %rax
imulq $274877907, %rax, %rax
sarq $38, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rdx,4)
addss %xmm0, %xmm1
addq $1, %rdx
cmpq $10000, %rdx
jne .L14
movss %xmm1, 12(%rsp)
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 48(%rsp)
leaq 48(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0x00000000, 60(%rsp)
leaq 60(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movl $10000, %esi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z10sum_kernelPfiS_PfiS_
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6868:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10sum_kernelPfiS_"
.section .rodata.str1.8
.align 8
.LC5:
.string "_ZN49_INTERNAL_5dfde221_18_reduction_tests_cu_2ba847b74cuda3std3__419piecewise_constructE"
.align 8
.LC6:
.string "_ZN49_INTERNAL_5dfde221_18_reduction_tests_cu_2ba847b74cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC7:
.string "_ZN49_INTERNAL_5dfde221_18_reduction_tests_cu_2ba847b74cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6896:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_kernelPfiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6896:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cooperative_groups.h>
#include <stdio.h>
#include "cuda.h"
#include "cuda_runtime.h"
#include <iostream>
#define ARRAYSIZE 10000
#define BLOCKSIZE 256
using namespace cooperative_groups;
// Basic reduction code found in the presentation; going to test on a variety of
// thread groups
__device__ float threadSum(float *x, int elements)
{
float thread_sum = 0.0;
int id = blockIdx.x*blockDim.x + threadIdx.x;
int step = blockDim.x*gridDim.x;
for (int i = id; i < elements / step; i += step)
{
thread_sum += x[i];
}
return thread_sum;
}
template <unsigned size>
__device__ float reduce(thread_block_tile<size> g, float val)
{
for (int i = g.size() / 2; i > 0; i /= 2) {
val += g.shfl_down(val, i);
}
return val;
}
// use this kernel to get sum
__global__ void sum_kernel(float *x, int elements, float *val)
{
float thread_sum = threadSum(x, elements);
thread_block_tile<32> g = tiled_partition<32>(this_thread_block());
float tile_sum = reduce<32>(g, thread_sum);
// first block and first warp in block
if (g.thread_rank() == 0)
{
atomicAdd(val, tile_sum);
}
}
int main(void)
{
float *x, *devX, *devSum; // pointers for local and device arrays
x = new float[ARRAYSIZE]; // make x the specified size
float local_sum = 0.0;
int grid_size = (ARRAYSIZE + BLOCKSIZE - 1)/BLOCKSIZE;
// compute sum of all array elements and fill x with the data where the ith
// element is i
for (int i = 0; i < ARRAYSIZE; i++)
{
x[i] = i/1000;
local_sum += i/1000;
}
// create an array on the device that contains X and copy over the data
cudaMalloc((void**)&devX, ARRAYSIZE*sizeof(float));
cudaMalloc((void**)&devSum, sizeof(float));
cudaMemcpy(devX, x, ARRAYSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(devSum, &local_sum, sizeof(float), cudaMemcpyHostToDevice);
// Setup timers to test different configurations
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start); // start timer
// run the kernel
sum_kernel<<<grid_size, BLOCKSIZE>>>(devX, ARRAYSIZE, devSum);
cudaEventRecord(stop); // stop timing
// get the runtime
cudaEventSynchronize(stop);
float milliseconds = 0.0;
cudaEventElapsedTime(&milliseconds, start, stop);
float device_sum = 0.0;
cudaMemcpy(&device_sum, devSum, sizeof(float), cudaMemcpyDeviceToHost); // print the runtime
std::cout << milliseconds << " milliseconds for parallel run" << std::endl;
std::cout << "Host sum: " << local_sum << std::endl;
std::cout << "Device sum: " << device_sum << std::endl;
// free memory
cudaFree(devX);
cudaFree(devSum);
delete[] x;
return 0;
}
|
#include <hip/hip_cooperative_groups.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#define ARRAYSIZE 10000
#define BLOCKSIZE 256
using namespace cooperative_groups;
// Basic reduction code found in the presentation; going to test on a variety of
// thread groups
__device__ float threadSum(float *x, int elements)
{
float thread_sum = 0.0;
int id = blockIdx.x*blockDim.x + threadIdx.x;
int step = blockDim.x*gridDim.x;
for (int i = id; i < elements / step; i += step)
{
thread_sum += x[i];
}
return thread_sum;
}
template <unsigned size>
__device__ float reduce(thread_block_tile<size> g, float val)
{
for (int i = g.size() / 2; i > 0; i /= 2) {
val += g.shfl_down(val, i);
}
return val;
}
// use this kernel to get sum
__global__ void sum_kernel(float *x, int elements, float *val)
{
float thread_sum = threadSum(x, elements);
thread_block_tile<32> g = tiled_partition<32>(this_thread_block());
float tile_sum = reduce<32>(g, thread_sum);
// first block and first warp in block
if (g.thread_rank() == 0)
{
atomicAdd(val, tile_sum);
}
}
int main(void)
{
float *x, *devX, *devSum; // pointers for local and device arrays
x = new float[ARRAYSIZE]; // make x the specified size
float local_sum = 0.0;
int grid_size = (ARRAYSIZE + BLOCKSIZE - 1)/BLOCKSIZE;
// compute sum of all array elements and fill x with the data where the ith
// element is i
for (int i = 0; i < ARRAYSIZE; i++)
{
x[i] = i/1000;
local_sum += i/1000;
}
// create an array on the device that contains X and copy over the data
hipMalloc((void**)&devX, ARRAYSIZE*sizeof(float));
hipMalloc((void**)&devSum, sizeof(float));
hipMemcpy(devX, x, ARRAYSIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(devSum, &local_sum, sizeof(float), hipMemcpyHostToDevice);
// Setup timers to test different configurations
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start); // start timer
// run the kernel
sum_kernel<<<grid_size, BLOCKSIZE>>>(devX, ARRAYSIZE, devSum);
hipEventRecord(stop); // stop timing
// get the runtime
hipEventSynchronize(stop);
float milliseconds = 0.0;
hipEventElapsedTime(&milliseconds, start, stop);
float device_sum = 0.0;
hipMemcpy(&device_sum, devSum, sizeof(float), hipMemcpyDeviceToHost); // print the runtime
std::cout << milliseconds << " milliseconds for parallel run" << std::endl;
std::cout << "Host sum: " << local_sum << std::endl;
std::cout << "Device sum: " << device_sum << std::endl;
// free memory
hipFree(devX);
hipFree(devSum);
delete[] x;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_cooperative_groups.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#define ARRAYSIZE 10000
#define BLOCKSIZE 256
using namespace cooperative_groups;
// Basic reduction code found in the presentation; going to test on a variety of
// thread groups
__device__ float threadSum(float *x, int elements)
{
float thread_sum = 0.0;
int id = blockIdx.x*blockDim.x + threadIdx.x;
int step = blockDim.x*gridDim.x;
for (int i = id; i < elements / step; i += step)
{
thread_sum += x[i];
}
return thread_sum;
}
template <unsigned size>
__device__ float reduce(thread_block_tile<size> g, float val)
{
for (int i = g.size() / 2; i > 0; i /= 2) {
val += g.shfl_down(val, i);
}
return val;
}
// use this kernel to get sum
__global__ void sum_kernel(float *x, int elements, float *val)
{
float thread_sum = threadSum(x, elements);
thread_block_tile<32> g = tiled_partition<32>(this_thread_block());
float tile_sum = reduce<32>(g, thread_sum);
// first block and first warp in block
if (g.thread_rank() == 0)
{
atomicAdd(val, tile_sum);
}
}
int main(void)
{
float *x, *devX, *devSum; // pointers for local and device arrays
x = new float[ARRAYSIZE]; // make x the specified size
float local_sum = 0.0;
int grid_size = (ARRAYSIZE + BLOCKSIZE - 1)/BLOCKSIZE;
// compute sum of all array elements and fill x with the data where the ith
// element is i
for (int i = 0; i < ARRAYSIZE; i++)
{
x[i] = i/1000;
local_sum += i/1000;
}
// create an array on the device that contains X and copy over the data
hipMalloc((void**)&devX, ARRAYSIZE*sizeof(float));
hipMalloc((void**)&devSum, sizeof(float));
hipMemcpy(devX, x, ARRAYSIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(devSum, &local_sum, sizeof(float), hipMemcpyHostToDevice);
// Setup timers to test different configurations
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start); // start timer
// run the kernel
sum_kernel<<<grid_size, BLOCKSIZE>>>(devX, ARRAYSIZE, devSum);
hipEventRecord(stop); // stop timing
// get the runtime
hipEventSynchronize(stop);
float milliseconds = 0.0;
hipEventElapsedTime(&milliseconds, start, stop);
float device_sum = 0.0;
hipMemcpy(&device_sum, devSum, sizeof(float), hipMemcpyDeviceToHost); // print the runtime
std::cout << milliseconds << " milliseconds for parallel run" << std::endl;
std::cout << "Host sum: " << local_sum << std::endl;
std::cout << "Device sum: " << device_sum << std::endl;
// free memory
hipFree(devX);
hipFree(devSum);
delete[] x;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sum_kernelPfiS_
.globl _Z10sum_kernelPfiS_
.p2align 8
.type _Z10sum_kernelPfiS_,@function
_Z10sum_kernelPfiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s7, s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v5, 0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s2
s_cselect_b32 s3, 12, 18
s_ashr_i32 s10, s7, 31
v_mov_b32_e32 v1, s3
s_add_i32 s7, s7, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s7, s7, s10
global_load_u16 v4, v1, s[4:5]
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s3, v4
s_mul_i32 s6, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s6, 31
s_add_i32 s3, s6, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
s_xor_b32 s2, s10, s2
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s9, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s8, v1
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s9, s9, s8
v_mad_u64_u32 v[2:3], null, s15, v4, v[1:2]
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_mul_hi_u32 s8, s7, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s3
s_sub_i32 s7, s7, s9
s_add_i32 s9, s8, 1
s_sub_i32 s10, s7, s3
s_cmp_ge_u32 s7, s3
s_cselect_b32 s8, s9, s8
s_cselect_b32 s7, s10, s7
s_add_i32 s9, s8, 1
s_cmp_ge_u32 s7, s3
s_cselect_b32 s3, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
s_sub_i32 s10, s3, s2
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s10, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, 0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v6, v[3:4], off
v_add_nc_u32_e32 v2, s6, v2
v_add_co_u32 v3, vcc_lo, v3, s8
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s10, v2
s_or_b32 s11, s2, s11
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s11
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s2, s[4:5], 0xc
v_mbcnt_lo_u32_b32 v2, -1, 0
s_mov_b32 s4, 16
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s4, v2
s_lshr_b32 s5, s4, 1
s_cmp_gt_u32 s4, 1
v_cmp_gt_u32_e32 vcc_lo, 32, v3
v_cndmask_b32_e64 v3, 0, s4, vcc_lo
s_mov_b32 s4, s5
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v3, v3, v2, 2
ds_bpermute_b32 v3, v3, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v3
s_cbranch_scc1 .LBB0_5
v_bfe_u32 v2, v0, 10, 5
v_bfe_u32 v0, v0, 20, 10
s_and_b32 s3, 0xffff, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_mov_b32 s2, exec_lo
v_and_b32_e32 v0, 31, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_bfrev_b32_e32 v2, 1
s_mov_b32 s2, exec_lo
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ctz_i32_b32 s3, s2
v_readlane_b32 s4, v5, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, s3
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s4, v2
s_cbranch_scc1 .LBB0_8
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s3
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_kernelPfiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10sum_kernelPfiS_, .Lfunc_end0-_Z10sum_kernelPfiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_kernelPfiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10sum_kernelPfiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_cooperative_groups.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#define ARRAYSIZE 10000
#define BLOCKSIZE 256
using namespace cooperative_groups;
// Basic reduction code found in the presentation; going to test on a variety of
// thread groups
__device__ float threadSum(float *x, int elements)
{
float thread_sum = 0.0;
int id = blockIdx.x*blockDim.x + threadIdx.x;
int step = blockDim.x*gridDim.x;
for (int i = id; i < elements / step; i += step)
{
thread_sum += x[i];
}
return thread_sum;
}
template <unsigned size>
__device__ float reduce(thread_block_tile<size> g, float val)
{
for (int i = g.size() / 2; i > 0; i /= 2) {
val += g.shfl_down(val, i);
}
return val;
}
// use this kernel to get sum
__global__ void sum_kernel(float *x, int elements, float *val)
{
float thread_sum = threadSum(x, elements);
thread_block_tile<32> g = tiled_partition<32>(this_thread_block());
float tile_sum = reduce<32>(g, thread_sum);
// first block and first warp in block
if (g.thread_rank() == 0)
{
atomicAdd(val, tile_sum);
}
}
int main(void)
{
float *x, *devX, *devSum; // pointers for local and device arrays
x = new float[ARRAYSIZE]; // make x the specified size
float local_sum = 0.0;
int grid_size = (ARRAYSIZE + BLOCKSIZE - 1)/BLOCKSIZE;
// compute sum of all array elements and fill x with the data where the ith
// element is i
for (int i = 0; i < ARRAYSIZE; i++)
{
x[i] = i/1000;
local_sum += i/1000;
}
// create an array on the device that contains X and copy over the data
hipMalloc((void**)&devX, ARRAYSIZE*sizeof(float));
hipMalloc((void**)&devSum, sizeof(float));
hipMemcpy(devX, x, ARRAYSIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(devSum, &local_sum, sizeof(float), hipMemcpyHostToDevice);
// Setup timers to test different configurations
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start); // start timer
// run the kernel
sum_kernel<<<grid_size, BLOCKSIZE>>>(devX, ARRAYSIZE, devSum);
hipEventRecord(stop); // stop timing
// get the runtime
hipEventSynchronize(stop);
float milliseconds = 0.0;
hipEventElapsedTime(&milliseconds, start, stop);
float device_sum = 0.0;
hipMemcpy(&device_sum, devSum, sizeof(float), hipMemcpyDeviceToHost); // print the runtime
std::cout << milliseconds << " milliseconds for parallel run" << std::endl;
std::cout << "Host sum: " << local_sum << std::endl;
std::cout << "Device sum: " << device_sum << std::endl;
// free memory
hipFree(devX);
hipFree(devSum);
delete[] x;
return 0;
}
|
.text
.file "reduction_tests.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__sum_kernelPfiS_ # -- Begin function _Z25__device_stub__sum_kernelPfiS_
.p2align 4, 0x90
.type _Z25__device_stub__sum_kernelPfiS_,@function
_Z25__device_stub__sum_kernelPfiS_: # @_Z25__device_stub__sum_kernelPfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sum_kernelPfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sum_kernelPfiS_, .Lfunc_end0-_Z25__device_stub__sum_kernelPfiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %rbx
movl $0, 12(%rsp)
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imulq $274877907, %rcx, %rcx # imm = 0x10624DD3
shrq $38, %rcx
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
movss %xmm1, (%rbx,%rax,4)
addss %xmm1, %xmm0
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
movss %xmm0, 12(%rsp)
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967336, %rdi # imm = 0x100000028
leaq 216(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 136(%rsp)
movl $10000, 52(%rsp) # imm = 0x2710
movq %rcx, 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 52(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10sum_kernelPfiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 64(%rsp)
movq 56(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $0, 40(%rsp)
movq 16(%rsp), %rsi
leaq 40(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $30, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_17
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB1_8
.LBB1_7:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%r14)
je .LBB1_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_kernelPfiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sum_kernelPfiS_,@object # @_Z10sum_kernelPfiS_
.section .rodata,"a",@progbits
.globl _Z10sum_kernelPfiS_
.p2align 3, 0x0
_Z10sum_kernelPfiS_:
.quad _Z25__device_stub__sum_kernelPfiS_
.size _Z10sum_kernelPfiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " milliseconds for parallel run"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host sum: "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device sum: "
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10sum_kernelPfiS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sum_kernelPfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sum_kernelPfiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10sum_kernelPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ IABS R8, c[0x0][0x168] ; /* 0x00005a0000087a13 */
/* 0x000fe20000000000 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x5f0 ; /* 0x000005a000007945 */
/* 0x000fe20003800000 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*0060*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fc800000001ff */
/*0070*/ IABS R5, R0.reuse ; /* 0x0000000000057213 */
/* 0x080fe40000000000 */
/*0080*/ IABS R9, R0 ; /* 0x0000000000097213 */
/* 0x000fe40000000000 */
/*0090*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc40007ffe0ff */
/*00c0*/ IADD3 R4, RZ, -R9, RZ ; /* 0x80000009ff047210 */
/* 0x000fc80007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00f0*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*0130*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0140*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fe200078e00ff */
/*0150*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e260000002100 */
/*0160*/ IMAD R4, R3, R4, R6 ; /* 0x0000000403047224 */
/* 0x000fca00078e0206 */
/*0170*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0180*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*0190*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f26070 */
/*01b0*/ LOP3.LUT R4, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000047a12 */
/* 0x000fe400078e3cff */
/*01c0*/ LOP3.LUT R5, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff057212 */
/* 0x000fe400078e33ff */
/*01d0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f06270 */
/*01e0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0200*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R3, R7, c[0x0][0x0], R2 ; /* 0x0000000007037a24 */
/* 0x001fc800078e0202 */
/*0220*/ @!P0 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff048224 */
/* 0x000fca00078e0a04 */
/*0230*/ SEL R4, R5, R4, !P1 ; /* 0x0000000405047207 */
/* 0x000fc80004800000 */
/*0240*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f06270 */
/*0250*/ @P0 BRA 0x5e0 ; /* 0x0000038000000947 */
/* 0x000fea0003800000 */
/*0260*/ I2F.U32.RP R8, R0 ; /* 0x0000000000087306 */
/* 0x000e220000209000 */
/*0270*/ IADD3 R6, R0, R3, RZ ; /* 0x0000000300067210 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*0290*/ BSSY B1, 0x4c0 ; /* 0x0000022000017945 */
/* 0x000fe20003800000 */
/*02a0*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe40000000f00 */
/*02b0*/ LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff097212 */
/* 0x000fe200078e33ff */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*02d0*/ IADD3 R9, R9, R4, R0 ; /* 0x0000000409097210 */
/* 0x000fe20007ffe000 */
/*02e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*02f0*/ IADD3 R7, R8, 0xffffffe, RZ ; /* 0x0ffffffe08077810 */
/* 0x001fcc0007ffe0ff */
/*0300*/ F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000021f000 */
/*0310*/ IMAD R11, R11, R7, RZ ; /* 0x000000070b0b7224 */
/* 0x001fc800078e02ff */
/*0320*/ IMAD.HI.U32 R6, R7, R11, R6 ; /* 0x0000000b07067227 */
/* 0x000fcc00078e0006 */
/*0330*/ IMAD.HI.U32 R6, R6, R9, RZ ; /* 0x0000000906067227 */
/* 0x000fca00078e00ff */
/*0340*/ IADD3 R8, -R6, RZ, RZ ; /* 0x000000ff06087210 */
/* 0x000fca0007ffe1ff */
/*0350*/ IMAD R9, R0, R8, R9 ; /* 0x0000000800097224 */
/* 0x000fca00078e0209 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f06070 */
/*0370*/ @P0 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109090824 */
/* 0x000fe200078e0a00 */
/*0380*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*0390*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*03a0*/ ISETP.GE.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f26070 */
/*03b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ SEL R6, R5, R6, !P0 ; /* 0x0000000605067207 */
/* 0x000fc80004000000 */
/*03d0*/ IADD3 R5, R6.reuse, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x040fe40007ffe0ff */
/*03e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*03f0*/ LOP3.LUT P0, R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fda000780c0ff */
/*0400*/ @!P0 BRA 0x4b0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0420*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fc600000001ff */
/*0430*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0440*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0450*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fc600078e0203 */
/*0470*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0480*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*0490*/ FADD R14, R9, R14 ; /* 0x0000000e090e7221 */
/* 0x004fd00000000000 */
/*04a0*/ @P0 BRA 0x440 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*04b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04c0*/ @!P1 BRA 0x5e0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*04d0*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fcc00078e0206 */
/*04f0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe400078e0206 */
/*0500*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0510*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0208 */
/*0520*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee8000c1e1900 */
/*0530*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc400078e020a */
/*0540*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1900 */
/*0560*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0570*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0580*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe20003f06270 */
/*0590*/ FADD R14, R7, R14 ; /* 0x0000000e070e7221 */
/* 0x004fc80000000000 */
/*05a0*/ FADD R14, R14, R9 ; /* 0x000000090e0e7221 */
/* 0x008fc80000000000 */
/*05b0*/ FADD R14, R14, R11 ; /* 0x0000000b0e0e7221 */
/* 0x010fc80000000000 */
/*05c0*/ FADD R14, R14, R13 ; /* 0x0000000d0e0e7221 */
/* 0x020fe20000000000 */
/*05d0*/ @!P0 BRA 0x4d0 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ SHFL.DOWN PT, R3, R14, 0x10, 0x1f ; /* 0x0a001f000e037f89 */
/* 0x000e2800000e0000 */
/*0600*/ S2R R9, SR_TID.Z ; /* 0x0000000000097919 */
/* 0x000e680000002300 */
/*0610*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e620000002200 */
/*0620*/ FADD R3, R3, R14 ; /* 0x0000000e03037221 */
/* 0x001fca0000000000 */
/*0630*/ SHFL.DOWN PT, R0, R3, 0x8, 0x1f ; /* 0x09001f0003007f89 */
/* 0x000e2200000e0000 */
/*0640*/ IMAD R9, R9, c[0x0][0x4], R6 ; /* 0x0000010009097a24 */
/* 0x002fc800078e0206 */
/*0650*/ IMAD R9, R9, c[0x0][0x0], R2 ; /* 0x0000000009097a24 */
/* 0x000fca00078e0202 */
/*0660*/ LOP3.LUT P0, RZ, R9, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f09ff7812 */
/* 0x000fe2000780c0ff */
/*0670*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x001fca0000000000 */
/*0680*/ SHFL.DOWN PT, R5, R0, 0x4, 0x1f ; /* 0x08801f0000057f89 */
/* 0x000e2400000e0000 */
/*0690*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x001fca0000000000 */
/*06a0*/ SHFL.DOWN PT, R4, R5, 0x2, 0x1f ; /* 0x08401f0005047f89 */
/* 0x000e2400000e0000 */
/*06b0*/ FADD R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x001fca0000000000 */
/*06c0*/ SHFL.DOWN PT, R7, R4, 0x1, 0x1f ; /* 0x08201f0004077f89 */
/* 0x000e2400000e0000 */
/*06d0*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x001fe20000000000 */
/*06e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0700*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0710*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e784 */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sum_kernelPfiS_
.globl _Z10sum_kernelPfiS_
.p2align 8
.type _Z10sum_kernelPfiS_,@function
_Z10sum_kernelPfiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s7, s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v5, 0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s2
s_cselect_b32 s3, 12, 18
s_ashr_i32 s10, s7, 31
v_mov_b32_e32 v1, s3
s_add_i32 s7, s7, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s7, s7, s10
global_load_u16 v4, v1, s[4:5]
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s3, v4
s_mul_i32 s6, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s6, 31
s_add_i32 s3, s6, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
s_xor_b32 s2, s10, s2
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s9, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s8, v1
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s9, s9, s8
v_mad_u64_u32 v[2:3], null, s15, v4, v[1:2]
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_mul_hi_u32 s8, s7, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s3
s_sub_i32 s7, s7, s9
s_add_i32 s9, s8, 1
s_sub_i32 s10, s7, s3
s_cmp_ge_u32 s7, s3
s_cselect_b32 s8, s9, s8
s_cselect_b32 s7, s10, s7
s_add_i32 s9, s8, 1
s_cmp_ge_u32 s7, s3
s_cselect_b32 s3, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
s_sub_i32 s10, s3, s2
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s10, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, 0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v6, v[3:4], off
v_add_nc_u32_e32 v2, s6, v2
v_add_co_u32 v3, vcc_lo, v3, s8
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s10, v2
s_or_b32 s11, s2, s11
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s11
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s2, s[4:5], 0xc
v_mbcnt_lo_u32_b32 v2, -1, 0
s_mov_b32 s4, 16
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s4, v2
s_lshr_b32 s5, s4, 1
s_cmp_gt_u32 s4, 1
v_cmp_gt_u32_e32 vcc_lo, 32, v3
v_cndmask_b32_e64 v3, 0, s4, vcc_lo
s_mov_b32 s4, s5
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v3, v3, v2, 2
ds_bpermute_b32 v3, v3, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v3
s_cbranch_scc1 .LBB0_5
v_bfe_u32 v2, v0, 10, 5
v_bfe_u32 v0, v0, 20, 10
s_and_b32 s3, 0xffff, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_mov_b32 s2, exec_lo
v_and_b32_e32 v0, 31, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_bfrev_b32_e32 v2, 1
s_mov_b32 s2, exec_lo
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ctz_i32_b32 s3, s2
v_readlane_b32 s4, v5, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, s3
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s4, v2
s_cbranch_scc1 .LBB0_8
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s3
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_kernelPfiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10sum_kernelPfiS_, .Lfunc_end0-_Z10sum_kernelPfiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_kernelPfiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10sum_kernelPfiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0013c77a_00000000-6_reduction_tests.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6871:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6871:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9threadSumPfi
.type _Z9threadSumPfi, @function
_Z9threadSumPfi:
.LFB6866:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6866:
.size _Z9threadSumPfi, .-_Z9threadSumPfi
.globl _Z33__device_stub__Z10sum_kernelPfiS_PfiS_
.type _Z33__device_stub__Z10sum_kernelPfiS_PfiS_, @function
_Z33__device_stub__Z10sum_kernelPfiS_PfiS_:
.LFB6893:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sum_kernelPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6893:
.size _Z33__device_stub__Z10sum_kernelPfiS_PfiS_, .-_Z33__device_stub__Z10sum_kernelPfiS_PfiS_
.globl _Z10sum_kernelPfiS_
.type _Z10sum_kernelPfiS_, @function
_Z10sum_kernelPfiS_:
.LFB6894:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10sum_kernelPfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6894:
.size _Z10sum_kernelPfiS_, .-_Z10sum_kernelPfiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " milliseconds for parallel run"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Host sum: "
.LC3:
.string "Device sum: "
.text
.globl main
.type main, @function
main:
.LFB6868:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $40000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $0, %edx
pxor %xmm1, %xmm1
.L14:
movslq %edx, %rax
imulq $274877907, %rax, %rax
sarq $38, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rdx,4)
addss %xmm0, %xmm1
addq $1, %rdx
cmpq $10000, %rdx
jne .L14
movss %xmm1, 12(%rsp)
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 48(%rsp)
leaq 48(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0x00000000, 60(%rsp)
leaq 60(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movl $10000, %esi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z10sum_kernelPfiS_PfiS_
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6868:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10sum_kernelPfiS_"
.section .rodata.str1.8
.align 8
.LC5:
.string "_ZN49_INTERNAL_5dfde221_18_reduction_tests_cu_2ba847b74cuda3std3__419piecewise_constructE"
.align 8
.LC6:
.string "_ZN49_INTERNAL_5dfde221_18_reduction_tests_cu_2ba847b74cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC7:
.string "_ZN49_INTERNAL_5dfde221_18_reduction_tests_cu_2ba847b74cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6896:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_kernelPfiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6896:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "reduction_tests.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__sum_kernelPfiS_ # -- Begin function _Z25__device_stub__sum_kernelPfiS_
.p2align 4, 0x90
.type _Z25__device_stub__sum_kernelPfiS_,@function
_Z25__device_stub__sum_kernelPfiS_: # @_Z25__device_stub__sum_kernelPfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sum_kernelPfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sum_kernelPfiS_, .Lfunc_end0-_Z25__device_stub__sum_kernelPfiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %rbx
movl $0, 12(%rsp)
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imulq $274877907, %rcx, %rcx # imm = 0x10624DD3
shrq $38, %rcx
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
movss %xmm1, (%rbx,%rax,4)
addss %xmm1, %xmm0
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
movss %xmm0, 12(%rsp)
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967336, %rdi # imm = 0x100000028
leaq 216(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 136(%rsp)
movl $10000, 52(%rsp) # imm = 0x2710
movq %rcx, 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 52(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10sum_kernelPfiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 64(%rsp)
movq 56(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $0, 40(%rsp)
movq 16(%rsp), %rsi
leaq 40(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $30, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_17
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB1_8
.LBB1_7:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%r14)
je .LBB1_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_kernelPfiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sum_kernelPfiS_,@object # @_Z10sum_kernelPfiS_
.section .rodata,"a",@progbits
.globl _Z10sum_kernelPfiS_
.p2align 3, 0x0
_Z10sum_kernelPfiS_:
.quad _Z25__device_stub__sum_kernelPfiS_
.size _Z10sum_kernelPfiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " milliseconds for parallel run"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host sum: "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device sum: "
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10sum_kernelPfiS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sum_kernelPfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sum_kernelPfiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda.h>
#include <stdio.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
//#define BLOCK_WIDTH 512
__global__ void printMatrix(float **d_matrix, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j < size + 1 && j >=0) {
printf("i is %d, j is %d, %f \n", i, j, d_matrix[i][j]);
}
}
}
__global__ void changeFirstElementToOne(float **d_matrix, int pivot, int size, int firstElement) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i == pivot) {
if (j >= pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] / firstElement;
}
}
}
__global__ void eliminationKernel(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j > pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][pivot] * d_matrix[pivot][j];
}
}
}
__global__ void setPivotColumnToZero(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j == pivot) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void backSubstitution(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == size) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][subLine] * d_matrix[subLine][size];
}
}
}
__global__ void setSubColToZero(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == subLine) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void writeToDResult(float **d_matrix, int size, float *d_result) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j == size) {
d_result[i] = d_matrix[i][j];
}
}
}
int main(void) {
// read in data
std::vector<int> int_list;
std::string line_;
std::ifstream file_("test100.txt");
if (!file_) {
std::cout << "Cannot open file.\n";
return 0;
}
int size; // size of the matrix and vectors
file_ >> size;
float **matrix; // matrix of the linear system
matrix = new float*[size];
for (int i = 0; i < size; i++) {
matrix[i] = new float[size+1];
}
for (int i = 0; i < size; i++) {
for (int j = 0; j < size + 1; j++) {
file_ >> matrix[i][j];
}
}
// initialize variable
float * result, * d_result; // result vector
float **d_matrix;
float **d_matrix_h;
d_matrix_h = (float**)malloc(size * sizeof(float *));
// alloc space for device copies of a
cudaMalloc((void **) &d_result, size * sizeof(float));
cudaMalloc((void **) &d_matrix, size * sizeof(float*));
// alloc space for host copies of result
result = (float *)malloc(size * sizeof(float));
// copy from host to device
for (int i = 0; i < size; i++) {
cudaMalloc((void**)&(d_matrix_h[i]), (size+1) * sizeof(float));
cudaMemcpy(d_matrix_h[i], matrix[i], (size+1) * sizeof(float), cudaMemcpyHostToDevice);
}
cudaMemcpy(d_matrix, d_matrix_h, size * sizeof(float *), cudaMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8);
dim3 numBlocks((size - 1 + threadsPerBlock.x)/threadsPerBlock.x, (size + 1 - 1 + threadsPerBlock.y)/threadsPerBlock.y);
struct timespec cudalustart = {0,0}; //time of constructing GF
struct timespec cudaluend = {0,0};
clock_gettime(CLOCK_REALTIME,&cudalustart);
// gaussian elimination
for (int i = 0; i < size; i++) { // i is the pivot line here.
// change first element of the pivot line to 1
float firstElement;
cudaMemcpy(&firstElement, &d_matrix_h[i][i], sizeof(float), cudaMemcpyDeviceToHost);
// std::cout << firstElement << std::endl;
changeFirstElementToOne<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size, firstElement);
// the line under pivot line minus pivot line
eliminationKernel<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setPivotColumnToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// back substitution
for (int i = size - 1; i > 0; i--) { // form the last line to first line
// current line is i. every line i 's "b"
backSubstitution<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setSubColToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// write result from d_matrix to d_result
writeToDResult<<<numBlocks, threadsPerBlock>>>(d_matrix, size, d_result);
// copy result back to host
cudaMemcpy(result, d_result, size * sizeof(float), cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME,&cudaluend);
std::cout<<"The time is "<<(cudaluend.tv_sec-cudalustart.tv_sec)*1000+(cudaluend.tv_nsec-cudalustart.tv_nsec)/1000000<<"ms\n";
/* // print the result
for (int x = 0; x < size; x++) {
std::cout << result[x] << std::endl;
}
*/
// clean up
free(matrix); free(result); free(d_matrix_h);
cudaFree(d_matrix); cudaFree(d_result);
return 0;
}
|
.file "tmpxft_001247a7_00000000-6_GE.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4177:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4177:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11printMatrixPPfiPPfi
.type _Z33__device_stub__Z11printMatrixPPfiPPfi, @function
_Z33__device_stub__Z11printMatrixPPfiPPfi:
.LFB4199:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11printMatrixPPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4199:
.size _Z33__device_stub__Z11printMatrixPPfiPPfi, .-_Z33__device_stub__Z11printMatrixPPfiPPfi
.globl _Z11printMatrixPPfi
.type _Z11printMatrixPPfi, @function
_Z11printMatrixPPfi:
.LFB4200:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11printMatrixPPfiPPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4200:
.size _Z11printMatrixPPfi, .-_Z11printMatrixPPfi
.globl _Z47__device_stub__Z23changeFirstElementToOnePPfiiiPPfiii
.type _Z47__device_stub__Z23changeFirstElementToOnePPfiiiPPfiii, @function
_Z47__device_stub__Z23changeFirstElementToOnePPfiiiPPfiii:
.LFB4201:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23changeFirstElementToOnePPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4201:
.size _Z47__device_stub__Z23changeFirstElementToOnePPfiiiPPfiii, .-_Z47__device_stub__Z23changeFirstElementToOnePPfiiiPPfiii
.globl _Z23changeFirstElementToOnePPfiii
.type _Z23changeFirstElementToOnePPfiii, @function
_Z23changeFirstElementToOnePPfiii:
.LFB4202:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23changeFirstElementToOnePPfiiiPPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4202:
.size _Z23changeFirstElementToOnePPfiii, .-_Z23changeFirstElementToOnePPfiii
.globl _Z40__device_stub__Z17eliminationKernelPPfiiPPfii
.type _Z40__device_stub__Z17eliminationKernelPPfiiPPfii, @function
_Z40__device_stub__Z17eliminationKernelPPfiiPPfii:
.LFB4203:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17eliminationKernelPPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4203:
.size _Z40__device_stub__Z17eliminationKernelPPfiiPPfii, .-_Z40__device_stub__Z17eliminationKernelPPfiiPPfii
.globl _Z17eliminationKernelPPfii
.type _Z17eliminationKernelPPfii, @function
_Z17eliminationKernelPPfii:
.LFB4204:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17eliminationKernelPPfiiPPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4204:
.size _Z17eliminationKernelPPfii, .-_Z17eliminationKernelPPfii
.globl _Z43__device_stub__Z20setPivotColumnToZeroPPfiiPPfii
.type _Z43__device_stub__Z20setPivotColumnToZeroPPfiiPPfii, @function
_Z43__device_stub__Z20setPivotColumnToZeroPPfiiPPfii:
.LFB4205:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20setPivotColumnToZeroPPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4205:
.size _Z43__device_stub__Z20setPivotColumnToZeroPPfiiPPfii, .-_Z43__device_stub__Z20setPivotColumnToZeroPPfiiPPfii
.globl _Z20setPivotColumnToZeroPPfii
.type _Z20setPivotColumnToZeroPPfii, @function
_Z20setPivotColumnToZeroPPfii:
.LFB4206:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20setPivotColumnToZeroPPfiiPPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4206:
.size _Z20setPivotColumnToZeroPPfii, .-_Z20setPivotColumnToZeroPPfii
.globl _Z39__device_stub__Z16backSubstitutionPPfiiPPfii
.type _Z39__device_stub__Z16backSubstitutionPPfiiPPfii, @function
_Z39__device_stub__Z16backSubstitutionPPfiiPPfii:
.LFB4207:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16backSubstitutionPPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4207:
.size _Z39__device_stub__Z16backSubstitutionPPfiiPPfii, .-_Z39__device_stub__Z16backSubstitutionPPfiiPPfii
.globl _Z16backSubstitutionPPfii
.type _Z16backSubstitutionPPfii, @function
_Z16backSubstitutionPPfii:
.LFB4208:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16backSubstitutionPPfiiPPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4208:
.size _Z16backSubstitutionPPfii, .-_Z16backSubstitutionPPfii
.globl _Z38__device_stub__Z15setSubColToZeroPPfiiPPfii
.type _Z38__device_stub__Z15setSubColToZeroPPfiiPPfii, @function
_Z38__device_stub__Z15setSubColToZeroPPfiiPPfii:
.LFB4209:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15setSubColToZeroPPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4209:
.size _Z38__device_stub__Z15setSubColToZeroPPfiiPPfii, .-_Z38__device_stub__Z15setSubColToZeroPPfiiPPfii
.globl _Z15setSubColToZeroPPfii
.type _Z15setSubColToZeroPPfii, @function
_Z15setSubColToZeroPPfii:
.LFB4210:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15setSubColToZeroPPfiiPPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4210:
.size _Z15setSubColToZeroPPfii, .-_Z15setSubColToZeroPPfii
.globl _Z38__device_stub__Z14writeToDResultPPfiS_PPfiS_
.type _Z38__device_stub__Z14writeToDResultPPfiS_PPfiS_, @function
_Z38__device_stub__Z14writeToDResultPPfiS_PPfiS_:
.LFB4211:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14writeToDResultPPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4211:
.size _Z38__device_stub__Z14writeToDResultPPfiS_PPfiS_, .-_Z38__device_stub__Z14writeToDResultPPfiS_PPfiS_
.globl _Z14writeToDResultPPfiS_
.type _Z14writeToDResultPPfiS_, @function
_Z14writeToDResultPPfiS_:
.LFB4212:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14writeToDResultPPfiS_PPfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4212:
.size _Z14writeToDResultPPfiS_, .-_Z14writeToDResultPPfiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14writeToDResultPPfiS_"
.LC1:
.string "_Z15setSubColToZeroPPfii"
.LC2:
.string "_Z16backSubstitutionPPfii"
.LC3:
.string "_Z20setPivotColumnToZeroPPfii"
.LC4:
.string "_Z17eliminationKernelPPfii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z23changeFirstElementToOnePPfiii"
.section .rodata.str1.1
.LC6:
.string "_Z11printMatrixPPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4214:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14writeToDResultPPfiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15setSubColToZeroPPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16backSubstitutionPPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20setPivotColumnToZeroPPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17eliminationKernelPPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z23changeFirstElementToOnePPfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11printMatrixPPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4214:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4540:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L64:
ret
.cfi_endproc
.LFE4540:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC7:
.string "test100.txt"
.LC8:
.string "Cannot open file.\n"
.LC9:
.string "The time is "
.LC10:
.string "ms\n"
.text
.globl main
.type main, @function
main:
.LFB4163:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4163
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $680, %rsp
.cfi_def_cfa_offset 736
movq %fs:40, %rax
movq %rax, 664(%rsp)
xorl %eax, %eax
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq $0, 120(%rsp)
movb $0, 128(%rsp)
leaq 144(%rsp), %rdi
movl $8, %edx
leaq .LC7(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movl 432(%rsp), %r13d
andl $5, %r13d
jne .L109
movq %rsp, %rsi
leaq 144(%rsp), %rdi
.LEHB1:
call _ZNSirsERi@PLT
jmp .L110
.L109:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L69
.L110:
movslq (%rsp), %rax
movabsq $1152921504606846975, %rdx
cmpq %rax, %rdx
jb .L70
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %r14
movl (%rsp), %eax
movl $0, %ebx
movabsq $2305843009213693950, %rbp
testl %eax, %eax
jg .L71
.L72:
movslq %eax, %rbx
leaq 0(,%rbx,8), %rdi
call malloc@PLT
movq %rax, %r12
leaq 0(,%rbx,4), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
jmp .L111
.L70:
movq 664(%rsp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L73:
call __cxa_throw_bad_array_new_length@PLT
.L98:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L92:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 664(%rsp), %rax
subq %fs:40, %rax
je .L93
call __stack_chk_fail@PLT
.L113:
movq %rax, (%r14,%rbx,8)
movl (%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jle .L112
.L71:
addl $1, %eax
cltq
cmpq %rax, %rbp
jb .L74
leaq 0(,%rax,4), %rdi
call _Znam@PLT
jmp .L113
.L74:
movq 664(%rsp), %rax
subq %fs:40, %rax
je .L76
call __stack_chk_fail@PLT
.L76:
call __cxa_throw_bad_array_new_length@PLT
.L112:
testl %eax, %eax
jle .L72
movq %r14, %rbp
leaq 144(%rsp), %r12
jmp .L77
.L114:
addq $1, %rbx
cmpl %ebx, (%rsp)
jl .L79
.L78:
movq 0(%rbp), %rax
leaq (%rax,%rbx,4), %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L114
.L79:
addl $1, %r13d
movl (%rsp), %eax
addq $8, %rbp
cmpl %r13d, %eax
jle .L72
.L77:
movl $0, %ebx
cmpl $0, (%rsp)
jns .L78
jmp .L79
.L111:
movslq (%rsp), %rsi
salq $3, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl (%rsp), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L80
movq %r12, %r13
movl $0, %ebp
jmp .L81
.L115:
movl (%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movq (%r14,%rbp,8), %rsi
movq 0(%r13), %rdi
movl $1, %ecx
call cudaMemcpy@PLT
movl (%rsp), %ebx
addq $1, %rbp
addq $8, %r13
cmpl %ebp, %ebx
jle .L80
.L81:
leal 1(%rbx), %esi
movslq %esi, %rsi
salq $2, %rsi
movq %r13, %rdi
call cudaMalloc@PLT
jmp .L115
.L80:
movslq %ebx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl (%rsp), %eax
leal 7(%rax), %edx
shrl $3, %edx
movl %edx, 36(%rsp)
addl $8, %eax
shrl $3, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
cmpl $0, (%rsp)
jle .L82
movl $0, %ebp
leaq 4(%rsp), %r13
jmp .L86
.L118:
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L83
cvttss2sil 4(%rsp), %ecx
movl (%rsp), %edx
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z47__device_stub__Z23changeFirstElementToOnePPfiiiPPfiii
.L83:
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L84
movl (%rsp), %edx
movl %ebx, %esi
movq 16(%rsp), %rdi
call _Z40__device_stub__Z17eliminationKernelPPfiiPPfii
.L84:
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L116
.L85:
movl (%rsp), %ebx
addq $1, %rbp
cmpl %ebp, %ebx
jle .L117
.L86:
movl %ebp, %ebx
movq (%r12,%rbp,8), %rax
leaq (%rax,%rbp,4), %rsi
movl $2, %ecx
movl $4, %edx
movq %r13, %rdi
call cudaMemcpy@PLT
jmp .L118
.L116:
movl (%rsp), %edx
movl %ebx, %esi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z20setPivotColumnToZeroPPfiiPPfii
jmp .L85
.L117:
subl $1, %ebx
testl %ebx, %ebx
jg .L89
.L82:
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
jmp .L119
.L121:
testl %eax, %eax
jne .L87
movl (%rsp), %edx
movl %ebx, %esi
movq 16(%rsp), %rdi
call _Z39__device_stub__Z16backSubstitutionPPfiiPPfii
.L87:
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L120
.L88:
subl $1, %ebx
je .L82
.L89:
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
jmp .L121
.L120:
movl (%rsp), %edx
movl %ebx, %esi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z15setSubColToZeroPPfiiPPfii
jmp .L88
.L119:
testl %eax, %eax
jne .L90
movq 8(%rsp), %rdx
movl (%rsp), %esi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z14writeToDResultPPfiS_PPfiS_
.L90:
movslq (%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 64(%rsp), %rcx
subq 48(%rsp), %rcx
imulq $1000, %rcx, %rcx
movq 72(%rsp), %rax
subq 56(%rsp), %rax
movl $1000000, %esi
cqto
idivq %rsi
leaq (%rcx,%rax), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
.L69:
leaq 144(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 664(%rsp), %rax
subq %fs:40, %rax
jne .L122
movl $0, %eax
addq $680, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L97:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L92
.L93:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L122:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4163:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4163-.LLSDACSB4163
.LLSDACSB4163:
.uleb128 .LEHB0-.LFB4163
.uleb128 .LEHE0-.LEHB0
.uleb128 .L97-.LFB4163
.uleb128 0
.uleb128 .LEHB1-.LFB4163
.uleb128 .LEHE1-.LEHB1
.uleb128 .L98-.LFB4163
.uleb128 0
.uleb128 .LEHB2-.LFB4163
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4163:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda.h>
#include <stdio.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
//#define BLOCK_WIDTH 512
__global__ void printMatrix(float **d_matrix, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j < size + 1 && j >=0) {
printf("i is %d, j is %d, %f \n", i, j, d_matrix[i][j]);
}
}
}
__global__ void changeFirstElementToOne(float **d_matrix, int pivot, int size, int firstElement) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i == pivot) {
if (j >= pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] / firstElement;
}
}
}
__global__ void eliminationKernel(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j > pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][pivot] * d_matrix[pivot][j];
}
}
}
__global__ void setPivotColumnToZero(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j == pivot) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void backSubstitution(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == size) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][subLine] * d_matrix[subLine][size];
}
}
}
__global__ void setSubColToZero(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == subLine) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void writeToDResult(float **d_matrix, int size, float *d_result) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j == size) {
d_result[i] = d_matrix[i][j];
}
}
}
int main(void) {
// read in data
std::vector<int> int_list;
std::string line_;
std::ifstream file_("test100.txt");
if (!file_) {
std::cout << "Cannot open file.\n";
return 0;
}
int size; // size of the matrix and vectors
file_ >> size;
float **matrix; // matrix of the linear system
matrix = new float*[size];
for (int i = 0; i < size; i++) {
matrix[i] = new float[size+1];
}
for (int i = 0; i < size; i++) {
for (int j = 0; j < size + 1; j++) {
file_ >> matrix[i][j];
}
}
// initialize variable
float * result, * d_result; // result vector
float **d_matrix;
float **d_matrix_h;
d_matrix_h = (float**)malloc(size * sizeof(float *));
// alloc space for device copies of a
cudaMalloc((void **) &d_result, size * sizeof(float));
cudaMalloc((void **) &d_matrix, size * sizeof(float*));
// alloc space for host copies of result
result = (float *)malloc(size * sizeof(float));
// copy from host to device
for (int i = 0; i < size; i++) {
cudaMalloc((void**)&(d_matrix_h[i]), (size+1) * sizeof(float));
cudaMemcpy(d_matrix_h[i], matrix[i], (size+1) * sizeof(float), cudaMemcpyHostToDevice);
}
cudaMemcpy(d_matrix, d_matrix_h, size * sizeof(float *), cudaMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8);
dim3 numBlocks((size - 1 + threadsPerBlock.x)/threadsPerBlock.x, (size + 1 - 1 + threadsPerBlock.y)/threadsPerBlock.y);
struct timespec cudalustart = {0,0}; //time of constructing GF
struct timespec cudaluend = {0,0};
clock_gettime(CLOCK_REALTIME,&cudalustart);
// gaussian elimination
for (int i = 0; i < size; i++) { // i is the pivot line here.
// change first element of the pivot line to 1
float firstElement;
cudaMemcpy(&firstElement, &d_matrix_h[i][i], sizeof(float), cudaMemcpyDeviceToHost);
// std::cout << firstElement << std::endl;
changeFirstElementToOne<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size, firstElement);
// the line under pivot line minus pivot line
eliminationKernel<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setPivotColumnToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// back substitution
for (int i = size - 1; i > 0; i--) { // form the last line to first line
// current line is i. every line i 's "b"
backSubstitution<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setSubColToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// write result from d_matrix to d_result
writeToDResult<<<numBlocks, threadsPerBlock>>>(d_matrix, size, d_result);
// copy result back to host
cudaMemcpy(result, d_result, size * sizeof(float), cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME,&cudaluend);
std::cout<<"The time is "<<(cudaluend.tv_sec-cudalustart.tv_sec)*1000+(cudaluend.tv_nsec-cudalustart.tv_nsec)/1000000<<"ms\n";
/* // print the result
for (int x = 0; x < size; x++) {
std::cout << result[x] << std::endl;
}
*/
// clean up
free(matrix); free(result); free(d_matrix_h);
cudaFree(d_matrix); cudaFree(d_result);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
//#define BLOCK_WIDTH 512
__global__ void printMatrix(float **d_matrix, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j < size + 1 && j >=0) {
printf("i is %d, j is %d, %f \n", i, j, d_matrix[i][j]);
}
}
}
__global__ void changeFirstElementToOne(float **d_matrix, int pivot, int size, int firstElement) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i == pivot) {
if (j >= pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] / firstElement;
}
}
}
__global__ void eliminationKernel(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j > pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][pivot] * d_matrix[pivot][j];
}
}
}
__global__ void setPivotColumnToZero(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j == pivot) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void backSubstitution(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == size) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][subLine] * d_matrix[subLine][size];
}
}
}
__global__ void setSubColToZero(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == subLine) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void writeToDResult(float **d_matrix, int size, float *d_result) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j == size) {
d_result[i] = d_matrix[i][j];
}
}
}
int main(void) {
// read in data
std::vector<int> int_list;
std::string line_;
std::ifstream file_("test100.txt");
if (!file_) {
std::cout << "Cannot open file.\n";
return 0;
}
int size; // size of the matrix and vectors
file_ >> size;
float **matrix; // matrix of the linear system
matrix = new float*[size];
for (int i = 0; i < size; i++) {
matrix[i] = new float[size+1];
}
for (int i = 0; i < size; i++) {
for (int j = 0; j < size + 1; j++) {
file_ >> matrix[i][j];
}
}
// initialize variable
float * result, * d_result; // result vector
float **d_matrix;
float **d_matrix_h;
d_matrix_h = (float**)malloc(size * sizeof(float *));
// alloc space for device copies of a
hipMalloc((void **) &d_result, size * sizeof(float));
hipMalloc((void **) &d_matrix, size * sizeof(float*));
// alloc space for host copies of result
result = (float *)malloc(size * sizeof(float));
// copy from host to device
for (int i = 0; i < size; i++) {
hipMalloc((void**)&(d_matrix_h[i]), (size+1) * sizeof(float));
hipMemcpy(d_matrix_h[i], matrix[i], (size+1) * sizeof(float), hipMemcpyHostToDevice);
}
hipMemcpy(d_matrix, d_matrix_h, size * sizeof(float *), hipMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8);
dim3 numBlocks((size - 1 + threadsPerBlock.x)/threadsPerBlock.x, (size + 1 - 1 + threadsPerBlock.y)/threadsPerBlock.y);
struct timespec cudalustart = {0,0}; //time of constructing GF
struct timespec cudaluend = {0,0};
clock_gettime(CLOCK_REALTIME,&cudalustart);
// gaussian elimination
for (int i = 0; i < size; i++) { // i is the pivot line here.
// change first element of the pivot line to 1
float firstElement;
hipMemcpy(&firstElement, &d_matrix_h[i][i], sizeof(float), hipMemcpyDeviceToHost);
// std::cout << firstElement << std::endl;
changeFirstElementToOne<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size, firstElement);
// the line under pivot line minus pivot line
eliminationKernel<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setPivotColumnToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// back substitution
for (int i = size - 1; i > 0; i--) { // form the last line to first line
// current line is i. every line i 's "b"
backSubstitution<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setSubColToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// write result from d_matrix to d_result
writeToDResult<<<numBlocks, threadsPerBlock>>>(d_matrix, size, d_result);
// copy result back to host
hipMemcpy(result, d_result, size * sizeof(float), hipMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME,&cudaluend);
std::cout<<"The time is "<<(cudaluend.tv_sec-cudalustart.tv_sec)*1000+(cudaluend.tv_nsec-cudalustart.tv_nsec)/1000000<<"ms\n";
/* // print the result
for (int x = 0; x < size; x++) {
std::cout << result[x] << std::endl;
}
*/
// clean up
free(matrix); free(result); free(d_matrix_h);
hipFree(d_matrix); hipFree(d_result);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
//#define BLOCK_WIDTH 512
__global__ void printMatrix(float **d_matrix, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j < size + 1 && j >=0) {
printf("i is %d, j is %d, %f \n", i, j, d_matrix[i][j]);
}
}
}
__global__ void changeFirstElementToOne(float **d_matrix, int pivot, int size, int firstElement) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i == pivot) {
if (j >= pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] / firstElement;
}
}
}
__global__ void eliminationKernel(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j > pivot && j < size+1) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][pivot] * d_matrix[pivot][j];
}
}
}
__global__ void setPivotColumnToZero(float **d_matrix, int pivot, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i > pivot && i < size) {
if (j == pivot) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void backSubstitution(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == size) {
d_matrix[i][j] = d_matrix[i][j] - d_matrix[i][subLine] * d_matrix[subLine][size];
}
}
}
__global__ void setSubColToZero(float **d_matrix, int subLine, int size) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < subLine && i >= 0) {
if (j == subLine) {
d_matrix[i][j] = 0.0;
}
}
}
__global__ void writeToDResult(float **d_matrix, int size, float *d_result) {
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i < size && i >= 0) {
if (j == size) {
d_result[i] = d_matrix[i][j];
}
}
}
int main(void) {
// read in data
std::vector<int> int_list;
std::string line_;
std::ifstream file_("test100.txt");
if (!file_) {
std::cout << "Cannot open file.\n";
return 0;
}
int size; // size of the matrix and vectors
file_ >> size;
float **matrix; // matrix of the linear system
matrix = new float*[size];
for (int i = 0; i < size; i++) {
matrix[i] = new float[size+1];
}
for (int i = 0; i < size; i++) {
for (int j = 0; j < size + 1; j++) {
file_ >> matrix[i][j];
}
}
// initialize variable
float * result, * d_result; // result vector
float **d_matrix;
float **d_matrix_h;
d_matrix_h = (float**)malloc(size * sizeof(float *));
// alloc space for device copies of a
hipMalloc((void **) &d_result, size * sizeof(float));
hipMalloc((void **) &d_matrix, size * sizeof(float*));
// alloc space for host copies of result
result = (float *)malloc(size * sizeof(float));
// copy from host to device
for (int i = 0; i < size; i++) {
hipMalloc((void**)&(d_matrix_h[i]), (size+1) * sizeof(float));
hipMemcpy(d_matrix_h[i], matrix[i], (size+1) * sizeof(float), hipMemcpyHostToDevice);
}
hipMemcpy(d_matrix, d_matrix_h, size * sizeof(float *), hipMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8);
dim3 numBlocks((size - 1 + threadsPerBlock.x)/threadsPerBlock.x, (size + 1 - 1 + threadsPerBlock.y)/threadsPerBlock.y);
struct timespec cudalustart = {0,0}; //time of constructing GF
struct timespec cudaluend = {0,0};
clock_gettime(CLOCK_REALTIME,&cudalustart);
// gaussian elimination
for (int i = 0; i < size; i++) { // i is the pivot line here.
// change first element of the pivot line to 1
float firstElement;
hipMemcpy(&firstElement, &d_matrix_h[i][i], sizeof(float), hipMemcpyDeviceToHost);
// std::cout << firstElement << std::endl;
changeFirstElementToOne<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size, firstElement);
// the line under pivot line minus pivot line
eliminationKernel<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setPivotColumnToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// back substitution
for (int i = size - 1; i > 0; i--) { // form the last line to first line
// current line is i. every line i 's "b"
backSubstitution<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
setSubColToZero<<<numBlocks, threadsPerBlock>>>(d_matrix, i, size);
}
// write result from d_matrix to d_result
writeToDResult<<<numBlocks, threadsPerBlock>>>(d_matrix, size, d_result);
// copy result back to host
hipMemcpy(result, d_result, size * sizeof(float), hipMemcpyDeviceToHost);
clock_gettime(CLOCK_REALTIME,&cudaluend);
std::cout<<"The time is "<<(cudaluend.tv_sec-cudalustart.tv_sec)*1000+(cudaluend.tv_nsec-cudalustart.tv_nsec)/1000000<<"ms\n";
/* // print the result
for (int x = 0; x < size; x++) {
std::cout << result[x] << std::endl;
}
*/
// clean up
free(matrix); free(result); free(d_matrix_h);
hipFree(d_matrix); hipFree(d_result);
return 0;
}
|
.text
.file "GE.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__printMatrixPPfi # -- Begin function _Z26__device_stub__printMatrixPPfi
.p2align 4, 0x90
.type _Z26__device_stub__printMatrixPPfi,@function
_Z26__device_stub__printMatrixPPfi: # @_Z26__device_stub__printMatrixPPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11printMatrixPPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__printMatrixPPfi, .Lfunc_end0-_Z26__device_stub__printMatrixPPfi
.cfi_endproc
# -- End function
.globl _Z38__device_stub__changeFirstElementToOnePPfiii # -- Begin function _Z38__device_stub__changeFirstElementToOnePPfiii
.p2align 4, 0x90
.type _Z38__device_stub__changeFirstElementToOnePPfiii,@function
_Z38__device_stub__changeFirstElementToOnePPfiii: # @_Z38__device_stub__changeFirstElementToOnePPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23changeFirstElementToOnePPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z38__device_stub__changeFirstElementToOnePPfiii, .Lfunc_end1-_Z38__device_stub__changeFirstElementToOnePPfiii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__eliminationKernelPPfii # -- Begin function _Z32__device_stub__eliminationKernelPPfii
.p2align 4, 0x90
.type _Z32__device_stub__eliminationKernelPPfii,@function
_Z32__device_stub__eliminationKernelPPfii: # @_Z32__device_stub__eliminationKernelPPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17eliminationKernelPPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z32__device_stub__eliminationKernelPPfii, .Lfunc_end2-_Z32__device_stub__eliminationKernelPPfii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__setPivotColumnToZeroPPfii # -- Begin function _Z35__device_stub__setPivotColumnToZeroPPfii
.p2align 4, 0x90
.type _Z35__device_stub__setPivotColumnToZeroPPfii,@function
_Z35__device_stub__setPivotColumnToZeroPPfii: # @_Z35__device_stub__setPivotColumnToZeroPPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20setPivotColumnToZeroPPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z35__device_stub__setPivotColumnToZeroPPfii, .Lfunc_end3-_Z35__device_stub__setPivotColumnToZeroPPfii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__backSubstitutionPPfii # -- Begin function _Z31__device_stub__backSubstitutionPPfii
.p2align 4, 0x90
.type _Z31__device_stub__backSubstitutionPPfii,@function
_Z31__device_stub__backSubstitutionPPfii: # @_Z31__device_stub__backSubstitutionPPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16backSubstitutionPPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z31__device_stub__backSubstitutionPPfii, .Lfunc_end4-_Z31__device_stub__backSubstitutionPPfii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__setSubColToZeroPPfii # -- Begin function _Z30__device_stub__setSubColToZeroPPfii
.p2align 4, 0x90
.type _Z30__device_stub__setSubColToZeroPPfii,@function
_Z30__device_stub__setSubColToZeroPPfii: # @_Z30__device_stub__setSubColToZeroPPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15setSubColToZeroPPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z30__device_stub__setSubColToZeroPPfii, .Lfunc_end5-_Z30__device_stub__setSubColToZeroPPfii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__writeToDResultPPfiS_ # -- Begin function _Z29__device_stub__writeToDResultPPfiS_
.p2align 4, 0x90
.type _Z29__device_stub__writeToDResultPPfiS_,@function
_Z29__device_stub__writeToDResultPPfiS_: # @_Z29__device_stub__writeToDResultPPfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14writeToDResultPPfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z29__device_stub__writeToDResultPPfiS_, .Lfunc_end6-_Z29__device_stub__writeToDResultPPfiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $744, %rsp # imm = 0x2E8
.cfi_def_cfa_offset 800
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 208(%rsp), %rax
movq %rax, 192(%rsp)
movq $0, 200(%rsp)
movb $0, 208(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movl $.L.str, %esi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
movq 224(%rsp), %rax
movq -24(%rax), %rax
testb $5, 256(%rsp,%rax)
je .LBB7_7
# %bb.2:
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp4:
jmp .LBB7_3
.LBB7_7:
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movq %rsp, %rsi
callq _ZNSirsERi
.Ltmp7:
# %bb.8:
movslq (%rsp), %rbx
leaq (,%rbx,8), %rax
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %rax, %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
callq _Znam
movq %rax, 128(%rsp) # 8-byte Spill
.Ltmp10:
# %bb.9: # %.preheader193
movl %ebx, %r14d
testl %r14d, %r14d
jle .LBB7_13
# %bb.10: # %.lr.ph
leaq 4(,%r14,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_11: # =>This Inner Loop Header: Depth=1
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Znam
.Ltmp13:
# %bb.12: # in Loop: Header=BB7_11 Depth=1
movq 128(%rsp), %rcx # 8-byte Reload
movq %rax, (%rcx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB7_11
.LBB7_13: # %.preheader192
movl (%rsp), %eax
testl %eax, %eax
jle .LBB7_20
# %bb.14: # %.preheader191.preheader
xorl %r15d, %r15d
leaq 224(%rsp), %rbx
jmp .LBB7_15
.p2align 4, 0x90
.LBB7_19: # %._crit_edge
# in Loop: Header=BB7_15 Depth=1
incq %r15
movslq (%rsp), %rax
cmpq %rax, %r15
jge .LBB7_20
.LBB7_15: # %.preheader191
# =>This Loop Header: Depth=1
# Child Loop BB7_17 Depth 2
cmpl $0, (%rsp)
js .LBB7_19
# %bb.16: # %.lr.ph202
# in Loop: Header=BB7_15 Depth=1
movq 128(%rsp), %rax # 8-byte Reload
movq (%rax,%r15,8), %r14
movq $-1, %r12
.p2align 4, 0x90
.LBB7_17: # Parent Loop BB7_15 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp15:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r14, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp16:
# %bb.18: # %_ZNSirsERf.exit
# in Loop: Header=BB7_17 Depth=2
movslq (%rsp), %rax
incq %r12
addq $4, %r14
cmpq %rax, %r12
jl .LBB7_17
jmp .LBB7_19
.LBB7_20: # %._crit_edge204
movslq %eax, %rbx
leaq (,%rbx,8), %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, 120(%rsp) # 8-byte Spill
shlq $2, %rbx
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp19:
# %bb.21:
movslq (%rsp), %rsi
shlq $3, %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipMalloc
.Ltmp21:
# %bb.22:
movslq (%rsp), %r12
leaq (,%r12,4), %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, 152(%rsp) # 8-byte Spill
testq %r12, %r12
jle .LBB7_27
# %bb.23: # %.lr.ph207.preheader
xorl %r14d, %r14d
movq 120(%rsp), %rbx # 8-byte Reload
movq 128(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB7_24: # %.lr.ph207
# =>This Inner Loop Header: Depth=1
movslq %r12d, %rax
leaq 4(,%rax,4), %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq hipMalloc
.Ltmp23:
# %bb.25: # in Loop: Header=BB7_24 Depth=1
movq (%rbx), %rdi
movq (%r15), %rsi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp25:
# %bb.26: # in Loop: Header=BB7_24 Depth=1
incq %r14
movslq (%rsp), %r12
addq $8, %r15
addq $8, %rbx
cmpq %r12, %r14
jl .LBB7_24
.LBB7_27: # %._crit_edge208
movq 72(%rsp), %rdi
movslq %r12d, %rdx
shlq $3, %rdx
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq 120(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
.Ltmp28:
# %bb.28:
movl (%rsp), %r12d
leal 7(%r12), %eax
shrl $3, %eax
addl $8, %r12d
shrl $3, %r12d
shlq $32, %r12
orq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl (%rsp), %r15d
testl %r15d, %r15d
jle .LBB7_44
# %bb.29: # %.lr.ph212
xorl %r14d, %r14d
movabsq $34359738376, %rbp # imm = 0x800000008
leaq 80(%rsp), %rbx
xorl %r13d, %r13d
jmp .LBB7_30
.p2align 4, 0x90
.LBB7_43: # in Loop: Header=BB7_30 Depth=1
incq %r13
movslq (%rsp), %r15
addq $4, %r14
cmpq %r15, %r13
jge .LBB7_44
.LBB7_30: # =>This Inner Loop Header: Depth=1
movq 120(%rsp), %rax # 8-byte Reload
movq (%rax,%r14,2), %rsi
addq %r14, %rsi
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $4, %edx
leaq 144(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.31: # in Loop: Header=BB7_30 Depth=1
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp33:
# %bb.32: # in Loop: Header=BB7_30 Depth=1
testl %eax, %eax
jne .LBB7_35
# %bb.33: # in Loop: Header=BB7_30 Depth=1
movq 72(%rsp), %rax
movl (%rsp), %ecx
cvttss2si 144(%rsp), %edx
movq %rax, 56(%rsp)
movl %r13d, 8(%rsp)
movl %ecx, 4(%rsp)
movl %edx, 148(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 148(%rsp), %rax
movq %rax, 104(%rsp)
.Ltmp34:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp35:
# %bb.34: # %.noexc
# in Loop: Header=BB7_30 Depth=1
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp36:
.cfi_escape 0x2e, 0x10
movl $_Z23changeFirstElementToOnePPfiii, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp37:
.LBB7_35: # in Loop: Header=BB7_30 Depth=1
.Ltmp38:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp39:
# %bb.36: # in Loop: Header=BB7_30 Depth=1
testl %eax, %eax
jne .LBB7_39
# %bb.37: # in Loop: Header=BB7_30 Depth=1
movq 72(%rsp), %rax
movl (%rsp), %ecx
movq %rax, 56(%rsp)
movl %r13d, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
.Ltmp40:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp41:
# %bb.38: # %.noexc122
# in Loop: Header=BB7_30 Depth=1
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp42:
.cfi_escape 0x2e, 0x10
movl $_Z17eliminationKernelPPfii, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp43:
.LBB7_39: # in Loop: Header=BB7_30 Depth=1
.Ltmp44:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp45:
# %bb.40: # in Loop: Header=BB7_30 Depth=1
testl %eax, %eax
jne .LBB7_43
# %bb.41: # in Loop: Header=BB7_30 Depth=1
movq 72(%rsp), %rax
movl (%rsp), %ecx
movq %rax, 56(%rsp)
movl %r13d, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
.Ltmp46:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp47:
# %bb.42: # %.noexc130
# in Loop: Header=BB7_30 Depth=1
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp48:
.cfi_escape 0x2e, 0x10
movl $_Z20setPivotColumnToZeroPPfii, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp49:
jmp .LBB7_43
.LBB7_44: # %.preheader
cmpl $2, %r15d
jl .LBB7_55
# %bb.45: # %.lr.ph216
incl %r15d
movabsq $34359738376, %rbx # imm = 0x800000008
leaq 64(%rsp), %rbp
leaq 80(%rsp), %r14
jmp .LBB7_46
.p2align 4, 0x90
.LBB7_54: # in Loop: Header=BB7_46 Depth=1
decl %r15d
cmpl $2, %r15d
jle .LBB7_55
.LBB7_46: # =>This Inner Loop Header: Depth=1
.Ltmp51:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp52:
# %bb.47: # in Loop: Header=BB7_46 Depth=1
leal -2(%r15), %r13d
testl %eax, %eax
jne .LBB7_50
# %bb.48: # in Loop: Header=BB7_46 Depth=1
movq 72(%rsp), %rax
movl (%rsp), %ecx
movq %rax, 56(%rsp)
movl %r13d, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
.Ltmp53:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
.Ltmp54:
# %bb.49: # %.noexc138
# in Loop: Header=BB7_46 Depth=1
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp55:
.cfi_escape 0x2e, 0x10
movl $_Z16backSubstitutionPPfii, %edi
movq %r14, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp56:
.LBB7_50: # in Loop: Header=BB7_46 Depth=1
.Ltmp57:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp58:
# %bb.51: # in Loop: Header=BB7_46 Depth=1
testl %eax, %eax
jne .LBB7_54
# %bb.52: # in Loop: Header=BB7_46 Depth=1
movq 72(%rsp), %rax
movl (%rsp), %ecx
movq %rax, 56(%rsp)
movl %r13d, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
.Ltmp59:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
.Ltmp60:
# %bb.53: # %.noexc146
# in Loop: Header=BB7_46 Depth=1
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp61:
.cfi_escape 0x2e, 0x10
movl $_Z15setSubColToZeroPPfii, %edi
movq %r14, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp62:
jmp .LBB7_54
.LBB7_55: # %._crit_edge217
.Ltmp64:
.cfi_escape 0x2e, 0x00
movabsq $34359738376, %rdx # imm = 0x800000008
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp65:
# %bb.56:
testl %eax, %eax
jne .LBB7_59
# %bb.57:
movq 72(%rsp), %rax
movl (%rsp), %ecx
movq 136(%rsp), %rdx
movq %rax, 56(%rsp)
movl %ecx, 4(%rsp)
movq %rdx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
.Ltmp66:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp67:
# %bb.58: # %.noexc154
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp68:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z14writeToDResultPPfiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp69:
.LBB7_59:
movq 136(%rsp), %rsi
movslq (%rsp), %rdx
shlq $2, %rdx
.Ltmp70:
.cfi_escape 0x2e, 0x00
movq 152(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.Ltmp71:
# %bb.60:
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
.Ltmp72:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp73:
# %bb.61: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit157
movq 160(%rsp), %rcx
movq 168(%rsp), %rax
subq 176(%rsp), %rcx
imulq $1000, %rcx, %rcx # imm = 0x3E8
subq 184(%rsp), %rax
movabsq $4835703278458516699, %rdx # imm = 0x431BDE82D7B634DB
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
.Ltmp74:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp75:
# %bb.62: # %_ZNSolsEl.exit
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp77:
# %bb.63: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit160
.cfi_escape 0x2e, 0x00
movq 128(%rsp), %rdi # 8-byte Reload
callq free
.cfi_escape 0x2e, 0x00
movq 152(%rsp), %rdi # 8-byte Reload
callq free
.cfi_escape 0x2e, 0x00
movq 120(%rsp), %rdi # 8-byte Reload
callq free
movq 72(%rsp), %rdi
.Ltmp78:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp79:
# %bb.64:
movq 136(%rsp), %rdi
.Ltmp80:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp81:
.LBB7_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 480(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .LBB7_5
# %bb.4: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB7_5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
xorl %eax, %eax
addq $744, %rsp # imm = 0x2E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_66:
.cfi_def_cfa_offset 800
.Ltmp11:
jmp .LBB7_71
.LBB7_65:
.Ltmp8:
jmp .LBB7_71
.LBB7_70:
.Ltmp5:
jmp .LBB7_71
.LBB7_6:
.Ltmp2:
movq %rax, %rbx
jmp .LBB7_72
.LBB7_76:
.Ltmp29:
jmp .LBB7_71
.LBB7_78:
.Ltmp82:
jmp .LBB7_71
.LBB7_67:
.Ltmp14:
jmp .LBB7_71
.LBB7_77:
.Ltmp26:
jmp .LBB7_71
.LBB7_69:
.Ltmp63:
jmp .LBB7_71
.LBB7_68:
.Ltmp50:
jmp .LBB7_71
.LBB7_75:
.Ltmp17:
.LBB7_71:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 480(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB7_72:
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .LBB7_74
# %bb.73: # %.critedge.i.i161
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB7_74: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit163
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table7:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp21-.Ltmp18 # Call between .Ltmp18 and .Ltmp21
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp25-.Ltmp22 # Call between .Ltmp22 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp49-.Ltmp30 # Call between .Ltmp30 and .Ltmp49
.uleb128 .Ltmp50-.Lfunc_begin0 # jumps to .Ltmp50
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp62-.Ltmp51 # Call between .Ltmp51 and .Ltmp62
.uleb128 .Ltmp63-.Lfunc_begin0 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp81-.Ltmp64 # Call between .Ltmp64 and .Ltmp81
.uleb128 .Ltmp82-.Lfunc_begin0 # jumps to .Ltmp82
.byte 0 # On action: cleanup
.uleb128 .Ltmp81-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Lfunc_end7-.Ltmp81 # Call between .Ltmp81 and .Lfunc_end7
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11printMatrixPPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23changeFirstElementToOnePPfiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17eliminationKernelPPfii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20setPivotColumnToZeroPPfii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16backSubstitutionPPfii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15setSubColToZeroPPfii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14writeToDResultPPfiS_, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11printMatrixPPfi,@object # @_Z11printMatrixPPfi
.section .rodata,"a",@progbits
.globl _Z11printMatrixPPfi
.p2align 3, 0x0
_Z11printMatrixPPfi:
.quad _Z26__device_stub__printMatrixPPfi
.size _Z11printMatrixPPfi, 8
.type _Z23changeFirstElementToOnePPfiii,@object # @_Z23changeFirstElementToOnePPfiii
.globl _Z23changeFirstElementToOnePPfiii
.p2align 3, 0x0
_Z23changeFirstElementToOnePPfiii:
.quad _Z38__device_stub__changeFirstElementToOnePPfiii
.size _Z23changeFirstElementToOnePPfiii, 8
.type _Z17eliminationKernelPPfii,@object # @_Z17eliminationKernelPPfii
.globl _Z17eliminationKernelPPfii
.p2align 3, 0x0
_Z17eliminationKernelPPfii:
.quad _Z32__device_stub__eliminationKernelPPfii
.size _Z17eliminationKernelPPfii, 8
.type _Z20setPivotColumnToZeroPPfii,@object # @_Z20setPivotColumnToZeroPPfii
.globl _Z20setPivotColumnToZeroPPfii
.p2align 3, 0x0
_Z20setPivotColumnToZeroPPfii:
.quad _Z35__device_stub__setPivotColumnToZeroPPfii
.size _Z20setPivotColumnToZeroPPfii, 8
.type _Z16backSubstitutionPPfii,@object # @_Z16backSubstitutionPPfii
.globl _Z16backSubstitutionPPfii
.p2align 3, 0x0
_Z16backSubstitutionPPfii:
.quad _Z31__device_stub__backSubstitutionPPfii
.size _Z16backSubstitutionPPfii, 8
.type _Z15setSubColToZeroPPfii,@object # @_Z15setSubColToZeroPPfii
.globl _Z15setSubColToZeroPPfii
.p2align 3, 0x0
_Z15setSubColToZeroPPfii:
.quad _Z30__device_stub__setSubColToZeroPPfii
.size _Z15setSubColToZeroPPfii, 8
.type _Z14writeToDResultPPfiS_,@object # @_Z14writeToDResultPPfiS_
.globl _Z14writeToDResultPPfiS_
.p2align 3, 0x0
_Z14writeToDResultPPfiS_:
.quad _Z29__device_stub__writeToDResultPPfiS_
.size _Z14writeToDResultPPfiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "test100.txt"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot open file.\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The time is "
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ms\n"
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11printMatrixPPfi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23changeFirstElementToOnePPfiii"
.size .L__unnamed_2, 34
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17eliminationKernelPPfii"
.size .L__unnamed_3, 27
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z20setPivotColumnToZeroPPfii"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z16backSubstitutionPPfii"
.size .L__unnamed_5, 26
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z15setSubColToZeroPPfii"
.size .L__unnamed_6, 25
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z14writeToDResultPPfiS_"
.size .L__unnamed_7, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__printMatrixPPfi
.addrsig_sym _Z38__device_stub__changeFirstElementToOnePPfiii
.addrsig_sym _Z32__device_stub__eliminationKernelPPfii
.addrsig_sym _Z35__device_stub__setPivotColumnToZeroPPfii
.addrsig_sym _Z31__device_stub__backSubstitutionPPfii
.addrsig_sym _Z30__device_stub__setSubColToZeroPPfii
.addrsig_sym _Z29__device_stub__writeToDResultPPfiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z11printMatrixPPfi
.addrsig_sym _Z23changeFirstElementToOnePPfiii
.addrsig_sym _Z17eliminationKernelPPfii
.addrsig_sym _Z20setPivotColumnToZeroPPfii
.addrsig_sym _Z16backSubstitutionPPfii
.addrsig_sym _Z15setSubColToZeroPPfii
.addrsig_sym _Z14writeToDResultPPfiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// nvcc -arch=compute_20
//
#include "stdio.h"
#include "inttypes.h"
#include "time.h"
#include "math.h"
// Device code
#define TPB (256) // number of threads per block
#define MAX_V (200000)
typedef struct{
double _sqrt;
double _log;
} table_t;
__global__ void build_table(table_t *d_table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if ((thread==0)||(thread>MAX_V))
return;
double n=(double) thread;;
d_table[thread]._sqrt=1.0/sqrt(n);
d_table[thread]._log=log(n);
}
#define NUM_T_POWERS (10) // how many powers of t
#define NUM_T2PI_POWERS (10) // how many powers of t/2Pi
__global__ void RS(const double *ts, const long unsigned int *N, double *res, const table_t *table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if (thread >=N[0])
return;
double t=ts[thread];
// set up powers of t
double t_pows[NUM_T_POWERS];
t_pows[0]=t;
for(int j=1;j<NUM_T_POWERS;j++)
t_pows[j]=t_pows[j-1]*t;
//set up powers of t/2pi
double t2pi_pows[NUM_T2PI_POWERS];
t2pi_pows[0]=t/(2.0*M_PI);
for(int j=1;j<NUM_T2PI_POWERS;j++)
t2pi_pows[j]=t2pi_pows[j-1]*t2pi_pows[0];
// V=floor(sqrt(t/2pi))
double sqrt_t_2pi=sqrt(t2pi_pows[0]);
unsigned long int V=floor(sqrt_t_2pi);
if(V>MAX_V)
return;
double theta=t/2.0*(log(t2pi_pows[0])-1)-M_PI/8.0+1.0/(48.0*t);
theta=theta+7.0/(5760.0*t_pows[2])+31.0/(80640.0*t_pows[4]);
double res1=0.0;
for(unsigned long int n=1;n<=V;n++)
res1=res1+table[n]._sqrt*cos(theta-t*table[n]._log);
res1=res1+res1;
double p=sqrt_t_2pi-V;
double C0=cos(2.0*M_PI*(p*p-p-1.0/16.0))/cos(2.0*M_PI*p);
if(V&1)
res1=res1+1.0/sqrt(sqrt_t_2pi)*C0;
else
res1=res1-1.0/sqrt(sqrt_t_2pi)*C0;
res[thread]=res1;
}
#define _N_ (8192) // how many zeros to send to GPU at one time
// Host code
// read our 13 byte structure representing a zero gap
// into a quad
double in_bytes(FILE *infile)
{
uint64_t a;uint32_t b;uint8_t c;
if(fread(&a,sizeof(uint64_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (a). Exiting.\n");
exit(0);
}
//printf("a=%lu\n",a);
if(fread(&b,sizeof(uint32_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (b). Exiting.\n");
exit(0);
}
//printf("b=%u\n",b);
if(fread(&c,sizeof(uint8_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (c). Exiting.\n");
exit(0);
}
double r1;
//printf("Read a=%lX b=%x c=%x\n",a,b,c);
r1=(double) c/32.0 + (double) b/(32.0*256.0*256.0*256.0*256.0)+(double) (a&0xfff8000000000000)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^3, /2^37, /2^101
//r2=(double) (a&0x0007ffffffffffff)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^101
//printf("r1=%50.48e\nr2=%50.48e\n",r1,r2);
return(r1);
}
void print_elapsed(clock_t st_time)
{
clock_t this_time=clock();
//printf("this_time=%lu start_time %lu\n",this_time,st_time);
printf("%f seconds elapsed.\n",(double) (this_time-st_time)/(double) CLOCKS_PER_SEC);
}
//
int main(int argc, char **argv)
{
clock_t st_time=clock();
printf("In main\n");
FILE *infile=fopen(argv[1],"rb");
if(!infile)
{
printf("Failed to open file %s for binary input. Exiting.\n");
exit(0);
}
int devcount;
cudaGetDeviceCount(&devcount);
printf("Found %d CUDA devices.\n",devcount);
cudaSetDevice(1);
//cudaDeviceReset();
printf("Allocating device memory for sin_table\n");
print_elapsed(st_time);
double h_A[_N_],h_B[_N_];
table_t *d_table;
cudaMalloc((void **)&d_table,sizeof(table_t)*(MAX_V+1));
long unsigned int h_N[1];
h_N[0]=_N_;
//for(int i=0;i<N;i++) printf("%20.18e\n",to_double(h_A[i]));
// Allocate vectors in device memory
printf("Allocating other device memory.\n");
print_elapsed(st_time);
size_t size = h_N[0] * sizeof(double);
double* d_A;
cudaMalloc((void**)&d_A, size);
double* d_B;
cudaMalloc((void**)&d_B, size);
unsigned long int *d_N;
cudaMalloc((void **)&d_N,sizeof(long unsigned int));
// Copy vectors from host memory to device memory
// h_A and h_B are input vectors stored in host memory
int threadsPerBlock = TPB;
int num_blocks = MAX_V/TPB;
if(num_blocks*threadsPerBlock<MAX_V)
num_blocks++;
build_table<<<num_blocks, threadsPerBlock>>>(d_table);
num_blocks=h_N[0]/threadsPerBlock;
if(num_blocks*threadsPerBlock<h_N[0])
num_blocks++;
long int num_its;
fread(&num_its,sizeof(long int),1,infile);
printf("Doing %ld iterations on file %s.\n",num_its,argv[1]);
double st[2];
long int zs[2];
unsigned long int ptr=0;
double del_t,t;
for(long int it=0;it<num_its;it++)
{
if(it==100) break;
fread(st,sizeof(double),2,infile);
fread(&zs[0],sizeof(long int),1,infile);
if(st[0]==0.0)
continue;
t=st[0];
fread(&zs[1],sizeof(long int),1,infile);
//printf("Processing zero %ld to %ld=%ld in total.\n",zs[0]+1,zs[1],zs[1]-zs[0]);
for(long int z=zs[0]+1;z<=zs[1];z++)
{
del_t=in_bytes(infile);
if(del_t==0.0)
{
printf("Two zeros 0 apart. Exiting.\n");
exit(0);
}
t+=del_t;
//printf("Zero at %80.78e\n",to_double(t));
h_A[ptr++]=t;
if(ptr==h_N[0])
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
//print_elapsed(st_time);
// copy zeros and N to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_N, h_N, sizeof(long unsigned int), cudaMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory d_B to host memory h_B
cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
//print_elapsed(st_time);
ptr=0;
}
}
}
if(ptr!=0) // zeros didn't fit exactly into blocks
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_N, &ptr, sizeof(long unsigned int), cudaMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory to host memory
// h_B contains the result in host memory
cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
}
for(long unsigned int i=(ptr>=20?ptr-20:0);i<ptr;i++)
printf("Zero at %f rs returned %f\n",h_A[i],h_B[i]);
print_elapsed(st_time);
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_N);
}
|
.file "tmpxft_0015bd1a_00000000-6_rs_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Fatal error in in_bytes (a). Exiting.\n"
.align 8
.LC1:
.string "Fatal error in in_bytes (b). Exiting.\n"
.align 8
.LC2:
.string "Fatal error in in_bytes (c). Exiting.\n"
.text
.globl _Z8in_bytesP8_IO_FILE
.type _Z8in_bytesP8_IO_FILE, @function
_Z8in_bytesP8_IO_FILE:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $8, %edx
movl $8, %esi
call __fread_chk@PLT
cmpq $1, %rax
je .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L4:
leaq 12(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
cmpq $1, %rax
je .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L5:
leaq 11(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $1, %edx
movl $1, %esi
call __fread_chk@PLT
cmpq $1, %rax
jne .L13
movzbl 11(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC3(%rip), %xmm0
movl 12(%rsp), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC4(%rip), %xmm1
addsd %xmm1, %xmm0
movabsq $-2251799813685248, %rax
andq 16(%rsp), %rax
js .L9
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
.L10:
mulsd .LC5(%rip), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L9:
shrq %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L10
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8in_bytesP8_IO_FILE, .-_Z8in_bytesP8_IO_FILE
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "%f seconds elapsed.\n"
.text
.globl _Z13print_elapsedl
.type _Z13print_elapsedl, @function
_Z13print_elapsedl:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13print_elapsedl, .-_Z13print_elapsedl
.globl _Z38__device_stub__Z11build_tableP7table_tP7table_t
.type _Z38__device_stub__Z11build_tableP7table_tP7table_t, @function
_Z38__device_stub__Z11build_tableP7table_tP7table_t:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11build_tableP7table_t(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z11build_tableP7table_tP7table_t, .-_Z38__device_stub__Z11build_tableP7table_tP7table_t
.globl _Z11build_tableP7table_t
.type _Z11build_tableP7table_t, @function
_Z11build_tableP7table_t:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11build_tableP7table_tP7table_t
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11build_tableP7table_t, .-_Z11build_tableP7table_t
.globl _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
.type _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t, @function
_Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2RSPKdPKmPdPK7table_t(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t, .-_Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
.globl _Z2RSPKdPKmPdPK7table_t
.type _Z2RSPKdPKmPdPK7table_t, @function
_Z2RSPKdPKmPdPK7table_t:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z2RSPKdPKmPdPK7table_t, .-_Z2RSPKdPKmPdPK7table_t
.section .rodata.str1.1
.LC8:
.string "In main\n"
.LC9:
.string "rb"
.section .rodata.str1.8
.align 8
.LC10:
.string "Failed to open file %s for binary input. Exiting.\n"
.section .rodata.str1.1
.LC11:
.string "Found %d CUDA devices.\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Allocating device memory for sin_table\n"
.align 8
.LC13:
.string "Allocating other device memory.\n"
.align 8
.LC14:
.string "Doing %ld iterations on file %s.\n"
.section .rodata.str1.1
.LC16:
.string "Two zeros 0 apart. Exiting.\n"
.LC17:
.string "Zero at %f rs returned %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -131072(%rsp), %r11
.cfi_def_cfa 11, 131128
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $184, %rsp
.cfi_def_cfa_offset 131312
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 131240(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 24(%rsp)
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %rdi
leaq .LC9(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L58
movq %rax, %r12
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 44(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %r15
movq %r15, %rdi
call _Z13print_elapsedl
leaq 48(%rsp), %rdi
movl $3200016, %esi
call cudaMalloc@PLT
movq $8192, 120(%rsp)
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call _Z13print_elapsedl
movq 120(%rsp), %rax
leaq 0(,%rax,8), %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $782, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L35:
movq 120(%rsp), %rcx
movq %rcx, %rdx
shrq $8, %rdx
movl %edx, %eax
sall $8, %eax
cltq
cmpq %rcx, %rax
movl %edx, %eax
adcl $0, %eax
movl %eax, 20(%rsp)
leaq 80(%rsp), %rdi
movq %r12, %r8
movl $1, %ecx
movl $8, %edx
movl $8, %esi
call __fread_chk@PLT
movq 8(%rbx), %rcx
movq 80(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 88(%rsp)
cmpq $0, 80(%rsp)
jle .L48
movl $0, %r13d
leaq 128(%rsp), %r15
leaq 144(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L45
.L58:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L59:
movq 48(%rsp), %rdi
call _Z38__device_stub__Z11build_tableP7table_tP7table_t
jmp .L35
.L60:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
leaq 65696(%rsp), %rdi
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movq $0, 88(%rsp)
.L42:
addq $1, %rbp
cmpq %rbp, 152(%rsp)
jl .L38
.L44:
movq %r12, %rdi
call _Z8in_bytesP8_IO_FILE
pxor %xmm3, %xmm3
ucomisd %xmm3, %xmm0
jp .L40
je .L60
.L40:
movq %rbx, %xmm2
addsd %xmm0, %xmm2
movq %xmm2, %rbx
movq 88(%rsp), %rdx
leaq 1(%rdx), %rax
movq %rax, 88(%rsp)
movsd %xmm2, 160(%rsp,%rdx,8)
cmpq 120(%rsp), %rax
jne .L42
leaq 160(%rsp), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl 20(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movq 48(%rsp), %rcx
movq 64(%rsp), %rdx
movq 72(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
jmp .L43
.L38:
addq $1, %r13
cmpq %r13, 80(%rsp)
jle .L53
cmpq $100, %r13
je .L53
.L45:
movq %r12, %r8
movl $2, %ecx
movl $8, %edx
movl $16, %esi
movq %r15, %rdi
call __fread_chk@PLT
movq %r12, %r8
movl $1, %ecx
movl $8, %edx
movl $16, %esi
movq 8(%rsp), %rdi
call __fread_chk@PLT
movq 128(%rsp), %rbx
movq %rbx, %xmm5
pxor %xmm6, %xmm6
ucomisd %xmm6, %xmm5
jp .L51
je .L38
.L51:
leaq 152(%rsp), %rdi
movq %r12, %r8
movl $1, %ecx
movl $8, %edx
movl $8, %esi
call __fread_chk@PLT
movq 144(%rsp), %rax
leaq 1(%rax), %rbp
cmpq 152(%rsp), %rbp
jle .L44
jmp .L38
.L53:
cmpq $0, 88(%rsp)
je .L48
leaq 160(%rsp), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl 20(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L47:
leaq 65696(%rsp), %rdi
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
movl $20, %ebx
cmpq %rbx, %rax
cmovnb %rax, %rbx
subq $20, %rbx
cmpq %rax, %rbx
jnb .L48
leaq .LC17(%rip), %rbp
.L49:
movsd 160(%rsp,%rbx,8), %xmm0
movsd 65696(%rsp,%rbx,8), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq 88(%rsp), %rbx
jb .L49
.L48:
movq 24(%rsp), %rdi
call _Z13print_elapsedl
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 131240(%rsp), %rax
subq %fs:40, %rax
jne .L62
movl $0, %eax
addq $131256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movq 48(%rsp), %rcx
movq 64(%rsp), %rdx
movq 72(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
jmp .L47
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z2RSPKdPKmPdPK7table_t"
.LC19:
.string "_Z11build_tableP7table_t"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z2RSPKdPKmPdPK7table_t(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z11build_tableP7table_t(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1067450368
.align 8
.LC4:
.long 0
.long 1033895936
.align 8
.LC5:
.long 0
.long 966787072
.align 8
.LC6:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// nvcc -arch=compute_20
//
#include "stdio.h"
#include "inttypes.h"
#include "time.h"
#include "math.h"
// Device code
#define TPB (256) // number of threads per block
#define MAX_V (200000)
typedef struct{
double _sqrt;
double _log;
} table_t;
__global__ void build_table(table_t *d_table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if ((thread==0)||(thread>MAX_V))
return;
double n=(double) thread;;
d_table[thread]._sqrt=1.0/sqrt(n);
d_table[thread]._log=log(n);
}
#define NUM_T_POWERS (10) // how many powers of t
#define NUM_T2PI_POWERS (10) // how many powers of t/2Pi
__global__ void RS(const double *ts, const long unsigned int *N, double *res, const table_t *table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if (thread >=N[0])
return;
double t=ts[thread];
// set up powers of t
double t_pows[NUM_T_POWERS];
t_pows[0]=t;
for(int j=1;j<NUM_T_POWERS;j++)
t_pows[j]=t_pows[j-1]*t;
//set up powers of t/2pi
double t2pi_pows[NUM_T2PI_POWERS];
t2pi_pows[0]=t/(2.0*M_PI);
for(int j=1;j<NUM_T2PI_POWERS;j++)
t2pi_pows[j]=t2pi_pows[j-1]*t2pi_pows[0];
// V=floor(sqrt(t/2pi))
double sqrt_t_2pi=sqrt(t2pi_pows[0]);
unsigned long int V=floor(sqrt_t_2pi);
if(V>MAX_V)
return;
double theta=t/2.0*(log(t2pi_pows[0])-1)-M_PI/8.0+1.0/(48.0*t);
theta=theta+7.0/(5760.0*t_pows[2])+31.0/(80640.0*t_pows[4]);
double res1=0.0;
for(unsigned long int n=1;n<=V;n++)
res1=res1+table[n]._sqrt*cos(theta-t*table[n]._log);
res1=res1+res1;
double p=sqrt_t_2pi-V;
double C0=cos(2.0*M_PI*(p*p-p-1.0/16.0))/cos(2.0*M_PI*p);
if(V&1)
res1=res1+1.0/sqrt(sqrt_t_2pi)*C0;
else
res1=res1-1.0/sqrt(sqrt_t_2pi)*C0;
res[thread]=res1;
}
#define _N_ (8192) // how many zeros to send to GPU at one time
// Host code
// read our 13 byte structure representing a zero gap
// into a quad
double in_bytes(FILE *infile)
{
uint64_t a;uint32_t b;uint8_t c;
if(fread(&a,sizeof(uint64_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (a). Exiting.\n");
exit(0);
}
//printf("a=%lu\n",a);
if(fread(&b,sizeof(uint32_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (b). Exiting.\n");
exit(0);
}
//printf("b=%u\n",b);
if(fread(&c,sizeof(uint8_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (c). Exiting.\n");
exit(0);
}
double r1;
//printf("Read a=%lX b=%x c=%x\n",a,b,c);
r1=(double) c/32.0 + (double) b/(32.0*256.0*256.0*256.0*256.0)+(double) (a&0xfff8000000000000)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^3, /2^37, /2^101
//r2=(double) (a&0x0007ffffffffffff)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^101
//printf("r1=%50.48e\nr2=%50.48e\n",r1,r2);
return(r1);
}
void print_elapsed(clock_t st_time)
{
clock_t this_time=clock();
//printf("this_time=%lu start_time %lu\n",this_time,st_time);
printf("%f seconds elapsed.\n",(double) (this_time-st_time)/(double) CLOCKS_PER_SEC);
}
//
int main(int argc, char **argv)
{
clock_t st_time=clock();
printf("In main\n");
FILE *infile=fopen(argv[1],"rb");
if(!infile)
{
printf("Failed to open file %s for binary input. Exiting.\n");
exit(0);
}
int devcount;
cudaGetDeviceCount(&devcount);
printf("Found %d CUDA devices.\n",devcount);
cudaSetDevice(1);
//cudaDeviceReset();
printf("Allocating device memory for sin_table\n");
print_elapsed(st_time);
double h_A[_N_],h_B[_N_];
table_t *d_table;
cudaMalloc((void **)&d_table,sizeof(table_t)*(MAX_V+1));
long unsigned int h_N[1];
h_N[0]=_N_;
//for(int i=0;i<N;i++) printf("%20.18e\n",to_double(h_A[i]));
// Allocate vectors in device memory
printf("Allocating other device memory.\n");
print_elapsed(st_time);
size_t size = h_N[0] * sizeof(double);
double* d_A;
cudaMalloc((void**)&d_A, size);
double* d_B;
cudaMalloc((void**)&d_B, size);
unsigned long int *d_N;
cudaMalloc((void **)&d_N,sizeof(long unsigned int));
// Copy vectors from host memory to device memory
// h_A and h_B are input vectors stored in host memory
int threadsPerBlock = TPB;
int num_blocks = MAX_V/TPB;
if(num_blocks*threadsPerBlock<MAX_V)
num_blocks++;
build_table<<<num_blocks, threadsPerBlock>>>(d_table);
num_blocks=h_N[0]/threadsPerBlock;
if(num_blocks*threadsPerBlock<h_N[0])
num_blocks++;
long int num_its;
fread(&num_its,sizeof(long int),1,infile);
printf("Doing %ld iterations on file %s.\n",num_its,argv[1]);
double st[2];
long int zs[2];
unsigned long int ptr=0;
double del_t,t;
for(long int it=0;it<num_its;it++)
{
if(it==100) break;
fread(st,sizeof(double),2,infile);
fread(&zs[0],sizeof(long int),1,infile);
if(st[0]==0.0)
continue;
t=st[0];
fread(&zs[1],sizeof(long int),1,infile);
//printf("Processing zero %ld to %ld=%ld in total.\n",zs[0]+1,zs[1],zs[1]-zs[0]);
for(long int z=zs[0]+1;z<=zs[1];z++)
{
del_t=in_bytes(infile);
if(del_t==0.0)
{
printf("Two zeros 0 apart. Exiting.\n");
exit(0);
}
t+=del_t;
//printf("Zero at %80.78e\n",to_double(t));
h_A[ptr++]=t;
if(ptr==h_N[0])
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
//print_elapsed(st_time);
// copy zeros and N to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_N, h_N, sizeof(long unsigned int), cudaMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory d_B to host memory h_B
cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
//print_elapsed(st_time);
ptr=0;
}
}
}
if(ptr!=0) // zeros didn't fit exactly into blocks
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_N, &ptr, sizeof(long unsigned int), cudaMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory to host memory
// h_B contains the result in host memory
cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
}
for(long unsigned int i=(ptr>=20?ptr-20:0);i<ptr;i++)
printf("Zero at %f rs returned %f\n",h_A[i],h_B[i]);
print_elapsed(st_time);
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_N);
}
|
// nvcc -arch=compute_20
//
#include <hip/hip_runtime.h>
#include "stdio.h"
#include "inttypes.h"
#include "time.h"
#include "math.h"
// Device code
#define TPB (256) // number of threads per block
#define MAX_V (200000)
typedef struct{
double _sqrt;
double _log;
} table_t;
__global__ void build_table(table_t *d_table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if ((thread==0)||(thread>MAX_V))
return;
double n=(double) thread;;
d_table[thread]._sqrt=1.0/sqrt(n);
d_table[thread]._log=log(n);
}
#define NUM_T_POWERS (10) // how many powers of t
#define NUM_T2PI_POWERS (10) // how many powers of t/2Pi
__global__ void RS(const double *ts, const long unsigned int *N, double *res, const table_t *table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if (thread >=N[0])
return;
double t=ts[thread];
// set up powers of t
double t_pows[NUM_T_POWERS];
t_pows[0]=t;
for(int j=1;j<NUM_T_POWERS;j++)
t_pows[j]=t_pows[j-1]*t;
//set up powers of t/2pi
double t2pi_pows[NUM_T2PI_POWERS];
t2pi_pows[0]=t/(2.0*M_PI);
for(int j=1;j<NUM_T2PI_POWERS;j++)
t2pi_pows[j]=t2pi_pows[j-1]*t2pi_pows[0];
// V=floor(sqrt(t/2pi))
double sqrt_t_2pi=sqrt(t2pi_pows[0]);
unsigned long int V=floor(sqrt_t_2pi);
if(V>MAX_V)
return;
double theta=t/2.0*(log(t2pi_pows[0])-1)-M_PI/8.0+1.0/(48.0*t);
theta=theta+7.0/(5760.0*t_pows[2])+31.0/(80640.0*t_pows[4]);
double res1=0.0;
for(unsigned long int n=1;n<=V;n++)
res1=res1+table[n]._sqrt*cos(theta-t*table[n]._log);
res1=res1+res1;
double p=sqrt_t_2pi-V;
double C0=cos(2.0*M_PI*(p*p-p-1.0/16.0))/cos(2.0*M_PI*p);
if(V&1)
res1=res1+1.0/sqrt(sqrt_t_2pi)*C0;
else
res1=res1-1.0/sqrt(sqrt_t_2pi)*C0;
res[thread]=res1;
}
#define _N_ (8192) // how many zeros to send to GPU at one time
// Host code
// read our 13 byte structure representing a zero gap
// into a quad
double in_bytes(FILE *infile)
{
uint64_t a;uint32_t b;uint8_t c;
if(fread(&a,sizeof(uint64_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (a). Exiting.\n");
exit(0);
}
//printf("a=%lu\n",a);
if(fread(&b,sizeof(uint32_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (b). Exiting.\n");
exit(0);
}
//printf("b=%u\n",b);
if(fread(&c,sizeof(uint8_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (c). Exiting.\n");
exit(0);
}
double r1;
//printf("Read a=%lX b=%x c=%x\n",a,b,c);
r1=(double) c/32.0 + (double) b/(32.0*256.0*256.0*256.0*256.0)+(double) (a&0xfff8000000000000)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^3, /2^37, /2^101
//r2=(double) (a&0x0007ffffffffffff)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^101
//printf("r1=%50.48e\nr2=%50.48e\n",r1,r2);
return(r1);
}
void print_elapsed(clock_t st_time)
{
clock_t this_time=clock();
//printf("this_time=%lu start_time %lu\n",this_time,st_time);
printf("%f seconds elapsed.\n",(double) (this_time-st_time)/(double) CLOCKS_PER_SEC);
}
//
int main(int argc, char **argv)
{
clock_t st_time=clock();
printf("In main\n");
FILE *infile=fopen(argv[1],"rb");
if(!infile)
{
printf("Failed to open file %s for binary input. Exiting.\n");
exit(0);
}
int devcount;
hipGetDeviceCount(&devcount);
printf("Found %d CUDA devices.\n",devcount);
hipSetDevice(1);
//cudaDeviceReset();
printf("Allocating device memory for sin_table\n");
print_elapsed(st_time);
double h_A[_N_],h_B[_N_];
table_t *d_table;
hipMalloc((void **)&d_table,sizeof(table_t)*(MAX_V+1));
long unsigned int h_N[1];
h_N[0]=_N_;
//for(int i=0;i<N;i++) printf("%20.18e\n",to_double(h_A[i]));
// Allocate vectors in device memory
printf("Allocating other device memory.\n");
print_elapsed(st_time);
size_t size = h_N[0] * sizeof(double);
double* d_A;
hipMalloc((void**)&d_A, size);
double* d_B;
hipMalloc((void**)&d_B, size);
unsigned long int *d_N;
hipMalloc((void **)&d_N,sizeof(long unsigned int));
// Copy vectors from host memory to device memory
// h_A and h_B are input vectors stored in host memory
int threadsPerBlock = TPB;
int num_blocks = MAX_V/TPB;
if(num_blocks*threadsPerBlock<MAX_V)
num_blocks++;
build_table<<<num_blocks, threadsPerBlock>>>(d_table);
num_blocks=h_N[0]/threadsPerBlock;
if(num_blocks*threadsPerBlock<h_N[0])
num_blocks++;
long int num_its;
fread(&num_its,sizeof(long int),1,infile);
printf("Doing %ld iterations on file %s.\n",num_its,argv[1]);
double st[2];
long int zs[2];
unsigned long int ptr=0;
double del_t,t;
for(long int it=0;it<num_its;it++)
{
if(it==100) break;
fread(st,sizeof(double),2,infile);
fread(&zs[0],sizeof(long int),1,infile);
if(st[0]==0.0)
continue;
t=st[0];
fread(&zs[1],sizeof(long int),1,infile);
//printf("Processing zero %ld to %ld=%ld in total.\n",zs[0]+1,zs[1],zs[1]-zs[0]);
for(long int z=zs[0]+1;z<=zs[1];z++)
{
del_t=in_bytes(infile);
if(del_t==0.0)
{
printf("Two zeros 0 apart. Exiting.\n");
exit(0);
}
t+=del_t;
//printf("Zero at %80.78e\n",to_double(t));
h_A[ptr++]=t;
if(ptr==h_N[0])
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
//print_elapsed(st_time);
// copy zeros and N to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_N, h_N, sizeof(long unsigned int), hipMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory d_B to host memory h_B
hipMemcpy(h_B, d_B, size, hipMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
//print_elapsed(st_time);
ptr=0;
}
}
}
if(ptr!=0) // zeros didn't fit exactly into blocks
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_N, &ptr, sizeof(long unsigned int), hipMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory to host memory
// h_B contains the result in host memory
hipMemcpy(h_B, d_B, size, hipMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
}
for(long unsigned int i=(ptr>=20?ptr-20:0);i<ptr;i++)
printf("Zero at %f rs returned %f\n",h_A[i],h_B[i]);
print_elapsed(st_time);
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_N);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// nvcc -arch=compute_20
//
#include <hip/hip_runtime.h>
#include "stdio.h"
#include "inttypes.h"
#include "time.h"
#include "math.h"
// Device code
#define TPB (256) // number of threads per block
#define MAX_V (200000)
typedef struct{
double _sqrt;
double _log;
} table_t;
__global__ void build_table(table_t *d_table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if ((thread==0)||(thread>MAX_V))
return;
double n=(double) thread;;
d_table[thread]._sqrt=1.0/sqrt(n);
d_table[thread]._log=log(n);
}
#define NUM_T_POWERS (10) // how many powers of t
#define NUM_T2PI_POWERS (10) // how many powers of t/2Pi
__global__ void RS(const double *ts, const long unsigned int *N, double *res, const table_t *table)
{
int thread = blockIdx.x*TPB+threadIdx.x;
if (thread >=N[0])
return;
double t=ts[thread];
// set up powers of t
double t_pows[NUM_T_POWERS];
t_pows[0]=t;
for(int j=1;j<NUM_T_POWERS;j++)
t_pows[j]=t_pows[j-1]*t;
//set up powers of t/2pi
double t2pi_pows[NUM_T2PI_POWERS];
t2pi_pows[0]=t/(2.0*M_PI);
for(int j=1;j<NUM_T2PI_POWERS;j++)
t2pi_pows[j]=t2pi_pows[j-1]*t2pi_pows[0];
// V=floor(sqrt(t/2pi))
double sqrt_t_2pi=sqrt(t2pi_pows[0]);
unsigned long int V=floor(sqrt_t_2pi);
if(V>MAX_V)
return;
double theta=t/2.0*(log(t2pi_pows[0])-1)-M_PI/8.0+1.0/(48.0*t);
theta=theta+7.0/(5760.0*t_pows[2])+31.0/(80640.0*t_pows[4]);
double res1=0.0;
for(unsigned long int n=1;n<=V;n++)
res1=res1+table[n]._sqrt*cos(theta-t*table[n]._log);
res1=res1+res1;
double p=sqrt_t_2pi-V;
double C0=cos(2.0*M_PI*(p*p-p-1.0/16.0))/cos(2.0*M_PI*p);
if(V&1)
res1=res1+1.0/sqrt(sqrt_t_2pi)*C0;
else
res1=res1-1.0/sqrt(sqrt_t_2pi)*C0;
res[thread]=res1;
}
#define _N_ (8192) // how many zeros to send to GPU at one time
// Host code
// read our 13 byte structure representing a zero gap
// into a quad
double in_bytes(FILE *infile)
{
uint64_t a;uint32_t b;uint8_t c;
if(fread(&a,sizeof(uint64_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (a). Exiting.\n");
exit(0);
}
//printf("a=%lu\n",a);
if(fread(&b,sizeof(uint32_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (b). Exiting.\n");
exit(0);
}
//printf("b=%u\n",b);
if(fread(&c,sizeof(uint8_t),1,infile)!=1)
{
printf("Fatal error in in_bytes (c). Exiting.\n");
exit(0);
}
double r1;
//printf("Read a=%lX b=%x c=%x\n",a,b,c);
r1=(double) c/32.0 + (double) b/(32.0*256.0*256.0*256.0*256.0)+(double) (a&0xfff8000000000000)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^3, /2^37, /2^101
//r2=(double) (a&0x0007ffffffffffff)/(32.0*65536.0*65536.0*65536.0*65536.0*65536.0*65536.0); // /2^101
//printf("r1=%50.48e\nr2=%50.48e\n",r1,r2);
return(r1);
}
void print_elapsed(clock_t st_time)
{
clock_t this_time=clock();
//printf("this_time=%lu start_time %lu\n",this_time,st_time);
printf("%f seconds elapsed.\n",(double) (this_time-st_time)/(double) CLOCKS_PER_SEC);
}
//
int main(int argc, char **argv)
{
clock_t st_time=clock();
printf("In main\n");
FILE *infile=fopen(argv[1],"rb");
if(!infile)
{
printf("Failed to open file %s for binary input. Exiting.\n");
exit(0);
}
int devcount;
hipGetDeviceCount(&devcount);
printf("Found %d CUDA devices.\n",devcount);
hipSetDevice(1);
//cudaDeviceReset();
printf("Allocating device memory for sin_table\n");
print_elapsed(st_time);
double h_A[_N_],h_B[_N_];
table_t *d_table;
hipMalloc((void **)&d_table,sizeof(table_t)*(MAX_V+1));
long unsigned int h_N[1];
h_N[0]=_N_;
//for(int i=0;i<N;i++) printf("%20.18e\n",to_double(h_A[i]));
// Allocate vectors in device memory
printf("Allocating other device memory.\n");
print_elapsed(st_time);
size_t size = h_N[0] * sizeof(double);
double* d_A;
hipMalloc((void**)&d_A, size);
double* d_B;
hipMalloc((void**)&d_B, size);
unsigned long int *d_N;
hipMalloc((void **)&d_N,sizeof(long unsigned int));
// Copy vectors from host memory to device memory
// h_A and h_B are input vectors stored in host memory
int threadsPerBlock = TPB;
int num_blocks = MAX_V/TPB;
if(num_blocks*threadsPerBlock<MAX_V)
num_blocks++;
build_table<<<num_blocks, threadsPerBlock>>>(d_table);
num_blocks=h_N[0]/threadsPerBlock;
if(num_blocks*threadsPerBlock<h_N[0])
num_blocks++;
long int num_its;
fread(&num_its,sizeof(long int),1,infile);
printf("Doing %ld iterations on file %s.\n",num_its,argv[1]);
double st[2];
long int zs[2];
unsigned long int ptr=0;
double del_t,t;
for(long int it=0;it<num_its;it++)
{
if(it==100) break;
fread(st,sizeof(double),2,infile);
fread(&zs[0],sizeof(long int),1,infile);
if(st[0]==0.0)
continue;
t=st[0];
fread(&zs[1],sizeof(long int),1,infile);
//printf("Processing zero %ld to %ld=%ld in total.\n",zs[0]+1,zs[1],zs[1]-zs[0]);
for(long int z=zs[0]+1;z<=zs[1];z++)
{
del_t=in_bytes(infile);
if(del_t==0.0)
{
printf("Two zeros 0 apart. Exiting.\n");
exit(0);
}
t+=del_t;
//printf("Zero at %80.78e\n",to_double(t));
h_A[ptr++]=t;
if(ptr==h_N[0])
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
//print_elapsed(st_time);
// copy zeros and N to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_N, h_N, sizeof(long unsigned int), hipMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory d_B to host memory h_B
hipMemcpy(h_B, d_B, size, hipMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
//print_elapsed(st_time);
ptr=0;
}
}
}
if(ptr!=0) // zeros didn't fit exactly into blocks
{
//printf("Invoking GPU with first zero at %f\n",to_double(h_A[0]));
//printf("Last zero at %f\n",to_double(h_A[ptr-1]));
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_N, &ptr, sizeof(long unsigned int), hipMemcpyHostToDevice);
// Invoke kernel
RS<<<num_blocks, threadsPerBlock>>>(d_A, d_N, d_B,d_table);
// Copy result from device memory to host memory
// h_B contains the result in host memory
hipMemcpy(h_B, d_B, size, hipMemcpyDeviceToHost);
//printf("First result was %f\n",to_double(h_B[0]));
//printf("Last result was %f\n",to_double(h_B[ptr-1]));
}
for(long unsigned int i=(ptr>=20?ptr-20:0);i<ptr;i++)
printf("Zero at %f rs returned %f\n",h_A[i],h_B[i]);
print_elapsed(st_time);
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_N);
}
|
.text
.file "rs_double.hip"
.globl _Z26__device_stub__build_tableP7table_t # -- Begin function _Z26__device_stub__build_tableP7table_t
.p2align 4, 0x90
.type _Z26__device_stub__build_tableP7table_t,@function
_Z26__device_stub__build_tableP7table_t: # @_Z26__device_stub__build_tableP7table_t
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11build_tableP7table_t, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__build_tableP7table_t, .Lfunc_end0-_Z26__device_stub__build_tableP7table_t
.cfi_endproc
# -- End function
.globl _Z17__device_stub__RSPKdPKmPdPK7table_t # -- Begin function _Z17__device_stub__RSPKdPKmPdPK7table_t
.p2align 4, 0x90
.type _Z17__device_stub__RSPKdPKmPdPK7table_t,@function
_Z17__device_stub__RSPKdPKmPdPK7table_t: # @_Z17__device_stub__RSPKdPKmPdPK7table_t
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2RSPKdPKmPdPK7table_t, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z17__device_stub__RSPKdPKmPdPK7table_t, .Lfunc_end1-_Z17__device_stub__RSPKdPKmPdPK7table_t
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8in_bytesP8_IO_FILE
.LCPI2_0:
.quad 0x3fa0000000000000 # double 0.03125
.LCPI2_1:
.quad 0x3da0000000000000 # double 7.2759576141834259E-12
.LCPI2_4:
.quad 0x39a0000000000000 # double 3.944304526105059E-31
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_3:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z8in_bytesP8_IO_FILE
.p2align 4, 0x90
.type _Z8in_bytesP8_IO_FILE,@function
_Z8in_bytesP8_IO_FILE: # @_Z8in_bytesP8_IO_FILE
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movl $8, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB2_1
# %bb.3:
leaq 4(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB2_4
# %bb.5:
leaq 3(%rsp), %rdi
movl $1, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB2_6
# %bb.7:
movzbl 3(%rsp), %eax
cvtsi2sd %eax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movl 4(%rsp), %eax
cvtsi2sd %rax, %xmm1
mulsd .LCPI2_1(%rip), %xmm1
movabsq $-2251799813685248, %rax # imm = 0xFFF8000000000000
andq 8(%rsp), %rax
movq %rax, %xmm2
punpckldq .LCPI2_2(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI2_3(%rip), %xmm2
addsd %xmm0, %xmm1
movapd %xmm2, %xmm0
unpckhpd %xmm2, %xmm0 # xmm0 = xmm0[1],xmm2[1]
addsd %xmm2, %xmm0
mulsd .LCPI2_4(%rip), %xmm0
addsd %xmm1, %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 32
movl $.Lstr.2, %edi
jmp .LBB2_2
.LBB2_4:
movl $.Lstr.1, %edi
jmp .LBB2_2
.LBB2_6:
movl $.Lstr, %edi
.LBB2_2:
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z8in_bytesP8_IO_FILE, .Lfunc_end2-_Z8in_bytesP8_IO_FILE
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13print_elapsedl
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z13print_elapsedl
.p2align 4, 0x90
.type _Z13print_elapsedl,@function
_Z13print_elapsedl: # @_Z13print_elapsedl
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z13print_elapsedl, .Lfunc_end3-_Z13print_elapsedl
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $131336, %rsp # imm = 0x20108
.cfi_def_cfa_offset 131392
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
callq clock
movq %rax, %rbx
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%r13), %rdi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_21
# %bb.1:
movq %rax, %r12
movabsq $4294967552, %r14 # imm = 0x100000100
leaq 140(%rsp), %rdi
callq hipGetDeviceCount
movl 140(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
movl $.Lstr.4, %edi
callq puts@PLT
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
leaq 64(%rsp), %rdi
movl $3200016, %esi # imm = 0x30D410
callq hipMalloc
movq $8192, 56(%rsp) # imm = 0x2000
movl $.Lstr.5, %edi
callq puts@PLT
callq clock
movq %rbx, 232(%rsp) # 8-byte Spill
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 56(%rsp), %r15
shlq $3, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 526(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_3
# %bb.2:
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 256(%rsp), %rdi
leaq 65792(%rsp), %rsi
leaq 208(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 256(%rsp), %rsi
movl 264(%rsp), %edx
movq 65792(%rsp), %rcx
movl 65800(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z11build_tableP7table_t, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_3:
movq 56(%rsp), %rax
movq %rax, %r14
shrq $8, %r14
movl %r14d, %ecx
shll $8, %ecx
movslq %ecx, %rcx
cmpq %rax, %rcx
adcl $0, %r14d
leaq 248(%rsp), %rdi
movl $8, %esi
movl $1, %edx
movq %r12, %rcx
callq fread
movq 248(%rsp), %rbx
movq 8(%r13), %rdx
movl $.L.str.10, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq $0, (%rsp)
movl %r14d, %eax
movq %rax, 192(%rsp) # 8-byte Spill
testq %rbx, %rbx
jle .LBB4_14
# %bb.4: # %.lr.ph100
movabsq $4294967552, %rax # imm = 0x100000100
movq 192(%rsp), %rcx # 8-byte Reload
leaq (%rax,%rcx), %rbp
addq $-256, %rbp
decq %rbx
cmpq $99, %rbx
movl $99, %eax
cmovbq %rbx, %rax
movq %rax, 240(%rsp) # 8-byte Spill
xorl %ebx, %ebx
leaq 65792(%rsp), %r14
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_13: # %.loopexit
# in Loop: Header=BB4_5 Depth=1
leaq 1(%rbx), %rax
cmpq 240(%rsp), %rbx # 8-byte Folded Reload
movq %rax, %rbx
je .LBB4_14
.LBB4_5: # =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
movl $8, %esi
movl $2, %edx
leaq 208(%rsp), %rdi
movq %r12, %rcx
callq fread
movl $8, %esi
movl $1, %edx
leaq 144(%rsp), %rdi
movq %r12, %rcx
callq fread
movsd 208(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 200(%rsp) # 8-byte Spill
ucomisd .LCPI4_1(%rip), %xmm0
jne .LBB4_6
jnp .LBB4_13
.LBB4_6: # in Loop: Header=BB4_5 Depth=1
movl $8, %esi
movl $1, %edx
leaq 152(%rsp), %rdi
movq %r12, %rcx
callq fread
movq 152(%rsp), %r13
subq 144(%rsp), %r13
jg .LBB4_7
jmp .LBB4_13
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_7 Depth=2
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq $0, (%rsp)
.LBB4_12: # in Loop: Header=BB4_7 Depth=2
decq %r13
je .LBB4_13
.LBB4_7: # %.lr.ph
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
callq _Z8in_bytesP8_IO_FILE
ucomisd .LCPI4_1(%rip), %xmm0
jne .LBB4_8
jnp .LBB4_22
.LBB4_8: # in Loop: Header=BB4_7 Depth=2
movsd 200(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movq (%rsp), %rax
leaq 1(%rax), %rcx
movq %rcx, (%rsp)
movsd %xmm1, 200(%rsp) # 8-byte Spill
movsd %xmm1, 256(%rsp,%rax,8)
cmpq 56(%rsp), %rcx
jne .LBB4_12
# %bb.9: # in Loop: Header=BB4_7 Depth=2
movq 24(%rsp), %rdi
leaq 256(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $8, %edx
leaq 56(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_7 Depth=2
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z2RSPKdPKmPdPK7table_t, %edi
leaq 160(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_11
.LBB4_14: # %._crit_edge
cmpq $0, (%rsp)
je .LBB4_18
# %bb.15:
movq 24(%rsp), %rdi
leaq 256(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rsp, %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
movq 192(%rsp), %rax # 8-byte Reload
leaq (%rdx,%rax), %rdi
addq $-256, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z2RSPKdPKmPdPK7table_t, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_17:
movq 16(%rsp), %rsi
leaq 65792(%rsp), %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
.LBB4_18:
movq (%rsp), %rax
leaq -20(%rax), %rcx
xorl %ebx, %ebx
cmpq $20, %rax
cmovaeq %rcx, %rbx
cmpq %rax, %rbx
jae .LBB4_20
.p2align 4, 0x90
.LBB4_19: # %.lr.ph103
# =>This Inner Loop Header: Depth=1
movsd 256(%rsp,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movsd 65792(%rsp,%rbx,8), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.12, %edi
movb $2, %al
callq printf
incq %rbx
cmpq (%rsp), %rbx
jb .LBB4_19
.LBB4_20: # %._crit_edge104
callq clock
subq 232(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $131336, %rsp # imm = 0x20108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_22:
.cfi_def_cfa_offset 131392
movl $.Lstr.6, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB4_21:
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11build_tableP7table_t, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2RSPKdPKmPdPK7table_t, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11build_tableP7table_t,@object # @_Z11build_tableP7table_t
.section .rodata,"a",@progbits
.globl _Z11build_tableP7table_t
.p2align 3, 0x0
_Z11build_tableP7table_t:
.quad _Z26__device_stub__build_tableP7table_t
.size _Z11build_tableP7table_t, 8
.type _Z2RSPKdPKmPdPK7table_t,@object # @_Z2RSPKdPKmPdPK7table_t
.globl _Z2RSPKdPKmPdPK7table_t
.p2align 3, 0x0
_Z2RSPKdPKmPdPK7table_t:
.quad _Z17__device_stub__RSPKdPKmPdPK7table_t
.size _Z2RSPKdPKmPdPK7table_t, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%f seconds elapsed.\n"
.size .L.str.3, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to open file %s for binary input. Exiting.\n"
.size .L.str.6, 51
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Found %d CUDA devices.\n"
.size .L.str.7, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Doing %ld iterations on file %s.\n"
.size .L.str.10, 34
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Zero at %f rs returned %f\n"
.size .L.str.12, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11build_tableP7table_t"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2RSPKdPKmPdPK7table_t"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Fatal error in in_bytes (c). Exiting."
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Fatal error in in_bytes (b). Exiting."
.size .Lstr.1, 38
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Fatal error in in_bytes (a). Exiting."
.size .Lstr.2, 38
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "In main"
.size .Lstr.3, 8
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Allocating device memory for sin_table"
.size .Lstr.4, 39
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Allocating other device memory."
.size .Lstr.5, 32
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Two zeros 0 apart. Exiting."
.size .Lstr.6, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__build_tableP7table_t
.addrsig_sym _Z17__device_stub__RSPKdPKmPdPK7table_t
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11build_tableP7table_t
.addrsig_sym _Z2RSPKdPKmPdPK7table_t
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0015bd1a_00000000-6_rs_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Fatal error in in_bytes (a). Exiting.\n"
.align 8
.LC1:
.string "Fatal error in in_bytes (b). Exiting.\n"
.align 8
.LC2:
.string "Fatal error in in_bytes (c). Exiting.\n"
.text
.globl _Z8in_bytesP8_IO_FILE
.type _Z8in_bytesP8_IO_FILE, @function
_Z8in_bytesP8_IO_FILE:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $8, %edx
movl $8, %esi
call __fread_chk@PLT
cmpq $1, %rax
je .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L4:
leaq 12(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
cmpq $1, %rax
je .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L5:
leaq 11(%rsp), %rdi
movq %rbx, %r8
movl $1, %ecx
movl $1, %edx
movl $1, %esi
call __fread_chk@PLT
cmpq $1, %rax
jne .L13
movzbl 11(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC3(%rip), %xmm0
movl 12(%rsp), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC4(%rip), %xmm1
addsd %xmm1, %xmm0
movabsq $-2251799813685248, %rax
andq 16(%rsp), %rax
js .L9
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
.L10:
mulsd .LC5(%rip), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L9:
shrq %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L10
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8in_bytesP8_IO_FILE, .-_Z8in_bytesP8_IO_FILE
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "%f seconds elapsed.\n"
.text
.globl _Z13print_elapsedl
.type _Z13print_elapsedl, @function
_Z13print_elapsedl:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13print_elapsedl, .-_Z13print_elapsedl
.globl _Z38__device_stub__Z11build_tableP7table_tP7table_t
.type _Z38__device_stub__Z11build_tableP7table_tP7table_t, @function
_Z38__device_stub__Z11build_tableP7table_tP7table_t:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11build_tableP7table_t(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z11build_tableP7table_tP7table_t, .-_Z38__device_stub__Z11build_tableP7table_tP7table_t
.globl _Z11build_tableP7table_t
.type _Z11build_tableP7table_t, @function
_Z11build_tableP7table_t:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11build_tableP7table_tP7table_t
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11build_tableP7table_t, .-_Z11build_tableP7table_t
.globl _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
.type _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t, @function
_Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2RSPKdPKmPdPK7table_t(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t, .-_Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
.globl _Z2RSPKdPKmPdPK7table_t
.type _Z2RSPKdPKmPdPK7table_t, @function
_Z2RSPKdPKmPdPK7table_t:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z2RSPKdPKmPdPK7table_t, .-_Z2RSPKdPKmPdPK7table_t
.section .rodata.str1.1
.LC8:
.string "In main\n"
.LC9:
.string "rb"
.section .rodata.str1.8
.align 8
.LC10:
.string "Failed to open file %s for binary input. Exiting.\n"
.section .rodata.str1.1
.LC11:
.string "Found %d CUDA devices.\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Allocating device memory for sin_table\n"
.align 8
.LC13:
.string "Allocating other device memory.\n"
.align 8
.LC14:
.string "Doing %ld iterations on file %s.\n"
.section .rodata.str1.1
.LC16:
.string "Two zeros 0 apart. Exiting.\n"
.LC17:
.string "Zero at %f rs returned %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -131072(%rsp), %r11
.cfi_def_cfa 11, 131128
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $184, %rsp
.cfi_def_cfa_offset 131312
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 131240(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 24(%rsp)
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %rdi
leaq .LC9(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L58
movq %rax, %r12
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 44(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %r15
movq %r15, %rdi
call _Z13print_elapsedl
leaq 48(%rsp), %rdi
movl $3200016, %esi
call cudaMalloc@PLT
movq $8192, 120(%rsp)
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call _Z13print_elapsedl
movq 120(%rsp), %rax
leaq 0(,%rax,8), %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $782, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L35:
movq 120(%rsp), %rcx
movq %rcx, %rdx
shrq $8, %rdx
movl %edx, %eax
sall $8, %eax
cltq
cmpq %rcx, %rax
movl %edx, %eax
adcl $0, %eax
movl %eax, 20(%rsp)
leaq 80(%rsp), %rdi
movq %r12, %r8
movl $1, %ecx
movl $8, %edx
movl $8, %esi
call __fread_chk@PLT
movq 8(%rbx), %rcx
movq 80(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 88(%rsp)
cmpq $0, 80(%rsp)
jle .L48
movl $0, %r13d
leaq 128(%rsp), %r15
leaq 144(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L45
.L58:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L59:
movq 48(%rsp), %rdi
call _Z38__device_stub__Z11build_tableP7table_tP7table_t
jmp .L35
.L60:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
leaq 65696(%rsp), %rdi
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movq $0, 88(%rsp)
.L42:
addq $1, %rbp
cmpq %rbp, 152(%rsp)
jl .L38
.L44:
movq %r12, %rdi
call _Z8in_bytesP8_IO_FILE
pxor %xmm3, %xmm3
ucomisd %xmm3, %xmm0
jp .L40
je .L60
.L40:
movq %rbx, %xmm2
addsd %xmm0, %xmm2
movq %xmm2, %rbx
movq 88(%rsp), %rdx
leaq 1(%rdx), %rax
movq %rax, 88(%rsp)
movsd %xmm2, 160(%rsp,%rdx,8)
cmpq 120(%rsp), %rax
jne .L42
leaq 160(%rsp), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl 20(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movq 48(%rsp), %rcx
movq 64(%rsp), %rdx
movq 72(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
jmp .L43
.L38:
addq $1, %r13
cmpq %r13, 80(%rsp)
jle .L53
cmpq $100, %r13
je .L53
.L45:
movq %r12, %r8
movl $2, %ecx
movl $8, %edx
movl $16, %esi
movq %r15, %rdi
call __fread_chk@PLT
movq %r12, %r8
movl $1, %ecx
movl $8, %edx
movl $16, %esi
movq 8(%rsp), %rdi
call __fread_chk@PLT
movq 128(%rsp), %rbx
movq %rbx, %xmm5
pxor %xmm6, %xmm6
ucomisd %xmm6, %xmm5
jp .L51
je .L38
.L51:
leaq 152(%rsp), %rdi
movq %r12, %r8
movl $1, %ecx
movl $8, %edx
movl $8, %esi
call __fread_chk@PLT
movq 144(%rsp), %rax
leaq 1(%rax), %rbp
cmpq 152(%rsp), %rbp
jle .L44
jmp .L38
.L53:
cmpq $0, 88(%rsp)
je .L48
leaq 160(%rsp), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl 20(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L47:
leaq 65696(%rsp), %rdi
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
movl $20, %ebx
cmpq %rbx, %rax
cmovnb %rax, %rbx
subq $20, %rbx
cmpq %rax, %rbx
jnb .L48
leaq .LC17(%rip), %rbp
.L49:
movsd 160(%rsp,%rbx,8), %xmm0
movsd 65696(%rsp,%rbx,8), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq 88(%rsp), %rbx
jb .L49
.L48:
movq 24(%rsp), %rdi
call _Z13print_elapsedl
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 131240(%rsp), %rax
subq %fs:40, %rax
jne .L62
movl $0, %eax
addq $131256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movq 48(%rsp), %rcx
movq 64(%rsp), %rdx
movq 72(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z37__device_stub__Z2RSPKdPKmPdPK7table_tPKdPKmPdPK7table_t
jmp .L47
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z2RSPKdPKmPdPK7table_t"
.LC19:
.string "_Z11build_tableP7table_t"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z2RSPKdPKmPdPK7table_t(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z11build_tableP7table_t(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1067450368
.align 8
.LC4:
.long 0
.long 1033895936
.align 8
.LC5:
.long 0
.long 966787072
.align 8
.LC6:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "rs_double.hip"
.globl _Z26__device_stub__build_tableP7table_t # -- Begin function _Z26__device_stub__build_tableP7table_t
.p2align 4, 0x90
.type _Z26__device_stub__build_tableP7table_t,@function
_Z26__device_stub__build_tableP7table_t: # @_Z26__device_stub__build_tableP7table_t
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11build_tableP7table_t, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__build_tableP7table_t, .Lfunc_end0-_Z26__device_stub__build_tableP7table_t
.cfi_endproc
# -- End function
.globl _Z17__device_stub__RSPKdPKmPdPK7table_t # -- Begin function _Z17__device_stub__RSPKdPKmPdPK7table_t
.p2align 4, 0x90
.type _Z17__device_stub__RSPKdPKmPdPK7table_t,@function
_Z17__device_stub__RSPKdPKmPdPK7table_t: # @_Z17__device_stub__RSPKdPKmPdPK7table_t
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2RSPKdPKmPdPK7table_t, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z17__device_stub__RSPKdPKmPdPK7table_t, .Lfunc_end1-_Z17__device_stub__RSPKdPKmPdPK7table_t
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8in_bytesP8_IO_FILE
.LCPI2_0:
.quad 0x3fa0000000000000 # double 0.03125
.LCPI2_1:
.quad 0x3da0000000000000 # double 7.2759576141834259E-12
.LCPI2_4:
.quad 0x39a0000000000000 # double 3.944304526105059E-31
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_3:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z8in_bytesP8_IO_FILE
.p2align 4, 0x90
.type _Z8in_bytesP8_IO_FILE,@function
_Z8in_bytesP8_IO_FILE: # @_Z8in_bytesP8_IO_FILE
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movl $8, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB2_1
# %bb.3:
leaq 4(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB2_4
# %bb.5:
leaq 3(%rsp), %rdi
movl $1, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB2_6
# %bb.7:
movzbl 3(%rsp), %eax
cvtsi2sd %eax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movl 4(%rsp), %eax
cvtsi2sd %rax, %xmm1
mulsd .LCPI2_1(%rip), %xmm1
movabsq $-2251799813685248, %rax # imm = 0xFFF8000000000000
andq 8(%rsp), %rax
movq %rax, %xmm2
punpckldq .LCPI2_2(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI2_3(%rip), %xmm2
addsd %xmm0, %xmm1
movapd %xmm2, %xmm0
unpckhpd %xmm2, %xmm0 # xmm0 = xmm0[1],xmm2[1]
addsd %xmm2, %xmm0
mulsd .LCPI2_4(%rip), %xmm0
addsd %xmm1, %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 32
movl $.Lstr.2, %edi
jmp .LBB2_2
.LBB2_4:
movl $.Lstr.1, %edi
jmp .LBB2_2
.LBB2_6:
movl $.Lstr, %edi
.LBB2_2:
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z8in_bytesP8_IO_FILE, .Lfunc_end2-_Z8in_bytesP8_IO_FILE
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13print_elapsedl
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z13print_elapsedl
.p2align 4, 0x90
.type _Z13print_elapsedl,@function
_Z13print_elapsedl: # @_Z13print_elapsedl
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z13print_elapsedl, .Lfunc_end3-_Z13print_elapsedl
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $131336, %rsp # imm = 0x20108
.cfi_def_cfa_offset 131392
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
callq clock
movq %rax, %rbx
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%r13), %rdi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_21
# %bb.1:
movq %rax, %r12
movabsq $4294967552, %r14 # imm = 0x100000100
leaq 140(%rsp), %rdi
callq hipGetDeviceCount
movl 140(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
movl $.Lstr.4, %edi
callq puts@PLT
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
leaq 64(%rsp), %rdi
movl $3200016, %esi # imm = 0x30D410
callq hipMalloc
movq $8192, 56(%rsp) # imm = 0x2000
movl $.Lstr.5, %edi
callq puts@PLT
callq clock
movq %rbx, 232(%rsp) # 8-byte Spill
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 56(%rsp), %r15
shlq $3, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 526(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_3
# %bb.2:
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 256(%rsp), %rdi
leaq 65792(%rsp), %rsi
leaq 208(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 256(%rsp), %rsi
movl 264(%rsp), %edx
movq 65792(%rsp), %rcx
movl 65800(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z11build_tableP7table_t, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_3:
movq 56(%rsp), %rax
movq %rax, %r14
shrq $8, %r14
movl %r14d, %ecx
shll $8, %ecx
movslq %ecx, %rcx
cmpq %rax, %rcx
adcl $0, %r14d
leaq 248(%rsp), %rdi
movl $8, %esi
movl $1, %edx
movq %r12, %rcx
callq fread
movq 248(%rsp), %rbx
movq 8(%r13), %rdx
movl $.L.str.10, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq $0, (%rsp)
movl %r14d, %eax
movq %rax, 192(%rsp) # 8-byte Spill
testq %rbx, %rbx
jle .LBB4_14
# %bb.4: # %.lr.ph100
movabsq $4294967552, %rax # imm = 0x100000100
movq 192(%rsp), %rcx # 8-byte Reload
leaq (%rax,%rcx), %rbp
addq $-256, %rbp
decq %rbx
cmpq $99, %rbx
movl $99, %eax
cmovbq %rbx, %rax
movq %rax, 240(%rsp) # 8-byte Spill
xorl %ebx, %ebx
leaq 65792(%rsp), %r14
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_13: # %.loopexit
# in Loop: Header=BB4_5 Depth=1
leaq 1(%rbx), %rax
cmpq 240(%rsp), %rbx # 8-byte Folded Reload
movq %rax, %rbx
je .LBB4_14
.LBB4_5: # =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
movl $8, %esi
movl $2, %edx
leaq 208(%rsp), %rdi
movq %r12, %rcx
callq fread
movl $8, %esi
movl $1, %edx
leaq 144(%rsp), %rdi
movq %r12, %rcx
callq fread
movsd 208(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 200(%rsp) # 8-byte Spill
ucomisd .LCPI4_1(%rip), %xmm0
jne .LBB4_6
jnp .LBB4_13
.LBB4_6: # in Loop: Header=BB4_5 Depth=1
movl $8, %esi
movl $1, %edx
leaq 152(%rsp), %rdi
movq %r12, %rcx
callq fread
movq 152(%rsp), %r13
subq 144(%rsp), %r13
jg .LBB4_7
jmp .LBB4_13
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_7 Depth=2
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq $0, (%rsp)
.LBB4_12: # in Loop: Header=BB4_7 Depth=2
decq %r13
je .LBB4_13
.LBB4_7: # %.lr.ph
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
callq _Z8in_bytesP8_IO_FILE
ucomisd .LCPI4_1(%rip), %xmm0
jne .LBB4_8
jnp .LBB4_22
.LBB4_8: # in Loop: Header=BB4_7 Depth=2
movsd 200(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movq (%rsp), %rax
leaq 1(%rax), %rcx
movq %rcx, (%rsp)
movsd %xmm1, 200(%rsp) # 8-byte Spill
movsd %xmm1, 256(%rsp,%rax,8)
cmpq 56(%rsp), %rcx
jne .LBB4_12
# %bb.9: # in Loop: Header=BB4_7 Depth=2
movq 24(%rsp), %rdi
leaq 256(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $8, %edx
leaq 56(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_7 Depth=2
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z2RSPKdPKmPdPK7table_t, %edi
leaq 160(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_11
.LBB4_14: # %._crit_edge
cmpq $0, (%rsp)
je .LBB4_18
# %bb.15:
movq 24(%rsp), %rdi
leaq 256(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rsp, %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
movq 192(%rsp), %rax # 8-byte Reload
leaq (%rdx,%rax), %rdi
addq $-256, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z2RSPKdPKmPdPK7table_t, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_17:
movq 16(%rsp), %rsi
leaq 65792(%rsp), %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
.LBB4_18:
movq (%rsp), %rax
leaq -20(%rax), %rcx
xorl %ebx, %ebx
cmpq $20, %rax
cmovaeq %rcx, %rbx
cmpq %rax, %rbx
jae .LBB4_20
.p2align 4, 0x90
.LBB4_19: # %.lr.ph103
# =>This Inner Loop Header: Depth=1
movsd 256(%rsp,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movsd 65792(%rsp,%rbx,8), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.12, %edi
movb $2, %al
callq printf
incq %rbx
cmpq (%rsp), %rbx
jb .LBB4_19
.LBB4_20: # %._crit_edge104
callq clock
subq 232(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $131336, %rsp # imm = 0x20108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_22:
.cfi_def_cfa_offset 131392
movl $.Lstr.6, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB4_21:
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11build_tableP7table_t, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2RSPKdPKmPdPK7table_t, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11build_tableP7table_t,@object # @_Z11build_tableP7table_t
.section .rodata,"a",@progbits
.globl _Z11build_tableP7table_t
.p2align 3, 0x0
_Z11build_tableP7table_t:
.quad _Z26__device_stub__build_tableP7table_t
.size _Z11build_tableP7table_t, 8
.type _Z2RSPKdPKmPdPK7table_t,@object # @_Z2RSPKdPKmPdPK7table_t
.globl _Z2RSPKdPKmPdPK7table_t
.p2align 3, 0x0
_Z2RSPKdPKmPdPK7table_t:
.quad _Z17__device_stub__RSPKdPKmPdPK7table_t
.size _Z2RSPKdPKmPdPK7table_t, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%f seconds elapsed.\n"
.size .L.str.3, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to open file %s for binary input. Exiting.\n"
.size .L.str.6, 51
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Found %d CUDA devices.\n"
.size .L.str.7, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Doing %ld iterations on file %s.\n"
.size .L.str.10, 34
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Zero at %f rs returned %f\n"
.size .L.str.12, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11build_tableP7table_t"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2RSPKdPKmPdPK7table_t"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Fatal error in in_bytes (c). Exiting."
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Fatal error in in_bytes (b). Exiting."
.size .Lstr.1, 38
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Fatal error in in_bytes (a). Exiting."
.size .Lstr.2, 38
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "In main"
.size .Lstr.3, 8
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Allocating device memory for sin_table"
.size .Lstr.4, 39
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Allocating other device memory."
.size .Lstr.5, 32
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Two zeros 0 apart. Exiting."
.size .Lstr.6, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__build_tableP7table_t
.addrsig_sym _Z17__device_stub__RSPKdPKmPdPK7table_t
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11build_tableP7table_t
.addrsig_sym _Z2RSPKdPKmPdPK7table_t
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/******************************************************************************
*cr
*cr (C) Copyright 2010-2013 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)
// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048
// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128
/******************************************************************************
GPU kernels
*******************************************************************************/
__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
unsigned int iterator;
//unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int nodeInformation;
unsigned int iteratorNode;
unsigned int count;
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
// Do your computation here
// INSERT KERNEL CODE HERE
//for every node in the queue, we run this.
count = 0;
if(idx< *numCurrLevelNodes)
{
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
count++;
}
}
}
}
//__syncthreads();
}
__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
//have a queue in local thread copy. When thread computation completed,
//Initialization of Variables
__shared__ unsigned int localQueue[BQ_CAPACITY];
__shared__ unsigned int totalCount;
__shared__ unsigned int numberOfElementsToCopy;
__shared__ unsigned int queueStart;
int iterator;
unsigned int nodeInformation;
unsigned int iteratorNode;
int tid = threadIdx.x+blockIdx.x * blockDim.x;
//Initializing queue count
if(threadIdx.x == 0)
{
totalCount = 0;
}
__syncthreads();
//sync all the threads at this point as
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
//for every node in the queue, we run this.
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
int previousNodeVal = atomicAdd(&(totalCount),1);
if (previousNodeVal < BQ_CAPACITY){
//if the load is less than capacty. Load this in the local queue of thread
localQueue[previousNodeVal] = iteratorNode;
}
else {
//if block queue is saturated, we cannot place next level node in local queue.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
totalCount = BQ_CAPACITY; // if total count exceeds the capacity.
}
}
}
}
//preprocessing per local thread complete. Now, syncing threads
__syncthreads();
//for first thread, increment the global pointer for the next block.
if(blockIdx.x*blockDim.x < *numCurrLevelNodes)
{
//only let the first block to make changes globally.
if(threadIdx.x == 0)
{
//make the pointers incremented to the next level. So global threads can write parallely.
queueStart = atomicAdd(&(*numNextLevelNodes),totalCount);
//how many number should be copied.
numberOfElementsToCopy = ((totalCount-1)/BLOCK_SIZE +1);
}
__syncthreads();
//copy elements on a per thread basis.
for(unsigned int iter = 0;iter < numberOfElementsToCopy; iter++)
{
int index = threadIdx.x*numberOfElementsToCopy;
if( index + iter < totalCount)
{
//no element more than this should be copied.
nextLevelNodes[queueStart + index + iter] = localQueue[index+iter];
}
}
}
}
__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
}
/******************************************************************************
Functions
*******************************************************************************/
void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
// Loop over all nodes in the curent level
for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
unsigned int node = currLevelNodes[idx];
// Loop over all neighbors of the node
for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
++nbrIdx) {
unsigned int neighbor = nodeNeighbors[nbrIdx];
// If the neighbor hasn't been visited yet
if(!nodeVisited[neighbor]) {
// Mark it and add it to the queue
nodeVisited[neighbor] = 1;
nextLevelNodes[*numNextLevelNodes] = neighbor;
++(*numNextLevelNodes);
}
}
}
}
void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
|
code for sm_80
Function : _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0060*/ @!P0 STS [0x2000], RZ ; /* 0x002000ffff008388 */
/* 0x000fe80000000800 */
/*0070*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0080*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea8000c1e1900 */
/*0090*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*00a0*/ IMAD R6, R7, c[0x0][0x0], R0 ; /* 0x0000000007067a24 */
/* 0x001fca00078e0200 */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fda0003f26070 */
/*00c0*/ @P1 BRA 0x510 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*00e0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.WIDE.U32 R8, R6, R17, c[0x0][0x178] ; /* 0x00005e0006087625 */
/* 0x000fcc00078e0011 */
/*0100*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IADD3 R4, R8.reuse, 0x1, RZ ; /* 0x0000000108047810 */
/* 0x044fe20007ffe0ff */
/*0120*/ IMAD.WIDE.U32 R10, R8, R17, c[0x0][0x160] ; /* 0x00005800080a7625 */
/* 0x000fc800078e0011 */
/*0130*/ IMAD.WIDE.U32 R4, R4, R17, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0011 */
/*0140*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x4d0 ; /* 0x0000036000007945 */
/* 0x000fe20003800000 */
/*0170*/ ISETP.GE.U32.AND P1, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x004fda0003f26070 */
/*0180*/ @P1 BRA 0x4c0 ; /* 0x0000033000001947 */
/* 0x001fea0003800000 */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*01a0*/ BSSY B1, 0x4b0 ; /* 0x0000030000017945 */
/* 0x000fe60003800000 */
/*01b0*/ IMAD.WIDE R10, R8, R17, c[0x0][0x168] ; /* 0x00005a00080a7625 */
/* 0x000fca00078e0211 */
/*01c0*/ LDG.E R9, [R10.64] ; /* 0x000000060a097981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c7424 */
/* 0x000fe200078e00ff */
/*01e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.WIDE.U32 R14, R9, R12, c[0x0][0x170] ; /* 0x00005c00090e7625 */
/* 0x004fcc00078e000c */
/*0210*/ ATOMG.E.ADD.STRONG.GPU PT, R14, [R14.64], R13 ; /* 0x0000000d0e0e79a8 */
/* 0x000ea200081ee1c6 */
/*0220*/ BSSY B2, 0x440 ; /* 0x0000021000027945 */
/* 0x000fe20003800000 */
/*0230*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x004fda0003f25270 */
/*0240*/ @P1 BRA 0x430 ; /* 0x000001e000001947 */
/* 0x000fea0003800000 */
/*0250*/ S2R R16, SR_LANEID ; /* 0x0000000000107919 */
/* 0x000e220000000000 */
/*0260*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0270*/ FLO.U32 R15, UR4 ; /* 0x00000004000f7d00 */
/* 0x000e2200080e0000 */
/*0280*/ S2R R17, SR_LTMASK ; /* 0x0000000000117919 */
/* 0x000e6e0000003900 */
/*0290*/ POPC R13, UR4 ; /* 0x00000004000d7d09 */
/* 0x000ea20008000000 */
/*02a0*/ ISETP.EQ.U32.AND P1, PT, R15, R16, PT ; /* 0x000000100f00720c */
/* 0x001fc40003f22070 */
/*02b0*/ LOP3.LUT R19, R17, UR4, RZ, 0xc0, !PT ; /* 0x0000000411137c12 */
/* 0x002fcc000f8ec0ff */
/*02c0*/ POPC R19, R19 ; /* 0x0000001300137309 */
/* 0x000e2a0000000000 */
/*02d0*/ @P1 ATOMS.ADD R18, [0x2000], R13 ; /* 0x0020000dff12138c */
/* 0x004e680000000000 */
/*02e0*/ SHFL.IDX PT, R14, R18, R15, 0x1f ; /* 0x00001f0f120e7589 */
/* 0x002e2400000e0000 */
/*02f0*/ IMAD.IADD R14, R14, 0x1, R19 ; /* 0x000000010e0e7824 */
/* 0x001fca00078e0213 */
/*0300*/ ISETP.GE.AND P1, PT, R14, 0x800, PT ; /* 0x000008000e00780c */
/* 0x000fda0003f26270 */
/*0310*/ @!P1 BRA 0x420 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0320*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0330*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0e7624 */
/* 0x000fe200078e00ff */
/*0340*/ FLO.U32 R21, UR4 ; /* 0x0000000400157d00 */
/* 0x000e2200080e0000 */
/*0350*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0f7624 */
/* 0x000fce00078e00ff */
/*0360*/ POPC R19, UR4 ; /* 0x0000000400137d09 */
/* 0x000e620008000000 */
/*0370*/ ISETP.EQ.U32.AND P1, PT, R21, R16, PT ; /* 0x000000101500720c */
/* 0x001fda0003f22070 */
/*0380*/ @P1 ATOMG.E.ADD.STRONG.GPU PT, R14, [R14.64], R19 ; /* 0x000000130e0e19a8 */
/* 0x002ea200081ee1c6 */
/*0390*/ LOP3.LUT R17, R17, UR4, RZ, 0xc0, !PT ; /* 0x0000000411117c12 */
/* 0x000fc8000f8ec0ff */
/*03a0*/ POPC R16, R17 ; /* 0x0000001100107309 */
/* 0x000e220000000000 */
/*03b0*/ SHFL.IDX PT, R13, R14, R21, 0x1f ; /* 0x00001f150e0d7589 */
/* 0x004e2400000e0000 */
/*03c0*/ IMAD.IADD R13, R13, 0x1, R16 ; /* 0x000000010d0d7824 */
/* 0x001fe400078e0210 */
/*03d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x800 ; /* 0x00000800ff107424 */
/* 0x000fe400078e00ff */
/*03e0*/ IMAD.WIDE.U32 R12, R13, R12, c[0x0][0x180] ; /* 0x000060000d0c7625 */
/* 0x000fc600078e000c */
/*03f0*/ STS [0x2000], R16 ; /* 0x00200010ff007388 */
/* 0x0001e80000000800 */
/*0400*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e2000c101906 */
/*0410*/ BRA 0x430 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0420*/ STS [R14.X4], R9 ; /* 0x000000090e007388 */
/* 0x0001e40000004800 */
/*0430*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0440*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x001ea2000c1e1900 */
/*0450*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R10, P2, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fca0007f5e0ff */
/*0470*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0480*/ ISETP.GE.U32.AND P1, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x004fda0003f26070 */
/*0490*/ @!P1 BRA 0x1c0 ; /* 0xfffffd2000009947 */
/* 0x000fea000383ffff */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04b0*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000164000c1e1900 */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fc800078e00ff */
/*04e0*/ IMAD R6, R5, c[0x0][0xc], R6 ; /* 0x0000030005067a24 */
/* 0x000fca00078e0206 */
/*04f0*/ ISETP.GE.U32.AND P1, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x020fda0003f26070 */
/*0500*/ @!P1 BRA 0xe0 ; /* 0xfffffbd000009947 */
/* 0x000fea000383ffff */
/*0510*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x001ea2000c1e1900 */
/*0540*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fca00078e02ff */
/*0550*/ ISETP.GE.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f26070 */
/*0560*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0570*/ BSSY B0, 0x620 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0580*/ @P0 BRA 0x610 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0590*/ LDS R5, [0x2000] ; /* 0x00200000ff057984 */
/* 0x000e220000000800 */
/*05a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff027624 */
/* 0x000fe400078e00ff */
/*05b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff037624 */
/* 0x000fca00078e00ff */
/*05c0*/ ATOMG.E.ADD.STRONG.GPU PT, R2, [R2.64], R5 ; /* 0x00000005020279a8 */
/* 0x001ea200081ee1c6 */
/*05d0*/ IADD3 R4, R5, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ LEA.HI R4, R4, 0x1, RZ, 0x17 ; /* 0x0000000104047811 */
/* 0x000fca00078fb8ff */
/*05f0*/ STS [0x2004], R4 ; /* 0x00200404ff007388 */
/* 0x0001e80000000800 */
/*0600*/ STS [0x2008], R2 ; /* 0x00200802ff007388 */
/* 0x0041e40000000800 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0630*/ LDS.128 R4, [0x2000] ; /* 0x00200000ff047984 */
/* 0x001e240000000c00 */
/*0640*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x001fda0003f05270 */
/*0650*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0660*/ IADD3 R2, R5.reuse, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x040fe20007ffe0ff */
/*0670*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0680*/ LOP3.LUT R14, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x00000003050e7812 */
/* 0x040fe200078ec0ff */
/*0690*/ IMAD R7, R5, R0, RZ ; /* 0x0000000005077224 */
/* 0x000fe200078e02ff */
/*06a0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*06b0*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f05270 */
/*06c0*/ @!P1 BRA 0x960 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.IADD R16, R7.reuse, 0x1, R6 ; /* 0x0000000107107824 */
/* 0x040fe200078e0206 */
/*06e0*/ IADD3 R17, R7.reuse, 0x3, RZ ; /* 0x0000000307117810 */
/* 0x040fe20007ffe0ff */
/*06f0*/ IMAD.IADD R5, R14, 0x1, -R5 ; /* 0x000000010e057824 */
/* 0x000fe200078e0a05 */
/*0700*/ IADD3 R18, R7.reuse, 0x1, RZ ; /* 0x0000000107127810 */
/* 0x040fe20007ffe0ff */
/*0710*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0720*/ LEA R15, R7, 0x8, 0x2 ; /* 0x00000008070f7811 */
/* 0x000fe400078e10ff */
/*0730*/ IADD3 R0, R16.reuse, 0x3, RZ ; /* 0x0000000310007810 */
/* 0x040fe40007ffe0ff */
/*0740*/ IADD3 R20, R16, 0x1, RZ ; /* 0x0000000110147810 */
/* 0x000fe40007ffe0ff */
/*0750*/ IADD3 R3, R7, UR4, RZ ; /* 0x0000000407037c10 */
/* 0x001fe4000fffe0ff */
/*0760*/ IADD3 R9, R18, UR4, RZ ; /* 0x0000000412097c10 */
/* 0x000fc4000fffe0ff */
/*0770*/ IADD3 R11, R17, -0x1, RZ ; /* 0xffffffff110b7810 */
/* 0x000fe40007ffe0ff */
/*0780*/ ISETP.GE.U32.AND P1, PT, R3, R4.reuse, PT ; /* 0x000000040300720c */
/* 0x080fe40003f26070 */
/*0790*/ ISETP.GE.U32.AND P2, PT, R9, R4.reuse, PT ; /* 0x000000040900720c */
/* 0x080fe40003f46070 */
/*07a0*/ ISETP.GE.U32.AND P3, PT, R11, R4.reuse, PT ; /* 0x000000040b00720c */
/* 0x080fe40003f66070 */
/*07b0*/ ISETP.GE.U32.AND P4, PT, R17.reuse, R4, PT ; /* 0x000000041100720c */
/* 0x040fe40003f86070 */
/*07c0*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fca0007ffe0ff */
/*07d0*/ @!P1 LDS R25, [R15+-0x8] ; /* 0xfffff8000f199984 */
/* 0x000e220000000800 */
/*07e0*/ @!P1 IADD3 R2, R16, UR4, RZ ; /* 0x0000000410029c10 */
/* 0x000fe2000fffe0ff */
/*07f0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fe200078e00ff */
/*0800*/ @!P2 IADD3 R8, R20, UR4, RZ ; /* 0x000000041408ac10 */
/* 0x000fe2000fffe0ff */
/*0810*/ @!P2 LDS R23, [R15+-0x4] ; /* 0xfffffc000f17a984 */
/* 0x000e620000000800 */
/*0820*/ @!P2 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff09a424 */
/* 0x000fe200078e00ff */
/*0830*/ @!P3 IADD3 R10, R0, -0x1, RZ ; /* 0xffffffff000ab810 */
/* 0x000fe20007ffe0ff */
/*0840*/ @!P3 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0bb424 */
/* 0x000fe200078e00ff */
/*0850*/ @!P3 LDS R21, [R15] ; /* 0x000000000f15b984 */
/* 0x000ea20000000800 */
/*0860*/ @!P4 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0dc424 */
/* 0x000fe200078e00ff */
/*0870*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0880*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002029625 */
/* 0x000fe200078e0003 */
/*0890*/ @!P4 LDS R19, [R15+0x4] ; /* 0x000004000f13c984 */
/* 0x0007260000000800 */
/*08a0*/ @!P2 IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x000060000808a625 */
/* 0x000fe200078e0009 */
/*08b0*/ IADD3 R22, R5, UR4, RZ ; /* 0x0000000405167c10 */
/* 0x000fc6000fffe0ff */
/*08c0*/ @!P3 IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x180] ; /* 0x000060000a0ab625 */
/* 0x000fe200078e000b */
/*08d0*/ IADD3 R15, R15, 0x10, RZ ; /* 0x000000100f0f7810 */
/* 0x008fc60007ffe0ff */
/*08e0*/ @!P4 IMAD.WIDE.U32 R12, R0.reuse, R13, c[0x0][0x180] ; /* 0x00006000000cc625 */
/* 0x040fe200078e000d */
/*08f0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0900*/ @!P1 STG.E [R2.64], R25 ; /* 0x0000001902009986 */
/* 0x0011e2000c101906 */
/*0910*/ ISETP.NE.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc60003f25270 */
/*0920*/ @!P2 STG.E [R8.64], R23 ; /* 0x000000170800a986 */
/* 0x0021e8000c101906 */
/*0930*/ @!P3 STG.E [R10.64], R21 ; /* 0x000000150a00b986 */
/* 0x0041e8000c101906 */
/*0940*/ @!P4 STG.E [R12.64], R19 ; /* 0x000000130c00c986 */
/* 0x0101e4000c101906 */
/*0950*/ @P1 BRA 0x750 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0960*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0970*/ IADD3 R5, R7.reuse, UR4, RZ ; /* 0x0000000407057c10 */
/* 0x040fe4000fffe0ff */
/*0980*/ IADD3 R6, R7, UR4, R6 ; /* 0x0000000407067c10 */
/* 0x000fc6000fffe006 */
/*0990*/ IMAD.SHL.U32 R0, R5, 0x4, RZ ; /* 0x0000000405007824 */
/* 0x000fe400078e00ff */
/*09a0*/ ISETP.GE.U32.AND P0, PT, R5.reuse, R4, PT ; /* 0x000000040500720c */
/* 0x040fe40003f06070 */
/*09b0*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fd20007ffe0ff */
/*09d0*/ @!P0 LDS R7, [R0] ; /* 0x0000000000078984 */
/* 0x0002a20000000800 */
/*09e0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x001fc800078e00ff */
/*09f0*/ @!P0 IMAD.WIDE.U32 R2, R6.reuse, R3, c[0x0][0x180] ; /* 0x0000600006028625 */
/* 0x040fe200078e0003 */
/*0a00*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0a10*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x002fe40007ffe0ff */
/*0a20*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0041e2000c101906 */
/*0a30*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fda0003f05270 */
/*0a40*/ @P0 BRA 0x9a0 ; /* 0xffffff5000000947 */
/* 0x001fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x18c] ; /* 0x0000630000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0207 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f06070 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e0005 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fe20003f06070 */
/*00c0*/ BSSY B0, 0x3d0 ; /* 0x0000030000007945 */
/* 0x000fd80003800000 */
/*00d0*/ @P0 BRA 0x3c0 ; /* 0x000002e000000947 */
/* 0x003fea0003800000 */
/*00e0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fd400000001ff */
/*00f0*/ IMAD.WIDE.U32 R6, R0, R15, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fcc00078e000f */
/*0100*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IADD3 R4, R6.reuse, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x044fe20007ffe0ff */
/*0120*/ IMAD.WIDE.U32 R8, R6, R15, c[0x0][0x160] ; /* 0x0000580006087625 */
/* 0x000fc800078e000f */
/*0130*/ IMAD.WIDE.U32 R4, R4, R15, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e000f */
/*0140*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea4000c1e1900 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fda0003f06070 */
/*0170*/ @P0 BRA 0x3c0 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0190*/ BSSY B1, 0x3b0 ; /* 0x0000021000017945 */
/* 0x000fe60003800000 */
/*01a0*/ IMAD.WIDE.U32 R8, R6, R15, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fca00078e000f */
/*01b0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x001ea2000c1e1900 */
/*01c0*/ MOV R16, 0x4 ; /* 0x0000000400107802 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*01e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*01f0*/ IMAD.WIDE.U32 R10, R17, R16, c[0x0][0x170] ; /* 0x00005c00110a7625 */
/* 0x004fcc00078e0010 */
/*0200*/ ATOMG.E.ADD.STRONG.GPU PT, R10, [R10.64], R7 ; /* 0x000000070a0a79a8 */
/* 0x000ea200081ee1c4 */
/*0210*/ BSSY B2, 0x340 ; /* 0x0000012000027945 */
/* 0x000fe20003800000 */
/*0220*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0230*/ @P0 BRA 0x330 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*0240*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e220000000000 */
/*0250*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0260*/ MOV R10, c[0x0][0x190] ; /* 0x00006400000a7a02 */
/* 0x000fe20000000f00 */
/*0270*/ FLO.U32 R14, UR6 ; /* 0x00000006000e7d00 */
/* 0x000e3000080e0000 */
/*0280*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x000e620008000000 */
/*0290*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fe20003f02070 */
/*02a0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0b7624 */
/* 0x000fd800078e00ff */
/*02b0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R7, [R10.64], R7 ; /* 0x000000070a0709a8 */
/* 0x002ea800081ee1c4 */
/*02c0*/ S2R R13, SR_LTMASK ; /* 0x00000000000d7919 */
/* 0x000e240000003900 */
/*02d0*/ LOP3.LUT R15, R13, UR6, RZ, 0xc0, !PT ; /* 0x000000060d0f7c12 */
/* 0x001fcc000f8ec0ff */
/*02e0*/ POPC R15, R15 ; /* 0x0000000f000f7309 */
/* 0x000e220000000000 */
/*02f0*/ SHFL.IDX PT, R12, R7, R14, 0x1f ; /* 0x00001f0e070c7589 */
/* 0x004e2400000e0000 */
/*0300*/ IADD3 R12, R12, R15, RZ ; /* 0x0000000f0c0c7210 */
/* 0x001fca0007ffe0ff */
/*0310*/ IMAD.WIDE.U32 R12, R12, R16, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x000fca00078e0010 */
/*0320*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0001e4000c101904 */
/*0330*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fca0007f3e0ff */
/*0370*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0609 */
/*0380*/ ISETP.GE.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x004fda0003f06070 */
/*0390*/ @!P0 BRA 0x1b0 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*03a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03b0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000364000c1e1900 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fca0000000f00 */
/*03e0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x020fda0003f06070 */
/*0400*/ @!P0 BRA 0xb0 ; /* 0xfffffca000008947 */
/* 0x000fea000383ffff */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/******************************************************************************
*cr
*cr (C) Copyright 2010-2013 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)
// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048
// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128
/******************************************************************************
GPU kernels
*******************************************************************************/
__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
unsigned int iterator;
//unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int nodeInformation;
unsigned int iteratorNode;
unsigned int count;
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
// Do your computation here
// INSERT KERNEL CODE HERE
//for every node in the queue, we run this.
count = 0;
if(idx< *numCurrLevelNodes)
{
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
count++;
}
}
}
}
//__syncthreads();
}
__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
//have a queue in local thread copy. When thread computation completed,
//Initialization of Variables
__shared__ unsigned int localQueue[BQ_CAPACITY];
__shared__ unsigned int totalCount;
__shared__ unsigned int numberOfElementsToCopy;
__shared__ unsigned int queueStart;
int iterator;
unsigned int nodeInformation;
unsigned int iteratorNode;
int tid = threadIdx.x+blockIdx.x * blockDim.x;
//Initializing queue count
if(threadIdx.x == 0)
{
totalCount = 0;
}
__syncthreads();
//sync all the threads at this point as
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
//for every node in the queue, we run this.
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
int previousNodeVal = atomicAdd(&(totalCount),1);
if (previousNodeVal < BQ_CAPACITY){
//if the load is less than capacty. Load this in the local queue of thread
localQueue[previousNodeVal] = iteratorNode;
}
else {
//if block queue is saturated, we cannot place next level node in local queue.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
totalCount = BQ_CAPACITY; // if total count exceeds the capacity.
}
}
}
}
//preprocessing per local thread complete. Now, syncing threads
__syncthreads();
//for first thread, increment the global pointer for the next block.
if(blockIdx.x*blockDim.x < *numCurrLevelNodes)
{
//only let the first block to make changes globally.
if(threadIdx.x == 0)
{
//make the pointers incremented to the next level. So global threads can write parallely.
queueStart = atomicAdd(&(*numNextLevelNodes),totalCount);
//how many number should be copied.
numberOfElementsToCopy = ((totalCount-1)/BLOCK_SIZE +1);
}
__syncthreads();
//copy elements on a per thread basis.
for(unsigned int iter = 0;iter < numberOfElementsToCopy; iter++)
{
int index = threadIdx.x*numberOfElementsToCopy;
if( index + iter < totalCount)
{
//no element more than this should be copied.
nextLevelNodes[queueStart + index + iter] = localQueue[index+iter];
}
}
}
}
__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
}
/******************************************************************************
Functions
*******************************************************************************/
void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
// Loop over all nodes in the curent level
for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
unsigned int node = currLevelNodes[idx];
// Loop over all neighbors of the node
for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
++nbrIdx) {
unsigned int neighbor = nodeNeighbors[nbrIdx];
// If the neighbor hasn't been visited yet
if(!nodeVisited[neighbor]) {
// Mark it and add it to the queue
nodeVisited[neighbor] = 1;
nextLevelNodes[*numNextLevelNodes] = neighbor;
++(*numNextLevelNodes);
}
}
}
}
void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
|
.file "tmpxft_000b7d43_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cpu_queuingPjS_S_S_S_S_S_
.type _Z11cpu_queuingPjS_S_S_S_S_S_, @function
_Z11cpu_queuingPjS_S_S_S_S_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbx
movq 40(%rsp), %rdi
cmpl $0, (%r9)
je .L3
movq %rsi, %rbp
movq %rdx, %r11
movq %rcx, %r12
movq %r9, %r13
movl $0, %r9d
jmp .L8
.L6:
addl $1, %eax
addq $4, %rdx
cmpl (%r10), %eax
jnb .L5
.L7:
movl (%rdx), %ecx
movl %ecx, %esi
leaq (%r11,%rsi,4), %rsi
cmpl $0, (%rsi)
jne .L6
movl $1, (%rsi)
movl (%rdi), %esi
movl %ecx, (%r8,%rsi,4)
addl $1, (%rdi)
jmp .L6
.L5:
addq $1, %r9
cmpl 0(%r13), %r9d
jnb .L3
.L8:
movl (%r12,%r9,4), %edx
movl %edx, %eax
movl (%rbx,%rax,4), %eax
leal 1(%rdx), %edx
leaq (%rbx,%rdx,4), %r10
cmpl (%r10), %eax
jnb .L5
movl %eax, %edx
leaq 0(%rbp,%rdx,4), %rdx
jmp .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z11cpu_queuingPjS_S_S_S_S_S_, .-_Z11cpu_queuingPjS_S_S_S_S_S_
.globl _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.type _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.globl _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.type _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, @function
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, .-_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.globl _Z18gpu_global_queuingPjS_S_S_S_S_S_
.type _Z18gpu_global_queuingPjS_S_S_S_S_S_, @function
_Z18gpu_global_queuingPjS_S_S_S_S_S_:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $45, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L20
.cfi_endproc
.LFE2028:
.size _Z18gpu_global_queuingPjS_S_S_S_S_S_, .-_Z18gpu_global_queuingPjS_S_S_S_S_S_
.globl _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.type _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.globl _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.type _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, @function
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, .-_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.globl _Z17gpu_block_queuingPjS_S_S_S_S_S_
.type _Z17gpu_block_queuingPjS_S_S_S_S_S_, @function
_Z17gpu_block_queuingPjS_S_S_S_S_S_:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $45, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L32
.cfi_endproc
.LFE2029:
.size _Z17gpu_block_queuingPjS_S_S_S_S_S_, .-_Z17gpu_block_queuingPjS_S_S_S_S_S_
.globl _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.type _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.globl _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.type _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, @function
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_:
.LFB2060:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .-_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.globl _Z16gpu_warp_queuingPjS_S_S_S_S_S_
.type _Z16gpu_warp_queuingPjS_S_S_S_S_S_, @function
_Z16gpu_warp_queuingPjS_S_S_S_S_S_:
.LFB2030:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $45, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L44:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L44
.cfi_endproc
.LFE2030:
.size _Z16gpu_warp_queuingPjS_S_S_S_S_S_, .-_Z16gpu_warp_queuingPjS_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_"
.align 8
.LC1:
.string "_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_"
.align 8
.LC2:
.string "_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/******************************************************************************
*cr
*cr (C) Copyright 2010-2013 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)
// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048
// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128
/******************************************************************************
GPU kernels
*******************************************************************************/
__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
unsigned int iterator;
//unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int nodeInformation;
unsigned int iteratorNode;
unsigned int count;
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
// Do your computation here
// INSERT KERNEL CODE HERE
//for every node in the queue, we run this.
count = 0;
if(idx< *numCurrLevelNodes)
{
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
count++;
}
}
}
}
//__syncthreads();
}
__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
//have a queue in local thread copy. When thread computation completed,
//Initialization of Variables
__shared__ unsigned int localQueue[BQ_CAPACITY];
__shared__ unsigned int totalCount;
__shared__ unsigned int numberOfElementsToCopy;
__shared__ unsigned int queueStart;
int iterator;
unsigned int nodeInformation;
unsigned int iteratorNode;
int tid = threadIdx.x+blockIdx.x * blockDim.x;
//Initializing queue count
if(threadIdx.x == 0)
{
totalCount = 0;
}
__syncthreads();
//sync all the threads at this point as
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
//for every node in the queue, we run this.
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
int previousNodeVal = atomicAdd(&(totalCount),1);
if (previousNodeVal < BQ_CAPACITY){
//if the load is less than capacty. Load this in the local queue of thread
localQueue[previousNodeVal] = iteratorNode;
}
else {
//if block queue is saturated, we cannot place next level node in local queue.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
totalCount = BQ_CAPACITY; // if total count exceeds the capacity.
}
}
}
}
//preprocessing per local thread complete. Now, syncing threads
__syncthreads();
//for first thread, increment the global pointer for the next block.
if(blockIdx.x*blockDim.x < *numCurrLevelNodes)
{
//only let the first block to make changes globally.
if(threadIdx.x == 0)
{
//make the pointers incremented to the next level. So global threads can write parallely.
queueStart = atomicAdd(&(*numNextLevelNodes),totalCount);
//how many number should be copied.
numberOfElementsToCopy = ((totalCount-1)/BLOCK_SIZE +1);
}
__syncthreads();
//copy elements on a per thread basis.
for(unsigned int iter = 0;iter < numberOfElementsToCopy; iter++)
{
int index = threadIdx.x*numberOfElementsToCopy;
if( index + iter < totalCount)
{
//no element more than this should be copied.
nextLevelNodes[queueStart + index + iter] = localQueue[index+iter];
}
}
}
}
__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
}
/******************************************************************************
Functions
*******************************************************************************/
void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
// Loop over all nodes in the curent level
for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
unsigned int node = currLevelNodes[idx];
// Loop over all neighbors of the node
for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
++nbrIdx) {
unsigned int neighbor = nodeNeighbors[nbrIdx];
// If the neighbor hasn't been visited yet
if(!nodeVisited[neighbor]) {
// Mark it and add it to the queue
nodeVisited[neighbor] = 1;
nextLevelNodes[*numNextLevelNodes] = neighbor;
++(*numNextLevelNodes);
}
}
}
}
void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
|
#include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010-2013 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)
// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048
// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128
/******************************************************************************
GPU kernels
*******************************************************************************/
__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
unsigned int iterator;
//unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int nodeInformation;
unsigned int iteratorNode;
unsigned int count;
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
// Do your computation here
// INSERT KERNEL CODE HERE
//for every node in the queue, we run this.
count = 0;
if(idx< *numCurrLevelNodes)
{
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
count++;
}
}
}
}
//__syncthreads();
}
__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
//have a queue in local thread copy. When thread computation completed,
//Initialization of Variables
__shared__ unsigned int localQueue[BQ_CAPACITY];
__shared__ unsigned int totalCount;
__shared__ unsigned int numberOfElementsToCopy;
__shared__ unsigned int queueStart;
int iterator;
unsigned int nodeInformation;
unsigned int iteratorNode;
int tid = threadIdx.x+blockIdx.x * blockDim.x;
//Initializing queue count
if(threadIdx.x == 0)
{
totalCount = 0;
}
__syncthreads();
//sync all the threads at this point as
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
//for every node in the queue, we run this.
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
int previousNodeVal = atomicAdd(&(totalCount),1);
if (previousNodeVal < BQ_CAPACITY){
//if the load is less than capacty. Load this in the local queue of thread
localQueue[previousNodeVal] = iteratorNode;
}
else {
//if block queue is saturated, we cannot place next level node in local queue.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
totalCount = BQ_CAPACITY; // if total count exceeds the capacity.
}
}
}
}
//preprocessing per local thread complete. Now, syncing threads
__syncthreads();
//for first thread, increment the global pointer for the next block.
if(blockIdx.x*blockDim.x < *numCurrLevelNodes)
{
//only let the first block to make changes globally.
if(threadIdx.x == 0)
{
//make the pointers incremented to the next level. So global threads can write parallely.
queueStart = atomicAdd(&(*numNextLevelNodes),totalCount);
//how many number should be copied.
numberOfElementsToCopy = ((totalCount-1)/BLOCK_SIZE +1);
}
__syncthreads();
//copy elements on a per thread basis.
for(unsigned int iter = 0;iter < numberOfElementsToCopy; iter++)
{
int index = threadIdx.x*numberOfElementsToCopy;
if( index + iter < totalCount)
{
//no element more than this should be copied.
nextLevelNodes[queueStart + index + iter] = localQueue[index+iter];
}
}
}
}
__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
}
/******************************************************************************
Functions
*******************************************************************************/
void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
// Loop over all nodes in the curent level
for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
unsigned int node = currLevelNodes[idx];
// Loop over all neighbors of the node
for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
++nbrIdx) {
unsigned int neighbor = nodeNeighbors[nbrIdx];
// If the neighbor hasn't been visited yet
if(!nodeVisited[neighbor]) {
// Mark it and add it to the queue
nodeVisited[neighbor] = 1;
nextLevelNodes[*numNextLevelNodes] = neighbor;
++(*numNextLevelNodes);
}
}
}
}
void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010-2013 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)
// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048
// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128
/******************************************************************************
GPU kernels
*******************************************************************************/
__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
unsigned int iterator;
//unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int nodeInformation;
unsigned int iteratorNode;
unsigned int count;
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
// Do your computation here
// INSERT KERNEL CODE HERE
//for every node in the queue, we run this.
count = 0;
if(idx< *numCurrLevelNodes)
{
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
count++;
}
}
}
}
//__syncthreads();
}
__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
//have a queue in local thread copy. When thread computation completed,
//Initialization of Variables
__shared__ unsigned int localQueue[BQ_CAPACITY];
__shared__ unsigned int totalCount;
__shared__ unsigned int numberOfElementsToCopy;
__shared__ unsigned int queueStart;
int iterator;
unsigned int nodeInformation;
unsigned int iteratorNode;
int tid = threadIdx.x+blockIdx.x * blockDim.x;
//Initializing queue count
if(threadIdx.x == 0)
{
totalCount = 0;
}
__syncthreads();
//sync all the threads at this point as
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
//for every node in the queue, we run this.
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
int previousNodeVal = atomicAdd(&(totalCount),1);
if (previousNodeVal < BQ_CAPACITY){
//if the load is less than capacty. Load this in the local queue of thread
localQueue[previousNodeVal] = iteratorNode;
}
else {
//if block queue is saturated, we cannot place next level node in local queue.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
totalCount = BQ_CAPACITY; // if total count exceeds the capacity.
}
}
}
}
//preprocessing per local thread complete. Now, syncing threads
__syncthreads();
//for first thread, increment the global pointer for the next block.
if(blockIdx.x*blockDim.x < *numCurrLevelNodes)
{
//only let the first block to make changes globally.
if(threadIdx.x == 0)
{
//make the pointers incremented to the next level. So global threads can write parallely.
queueStart = atomicAdd(&(*numNextLevelNodes),totalCount);
//how many number should be copied.
numberOfElementsToCopy = ((totalCount-1)/BLOCK_SIZE +1);
}
__syncthreads();
//copy elements on a per thread basis.
for(unsigned int iter = 0;iter < numberOfElementsToCopy; iter++)
{
int index = threadIdx.x*numberOfElementsToCopy;
if( index + iter < totalCount)
{
//no element more than this should be copied.
nextLevelNodes[queueStart + index + iter] = localQueue[index+iter];
}
}
}
}
__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
}
/******************************************************************************
Functions
*******************************************************************************/
void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
// Loop over all nodes in the curent level
for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
unsigned int node = currLevelNodes[idx];
// Loop over all neighbors of the node
for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
++nbrIdx) {
unsigned int neighbor = nodeNeighbors[nbrIdx];
// If the neighbor hasn't been visited yet
if(!nodeVisited[neighbor]) {
// Mark it and add it to the queue
nodeVisited[neighbor] = 1;
nextLevelNodes[*numNextLevelNodes] = neighbor;
++(*numNextLevelNodes);
}
}
}
}
void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.globl _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.p2align 8
.type _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_,@function
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x28
s_load_b32 s6, s[0:1], 0x44
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s7, s[2:3], 0x0
s_and_b32 s16, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB0_10
s_load_b32 s17, s[4:5], 0x0
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b64 s[14:15], s[0:1], 0x30
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s17, s16
s_mov_b32 s16, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s17
global_load_b32 v2, v3, s[2:3]
v_add_nc_u32_e32 v1, s1, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, v1, v2
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_10
.LBB0_3:
v_mov_b32_e32 v2, 0
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_mov_b32_e32 v7, v2
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_mov_b32 v5, v2 :: v_dual_add_nc_u32 v6, 1, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v8, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v6, v[8:9], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_u32_e64 v6, v2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v7, v3
s_mov_b32 s18, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s19
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s19, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v10, v3 :: v_dual_add_nc_u32 v9, s19, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s12, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo
global_store_b32 v[9:10], v2, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v2, v[4:5], off
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v7, s0, v7, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_waitcnt vmcnt(0)
v_cmp_ge_u32_e32 vcc_lo, v6, v2
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_2
.LBB0_7:
global_load_b32 v2, v[7:8], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[9:10], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_atomic_add_u32 v9, v[9:10], v0, off glc
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_6
s_mov_b32 s20, exec_lo
s_mov_b32 s19, exec_lo
v_mbcnt_lo_u32_b32 v9, s20, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s20, s20
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v10, s20
global_atomic_add_u32 v10, v3, v10, s[14:15] glc
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end0-_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.globl _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.p2align 8
.type _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_,@function
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_:
s_load_b32 s3, s[0:1], 0x44
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v1, 0
ds_store_b32 v1, v1 offset:8196
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x20
s_load_b64 s[12:13], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s14, 0xffff, s3
s_mov_b32 s3, exec_lo
s_mul_i32 s15, s15, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v0
s_load_b32 s4, s[18:19], 0x0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB1_17
s_clause 0x1
s_load_b32 s20, s[0:1], 0x38
s_load_b256 s[4:11], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v10, 0x800
v_mov_b32_e32 v9, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s20, s14
s_mov_b32 s14, 0
s_branch .LBB1_5
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s20
global_load_b32 v2, v3, s[18:19]
v_add_nc_u32_e32 v1, s1, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, v1, v2
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB1_17
.LBB1_5:
v_mov_b32_e32 v2, 0
s_mov_b32 s20, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_mov_b32_e32 v7, v2
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_mov_b32 v5, v2 :: v_dual_add_nc_u32 v6, 1, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v11, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v6, v[11:12], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_u32_e64 v6, v2
s_cbranch_execz .LBB1_4
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_branch .LBB1_8
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v2, v[4:5], off
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v7, s0, v7, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_waitcnt vmcnt(0)
v_cmp_ge_u32_e32 vcc_lo, v6, v2
s_or_b32 s21, vcc_lo, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB1_4
.LBB1_8:
global_load_b32 v2, v[7:8], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
global_atomic_add_u32 v11, v[11:12], v9, off glc
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v11
s_cbranch_execz .LBB1_7
s_mov_b32 s23, exec_lo
s_mov_b32 s22, exec_lo
v_mbcnt_lo_u32_b32 v11, s23, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v11
s_cbranch_execz .LBB1_11
s_bcnt1_i32_b32 s23, s23
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v12, s23
ds_add_rtn_u32 v12, v3, v12 offset:8196
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s22
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s22, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, s22, v11
s_mov_b32 s22, exec_lo
v_cmpx_lt_i32_e32 0x7ff, v11
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB1_15
s_mov_b32 s24, exec_lo
s_mov_b32 s23, exec_lo
v_mbcnt_lo_u32_b32 v11, s24, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v11
s_cbranch_execz .LBB1_14
s_bcnt1_i32_b32 s24, s24
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v12, s24
global_atomic_add_u32 v12, v3, v12, s[12:13] glc
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s23
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s23, v12
v_mov_b32_e32 v12, v3
ds_store_b32 v3, v10 offset:8196
v_add_nc_u32_e32 v11, s23, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s16, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v12, vcc_lo
global_store_b32 v[11:12], v2, off
.LBB1_15:
s_and_not1_saveexec_b32 s22, s22
s_cbranch_execz .LBB1_7
v_lshlrev_b32_e32 v11, 2, v11
ds_store_b32 v11, v2
s_branch .LBB1_7
.LBB1_17:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v1, v1, s[18:19]
s_waitcnt vmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, s15, v1
s_cbranch_vccz .LBB1_27
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_22
v_mov_b32_e32 v1, 0
s_mov_b32 s1, exec_lo
s_mov_b32 s2, exec_lo
v_mbcnt_lo_u32_b32 v3, s1, 0
ds_load_b32 v2, v1 offset:8196
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB1_21
s_bcnt1_i32_b32 s1, s1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v2, s1
global_atomic_add_u32 v4, v1, v4, s[12:13] glc
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, -1, v2
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s2, v4
s_movk_i32 s1, 0x2000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, s1, v1
v_lshrrev_b32_e32 v6, 9, v5
v_mad_u64_u32 v[4:5], null, v2, v3, s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v6
ds_store_2addr_b32 v1, v4, v2 offset1:2
.LBB1_22:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v1 offset:8200
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_cbranch_vccnz .LBB1_27
s_movk_i32 s0, 0x2000
v_mul_lo_u32 v5, v4, v0
v_add_nc_u32_e32 v2, s0, v1
ds_load_2addr_b32 v[2:3], v2 offset1:1
v_lshlrev_b32_e32 v6, 2, v5
s_branch .LBB1_25
.p2align 6
.LBB1_24:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v4, -1, v4
v_add_nc_u32_e32 v6, 4, v6
v_add_nc_u32_e32 v5, 1, v5
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_cbranch_vccz .LBB1_27
.LBB1_25:
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_u32_e64 v5, v3
s_cbranch_execz .LBB1_24
ds_load_b32 v9, v6
v_add_nc_u32_e32 v0, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_co_u32 v7, vcc_lo, s16, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[7:8], v9, off
s_branch .LBB1_24
.LBB1_27:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 8204
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end1-_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.globl _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.p2align 8
.type _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@function
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end2-_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8204
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010-2013 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)
// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048
// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128
/******************************************************************************
GPU kernels
*******************************************************************************/
__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
unsigned int iterator;
//unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int nodeInformation;
unsigned int iteratorNode;
unsigned int count;
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
// Do your computation here
// INSERT KERNEL CODE HERE
//for every node in the queue, we run this.
count = 0;
if(idx< *numCurrLevelNodes)
{
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
count++;
}
}
}
}
//__syncthreads();
}
__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
//have a queue in local thread copy. When thread computation completed,
//Initialization of Variables
__shared__ unsigned int localQueue[BQ_CAPACITY];
__shared__ unsigned int totalCount;
__shared__ unsigned int numberOfElementsToCopy;
__shared__ unsigned int queueStart;
int iterator;
unsigned int nodeInformation;
unsigned int iteratorNode;
int tid = threadIdx.x+blockIdx.x * blockDim.x;
//Initializing queue count
if(threadIdx.x == 0)
{
totalCount = 0;
}
__syncthreads();
//sync all the threads at this point as
for(unsigned int idx = tid; idx < *numCurrLevelNodes; idx += blockDim.x*gridDim.x) {
//for every node in the queue, we run this.
nodeInformation = currLevelNodes[idx];
//loop over all the neighbours
for(iterator=nodePtrs[nodeInformation];iterator<nodePtrs[nodeInformation+1];iterator++)
{
iteratorNode = nodeNeighbors[iterator];
if(!atomicAdd(&nodeVisited[iteratorNode],1))
{
//if it has not been visited.
int previousNodeVal = atomicAdd(&(totalCount),1);
if (previousNodeVal < BQ_CAPACITY){
//if the load is less than capacty. Load this in the local queue of thread
localQueue[previousNodeVal] = iteratorNode;
}
else {
//if block queue is saturated, we cannot place next level node in local queue.
nextLevelNodes[atomicAdd(&(*numNextLevelNodes),1)] = iteratorNode;
totalCount = BQ_CAPACITY; // if total count exceeds the capacity.
}
}
}
}
//preprocessing per local thread complete. Now, syncing threads
__syncthreads();
//for first thread, increment the global pointer for the next block.
if(blockIdx.x*blockDim.x < *numCurrLevelNodes)
{
//only let the first block to make changes globally.
if(threadIdx.x == 0)
{
//make the pointers incremented to the next level. So global threads can write parallely.
queueStart = atomicAdd(&(*numNextLevelNodes),totalCount);
//how many number should be copied.
numberOfElementsToCopy = ((totalCount-1)/BLOCK_SIZE +1);
}
__syncthreads();
//copy elements on a per thread basis.
for(unsigned int iter = 0;iter < numberOfElementsToCopy; iter++)
{
int index = threadIdx.x*numberOfElementsToCopy;
if( index + iter < totalCount)
{
//no element more than this should be copied.
nextLevelNodes[queueStart + index + iter] = localQueue[index+iter];
}
}
}
}
__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
unsigned int *nodeNeighbors, unsigned int *nodeVisited,
unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
// INSERT KERNEL CODE HERE
}
/******************************************************************************
Functions
*******************************************************************************/
void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
// Loop over all nodes in the curent level
for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
unsigned int node = currLevelNodes[idx];
// Loop over all neighbors of the node
for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
++nbrIdx) {
unsigned int neighbor = nodeNeighbors[nbrIdx];
// If the neighbor hasn't been visited yet
if(!nodeVisited[neighbor]) {
// Mark it and add it to the queue
nodeVisited[neighbor] = 1;
nextLevelNodes[*numNextLevelNodes] = neighbor;
++(*numNextLevelNodes);
}
}
}
}
void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
unsigned int *nodeVisited, unsigned int *currLevelNodes,
unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
unsigned int *numNextLevelNodes) {
const unsigned int numBlocks = 45;
gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
numCurrLevelNodes, numNextLevelNodes);
}
|
.text
.file "kernel.hip"
.globl _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_,@function
_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_: # @_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end0-_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_,@function
_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_: # @_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end1-_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@function
_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_: # @_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end2-_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z11cpu_queuingPjS_S_S_S_S_S_ # -- Begin function _Z11cpu_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z11cpu_queuingPjS_S_S_S_S_S_,@function
_Z11cpu_queuingPjS_S_S_S_S_S_: # @_Z11cpu_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
cmpl $0, (%r9)
je .LBB3_5
# %bb.1: # %.lr.ph24.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq 32(%rsp), %rax
xorl %r10d, %r10d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_3: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r10
movl (%r9), %r11d
cmpq %r11, %r10
jae .LBB3_4
.LBB3_2: # %.lr.ph24
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl (%rcx,%r10,4), %ebx
movl (%rdi,%rbx,4), %r11d
incl %ebx
cmpl (%rdi,%rbx,4), %r11d
jb .LBB3_6
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=2
incq %r11
movl (%rdi,%rbx,4), %r14d
cmpq %r14, %r11
jae .LBB3_3
.LBB3_6: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r11,4), %r14d
cmpl $0, (%rdx,%r14,4)
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=2
movl $1, (%rdx,%r14,4)
movl (%rax), %r15d
movl %r14d, (%r8,%r15,4)
incl (%rax)
jmp .LBB3_8
.LBB3_4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_5: # %._crit_edge25
retq
.Lfunc_end3:
.size _Z11cpu_queuingPjS_S_S_S_S_S_, .Lfunc_end3-_Z11cpu_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z18gpu_global_queuingPjS_S_S_S_S_S_ # -- Begin function _Z18gpu_global_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z18gpu_global_queuingPjS_S_S_S_S_S_,@function
_Z18gpu_global_queuingPjS_S_S_S_S_S_: # @_Z18gpu_global_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movabsq $4294967341, %rdi # imm = 0x10000002D
leaq 467(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 224(%rsp), %rax
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z18gpu_global_queuingPjS_S_S_S_S_S_, .Lfunc_end4-_Z18gpu_global_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z17gpu_block_queuingPjS_S_S_S_S_S_ # -- Begin function _Z17gpu_block_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z17gpu_block_queuingPjS_S_S_S_S_S_,@function
_Z17gpu_block_queuingPjS_S_S_S_S_S_: # @_Z17gpu_block_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movabsq $4294967341, %rdi # imm = 0x10000002D
leaq 467(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 224(%rsp), %rax
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z17gpu_block_queuingPjS_S_S_S_S_S_, .Lfunc_end5-_Z17gpu_block_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z16gpu_warp_queuingPjS_S_S_S_S_S_ # -- Begin function _Z16gpu_warp_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z16gpu_warp_queuingPjS_S_S_S_S_S_,@function
_Z16gpu_warp_queuingPjS_S_S_S_S_S_: # @_Z16gpu_warp_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movabsq $4294967341, %rdi # imm = 0x10000002D
leaq 467(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 224(%rsp), %rax
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z16gpu_warp_queuingPjS_S_S_S_S_S_, .Lfunc_end6-_Z16gpu_warp_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.p2align 3, 0x0
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_:
.quad _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.size _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, 8
.type _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.globl _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.p2align 3, 0x0
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_:
.quad _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.size _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, 8
.type _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.globl _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.p2align 3, 0x0
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_:
.quad _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.size _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_"
.size .L__unnamed_3, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000b7d43_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cpu_queuingPjS_S_S_S_S_S_
.type _Z11cpu_queuingPjS_S_S_S_S_S_, @function
_Z11cpu_queuingPjS_S_S_S_S_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbx
movq 40(%rsp), %rdi
cmpl $0, (%r9)
je .L3
movq %rsi, %rbp
movq %rdx, %r11
movq %rcx, %r12
movq %r9, %r13
movl $0, %r9d
jmp .L8
.L6:
addl $1, %eax
addq $4, %rdx
cmpl (%r10), %eax
jnb .L5
.L7:
movl (%rdx), %ecx
movl %ecx, %esi
leaq (%r11,%rsi,4), %rsi
cmpl $0, (%rsi)
jne .L6
movl $1, (%rsi)
movl (%rdi), %esi
movl %ecx, (%r8,%rsi,4)
addl $1, (%rdi)
jmp .L6
.L5:
addq $1, %r9
cmpl 0(%r13), %r9d
jnb .L3
.L8:
movl (%r12,%r9,4), %edx
movl %edx, %eax
movl (%rbx,%rax,4), %eax
leal 1(%rdx), %edx
leaq (%rbx,%rdx,4), %r10
cmpl (%r10), %eax
jnb .L5
movl %eax, %edx
leaq 0(%rbp,%rdx,4), %rdx
jmp .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z11cpu_queuingPjS_S_S_S_S_S_, .-_Z11cpu_queuingPjS_S_S_S_S_S_
.globl _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.type _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.globl _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.type _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, @function
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, .-_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.globl _Z18gpu_global_queuingPjS_S_S_S_S_S_
.type _Z18gpu_global_queuingPjS_S_S_S_S_S_, @function
_Z18gpu_global_queuingPjS_S_S_S_S_S_:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $45, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L20
.cfi_endproc
.LFE2028:
.size _Z18gpu_global_queuingPjS_S_S_S_S_S_, .-_Z18gpu_global_queuingPjS_S_S_S_S_S_
.globl _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.type _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.globl _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.type _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, @function
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, .-_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.globl _Z17gpu_block_queuingPjS_S_S_S_S_S_
.type _Z17gpu_block_queuingPjS_S_S_S_S_S_, @function
_Z17gpu_block_queuingPjS_S_S_S_S_S_:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $45, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L32
.cfi_endproc
.LFE2029:
.size _Z17gpu_block_queuingPjS_S_S_S_S_S_, .-_Z17gpu_block_queuingPjS_S_S_S_S_S_
.globl _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.type _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.globl _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.type _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, @function
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_:
.LFB2060:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .-_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.globl _Z16gpu_warp_queuingPjS_S_S_S_S_S_
.type _Z16gpu_warp_queuingPjS_S_S_S_S_S_, @function
_Z16gpu_warp_queuingPjS_S_S_S_S_S_:
.LFB2030:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $45, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L44:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L44
.cfi_endproc
.LFE2030:
.size _Z16gpu_warp_queuingPjS_S_S_S_S_S_, .-_Z16gpu_warp_queuingPjS_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_"
.align 8
.LC1:
.string "_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_"
.align 8
.LC2:
.string "_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_,@function
_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_: # @_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end0-_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_,@function
_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_: # @_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end1-_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@function
_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_: # @_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end2-_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z11cpu_queuingPjS_S_S_S_S_S_ # -- Begin function _Z11cpu_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z11cpu_queuingPjS_S_S_S_S_S_,@function
_Z11cpu_queuingPjS_S_S_S_S_S_: # @_Z11cpu_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
cmpl $0, (%r9)
je .LBB3_5
# %bb.1: # %.lr.ph24.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq 32(%rsp), %rax
xorl %r10d, %r10d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_3: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r10
movl (%r9), %r11d
cmpq %r11, %r10
jae .LBB3_4
.LBB3_2: # %.lr.ph24
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl (%rcx,%r10,4), %ebx
movl (%rdi,%rbx,4), %r11d
incl %ebx
cmpl (%rdi,%rbx,4), %r11d
jb .LBB3_6
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=2
incq %r11
movl (%rdi,%rbx,4), %r14d
cmpq %r14, %r11
jae .LBB3_3
.LBB3_6: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r11,4), %r14d
cmpl $0, (%rdx,%r14,4)
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=2
movl $1, (%rdx,%r14,4)
movl (%rax), %r15d
movl %r14d, (%r8,%r15,4)
incl (%rax)
jmp .LBB3_8
.LBB3_4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_5: # %._crit_edge25
retq
.Lfunc_end3:
.size _Z11cpu_queuingPjS_S_S_S_S_S_, .Lfunc_end3-_Z11cpu_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z18gpu_global_queuingPjS_S_S_S_S_S_ # -- Begin function _Z18gpu_global_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z18gpu_global_queuingPjS_S_S_S_S_S_,@function
_Z18gpu_global_queuingPjS_S_S_S_S_S_: # @_Z18gpu_global_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movabsq $4294967341, %rdi # imm = 0x10000002D
leaq 467(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 224(%rsp), %rax
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z18gpu_global_queuingPjS_S_S_S_S_S_, .Lfunc_end4-_Z18gpu_global_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z17gpu_block_queuingPjS_S_S_S_S_S_ # -- Begin function _Z17gpu_block_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z17gpu_block_queuingPjS_S_S_S_S_S_,@function
_Z17gpu_block_queuingPjS_S_S_S_S_S_: # @_Z17gpu_block_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movabsq $4294967341, %rdi # imm = 0x10000002D
leaq 467(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 224(%rsp), %rax
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z17gpu_block_queuingPjS_S_S_S_S_S_, .Lfunc_end5-_Z17gpu_block_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z16gpu_warp_queuingPjS_S_S_S_S_S_ # -- Begin function _Z16gpu_warp_queuingPjS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z16gpu_warp_queuingPjS_S_S_S_S_S_,@function
_Z16gpu_warp_queuingPjS_S_S_S_S_S_: # @_Z16gpu_warp_queuingPjS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
movabsq $4294967341, %rdi # imm = 0x10000002D
leaq 467(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 224(%rsp), %rax
movq %rbp, 104(%rsp)
movq %r13, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z16gpu_warp_queuingPjS_S_S_S_S_S_, .Lfunc_end6-_Z16gpu_warp_queuingPjS_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.p2align 3, 0x0
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_:
.quad _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.size _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, 8
.type _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.globl _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.p2align 3, 0x0
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_:
.quad _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.size _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, 8
.type _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.globl _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.p2align 3, 0x0
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_:
.quad _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.size _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_"
.size .L__unnamed_3, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand_kernel.h>
extern "C"
{
__global__ void setup_kernel(curandState *state, int seed, int n, int verbose)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (verbose){
printf("Setting up RNG in thread %d (n=%d)...\n",idx,n);
}
curand_init(seed, idx, 0, &state[idx]);
return;
}
__global__ void rnorm_basic_kernel(curandState *state, double *vals, int n, double mu, double sigma)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (idx < n) {
vals[idx] = mu + sigma * curand_normal_double(&state[idx]);
}
return;
}
__global__ void rnorm_kernel(curandState *state, double *vals, int n, double mu, double sigma, int numSamples)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
int k;
int startIdx = idx*numSamples;
for(k = 0; k < numSamples; k++) {
if(startIdx + k < n)
vals[startIdx + k] = mu + sigma * curand_normal_double(&state[idx]);
}
return;
}
} // END extern
|
.file "tmpxft_00132064_00000000-6_random.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii
.type _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii, @function
_Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii:
.LFB2295:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq setup_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii, .-_Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii
.globl setup_kernel
.type setup_kernel, @function
setup_kernel:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size setup_kernel, .-setup_kernel
.globl _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd
.type _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd, @function
_Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd:
.LFB2297:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq rnorm_basic_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd, .-_Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd
.globl rnorm_basic_kernel
.type rnorm_basic_kernel, @function
rnorm_basic_kernel:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size rnorm_basic_kernel, .-rnorm_basic_kernel
.globl _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi
.type _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi, @function
_Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi:
.LFB2299:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq rnorm_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi, .-_Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi
.globl rnorm_kernel
.type rnorm_kernel, @function
rnorm_kernel:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size rnorm_kernel, .-rnorm_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rnorm_kernel"
.LC1:
.string "rnorm_basic_kernel"
.LC2:
.string "setup_kernel"
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq rnorm_kernel(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq rnorm_basic_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq setup_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand_kernel.h>
extern "C"
{
__global__ void setup_kernel(curandState *state, int seed, int n, int verbose)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (verbose){
printf("Setting up RNG in thread %d (n=%d)...\n",idx,n);
}
curand_init(seed, idx, 0, &state[idx]);
return;
}
__global__ void rnorm_basic_kernel(curandState *state, double *vals, int n, double mu, double sigma)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (idx < n) {
vals[idx] = mu + sigma * curand_normal_double(&state[idx]);
}
return;
}
__global__ void rnorm_kernel(curandState *state, double *vals, int n, double mu, double sigma, int numSamples)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
int k;
int startIdx = idx*numSamples;
for(k = 0; k < numSamples; k++) {
if(startIdx + k < n)
vals[startIdx + k] = mu + sigma * curand_normal_double(&state[idx]);
}
return;
}
} // END extern
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
extern "C"
{
__global__ void setup_kernel(hiprandState *state, int seed, int n, int verbose)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (verbose){
printf("Setting up RNG in thread %d (n=%d)...\n",idx,n);
}
hiprand_init(seed, idx, 0, &state[idx]);
return;
}
__global__ void rnorm_basic_kernel(hiprandState *state, double *vals, int n, double mu, double sigma)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (idx < n) {
vals[idx] = mu + sigma * hiprand_normal_double(&state[idx]);
}
return;
}
__global__ void rnorm_kernel(hiprandState *state, double *vals, int n, double mu, double sigma, int numSamples)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
int k;
int startIdx = idx*numSamples;
for(k = 0; k < numSamples; k++) {
if(startIdx + k < n)
vals[startIdx + k] = mu + sigma * hiprand_normal_double(&state[idx]);
}
return;
}
} // END extern
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
extern "C"
{
__global__ void setup_kernel(hiprandState *state, int seed, int n, int verbose)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (verbose){
printf("Setting up RNG in thread %d (n=%d)...\n",idx,n);
}
hiprand_init(seed, idx, 0, &state[idx]);
return;
}
__global__ void rnorm_basic_kernel(hiprandState *state, double *vals, int n, double mu, double sigma)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if (idx < n) {
vals[idx] = mu + sigma * hiprand_normal_double(&state[idx]);
}
return;
}
__global__ void rnorm_kernel(hiprandState *state, double *vals, int n, double mu, double sigma, int numSamples)
{
// Usual block/thread indexing...
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
int blocksize = blockDim.x * blockDim.y * blockDim.z;
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
int k;
int startIdx = idx*numSamples;
for(k = 0; k < numSamples; k++) {
if(startIdx + k < n)
vals[startIdx + k] = mu + sigma * hiprand_normal_double(&state[idx]);
}
return;
}
} // END extern
|
.text
.file "random.hip"
.globl __device_stub__setup_kernel # -- Begin function __device_stub__setup_kernel
.p2align 4, 0x90
.type __device_stub__setup_kernel,@function
__device_stub__setup_kernel: # @__device_stub__setup_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $setup_kernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__setup_kernel, .Lfunc_end0-__device_stub__setup_kernel
.cfi_endproc
# -- End function
.globl __device_stub__rnorm_basic_kernel # -- Begin function __device_stub__rnorm_basic_kernel
.p2align 4, 0x90
.type __device_stub__rnorm_basic_kernel,@function
__device_stub__rnorm_basic_kernel: # @__device_stub__rnorm_basic_kernel
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $rnorm_basic_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size __device_stub__rnorm_basic_kernel, .Lfunc_end1-__device_stub__rnorm_basic_kernel
.cfi_endproc
# -- End function
.globl __device_stub__rnorm_kernel # -- Begin function __device_stub__rnorm_kernel
.p2align 4, 0x90
.type __device_stub__rnorm_kernel,@function
__device_stub__rnorm_kernel: # @__device_stub__rnorm_kernel
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $rnorm_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size __device_stub__rnorm_kernel, .Lfunc_end2-__device_stub__rnorm_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $setup_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $rnorm_basic_kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $rnorm_kernel, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type setup_kernel,@object # @setup_kernel
.section .rodata,"a",@progbits
.globl setup_kernel
.p2align 3, 0x0
setup_kernel:
.quad __device_stub__setup_kernel
.size setup_kernel, 8
.type rnorm_basic_kernel,@object # @rnorm_basic_kernel
.globl rnorm_basic_kernel
.p2align 3, 0x0
rnorm_basic_kernel:
.quad __device_stub__rnorm_basic_kernel
.size rnorm_basic_kernel, 8
.type rnorm_kernel,@object # @rnorm_kernel
.globl rnorm_kernel
.p2align 3, 0x0
rnorm_kernel:
.quad __device_stub__rnorm_kernel
.size rnorm_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "setup_kernel"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "rnorm_basic_kernel"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "rnorm_kernel"
.size .L__unnamed_3, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__setup_kernel
.addrsig_sym __device_stub__rnorm_basic_kernel
.addrsig_sym __device_stub__rnorm_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym setup_kernel
.addrsig_sym rnorm_basic_kernel
.addrsig_sym rnorm_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00132064_00000000-6_random.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii
.type _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii, @function
_Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii:
.LFB2295:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq setup_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii, .-_Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii
.globl setup_kernel
.type setup_kernel, @function
setup_kernel:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z12setup_kernelP17curandStateXORWOWiiiP17curandStateXORWOWiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size setup_kernel, .-setup_kernel
.globl _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd
.type _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd, @function
_Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd:
.LFB2297:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq rnorm_basic_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd, .-_Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd
.globl rnorm_basic_kernel
.type rnorm_basic_kernel, @function
rnorm_basic_kernel:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z18rnorm_basic_kernelP17curandStateXORWOWPdiddP17curandStateXORWOWPdidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size rnorm_basic_kernel, .-rnorm_basic_kernel
.globl _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi
.type _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi, @function
_Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi:
.LFB2299:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq rnorm_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi, .-_Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi
.globl rnorm_kernel
.type rnorm_kernel, @function
rnorm_kernel:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z12rnorm_kernelP17curandStateXORWOWPdiddiP17curandStateXORWOWPdiddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size rnorm_kernel, .-rnorm_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rnorm_kernel"
.LC1:
.string "rnorm_basic_kernel"
.LC2:
.string "setup_kernel"
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq rnorm_kernel(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq rnorm_basic_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq setup_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "random.hip"
.globl __device_stub__setup_kernel # -- Begin function __device_stub__setup_kernel
.p2align 4, 0x90
.type __device_stub__setup_kernel,@function
__device_stub__setup_kernel: # @__device_stub__setup_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $setup_kernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__setup_kernel, .Lfunc_end0-__device_stub__setup_kernel
.cfi_endproc
# -- End function
.globl __device_stub__rnorm_basic_kernel # -- Begin function __device_stub__rnorm_basic_kernel
.p2align 4, 0x90
.type __device_stub__rnorm_basic_kernel,@function
__device_stub__rnorm_basic_kernel: # @__device_stub__rnorm_basic_kernel
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $rnorm_basic_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size __device_stub__rnorm_basic_kernel, .Lfunc_end1-__device_stub__rnorm_basic_kernel
.cfi_endproc
# -- End function
.globl __device_stub__rnorm_kernel # -- Begin function __device_stub__rnorm_kernel
.p2align 4, 0x90
.type __device_stub__rnorm_kernel,@function
__device_stub__rnorm_kernel: # @__device_stub__rnorm_kernel
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $rnorm_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size __device_stub__rnorm_kernel, .Lfunc_end2-__device_stub__rnorm_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $setup_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $rnorm_basic_kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $rnorm_kernel, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type setup_kernel,@object # @setup_kernel
.section .rodata,"a",@progbits
.globl setup_kernel
.p2align 3, 0x0
setup_kernel:
.quad __device_stub__setup_kernel
.size setup_kernel, 8
.type rnorm_basic_kernel,@object # @rnorm_basic_kernel
.globl rnorm_basic_kernel
.p2align 3, 0x0
rnorm_basic_kernel:
.quad __device_stub__rnorm_basic_kernel
.size rnorm_basic_kernel, 8
.type rnorm_kernel,@object # @rnorm_kernel
.globl rnorm_kernel
.p2align 3, 0x0
rnorm_kernel:
.quad __device_stub__rnorm_kernel
.size rnorm_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "setup_kernel"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "rnorm_basic_kernel"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "rnorm_kernel"
.size .L__unnamed_3, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__setup_kernel
.addrsig_sym __device_stub__rnorm_basic_kernel
.addrsig_sym __device_stub__rnorm_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym setup_kernel
.addrsig_sym rnorm_basic_kernel
.addrsig_sym rnorm_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// GPU kernel
__device__ void StencilUpdate(void* param)
{
float* paramIn = (float*)param;
int N = (int)paramIn[0];
float h = paramIn[1];
float dt = paramIn[2];
float alpha = paramIn[3];
float* u = paramIn+5;
float* u_prev = paramIn+5+N*N;
// Setting up indices
int i = threadIdx.x;
int I = i;
//if (I>=N*N){return;}
while (I < N*N)
{
// if not boundary do
if ( (I>N) && (I< N*N-1-N) && (I%N!=0) && (I%N!=N-1))
{
u[I] = u_prev[I] + alpha*dt/(h*h) * (u_prev[I+1] + u_prev[I-1] + u_prev[I+N] + u_prev[I-N] - 4*u_prev[I]);
}
I = I + 32;
}
// Boundary conditions are automatically imposed
// as we don't touch boundaries
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// GPU kernel
__device__ void StencilUpdate(void* param)
{
float* paramIn = (float*)param;
int N = (int)paramIn[0];
float h = paramIn[1];
float dt = paramIn[2];
float alpha = paramIn[3];
float* u = paramIn+5;
float* u_prev = paramIn+5+N*N;
// Setting up indices
int i = threadIdx.x;
int I = i;
//if (I>=N*N){return;}
while (I < N*N)
{
// if not boundary do
if ( (I>N) && (I< N*N-1-N) && (I%N!=0) && (I%N!=N-1))
{
u[I] = u_prev[I] + alpha*dt/(h*h) * (u_prev[I+1] + u_prev[I-1] + u_prev[I+N] + u_prev[I-N] - 4*u_prev[I]);
}
I = I + 32;
}
// Boundary conditions are automatically imposed
// as we don't touch boundaries
}
|
.file "tmpxft_00058381_00000000-6_StencilUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13StencilUpdatePv
.type _Z13StencilUpdatePv, @function
_Z13StencilUpdatePv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13StencilUpdatePv, .-_Z13StencilUpdatePv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// GPU kernel
__device__ void StencilUpdate(void* param)
{
float* paramIn = (float*)param;
int N = (int)paramIn[0];
float h = paramIn[1];
float dt = paramIn[2];
float alpha = paramIn[3];
float* u = paramIn+5;
float* u_prev = paramIn+5+N*N;
// Setting up indices
int i = threadIdx.x;
int I = i;
//if (I>=N*N){return;}
while (I < N*N)
{
// if not boundary do
if ( (I>N) && (I< N*N-1-N) && (I%N!=0) && (I%N!=N-1))
{
u[I] = u_prev[I] + alpha*dt/(h*h) * (u_prev[I+1] + u_prev[I-1] + u_prev[I+N] + u_prev[I-N] - 4*u_prev[I]);
}
I = I + 32;
}
// Boundary conditions are automatically imposed
// as we don't touch boundaries
}
|
#include <hip/hip_runtime.h>
// GPU kernel
__device__ void StencilUpdate(void* param)
{
float* paramIn = (float*)param;
int N = (int)paramIn[0];
float h = paramIn[1];
float dt = paramIn[2];
float alpha = paramIn[3];
float* u = paramIn+5;
float* u_prev = paramIn+5+N*N;
// Setting up indices
int i = threadIdx.x;
int I = i;
//if (I>=N*N){return;}
while (I < N*N)
{
// if not boundary do
if ( (I>N) && (I< N*N-1-N) && (I%N!=0) && (I%N!=N-1))
{
u[I] = u_prev[I] + alpha*dt/(h*h) * (u_prev[I+1] + u_prev[I-1] + u_prev[I+N] + u_prev[I-N] - 4*u_prev[I]);
}
I = I + 32;
}
// Boundary conditions are automatically imposed
// as we don't touch boundaries
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
// GPU kernel
__device__ void StencilUpdate(void* param)
{
float* paramIn = (float*)param;
int N = (int)paramIn[0];
float h = paramIn[1];
float dt = paramIn[2];
float alpha = paramIn[3];
float* u = paramIn+5;
float* u_prev = paramIn+5+N*N;
// Setting up indices
int i = threadIdx.x;
int I = i;
//if (I>=N*N){return;}
while (I < N*N)
{
// if not boundary do
if ( (I>N) && (I< N*N-1-N) && (I%N!=0) && (I%N!=N-1))
{
u[I] = u_prev[I] + alpha*dt/(h*h) * (u_prev[I+1] + u_prev[I-1] + u_prev[I+N] + u_prev[I-N] - 4*u_prev[I]);
}
I = I + 32;
}
// Boundary conditions are automatically imposed
// as we don't touch boundaries
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
// GPU kernel
__device__ void StencilUpdate(void* param)
{
float* paramIn = (float*)param;
int N = (int)paramIn[0];
float h = paramIn[1];
float dt = paramIn[2];
float alpha = paramIn[3];
float* u = paramIn+5;
float* u_prev = paramIn+5+N*N;
// Setting up indices
int i = threadIdx.x;
int I = i;
//if (I>=N*N){return;}
while (I < N*N)
{
// if not boundary do
if ( (I>N) && (I< N*N-1-N) && (I%N!=0) && (I%N!=N-1))
{
u[I] = u_prev[I] + alpha*dt/(h*h) * (u_prev[I+1] + u_prev[I-1] + u_prev[I+N] + u_prev[I-N] - 4*u_prev[I]);
}
I = I + 32;
}
// Boundary conditions are automatically imposed
// as we don't touch boundaries
}
|
.text
.file "StencilUpdate.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00058381_00000000-6_StencilUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13StencilUpdatePv
.type _Z13StencilUpdatePv, @function
_Z13StencilUpdatePv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13StencilUpdatePv, .-_Z13StencilUpdatePv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "StencilUpdate.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void copyToOpenMM( float *target, float *source, int N ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
int atom = elementNum / 3;
if( elementNum > N ) {
return;
}
//else target[elementNum] = source[elementNum];
else {
target[4 * atom + elementNum % 3] = source[elementNum];
}
}
|
code for sm_80
Function : _Z12copyToOpenMMPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R6, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0206 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.HI R4, R0, 0x55555556, RZ ; /* 0x5555555600047827 */
/* 0x000fca00078e02ff */
/*00b0*/ LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404057211 */
/* 0x000fca00078f08ff */
/*00c0*/ IMAD R0, R5, -0x3, R0 ; /* 0xfffffffd05007824 */
/* 0x000fca00078e0200 */
/*00d0*/ LEA R5, R5, R0, 0x2 ; /* 0x0000000005057211 */
/* 0x000fca00078e10ff */
/*00e0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0206 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void copyToOpenMM( float *target, float *source, int N ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
int atom = elementNum / 3;
if( elementNum > N ) {
return;
}
//else target[elementNum] = source[elementNum];
else {
target[4 * atom + elementNum % 3] = source[elementNum];
}
}
|
.file "tmpxft_0006bb01_00000000-6_copyToOpenMM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i
.type _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i, @function
_Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12copyToOpenMMPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i, .-_Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i
.globl _Z12copyToOpenMMPfS_i
.type _Z12copyToOpenMMPfS_i, @function
_Z12copyToOpenMMPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12copyToOpenMMPfS_i, .-_Z12copyToOpenMMPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12copyToOpenMMPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12copyToOpenMMPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void copyToOpenMM( float *target, float *source, int N ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
int atom = elementNum / 3;
if( elementNum > N ) {
return;
}
//else target[elementNum] = source[elementNum];
else {
target[4 * atom + elementNum % 3] = source[elementNum];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copyToOpenMM( float *target, float *source, int N ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
int atom = elementNum / 3;
if( elementNum > N ) {
return;
}
//else target[elementNum] = source[elementNum];
else {
target[4 * atom + elementNum % 3] = source[elementNum];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copyToOpenMM( float *target, float *source, int N ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
int atom = elementNum / 3;
if( elementNum > N ) {
return;
}
//else target[elementNum] = source[elementNum];
else {
target[4 * atom + elementNum % 3] = source[elementNum];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12copyToOpenMMPfS_i
.globl _Z12copyToOpenMMPfS_i
.p2align 8
.type _Z12copyToOpenMMPfS_i,@function
_Z12copyToOpenMMPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_i32 v0, v1, 0x55555556
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshrrev_b32_e32 v3, 31, v0
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v0, 1, v0
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 2, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12copyToOpenMMPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12copyToOpenMMPfS_i, .Lfunc_end0-_Z12copyToOpenMMPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12copyToOpenMMPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12copyToOpenMMPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copyToOpenMM( float *target, float *source, int N ) {
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
int atom = elementNum / 3;
if( elementNum > N ) {
return;
}
//else target[elementNum] = source[elementNum];
else {
target[4 * atom + elementNum % 3] = source[elementNum];
}
}
|
.text
.file "copyToOpenMM.hip"
.globl _Z27__device_stub__copyToOpenMMPfS_i # -- Begin function _Z27__device_stub__copyToOpenMMPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__copyToOpenMMPfS_i,@function
_Z27__device_stub__copyToOpenMMPfS_i: # @_Z27__device_stub__copyToOpenMMPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12copyToOpenMMPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__copyToOpenMMPfS_i, .Lfunc_end0-_Z27__device_stub__copyToOpenMMPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12copyToOpenMMPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12copyToOpenMMPfS_i,@object # @_Z12copyToOpenMMPfS_i
.section .rodata,"a",@progbits
.globl _Z12copyToOpenMMPfS_i
.p2align 3, 0x0
_Z12copyToOpenMMPfS_i:
.quad _Z27__device_stub__copyToOpenMMPfS_i
.size _Z12copyToOpenMMPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12copyToOpenMMPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__copyToOpenMMPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12copyToOpenMMPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12copyToOpenMMPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R6, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0206 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.HI R4, R0, 0x55555556, RZ ; /* 0x5555555600047827 */
/* 0x000fca00078e02ff */
/*00b0*/ LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404057211 */
/* 0x000fca00078f08ff */
/*00c0*/ IMAD R0, R5, -0x3, R0 ; /* 0xfffffffd05007824 */
/* 0x000fca00078e0200 */
/*00d0*/ LEA R5, R5, R0, 0x2 ; /* 0x0000000005057211 */
/* 0x000fca00078e10ff */
/*00e0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0206 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12copyToOpenMMPfS_i
.globl _Z12copyToOpenMMPfS_i
.p2align 8
.type _Z12copyToOpenMMPfS_i,@function
_Z12copyToOpenMMPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_i32 v0, v1, 0x55555556
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshrrev_b32_e32 v3, 31, v0
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v0, 1, v0
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 2, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12copyToOpenMMPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12copyToOpenMMPfS_i, .Lfunc_end0-_Z12copyToOpenMMPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12copyToOpenMMPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12copyToOpenMMPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0006bb01_00000000-6_copyToOpenMM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i
.type _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i, @function
_Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12copyToOpenMMPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i, .-_Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i
.globl _Z12copyToOpenMMPfS_i
.type _Z12copyToOpenMMPfS_i, @function
_Z12copyToOpenMMPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12copyToOpenMMPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12copyToOpenMMPfS_i, .-_Z12copyToOpenMMPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12copyToOpenMMPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12copyToOpenMMPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "copyToOpenMM.hip"
.globl _Z27__device_stub__copyToOpenMMPfS_i # -- Begin function _Z27__device_stub__copyToOpenMMPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__copyToOpenMMPfS_i,@function
_Z27__device_stub__copyToOpenMMPfS_i: # @_Z27__device_stub__copyToOpenMMPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12copyToOpenMMPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__copyToOpenMMPfS_i, .Lfunc_end0-_Z27__device_stub__copyToOpenMMPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12copyToOpenMMPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12copyToOpenMMPfS_i,@object # @_Z12copyToOpenMMPfS_i
.section .rodata,"a",@progbits
.globl _Z12copyToOpenMMPfS_i
.p2align 3, 0x0
_Z12copyToOpenMMPfS_i:
.quad _Z27__device_stub__copyToOpenMMPfS_i
.size _Z12copyToOpenMMPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12copyToOpenMMPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__copyToOpenMMPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12copyToOpenMMPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <sys/time.h>
__global__ void square( int * d_in,int n){
int totalSum;
if (threadIdx.x == 0) totalSum = 0;
__syncthreads();
int localVal = d_in[threadIdx.x];
for(int i=0;i<n;i++)
atomicAdd(&totalSum, 1);
__syncthreads();
}
int main(int argc, char ** argv) {
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int * d_in;
cudaMalloc((void**) &d_in, ARRAY_BYTES);
// cudaMalloc((void*) &totalSum, sizeof(float));
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
for(int i=100;i<1000;i+=10){
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
for(int j=0;j<1000000;j++)
square<<<1, 64>>>(d_in,i);
gettimeofday(&tv2, NULL);
printf ("%d\t%f\n",i,
(double) (tv2.tv_usec - tv1.tv_usec) / 1000000 +
(double) (tv2.tv_sec - tv1.tv_sec));
}
// cudaMemcpy(ans, totalSum, sizeof(float), cudaMemcpyDeviceToHost);
// printf("%f\n",ans);
cudaFree(d_in);
return 0;
}
|
code for sm_80
Function : _Z6squarePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f01270 */
/*0030*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ BPT.TRAP 0x1 ; /* 0x000000040000795c */
/* 0x000fea0000300000 */
/*0060*/ BRA 0x60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <sys/time.h>
__global__ void square( int * d_in,int n){
int totalSum;
if (threadIdx.x == 0) totalSum = 0;
__syncthreads();
int localVal = d_in[threadIdx.x];
for(int i=0;i<n;i++)
atomicAdd(&totalSum, 1);
__syncthreads();
}
int main(int argc, char ** argv) {
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int * d_in;
cudaMalloc((void**) &d_in, ARRAY_BYTES);
// cudaMalloc((void*) &totalSum, sizeof(float));
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
for(int i=100;i<1000;i+=10){
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
for(int j=0;j<1000000;j++)
square<<<1, 64>>>(d_in,i);
gettimeofday(&tv2, NULL);
printf ("%d\t%f\n",i,
(double) (tv2.tv_usec - tv1.tv_usec) / 1000000 +
(double) (tv2.tv_sec - tv1.tv_sec));
}
// cudaMemcpy(ans, totalSum, sizeof(float), cudaMemcpyDeviceToHost);
// printf("%f\n",ans);
cudaFree(d_in);
return 0;
}
|
.file "tmpxft_001001f6_00000000-6_atomics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6squarePiiPii
.type _Z26__device_stub__Z6squarePiiPii, @function
_Z26__device_stub__Z6squarePiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6squarePiiPii, .-_Z26__device_stub__Z6squarePiiPii
.globl _Z6squarePii
.type _Z6squarePii, @function
_Z6squarePii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6squarePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePii, .-_Z6squarePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\t%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $336, %rsp
.cfi_def_cfa_offset 384
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, %ebp
leaq 32(%rsp), %r14
leaq 48(%rsp), %r13
leaq .LC1(%rip), %r12
jmp .L15
.L13:
subl $1, %ebx
je .L21
.L14:
movl $64, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6squarePiiPii
jmp .L13
.L21:
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
movq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movl %ebp, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $10, %ebp
cmpl $1000, %ebp
je .L22
.L15:
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
movl $1000000, %ebx
jmp .L14
.L22:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $336, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6squarePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <sys/time.h>
__global__ void square( int * d_in,int n){
int totalSum;
if (threadIdx.x == 0) totalSum = 0;
__syncthreads();
int localVal = d_in[threadIdx.x];
for(int i=0;i<n;i++)
atomicAdd(&totalSum, 1);
__syncthreads();
}
int main(int argc, char ** argv) {
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int * d_in;
cudaMalloc((void**) &d_in, ARRAY_BYTES);
// cudaMalloc((void*) &totalSum, sizeof(float));
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
for(int i=100;i<1000;i+=10){
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
for(int j=0;j<1000000;j++)
square<<<1, 64>>>(d_in,i);
gettimeofday(&tv2, NULL);
printf ("%d\t%f\n",i,
(double) (tv2.tv_usec - tv1.tv_usec) / 1000000 +
(double) (tv2.tv_sec - tv1.tv_sec));
}
// cudaMemcpy(ans, totalSum, sizeof(float), cudaMemcpyDeviceToHost);
// printf("%f\n",ans);
cudaFree(d_in);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
__global__ void square( int * d_in,int n){
int totalSum;
if (threadIdx.x == 0) totalSum = 0;
__syncthreads();
int localVal = d_in[threadIdx.x];
for(int i=0;i<n;i++)
atomicAdd(&totalSum, 1);
__syncthreads();
}
int main(int argc, char ** argv) {
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int * d_in;
hipMalloc((void**) &d_in, ARRAY_BYTES);
// cudaMalloc((void*) &totalSum, sizeof(float));
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
for(int i=100;i<1000;i+=10){
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
for(int j=0;j<1000000;j++)
square<<<1, 64>>>(d_in,i);
gettimeofday(&tv2, NULL);
printf ("%d\t%f\n",i,
(double) (tv2.tv_usec - tv1.tv_usec) / 1000000 +
(double) (tv2.tv_sec - tv1.tv_sec));
}
// cudaMemcpy(ans, totalSum, sizeof(float), cudaMemcpyDeviceToHost);
// printf("%f\n",ans);
hipFree(d_in);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
__global__ void square( int * d_in,int n){
int totalSum;
if (threadIdx.x == 0) totalSum = 0;
__syncthreads();
int localVal = d_in[threadIdx.x];
for(int i=0;i<n;i++)
atomicAdd(&totalSum, 1);
__syncthreads();
}
int main(int argc, char ** argv) {
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int * d_in;
hipMalloc((void**) &d_in, ARRAY_BYTES);
// cudaMalloc((void*) &totalSum, sizeof(float));
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
for(int i=100;i<1000;i+=10){
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
for(int j=0;j<1000000;j++)
square<<<1, 64>>>(d_in,i);
gettimeofday(&tv2, NULL);
printf ("%d\t%f\n",i,
(double) (tv2.tv_usec - tv1.tv_usec) / 1000000 +
(double) (tv2.tv_sec - tv1.tv_sec));
}
// cudaMemcpy(ans, totalSum, sizeof(float), cudaMemcpyDeviceToHost);
// printf("%f\n",ans);
hipFree(d_in);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePii
.globl _Z6squarePii
.p2align 8
.type _Z6squarePii,@function
_Z6squarePii:
s_load_b64 s[0:1], s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s1
v_mul_lo_u32 v2, s0, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v3, s1, v2
v_add_lshl_u32 v0, v2, v0, 2
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v1, 0
ds_store_b32 v0, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_load_b32 s0, s[2:3], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s0, 1
s_cbranch_scc1 .LBB0_4
.LBB0_3:
ds_load_b32 v1, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, 1, v1
ds_store_b32 v0, v1
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePii, .Lfunc_end0-_Z6squarePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
__global__ void square( int * d_in,int n){
int totalSum;
if (threadIdx.x == 0) totalSum = 0;
__syncthreads();
int localVal = d_in[threadIdx.x];
for(int i=0;i<n;i++)
atomicAdd(&totalSum, 1);
__syncthreads();
}
int main(int argc, char ** argv) {
const int ARRAY_SIZE = 64;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// generate the input array on the host
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int * d_in;
hipMalloc((void**) &d_in, ARRAY_BYTES);
// cudaMalloc((void*) &totalSum, sizeof(float));
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
for(int i=100;i<1000;i+=10){
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
for(int j=0;j<1000000;j++)
square<<<1, 64>>>(d_in,i);
gettimeofday(&tv2, NULL);
printf ("%d\t%f\n",i,
(double) (tv2.tv_usec - tv1.tv_usec) / 1000000 +
(double) (tv2.tv_sec - tv1.tv_sec));
}
// cudaMemcpy(ans, totalSum, sizeof(float), cudaMemcpyDeviceToHost);
// printf("%f\n",ans);
hipFree(d_in);
return 0;
}
|
.text
.file "atomics.hip"
.globl _Z21__device_stub__squarePii # -- Begin function _Z21__device_stub__squarePii
.p2align 4, 0x90
.type _Z21__device_stub__squarePii,@function
_Z21__device_stub__squarePii: # @_Z21__device_stub__squarePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePii, .Lfunc_end0-_Z21__device_stub__squarePii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 112(%rsp,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq (%rsp), %rdi
leaq 112(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movl $100, %r14d
leaq 63(%rbx), %r12
leaq 40(%rsp), %r13
leaq 16(%rsp), %rbp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq %rbp, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 104(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
subq 96(%rsp), %rax
divsd .LCPI1_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
leal 10(%r14), %eax
cmpl $990, %r14d # imm = 0x3DE
movl %eax, %r14d
jae .LBB1_8
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000000, %r15d # imm = 0xF4240
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
decl %r15d
je .LBB1_7
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6squarePii, %edi
movq %rbp, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_8:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePii,@object # @_Z6squarePii
.section .rodata,"a",@progbits
.globl _Z6squarePii
.p2align 3, 0x0
_Z6squarePii:
.quad _Z21__device_stub__squarePii
.size _Z6squarePii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t%f\n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6squarePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f01270 */
/*0030*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ BPT.TRAP 0x1 ; /* 0x000000040000795c */
/* 0x000fea0000300000 */
/*0060*/ BRA 0x60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePii
.globl _Z6squarePii
.p2align 8
.type _Z6squarePii,@function
_Z6squarePii:
s_load_b64 s[0:1], s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s1
v_mul_lo_u32 v2, s0, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v3, s1, v2
v_add_lshl_u32 v0, v2, v0, 2
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v1, 0
ds_store_b32 v0, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_load_b32 s0, s[2:3], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s0, 1
s_cbranch_scc1 .LBB0_4
.LBB0_3:
ds_load_b32 v1, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, 1, v1
ds_store_b32 v0, v1
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePii, .Lfunc_end0-_Z6squarePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001001f6_00000000-6_atomics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6squarePiiPii
.type _Z26__device_stub__Z6squarePiiPii, @function
_Z26__device_stub__Z6squarePiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6squarePiiPii, .-_Z26__device_stub__Z6squarePiiPii
.globl _Z6squarePii
.type _Z6squarePii, @function
_Z6squarePii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6squarePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePii, .-_Z6squarePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\t%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $336, %rsp
.cfi_def_cfa_offset 384
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, %ebp
leaq 32(%rsp), %r14
leaq 48(%rsp), %r13
leaq .LC1(%rip), %r12
jmp .L15
.L13:
subl $1, %ebx
je .L21
.L14:
movl $64, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6squarePiiPii
jmp .L13
.L21:
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
movq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movl %ebp, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $10, %ebp
cmpl $1000, %ebp
je .L22
.L15:
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
movl $1000000, %ebx
jmp .L14
.L22:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $336, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6squarePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "atomics.hip"
.globl _Z21__device_stub__squarePii # -- Begin function _Z21__device_stub__squarePii
.p2align 4, 0x90
.type _Z21__device_stub__squarePii,@function
_Z21__device_stub__squarePii: # @_Z21__device_stub__squarePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePii, .Lfunc_end0-_Z21__device_stub__squarePii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 112(%rsp,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq (%rsp), %rdi
leaq 112(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movl $100, %r14d
leaq 63(%rbx), %r12
leaq 40(%rsp), %r13
leaq 16(%rsp), %rbp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq %rbp, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 104(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
subq 96(%rsp), %rax
divsd .LCPI1_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
leal 10(%r14), %eax
cmpl $990, %r14d # imm = 0x3DE
movl %eax, %r14d
jae .LBB1_8
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $1000000, %r15d # imm = 0xF4240
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
decl %r15d
je .LBB1_7
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6squarePii, %edi
movq %rbp, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_8:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePii,@object # @_Z6squarePii
.section .rodata,"a",@progbits
.globl _Z6squarePii
.p2align 3, 0x0
_Z6squarePii:
.quad _Z21__device_stub__squarePii
.size _Z6squarePii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t%f\n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// My first CUDA program!
// 2018.9.1
#include <stdio.h>
__global__ void helloFromGPU(void)
{
printf("Hello GPU! from thread \n");
}
int main(void)
{
printf("Hello cPU! \n");
helloFromGPU <<<1,10>>>();
//cudaDeviceReset();
cudaDeviceSynchronize();
return 0;
}
|
code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// My first CUDA program!
// 2018.9.1
#include <stdio.h>
__global__ void helloFromGPU(void)
{
printf("Hello GPU! from thread \n");
}
int main(void)
{
printf("Hello cPU! \n");
helloFromGPU <<<1,10>>>();
//cudaDeviceReset();
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_0004f842_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello cPU! \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// My first CUDA program!
// 2018.9.1
#include <stdio.h>
__global__ void helloFromGPU(void)
{
printf("Hello GPU! from thread \n");
}
int main(void)
{
printf("Hello cPU! \n");
helloFromGPU <<<1,10>>>();
//cudaDeviceReset();
cudaDeviceSynchronize();
return 0;
}
|
// My first CUDA program!
// 2018.9.1
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloFromGPU(void)
{
printf("Hello GPU! from thread \n");
}
int main(void)
{
printf("Hello cPU! \n");
helloFromGPU <<<1,10>>>();
//cudaDeviceReset();
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// My first CUDA program!
// 2018.9.1
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloFromGPU(void)
{
printf("Hello GPU! from thread \n");
}
int main(void)
{
printf("Hello cPU! \n");
helloFromGPU <<<1,10>>>();
//cudaDeviceReset();
hipDeviceSynchronize();
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 25
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello GPU! from thread \n"
.size .str, 25
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// My first CUDA program!
// 2018.9.1
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloFromGPU(void)
{
printf("Hello GPU! from thread \n");
}
int main(void)
{
printf("Hello cPU! \n");
helloFromGPU <<<1,10>>>();
//cudaDeviceReset();
hipDeviceSynchronize();
return 0;
}
|
.text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello cPU! "
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 25
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello GPU! from thread \n"
.size .str, 25
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0004f842_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello cPU! \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello cPU! "
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__device__ int isPrimeGPU(long x) {
long long i;
for (i = 2; i * i < x + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__host__ int isPrime(long x) {
long i;
for (i = 2; i < sqrt(x) + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__global__ void primeFind(int* c, long n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
c[0] = (int)0;
c[1] = (int)0;
c[2] = (int)1;
long num = (id * 2)-1;
if (id < ((n/2)+1) && 1 < id) {//global thread 0 and 1 dont do anything need to deal with
if (id * 2 < n) {//even numbers
c[id * 2] = 0;
}
if (num < n) {//odd numbers
c[num] = isPrimeGPU(num);
}
}
}
int main(int argc, const char* argv[]) {
if (argc < 3){
printf("Usage: prime upbound\n");
exit(-1);
}
// Size of vectors
long n = atoi(argv[1]);
printf("n = %ld \n", n);
if(n <= 0){
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
int blockSize = atoi(argv[2]);
printf("block size = %d \n", blockSize);
// Host output
int* cpuOutput;
//Device output vector
int* gpuOutput;
// Size, in bytes, of each output
size_t bytes = (unsigned long long)n * sizeof(int);
// Allocate memory for each vector on host
cpuOutput = (int*)malloc(bytes);//pc results new int[n]
gpuOutput = (int*)malloc(bytes);//gpu results
//initalize
for (long j = 0; j < n; j++) {
cpuOutput[j] = 0;
gpuOutput[j] = 0;
}
clock_t cStart = clock();
double cpuStart = (double) cStart/CLOCKS_PER_SEC;//
///////////////////////////////////////////////////////////////////////////////////
//do it on cpu
//TODO add systime to check how long it takes
cpuOutput[0] = (int)0;
cpuOutput[1] = (int)0;
cpuOutput[2] = (int)1;
for (long i = 2; i < (n/2)+1; i++) {
long num = (i * 2) - 1;
if (i * 2 < n) {
cpuOutput[i * 2] = 0;
}
if (num < n) {
cpuOutput[num] = isPrime(num);
}
}
clock_t cEnd = clock();
double cpuEnd = (double)cEnd/CLOCKS_PER_SEC;
//sum up pc result of # of primes
int sum = 0;
for (int i = 0; i < n; i++) {
sum += (int)cpuOutput[i];
}
printf("CPU final result: %d\n", sum);
double cpuTotal = cpuEnd - cpuStart;
printf("CPU took %lf seconds to find primes numbers up to %ld\n", cpuTotal, n);
////////////////////////////////////////////////////////////////////////
//do it on gpu
//TODO sys clock time for seeing how much time it takes
clock_t gStart = clock();
double gpuStart = (double)gStart / CLOCKS_PER_SEC;;
//Device output vector
int* d_output;
// Allocate memory for each vector on GPU
cudaMalloc(&d_output, bytes);
// Copy host vectors to device//i dont think we need to do this
cudaMemcpy(d_output, gpuOutput, bytes, cudaMemcpyHostToDevice);
int gridSize;
// Number of thread blocks in grid
gridSize = (int)ceil((double)((double)((n+1)/2)/blockSize));
primeFind<<<gridSize, blockSize>>>(d_output, n);
// Copy array back to host
cudaMemcpy(gpuOutput, d_output, bytes, cudaMemcpyDeviceToHost);
clock_t gEnd = clock();
double gpuEnd = (double)gEnd / CLOCKS_PER_SEC;
// Sum up vector c and print result divided by n, this should equal 1 without error
sum = 0;
for (long i = 2; i < n; i++) {
sum += (int)gpuOutput[i];
}
printf("GPU final result: %d\n", sum);
long double gpuTotal = gpuEnd - gpuStart;
printf("GPU took %Lf seconds to find primes numbers up to %ld\n", gpuTotal, n);
printf("GPU speeds up the process %Lf times.\n", cpuTotal / gpuTotal);
// Release device memory
cudaFree(d_output);
// Release host memory
free(cpuOutput);
free(gpuOutput);
return 0;
}
|
code for sm_80
Function : _Z9primeFindPil
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0040*/ ULEA.HI UR4, UP0, UR5, UR4, URZ, 0x1 ; /* 0x0000000405047291 */
/* 0x000fe2000f81083f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0070*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc800087fe43f */
/*0080*/ USHF.R.S64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe40008001005 */
/*0090*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe20008011405 */
/*00a0*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*00b0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*00c0*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe40000011404 */
/*00d0*/ ISETP.LE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe2000bf03070 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ ISETP.GE.AND.EX P0, PT, R3, R0, PT, P0 ; /* 0x000000000300720c */
/* 0x000fe20003f06300 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.LT.OR P0, PT, R4, 0x2, !P0 ; /* 0x000000020400780c */
/* 0x000fe40004701670 */
/*0120*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x0001e8000c101904 */
/*0130*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101904 */
/*0140*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x0001e6000c101904 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.SHL.U32 R2, R4, 0x2, RZ ; /* 0x0000000204027824 */
/* 0x001fca00078e00ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe40003f06070 */
/*0180*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0190*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fe40003f06300 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f26070 */
/*01c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*01d0*/ ISETP.GE.AND.EX P1, PT, R5, c[0x0][0x16c], PT, P1 ; /* 0x00005b0005007a0c */
/* 0x000fca0003f26310 */
/*01e0*/ @!P0 LEA R6, P2, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002068a11 */
/* 0x000fc800078410ff */
/*01f0*/ @!P0 LEA.HI.X R7, R2, c[0x0][0x164], R3, 0x2, P2 ; /* 0x0000590002078a11 */
/* 0x000fca00010f1403 */
/*0200*/ @!P0 STG.E [R6.64], RZ ; /* 0x000000ff06008986 */
/* 0x0001e2000c101904 */
/*0210*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0220*/ ISETP.GE.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06270 */
/*0230*/ BSSY B0, 0x530 ; /* 0x000002f000007945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x001fd600078e00ff */
/*0250*/ @!P0 BRA 0x520 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fca00078e00ff */
/*0280*/ LOP3.LUT R2, R5, R6, RZ, 0xfc, !PT ; /* 0x0000000605027212 */
/* 0x000fe200078efcff */
/*0290*/ BSSY B1, 0x450 ; /* 0x000001b000017945 */
/* 0x000fe60003800000 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05070 */
/*02b0*/ @!P0 BRA 0x310 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02c0*/ MOV R4, 0x2e0 ; /* 0x000002e000047802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x570 ; /* 0x0000029000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*02f0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f05300 */
/*0300*/ BRA 0x440 ; /* 0x0000013000007947 */
/* 0x000fee0003800000 */
/*0310*/ I2F.U32.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209000 */
/*0320*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f25070 */
/*0330*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0340*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0350*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0370*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a03 */
/*0380*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fc800078e02ff */
/*0390*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*03a0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*03b0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*03c0*/ IMAD R8, R7, R3, R0 ; /* 0x0000000307087224 */
/* 0x000fca00078e0200 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06070 */
/*03e0*/ @P0 IMAD.IADD R8, R8, 0x1, -R7 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a07 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06070 */
/*0400*/ @P0 IMAD.IADD R8, R8, 0x1, -R7 ; /* 0x0000000108080824 */
/* 0x000fe200078e0a07 */
/*0410*/ @!P1 LOP3.LUT R8, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff089212 */
/* 0x000fc800078e33ff */
/*0420*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0430*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd00003f05300 */
/*0440*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R2, P1, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007f3e0ff */
/*0460*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0470*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0480*/ @!P0 BRA 0x520 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0002 */
/*04a0*/ IMAD R4, R6, R7.reuse, RZ ; /* 0x0000000706047224 */
/* 0x080fe400078e02ff */
/*04b0*/ IMAD.WIDE.U32 R2, R7, R7, RZ ; /* 0x0000000707027225 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD R9, R7, R6, R4 ; /* 0x0000000607097224 */
/* 0x000fe200078e0204 */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R2, R0, PT ; /* 0x000000000200720c */
/* 0x000fc80003f04070 */
/*04e0*/ IADD3 R2, R3, R9, RZ ; /* 0x0000000903027210 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GT.AND.EX P0, PT, R2, R5, PT, P0 ; /* 0x000000050200720c */
/* 0x000fda0003f04300 */
/*0500*/ @!P0 BRA 0x280 ; /* 0xfffffd7000008947 */
/* 0x000fea000383ffff */
/*0510*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*0540*/ LEA.HI.X R3, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1405 */
/*0550*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ IADD3 R2, P1, RZ, -R7, RZ ; /* 0x80000007ff027210 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f06270 */
/*0590*/ IMAD.X R3, RZ, RZ, ~R6, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0e06 */
/*05a0*/ SEL R2, R2, R7, !P0 ; /* 0x0000000702027207 */
/* 0x000fc80004000000 */
/*05b0*/ SEL R3, R3, R6, !P0 ; /* 0x0000000603037207 */
/* 0x000fc80004000000 */
/*05c0*/ I2F.U64.RP R12, R2 ; /* 0x00000002000c7312 */
/* 0x000e300000309000 */
/*05d0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*05e0*/ IADD3 R8, R12, 0x1ffffffe, RZ ; /* 0x1ffffffe0c087810 */
/* 0x001fcc0007ffe0ff */
/*05f0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*0600*/ IMAD.WIDE.U32 R10, R8, R2, RZ ; /* 0x00000002080a7225 */
/* 0x001fc800078e00ff */
/*0610*/ IMAD R11, R8, R3, R11 ; /* 0x00000003080b7224 */
/* 0x000fe200078e020b */
/*0620*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fc60007f1e0ff */
/*0630*/ IMAD R11, R9, R2, R11 ; /* 0x00000002090b7224 */
/* 0x000fe400078e020b */
/*0640*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc800078e00ff */
/*0650*/ IMAD.X R15, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0e0b */
/*0660*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0670*/ IMAD R17, R9, R15.reuse, RZ ; /* 0x0000000f09117224 */
/* 0x080fe400078e02ff */
/*0680*/ IMAD.WIDE.U32 R10, P0, R8, R15, R10 ; /* 0x0000000f080a7225 */
/* 0x000fc8000780000a */
/*0690*/ IMAD.HI.U32 R15, R9, R15, RZ ; /* 0x0000000f090f7227 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fca000782000a */
/*06b0*/ IADD3 R11, P2, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x000fe20007f5e0ff */
/*06c0*/ IMAD.X R10, R15, 0x1, R9, P0 ; /* 0x000000010f0a7824 */
/* 0x000fc800000e0609 */
/*06d0*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fe200078e00ff */
/*06e0*/ IADD3.X R13, RZ, RZ, R10, P2, P1 ; /* 0x000000ffff0d7210 */
/* 0x000fe400017e240a */
/*06f0*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f26270 */
/*0700*/ IMAD R9, R11, R3, R9 ; /* 0x000000030b097224 */
/* 0x000fe200078e0209 */
/*0710*/ IADD3 R15, P0, RZ, -R8, RZ ; /* 0x80000008ff0f7210 */
/* 0x000fc60007f1e0ff */
/*0720*/ IMAD R9, R13, R2, R9 ; /* 0x000000020d097224 */
/* 0x000fe400078e0209 */
/*0730*/ IMAD.HI.U32 R10, R11, R15, RZ ; /* 0x0000000f0b0a7227 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.X R8, RZ, RZ, ~R9, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e09 */
/*0750*/ IADD3 R9, P4, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fc60007f9e0ff */
/*0760*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fc8000780000a */
/*0770*/ IMAD.X R12, RZ, RZ, ~R5, P4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400020e0e05 */
/*0780*/ IMAD.HI.U32 R10, P2, R13, R15, R10 ; /* 0x0000000f0d0a7227 */
/* 0x000fe2000784000a */
/*0790*/ SEL R11, R9, R0, !P1 ; /* 0x00000000090b7207 */
/* 0x000fe40004800000 */
/*07a0*/ SEL R12, R12, R5, !P1 ; /* 0x000000050c0c7207 */
/* 0x000fe20004800000 */
/*07b0*/ IMAD R15, R13.reuse, R8.reuse, RZ ; /* 0x000000080d0f7224 */
/* 0x0c0fe400078e02ff */
/*07c0*/ IMAD.HI.U32 R8, R13, R8, RZ ; /* 0x000000080d087227 */
/* 0x000fc600078e00ff */
/*07d0*/ IADD3 R10, P3, R15, R10, RZ ; /* 0x0000000a0f0a7210 */
/* 0x000fe20007f7e0ff */
/*07e0*/ IMAD.X R13, R8, 0x1, R13, P0 ; /* 0x00000001080d7824 */
/* 0x000fe400000e060d */
/*07f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0800*/ IMAD.HI.U32 R8, R10, R11, RZ ; /* 0x0000000b0a087227 */
/* 0x000fe200078e00ff */
/*0810*/ IADD3.X R13, RZ, RZ, R13, P3, P2 ; /* 0x000000ffff0d7210 */
/* 0x000fca0001fe440d */
/*0820*/ IMAD.WIDE.U32 R8, R10, R12, R8 ; /* 0x0000000c0a087225 */
/* 0x000fc800078e0008 */
/*0830*/ IMAD R15, R13.reuse, R12, RZ ; /* 0x0000000c0d0f7224 */
/* 0x040fe400078e02ff */
/*0840*/ IMAD.HI.U32 R8, P0, R13, R11, R8 ; /* 0x0000000b0d087227 */
/* 0x000fc80007800008 */
/*0850*/ IMAD.HI.U32 R10, R13, R12, RZ ; /* 0x0000000c0d0a7227 */
/* 0x000fe200078e00ff */
/*0860*/ IADD3 R13, P2, R15, R8, RZ ; /* 0x000000080f0d7210 */
/* 0x000fc80007f5e0ff */
/*0870*/ IADD3.X R10, R10, RZ, RZ, P0, !PT ; /* 0x000000ff0a0a7210 */
/* 0x000fe200007fe4ff */
/*0880*/ IMAD.WIDE.U32 R8, R13, R2, RZ ; /* 0x000000020d087225 */
/* 0x000fc800078e00ff */
/*0890*/ IMAD.X R15, RZ, RZ, R10, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060a */
/*08a0*/ IMAD R13, R13, R3, R9 ; /* 0x000000030d0d7224 */
/* 0x000fe200078e0209 */
/*08b0*/ IADD3 R9, P2, -R8, R11, RZ ; /* 0x0000000b08097210 */
/* 0x000fc60007f5e1ff */
/*08c0*/ IMAD R13, R15, R2.reuse, R13 ; /* 0x000000020f0d7224 */
/* 0x080fe200078e020d */
/*08d0*/ ISETP.GE.U32.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fc60003f06070 */
/*08e0*/ IMAD.X R15, R12, 0x1, ~R13, P2 ; /* 0x000000010c0f7824 */
/* 0x000fe200010e0e0d */
/*08f0*/ IADD3 R11, P2, R9, -R2, RZ ; /* 0x80000002090b7210 */
/* 0x000fc80007f5e0ff */
/*0900*/ ISETP.GE.U32.AND.EX P0, PT, R15.reuse, R3, PT, P0 ; /* 0x000000030f00720c */
/* 0x040fe20003f06100 */
/*0910*/ IMAD.X R13, R15, 0x1, ~R3, P2 ; /* 0x000000010f0d7824 */
/* 0x000fc600010e0e03 */
/*0920*/ SEL R11, R11, R9, P0 ; /* 0x000000090b0b7207 */
/* 0x000fe40000000000 */
/*0930*/ SEL R13, R13, R15, P0 ; /* 0x0000000f0d0d7207 */
/* 0x000fe40000000000 */
/*0940*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R2.reuse, PT ; /* 0x000000020b00720c */
/* 0x0c0fe40003f06070 */
/*0950*/ IADD3 R8, P2, R11, -R2, RZ ; /* 0x800000020b087210 */
/* 0x000fe40007f5e0ff */
/*0960*/ ISETP.GE.U32.AND.EX P0, PT, R13, R3, PT, P0 ; /* 0x000000030d00720c */
/* 0x000fc60003f06100 */
/*0970*/ IMAD.X R9, R13, 0x1, ~R3, P2 ; /* 0x000000010d097824 */
/* 0x000fe200010e0e03 */
/*0980*/ SEL R8, R8, R11, P0 ; /* 0x0000000b08087207 */
/* 0x000fc80000000000 */
/*0990*/ SEL R9, R9, R13, P0 ; /* 0x0000000d09097207 */
/* 0x000fe40000000000 */
/*09a0*/ IADD3 R3, P2, RZ, -R8.reuse, RZ ; /* 0x80000008ff037210 */
/* 0x080fe40007f5e0ff */
/*09b0*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05070 */
/*09c0*/ SEL R8, R3, R8, !P1 ; /* 0x0000000803087207 */
/* 0x000fe20004800000 */
/*09d0*/ IMAD.X R2, RZ, RZ, ~R9, P2 ; /* 0x000000ffff027224 */
/* 0x000fe200010e0e09 */
/*09e0*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fe20003f05300 */
/*09f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc600078e00ff */
/*0a00*/ SEL R9, R2, R9, !P1 ; /* 0x0000000902097207 */
/* 0x000fe20004800000 */
/*0a10*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0a20*/ SEL R8, R8, 0xffffffff, P0 ; /* 0xffffffff08087807 */
/* 0x000fe40000000000 */
/*0a30*/ SEL R9, R9, 0xffffffff, P0 ; /* 0xffffffff09097807 */
/* 0x000fe20000000000 */
/*0a40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff5b002007950 */
/* 0x000fec0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__device__ int isPrimeGPU(long x) {
long long i;
for (i = 2; i * i < x + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__host__ int isPrime(long x) {
long i;
for (i = 2; i < sqrt(x) + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__global__ void primeFind(int* c, long n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
c[0] = (int)0;
c[1] = (int)0;
c[2] = (int)1;
long num = (id * 2)-1;
if (id < ((n/2)+1) && 1 < id) {//global thread 0 and 1 dont do anything need to deal with
if (id * 2 < n) {//even numbers
c[id * 2] = 0;
}
if (num < n) {//odd numbers
c[num] = isPrimeGPU(num);
}
}
}
int main(int argc, const char* argv[]) {
if (argc < 3){
printf("Usage: prime upbound\n");
exit(-1);
}
// Size of vectors
long n = atoi(argv[1]);
printf("n = %ld \n", n);
if(n <= 0){
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
int blockSize = atoi(argv[2]);
printf("block size = %d \n", blockSize);
// Host output
int* cpuOutput;
//Device output vector
int* gpuOutput;
// Size, in bytes, of each output
size_t bytes = (unsigned long long)n * sizeof(int);
// Allocate memory for each vector on host
cpuOutput = (int*)malloc(bytes);//pc results new int[n]
gpuOutput = (int*)malloc(bytes);//gpu results
//initalize
for (long j = 0; j < n; j++) {
cpuOutput[j] = 0;
gpuOutput[j] = 0;
}
clock_t cStart = clock();
double cpuStart = (double) cStart/CLOCKS_PER_SEC;//
///////////////////////////////////////////////////////////////////////////////////
//do it on cpu
//TODO add systime to check how long it takes
cpuOutput[0] = (int)0;
cpuOutput[1] = (int)0;
cpuOutput[2] = (int)1;
for (long i = 2; i < (n/2)+1; i++) {
long num = (i * 2) - 1;
if (i * 2 < n) {
cpuOutput[i * 2] = 0;
}
if (num < n) {
cpuOutput[num] = isPrime(num);
}
}
clock_t cEnd = clock();
double cpuEnd = (double)cEnd/CLOCKS_PER_SEC;
//sum up pc result of # of primes
int sum = 0;
for (int i = 0; i < n; i++) {
sum += (int)cpuOutput[i];
}
printf("CPU final result: %d\n", sum);
double cpuTotal = cpuEnd - cpuStart;
printf("CPU took %lf seconds to find primes numbers up to %ld\n", cpuTotal, n);
////////////////////////////////////////////////////////////////////////
//do it on gpu
//TODO sys clock time for seeing how much time it takes
clock_t gStart = clock();
double gpuStart = (double)gStart / CLOCKS_PER_SEC;;
//Device output vector
int* d_output;
// Allocate memory for each vector on GPU
cudaMalloc(&d_output, bytes);
// Copy host vectors to device//i dont think we need to do this
cudaMemcpy(d_output, gpuOutput, bytes, cudaMemcpyHostToDevice);
int gridSize;
// Number of thread blocks in grid
gridSize = (int)ceil((double)((double)((n+1)/2)/blockSize));
primeFind<<<gridSize, blockSize>>>(d_output, n);
// Copy array back to host
cudaMemcpy(gpuOutput, d_output, bytes, cudaMemcpyDeviceToHost);
clock_t gEnd = clock();
double gpuEnd = (double)gEnd / CLOCKS_PER_SEC;
// Sum up vector c and print result divided by n, this should equal 1 without error
sum = 0;
for (long i = 2; i < n; i++) {
sum += (int)gpuOutput[i];
}
printf("GPU final result: %d\n", sum);
long double gpuTotal = gpuEnd - gpuStart;
printf("GPU took %Lf seconds to find primes numbers up to %ld\n", gpuTotal, n);
printf("GPU speeds up the process %Lf times.\n", cpuTotal / gpuTotal);
// Release device memory
cudaFree(d_output);
// Release host memory
free(cpuOutput);
free(gpuOutput);
return 0;
}
|
.file "tmpxft_000b0faf_00000000-6_lab1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10isPrimeGPUl
.type _Z10isPrimeGPUl, @function
_Z10isPrimeGPUl:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10isPrimeGPUl, .-_Z10isPrimeGPUl
.globl _Z7isPrimel
.type _Z7isPrimel, @function
_Z7isPrimel:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl $2, %ebx
jmp .L6
.L17:
addq $1, %rbx
.L6:
pxor %xmm2, %xmm2
cvtsi2sdq %rbx, %xmm2
movsd %xmm2, 8(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L14
sqrtsd %xmm0, %xmm0
.L10:
addsd .LC1(%rip), %xmm0
comisd 8(%rsp), %xmm0
jbe .L16
movq %rbp, %rax
cqto
idivq %rbx
testq %rdx, %rdx
jne .L17
movl $0, %eax
jmp .L5
.L14:
call sqrt@PLT
jmp .L10
.L16:
movl $1, %eax
.L5:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7isPrimel, .-_Z7isPrimel
.globl _Z29__device_stub__Z9primeFindPilPil
.type _Z29__device_stub__Z9primeFindPilPil, @function
_Z29__device_stub__Z9primeFindPilPil:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9primeFindPil(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z9primeFindPilPil, .-_Z29__device_stub__Z9primeFindPilPil
.globl _Z9primeFindPil
.type _Z9primeFindPil, @function
_Z9primeFindPil:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9primeFindPilPil
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9primeFindPil, .-_Z9primeFindPil
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Usage: prime upbound\n"
.LC3:
.string "n = %ld \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Usage: prime upbound, you input invalid upbound number!\n"
.section .rodata.str1.1
.LC5:
.string "block size = %d \n"
.LC7:
.string "CPU final result: %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "CPU took %lf seconds to find primes numbers up to %ld\n"
.section .rodata.str1.1
.LC11:
.string "GPU final result: %d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "GPU took %Lf seconds to find primes numbers up to %ld\n"
.align 8
.LC13:
.string "GPU speeds up the process %Lf times.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jle .L46
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movslq %eax, %rbp
movq %rbp, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbp, %rbp
jle .L47
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 24(%rsp), %rax
leaq 0(,%rax,4), %rbx
movq %rbx, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movl $0, %ebx
.L29:
movl $0, 0(%r13,%rbx,4)
movl $0, (%r14,%rbx,4)
movq %rbx, (%rsp)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L29
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movsd %xmm0, 40(%rsp)
movl $0, 0(%r13)
movl $0, 4(%r13)
movl $1, 8(%r13)
movq %rbx, %r15
shrq $63, %r15
addq %rbx, %r15
sarq %r15
cmpq $3, %rbx
jle .L30
movl $3, %r12d
movl $2, %ebp
jmp .L33
.L46:
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L47:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
cmpq %rbx, %rdi
jl .L48
.L32:
addq $1, %rbp
addq $2, %r12
cmpq %r15, %rbp
jg .L30
.L33:
movq %r12, %rdi
leaq (%rbp,%rbp), %rax
cmpq %rax, %rbx
jle .L31
movl $0, 0(%r13,%rbp,8)
jmp .L31
.L48:
call _Z7isPrimel
movl %eax, 0(%r13,%r12,4)
jmp .L32
.L30:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movq %xmm0, %rbp
movq %r13, %rax
movq 24(%rsp), %rsi
leal -1(%rsi), %edx
leaq 4(%r13,%rdx,4), %rsi
movl $0, %ecx
.L34:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L34
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %xmm5
subsd 40(%rsp), %xmm5
movsd %xmm5, 24(%rsp)
movq %rbx, %rdx
movapd %xmm5, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movsd %xmm0, 40(%rsp)
leaq 56(%rsp), %rdi
movq 16(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rax
addq $2, %rax
movq %rax, %rdx
shrq $63, %rdx
addq %rdx, %rax
sarq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 32(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC14(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC9(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L35
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC1(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L35:
movl 32(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
cvttsd2sil %xmm3, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L36:
movl $2, %ecx
movq 16(%rsp), %r15
movq %r15, %rdx
movq 56(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movq %xmm0, %rbp
cmpq $2, %rbx
jle .L40
leaq 8(%r14), %rax
movq %r15, %rcx
addq %r14, %rcx
movl $0, %edx
.L38:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L38
.L37:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %xmm6
subsd 40(%rsp), %xmm6
movsd %xmm6, (%rsp)
fldl (%rsp)
fld %st(0)
fstpt (%rsp)
leaq -16(%rsp), %rsp
.cfi_def_cfa_offset 176
fstpt (%rsp)
movq %rbx, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
fldt 16(%rsp)
fdivrl 40(%rsp)
fstpt (%rsp)
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq %rbx, %rsi
movq 56(%rsp), %rdi
call _Z29__device_stub__Z9primeFindPilPil
jmp .L36
.L40:
movl $0, %edx
jmp .L37
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z9primeFindPil"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z9primeFindPil(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC6:
.long 0
.long 1093567616
.align 8
.LC9:
.long 0
.long 1127219200
.align 8
.LC14:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__device__ int isPrimeGPU(long x) {
long long i;
for (i = 2; i * i < x + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__host__ int isPrime(long x) {
long i;
for (i = 2; i < sqrt(x) + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__global__ void primeFind(int* c, long n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
c[0] = (int)0;
c[1] = (int)0;
c[2] = (int)1;
long num = (id * 2)-1;
if (id < ((n/2)+1) && 1 < id) {//global thread 0 and 1 dont do anything need to deal with
if (id * 2 < n) {//even numbers
c[id * 2] = 0;
}
if (num < n) {//odd numbers
c[num] = isPrimeGPU(num);
}
}
}
int main(int argc, const char* argv[]) {
if (argc < 3){
printf("Usage: prime upbound\n");
exit(-1);
}
// Size of vectors
long n = atoi(argv[1]);
printf("n = %ld \n", n);
if(n <= 0){
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
int blockSize = atoi(argv[2]);
printf("block size = %d \n", blockSize);
// Host output
int* cpuOutput;
//Device output vector
int* gpuOutput;
// Size, in bytes, of each output
size_t bytes = (unsigned long long)n * sizeof(int);
// Allocate memory for each vector on host
cpuOutput = (int*)malloc(bytes);//pc results new int[n]
gpuOutput = (int*)malloc(bytes);//gpu results
//initalize
for (long j = 0; j < n; j++) {
cpuOutput[j] = 0;
gpuOutput[j] = 0;
}
clock_t cStart = clock();
double cpuStart = (double) cStart/CLOCKS_PER_SEC;//
///////////////////////////////////////////////////////////////////////////////////
//do it on cpu
//TODO add systime to check how long it takes
cpuOutput[0] = (int)0;
cpuOutput[1] = (int)0;
cpuOutput[2] = (int)1;
for (long i = 2; i < (n/2)+1; i++) {
long num = (i * 2) - 1;
if (i * 2 < n) {
cpuOutput[i * 2] = 0;
}
if (num < n) {
cpuOutput[num] = isPrime(num);
}
}
clock_t cEnd = clock();
double cpuEnd = (double)cEnd/CLOCKS_PER_SEC;
//sum up pc result of # of primes
int sum = 0;
for (int i = 0; i < n; i++) {
sum += (int)cpuOutput[i];
}
printf("CPU final result: %d\n", sum);
double cpuTotal = cpuEnd - cpuStart;
printf("CPU took %lf seconds to find primes numbers up to %ld\n", cpuTotal, n);
////////////////////////////////////////////////////////////////////////
//do it on gpu
//TODO sys clock time for seeing how much time it takes
clock_t gStart = clock();
double gpuStart = (double)gStart / CLOCKS_PER_SEC;;
//Device output vector
int* d_output;
// Allocate memory for each vector on GPU
cudaMalloc(&d_output, bytes);
// Copy host vectors to device//i dont think we need to do this
cudaMemcpy(d_output, gpuOutput, bytes, cudaMemcpyHostToDevice);
int gridSize;
// Number of thread blocks in grid
gridSize = (int)ceil((double)((double)((n+1)/2)/blockSize));
primeFind<<<gridSize, blockSize>>>(d_output, n);
// Copy array back to host
cudaMemcpy(gpuOutput, d_output, bytes, cudaMemcpyDeviceToHost);
clock_t gEnd = clock();
double gpuEnd = (double)gEnd / CLOCKS_PER_SEC;
// Sum up vector c and print result divided by n, this should equal 1 without error
sum = 0;
for (long i = 2; i < n; i++) {
sum += (int)gpuOutput[i];
}
printf("GPU final result: %d\n", sum);
long double gpuTotal = gpuEnd - gpuStart;
printf("GPU took %Lf seconds to find primes numbers up to %ld\n", gpuTotal, n);
printf("GPU speeds up the process %Lf times.\n", cpuTotal / gpuTotal);
// Release device memory
cudaFree(d_output);
// Release host memory
free(cpuOutput);
free(gpuOutput);
return 0;
}
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include "hip/hip_runtime.h"
__device__ int isPrimeGPU(long x) {
long long i;
for (i = 2; i * i < x + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__host__ int isPrime(long x) {
long i;
for (i = 2; i < sqrt(x) + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__global__ void primeFind(int* c, long n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
c[0] = (int)0;
c[1] = (int)0;
c[2] = (int)1;
long num = (id * 2)-1;
if (id < ((n/2)+1) && 1 < id) {//global thread 0 and 1 dont do anything need to deal with
if (id * 2 < n) {//even numbers
c[id * 2] = 0;
}
if (num < n) {//odd numbers
c[num] = isPrimeGPU(num);
}
}
}
int main(int argc, const char* argv[]) {
if (argc < 3){
printf("Usage: prime upbound\n");
exit(-1);
}
// Size of vectors
long n = atoi(argv[1]);
printf("n = %ld \n", n);
if(n <= 0){
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
int blockSize = atoi(argv[2]);
printf("block size = %d \n", blockSize);
// Host output
int* cpuOutput;
//Device output vector
int* gpuOutput;
// Size, in bytes, of each output
size_t bytes = (unsigned long long)n * sizeof(int);
// Allocate memory for each vector on host
cpuOutput = (int*)malloc(bytes);//pc results new int[n]
gpuOutput = (int*)malloc(bytes);//gpu results
//initalize
for (long j = 0; j < n; j++) {
cpuOutput[j] = 0;
gpuOutput[j] = 0;
}
clock_t cStart = clock();
double cpuStart = (double) cStart/CLOCKS_PER_SEC;//
///////////////////////////////////////////////////////////////////////////////////
//do it on cpu
//TODO add systime to check how long it takes
cpuOutput[0] = (int)0;
cpuOutput[1] = (int)0;
cpuOutput[2] = (int)1;
for (long i = 2; i < (n/2)+1; i++) {
long num = (i * 2) - 1;
if (i * 2 < n) {
cpuOutput[i * 2] = 0;
}
if (num < n) {
cpuOutput[num] = isPrime(num);
}
}
clock_t cEnd = clock();
double cpuEnd = (double)cEnd/CLOCKS_PER_SEC;
//sum up pc result of # of primes
int sum = 0;
for (int i = 0; i < n; i++) {
sum += (int)cpuOutput[i];
}
printf("CPU final result: %d\n", sum);
double cpuTotal = cpuEnd - cpuStart;
printf("CPU took %lf seconds to find primes numbers up to %ld\n", cpuTotal, n);
////////////////////////////////////////////////////////////////////////
//do it on gpu
//TODO sys clock time for seeing how much time it takes
clock_t gStart = clock();
double gpuStart = (double)gStart / CLOCKS_PER_SEC;;
//Device output vector
int* d_output;
// Allocate memory for each vector on GPU
hipMalloc(&d_output, bytes);
// Copy host vectors to device//i dont think we need to do this
hipMemcpy(d_output, gpuOutput, bytes, hipMemcpyHostToDevice);
int gridSize;
// Number of thread blocks in grid
gridSize = (int)ceil((double)((double)((n+1)/2)/blockSize));
primeFind<<<gridSize, blockSize>>>(d_output, n);
// Copy array back to host
hipMemcpy(gpuOutput, d_output, bytes, hipMemcpyDeviceToHost);
clock_t gEnd = clock();
double gpuEnd = (double)gEnd / CLOCKS_PER_SEC;
// Sum up vector c and print result divided by n, this should equal 1 without error
sum = 0;
for (long i = 2; i < n; i++) {
sum += (int)gpuOutput[i];
}
printf("GPU final result: %d\n", sum);
long double gpuTotal = gpuEnd - gpuStart;
printf("GPU took %Lf seconds to find primes numbers up to %ld\n", gpuTotal, n);
printf("GPU speeds up the process %Lf times.\n", cpuTotal / gpuTotal);
// Release device memory
hipFree(d_output);
// Release host memory
free(cpuOutput);
free(gpuOutput);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include "hip/hip_runtime.h"
__device__ int isPrimeGPU(long x) {
long long i;
for (i = 2; i * i < x + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__host__ int isPrime(long x) {
long i;
for (i = 2; i < sqrt(x) + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__global__ void primeFind(int* c, long n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
c[0] = (int)0;
c[1] = (int)0;
c[2] = (int)1;
long num = (id * 2)-1;
if (id < ((n/2)+1) && 1 < id) {//global thread 0 and 1 dont do anything need to deal with
if (id * 2 < n) {//even numbers
c[id * 2] = 0;
}
if (num < n) {//odd numbers
c[num] = isPrimeGPU(num);
}
}
}
int main(int argc, const char* argv[]) {
if (argc < 3){
printf("Usage: prime upbound\n");
exit(-1);
}
// Size of vectors
long n = atoi(argv[1]);
printf("n = %ld \n", n);
if(n <= 0){
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
int blockSize = atoi(argv[2]);
printf("block size = %d \n", blockSize);
// Host output
int* cpuOutput;
//Device output vector
int* gpuOutput;
// Size, in bytes, of each output
size_t bytes = (unsigned long long)n * sizeof(int);
// Allocate memory for each vector on host
cpuOutput = (int*)malloc(bytes);//pc results new int[n]
gpuOutput = (int*)malloc(bytes);//gpu results
//initalize
for (long j = 0; j < n; j++) {
cpuOutput[j] = 0;
gpuOutput[j] = 0;
}
clock_t cStart = clock();
double cpuStart = (double) cStart/CLOCKS_PER_SEC;//
///////////////////////////////////////////////////////////////////////////////////
//do it on cpu
//TODO add systime to check how long it takes
cpuOutput[0] = (int)0;
cpuOutput[1] = (int)0;
cpuOutput[2] = (int)1;
for (long i = 2; i < (n/2)+1; i++) {
long num = (i * 2) - 1;
if (i * 2 < n) {
cpuOutput[i * 2] = 0;
}
if (num < n) {
cpuOutput[num] = isPrime(num);
}
}
clock_t cEnd = clock();
double cpuEnd = (double)cEnd/CLOCKS_PER_SEC;
//sum up pc result of # of primes
int sum = 0;
for (int i = 0; i < n; i++) {
sum += (int)cpuOutput[i];
}
printf("CPU final result: %d\n", sum);
double cpuTotal = cpuEnd - cpuStart;
printf("CPU took %lf seconds to find primes numbers up to %ld\n", cpuTotal, n);
////////////////////////////////////////////////////////////////////////
//do it on gpu
//TODO sys clock time for seeing how much time it takes
clock_t gStart = clock();
double gpuStart = (double)gStart / CLOCKS_PER_SEC;;
//Device output vector
int* d_output;
// Allocate memory for each vector on GPU
hipMalloc(&d_output, bytes);
// Copy host vectors to device//i dont think we need to do this
hipMemcpy(d_output, gpuOutput, bytes, hipMemcpyHostToDevice);
int gridSize;
// Number of thread blocks in grid
gridSize = (int)ceil((double)((double)((n+1)/2)/blockSize));
primeFind<<<gridSize, blockSize>>>(d_output, n);
// Copy array back to host
hipMemcpy(gpuOutput, d_output, bytes, hipMemcpyDeviceToHost);
clock_t gEnd = clock();
double gpuEnd = (double)gEnd / CLOCKS_PER_SEC;
// Sum up vector c and print result divided by n, this should equal 1 without error
sum = 0;
for (long i = 2; i < n; i++) {
sum += (int)gpuOutput[i];
}
printf("GPU final result: %d\n", sum);
long double gpuTotal = gpuEnd - gpuStart;
printf("GPU took %Lf seconds to find primes numbers up to %ld\n", gpuTotal, n);
printf("GPU speeds up the process %Lf times.\n", cpuTotal / gpuTotal);
// Release device memory
hipFree(d_output);
// Release host memory
free(cpuOutput);
free(gpuOutput);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9primeFindPil
.globl _Z9primeFindPil
.p2align 8
.type _Z9primeFindPil,@function
_Z9primeFindPil:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v5, 1 :: v_dual_mov_b32 v4, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_lshr_b32 s0, s7, 31
v_mov_b32_e32 v0, 0
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_ashr_i64 s[0:1], s[0:1], 1
v_ashrrev_i32_e32 v2, 31, v1
global_store_b96 v0, v[3:5], s[4:5]
v_cmp_ge_i64_e32 vcc_lo, s[0:1], v[1:2]
v_cmp_lt_i32_e64 s0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v0, 1, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_cmpx_gt_i64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[1:2], v3, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, -1, v0
s_mov_b64 s[2:3], 2
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_gt_i64_e32 vcc_lo, s[6:7], v[0:1]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execnz .LBB0_7
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_add_u32 s2, s2, 1
v_mov_b32_e32 v2, 0
s_addc_u32 s3, s3, 0
s_and_not1_b32 s0, s8, exec_lo
s_and_b32 s6, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s0, s6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s8
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_12
.LBB0_7:
s_mul_i32 s0, s2, s3
s_mul_hi_u32 s6, s2, s2
v_mov_b32_e32 v2, 1
s_add_i32 s6, s6, s0
s_or_b32 s8, s8, exec_lo
s_add_i32 s7, s6, s0
s_mul_i32 s6, s2, s2
s_mov_b32 s9, exec_lo
v_cmpx_le_i64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_6
v_or_b32_e32 v3, s3, v1
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s10, exec_lo, s0
s_cbranch_execz .LBB0_10
s_ashr_i32 s6, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s12, s2, s6
s_mov_b32 s7, s6
s_addc_u32 s13, s3, s6
s_xor_b64 s[6:7], s[12:13], s[6:7]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s6
v_cvt_f32_u32_e32 v3, s7
s_sub_u32 s0, 0, s6
s_subb_u32 s11, 0, s7
v_fmamk_f32 v2, v3, 0x4f800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
v_mul_f32_e32 v3, 0x2f800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v3, v3
v_fmamk_f32 v2, v3, 0xcf800000, v2
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v4, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, s0, v2
v_mul_lo_u32 v6, s11, v2
v_add_nc_u32_e32 v4, v5, v4
v_mul_lo_u32 v5, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v6
v_mul_hi_u32 v6, v2, v5
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v7, v2, v4
v_mul_hi_u32 v8, v2, v4
v_mul_hi_u32 v9, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v10, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_mov_b32_e32 v8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
v_mov_b32_e32 v10, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v4, s0, v2
v_mul_lo_u32 v6, s11, v2
v_mul_lo_u32 v5, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v5
v_mul_lo_u32 v5, s0, v2
v_add_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v2, v5
v_mul_lo_u32 v7, v2, v4
v_mul_hi_u32 v9, v2, v4
v_mul_hi_u32 v11, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v12, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v11, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, v0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, v1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v11, v7, v8
v_add_co_u32 v6, vcc_lo, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, v3, v5, vcc_lo
v_xor_b32_e32 v9, v9, v10
v_mul_hi_u32 v13, v11, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, v11, v12, 0
v_mad_u64_u32 v[4:5], null, v9, v6, 0
v_mad_u64_u32 v[6:7], null, v9, v12, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v13, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, s7, v4
v_mad_u64_u32 v[2:3], null, s6, v4, 0
v_mul_lo_u32 v4, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, vcc_lo, v11, v2
v_add3_u32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v9, v3
v_subrev_co_ci_u32_e64 v4, s0, s7, v4, vcc_lo
v_sub_co_ci_u32_e32 v3, vcc_lo, v9, v3, vcc_lo
v_sub_co_u32 v5, vcc_lo, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v6, s0, 0, v4, vcc_lo
v_cmp_le_u32_e64 s0, s6, v2
v_subrev_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_cndmask_b32_e64 v7, 0, -1, s0
v_cmp_le_u32_e64 s0, s6, v5
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s7, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, 0, -1, s0
v_cmp_le_u32_e64 s0, s7, v6
v_cndmask_b32_e64 v11, 0, -1, s0
v_cmp_eq_u32_e64 s0, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v11, v9, vcc_lo
v_sub_co_u32 v11, vcc_lo, v5, s6
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v9
v_cndmask_b32_e64 v7, v12, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
v_xor_b32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v8
v_sub_co_u32 v2, vcc_lo, v2, v8
s_delay_alu instid0(VALU_DEP_3)
v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v10, vcc_lo
.LBB0_10:
s_and_not1_saveexec_b32 s0, s10
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s6, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s6, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_mov_b32 v3, 0
s_branch .LBB0_5
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9primeFindPil
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9primeFindPil, .Lfunc_end0-_Z9primeFindPil
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9primeFindPil
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9primeFindPil.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include "hip/hip_runtime.h"
__device__ int isPrimeGPU(long x) {
long long i;
for (i = 2; i * i < x + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__host__ int isPrime(long x) {
long i;
for (i = 2; i < sqrt(x) + 1; i++) {
if (x % i == 0) {
return 0;
}
}
return 1;
}
__global__ void primeFind(int* c, long n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
c[0] = (int)0;
c[1] = (int)0;
c[2] = (int)1;
long num = (id * 2)-1;
if (id < ((n/2)+1) && 1 < id) {//global thread 0 and 1 dont do anything need to deal with
if (id * 2 < n) {//even numbers
c[id * 2] = 0;
}
if (num < n) {//odd numbers
c[num] = isPrimeGPU(num);
}
}
}
int main(int argc, const char* argv[]) {
if (argc < 3){
printf("Usage: prime upbound\n");
exit(-1);
}
// Size of vectors
long n = atoi(argv[1]);
printf("n = %ld \n", n);
if(n <= 0){
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
int blockSize = atoi(argv[2]);
printf("block size = %d \n", blockSize);
// Host output
int* cpuOutput;
//Device output vector
int* gpuOutput;
// Size, in bytes, of each output
size_t bytes = (unsigned long long)n * sizeof(int);
// Allocate memory for each vector on host
cpuOutput = (int*)malloc(bytes);//pc results new int[n]
gpuOutput = (int*)malloc(bytes);//gpu results
//initalize
for (long j = 0; j < n; j++) {
cpuOutput[j] = 0;
gpuOutput[j] = 0;
}
clock_t cStart = clock();
double cpuStart = (double) cStart/CLOCKS_PER_SEC;//
///////////////////////////////////////////////////////////////////////////////////
//do it on cpu
//TODO add systime to check how long it takes
cpuOutput[0] = (int)0;
cpuOutput[1] = (int)0;
cpuOutput[2] = (int)1;
for (long i = 2; i < (n/2)+1; i++) {
long num = (i * 2) - 1;
if (i * 2 < n) {
cpuOutput[i * 2] = 0;
}
if (num < n) {
cpuOutput[num] = isPrime(num);
}
}
clock_t cEnd = clock();
double cpuEnd = (double)cEnd/CLOCKS_PER_SEC;
//sum up pc result of # of primes
int sum = 0;
for (int i = 0; i < n; i++) {
sum += (int)cpuOutput[i];
}
printf("CPU final result: %d\n", sum);
double cpuTotal = cpuEnd - cpuStart;
printf("CPU took %lf seconds to find primes numbers up to %ld\n", cpuTotal, n);
////////////////////////////////////////////////////////////////////////
//do it on gpu
//TODO sys clock time for seeing how much time it takes
clock_t gStart = clock();
double gpuStart = (double)gStart / CLOCKS_PER_SEC;;
//Device output vector
int* d_output;
// Allocate memory for each vector on GPU
hipMalloc(&d_output, bytes);
// Copy host vectors to device//i dont think we need to do this
hipMemcpy(d_output, gpuOutput, bytes, hipMemcpyHostToDevice);
int gridSize;
// Number of thread blocks in grid
gridSize = (int)ceil((double)((double)((n+1)/2)/blockSize));
primeFind<<<gridSize, blockSize>>>(d_output, n);
// Copy array back to host
hipMemcpy(gpuOutput, d_output, bytes, hipMemcpyDeviceToHost);
clock_t gEnd = clock();
double gpuEnd = (double)gEnd / CLOCKS_PER_SEC;
// Sum up vector c and print result divided by n, this should equal 1 without error
sum = 0;
for (long i = 2; i < n; i++) {
sum += (int)gpuOutput[i];
}
printf("GPU final result: %d\n", sum);
long double gpuTotal = gpuEnd - gpuStart;
printf("GPU took %Lf seconds to find primes numbers up to %ld\n", gpuTotal, n);
printf("GPU speeds up the process %Lf times.\n", cpuTotal / gpuTotal);
// Release device memory
hipFree(d_output);
// Release host memory
free(cpuOutput);
free(gpuOutput);
return 0;
}
|
.text
.file "lab1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7isPrimel
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0x4000000000000000 # double 2
.text
.globl _Z7isPrimel
.p2align 4, 0x90
.type _Z7isPrimel,@function
_Z7isPrimel: # @_Z7isPrimel
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
cvtsi2sd %rdi, %xmm2
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
jb .LBB0_2
# %bb.1:
xorps %xmm0, %xmm0
sqrtsd %xmm2, %xmm0
jmp .LBB0_3
.LBB0_2: # %call.sqrt
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_3: # %.split
addsd .LCPI0_0(%rip), %xmm0
movl $1, %eax
ucomisd .LCPI0_1(%rip), %xmm0
jbe .LBB0_11
# %bb.4: # %.lr.ph.preheader
movl $2, %r14d
sqrtsd %xmm2, %xmm3
xorpd %xmm4, %xmm4
movsd .LCPI0_0(%rip), %xmm5 # xmm5 = mem[0],zero
movsd %xmm3, 16(%rsp) # 8-byte Spill
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_8: # %.split10
# in Loop: Header=BB0_5 Depth=1
incq %r14
xorps %xmm1, %xmm1
cvtsi2sd %r14, %xmm1
addsd %xmm5, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB0_9
.LBB0_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rax
cqto
idivq %r14
testq %rdx, %rdx
je .LBB0_10
# %bb.6: # in Loop: Header=BB0_5 Depth=1
ucomisd %xmm4, %xmm2
movapd %xmm3, %xmm0
jae .LBB0_8
# %bb.7: # %call.sqrt11
# in Loop: Header=BB0_5 Depth=1
movapd %xmm2, %xmm0
callq sqrt
movsd .LCPI0_0(%rip), %xmm5 # xmm5 = mem[0],zero
xorpd %xmm4, %xmm4
movsd 16(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
jmp .LBB0_8
.LBB0_10:
xorl %eax, %eax
jmp .LBB0_11
.LBB0_9:
movl $1, %eax
.LBB0_11: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7isPrimel, .Lfunc_end0-_Z7isPrimel
.cfi_endproc
# -- End function
.globl _Z24__device_stub__primeFindPil # -- Begin function _Z24__device_stub__primeFindPil
.p2align 4, 0x90
.type _Z24__device_stub__primeFindPil,@function
_Z24__device_stub__primeFindPil: # @_Z24__device_stub__primeFindPil
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9primeFindPil, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__primeFindPil, .Lfunc_end1-_Z24__device_stub__primeFindPil
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.LCPI2_2:
.quad 0x4000000000000000 # double 2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jle .LBB2_30
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r12d, %rbx
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB2_31
# %bb.2:
movq %r12, 56(%rsp) # 8-byte Spill
shlq $32, %r12
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $.L.str.3, %edi
movq %rax, 64(%rsp) # 8-byte Spill
movl %eax, %esi
xorl %eax, %eax
callq printf
sarq $30, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testq %rbx, %rbx
jle .LBB2_4
# %bb.3: # %.lr.ph.preheader
movq %r14, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq %r15, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
.LBB2_4: # %._crit_edge
movq %r12, 72(%rsp) # 8-byte Spill
movq %r15, 80(%rsp) # 8-byte Spill
callq clock
cvtsi2sd %rax, %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq $0, (%r14)
movl $1, 8(%r14)
cmpq $4, %rbx
jae .LBB2_13
.LBB2_5: # %._crit_edge92
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 56(%rsp), %rcx # 8-byte Reload
cmpl $2, %ecx
movl $1, %eax
cmovgel %ecx, %eax
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_6: # %.lr.ph96
# =>This Inner Loop Header: Depth=1
addl (%r14,%rcx,4), %esi
incq %rcx
cmpq %rcx, %rax
jne .LBB2_6
# %bb.7: # %._crit_edge97
xorl %ebp, %ebp
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movb $1, %al
callq printf
callq clock
movq %rax, 24(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movq 72(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 1(%rbx), %rax
shrq %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq 64(%rsp), %r13 # 8-byte Reload
xorps %xmm1, %xmm1
cvtsi2sd %r13d, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r13d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 40(%rsp), %rax
movq %rax, 168(%rsp)
movq %rbx, 160(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rax
movq 112(%rsp), %rdi
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 176(%rsp), %r9
movl $_Z9primeFindPil, %edi
callq hipLaunchKernel
.LBB2_9:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq clock
cmpq $3, %rbx
jl .LBB2_12
# %bb.10: # %.lr.ph101.preheader
xorl %ebp, %ebp
movl $2, %ecx
.p2align 4, 0x90
.LBB2_11: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
addl (%r15,%rcx,4), %ebp
incq %rcx
cmpq %rcx, %rbx
jne .LBB2_11
.LBB2_12: # %._crit_edge102
cvtsi2sd %rax, %xmm2
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm2
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1 # 8-byte Folded Reload
divsd %xmm0, %xmm1
subsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movl $.L.str.6, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 96(%rsp)
fldl 96(%rsp)
fld %st(0)
fstpt 24(%rsp) # 10-byte Folded Spill
fstpt (%rsp)
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp)
fldt 24(%rsp) # 10-byte Folded Reload
fdivrl 104(%rsp)
fstpt (%rsp)
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13: # %.lr.ph91.preheader
.cfi_def_cfa_offset 256
movq %rbx, %rbp
shrq %rbp
movl $2, %r12d
xorpd %xmm2, %xmm2
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
movq %r14, 88(%rsp) # 8-byte Spill
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_17 Depth=1
movl $1, %ecx
.LBB2_15: # %_Z7isPrimel.exit
# in Loop: Header=BB2_17 Depth=1
movq 88(%rsp), %r14 # 8-byte Reload
movl %ecx, -4(%r14,%r15,4)
.LBB2_16: # in Loop: Header=BB2_17 Depth=1
leaq 1(%r12), %rax
cmpq %rbp, %r12
movq %rax, %r12
je .LBB2_5
.LBB2_17: # %.lr.ph91
# =>This Loop Header: Depth=1
# Child Loop BB2_26 Depth 2
leaq (%r12,%r12), %r15
cmpq %rbx, %r15
jge .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movl $0, (%r14,%r15,4)
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
cmpq %rbx, %r15
jg .LBB2_16
# %bb.20: # in Loop: Header=BB2_17 Depth=1
leaq -1(,%r12,2), %r13
xorps %xmm4, %xmm4
cvtsi2sd %r13, %xmm4
ucomisd %xmm2, %xmm4
movsd %xmm4, 16(%rsp) # 8-byte Spill
jb .LBB2_22
# %bb.21: # in Loop: Header=BB2_17 Depth=1
xorps %xmm0, %xmm0
sqrtsd %xmm4, %xmm0
jmp .LBB2_23
.p2align 4, 0x90
.LBB2_22: # %call.sqrt
# in Loop: Header=BB2_17 Depth=1
movapd %xmm4, %xmm0
callq sqrt
movsd 16(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
xorpd %xmm2, %xmm2
.LBB2_23: # %.split
# in Loop: Header=BB2_17 Depth=1
addsd %xmm3, %xmm0
ucomisd .LCPI2_2(%rip), %xmm0
jbe .LBB2_14
# %bb.24: # %.lr.ph.i.preheader
# in Loop: Header=BB2_17 Depth=1
movl $2, %r14d
xorps %xmm5, %xmm5
sqrtsd %xmm4, %xmm5
movsd %xmm5, 24(%rsp) # 8-byte Spill
jmp .LBB2_26
.p2align 4, 0x90
.LBB2_25: # %.split112
# in Loop: Header=BB2_26 Depth=2
incq %r14
xorps %xmm1, %xmm1
cvtsi2sd %r14, %xmm1
addsd %xmm3, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB2_14
.LBB2_26: # %.lr.ph.i
# Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
xorl %ecx, %ecx
movq %r13, %rax
xorl %edx, %edx
divq %r14
testq %rdx, %rdx
je .LBB2_15
# %bb.27: # in Loop: Header=BB2_26 Depth=2
ucomisd %xmm2, %xmm4
movapd %xmm5, %xmm0
jae .LBB2_25
# %bb.28: # %call.sqrt113
# in Loop: Header=BB2_26 Depth=2
movapd %xmm4, %xmm0
callq sqrt
movsd 24(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
movsd 16(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
xorpd %xmm2, %xmm2
jmp .LBB2_25
.LBB2_30:
movl $.Lstr.1, %edi
jmp .LBB2_32
.LBB2_31:
movl $.Lstr, %edi
.LBB2_32:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9primeFindPil, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9primeFindPil,@object # @_Z9primeFindPil
.section .rodata,"a",@progbits
.globl _Z9primeFindPil
.p2align 3, 0x0
_Z9primeFindPil:
.quad _Z24__device_stub__primeFindPil
.size _Z9primeFindPil, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "n = %ld \n"
.size .L.str.1, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "block size = %d \n"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU final result: %d\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU took %lf seconds to find primes numbers up to %ld\n"
.size .L.str.5, 55
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU final result: %d\n"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU took %Lf seconds to find primes numbers up to %ld\n"
.size .L.str.7, 55
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU speeds up the process %Lf times.\n"
.size .L.str.8, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9primeFindPil"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: prime upbound, you input invalid upbound number!"
.size .Lstr, 56
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: prime upbound"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__primeFindPil
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9primeFindPil
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9primeFindPil
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0040*/ ULEA.HI UR4, UP0, UR5, UR4, URZ, 0x1 ; /* 0x0000000405047291 */
/* 0x000fe2000f81083f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0070*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc800087fe43f */
/*0080*/ USHF.R.S64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe40008001005 */
/*0090*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe20008011405 */
/*00a0*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*00b0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*00c0*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe40000011404 */
/*00d0*/ ISETP.LE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe2000bf03070 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ ISETP.GE.AND.EX P0, PT, R3, R0, PT, P0 ; /* 0x000000000300720c */
/* 0x000fe20003f06300 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.LT.OR P0, PT, R4, 0x2, !P0 ; /* 0x000000020400780c */
/* 0x000fe40004701670 */
/*0120*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x0001e8000c101904 */
/*0130*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101904 */
/*0140*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x0001e6000c101904 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.SHL.U32 R2, R4, 0x2, RZ ; /* 0x0000000204027824 */
/* 0x001fca00078e00ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe40003f06070 */
/*0180*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0190*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fe40003f06300 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f26070 */
/*01c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*01d0*/ ISETP.GE.AND.EX P1, PT, R5, c[0x0][0x16c], PT, P1 ; /* 0x00005b0005007a0c */
/* 0x000fca0003f26310 */
/*01e0*/ @!P0 LEA R6, P2, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002068a11 */
/* 0x000fc800078410ff */
/*01f0*/ @!P0 LEA.HI.X R7, R2, c[0x0][0x164], R3, 0x2, P2 ; /* 0x0000590002078a11 */
/* 0x000fca00010f1403 */
/*0200*/ @!P0 STG.E [R6.64], RZ ; /* 0x000000ff06008986 */
/* 0x0001e2000c101904 */
/*0210*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0220*/ ISETP.GE.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06270 */
/*0230*/ BSSY B0, 0x530 ; /* 0x000002f000007945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x001fd600078e00ff */
/*0250*/ @!P0 BRA 0x520 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fca00078e00ff */
/*0280*/ LOP3.LUT R2, R5, R6, RZ, 0xfc, !PT ; /* 0x0000000605027212 */
/* 0x000fe200078efcff */
/*0290*/ BSSY B1, 0x450 ; /* 0x000001b000017945 */
/* 0x000fe60003800000 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05070 */
/*02b0*/ @!P0 BRA 0x310 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02c0*/ MOV R4, 0x2e0 ; /* 0x000002e000047802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x570 ; /* 0x0000029000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*02f0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f05300 */
/*0300*/ BRA 0x440 ; /* 0x0000013000007947 */
/* 0x000fee0003800000 */
/*0310*/ I2F.U32.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209000 */
/*0320*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f25070 */
/*0330*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0340*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0350*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0370*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a03 */
/*0380*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fc800078e02ff */
/*0390*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*03a0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*03b0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*03c0*/ IMAD R8, R7, R3, R0 ; /* 0x0000000307087224 */
/* 0x000fca00078e0200 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06070 */
/*03e0*/ @P0 IMAD.IADD R8, R8, 0x1, -R7 ; /* 0x0000000108080824 */
/* 0x000fca00078e0a07 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f06070 */
/*0400*/ @P0 IMAD.IADD R8, R8, 0x1, -R7 ; /* 0x0000000108080824 */
/* 0x000fe200078e0a07 */
/*0410*/ @!P1 LOP3.LUT R8, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff089212 */
/* 0x000fc800078e33ff */
/*0420*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0430*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd00003f05300 */
/*0440*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R2, P1, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe20007f3e0ff */
/*0460*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0470*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0480*/ @!P0 BRA 0x520 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0002 */
/*04a0*/ IMAD R4, R6, R7.reuse, RZ ; /* 0x0000000706047224 */
/* 0x080fe400078e02ff */
/*04b0*/ IMAD.WIDE.U32 R2, R7, R7, RZ ; /* 0x0000000707027225 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD R9, R7, R6, R4 ; /* 0x0000000607097224 */
/* 0x000fe200078e0204 */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R2, R0, PT ; /* 0x000000000200720c */
/* 0x000fc80003f04070 */
/*04e0*/ IADD3 R2, R3, R9, RZ ; /* 0x0000000903027210 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GT.AND.EX P0, PT, R2, R5, PT, P0 ; /* 0x000000050200720c */
/* 0x000fda0003f04300 */
/*0500*/ @!P0 BRA 0x280 ; /* 0xfffffd7000008947 */
/* 0x000fea000383ffff */
/*0510*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*0540*/ LEA.HI.X R3, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1405 */
/*0550*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ IADD3 R2, P1, RZ, -R7, RZ ; /* 0x80000007ff027210 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f06270 */
/*0590*/ IMAD.X R3, RZ, RZ, ~R6, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0e06 */
/*05a0*/ SEL R2, R2, R7, !P0 ; /* 0x0000000702027207 */
/* 0x000fc80004000000 */
/*05b0*/ SEL R3, R3, R6, !P0 ; /* 0x0000000603037207 */
/* 0x000fc80004000000 */
/*05c0*/ I2F.U64.RP R12, R2 ; /* 0x00000002000c7312 */
/* 0x000e300000309000 */
/*05d0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*05e0*/ IADD3 R8, R12, 0x1ffffffe, RZ ; /* 0x1ffffffe0c087810 */
/* 0x001fcc0007ffe0ff */
/*05f0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*0600*/ IMAD.WIDE.U32 R10, R8, R2, RZ ; /* 0x00000002080a7225 */
/* 0x001fc800078e00ff */
/*0610*/ IMAD R11, R8, R3, R11 ; /* 0x00000003080b7224 */
/* 0x000fe200078e020b */
/*0620*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fc60007f1e0ff */
/*0630*/ IMAD R11, R9, R2, R11 ; /* 0x00000002090b7224 */
/* 0x000fe400078e020b */
/*0640*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc800078e00ff */
/*0650*/ IMAD.X R15, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0e0b */
/*0660*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0670*/ IMAD R17, R9, R15.reuse, RZ ; /* 0x0000000f09117224 */
/* 0x080fe400078e02ff */
/*0680*/ IMAD.WIDE.U32 R10, P0, R8, R15, R10 ; /* 0x0000000f080a7225 */
/* 0x000fc8000780000a */
/*0690*/ IMAD.HI.U32 R15, R9, R15, RZ ; /* 0x0000000f090f7227 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fca000782000a */
/*06b0*/ IADD3 R11, P2, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x000fe20007f5e0ff */
/*06c0*/ IMAD.X R10, R15, 0x1, R9, P0 ; /* 0x000000010f0a7824 */
/* 0x000fc800000e0609 */
/*06d0*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fe200078e00ff */
/*06e0*/ IADD3.X R13, RZ, RZ, R10, P2, P1 ; /* 0x000000ffff0d7210 */
/* 0x000fe400017e240a */
/*06f0*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f26270 */
/*0700*/ IMAD R9, R11, R3, R9 ; /* 0x000000030b097224 */
/* 0x000fe200078e0209 */
/*0710*/ IADD3 R15, P0, RZ, -R8, RZ ; /* 0x80000008ff0f7210 */
/* 0x000fc60007f1e0ff */
/*0720*/ IMAD R9, R13, R2, R9 ; /* 0x000000020d097224 */
/* 0x000fe400078e0209 */
/*0730*/ IMAD.HI.U32 R10, R11, R15, RZ ; /* 0x0000000f0b0a7227 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.X R8, RZ, RZ, ~R9, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e09 */
/*0750*/ IADD3 R9, P4, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fc60007f9e0ff */
/*0760*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fc8000780000a */
/*0770*/ IMAD.X R12, RZ, RZ, ~R5, P4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400020e0e05 */
/*0780*/ IMAD.HI.U32 R10, P2, R13, R15, R10 ; /* 0x0000000f0d0a7227 */
/* 0x000fe2000784000a */
/*0790*/ SEL R11, R9, R0, !P1 ; /* 0x00000000090b7207 */
/* 0x000fe40004800000 */
/*07a0*/ SEL R12, R12, R5, !P1 ; /* 0x000000050c0c7207 */
/* 0x000fe20004800000 */
/*07b0*/ IMAD R15, R13.reuse, R8.reuse, RZ ; /* 0x000000080d0f7224 */
/* 0x0c0fe400078e02ff */
/*07c0*/ IMAD.HI.U32 R8, R13, R8, RZ ; /* 0x000000080d087227 */
/* 0x000fc600078e00ff */
/*07d0*/ IADD3 R10, P3, R15, R10, RZ ; /* 0x0000000a0f0a7210 */
/* 0x000fe20007f7e0ff */
/*07e0*/ IMAD.X R13, R8, 0x1, R13, P0 ; /* 0x00000001080d7824 */
/* 0x000fe400000e060d */
/*07f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0800*/ IMAD.HI.U32 R8, R10, R11, RZ ; /* 0x0000000b0a087227 */
/* 0x000fe200078e00ff */
/*0810*/ IADD3.X R13, RZ, RZ, R13, P3, P2 ; /* 0x000000ffff0d7210 */
/* 0x000fca0001fe440d */
/*0820*/ IMAD.WIDE.U32 R8, R10, R12, R8 ; /* 0x0000000c0a087225 */
/* 0x000fc800078e0008 */
/*0830*/ IMAD R15, R13.reuse, R12, RZ ; /* 0x0000000c0d0f7224 */
/* 0x040fe400078e02ff */
/*0840*/ IMAD.HI.U32 R8, P0, R13, R11, R8 ; /* 0x0000000b0d087227 */
/* 0x000fc80007800008 */
/*0850*/ IMAD.HI.U32 R10, R13, R12, RZ ; /* 0x0000000c0d0a7227 */
/* 0x000fe200078e00ff */
/*0860*/ IADD3 R13, P2, R15, R8, RZ ; /* 0x000000080f0d7210 */
/* 0x000fc80007f5e0ff */
/*0870*/ IADD3.X R10, R10, RZ, RZ, P0, !PT ; /* 0x000000ff0a0a7210 */
/* 0x000fe200007fe4ff */
/*0880*/ IMAD.WIDE.U32 R8, R13, R2, RZ ; /* 0x000000020d087225 */
/* 0x000fc800078e00ff */
/*0890*/ IMAD.X R15, RZ, RZ, R10, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060a */
/*08a0*/ IMAD R13, R13, R3, R9 ; /* 0x000000030d0d7224 */
/* 0x000fe200078e0209 */
/*08b0*/ IADD3 R9, P2, -R8, R11, RZ ; /* 0x0000000b08097210 */
/* 0x000fc60007f5e1ff */
/*08c0*/ IMAD R13, R15, R2.reuse, R13 ; /* 0x000000020f0d7224 */
/* 0x080fe200078e020d */
/*08d0*/ ISETP.GE.U32.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fc60003f06070 */
/*08e0*/ IMAD.X R15, R12, 0x1, ~R13, P2 ; /* 0x000000010c0f7824 */
/* 0x000fe200010e0e0d */
/*08f0*/ IADD3 R11, P2, R9, -R2, RZ ; /* 0x80000002090b7210 */
/* 0x000fc80007f5e0ff */
/*0900*/ ISETP.GE.U32.AND.EX P0, PT, R15.reuse, R3, PT, P0 ; /* 0x000000030f00720c */
/* 0x040fe20003f06100 */
/*0910*/ IMAD.X R13, R15, 0x1, ~R3, P2 ; /* 0x000000010f0d7824 */
/* 0x000fc600010e0e03 */
/*0920*/ SEL R11, R11, R9, P0 ; /* 0x000000090b0b7207 */
/* 0x000fe40000000000 */
/*0930*/ SEL R13, R13, R15, P0 ; /* 0x0000000f0d0d7207 */
/* 0x000fe40000000000 */
/*0940*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R2.reuse, PT ; /* 0x000000020b00720c */
/* 0x0c0fe40003f06070 */
/*0950*/ IADD3 R8, P2, R11, -R2, RZ ; /* 0x800000020b087210 */
/* 0x000fe40007f5e0ff */
/*0960*/ ISETP.GE.U32.AND.EX P0, PT, R13, R3, PT, P0 ; /* 0x000000030d00720c */
/* 0x000fc60003f06100 */
/*0970*/ IMAD.X R9, R13, 0x1, ~R3, P2 ; /* 0x000000010d097824 */
/* 0x000fe200010e0e03 */
/*0980*/ SEL R8, R8, R11, P0 ; /* 0x0000000b08087207 */
/* 0x000fc80000000000 */
/*0990*/ SEL R9, R9, R13, P0 ; /* 0x0000000d09097207 */
/* 0x000fe40000000000 */
/*09a0*/ IADD3 R3, P2, RZ, -R8.reuse, RZ ; /* 0x80000008ff037210 */
/* 0x080fe40007f5e0ff */
/*09b0*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05070 */
/*09c0*/ SEL R8, R3, R8, !P1 ; /* 0x0000000803087207 */
/* 0x000fe20004800000 */
/*09d0*/ IMAD.X R2, RZ, RZ, ~R9, P2 ; /* 0x000000ffff027224 */
/* 0x000fe200010e0e09 */
/*09e0*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fe20003f05300 */
/*09f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc600078e00ff */
/*0a00*/ SEL R9, R2, R9, !P1 ; /* 0x0000000902097207 */
/* 0x000fe20004800000 */
/*0a10*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0a20*/ SEL R8, R8, 0xffffffff, P0 ; /* 0xffffffff08087807 */
/* 0x000fe40000000000 */
/*0a30*/ SEL R9, R9, 0xffffffff, P0 ; /* 0xffffffff09097807 */
/* 0x000fe20000000000 */
/*0a40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff5b002007950 */
/* 0x000fec0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9primeFindPil
.globl _Z9primeFindPil
.p2align 8
.type _Z9primeFindPil,@function
_Z9primeFindPil:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v5, 1 :: v_dual_mov_b32 v4, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_lshr_b32 s0, s7, 31
v_mov_b32_e32 v0, 0
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_ashr_i64 s[0:1], s[0:1], 1
v_ashrrev_i32_e32 v2, 31, v1
global_store_b96 v0, v[3:5], s[4:5]
v_cmp_ge_i64_e32 vcc_lo, s[0:1], v[1:2]
v_cmp_lt_i32_e64 s0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v0, 1, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_cmpx_gt_i64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[1:2], v3, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, -1, v0
s_mov_b64 s[2:3], 2
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_gt_i64_e32 vcc_lo, s[6:7], v[0:1]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execnz .LBB0_7
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_add_u32 s2, s2, 1
v_mov_b32_e32 v2, 0
s_addc_u32 s3, s3, 0
s_and_not1_b32 s0, s8, exec_lo
s_and_b32 s6, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s0, s6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s8
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_12
.LBB0_7:
s_mul_i32 s0, s2, s3
s_mul_hi_u32 s6, s2, s2
v_mov_b32_e32 v2, 1
s_add_i32 s6, s6, s0
s_or_b32 s8, s8, exec_lo
s_add_i32 s7, s6, s0
s_mul_i32 s6, s2, s2
s_mov_b32 s9, exec_lo
v_cmpx_le_i64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_6
v_or_b32_e32 v3, s3, v1
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s10, exec_lo, s0
s_cbranch_execz .LBB0_10
s_ashr_i32 s6, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s12, s2, s6
s_mov_b32 s7, s6
s_addc_u32 s13, s3, s6
s_xor_b64 s[6:7], s[12:13], s[6:7]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s6
v_cvt_f32_u32_e32 v3, s7
s_sub_u32 s0, 0, s6
s_subb_u32 s11, 0, s7
v_fmamk_f32 v2, v3, 0x4f800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
v_mul_f32_e32 v3, 0x2f800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v3, v3
v_fmamk_f32 v2, v3, 0xcf800000, v2
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v4, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, s0, v2
v_mul_lo_u32 v6, s11, v2
v_add_nc_u32_e32 v4, v5, v4
v_mul_lo_u32 v5, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v6
v_mul_hi_u32 v6, v2, v5
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v7, v2, v4
v_mul_hi_u32 v8, v2, v4
v_mul_hi_u32 v9, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v10, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_mov_b32_e32 v8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
v_mov_b32_e32 v10, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v4, s0, v2
v_mul_lo_u32 v6, s11, v2
v_mul_lo_u32 v5, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v5
v_mul_lo_u32 v5, s0, v2
v_add_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v2, v5
v_mul_lo_u32 v7, v2, v4
v_mul_hi_u32 v9, v2, v4
v_mul_hi_u32 v11, v3, v5
v_mul_lo_u32 v5, v3, v5
v_mul_hi_u32 v12, v3, v4
v_mul_lo_u32 v4, v3, v4
v_add_co_u32 v6, vcc_lo, v6, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v11, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, v0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, v1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v11, v7, v8
v_add_co_u32 v6, vcc_lo, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, v3, v5, vcc_lo
v_xor_b32_e32 v9, v9, v10
v_mul_hi_u32 v13, v11, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, v11, v12, 0
v_mad_u64_u32 v[4:5], null, v9, v6, 0
v_mad_u64_u32 v[6:7], null, v9, v12, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v13, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, s7, v4
v_mad_u64_u32 v[2:3], null, s6, v4, 0
v_mul_lo_u32 v4, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, vcc_lo, v11, v2
v_add3_u32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v9, v3
v_subrev_co_ci_u32_e64 v4, s0, s7, v4, vcc_lo
v_sub_co_ci_u32_e32 v3, vcc_lo, v9, v3, vcc_lo
v_sub_co_u32 v5, vcc_lo, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v6, s0, 0, v4, vcc_lo
v_cmp_le_u32_e64 s0, s6, v2
v_subrev_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_cndmask_b32_e64 v7, 0, -1, s0
v_cmp_le_u32_e64 s0, s6, v5
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s7, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, 0, -1, s0
v_cmp_le_u32_e64 s0, s7, v6
v_cndmask_b32_e64 v11, 0, -1, s0
v_cmp_eq_u32_e64 s0, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v11, v9, vcc_lo
v_sub_co_u32 v11, vcc_lo, v5, s6
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v9
v_cndmask_b32_e64 v7, v12, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
v_xor_b32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v8
v_sub_co_u32 v2, vcc_lo, v2, v8
s_delay_alu instid0(VALU_DEP_3)
v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v10, vcc_lo
.LBB0_10:
s_and_not1_saveexec_b32 s0, s10
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s6, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s6, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_mov_b32 v3, 0
s_branch .LBB0_5
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9primeFindPil
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9primeFindPil, .Lfunc_end0-_Z9primeFindPil
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9primeFindPil
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9primeFindPil.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000b0faf_00000000-6_lab1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10isPrimeGPUl
.type _Z10isPrimeGPUl, @function
_Z10isPrimeGPUl:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10isPrimeGPUl, .-_Z10isPrimeGPUl
.globl _Z7isPrimel
.type _Z7isPrimel, @function
_Z7isPrimel:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl $2, %ebx
jmp .L6
.L17:
addq $1, %rbx
.L6:
pxor %xmm2, %xmm2
cvtsi2sdq %rbx, %xmm2
movsd %xmm2, 8(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L14
sqrtsd %xmm0, %xmm0
.L10:
addsd .LC1(%rip), %xmm0
comisd 8(%rsp), %xmm0
jbe .L16
movq %rbp, %rax
cqto
idivq %rbx
testq %rdx, %rdx
jne .L17
movl $0, %eax
jmp .L5
.L14:
call sqrt@PLT
jmp .L10
.L16:
movl $1, %eax
.L5:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7isPrimel, .-_Z7isPrimel
.globl _Z29__device_stub__Z9primeFindPilPil
.type _Z29__device_stub__Z9primeFindPilPil, @function
_Z29__device_stub__Z9primeFindPilPil:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9primeFindPil(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z9primeFindPilPil, .-_Z29__device_stub__Z9primeFindPilPil
.globl _Z9primeFindPil
.type _Z9primeFindPil, @function
_Z9primeFindPil:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9primeFindPilPil
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9primeFindPil, .-_Z9primeFindPil
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Usage: prime upbound\n"
.LC3:
.string "n = %ld \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Usage: prime upbound, you input invalid upbound number!\n"
.section .rodata.str1.1
.LC5:
.string "block size = %d \n"
.LC7:
.string "CPU final result: %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "CPU took %lf seconds to find primes numbers up to %ld\n"
.section .rodata.str1.1
.LC11:
.string "GPU final result: %d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "GPU took %Lf seconds to find primes numbers up to %ld\n"
.align 8
.LC13:
.string "GPU speeds up the process %Lf times.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jle .L46
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movslq %eax, %rbp
movq %rbp, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbp, %rbp
jle .L47
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 24(%rsp), %rax
leaq 0(,%rax,4), %rbx
movq %rbx, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movl $0, %ebx
.L29:
movl $0, 0(%r13,%rbx,4)
movl $0, (%r14,%rbx,4)
movq %rbx, (%rsp)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L29
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movsd %xmm0, 40(%rsp)
movl $0, 0(%r13)
movl $0, 4(%r13)
movl $1, 8(%r13)
movq %rbx, %r15
shrq $63, %r15
addq %rbx, %r15
sarq %r15
cmpq $3, %rbx
jle .L30
movl $3, %r12d
movl $2, %ebp
jmp .L33
.L46:
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L47:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
cmpq %rbx, %rdi
jl .L48
.L32:
addq $1, %rbp
addq $2, %r12
cmpq %r15, %rbp
jg .L30
.L33:
movq %r12, %rdi
leaq (%rbp,%rbp), %rax
cmpq %rax, %rbx
jle .L31
movl $0, 0(%r13,%rbp,8)
jmp .L31
.L48:
call _Z7isPrimel
movl %eax, 0(%r13,%r12,4)
jmp .L32
.L30:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movq %xmm0, %rbp
movq %r13, %rax
movq 24(%rsp), %rsi
leal -1(%rsi), %edx
leaq 4(%r13,%rdx,4), %rsi
movl $0, %ecx
.L34:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L34
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %xmm5
subsd 40(%rsp), %xmm5
movsd %xmm5, 24(%rsp)
movq %rbx, %rdx
movapd %xmm5, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movsd %xmm0, 40(%rsp)
leaq 56(%rsp), %rdi
movq 16(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rax
addq $2, %rax
movq %rax, %rdx
shrq $63, %rdx
addq %rdx, %rax
sarq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 32(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC14(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC9(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L35
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC1(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L35:
movl 32(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
cvttsd2sil %xmm3, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L36:
movl $2, %ecx
movq 16(%rsp), %r15
movq %r15, %rdx
movq 56(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
movq %xmm0, %rbp
cmpq $2, %rbx
jle .L40
leaq 8(%r14), %rax
movq %r15, %rcx
addq %r14, %rcx
movl $0, %edx
.L38:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L38
.L37:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %xmm6
subsd 40(%rsp), %xmm6
movsd %xmm6, (%rsp)
fldl (%rsp)
fld %st(0)
fstpt (%rsp)
leaq -16(%rsp), %rsp
.cfi_def_cfa_offset 176
fstpt (%rsp)
movq %rbx, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
fldt 16(%rsp)
fdivrl 40(%rsp)
fstpt (%rsp)
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq %rbx, %rsi
movq 56(%rsp), %rdi
call _Z29__device_stub__Z9primeFindPilPil
jmp .L36
.L40:
movl $0, %edx
jmp .L37
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z9primeFindPil"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z9primeFindPil(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC6:
.long 0
.long 1093567616
.align 8
.LC9:
.long 0
.long 1127219200
.align 8
.LC14:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "lab1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7isPrimel
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0x4000000000000000 # double 2
.text
.globl _Z7isPrimel
.p2align 4, 0x90
.type _Z7isPrimel,@function
_Z7isPrimel: # @_Z7isPrimel
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
cvtsi2sd %rdi, %xmm2
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
jb .LBB0_2
# %bb.1:
xorps %xmm0, %xmm0
sqrtsd %xmm2, %xmm0
jmp .LBB0_3
.LBB0_2: # %call.sqrt
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_3: # %.split
addsd .LCPI0_0(%rip), %xmm0
movl $1, %eax
ucomisd .LCPI0_1(%rip), %xmm0
jbe .LBB0_11
# %bb.4: # %.lr.ph.preheader
movl $2, %r14d
sqrtsd %xmm2, %xmm3
xorpd %xmm4, %xmm4
movsd .LCPI0_0(%rip), %xmm5 # xmm5 = mem[0],zero
movsd %xmm3, 16(%rsp) # 8-byte Spill
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_8: # %.split10
# in Loop: Header=BB0_5 Depth=1
incq %r14
xorps %xmm1, %xmm1
cvtsi2sd %r14, %xmm1
addsd %xmm5, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB0_9
.LBB0_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rax
cqto
idivq %r14
testq %rdx, %rdx
je .LBB0_10
# %bb.6: # in Loop: Header=BB0_5 Depth=1
ucomisd %xmm4, %xmm2
movapd %xmm3, %xmm0
jae .LBB0_8
# %bb.7: # %call.sqrt11
# in Loop: Header=BB0_5 Depth=1
movapd %xmm2, %xmm0
callq sqrt
movsd .LCPI0_0(%rip), %xmm5 # xmm5 = mem[0],zero
xorpd %xmm4, %xmm4
movsd 16(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
jmp .LBB0_8
.LBB0_10:
xorl %eax, %eax
jmp .LBB0_11
.LBB0_9:
movl $1, %eax
.LBB0_11: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7isPrimel, .Lfunc_end0-_Z7isPrimel
.cfi_endproc
# -- End function
.globl _Z24__device_stub__primeFindPil # -- Begin function _Z24__device_stub__primeFindPil
.p2align 4, 0x90
.type _Z24__device_stub__primeFindPil,@function
_Z24__device_stub__primeFindPil: # @_Z24__device_stub__primeFindPil
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9primeFindPil, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__primeFindPil, .Lfunc_end1-_Z24__device_stub__primeFindPil
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.LCPI2_2:
.quad 0x4000000000000000 # double 2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jle .LBB2_30
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r12d, %rbx
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB2_31
# %bb.2:
movq %r12, 56(%rsp) # 8-byte Spill
shlq $32, %r12
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $.L.str.3, %edi
movq %rax, 64(%rsp) # 8-byte Spill
movl %eax, %esi
xorl %eax, %eax
callq printf
sarq $30, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testq %rbx, %rbx
jle .LBB2_4
# %bb.3: # %.lr.ph.preheader
movq %r14, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq %r15, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
.LBB2_4: # %._crit_edge
movq %r12, 72(%rsp) # 8-byte Spill
movq %r15, 80(%rsp) # 8-byte Spill
callq clock
cvtsi2sd %rax, %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq $0, (%r14)
movl $1, 8(%r14)
cmpq $4, %rbx
jae .LBB2_13
.LBB2_5: # %._crit_edge92
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 56(%rsp), %rcx # 8-byte Reload
cmpl $2, %ecx
movl $1, %eax
cmovgel %ecx, %eax
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_6: # %.lr.ph96
# =>This Inner Loop Header: Depth=1
addl (%r14,%rcx,4), %esi
incq %rcx
cmpq %rcx, %rax
jne .LBB2_6
# %bb.7: # %._crit_edge97
xorl %ebp, %ebp
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movb $1, %al
callq printf
callq clock
movq %rax, 24(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movq 72(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 1(%rbx), %rax
shrq %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq 64(%rsp), %r13 # 8-byte Reload
xorps %xmm1, %xmm1
cvtsi2sd %r13d, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r13d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 40(%rsp), %rax
movq %rax, 168(%rsp)
movq %rbx, 160(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rax
movq 112(%rsp), %rdi
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 176(%rsp), %r9
movl $_Z9primeFindPil, %edi
callq hipLaunchKernel
.LBB2_9:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq clock
cmpq $3, %rbx
jl .LBB2_12
# %bb.10: # %.lr.ph101.preheader
xorl %ebp, %ebp
movl $2, %ecx
.p2align 4, 0x90
.LBB2_11: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
addl (%r15,%rcx,4), %ebp
incq %rcx
cmpq %rcx, %rbx
jne .LBB2_11
.LBB2_12: # %._crit_edge102
cvtsi2sd %rax, %xmm2
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm2
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1 # 8-byte Folded Reload
divsd %xmm0, %xmm1
subsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movl $.L.str.6, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 96(%rsp)
fldl 96(%rsp)
fld %st(0)
fstpt 24(%rsp) # 10-byte Folded Spill
fstpt (%rsp)
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp)
fldt 24(%rsp) # 10-byte Folded Reload
fdivrl 104(%rsp)
fstpt (%rsp)
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13: # %.lr.ph91.preheader
.cfi_def_cfa_offset 256
movq %rbx, %rbp
shrq %rbp
movl $2, %r12d
xorpd %xmm2, %xmm2
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
movq %r14, 88(%rsp) # 8-byte Spill
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_17 Depth=1
movl $1, %ecx
.LBB2_15: # %_Z7isPrimel.exit
# in Loop: Header=BB2_17 Depth=1
movq 88(%rsp), %r14 # 8-byte Reload
movl %ecx, -4(%r14,%r15,4)
.LBB2_16: # in Loop: Header=BB2_17 Depth=1
leaq 1(%r12), %rax
cmpq %rbp, %r12
movq %rax, %r12
je .LBB2_5
.LBB2_17: # %.lr.ph91
# =>This Loop Header: Depth=1
# Child Loop BB2_26 Depth 2
leaq (%r12,%r12), %r15
cmpq %rbx, %r15
jge .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movl $0, (%r14,%r15,4)
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
cmpq %rbx, %r15
jg .LBB2_16
# %bb.20: # in Loop: Header=BB2_17 Depth=1
leaq -1(,%r12,2), %r13
xorps %xmm4, %xmm4
cvtsi2sd %r13, %xmm4
ucomisd %xmm2, %xmm4
movsd %xmm4, 16(%rsp) # 8-byte Spill
jb .LBB2_22
# %bb.21: # in Loop: Header=BB2_17 Depth=1
xorps %xmm0, %xmm0
sqrtsd %xmm4, %xmm0
jmp .LBB2_23
.p2align 4, 0x90
.LBB2_22: # %call.sqrt
# in Loop: Header=BB2_17 Depth=1
movapd %xmm4, %xmm0
callq sqrt
movsd 16(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
xorpd %xmm2, %xmm2
.LBB2_23: # %.split
# in Loop: Header=BB2_17 Depth=1
addsd %xmm3, %xmm0
ucomisd .LCPI2_2(%rip), %xmm0
jbe .LBB2_14
# %bb.24: # %.lr.ph.i.preheader
# in Loop: Header=BB2_17 Depth=1
movl $2, %r14d
xorps %xmm5, %xmm5
sqrtsd %xmm4, %xmm5
movsd %xmm5, 24(%rsp) # 8-byte Spill
jmp .LBB2_26
.p2align 4, 0x90
.LBB2_25: # %.split112
# in Loop: Header=BB2_26 Depth=2
incq %r14
xorps %xmm1, %xmm1
cvtsi2sd %r14, %xmm1
addsd %xmm3, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB2_14
.LBB2_26: # %.lr.ph.i
# Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
xorl %ecx, %ecx
movq %r13, %rax
xorl %edx, %edx
divq %r14
testq %rdx, %rdx
je .LBB2_15
# %bb.27: # in Loop: Header=BB2_26 Depth=2
ucomisd %xmm2, %xmm4
movapd %xmm5, %xmm0
jae .LBB2_25
# %bb.28: # %call.sqrt113
# in Loop: Header=BB2_26 Depth=2
movapd %xmm4, %xmm0
callq sqrt
movsd 24(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
movsd 16(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
xorpd %xmm2, %xmm2
jmp .LBB2_25
.LBB2_30:
movl $.Lstr.1, %edi
jmp .LBB2_32
.LBB2_31:
movl $.Lstr, %edi
.LBB2_32:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9primeFindPil, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9primeFindPil,@object # @_Z9primeFindPil
.section .rodata,"a",@progbits
.globl _Z9primeFindPil
.p2align 3, 0x0
_Z9primeFindPil:
.quad _Z24__device_stub__primeFindPil
.size _Z9primeFindPil, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "n = %ld \n"
.size .L.str.1, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "block size = %d \n"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU final result: %d\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU took %lf seconds to find primes numbers up to %ld\n"
.size .L.str.5, 55
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU final result: %d\n"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU took %Lf seconds to find primes numbers up to %ld\n"
.size .L.str.7, 55
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU speeds up the process %Lf times.\n"
.size .L.str.8, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9primeFindPil"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: prime upbound, you input invalid upbound number!"
.size .Lstr, 56
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: prime upbound"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__primeFindPil
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9primeFindPil
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<stdio.h>
// nvcc separate source code into device and host components
__global__ void mykernel(void) {
// Device code is compiled by Nvidia compiler
// This function is called from host code
}
int main(void) {
// Host code goes here which is processed by standard host compiler
// e.g. gcc
// <<< >>> marks a call from host code to device code
// a.k.a. kernal launch, return to the parameters (1,1)
mykernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
}
|
code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<stdio.h>
// nvcc separate source code into device and host components
__global__ void mykernel(void) {
// Device code is compiled by Nvidia compiler
// This function is called from host code
}
int main(void) {
// Host code goes here which is processed by standard host compiler
// e.g. gcc
// <<< >>> marks a call from host code to device code
// a.k.a. kernal launch, return to the parameters (1,1)
mykernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
}
|
.file "tmpxft_001673a8_00000000-6_hello_world_device_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<stdio.h>
// nvcc separate source code into device and host components
__global__ void mykernel(void) {
// Device code is compiled by Nvidia compiler
// This function is called from host code
}
int main(void) {
// Host code goes here which is processed by standard host compiler
// e.g. gcc
// <<< >>> marks a call from host code to device code
// a.k.a. kernal launch, return to the parameters (1,1)
mykernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
}
|
#include <hip/hip_runtime.h>
#include<stdio.h>
// nvcc separate source code into device and host components
__global__ void mykernel(void) {
// Device code is compiled by Nvidia compiler
// This function is called from host code
}
int main(void) {
// Host code goes here which is processed by standard host compiler
// e.g. gcc
// <<< >>> marks a call from host code to device code
// a.k.a. kernal launch, return to the parameters (1,1)
mykernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
// nvcc separate source code into device and host components
__global__ void mykernel(void) {
// Device code is compiled by Nvidia compiler
// This function is called from host code
}
int main(void) {
// Host code goes here which is processed by standard host compiler
// e.g. gcc
// <<< >>> marks a call from host code to device code
// a.k.a. kernal launch, return to the parameters (1,1)
mykernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
// nvcc separate source code into device and host components
__global__ void mykernel(void) {
// Device code is compiled by Nvidia compiler
// This function is called from host code
}
int main(void) {
// Host code goes here which is processed by standard host compiler
// e.g. gcc
// <<< >>> marks a call from host code to device code
// a.k.a. kernal launch, return to the parameters (1,1)
mykernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
}
|
.text
.file "hello_world_device_code.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001673a8_00000000-6_hello_world_device_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "hello_world_device_code.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda_runtime.h>
// 考虑到 cudaMemcpy 传输事件，等于或者大于 CPU 计算的时间。
// 使用 共享内存 来避免数据拷贝传输的问题。
// 需要处理的元素数量
#define SIZE 1000
// 图像灰度等级划分为 16
#define NUM_BIN 16
// Define kernel function.
__global__ void hist_without_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
device_b[item]++;
}
}
__global__ void hist_with_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
atomicAdd(&(device_b[item]), 1);
}
}
int main(int argc, char **argv)
{
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int j = 0; j < NUM_BIN; ++j)
{
host_b[j] = 0;
}
int *device_a, *device_b;
cudaMalloc((void**)&device_a, SIZE * sizeof(int));
cudaMalloc((void**)&device_b, NUM_BIN * sizeof(int));
cudaMemcpy(device_a, host_a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, NUM_BIN * sizeof(int), cudaMemcpyHostToDevice);
// hist_without_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hist_with_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
cudaMemcpy(host_b, device_b, NUM_BIN * sizeof(int), cudaMemcpyDeviceToHost);
printf("Histogram using 16 bin without shared Memory is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
cudaFree(device_a);
cudaFree(device_b);
return 0;
}
|
code for sm_80
Function : _Z16hist_with_atomicPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x3e7, PT ; /* 0x000003e70200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x004fcc00078e0205 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19hist_without_atomicPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x3e7, PT ; /* 0x000003e70200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x004fca00078e0205 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda_runtime.h>
// 考虑到 cudaMemcpy 传输事件，等于或者大于 CPU 计算的时间。
// 使用 共享内存 来避免数据拷贝传输的问题。
// 需要处理的元素数量
#define SIZE 1000
// 图像灰度等级划分为 16
#define NUM_BIN 16
// Define kernel function.
__global__ void hist_without_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
device_b[item]++;
}
}
__global__ void hist_with_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
atomicAdd(&(device_b[item]), 1);
}
}
int main(int argc, char **argv)
{
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int j = 0; j < NUM_BIN; ++j)
{
host_b[j] = 0;
}
int *device_a, *device_b;
cudaMalloc((void**)&device_a, SIZE * sizeof(int));
cudaMalloc((void**)&device_b, NUM_BIN * sizeof(int));
cudaMemcpy(device_a, host_a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, NUM_BIN * sizeof(int), cudaMemcpyHostToDevice);
// hist_without_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hist_with_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
cudaMemcpy(host_b, device_b, NUM_BIN * sizeof(int), cudaMemcpyDeviceToHost);
printf("Histogram using 16 bin without shared Memory is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
cudaFree(device_a);
cudaFree(device_b);
return 0;
}
|
.file "tmpxft_00091fef_00000000-6_4_05_histogram_statistics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z19hist_without_atomicPiS_PiS_
.type _Z41__device_stub__Z19hist_without_atomicPiS_PiS_, @function
_Z41__device_stub__Z19hist_without_atomicPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19hist_without_atomicPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z19hist_without_atomicPiS_PiS_, .-_Z41__device_stub__Z19hist_without_atomicPiS_PiS_
.globl _Z19hist_without_atomicPiS_
.type _Z19hist_without_atomicPiS_, @function
_Z19hist_without_atomicPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19hist_without_atomicPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19hist_without_atomicPiS_, .-_Z19hist_without_atomicPiS_
.globl _Z38__device_stub__Z16hist_with_atomicPiS_PiS_
.type _Z38__device_stub__Z16hist_with_atomicPiS_PiS_, @function
_Z38__device_stub__Z16hist_with_atomicPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16hist_with_atomicPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z16hist_with_atomicPiS_PiS_, .-_Z38__device_stub__Z16hist_with_atomicPiS_PiS_
.globl _Z16hist_with_atomicPiS_
.type _Z16hist_with_atomicPiS_, @function
_Z16hist_with_atomicPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16hist_with_atomicPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16hist_with_atomicPiS_, .-_Z16hist_with_atomicPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Histogram using 16 bin without shared Memory is: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $40, %rsp
.cfi_def_cfa_offset 4160
movq %fs:40, %rax
movq %rax, 4120(%rsp)
xorl %eax, %eax
.L20:
movl %eax, %ecx
sarl $31, %ecx
shrl $28, %ecx
leal (%rcx,%rax), %edx
andl $15, %edx
subl %ecx, %edx
movl %edx, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L20
leaq 48(%rsp), %rax
leaq 112(%rsp), %rdx
.L21:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $63, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L23:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4120(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $4136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z16hist_with_atomicPiS_PiS_
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z16hist_with_atomicPiS_"
.LC3:
.string "_Z19hist_without_atomicPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16hist_with_atomicPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z19hist_without_atomicPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda_runtime.h>
// 考虑到 cudaMemcpy 传输事件，等于或者大于 CPU 计算的时间。
// 使用 共享内存 来避免数据拷贝传输的问题。
// 需要处理的元素数量
#define SIZE 1000
// 图像灰度等级划分为 16
#define NUM_BIN 16
// Define kernel function.
__global__ void hist_without_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
device_b[item]++;
}
}
__global__ void hist_with_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
atomicAdd(&(device_b[item]), 1);
}
}
int main(int argc, char **argv)
{
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int j = 0; j < NUM_BIN; ++j)
{
host_b[j] = 0;
}
int *device_a, *device_b;
cudaMalloc((void**)&device_a, SIZE * sizeof(int));
cudaMalloc((void**)&device_b, NUM_BIN * sizeof(int));
cudaMemcpy(device_a, host_a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, NUM_BIN * sizeof(int), cudaMemcpyHostToDevice);
// hist_without_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hist_with_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
cudaMemcpy(host_b, device_b, NUM_BIN * sizeof(int), cudaMemcpyDeviceToHost);
printf("Histogram using 16 bin without shared Memory is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
cudaFree(device_a);
cudaFree(device_b);
return 0;
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
// 考虑到 cudaMemcpy 传输事件，等于或者大于 CPU 计算的时间。
// 使用 共享内存 来避免数据拷贝传输的问题。
// 需要处理的元素数量
#define SIZE 1000
// 图像灰度等级划分为 16
#define NUM_BIN 16
// Define kernel function.
__global__ void hist_without_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
device_b[item]++;
}
}
__global__ void hist_with_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
atomicAdd(&(device_b[item]), 1);
}
}
int main(int argc, char **argv)
{
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int j = 0; j < NUM_BIN; ++j)
{
host_b[j] = 0;
}
int *device_a, *device_b;
hipMalloc((void**)&device_a, SIZE * sizeof(int));
hipMalloc((void**)&device_b, NUM_BIN * sizeof(int));
hipMemcpy(device_a, host_a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, NUM_BIN * sizeof(int), hipMemcpyHostToDevice);
// hist_without_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hist_with_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hipMemcpy(host_b, device_b, NUM_BIN * sizeof(int), hipMemcpyDeviceToHost);
printf("Histogram using 16 bin without shared Memory is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
hipFree(device_a);
hipFree(device_b);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
// 考虑到 cudaMemcpy 传输事件，等于或者大于 CPU 计算的时间。
// 使用 共享内存 来避免数据拷贝传输的问题。
// 需要处理的元素数量
#define SIZE 1000
// 图像灰度等级划分为 16
#define NUM_BIN 16
// Define kernel function.
__global__ void hist_without_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
device_b[item]++;
}
}
__global__ void hist_with_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
atomicAdd(&(device_b[item]), 1);
}
}
int main(int argc, char **argv)
{
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int j = 0; j < NUM_BIN; ++j)
{
host_b[j] = 0;
}
int *device_a, *device_b;
hipMalloc((void**)&device_a, SIZE * sizeof(int));
hipMalloc((void**)&device_b, NUM_BIN * sizeof(int));
hipMemcpy(device_a, host_a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, NUM_BIN * sizeof(int), hipMemcpyHostToDevice);
// hist_without_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hist_with_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hipMemcpy(host_b, device_b, NUM_BIN * sizeof(int), hipMemcpyDeviceToHost);
printf("Histogram using 16 bin without shared Memory is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
hipFree(device_a);
hipFree(device_b);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19hist_without_atomicPiS_
.globl _Z19hist_without_atomicPiS_
.p2align 8
.type _Z19hist_without_atomicPiS_,@function
_Z19hist_without_atomicPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19hist_without_atomicPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19hist_without_atomicPiS_, .Lfunc_end0-_Z19hist_without_atomicPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16hist_with_atomicPiS_
.globl _Z16hist_with_atomicPiS_
.p2align 8
.type _Z16hist_with_atomicPiS_,@function
_Z16hist_with_atomicPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16hist_with_atomicPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16hist_with_atomicPiS_, .Lfunc_end1-_Z16hist_with_atomicPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19hist_without_atomicPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19hist_without_atomicPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16hist_with_atomicPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16hist_with_atomicPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
// 考虑到 cudaMemcpy 传输事件，等于或者大于 CPU 计算的时间。
// 使用 共享内存 来避免数据拷贝传输的问题。
// 需要处理的元素数量
#define SIZE 1000
// 图像灰度等级划分为 16
#define NUM_BIN 16
// Define kernel function.
__global__ void hist_without_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
device_b[item]++;
}
}
__global__ void hist_with_atomic(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int item = device_a[tid];
if (tid < SIZE)
{
atomicAdd(&(device_b[item]), 1);
}
}
int main(int argc, char **argv)
{
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int j = 0; j < NUM_BIN; ++j)
{
host_b[j] = 0;
}
int *device_a, *device_b;
hipMalloc((void**)&device_a, SIZE * sizeof(int));
hipMalloc((void**)&device_b, NUM_BIN * sizeof(int));
hipMemcpy(device_a, host_a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, NUM_BIN * sizeof(int), hipMemcpyHostToDevice);
// hist_without_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hist_with_atomic <<< (SIZE + NUM_BIN - 1) / NUM_BIN, NUM_BIN >>> (device_b, device_a);
hipMemcpy(host_b, device_b, NUM_BIN * sizeof(int), hipMemcpyDeviceToHost);
printf("Histogram using 16 bin without shared Memory is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
hipFree(device_a);
hipFree(device_b);
return 0;
}
|
.text
.file "4_05_histogram_statistics.hip"
.globl _Z34__device_stub__hist_without_atomicPiS_ # -- Begin function _Z34__device_stub__hist_without_atomicPiS_
.p2align 4, 0x90
.type _Z34__device_stub__hist_without_atomicPiS_,@function
_Z34__device_stub__hist_without_atomicPiS_: # @_Z34__device_stub__hist_without_atomicPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19hist_without_atomicPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__hist_without_atomicPiS_, .Lfunc_end0-_Z34__device_stub__hist_without_atomicPiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__hist_with_atomicPiS_ # -- Begin function _Z31__device_stub__hist_with_atomicPiS_
.p2align 4, 0x90
.type _Z31__device_stub__hist_with_atomicPiS_,@function
_Z31__device_stub__hist_with_atomicPiS_: # @_Z31__device_stub__hist_with_atomicPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16hist_with_atomicPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__hist_with_atomicPiS_, .Lfunc_end1-_Z31__device_stub__hist_with_atomicPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $15, %ecx
movl %ecx, 160(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB2_1
# %bb.2:
xorps %xmm0, %xmm0
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdx # imm = 0x100000010
leaq 47(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16hist_with_atomicPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB2_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19hist_without_atomicPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16hist_with_atomicPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19hist_without_atomicPiS_,@object # @_Z19hist_without_atomicPiS_
.section .rodata,"a",@progbits
.globl _Z19hist_without_atomicPiS_
.p2align 3, 0x0
_Z19hist_without_atomicPiS_:
.quad _Z34__device_stub__hist_without_atomicPiS_
.size _Z19hist_without_atomicPiS_, 8
.type _Z16hist_with_atomicPiS_,@object # @_Z16hist_with_atomicPiS_
.globl _Z16hist_with_atomicPiS_
.p2align 3, 0x0
_Z16hist_with_atomicPiS_:
.quad _Z31__device_stub__hist_with_atomicPiS_
.size _Z16hist_with_atomicPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "bin %d: count %d\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19hist_without_atomicPiS_"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16hist_with_atomicPiS_"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Histogram using 16 bin without shared Memory is: "
.size .Lstr, 50
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__hist_without_atomicPiS_
.addrsig_sym _Z31__device_stub__hist_with_atomicPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19hist_without_atomicPiS_
.addrsig_sym _Z16hist_with_atomicPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z16hist_with_atomicPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x3e7, PT ; /* 0x000003e70200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x004fcc00078e0205 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19hist_without_atomicPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x3e7, PT ; /* 0x000003e70200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x004fca00078e0205 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19hist_without_atomicPiS_
.globl _Z19hist_without_atomicPiS_
.p2align 8
.type _Z19hist_without_atomicPiS_,@function
_Z19hist_without_atomicPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19hist_without_atomicPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19hist_without_atomicPiS_, .Lfunc_end0-_Z19hist_without_atomicPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16hist_with_atomicPiS_
.globl _Z16hist_with_atomicPiS_
.p2align 8
.type _Z16hist_with_atomicPiS_,@function
_Z16hist_with_atomicPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16hist_with_atomicPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16hist_with_atomicPiS_, .Lfunc_end1-_Z16hist_with_atomicPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19hist_without_atomicPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19hist_without_atomicPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16hist_with_atomicPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16hist_with_atomicPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00091fef_00000000-6_4_05_histogram_statistics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z19hist_without_atomicPiS_PiS_
.type _Z41__device_stub__Z19hist_without_atomicPiS_PiS_, @function
_Z41__device_stub__Z19hist_without_atomicPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19hist_without_atomicPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z19hist_without_atomicPiS_PiS_, .-_Z41__device_stub__Z19hist_without_atomicPiS_PiS_
.globl _Z19hist_without_atomicPiS_
.type _Z19hist_without_atomicPiS_, @function
_Z19hist_without_atomicPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19hist_without_atomicPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19hist_without_atomicPiS_, .-_Z19hist_without_atomicPiS_
.globl _Z38__device_stub__Z16hist_with_atomicPiS_PiS_
.type _Z38__device_stub__Z16hist_with_atomicPiS_PiS_, @function
_Z38__device_stub__Z16hist_with_atomicPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16hist_with_atomicPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z16hist_with_atomicPiS_PiS_, .-_Z38__device_stub__Z16hist_with_atomicPiS_PiS_
.globl _Z16hist_with_atomicPiS_
.type _Z16hist_with_atomicPiS_, @function
_Z16hist_with_atomicPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16hist_with_atomicPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16hist_with_atomicPiS_, .-_Z16hist_with_atomicPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Histogram using 16 bin without shared Memory is: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $40, %rsp
.cfi_def_cfa_offset 4160
movq %fs:40, %rax
movq %rax, 4120(%rsp)
xorl %eax, %eax
.L20:
movl %eax, %ecx
sarl $31, %ecx
shrl $28, %ecx
leal (%rcx,%rax), %edx
andl $15, %edx
subl %ecx, %edx
movl %edx, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L20
leaq 48(%rsp), %rax
leaq 112(%rsp), %rdx
.L21:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $63, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L23:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4120(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $4136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z16hist_with_atomicPiS_PiS_
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z16hist_with_atomicPiS_"
.LC3:
.string "_Z19hist_without_atomicPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16hist_with_atomicPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z19hist_without_atomicPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "4_05_histogram_statistics.hip"
.globl _Z34__device_stub__hist_without_atomicPiS_ # -- Begin function _Z34__device_stub__hist_without_atomicPiS_
.p2align 4, 0x90
.type _Z34__device_stub__hist_without_atomicPiS_,@function
_Z34__device_stub__hist_without_atomicPiS_: # @_Z34__device_stub__hist_without_atomicPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19hist_without_atomicPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__hist_without_atomicPiS_, .Lfunc_end0-_Z34__device_stub__hist_without_atomicPiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__hist_with_atomicPiS_ # -- Begin function _Z31__device_stub__hist_with_atomicPiS_
.p2align 4, 0x90
.type _Z31__device_stub__hist_with_atomicPiS_,@function
_Z31__device_stub__hist_with_atomicPiS_: # @_Z31__device_stub__hist_with_atomicPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16hist_with_atomicPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__hist_with_atomicPiS_, .Lfunc_end1-_Z31__device_stub__hist_with_atomicPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $15, %ecx
movl %ecx, 160(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB2_1
# %bb.2:
xorps %xmm0, %xmm0
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdx # imm = 0x100000010
leaq 47(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16hist_with_atomicPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB2_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19hist_without_atomicPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16hist_with_atomicPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19hist_without_atomicPiS_,@object # @_Z19hist_without_atomicPiS_
.section .rodata,"a",@progbits
.globl _Z19hist_without_atomicPiS_
.p2align 3, 0x0
_Z19hist_without_atomicPiS_:
.quad _Z34__device_stub__hist_without_atomicPiS_
.size _Z19hist_without_atomicPiS_, 8
.type _Z16hist_with_atomicPiS_,@object # @_Z16hist_with_atomicPiS_
.globl _Z16hist_with_atomicPiS_
.p2align 3, 0x0
_Z16hist_with_atomicPiS_:
.quad _Z31__device_stub__hist_with_atomicPiS_
.size _Z16hist_with_atomicPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "bin %d: count %d\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19hist_without_atomicPiS_"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16hist_with_atomicPiS_"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Histogram using 16 bin without shared Memory is: "
.size .Lstr, 50
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__hist_without_atomicPiS_
.addrsig_sym _Z31__device_stub__hist_with_atomicPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19hist_without_atomicPiS_
.addrsig_sym _Z16hist_with_atomicPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
* mmult_gpu.cu -- Device code for matrix multiplication benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void mmult_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
unsigned int i;
unsigned int product = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
for (i = 0; i < cols; i++)
product += a[row * cols + i] + b[i * cols + col];
c[index] = product;
}
|
code for sm_80
Function : _Z12mmult_kernelPjS_S_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R27, SR_TID.X ; /* 0x00000000001b7919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD R17, R2, c[0x0][0x0], R27 ; /* 0x0000000002117a24 */
/* 0x002fe200078e021b */
/*00a0*/ @!P0 BRA 0x4a0 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R18, c[0x0][0x17c] ; /* 0x00005f0000127a02 */
/* 0x000fe20000000f00 */
/*00c0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe400078e00ff */
/*00e0*/ IADD3 R3, R18.reuse, -0x1, RZ ; /* 0xffffffff12037810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R19, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312137812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*0110*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fd60003f05270 */
/*0120*/ @!P1 BRA 0x3c0 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R27, R27, c[0x0][0x17c], RZ ; /* 0x00005f001b1b7a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD R22, R0, R18, 0x3 ; /* 0x0000000300167424 */
/* 0x000fe200078e0212 */
/*0150*/ IADD3 R25, R19, -c[0x0][0x17c], RZ ; /* 0x80005f0013197a10 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD R16, R18, 0x2, R17 ; /* 0x0000000212107824 */
/* 0x000fe200078e0211 */
/*0170*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R27, R2, c[0x0][0x0], R27 ; /* 0x00000000021b7a24 */
/* 0x000fe400078e021b */
/*0190*/ IMAD R21, R18, 0x3, R17.reuse ; /* 0x0000000312157824 */
/* 0x100fe400078e0211 */
/*01a0*/ IMAD.MOV.U32 R23, RZ, RZ, R17 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0011 */
/*01b0*/ IADD3 R29, R22, -0x3, RZ ; /* 0xfffffffd161d7810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fc40000000f00 */
/*01d0*/ IADD3 R5, R22.reuse, -0x2, RZ ; /* 0xfffffffe16057810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ IADD3 R9, R22, -0x1, RZ ; /* 0xffffffff16097810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.WIDE.U32 R28, R29, R12, c[0x0][0x160] ; /* 0x000058001d1c7625 */
/* 0x000fc800078e000c */
/*0200*/ IMAD.WIDE.U32 R14, R23, R12.reuse, c[0x0][0x168] ; /* 0x00005a00170e7625 */
/* 0x080fe400078e000c */
/*0210*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.WIDE.U32 R4, R5, R12.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe400078e000c */
/*0230*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R6, R27, R12.reuse, c[0x0][0x168] ; /* 0x00005a001b067625 */
/* 0x080fe400078e000c */
/*0250*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R8, R9, R12, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc400078e000c */
/*0270*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R2, R16, R12.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x080fe400078e000c */
/*0290*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R10, R22, R12.reuse, c[0x0][0x160] ; /* 0x00005800160a7625 */
/* 0x080fe400078e000c */
/*02b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R12, R21, R12, c[0x0][0x168] ; /* 0x00005a00150c7625 */
/* 0x000fc400078e000c */
/*02d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD R16, R18.reuse, 0x4, R16 ; /* 0x0000000412107824 */
/* 0x040fe200078e0210 */
/*0310*/ LEA R27, R18.reuse, R27, 0x2 ; /* 0x0000001b121b7211 */
/* 0x040fe200078e10ff */
/*0320*/ IMAD R21, R18.reuse, 0x4, R21 ; /* 0x0000000412157824 */
/* 0x040fe200078e0215 */
/*0330*/ LEA R23, R18, R23, 0x2 ; /* 0x0000001712177211 */
/* 0x000fe400078e10ff */
/*0340*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fc40007ffe0ff */
/*0350*/ IADD3 R14, R14, R29, R24 ; /* 0x0000001d0e0e7210 */
/* 0x004fc80007ffe018 */
/*0360*/ IADD3 R5, R7, R4, R14 ; /* 0x0000000407057210 */
/* 0x008fe20007ffe00e */
/*0370*/ IMAD.IADD R4, R25, 0x1, R20 ; /* 0x0000000119047824 */
/* 0x000fca00078e0214 */
/*0380*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0390*/ IADD3 R5, R2, R8, R5 ; /* 0x0000000802057210 */
/* 0x010fc80007ffe005 */
/*03a0*/ IADD3 R24, R12, R10, R5 ; /* 0x0000000a0c187210 */
/* 0x020fce0007ffe005 */
/*03b0*/ @P1 BRA 0x1b0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*03c0*/ @!P0 BRA 0x4a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD R6, R20, c[0x0][0x17c], R17 ; /* 0x00005f0014067a24 */
/* 0x000fe400078e0211 */
/*03e0*/ IMAD R20, R0, c[0x0][0x17c], R20 ; /* 0x00005f0000147a24 */
/* 0x000fe400078e0214 */
/*03f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0400*/ IMAD.WIDE.U32 R2, R20, R5, c[0x0][0x160] ; /* 0x0000580014027625 */
/* 0x000fc800078e0005 */
/*0410*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0005 */
/*0420*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IADD3 R19, R19, -0x1, RZ ; /* 0xffffffff13137810 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fe40007ffe0ff */
/*0460*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc40003f05270 */
/*0470*/ IADD3 R6, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006067a10 */
/* 0x000fe40007ffe0ff */
/*0480*/ IADD3 R24, R4, R3, R24 ; /* 0x0000000304187210 */
/* 0x004fd20007ffe018 */
/*0490*/ @P0 BRA 0x3f0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD R2, R0, c[0x0][0x17c], R17 ; /* 0x00005f0000027a24 */
/* 0x000fc800078e0211 */
/*04c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04d0*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
* mmult_gpu.cu -- Device code for matrix multiplication benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void mmult_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
unsigned int i;
unsigned int product = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
for (i = 0; i < cols; i++)
product += a[row * cols + i] + b[i * cols + col];
c[index] = product;
}
|
.file "tmpxft_0013d63b_00000000-6_mmult_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj
.type _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj, @function
_Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12mmult_kernelPjS_S_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj, .-_Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj
.globl _Z12mmult_kernelPjS_S_jj
.type _Z12mmult_kernelPjS_S_jj, @function
_Z12mmult_kernelPjS_S_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12mmult_kernelPjS_S_jj, .-_Z12mmult_kernelPjS_S_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mmult_kernelPjS_S_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mmult_kernelPjS_S_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* mmult_gpu.cu -- Device code for matrix multiplication benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void mmult_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
unsigned int i;
unsigned int product = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
for (i = 0; i < cols; i++)
product += a[row * cols + i] + b[i * cols + col];
c[index] = product;
}
|
#include <hip/hip_runtime.h>
/*
* mmult_gpu.cu -- Device code for matrix multiplication benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void mmult_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
unsigned int i;
unsigned int product = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
for (i = 0; i < cols; i++)
product += a[row * cols + i] + b[i * cols + col];
c[index] = product;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
/*
* mmult_gpu.cu -- Device code for matrix multiplication benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void mmult_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
unsigned int i;
unsigned int product = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
for (i = 0; i < cols; i++)
product += a[row * cols + i] + b[i * cols + col];
c[index] = product;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mmult_kernelPjS_S_jj
.globl _Z12mmult_kernelPjS_S_jj
.p2align 8
.type _Z12mmult_kernelPjS_S_jj,@function
_Z12mmult_kernelPjS_S_jj:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_eq_u32 s2, 0
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v5, v2, s2
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
v_mov_b32_e32 v6, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v1, s3, v5
s_add_i32 s3, s3, 1
s_cmp_lg_u32 s2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v4, v[9:10], off
s_waitcnt vmcnt(0)
v_add3_u32 v6, v1, v6, v4
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v5, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mmult_kernelPjS_S_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mmult_kernelPjS_S_jj, .Lfunc_end0-_Z12mmult_kernelPjS_S_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mmult_kernelPjS_S_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mmult_kernelPjS_S_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
/*
* mmult_gpu.cu -- Device code for matrix multiplication benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void mmult_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
unsigned int i;
unsigned int product = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
for (i = 0; i < cols; i++)
product += a[row * cols + i] + b[i * cols + col];
c[index] = product;
}
|
.text
.file "mmult_gpu.hip"
.globl _Z27__device_stub__mmult_kernelPjS_S_jj # -- Begin function _Z27__device_stub__mmult_kernelPjS_S_jj
.p2align 4, 0x90
.type _Z27__device_stub__mmult_kernelPjS_S_jj,@function
_Z27__device_stub__mmult_kernelPjS_S_jj: # @_Z27__device_stub__mmult_kernelPjS_S_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mmult_kernelPjS_S_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__mmult_kernelPjS_S_jj, .Lfunc_end0-_Z27__device_stub__mmult_kernelPjS_S_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mmult_kernelPjS_S_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mmult_kernelPjS_S_jj,@object # @_Z12mmult_kernelPjS_S_jj
.section .rodata,"a",@progbits
.globl _Z12mmult_kernelPjS_S_jj
.p2align 3, 0x0
_Z12mmult_kernelPjS_S_jj:
.quad _Z27__device_stub__mmult_kernelPjS_S_jj
.size _Z12mmult_kernelPjS_S_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mmult_kernelPjS_S_jj"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mmult_kernelPjS_S_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mmult_kernelPjS_S_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12mmult_kernelPjS_S_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R27, SR_TID.X ; /* 0x00000000001b7919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD R17, R2, c[0x0][0x0], R27 ; /* 0x0000000002117a24 */
/* 0x002fe200078e021b */
/*00a0*/ @!P0 BRA 0x4a0 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R18, c[0x0][0x17c] ; /* 0x00005f0000127a02 */
/* 0x000fe20000000f00 */
/*00c0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe400078e00ff */
/*00e0*/ IADD3 R3, R18.reuse, -0x1, RZ ; /* 0xffffffff12037810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R19, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312137812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*0110*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fd60003f05270 */
/*0120*/ @!P1 BRA 0x3c0 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R27, R27, c[0x0][0x17c], RZ ; /* 0x00005f001b1b7a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD R22, R0, R18, 0x3 ; /* 0x0000000300167424 */
/* 0x000fe200078e0212 */
/*0150*/ IADD3 R25, R19, -c[0x0][0x17c], RZ ; /* 0x80005f0013197a10 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD R16, R18, 0x2, R17 ; /* 0x0000000212107824 */
/* 0x000fe200078e0211 */
/*0170*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R27, R2, c[0x0][0x0], R27 ; /* 0x00000000021b7a24 */
/* 0x000fe400078e021b */
/*0190*/ IMAD R21, R18, 0x3, R17.reuse ; /* 0x0000000312157824 */
/* 0x100fe400078e0211 */
/*01a0*/ IMAD.MOV.U32 R23, RZ, RZ, R17 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0011 */
/*01b0*/ IADD3 R29, R22, -0x3, RZ ; /* 0xfffffffd161d7810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fc40000000f00 */
/*01d0*/ IADD3 R5, R22.reuse, -0x2, RZ ; /* 0xfffffffe16057810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ IADD3 R9, R22, -0x1, RZ ; /* 0xffffffff16097810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.WIDE.U32 R28, R29, R12, c[0x0][0x160] ; /* 0x000058001d1c7625 */
/* 0x000fc800078e000c */
/*0200*/ IMAD.WIDE.U32 R14, R23, R12.reuse, c[0x0][0x168] ; /* 0x00005a00170e7625 */
/* 0x080fe400078e000c */
/*0210*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.WIDE.U32 R4, R5, R12.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe400078e000c */
/*0230*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R6, R27, R12.reuse, c[0x0][0x168] ; /* 0x00005a001b067625 */
/* 0x080fe400078e000c */
/*0250*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R8, R9, R12, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc400078e000c */
/*0270*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R2, R16, R12.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x080fe400078e000c */
/*0290*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R10, R22, R12.reuse, c[0x0][0x160] ; /* 0x00005800160a7625 */
/* 0x080fe400078e000c */
/*02b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R12, R21, R12, c[0x0][0x168] ; /* 0x00005a00150c7625 */
/* 0x000fc400078e000c */
/*02d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD R16, R18.reuse, 0x4, R16 ; /* 0x0000000412107824 */
/* 0x040fe200078e0210 */
/*0310*/ LEA R27, R18.reuse, R27, 0x2 ; /* 0x0000001b121b7211 */
/* 0x040fe200078e10ff */
/*0320*/ IMAD R21, R18.reuse, 0x4, R21 ; /* 0x0000000412157824 */
/* 0x040fe200078e0215 */
/*0330*/ LEA R23, R18, R23, 0x2 ; /* 0x0000001712177211 */
/* 0x000fe400078e10ff */
/*0340*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fc40007ffe0ff */
/*0350*/ IADD3 R14, R14, R29, R24 ; /* 0x0000001d0e0e7210 */
/* 0x004fc80007ffe018 */
/*0360*/ IADD3 R5, R7, R4, R14 ; /* 0x0000000407057210 */
/* 0x008fe20007ffe00e */
/*0370*/ IMAD.IADD R4, R25, 0x1, R20 ; /* 0x0000000119047824 */
/* 0x000fca00078e0214 */
/*0380*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0390*/ IADD3 R5, R2, R8, R5 ; /* 0x0000000802057210 */
/* 0x010fc80007ffe005 */
/*03a0*/ IADD3 R24, R12, R10, R5 ; /* 0x0000000a0c187210 */
/* 0x020fce0007ffe005 */
/*03b0*/ @P1 BRA 0x1b0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*03c0*/ @!P0 BRA 0x4a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD R6, R20, c[0x0][0x17c], R17 ; /* 0x00005f0014067a24 */
/* 0x000fe400078e0211 */
/*03e0*/ IMAD R20, R0, c[0x0][0x17c], R20 ; /* 0x00005f0000147a24 */
/* 0x000fe400078e0214 */
/*03f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0400*/ IMAD.WIDE.U32 R2, R20, R5, c[0x0][0x160] ; /* 0x0000580014027625 */
/* 0x000fc800078e0005 */
/*0410*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0005 */
/*0420*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IADD3 R19, R19, -0x1, RZ ; /* 0xffffffff13137810 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fe40007ffe0ff */
/*0460*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc40003f05270 */
/*0470*/ IADD3 R6, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006067a10 */
/* 0x000fe40007ffe0ff */
/*0480*/ IADD3 R24, R4, R3, R24 ; /* 0x0000000304187210 */
/* 0x004fd20007ffe018 */
/*0490*/ @P0 BRA 0x3f0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD R2, R0, c[0x0][0x17c], R17 ; /* 0x00005f0000027a24 */
/* 0x000fc800078e0211 */
/*04c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04d0*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mmult_kernelPjS_S_jj
.globl _Z12mmult_kernelPjS_S_jj
.p2align 8
.type _Z12mmult_kernelPjS_S_jj,@function
_Z12mmult_kernelPjS_S_jj:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_eq_u32 s2, 0
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v5, v2, s2
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
v_mov_b32_e32 v6, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v1, s3, v5
s_add_i32 s3, s3, 1
s_cmp_lg_u32 s2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v4, v[9:10], off
s_waitcnt vmcnt(0)
v_add3_u32 v6, v1, v6, v4
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v5, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mmult_kernelPjS_S_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mmult_kernelPjS_S_jj, .Lfunc_end0-_Z12mmult_kernelPjS_S_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mmult_kernelPjS_S_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mmult_kernelPjS_S_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0013d63b_00000000-6_mmult_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj
.type _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj, @function
_Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12mmult_kernelPjS_S_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj, .-_Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj
.globl _Z12mmult_kernelPjS_S_jj
.type _Z12mmult_kernelPjS_S_jj, @function
_Z12mmult_kernelPjS_S_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mmult_kernelPjS_S_jjPjS_S_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12mmult_kernelPjS_S_jj, .-_Z12mmult_kernelPjS_S_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mmult_kernelPjS_S_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mmult_kernelPjS_S_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "mmult_gpu.hip"
.globl _Z27__device_stub__mmult_kernelPjS_S_jj # -- Begin function _Z27__device_stub__mmult_kernelPjS_S_jj
.p2align 4, 0x90
.type _Z27__device_stub__mmult_kernelPjS_S_jj,@function
_Z27__device_stub__mmult_kernelPjS_S_jj: # @_Z27__device_stub__mmult_kernelPjS_S_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mmult_kernelPjS_S_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__mmult_kernelPjS_S_jj, .Lfunc_end0-_Z27__device_stub__mmult_kernelPjS_S_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mmult_kernelPjS_S_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mmult_kernelPjS_S_jj,@object # @_Z12mmult_kernelPjS_S_jj
.section .rodata,"a",@progbits
.globl _Z12mmult_kernelPjS_S_jj
.p2align 3, 0x0
_Z12mmult_kernelPjS_S_jj:
.quad _Z27__device_stub__mmult_kernelPjS_S_jj
.size _Z12mmult_kernelPjS_S_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mmult_kernelPjS_S_jj"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mmult_kernelPjS_S_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mmult_kernelPjS_S_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<stdio.h>
__global__ void end()
{
if(threadIdx.x==31 && blockIdx.x == 1023)
{
printf("end\n");
}
}
int main()
{
end<<<1024,32>>>();
cudaDeviceSynchronize();
}
|
code for sm_80
Function : _Z3endv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.AND P0, PT, R2, 0x3ff, PT ; /* 0x000003ff0200780c */
/* 0x001fc80003f05270 */
/*0040*/ ISETP.NE.OR P0, PT, R0, 0x1f, P0 ; /* 0x0000001f0000780c */
/* 0x002fda0000705670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
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