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stringlengths 10
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You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
extern "C" {
/*
#define BLOCK_SIZE 16
__global__ void matrix_multiply(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
}
*/
__global__ void matrix_multiply_0(const float* _A,const float *_B,float* _C,int _wa,int _wb)
{
float sum = 0;
//找出该线程所在的行列
int row = blockIdx.y*blockDim.y + threadIdx.y; // X 对应矩阵row, Y对应举证col
int col = blockIdx.x*blockDim.x + threadIdx.x;
//线程Thread(row,col)负责计算C(row,col)
for (int i = 0; i < _wa; ++i)
{
sum += _A[row*_wa + i]*_B[i*_wb + col];
}
_C[row*_wb + col] = sum;
}
__global__ void matrix_multiply_1(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
float sum = 0.0f;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if(row < numCRows && col < numCColumns){
for (int i = 0; i < numAColumns; ++i)
{
sum += A[row*numAColumns + i] * B[i*numBColumns + col];
}
C[row*numBColumns + col] = sum;
}
//printf("C = %f\n",C[row*numBColumns + col]);
}
__global__ void matrix_elementwise_multiply(float * A,float * B,float *C,int width,int height){
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = xIndex + yIndex * width;
if(xIndex < width && yIndex < height){
C[idx] = A[idx] * B[idx];
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrix_multiply_0
.globl matrix_multiply_0
.p2align 8
.type matrix_multiply_0,@function
matrix_multiply_0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrix_multiply_0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrix_multiply_0, .Lfunc_end0-matrix_multiply_0
.section .AMDGPU.csdata,"",@progbits
.text
.protected matrix_multiply_1
.globl matrix_multiply_1
.p2align 8
.type matrix_multiply_1,@function
matrix_multiply_1:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_6
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB1_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s3
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v6, 0
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrix_multiply_1
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size matrix_multiply_1, .Lfunc_end1-matrix_multiply_1
.section .AMDGPU.csdata,"",@progbits
.text
.protected matrix_elementwise_multiply
.globl matrix_elementwise_multiply
.p2align 8
.type matrix_elementwise_multiply,@function
matrix_elementwise_multiply:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrix_elementwise_multiply
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size matrix_elementwise_multiply, .Lfunc_end2-matrix_elementwise_multiply
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrix_multiply_0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrix_multiply_0.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrix_multiply_1
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrix_multiply_1.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrix_elementwise_multiply
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrix_elementwise_multiply.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
extern "C" {
/*
#define BLOCK_SIZE 16
__global__ void matrix_multiply(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
}
*/
__global__ void matrix_multiply_0(const float* _A,const float *_B,float* _C,int _wa,int _wb)
{
float sum = 0;
//找出该线程所在的行列
int row = blockIdx.y*blockDim.y + threadIdx.y; // X 对应矩阵row, Y对应举证col
int col = blockIdx.x*blockDim.x + threadIdx.x;
//线程Thread(row,col)负责计算C(row,col)
for (int i = 0; i < _wa; ++i)
{
sum += _A[row*_wa + i]*_B[i*_wb + col];
}
_C[row*_wb + col] = sum;
}
__global__ void matrix_multiply_1(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
float sum = 0.0f;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if(row < numCRows && col < numCColumns){
for (int i = 0; i < numAColumns; ++i)
{
sum += A[row*numAColumns + i] * B[i*numBColumns + col];
}
C[row*numBColumns + col] = sum;
}
//printf("C = %f\n",C[row*numBColumns + col]);
}
__global__ void matrix_elementwise_multiply(float * A,float * B,float *C,int width,int height){
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = xIndex + yIndex * width;
if(xIndex < width && yIndex < height){
C[idx] = A[idx] * B[idx];
}
}
}
|
.text
.file "10-matrix-multiply.hip"
.globl __device_stub__matrix_multiply_0 # -- Begin function __device_stub__matrix_multiply_0
.p2align 4, 0x90
.type __device_stub__matrix_multiply_0,@function
__device_stub__matrix_multiply_0: # @__device_stub__matrix_multiply_0
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrix_multiply_0, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__matrix_multiply_0, .Lfunc_end0-__device_stub__matrix_multiply_0
.cfi_endproc
# -- End function
.globl __device_stub__matrix_multiply_1 # -- Begin function __device_stub__matrix_multiply_1
.p2align 4, 0x90
.type __device_stub__matrix_multiply_1,@function
__device_stub__matrix_multiply_1: # @__device_stub__matrix_multiply_1
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $matrix_multiply_1, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub__matrix_multiply_1, .Lfunc_end1-__device_stub__matrix_multiply_1
.cfi_endproc
# -- End function
.globl __device_stub__matrix_elementwise_multiply # -- Begin function __device_stub__matrix_elementwise_multiply
.p2align 4, 0x90
.type __device_stub__matrix_elementwise_multiply,@function
__device_stub__matrix_elementwise_multiply: # @__device_stub__matrix_elementwise_multiply
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrix_elementwise_multiply, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__matrix_elementwise_multiply, .Lfunc_end2-__device_stub__matrix_elementwise_multiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_multiply_0, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_multiply_1, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_elementwise_multiply, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrix_multiply_0,@object # @matrix_multiply_0
.section .rodata,"a",@progbits
.globl matrix_multiply_0
.p2align 3, 0x0
matrix_multiply_0:
.quad __device_stub__matrix_multiply_0
.size matrix_multiply_0, 8
.type matrix_multiply_1,@object # @matrix_multiply_1
.globl matrix_multiply_1
.p2align 3, 0x0
matrix_multiply_1:
.quad __device_stub__matrix_multiply_1
.size matrix_multiply_1, 8
.type matrix_elementwise_multiply,@object # @matrix_elementwise_multiply
.globl matrix_elementwise_multiply
.p2align 3, 0x0
matrix_elementwise_multiply:
.quad __device_stub__matrix_elementwise_multiply
.size matrix_elementwise_multiply, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrix_multiply_0"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "matrix_multiply_1"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "matrix_elementwise_multiply"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrix_multiply_0
.addrsig_sym __device_stub__matrix_multiply_1
.addrsig_sym __device_stub__matrix_elementwise_multiply
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrix_multiply_0
.addrsig_sym matrix_multiply_1
.addrsig_sym matrix_elementwise_multiply
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000937b3_00000000-6_10-matrix-multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii
.type _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii, @function
_Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrix_multiply_0(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii, .-_Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii
.globl matrix_multiply_0
.type matrix_multiply_0, @function
matrix_multiply_0:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrix_multiply_0, .-matrix_multiply_0
.globl _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii
.type _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii, @function
_Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq matrix_multiply_1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii, .-_Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii
.globl matrix_multiply_1
.type matrix_multiply_1, @function
matrix_multiply_1:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size matrix_multiply_1, .-matrix_multiply_1
.globl _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii
.type _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii, @function
_Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrix_elementwise_multiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii, .-_Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii
.globl matrix_elementwise_multiply
.type matrix_elementwise_multiply, @function
matrix_elementwise_multiply:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size matrix_elementwise_multiply, .-matrix_elementwise_multiply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrix_elementwise_multiply"
.LC1:
.string "matrix_multiply_1"
.LC2:
.string "matrix_multiply_0"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrix_elementwise_multiply(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq matrix_multiply_1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq matrix_multiply_0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "10-matrix-multiply.hip"
.globl __device_stub__matrix_multiply_0 # -- Begin function __device_stub__matrix_multiply_0
.p2align 4, 0x90
.type __device_stub__matrix_multiply_0,@function
__device_stub__matrix_multiply_0: # @__device_stub__matrix_multiply_0
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrix_multiply_0, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__matrix_multiply_0, .Lfunc_end0-__device_stub__matrix_multiply_0
.cfi_endproc
# -- End function
.globl __device_stub__matrix_multiply_1 # -- Begin function __device_stub__matrix_multiply_1
.p2align 4, 0x90
.type __device_stub__matrix_multiply_1,@function
__device_stub__matrix_multiply_1: # @__device_stub__matrix_multiply_1
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $matrix_multiply_1, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub__matrix_multiply_1, .Lfunc_end1-__device_stub__matrix_multiply_1
.cfi_endproc
# -- End function
.globl __device_stub__matrix_elementwise_multiply # -- Begin function __device_stub__matrix_elementwise_multiply
.p2align 4, 0x90
.type __device_stub__matrix_elementwise_multiply,@function
__device_stub__matrix_elementwise_multiply: # @__device_stub__matrix_elementwise_multiply
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrix_elementwise_multiply, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__matrix_elementwise_multiply, .Lfunc_end2-__device_stub__matrix_elementwise_multiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_multiply_0, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_multiply_1, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrix_elementwise_multiply, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrix_multiply_0,@object # @matrix_multiply_0
.section .rodata,"a",@progbits
.globl matrix_multiply_0
.p2align 3, 0x0
matrix_multiply_0:
.quad __device_stub__matrix_multiply_0
.size matrix_multiply_0, 8
.type matrix_multiply_1,@object # @matrix_multiply_1
.globl matrix_multiply_1
.p2align 3, 0x0
matrix_multiply_1:
.quad __device_stub__matrix_multiply_1
.size matrix_multiply_1, 8
.type matrix_elementwise_multiply,@object # @matrix_elementwise_multiply
.globl matrix_elementwise_multiply
.p2align 3, 0x0
matrix_elementwise_multiply:
.quad __device_stub__matrix_elementwise_multiply
.size matrix_elementwise_multiply, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrix_multiply_0"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "matrix_multiply_1"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "matrix_elementwise_multiply"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrix_multiply_0
.addrsig_sym __device_stub__matrix_multiply_1
.addrsig_sym __device_stub__matrix_elementwise_multiply
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrix_multiply_0
.addrsig_sym matrix_multiply_1
.addrsig_sym matrix_elementwise_multiply
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
__global__ void reduce_kernel(const int* g_idata, int* g_odata,
unsigned int n) {
extern __shared__ int arr[];
long tid = threadIdx.x;
long idx = (long)blockIdx.x * (long)blockDim.x + tid;
if (idx < n)
arr[tid] = g_idata[idx];
else
arr[tid] = 0;
__syncthreads();
for (long i = blockDim.x / 2; i > 0; i >>= 1) {
if (tid < i) {
if (tid + i < n) // Not needed
arr[tid] += arr[tid + i];
}
__syncthreads();
}
if (tid == 0) g_odata[blockIdx.x] = arr[0];
}
__host__ int reduce(const int* arr, unsigned int N,
unsigned int threads_per_block) {
int num_blocks = (N + threads_per_block - 1) / threads_per_block;
int *darr, *dout;
cudaMalloc((void**)&darr, N * sizeof(int));
cudaMalloc((void**)&dout, num_blocks * sizeof(int));
// int* tmp = new int[num_blocks];
int* tmp = new int[1];
cudaMemcpy(darr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
while (num_blocks > 1) {
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
cudaDeviceSynchronize();
// cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(darr, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToDevice);
N = num_blocks;
num_blocks = (num_blocks + threads_per_block - 1) / threads_per_block;
// cudaMemcpy(darr, tmp, N * sizeof(int), cudaMemcpyHostToDevice);
}
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
cudaDeviceSynchronize();
cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(darr);
cudaFree(dout);
int ret = tmp[0];
delete[] tmp;
// return tmp[0];
return ret;
}
|
code for sm_80
Function : _Z13reduce_kernelPKiPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc800078e0005 */
/*0060*/ IMAD.WIDE.U32 R8, R7, c[0x0][0x0], R2 ; /* 0x0000000007087a25 */
/* 0x002fca00078e0002 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fc80003f06070 */
/*0080*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f06100 */
/*0090*/ @!P0 LEA R2, P1, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008028a11 */
/* 0x000fc800078210ff */
/*00a0*/ @!P0 LEA.HI.X R3, R8, c[0x0][0x164], R9, 0x2, P1 ; /* 0x0000590008038a11 */
/* 0x000fca00008f1409 */
/*00b0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00e0*/ @P0 STS [R5.X4], RZ ; /* 0x000000ff05000388 */
/* 0x0001e80000004800 */
/*00f0*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x0041e80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0110*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0120*/ @!P0 BRA 0x290 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0130*/ UMOV UR5, UR4 ; /* 0x0000000400057c82 */
/* 0x001fe40008000000 */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0150*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x001fe2000f8e00ff */
/*0160*/ ISETP.LT.U32.AND P0, PT, R5, UR5, PT ; /* 0x0000000505007c0c */
/* 0x000fe2000bf01070 */
/*0170*/ BSSY B0, 0x230 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0180*/ ISETP.GT.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f04100 */
/*0190*/ @!P0 BRA 0x220 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R3, P1, R5, UR5, RZ ; /* 0x0000000505037c10 */
/* 0x000fc8000ff3e0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06070 */
/*01c0*/ IMAD.X R0, RZ, RZ, UR4, P1 ; /* 0x00000004ff007e24 */
/* 0x000fca00088e06ff */
/*01d0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06100 */
/*01e0*/ @!P0 LDS R3, [R3.X4] ; /* 0x0000000003038984 */
/* 0x000fe80000004800 */
/*01f0*/ @!P0 LDS R0, [R5.X4] ; /* 0x0000000005008984 */
/* 0x000e240000004800 */
/*0200*/ @!P0 IMAD.IADD R0, R0, 0x1, R3 ; /* 0x0000000100008824 */
/* 0x001fca00078e0203 */
/*0210*/ @!P0 STS [R5.X4], R0 ; /* 0x0000000005008388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ USHF.R.U64 UR5, UR5, 0x1, UR4 ; /* 0x0000000105057899 */
/* 0x000fe20008001204 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011604 */
/*0260*/ ISETP.NE.U32.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fc8000bf05070 */
/*0270*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05300 */
/*0280*/ @P0 BRA 0x150 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x001fda0003f05270 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fc800078010ff */
/*02d0*/ LEA.HI.X R3, R7, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fca00000f14ff */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
__global__ void reduce_kernel(const int* g_idata, int* g_odata,
unsigned int n) {
extern __shared__ int arr[];
long tid = threadIdx.x;
long idx = (long)blockIdx.x * (long)blockDim.x + tid;
if (idx < n)
arr[tid] = g_idata[idx];
else
arr[tid] = 0;
__syncthreads();
for (long i = blockDim.x / 2; i > 0; i >>= 1) {
if (tid < i) {
if (tid + i < n) // Not needed
arr[tid] += arr[tid + i];
}
__syncthreads();
}
if (tid == 0) g_odata[blockIdx.x] = arr[0];
}
__host__ int reduce(const int* arr, unsigned int N,
unsigned int threads_per_block) {
int num_blocks = (N + threads_per_block - 1) / threads_per_block;
int *darr, *dout;
cudaMalloc((void**)&darr, N * sizeof(int));
cudaMalloc((void**)&dout, num_blocks * sizeof(int));
// int* tmp = new int[num_blocks];
int* tmp = new int[1];
cudaMemcpy(darr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
while (num_blocks > 1) {
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
cudaDeviceSynchronize();
// cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(darr, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToDevice);
N = num_blocks;
num_blocks = (num_blocks + threads_per_block - 1) / threads_per_block;
// cudaMemcpy(darr, tmp, N * sizeof(int), cudaMemcpyHostToDevice);
}
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
cudaDeviceSynchronize();
cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(darr);
cudaFree(dout);
int ret = tmp[0];
delete[] tmp;
// return tmp[0];
return ret;
}
|
.file "tmpxft_00107639_00000000-6_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
.type _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij, @function
_Z37__device_stub__Z13reduce_kernelPKiPijPKiPij:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13reduce_kernelPKiPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij, .-_Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
.globl _Z13reduce_kernelPKiPij
.type _Z13reduce_kernelPKiPij, @function
_Z13reduce_kernelPKiPij:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13reduce_kernelPKiPij, .-_Z13reduce_kernelPKiPij
.globl _Z6reducePKijj
.type _Z6reducePKijj, @function
_Z6reducePKijj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, %r12d
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal -1(%rdx), %r15d
leal (%r15,%rsi), %eax
movl $0, %edx
divl %ebp
movl %eax, %r13d
movl %eax, %ebx
movl %esi, %eax
leaq 0(,%rax,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movslq %r13d, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl $4, %edi
call _Znam@PLT
movq %rax, (%rsp)
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, %r13d
jle .L12
movl %ebp, %r14d
salq $2, %r14
jmp .L14
.L13:
call cudaDeviceSynchronize@PLT
movslq %ebx, %rdx
salq $2, %rdx
movl $3, %ecx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leal (%r12,%r15), %eax
movl $0, %edx
divl %ebp
movl %eax, %ebx
cmpl $1, %eax
jle .L12
.L14:
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r12d, %r13d
movl %ebx, %r12d
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movq %r14, %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %r13d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
jmp .L13
.L12:
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %ebp, %ebp
movl $0, %r9d
leaq 0(,%rbp,4), %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
movl (%rbx), %ebx
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r12d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z6reducePKijj, .-_Z6reducePKijj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13reduce_kernelPKiPij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduce_kernelPKiPij(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
__global__ void reduce_kernel(const int* g_idata, int* g_odata,
unsigned int n) {
extern __shared__ int arr[];
long tid = threadIdx.x;
long idx = (long)blockIdx.x * (long)blockDim.x + tid;
if (idx < n)
arr[tid] = g_idata[idx];
else
arr[tid] = 0;
__syncthreads();
for (long i = blockDim.x / 2; i > 0; i >>= 1) {
if (tid < i) {
if (tid + i < n) // Not needed
arr[tid] += arr[tid + i];
}
__syncthreads();
}
if (tid == 0) g_odata[blockIdx.x] = arr[0];
}
__host__ int reduce(const int* arr, unsigned int N,
unsigned int threads_per_block) {
int num_blocks = (N + threads_per_block - 1) / threads_per_block;
int *darr, *dout;
cudaMalloc((void**)&darr, N * sizeof(int));
cudaMalloc((void**)&dout, num_blocks * sizeof(int));
// int* tmp = new int[num_blocks];
int* tmp = new int[1];
cudaMemcpy(darr, arr, N * sizeof(int), cudaMemcpyHostToDevice);
while (num_blocks > 1) {
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
cudaDeviceSynchronize();
// cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(darr, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToDevice);
N = num_blocks;
num_blocks = (num_blocks + threads_per_block - 1) / threads_per_block;
// cudaMemcpy(darr, tmp, N * sizeof(int), cudaMemcpyHostToDevice);
}
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
cudaDeviceSynchronize();
cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(darr);
cudaFree(dout);
int ret = tmp[0];
delete[] tmp;
// return tmp[0];
return ret;
}
|
#include <hip/hip_runtime.h>
__global__ void reduce_kernel(const int* g_idata, int* g_odata,
unsigned int n) {
extern __shared__ int arr[];
long tid = threadIdx.x;
long idx = (long)blockIdx.x * (long)blockDim.x + tid;
if (idx < n)
arr[tid] = g_idata[idx];
else
arr[tid] = 0;
__syncthreads();
for (long i = blockDim.x / 2; i > 0; i >>= 1) {
if (tid < i) {
if (tid + i < n) // Not needed
arr[tid] += arr[tid + i];
}
__syncthreads();
}
if (tid == 0) g_odata[blockIdx.x] = arr[0];
}
__host__ int reduce(const int* arr, unsigned int N,
unsigned int threads_per_block) {
int num_blocks = (N + threads_per_block - 1) / threads_per_block;
int *darr, *dout;
hipMalloc((void**)&darr, N * sizeof(int));
hipMalloc((void**)&dout, num_blocks * sizeof(int));
// int* tmp = new int[num_blocks];
int* tmp = new int[1];
hipMemcpy(darr, arr, N * sizeof(int), hipMemcpyHostToDevice);
while (num_blocks > 1) {
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
hipDeviceSynchronize();
// cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
hipMemcpy(darr, dout, num_blocks * sizeof(int), hipMemcpyDeviceToDevice);
N = num_blocks;
num_blocks = (num_blocks + threads_per_block - 1) / threads_per_block;
// cudaMemcpy(darr, tmp, N * sizeof(int), cudaMemcpyHostToDevice);
}
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
hipDeviceSynchronize();
hipMemcpy(tmp, dout, num_blocks * sizeof(int), hipMemcpyDeviceToHost);
hipFree(darr);
hipFree(dout);
int ret = tmp[0];
delete[] tmp;
// return tmp[0];
return ret;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
__global__ void reduce_kernel(const int* g_idata, int* g_odata,
unsigned int n) {
extern __shared__ int arr[];
long tid = threadIdx.x;
long idx = (long)blockIdx.x * (long)blockDim.x + tid;
if (idx < n)
arr[tid] = g_idata[idx];
else
arr[tid] = 0;
__syncthreads();
for (long i = blockDim.x / 2; i > 0; i >>= 1) {
if (tid < i) {
if (tid + i < n) // Not needed
arr[tid] += arr[tid + i];
}
__syncthreads();
}
if (tid == 0) g_odata[blockIdx.x] = arr[0];
}
__host__ int reduce(const int* arr, unsigned int N,
unsigned int threads_per_block) {
int num_blocks = (N + threads_per_block - 1) / threads_per_block;
int *darr, *dout;
hipMalloc((void**)&darr, N * sizeof(int));
hipMalloc((void**)&dout, num_blocks * sizeof(int));
// int* tmp = new int[num_blocks];
int* tmp = new int[1];
hipMemcpy(darr, arr, N * sizeof(int), hipMemcpyHostToDevice);
while (num_blocks > 1) {
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
hipDeviceSynchronize();
// cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
hipMemcpy(darr, dout, num_blocks * sizeof(int), hipMemcpyDeviceToDevice);
N = num_blocks;
num_blocks = (num_blocks + threads_per_block - 1) / threads_per_block;
// cudaMemcpy(darr, tmp, N * sizeof(int), cudaMemcpyHostToDevice);
}
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
hipDeviceSynchronize();
hipMemcpy(tmp, dout, num_blocks * sizeof(int), hipMemcpyDeviceToHost);
hipFree(darr);
hipFree(dout);
int ret = tmp[0];
delete[] tmp;
// return tmp[0];
return ret;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13reduce_kernelPKiPij
.globl _Z13reduce_kernelPKiPij
.p2align 8
.type _Z13reduce_kernelPKiPij,@function
_Z13reduce_kernelPKiPij:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
s_mov_b32 s4, s15
s_mov_b32 s7, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s4, v[0:1]
v_cmpx_gt_u64_e64 s[6:7], v[2:3]
s_cbranch_execz .LBB0_2
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_cmp_lt_u16_e64 s3, s3, 2
v_lshl_add_u32 v2, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s3
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_7
v_lshl_add_u32 v4, v0, 2, 0
s_lshr_b32 s8, s2, 1
s_mov_b32 s9, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_u64_e64 s2, s[8:9], 2
s_lshr_b64 s[8:9], s[8:9], 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
.LBB0_5:
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_cmp_gt_u64_e32 vcc_lo, s[8:9], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s2, s[6:7], v[2:3]
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v4, v2
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduce_kernelPKiPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13reduce_kernelPKiPij, .Lfunc_end0-_Z13reduce_kernelPKiPij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduce_kernelPKiPij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13reduce_kernelPKiPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
__global__ void reduce_kernel(const int* g_idata, int* g_odata,
unsigned int n) {
extern __shared__ int arr[];
long tid = threadIdx.x;
long idx = (long)blockIdx.x * (long)blockDim.x + tid;
if (idx < n)
arr[tid] = g_idata[idx];
else
arr[tid] = 0;
__syncthreads();
for (long i = blockDim.x / 2; i > 0; i >>= 1) {
if (tid < i) {
if (tid + i < n) // Not needed
arr[tid] += arr[tid + i];
}
__syncthreads();
}
if (tid == 0) g_odata[blockIdx.x] = arr[0];
}
__host__ int reduce(const int* arr, unsigned int N,
unsigned int threads_per_block) {
int num_blocks = (N + threads_per_block - 1) / threads_per_block;
int *darr, *dout;
hipMalloc((void**)&darr, N * sizeof(int));
hipMalloc((void**)&dout, num_blocks * sizeof(int));
// int* tmp = new int[num_blocks];
int* tmp = new int[1];
hipMemcpy(darr, arr, N * sizeof(int), hipMemcpyHostToDevice);
while (num_blocks > 1) {
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
hipDeviceSynchronize();
// cudaMemcpy(tmp, dout, num_blocks * sizeof(int), cudaMemcpyDeviceToHost);
hipMemcpy(darr, dout, num_blocks * sizeof(int), hipMemcpyDeviceToDevice);
N = num_blocks;
num_blocks = (num_blocks + threads_per_block - 1) / threads_per_block;
// cudaMemcpy(darr, tmp, N * sizeof(int), cudaMemcpyHostToDevice);
}
reduce_kernel<<<num_blocks, threads_per_block,
sizeof(int) * threads_per_block>>>(darr, dout, N);
hipDeviceSynchronize();
hipMemcpy(tmp, dout, num_blocks * sizeof(int), hipMemcpyDeviceToHost);
hipFree(darr);
hipFree(dout);
int ret = tmp[0];
delete[] tmp;
// return tmp[0];
return ret;
}
|
.text
.file "reduce.hip"
.globl _Z28__device_stub__reduce_kernelPKiPij # -- Begin function _Z28__device_stub__reduce_kernelPKiPij
.p2align 4, 0x90
.type _Z28__device_stub__reduce_kernelPKiPij,@function
_Z28__device_stub__reduce_kernelPKiPij: # @_Z28__device_stub__reduce_kernelPKiPij
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduce_kernelPKiPij, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__reduce_kernelPKiPij, .Lfunc_end0-_Z28__device_stub__reduce_kernelPKiPij
.cfi_endproc
# -- End function
.globl _Z6reducePKijj # -- Begin function _Z6reducePKijj
.p2align 4, 0x90
.type _Z6reducePKijj,@function
_Z6reducePKijj: # @_Z6reducePKijj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r13d
movl %esi, %r15d
movq %rdi, %rbx
leal (%r15,%r13), %eax
decl %eax
xorl %edx, %edx
divl %r13d
movl %eax, %ebp
movl %esi, %r12d
shlq $2, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl %ebp, 28(%rsp) # 4-byte Spill
movslq %ebp, %r14
leaq (,%r14,4), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl $4, %edi
callq _Znam
movq %rax, 128(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, %rsi
movl %esi, %ebp
cmpl $2, %r14d
movq %rbp, 120(%rsp) # 8-byte Spill
jl .LBB1_1
# %bb.2: # %.lr.ph
leaq (,%rbp,4), %rax
movq %rax, 144(%rsp) # 8-byte Spill
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rbp
leal -1(%rsi), %eax
movq %rax, 136(%rsp) # 8-byte Spill
movl 28(%rsp), %eax # 4-byte Reload
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
shlq $2, %rbx
movq %rbx, %rdx
movl $3, %ecx
callq hipMemcpy
movq 136(%rsp), %rax # 8-byte Reload
addl %r12d, %eax
xorl %edx, %edx
movq %r14, %rsi
divl %esi
movl %r12d, %r15d
cmpl $1, %eax
movq %r13, %rcx
jle .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rsi, %r14
movl %eax, %r12d
movl %eax, %ebx
movq %rbx, %rdi
movq %rcx, %r13
orq %rcx, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
movq 144(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z13reduce_kernelPKiPij, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_1:
movl %r15d, %r12d
movl 28(%rsp), %eax # 4-byte Reload
movabsq $4294967296, %rcx # imm = 0x100000000
.LBB1_6: # %._crit_edge
movq 120(%rsp), %rdx # 8-byte Reload
leaq (,%rdx,4), %r8
movl %eax, %ebx
movl %eax, %edi
orq %rcx, %rdi
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r12d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13reduce_kernelPKiPij, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movslq %ebx, %rdx
shlq $2, %rdx
movq 128(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl (%r14), %ebx
movq %r14, %rdi
callq _ZdaPv
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6reducePKijj, .Lfunc_end1-_Z6reducePKijj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduce_kernelPKiPij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13reduce_kernelPKiPij,@object # @_Z13reduce_kernelPKiPij
.section .rodata,"a",@progbits
.globl _Z13reduce_kernelPKiPij
.p2align 3, 0x0
_Z13reduce_kernelPKiPij:
.quad _Z28__device_stub__reduce_kernelPKiPij
.size _Z13reduce_kernelPKiPij, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13reduce_kernelPKiPij"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__reduce_kernelPKiPij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13reduce_kernelPKiPij
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z13reduce_kernelPKiPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc800078e0005 */
/*0060*/ IMAD.WIDE.U32 R8, R7, c[0x0][0x0], R2 ; /* 0x0000000007087a25 */
/* 0x002fca00078e0002 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fc80003f06070 */
/*0080*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f06100 */
/*0090*/ @!P0 LEA R2, P1, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008028a11 */
/* 0x000fc800078210ff */
/*00a0*/ @!P0 LEA.HI.X R3, R8, c[0x0][0x164], R9, 0x2, P1 ; /* 0x0000590008038a11 */
/* 0x000fca00008f1409 */
/*00b0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00e0*/ @P0 STS [R5.X4], RZ ; /* 0x000000ff05000388 */
/* 0x0001e80000004800 */
/*00f0*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x0041e80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0110*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0120*/ @!P0 BRA 0x290 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0130*/ UMOV UR5, UR4 ; /* 0x0000000400057c82 */
/* 0x001fe40008000000 */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0150*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x001fe2000f8e00ff */
/*0160*/ ISETP.LT.U32.AND P0, PT, R5, UR5, PT ; /* 0x0000000505007c0c */
/* 0x000fe2000bf01070 */
/*0170*/ BSSY B0, 0x230 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0180*/ ISETP.GT.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f04100 */
/*0190*/ @!P0 BRA 0x220 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R3, P1, R5, UR5, RZ ; /* 0x0000000505037c10 */
/* 0x000fc8000ff3e0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06070 */
/*01c0*/ IMAD.X R0, RZ, RZ, UR4, P1 ; /* 0x00000004ff007e24 */
/* 0x000fca00088e06ff */
/*01d0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06100 */
/*01e0*/ @!P0 LDS R3, [R3.X4] ; /* 0x0000000003038984 */
/* 0x000fe80000004800 */
/*01f0*/ @!P0 LDS R0, [R5.X4] ; /* 0x0000000005008984 */
/* 0x000e240000004800 */
/*0200*/ @!P0 IMAD.IADD R0, R0, 0x1, R3 ; /* 0x0000000100008824 */
/* 0x001fca00078e0203 */
/*0210*/ @!P0 STS [R5.X4], R0 ; /* 0x0000000005008388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ USHF.R.U64 UR5, UR5, 0x1, UR4 ; /* 0x0000000105057899 */
/* 0x000fe20008001204 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011604 */
/*0260*/ ISETP.NE.U32.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fc8000bf05070 */
/*0270*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05300 */
/*0280*/ @P0 BRA 0x150 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x001fda0003f05270 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fc800078010ff */
/*02d0*/ LEA.HI.X R3, R7, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fca00000f14ff */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13reduce_kernelPKiPij
.globl _Z13reduce_kernelPKiPij
.p2align 8
.type _Z13reduce_kernelPKiPij,@function
_Z13reduce_kernelPKiPij:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
s_mov_b32 s4, s15
s_mov_b32 s7, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s4, v[0:1]
v_cmpx_gt_u64_e64 s[6:7], v[2:3]
s_cbranch_execz .LBB0_2
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_cmp_lt_u16_e64 s3, s3, 2
v_lshl_add_u32 v2, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s3
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_7
v_lshl_add_u32 v4, v0, 2, 0
s_lshr_b32 s8, s2, 1
s_mov_b32 s9, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_u64_e64 s2, s[8:9], 2
s_lshr_b64 s[8:9], s[8:9], 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
.LBB0_5:
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_cmp_gt_u64_e32 vcc_lo, s[8:9], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s2, s[6:7], v[2:3]
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v4, v2
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduce_kernelPKiPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13reduce_kernelPKiPij, .Lfunc_end0-_Z13reduce_kernelPKiPij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduce_kernelPKiPij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13reduce_kernelPKiPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00107639_00000000-6_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
.type _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij, @function
_Z37__device_stub__Z13reduce_kernelPKiPijPKiPij:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13reduce_kernelPKiPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij, .-_Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
.globl _Z13reduce_kernelPKiPij
.type _Z13reduce_kernelPKiPij, @function
_Z13reduce_kernelPKiPij:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13reduce_kernelPKiPij, .-_Z13reduce_kernelPKiPij
.globl _Z6reducePKijj
.type _Z6reducePKijj, @function
_Z6reducePKijj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, %r12d
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal -1(%rdx), %r15d
leal (%r15,%rsi), %eax
movl $0, %edx
divl %ebp
movl %eax, %r13d
movl %eax, %ebx
movl %esi, %eax
leaq 0(,%rax,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movslq %r13d, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl $4, %edi
call _Znam@PLT
movq %rax, (%rsp)
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, %r13d
jle .L12
movl %ebp, %r14d
salq $2, %r14
jmp .L14
.L13:
call cudaDeviceSynchronize@PLT
movslq %ebx, %rdx
salq $2, %rdx
movl $3, %ecx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leal (%r12,%r15), %eax
movl $0, %edx
divl %ebp
movl %eax, %ebx
cmpl $1, %eax
jle .L12
.L14:
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r12d, %r13d
movl %ebx, %r12d
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movq %r14, %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %r13d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
jmp .L13
.L12:
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %ebp, %ebp
movl $0, %r9d
leaq 0(,%rbp,4), %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
movl (%rbx), %ebx
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %r12d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13reduce_kernelPKiPijPKiPij
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z6reducePKijj, .-_Z6reducePKijj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13reduce_kernelPKiPij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduce_kernelPKiPij(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "reduce.hip"
.globl _Z28__device_stub__reduce_kernelPKiPij # -- Begin function _Z28__device_stub__reduce_kernelPKiPij
.p2align 4, 0x90
.type _Z28__device_stub__reduce_kernelPKiPij,@function
_Z28__device_stub__reduce_kernelPKiPij: # @_Z28__device_stub__reduce_kernelPKiPij
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduce_kernelPKiPij, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__reduce_kernelPKiPij, .Lfunc_end0-_Z28__device_stub__reduce_kernelPKiPij
.cfi_endproc
# -- End function
.globl _Z6reducePKijj # -- Begin function _Z6reducePKijj
.p2align 4, 0x90
.type _Z6reducePKijj,@function
_Z6reducePKijj: # @_Z6reducePKijj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r13d
movl %esi, %r15d
movq %rdi, %rbx
leal (%r15,%r13), %eax
decl %eax
xorl %edx, %edx
divl %r13d
movl %eax, %ebp
movl %esi, %r12d
shlq $2, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl %ebp, 28(%rsp) # 4-byte Spill
movslq %ebp, %r14
leaq (,%r14,4), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl $4, %edi
callq _Znam
movq %rax, 128(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, %rsi
movl %esi, %ebp
cmpl $2, %r14d
movq %rbp, 120(%rsp) # 8-byte Spill
jl .LBB1_1
# %bb.2: # %.lr.ph
leaq (,%rbp,4), %rax
movq %rax, 144(%rsp) # 8-byte Spill
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rbp
leal -1(%rsi), %eax
movq %rax, 136(%rsp) # 8-byte Spill
movl 28(%rsp), %eax # 4-byte Reload
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
shlq $2, %rbx
movq %rbx, %rdx
movl $3, %ecx
callq hipMemcpy
movq 136(%rsp), %rax # 8-byte Reload
addl %r12d, %eax
xorl %edx, %edx
movq %r14, %rsi
divl %esi
movl %r12d, %r15d
cmpl $1, %eax
movq %r13, %rcx
jle .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rsi, %r14
movl %eax, %r12d
movl %eax, %ebx
movq %rbx, %rdi
movq %rcx, %r13
orq %rcx, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
movq 144(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z13reduce_kernelPKiPij, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_1:
movl %r15d, %r12d
movl 28(%rsp), %eax # 4-byte Reload
movabsq $4294967296, %rcx # imm = 0x100000000
.LBB1_6: # %._crit_edge
movq 120(%rsp), %rdx # 8-byte Reload
leaq (,%rdx,4), %r8
movl %eax, %ebx
movl %eax, %edi
orq %rcx, %rdi
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r12d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13reduce_kernelPKiPij, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movslq %ebx, %rdx
shlq $2, %rdx
movq 128(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl (%r14), %ebx
movq %r14, %rdi
callq _ZdaPv
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6reducePKijj, .Lfunc_end1-_Z6reducePKijj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduce_kernelPKiPij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13reduce_kernelPKiPij,@object # @_Z13reduce_kernelPKiPij
.section .rodata,"a",@progbits
.globl _Z13reduce_kernelPKiPij
.p2align 3, 0x0
_Z13reduce_kernelPKiPij:
.quad _Z28__device_stub__reduce_kernelPKiPij
.size _Z13reduce_kernelPKiPij, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13reduce_kernelPKiPij"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__reduce_kernelPKiPij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13reduce_kernelPKiPij
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include "sys/time.h"
using namespace std;
double timeInSeconds (timeval& starttime, timeval& stopstime) {
return 1e-6*(1e6*(stopstime.tv_sec - starttime.tv_sec) + (stopstime.tv_usec - starttime.tv_usec));
}
//__device__ double* dev_vector1 = 0;
//__device__ double* dev_vector2 = 0;
//__device__ double* dev_results = 0;
__global__ void device_vector_mult (double* v1, double* v2, double* res) {
// IMPLEMENT ME 6: Multiply the threadIdx.x element of dev_vector1 by the
// corresponding element of dev_vector2, and store in dev_results.
res[threadIdx.x] = 2 * v1[threadIdx.x] * v2[threadIdx.x];
}
__global__ void device_vector_reduce (double* results, int* length) {
int len = *length;
while (len > 1) {
if (threadIdx.x < (len - (len % 2)) / 2) {
results[threadIdx.x] += results[threadIdx.x + (len + (len % 2)) / 2];
}
len = (len + (len % 2)) / 2;
__syncthreads();
}
}
__global__ void device_vector_simpleAdd (double* vec, double* res) {
if (threadIdx.x == 0) {
res[0] = 2;
}
}
int main (int argc, char** argv) {
int sizeOfVector = 100;
if (argc > 1) sizeOfVector = atoi(argv[1]);
// Declare and fill host-side arrays of doubles.
double* vector1 = new double[sizeOfVector];
double* vector2 = new double[sizeOfVector];
double* results = new double[sizeOfVector];
double* gpuresults = new double[sizeOfVector];
double* gpuAddresults = new double[sizeOfVector];
srand(42);
for (int i = 0; i < sizeOfVector; ++i) {
vector1[i] = rand() % 100;
vector2[i] = rand() % 100;
results[i] = 0;
gpuresults[i] = 0;
gpuAddresults[i] = 0;
}
timeval startTime;
timeval interTime;
timeval stopsTime;
gettimeofday(&startTime, NULL);
// Use the CPU for this part.
// IMPLEMENT ME 1: Multiply each element of vector1 by the corresponding
// element in vector2 and store in results.
for (int i = 0; i < sizeOfVector; ++i) {
results[i] = vector1[i] * vector2[i];
}
gettimeofday(&interTime, NULL);
double total = 0;
// IMPLEMENT ME 2: Sum the results array and store the sum in total.
for (int i = 0; i < sizeOfVector; ++i) {
total += results[i];
}
gettimeofday(&stopsTime, NULL);
cout << "Dot product is: " << total << endl;
// IMPLEMENT ME 3: Time the above operations together and separately
// using 'gettimeofday'.
cout << "Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double* dev_vector1 = 0;
double* dev_vector2 = 0;
double* dev_results = 0;
int sizeInBytes = sizeOfVector * sizeof(double);
cudaMalloc((void**) &dev_vector1, sizeInBytes);
cudaMalloc((void**) &dev_vector2, sizeInBytes);
cudaMalloc((void**) &dev_results, sizeInBytes);
cudaMemcpy(dev_vector1, vector1, sizeInBytes, cudaMemcpyHostToDevice);
cudaMemcpy(dev_vector2, vector2, sizeInBytes, cudaMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
device_vector_mult<<<1, sizeOfVector>>>(dev_vector1, dev_vector2, dev_results);
double gputotal = 0;
cudaMemcpy(gpuresults, dev_results, sizeInBytes, cudaMemcpyDeviceToHost);
gettimeofday(&interTime, NULL);
for (int i = 0; i < sizeOfVector; ++i) {
gputotal += gpuresults[i];
}
gettimeofday(&stopsTime, NULL);
cout << "GPU-mult Dot product is: " << gputotal << endl;
cout << "GPU-mult Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "GPU-mult Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "GPU-mult Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double * dev_added = 0;
cudaMalloc((void**) &dev_added, sizeof(double));
//device_vector_simpleAdd<<<1, sizeOfVector>>>(dev_results, dev_added);
device_vector_reduce<<<1, sizeOfVector>>>(dev_results, &sizeOfVector);
double host_added = 2;
//cudaMemcpy(&host_added, &dev_added[0], sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(&host_added, &dev_results[0], sizeof(double), cudaMemcpyDeviceToHost);
cout <<"GPU-full Dot product is: " << host_added << endl;
cout << "Size of Vectors is: " << sizeOfVector << endl;
return 0;
}
|
code for sm_80
Function : _Z23device_vector_simpleAddPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0050*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; /* 0x40000000ff057424 */
/* 0x000fca00078e00ff */
/*0090*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20device_vector_reducePdPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x004fda0003f06270 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0080*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fd200078e0002 */
/*00a0*/ IMAD.WIDE.U32 R2, R9, R4, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fc800078e0004 */
/*00b0*/ SHF.R.U32.HI R4, RZ, 0x1, R0 ; /* 0x00000001ff047819 */
/* 0x000fe40000011600 */
/*00c0*/ LOP3.LUT R5, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100057812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fc60003f06070 */
/*00e0*/ IMAD.IADD R8, R5, 0x1, R0 ; /* 0x0000000105087824 */
/* 0x000fca00078e0200 */
/*00f0*/ LEA.HI R0, R8, R8, RZ, 0x1 ; /* 0x0000000808007211 */
/* 0x000fca00078f08ff */
/*0100*/ @!P0 MOV R5, 0x8 ; /* 0x0000000800058802 */
/* 0x000fe20000000f00 */
/*0110*/ @!P0 LDG.E.64 R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ @!P0 LEA.HI.SX32 R4, R0, R9, 0x1f ; /* 0x0000000900048211 */
/* 0x000fca00078ffaff */
/*0130*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fcc00078e0005 */
/*0140*/ @!P0 LDG.E.64 R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011400 */
/*0160*/ @!P0 DADD R6, R6, R4 ; /* 0x0000000006068229 */
/* 0x004e0e0000000004 */
/*0170*/ @!P0 STG.E.64 [R2.64], R6 ; /* 0x0000000602008986 */
/* 0x0011e8000c101b04 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GT.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fda0003f04270 */
/*01a0*/ @P0 BRA 0xb0 ; /* 0xffffff0000000947 */
/* 0x001fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18device_vector_multPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fc800078e0009 */
/*0050*/ IMAD.WIDE.U32 R6, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x0c0fe400078e0009 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0080*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0009 */
/*0090*/ DADD R4, R2, R2 ; /* 0x0000000002047229 */
/* 0x004ecc0000000002 */
/*00a0*/ DMUL R4, R4, R6 ; /* 0x0000000604047228 */
/* 0x008e0e0000000000 */
/*00b0*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include "sys/time.h"
using namespace std;
double timeInSeconds (timeval& starttime, timeval& stopstime) {
return 1e-6*(1e6*(stopstime.tv_sec - starttime.tv_sec) + (stopstime.tv_usec - starttime.tv_usec));
}
//__device__ double* dev_vector1 = 0;
//__device__ double* dev_vector2 = 0;
//__device__ double* dev_results = 0;
__global__ void device_vector_mult (double* v1, double* v2, double* res) {
// IMPLEMENT ME 6: Multiply the threadIdx.x element of dev_vector1 by the
// corresponding element of dev_vector2, and store in dev_results.
res[threadIdx.x] = 2 * v1[threadIdx.x] * v2[threadIdx.x];
}
__global__ void device_vector_reduce (double* results, int* length) {
int len = *length;
while (len > 1) {
if (threadIdx.x < (len - (len % 2)) / 2) {
results[threadIdx.x] += results[threadIdx.x + (len + (len % 2)) / 2];
}
len = (len + (len % 2)) / 2;
__syncthreads();
}
}
__global__ void device_vector_simpleAdd (double* vec, double* res) {
if (threadIdx.x == 0) {
res[0] = 2;
}
}
int main (int argc, char** argv) {
int sizeOfVector = 100;
if (argc > 1) sizeOfVector = atoi(argv[1]);
// Declare and fill host-side arrays of doubles.
double* vector1 = new double[sizeOfVector];
double* vector2 = new double[sizeOfVector];
double* results = new double[sizeOfVector];
double* gpuresults = new double[sizeOfVector];
double* gpuAddresults = new double[sizeOfVector];
srand(42);
for (int i = 0; i < sizeOfVector; ++i) {
vector1[i] = rand() % 100;
vector2[i] = rand() % 100;
results[i] = 0;
gpuresults[i] = 0;
gpuAddresults[i] = 0;
}
timeval startTime;
timeval interTime;
timeval stopsTime;
gettimeofday(&startTime, NULL);
// Use the CPU for this part.
// IMPLEMENT ME 1: Multiply each element of vector1 by the corresponding
// element in vector2 and store in results.
for (int i = 0; i < sizeOfVector; ++i) {
results[i] = vector1[i] * vector2[i];
}
gettimeofday(&interTime, NULL);
double total = 0;
// IMPLEMENT ME 2: Sum the results array and store the sum in total.
for (int i = 0; i < sizeOfVector; ++i) {
total += results[i];
}
gettimeofday(&stopsTime, NULL);
cout << "Dot product is: " << total << endl;
// IMPLEMENT ME 3: Time the above operations together and separately
// using 'gettimeofday'.
cout << "Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double* dev_vector1 = 0;
double* dev_vector2 = 0;
double* dev_results = 0;
int sizeInBytes = sizeOfVector * sizeof(double);
cudaMalloc((void**) &dev_vector1, sizeInBytes);
cudaMalloc((void**) &dev_vector2, sizeInBytes);
cudaMalloc((void**) &dev_results, sizeInBytes);
cudaMemcpy(dev_vector1, vector1, sizeInBytes, cudaMemcpyHostToDevice);
cudaMemcpy(dev_vector2, vector2, sizeInBytes, cudaMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
device_vector_mult<<<1, sizeOfVector>>>(dev_vector1, dev_vector2, dev_results);
double gputotal = 0;
cudaMemcpy(gpuresults, dev_results, sizeInBytes, cudaMemcpyDeviceToHost);
gettimeofday(&interTime, NULL);
for (int i = 0; i < sizeOfVector; ++i) {
gputotal += gpuresults[i];
}
gettimeofday(&stopsTime, NULL);
cout << "GPU-mult Dot product is: " << gputotal << endl;
cout << "GPU-mult Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "GPU-mult Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "GPU-mult Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double * dev_added = 0;
cudaMalloc((void**) &dev_added, sizeof(double));
//device_vector_simpleAdd<<<1, sizeOfVector>>>(dev_results, dev_added);
device_vector_reduce<<<1, sizeOfVector>>>(dev_results, &sizeOfVector);
double host_added = 2;
//cudaMemcpy(&host_added, &dev_added[0], sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(&host_added, &dev_results[0], sizeof(double), cudaMemcpyDeviceToHost);
cout <<"GPU-full Dot product is: " << host_added << endl;
cout << "Size of Vectors is: " << sizeOfVector << endl;
return 0;
}
|
.file "tmpxft_00115af4_00000000-6_ex1b.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13timeInSecondsR7timevalS0_
.type _Z13timeInSecondsR7timevalS0_, @function
_Z13timeInSecondsR7timevalS0_:
.LFB3669:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq 8(%rsi), %rax
subq 8(%rdi), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE3669:
.size _Z13timeInSecondsR7timevalS0_, .-_Z13timeInSecondsR7timevalS0_
.globl _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
.type _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_, @function
_Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18device_vector_multPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_, .-_Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
.globl _Z18device_vector_multPdS_S_
.type _Z18device_vector_multPdS_S_, @function
_Z18device_vector_multPdS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z18device_vector_multPdS_S_, .-_Z18device_vector_multPdS_S_
.globl _Z42__device_stub__Z20device_vector_reducePdPiPdPi
.type _Z42__device_stub__Z20device_vector_reducePdPiPdPi, @function
_Z42__device_stub__Z20device_vector_reducePdPiPdPi:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20device_vector_reducePdPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z42__device_stub__Z20device_vector_reducePdPiPdPi, .-_Z42__device_stub__Z20device_vector_reducePdPiPdPi
.globl _Z20device_vector_reducePdPi
.type _Z20device_vector_reducePdPi, @function
_Z20device_vector_reducePdPi:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20device_vector_reducePdPiPdPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z20device_vector_reducePdPi, .-_Z20device_vector_reducePdPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Dot product is: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Time for multiplication (seconds): "
.align 8
.LC5:
.string "Time for addition (seconds): "
.align 8
.LC6:
.string "Overall time (seconds): "
.section .rodata.str1.1
.LC7:
.string "GPU-mult Dot product is: "
.section .rodata.str1.8
.align 8
.LC8:
.string "GPU-mult Time for multiplication (seconds): "
.align 8
.LC9:
.string "GPU-mult Time for addition (seconds): "
.align 8
.LC10:
.string "GPU-mult Overall time (seconds): "
.section .rodata.str1.1
.LC12:
.string "GPU-full Dot product is: "
.LC13:
.string "Size of Vectors is: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movl %edi, %eax
movq %fs:40, %rdx
movq %rdx, 152(%rsp)
xorl %edx, %edx
movl $100, 28(%rsp)
movl $100, %edi
cmpl $1, %eax
jg .L61
.L21:
salq $3, %rdi
call _Znam@PLT
movq %rax, %rbp
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L62
salq $3, %rdi
call _Znam@PLT
movq %rax, %rbx
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L63
salq $3, %rdi
call _Znam@PLT
movq %rax, %r14
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L64
salq $3, %rdi
call _Znam@PLT
movq %rax, %r12
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L65
salq $3, %rdi
call _Znam@PLT
movq %rax, %r15
movl $42, %edi
call srand@PLT
movl $0, %r13d
cmpl $0, 28(%rsp)
jle .L36
.L35:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%rbp,%r13,8)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%r13,8)
movq $0x000000000, (%r14,%r13,8)
movq $0x000000000, (%r12,%r13,8)
movq $0x000000000, (%r15,%r13,8)
addq $1, %r13
cmpl %r13d, 28(%rsp)
jg .L35
.L36:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 28(%rsp), %edx
testl %edx, %edx
jle .L38
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
.L39:
movsd 0(%rbp,%rax), %xmm0
mulsd (%rbx,%rax), %xmm0
movsd %xmm0, (%r14,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L39
.L38:
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 28(%rsp), %edx
testl %edx, %edx
jle .L49
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,8), %rdx
movl $0x000000000, %r14d
.L41:
movq %r14, %xmm1
addsd (%rax), %xmm1
movq %xmm1, %r14
addq $8, %rax
cmpq %rdx, %rax
jne .L41
.L40:
leaq 128(%rsp), %r15
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, (%rsp)
leaq 112(%rsp), %rsi
leaq 96(%rsp), %r14
movq %rsi, 8(%rsp)
movq %r14, %rdi
call _Z13timeInSecondsR7timevalS0_
movq (%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, (%rsp)
movq %r15, %rsi
movq 8(%rsp), %rdi
call _Z13timeInSecondsR7timevalS0_
movq (%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movq %r15, %rsi
movq %r14, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl 28(%rsp), %eax
leal 0(,%rax,8), %r13d
movslq %r13d, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
movl 28(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L42:
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 28(%rsp), %edx
testl %edx, %edx
jle .L50
movq %r12, %rax
movslq %edx, %rdx
leaq (%r12,%rdx,8), %rdx
movl $0x000000000, %ebx
.L44:
movq %rbx, %xmm2
addsd (%rax), %xmm2
movq %xmm2, %rbx
addq $8, %rax
cmpq %rdx, %rax
jne .L44
.L43:
leaq 128(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
leaq 112(%rsp), %r14
leaq 96(%rsp), %r13
movq %r14, %rsi
movq %r13, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq %r12, %rsi
movq %r14, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq %r12, %rsi
movq %r13, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl 28(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L45:
movq .LC11(%rip), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 80(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
movslq %eax, %rdi
movabsq $1152921504606846975, %rax
cmpq %rdi, %rax
jnb .L21
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L25
call __stack_chk_fail@PLT
.L25:
call __cxa_throw_bad_array_new_length@PLT
.L62:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L28:
call __cxa_throw_bad_array_new_length@PLT
.L63:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L31:
call __cxa_throw_bad_array_new_length@PLT
.L64:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L34
call __stack_chk_fail@PLT
.L34:
call __cxa_throw_bad_array_new_length@PLT
.L65:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L49:
movl $0x000000000, %r14d
jmp .L40
.L66:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
jmp .L42
.L50:
movl $0x000000000, %ebx
jmp .L43
.L67:
leaq 28(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z42__device_stub__Z20device_vector_reducePdPiPdPi
jmp .L45
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_
.type _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_, @function
_Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_:
.LFB3699:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23device_vector_simpleAddPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_, .-_Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_
.globl _Z23device_vector_simpleAddPdS_
.type _Z23device_vector_simpleAddPdS_, @function
_Z23device_vector_simpleAddPdS_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z23device_vector_simpleAddPdS_, .-_Z23device_vector_simpleAddPdS_
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z23device_vector_simpleAddPdS_"
.section .rodata.str1.1
.LC15:
.string "_Z20device_vector_reducePdPi"
.LC16:
.string "_Z18device_vector_multPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z23device_vector_simpleAddPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z20device_vector_reducePdPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z18device_vector_multPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long -1598689907
.long 1051772663
.align 8
.LC11:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include "sys/time.h"
using namespace std;
double timeInSeconds (timeval& starttime, timeval& stopstime) {
return 1e-6*(1e6*(stopstime.tv_sec - starttime.tv_sec) + (stopstime.tv_usec - starttime.tv_usec));
}
//__device__ double* dev_vector1 = 0;
//__device__ double* dev_vector2 = 0;
//__device__ double* dev_results = 0;
__global__ void device_vector_mult (double* v1, double* v2, double* res) {
// IMPLEMENT ME 6: Multiply the threadIdx.x element of dev_vector1 by the
// corresponding element of dev_vector2, and store in dev_results.
res[threadIdx.x] = 2 * v1[threadIdx.x] * v2[threadIdx.x];
}
__global__ void device_vector_reduce (double* results, int* length) {
int len = *length;
while (len > 1) {
if (threadIdx.x < (len - (len % 2)) / 2) {
results[threadIdx.x] += results[threadIdx.x + (len + (len % 2)) / 2];
}
len = (len + (len % 2)) / 2;
__syncthreads();
}
}
__global__ void device_vector_simpleAdd (double* vec, double* res) {
if (threadIdx.x == 0) {
res[0] = 2;
}
}
int main (int argc, char** argv) {
int sizeOfVector = 100;
if (argc > 1) sizeOfVector = atoi(argv[1]);
// Declare and fill host-side arrays of doubles.
double* vector1 = new double[sizeOfVector];
double* vector2 = new double[sizeOfVector];
double* results = new double[sizeOfVector];
double* gpuresults = new double[sizeOfVector];
double* gpuAddresults = new double[sizeOfVector];
srand(42);
for (int i = 0; i < sizeOfVector; ++i) {
vector1[i] = rand() % 100;
vector2[i] = rand() % 100;
results[i] = 0;
gpuresults[i] = 0;
gpuAddresults[i] = 0;
}
timeval startTime;
timeval interTime;
timeval stopsTime;
gettimeofday(&startTime, NULL);
// Use the CPU for this part.
// IMPLEMENT ME 1: Multiply each element of vector1 by the corresponding
// element in vector2 and store in results.
for (int i = 0; i < sizeOfVector; ++i) {
results[i] = vector1[i] * vector2[i];
}
gettimeofday(&interTime, NULL);
double total = 0;
// IMPLEMENT ME 2: Sum the results array and store the sum in total.
for (int i = 0; i < sizeOfVector; ++i) {
total += results[i];
}
gettimeofday(&stopsTime, NULL);
cout << "Dot product is: " << total << endl;
// IMPLEMENT ME 3: Time the above operations together and separately
// using 'gettimeofday'.
cout << "Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double* dev_vector1 = 0;
double* dev_vector2 = 0;
double* dev_results = 0;
int sizeInBytes = sizeOfVector * sizeof(double);
cudaMalloc((void**) &dev_vector1, sizeInBytes);
cudaMalloc((void**) &dev_vector2, sizeInBytes);
cudaMalloc((void**) &dev_results, sizeInBytes);
cudaMemcpy(dev_vector1, vector1, sizeInBytes, cudaMemcpyHostToDevice);
cudaMemcpy(dev_vector2, vector2, sizeInBytes, cudaMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
device_vector_mult<<<1, sizeOfVector>>>(dev_vector1, dev_vector2, dev_results);
double gputotal = 0;
cudaMemcpy(gpuresults, dev_results, sizeInBytes, cudaMemcpyDeviceToHost);
gettimeofday(&interTime, NULL);
for (int i = 0; i < sizeOfVector; ++i) {
gputotal += gpuresults[i];
}
gettimeofday(&stopsTime, NULL);
cout << "GPU-mult Dot product is: " << gputotal << endl;
cout << "GPU-mult Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "GPU-mult Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "GPU-mult Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double * dev_added = 0;
cudaMalloc((void**) &dev_added, sizeof(double));
//device_vector_simpleAdd<<<1, sizeOfVector>>>(dev_results, dev_added);
device_vector_reduce<<<1, sizeOfVector>>>(dev_results, &sizeOfVector);
double host_added = 2;
//cudaMemcpy(&host_added, &dev_added[0], sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(&host_added, &dev_results[0], sizeof(double), cudaMemcpyDeviceToHost);
cout <<"GPU-full Dot product is: " << host_added << endl;
cout << "Size of Vectors is: " << sizeOfVector << endl;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include "sys/time.h"
using namespace std;
double timeInSeconds (timeval& starttime, timeval& stopstime) {
return 1e-6*(1e6*(stopstime.tv_sec - starttime.tv_sec) + (stopstime.tv_usec - starttime.tv_usec));
}
//__device__ double* dev_vector1 = 0;
//__device__ double* dev_vector2 = 0;
//__device__ double* dev_results = 0;
__global__ void device_vector_mult (double* v1, double* v2, double* res) {
// IMPLEMENT ME 6: Multiply the threadIdx.x element of dev_vector1 by the
// corresponding element of dev_vector2, and store in dev_results.
res[threadIdx.x] = 2 * v1[threadIdx.x] * v2[threadIdx.x];
}
__global__ void device_vector_reduce (double* results, int* length) {
int len = *length;
while (len > 1) {
if (threadIdx.x < (len - (len % 2)) / 2) {
results[threadIdx.x] += results[threadIdx.x + (len + (len % 2)) / 2];
}
len = (len + (len % 2)) / 2;
__syncthreads();
}
}
__global__ void device_vector_simpleAdd (double* vec, double* res) {
if (threadIdx.x == 0) {
res[0] = 2;
}
}
int main (int argc, char** argv) {
int sizeOfVector = 100;
if (argc > 1) sizeOfVector = atoi(argv[1]);
// Declare and fill host-side arrays of doubles.
double* vector1 = new double[sizeOfVector];
double* vector2 = new double[sizeOfVector];
double* results = new double[sizeOfVector];
double* gpuresults = new double[sizeOfVector];
double* gpuAddresults = new double[sizeOfVector];
srand(42);
for (int i = 0; i < sizeOfVector; ++i) {
vector1[i] = rand() % 100;
vector2[i] = rand() % 100;
results[i] = 0;
gpuresults[i] = 0;
gpuAddresults[i] = 0;
}
timeval startTime;
timeval interTime;
timeval stopsTime;
gettimeofday(&startTime, NULL);
// Use the CPU for this part.
// IMPLEMENT ME 1: Multiply each element of vector1 by the corresponding
// element in vector2 and store in results.
for (int i = 0; i < sizeOfVector; ++i) {
results[i] = vector1[i] * vector2[i];
}
gettimeofday(&interTime, NULL);
double total = 0;
// IMPLEMENT ME 2: Sum the results array and store the sum in total.
for (int i = 0; i < sizeOfVector; ++i) {
total += results[i];
}
gettimeofday(&stopsTime, NULL);
cout << "Dot product is: " << total << endl;
// IMPLEMENT ME 3: Time the above operations together and separately
// using 'gettimeofday'.
cout << "Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double* dev_vector1 = 0;
double* dev_vector2 = 0;
double* dev_results = 0;
int sizeInBytes = sizeOfVector * sizeof(double);
hipMalloc((void**) &dev_vector1, sizeInBytes);
hipMalloc((void**) &dev_vector2, sizeInBytes);
hipMalloc((void**) &dev_results, sizeInBytes);
hipMemcpy(dev_vector1, vector1, sizeInBytes, hipMemcpyHostToDevice);
hipMemcpy(dev_vector2, vector2, sizeInBytes, hipMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
device_vector_mult<<<1, sizeOfVector>>>(dev_vector1, dev_vector2, dev_results);
double gputotal = 0;
hipMemcpy(gpuresults, dev_results, sizeInBytes, hipMemcpyDeviceToHost);
gettimeofday(&interTime, NULL);
for (int i = 0; i < sizeOfVector; ++i) {
gputotal += gpuresults[i];
}
gettimeofday(&stopsTime, NULL);
cout << "GPU-mult Dot product is: " << gputotal << endl;
cout << "GPU-mult Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "GPU-mult Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "GPU-mult Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double * dev_added = 0;
hipMalloc((void**) &dev_added, sizeof(double));
//device_vector_simpleAdd<<<1, sizeOfVector>>>(dev_results, dev_added);
device_vector_reduce<<<1, sizeOfVector>>>(dev_results, &sizeOfVector);
double host_added = 2;
//cudaMemcpy(&host_added, &dev_added[0], sizeof(double), cudaMemcpyDeviceToHost);
hipMemcpy(&host_added, &dev_results[0], sizeof(double), hipMemcpyDeviceToHost);
cout <<"GPU-full Dot product is: " << host_added << endl;
cout << "Size of Vectors is: " << sizeOfVector << endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include "sys/time.h"
using namespace std;
double timeInSeconds (timeval& starttime, timeval& stopstime) {
return 1e-6*(1e6*(stopstime.tv_sec - starttime.tv_sec) + (stopstime.tv_usec - starttime.tv_usec));
}
//__device__ double* dev_vector1 = 0;
//__device__ double* dev_vector2 = 0;
//__device__ double* dev_results = 0;
__global__ void device_vector_mult (double* v1, double* v2, double* res) {
// IMPLEMENT ME 6: Multiply the threadIdx.x element of dev_vector1 by the
// corresponding element of dev_vector2, and store in dev_results.
res[threadIdx.x] = 2 * v1[threadIdx.x] * v2[threadIdx.x];
}
__global__ void device_vector_reduce (double* results, int* length) {
int len = *length;
while (len > 1) {
if (threadIdx.x < (len - (len % 2)) / 2) {
results[threadIdx.x] += results[threadIdx.x + (len + (len % 2)) / 2];
}
len = (len + (len % 2)) / 2;
__syncthreads();
}
}
__global__ void device_vector_simpleAdd (double* vec, double* res) {
if (threadIdx.x == 0) {
res[0] = 2;
}
}
int main (int argc, char** argv) {
int sizeOfVector = 100;
if (argc > 1) sizeOfVector = atoi(argv[1]);
// Declare and fill host-side arrays of doubles.
double* vector1 = new double[sizeOfVector];
double* vector2 = new double[sizeOfVector];
double* results = new double[sizeOfVector];
double* gpuresults = new double[sizeOfVector];
double* gpuAddresults = new double[sizeOfVector];
srand(42);
for (int i = 0; i < sizeOfVector; ++i) {
vector1[i] = rand() % 100;
vector2[i] = rand() % 100;
results[i] = 0;
gpuresults[i] = 0;
gpuAddresults[i] = 0;
}
timeval startTime;
timeval interTime;
timeval stopsTime;
gettimeofday(&startTime, NULL);
// Use the CPU for this part.
// IMPLEMENT ME 1: Multiply each element of vector1 by the corresponding
// element in vector2 and store in results.
for (int i = 0; i < sizeOfVector; ++i) {
results[i] = vector1[i] * vector2[i];
}
gettimeofday(&interTime, NULL);
double total = 0;
// IMPLEMENT ME 2: Sum the results array and store the sum in total.
for (int i = 0; i < sizeOfVector; ++i) {
total += results[i];
}
gettimeofday(&stopsTime, NULL);
cout << "Dot product is: " << total << endl;
// IMPLEMENT ME 3: Time the above operations together and separately
// using 'gettimeofday'.
cout << "Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double* dev_vector1 = 0;
double* dev_vector2 = 0;
double* dev_results = 0;
int sizeInBytes = sizeOfVector * sizeof(double);
hipMalloc((void**) &dev_vector1, sizeInBytes);
hipMalloc((void**) &dev_vector2, sizeInBytes);
hipMalloc((void**) &dev_results, sizeInBytes);
hipMemcpy(dev_vector1, vector1, sizeInBytes, hipMemcpyHostToDevice);
hipMemcpy(dev_vector2, vector2, sizeInBytes, hipMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
device_vector_mult<<<1, sizeOfVector>>>(dev_vector1, dev_vector2, dev_results);
double gputotal = 0;
hipMemcpy(gpuresults, dev_results, sizeInBytes, hipMemcpyDeviceToHost);
gettimeofday(&interTime, NULL);
for (int i = 0; i < sizeOfVector; ++i) {
gputotal += gpuresults[i];
}
gettimeofday(&stopsTime, NULL);
cout << "GPU-mult Dot product is: " << gputotal << endl;
cout << "GPU-mult Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "GPU-mult Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "GPU-mult Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double * dev_added = 0;
hipMalloc((void**) &dev_added, sizeof(double));
//device_vector_simpleAdd<<<1, sizeOfVector>>>(dev_results, dev_added);
device_vector_reduce<<<1, sizeOfVector>>>(dev_results, &sizeOfVector);
double host_added = 2;
//cudaMemcpy(&host_added, &dev_added[0], sizeof(double), cudaMemcpyDeviceToHost);
hipMemcpy(&host_added, &dev_results[0], sizeof(double), hipMemcpyDeviceToHost);
cout <<"GPU-full Dot product is: " << host_added << endl;
cout << "Size of Vectors is: " << sizeOfVector << endl;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18device_vector_multPdS_S_
.globl _Z18device_vector_multPdS_S_
.p2align 8
.type _Z18device_vector_multPdS_S_,@function
_Z18device_vector_multPdS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[4:5]
global_load_b64 v[2:3], v4, s[6:7]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[0:1], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18device_vector_multPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18device_vector_multPdS_S_, .Lfunc_end0-_Z18device_vector_multPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20device_vector_reducePdPi
.globl _Z20device_vector_reducePdPi
.p2align 8
.type _Z20device_vector_reducePdPi,@function
_Z20device_vector_reducePdPi:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 3, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s3, s0, v1
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s3, s3, s2
s_waitcnt_vscnt null, 0x0
s_lshr_b32 s2, s3, 1
s_cmp_gt_u32 s3, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_lshr_b32 s3, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_and_b32 s3, s2, 1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_2
s_add_i32 s5, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s5, s5, 1
v_add_nc_u32_e32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[3:4], off
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
global_store_b64 v[3:4], v[5:6], off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20device_vector_reducePdPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20device_vector_reducePdPi, .Lfunc_end1-_Z20device_vector_reducePdPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23device_vector_simpleAddPdS_
.globl _Z23device_vector_simpleAddPdS_
.p2align 8
.type _Z23device_vector_simpleAddPdS_,@function
_Z23device_vector_simpleAddPdS_:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 2.0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23device_vector_simpleAddPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z23device_vector_simpleAddPdS_, .Lfunc_end2-_Z23device_vector_simpleAddPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18device_vector_multPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z18device_vector_multPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20device_vector_reducePdPi
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z20device_vector_reducePdPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23device_vector_simpleAddPdS_
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z23device_vector_simpleAddPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include "sys/time.h"
using namespace std;
double timeInSeconds (timeval& starttime, timeval& stopstime) {
return 1e-6*(1e6*(stopstime.tv_sec - starttime.tv_sec) + (stopstime.tv_usec - starttime.tv_usec));
}
//__device__ double* dev_vector1 = 0;
//__device__ double* dev_vector2 = 0;
//__device__ double* dev_results = 0;
__global__ void device_vector_mult (double* v1, double* v2, double* res) {
// IMPLEMENT ME 6: Multiply the threadIdx.x element of dev_vector1 by the
// corresponding element of dev_vector2, and store in dev_results.
res[threadIdx.x] = 2 * v1[threadIdx.x] * v2[threadIdx.x];
}
__global__ void device_vector_reduce (double* results, int* length) {
int len = *length;
while (len > 1) {
if (threadIdx.x < (len - (len % 2)) / 2) {
results[threadIdx.x] += results[threadIdx.x + (len + (len % 2)) / 2];
}
len = (len + (len % 2)) / 2;
__syncthreads();
}
}
__global__ void device_vector_simpleAdd (double* vec, double* res) {
if (threadIdx.x == 0) {
res[0] = 2;
}
}
int main (int argc, char** argv) {
int sizeOfVector = 100;
if (argc > 1) sizeOfVector = atoi(argv[1]);
// Declare and fill host-side arrays of doubles.
double* vector1 = new double[sizeOfVector];
double* vector2 = new double[sizeOfVector];
double* results = new double[sizeOfVector];
double* gpuresults = new double[sizeOfVector];
double* gpuAddresults = new double[sizeOfVector];
srand(42);
for (int i = 0; i < sizeOfVector; ++i) {
vector1[i] = rand() % 100;
vector2[i] = rand() % 100;
results[i] = 0;
gpuresults[i] = 0;
gpuAddresults[i] = 0;
}
timeval startTime;
timeval interTime;
timeval stopsTime;
gettimeofday(&startTime, NULL);
// Use the CPU for this part.
// IMPLEMENT ME 1: Multiply each element of vector1 by the corresponding
// element in vector2 and store in results.
for (int i = 0; i < sizeOfVector; ++i) {
results[i] = vector1[i] * vector2[i];
}
gettimeofday(&interTime, NULL);
double total = 0;
// IMPLEMENT ME 2: Sum the results array and store the sum in total.
for (int i = 0; i < sizeOfVector; ++i) {
total += results[i];
}
gettimeofday(&stopsTime, NULL);
cout << "Dot product is: " << total << endl;
// IMPLEMENT ME 3: Time the above operations together and separately
// using 'gettimeofday'.
cout << "Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double* dev_vector1 = 0;
double* dev_vector2 = 0;
double* dev_results = 0;
int sizeInBytes = sizeOfVector * sizeof(double);
hipMalloc((void**) &dev_vector1, sizeInBytes);
hipMalloc((void**) &dev_vector2, sizeInBytes);
hipMalloc((void**) &dev_results, sizeInBytes);
hipMemcpy(dev_vector1, vector1, sizeInBytes, hipMemcpyHostToDevice);
hipMemcpy(dev_vector2, vector2, sizeInBytes, hipMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
device_vector_mult<<<1, sizeOfVector>>>(dev_vector1, dev_vector2, dev_results);
double gputotal = 0;
hipMemcpy(gpuresults, dev_results, sizeInBytes, hipMemcpyDeviceToHost);
gettimeofday(&interTime, NULL);
for (int i = 0; i < sizeOfVector; ++i) {
gputotal += gpuresults[i];
}
gettimeofday(&stopsTime, NULL);
cout << "GPU-mult Dot product is: " << gputotal << endl;
cout << "GPU-mult Time for multiplication (seconds): " << timeInSeconds(startTime, interTime) << endl;
cout << "GPU-mult Time for addition (seconds): " << timeInSeconds(interTime, stopsTime) << endl;
cout << "GPU-mult Overall time (seconds): " << timeInSeconds(startTime, stopsTime) << endl;
double * dev_added = 0;
hipMalloc((void**) &dev_added, sizeof(double));
//device_vector_simpleAdd<<<1, sizeOfVector>>>(dev_results, dev_added);
device_vector_reduce<<<1, sizeOfVector>>>(dev_results, &sizeOfVector);
double host_added = 2;
//cudaMemcpy(&host_added, &dev_added[0], sizeof(double), cudaMemcpyDeviceToHost);
hipMemcpy(&host_added, &dev_results[0], sizeof(double), hipMemcpyDeviceToHost);
cout <<"GPU-full Dot product is: " << host_added << endl;
cout << "Size of Vectors is: " << sizeOfVector << endl;
return 0;
}
|
.text
.file "ex1b.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13timeInSecondsR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z13timeInSecondsR7timevalS0_
.p2align 4, 0x90
.type _Z13timeInSecondsR7timevalS0_,@function
_Z13timeInSecondsR7timevalS0_: # @_Z13timeInSecondsR7timevalS0_
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
movq 8(%rsi), %rcx
subq (%rdi), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI0_0(%rip), %xmm1
subq 8(%rdi), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI0_1(%rip), %xmm0
retq
.Lfunc_end0:
.size _Z13timeInSecondsR7timevalS0_, .Lfunc_end0-_Z13timeInSecondsR7timevalS0_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__device_vector_multPdS_S_ # -- Begin function _Z33__device_stub__device_vector_multPdS_S_
.p2align 4, 0x90
.type _Z33__device_stub__device_vector_multPdS_S_,@function
_Z33__device_stub__device_vector_multPdS_S_: # @_Z33__device_stub__device_vector_multPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18device_vector_multPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z33__device_stub__device_vector_multPdS_S_, .Lfunc_end1-_Z33__device_stub__device_vector_multPdS_S_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__device_vector_reducePdPi # -- Begin function _Z35__device_stub__device_vector_reducePdPi
.p2align 4, 0x90
.type _Z35__device_stub__device_vector_reducePdPi,@function
_Z35__device_stub__device_vector_reducePdPi: # @_Z35__device_stub__device_vector_reducePdPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20device_vector_reducePdPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z35__device_stub__device_vector_reducePdPi, .Lfunc_end2-_Z35__device_stub__device_vector_reducePdPi
.cfi_endproc
# -- End function
.globl _Z38__device_stub__device_vector_simpleAddPdS_ # -- Begin function _Z38__device_stub__device_vector_simpleAddPdS_
.p2align 4, 0x90
.type _Z38__device_stub__device_vector_simpleAddPdS_,@function
_Z38__device_stub__device_vector_simpleAddPdS_: # @_Z38__device_stub__device_vector_simpleAddPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23device_vector_simpleAddPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z38__device_stub__device_vector_simpleAddPdS_, .Lfunc_end3-_Z38__device_stub__device_vector_simpleAddPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100, 4(%rsp)
cmpl $2, %edi
jl .LBB4_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%rsp)
.LBB4_2:
movslq 4(%rsp), %rax
leaq (,%rax,8), %rcx
testq %rax, %rax
movq $-1, %rbx
cmovnsq %rcx, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r12
movq %rbx, %rdi
callq _Znam
movq %rax, %r15
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
movq %rbx, %rdi
callq _Znam
movq %rax, %rbx
movl $42, %edi
callq srand
cmpl $0, 4(%rsp)
jle .LBB4_5
# %bb.3: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r12,%r13,8)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r15,%r13,8)
movq $0, (%r14,%r13,8)
movq $0, (%rbx,%r13,8)
incq %r13
movslq 4(%rsp), %rax
cmpq %rax, %r13
jl .LBB4_4
.LBB4_5: # %._crit_edge
leaq 176(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB4_8
# %bb.6: # %.lr.ph117.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_7: # %.lr.ph117
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r15,%rcx,8), %xmm0
movsd %xmm0, (%r14,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_7
.LBB4_8: # %._crit_edge118
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
xorpd %xmm0, %xmm0
testl %eax, %eax
jle .LBB4_9
# %bb.31: # %.lr.ph122.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_32: # %.lr.ph122
# =>This Inner Loop Header: Depth=1
addsd (%r14,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_32
.LBB4_9: # %._crit_edge123
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_12
# %bb.11:
movzbl 67(%r14), %ecx
jmp .LBB4_13
.LBB4_12:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB4_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 160(%rsp), %rax
movq 168(%rsp), %rcx
movq 176(%rsp), %rbp
movq 184(%rsp), %r13
movq %rax, 208(%rsp) # 8-byte Spill
subq %rbp, %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rcx, %rax
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
movq %r13, 200(%rsp) # 8-byte Spill
cmpb $0, 56(%r14)
movq %rbp, 192(%rsp) # 8-byte Spill
je .LBB4_16
# %bb.15:
movzbl 67(%r14), %ecx
jmp .LBB4_17
.LBB4_16:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB4_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 144(%rsp), %r13
movq 152(%rsp), %rbp
movq %r13, %rax
subq 208(%rsp), %rax # 8-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %rbp, %rax
subq 8(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r14)
je .LBB4_20
# %bb.19:
movzbl 67(%r14), %ecx
jmp .LBB4_21
.LBB4_20:
movq %r14, %rdi
movq %rax, 8(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq 8(%rsp), %rax # 8-byte Reload
.LBB4_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq 192(%rsp), %r13 # 8-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 200(%rsp), %rbp # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%r14)
je .LBB4_24
# %bb.23:
movzbl 67(%r14), %ecx
jmp .LBB4_25
.LBB4_24:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB4_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movabsq $4294967296, %r14 # imm = 0x100000000
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, 32(%rsp)
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl 4(%rsp), %eax
shll $3, %eax
movslq %eax, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 176(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %edx
orq %r14, %rdx
leaq 1(%r14), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_27
# %bb.26:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18device_vector_multPdS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_27:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
xorpd %xmm0, %xmm0
testl %eax, %eax
jle .LBB4_28
# %bb.51: # %.lr.ph127.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_52: # %.lr.ph127
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_52
.LBB4_28: # %._crit_edge128
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB4_33
# %bb.30:
movzbl 67(%rbx), %ecx
jmp .LBB4_34
.LBB4_33:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 160(%rsp), %r14
movq 168(%rsp), %r13
movq 176(%rsp), %r12
movq 184(%rsp), %r15
movq %r14, %rax
subq %r12, %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %r13, %rax
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81
cmpb $0, 56(%rbx)
movq %r15, 8(%rsp) # 8-byte Spill
je .LBB4_37
# %bb.36:
movzbl 67(%rbx), %ecx
jmp .LBB4_38
.LBB4_37:
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB4_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit84
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 144(%rsp), %r15
movq 152(%rsp), %rbp
movq %r15, %rax
subq %r14, %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %rbp, %rax
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i86
cmpb $0, 56(%rbx)
je .LBB4_41
# %bb.40:
movzbl 67(%rbx), %ecx
jmp .LBB4_42
.LBB4_41:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit89
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r15
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 8(%rsp), %rbp # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91
cmpb $0, 56(%rbx)
movabsq $4294967296, %r15 # imm = 0x100000000
je .LBB4_45
# %bb.44:
movzbl 67(%rbx), %ecx
jmp .LBB4_46
.LBB4_45:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit94
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movl 4(%rsp), %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_48
# %bb.47:
movq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20device_vector_reducePdPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_48:
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 112(%rsp)
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 112(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i96
cmpb $0, 56(%rbx)
je .LBB4_53
# %bb.50:
movzbl 67(%rbx), %ecx
jmp .LBB4_54
.LBB4_53:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit99
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i101
cmpb $0, 56(%rbx)
je .LBB4_57
# %bb.56:
movzbl 67(%rbx), %ecx
jmp .LBB4_58
.LBB4_57:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit104
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_59:
.cfi_def_cfa_offset 272
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18device_vector_multPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20device_vector_reducePdPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23device_vector_simpleAddPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18device_vector_multPdS_S_,@object # @_Z18device_vector_multPdS_S_
.section .rodata,"a",@progbits
.globl _Z18device_vector_multPdS_S_
.p2align 3, 0x0
_Z18device_vector_multPdS_S_:
.quad _Z33__device_stub__device_vector_multPdS_S_
.size _Z18device_vector_multPdS_S_, 8
.type _Z20device_vector_reducePdPi,@object # @_Z20device_vector_reducePdPi
.globl _Z20device_vector_reducePdPi
.p2align 3, 0x0
_Z20device_vector_reducePdPi:
.quad _Z35__device_stub__device_vector_reducePdPi
.size _Z20device_vector_reducePdPi, 8
.type _Z23device_vector_simpleAddPdS_,@object # @_Z23device_vector_simpleAddPdS_
.globl _Z23device_vector_simpleAddPdS_
.p2align 3, 0x0
_Z23device_vector_simpleAddPdS_:
.quad _Z38__device_stub__device_vector_simpleAddPdS_
.size _Z23device_vector_simpleAddPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Dot product is: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time for multiplication (seconds): "
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time for addition (seconds): "
.size .L.str.2, 36
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Overall time (seconds): "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU-mult Dot product is: "
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU-mult Time for multiplication (seconds): "
.size .L.str.5, 45
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU-mult Time for addition (seconds): "
.size .L.str.6, 45
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU-mult Overall time (seconds): "
.size .L.str.7, 45
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU-full Dot product is: "
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Size of Vectors is: "
.size .L.str.9, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18device_vector_multPdS_S_"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20device_vector_reducePdPi"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z23device_vector_simpleAddPdS_"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__device_vector_multPdS_S_
.addrsig_sym _Z35__device_stub__device_vector_reducePdPi
.addrsig_sym _Z38__device_stub__device_vector_simpleAddPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18device_vector_multPdS_S_
.addrsig_sym _Z20device_vector_reducePdPi
.addrsig_sym _Z23device_vector_simpleAddPdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z23device_vector_simpleAddPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0050*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x40000000 ; /* 0x40000000ff057424 */
/* 0x000fca00078e00ff */
/*0090*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20device_vector_reducePdPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x004fda0003f06270 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0080*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fd200078e0002 */
/*00a0*/ IMAD.WIDE.U32 R2, R9, R4, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fc800078e0004 */
/*00b0*/ SHF.R.U32.HI R4, RZ, 0x1, R0 ; /* 0x00000001ff047819 */
/* 0x000fe40000011600 */
/*00c0*/ LOP3.LUT R5, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100057812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fc60003f06070 */
/*00e0*/ IMAD.IADD R8, R5, 0x1, R0 ; /* 0x0000000105087824 */
/* 0x000fca00078e0200 */
/*00f0*/ LEA.HI R0, R8, R8, RZ, 0x1 ; /* 0x0000000808007211 */
/* 0x000fca00078f08ff */
/*0100*/ @!P0 MOV R5, 0x8 ; /* 0x0000000800058802 */
/* 0x000fe20000000f00 */
/*0110*/ @!P0 LDG.E.64 R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ @!P0 LEA.HI.SX32 R4, R0, R9, 0x1f ; /* 0x0000000900048211 */
/* 0x000fca00078ffaff */
/*0130*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fcc00078e0005 */
/*0140*/ @!P0 LDG.E.64 R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011400 */
/*0160*/ @!P0 DADD R6, R6, R4 ; /* 0x0000000006068229 */
/* 0x004e0e0000000004 */
/*0170*/ @!P0 STG.E.64 [R2.64], R6 ; /* 0x0000000602008986 */
/* 0x0011e8000c101b04 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GT.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fda0003f04270 */
/*01a0*/ @P0 BRA 0xb0 ; /* 0xffffff0000000947 */
/* 0x001fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18device_vector_multPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fc800078e0009 */
/*0050*/ IMAD.WIDE.U32 R6, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x0c0fe400078e0009 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0080*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0009 */
/*0090*/ DADD R4, R2, R2 ; /* 0x0000000002047229 */
/* 0x004ecc0000000002 */
/*00a0*/ DMUL R4, R4, R6 ; /* 0x0000000604047228 */
/* 0x008e0e0000000000 */
/*00b0*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18device_vector_multPdS_S_
.globl _Z18device_vector_multPdS_S_
.p2align 8
.type _Z18device_vector_multPdS_S_,@function
_Z18device_vector_multPdS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[4:5]
global_load_b64 v[2:3], v4, s[6:7]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[0:1], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18device_vector_multPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18device_vector_multPdS_S_, .Lfunc_end0-_Z18device_vector_multPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20device_vector_reducePdPi
.globl _Z20device_vector_reducePdPi
.p2align 8
.type _Z20device_vector_reducePdPi,@function
_Z20device_vector_reducePdPi:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 3, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s3, s0, v1
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s3, s3, s2
s_waitcnt_vscnt null, 0x0
s_lshr_b32 s2, s3, 1
s_cmp_gt_u32 s3, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_lshr_b32 s3, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_and_b32 s3, s2, 1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_2
s_add_i32 s5, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s5, s5, 1
v_add_nc_u32_e32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[3:4], off
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
global_store_b64 v[3:4], v[5:6], off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20device_vector_reducePdPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20device_vector_reducePdPi, .Lfunc_end1-_Z20device_vector_reducePdPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23device_vector_simpleAddPdS_
.globl _Z23device_vector_simpleAddPdS_
.p2align 8
.type _Z23device_vector_simpleAddPdS_,@function
_Z23device_vector_simpleAddPdS_:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 2.0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23device_vector_simpleAddPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z23device_vector_simpleAddPdS_, .Lfunc_end2-_Z23device_vector_simpleAddPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18device_vector_multPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z18device_vector_multPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20device_vector_reducePdPi
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z20device_vector_reducePdPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23device_vector_simpleAddPdS_
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z23device_vector_simpleAddPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00115af4_00000000-6_ex1b.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13timeInSecondsR7timevalS0_
.type _Z13timeInSecondsR7timevalS0_, @function
_Z13timeInSecondsR7timevalS0_:
.LFB3669:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq 8(%rsi), %rax
subq 8(%rdi), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE3669:
.size _Z13timeInSecondsR7timevalS0_, .-_Z13timeInSecondsR7timevalS0_
.globl _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
.type _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_, @function
_Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18device_vector_multPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_, .-_Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
.globl _Z18device_vector_multPdS_S_
.type _Z18device_vector_multPdS_S_, @function
_Z18device_vector_multPdS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z18device_vector_multPdS_S_, .-_Z18device_vector_multPdS_S_
.globl _Z42__device_stub__Z20device_vector_reducePdPiPdPi
.type _Z42__device_stub__Z20device_vector_reducePdPiPdPi, @function
_Z42__device_stub__Z20device_vector_reducePdPiPdPi:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20device_vector_reducePdPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z42__device_stub__Z20device_vector_reducePdPiPdPi, .-_Z42__device_stub__Z20device_vector_reducePdPiPdPi
.globl _Z20device_vector_reducePdPi
.type _Z20device_vector_reducePdPi, @function
_Z20device_vector_reducePdPi:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20device_vector_reducePdPiPdPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z20device_vector_reducePdPi, .-_Z20device_vector_reducePdPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Dot product is: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Time for multiplication (seconds): "
.align 8
.LC5:
.string "Time for addition (seconds): "
.align 8
.LC6:
.string "Overall time (seconds): "
.section .rodata.str1.1
.LC7:
.string "GPU-mult Dot product is: "
.section .rodata.str1.8
.align 8
.LC8:
.string "GPU-mult Time for multiplication (seconds): "
.align 8
.LC9:
.string "GPU-mult Time for addition (seconds): "
.align 8
.LC10:
.string "GPU-mult Overall time (seconds): "
.section .rodata.str1.1
.LC12:
.string "GPU-full Dot product is: "
.LC13:
.string "Size of Vectors is: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movl %edi, %eax
movq %fs:40, %rdx
movq %rdx, 152(%rsp)
xorl %edx, %edx
movl $100, 28(%rsp)
movl $100, %edi
cmpl $1, %eax
jg .L61
.L21:
salq $3, %rdi
call _Znam@PLT
movq %rax, %rbp
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L62
salq $3, %rdi
call _Znam@PLT
movq %rax, %rbx
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L63
salq $3, %rdi
call _Znam@PLT
movq %rax, %r14
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L64
salq $3, %rdi
call _Znam@PLT
movq %rax, %r12
movslq 28(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L65
salq $3, %rdi
call _Znam@PLT
movq %rax, %r15
movl $42, %edi
call srand@PLT
movl $0, %r13d
cmpl $0, 28(%rsp)
jle .L36
.L35:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%rbp,%r13,8)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%r13,8)
movq $0x000000000, (%r14,%r13,8)
movq $0x000000000, (%r12,%r13,8)
movq $0x000000000, (%r15,%r13,8)
addq $1, %r13
cmpl %r13d, 28(%rsp)
jg .L35
.L36:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 28(%rsp), %edx
testl %edx, %edx
jle .L38
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
.L39:
movsd 0(%rbp,%rax), %xmm0
mulsd (%rbx,%rax), %xmm0
movsd %xmm0, (%r14,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L39
.L38:
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 28(%rsp), %edx
testl %edx, %edx
jle .L49
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,8), %rdx
movl $0x000000000, %r14d
.L41:
movq %r14, %xmm1
addsd (%rax), %xmm1
movq %xmm1, %r14
addq $8, %rax
cmpq %rdx, %rax
jne .L41
.L40:
leaq 128(%rsp), %r15
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, (%rsp)
leaq 112(%rsp), %rsi
leaq 96(%rsp), %r14
movq %rsi, 8(%rsp)
movq %r14, %rdi
call _Z13timeInSecondsR7timevalS0_
movq (%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, (%rsp)
movq %r15, %rsi
movq 8(%rsp), %rdi
call _Z13timeInSecondsR7timevalS0_
movq (%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movq %r15, %rsi
movq %r14, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl 28(%rsp), %eax
leal 0(,%rax,8), %r13d
movslq %r13d, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
movl 28(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L42:
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 28(%rsp), %edx
testl %edx, %edx
jle .L50
movq %r12, %rax
movslq %edx, %rdx
leaq (%r12,%rdx,8), %rdx
movl $0x000000000, %ebx
.L44:
movq %rbx, %xmm2
addsd (%rax), %xmm2
movq %xmm2, %rbx
addq $8, %rax
cmpq %rdx, %rax
jne .L44
.L43:
leaq 128(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
leaq 112(%rsp), %r14
leaq 96(%rsp), %r13
movq %r14, %rsi
movq %r13, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq %r12, %rsi
movq %r14, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq %r12, %rsi
movq %r13, %rdi
call _Z13timeInSecondsR7timevalS0_
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl 28(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L45:
movq .LC11(%rip), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 80(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
movslq %eax, %rdi
movabsq $1152921504606846975, %rax
cmpq %rdi, %rax
jnb .L21
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L25
call __stack_chk_fail@PLT
.L25:
call __cxa_throw_bad_array_new_length@PLT
.L62:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L28:
call __cxa_throw_bad_array_new_length@PLT
.L63:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L31:
call __cxa_throw_bad_array_new_length@PLT
.L64:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L34
call __stack_chk_fail@PLT
.L34:
call __cxa_throw_bad_array_new_length@PLT
.L65:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L49:
movl $0x000000000, %r14d
jmp .L40
.L66:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z18device_vector_multPdS_S_PdS_S_
jmp .L42
.L50:
movl $0x000000000, %ebx
jmp .L43
.L67:
leaq 28(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z42__device_stub__Z20device_vector_reducePdPiPdPi
jmp .L45
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_
.type _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_, @function
_Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_:
.LFB3699:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23device_vector_simpleAddPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_, .-_Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_
.globl _Z23device_vector_simpleAddPdS_
.type _Z23device_vector_simpleAddPdS_, @function
_Z23device_vector_simpleAddPdS_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z23device_vector_simpleAddPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z23device_vector_simpleAddPdS_, .-_Z23device_vector_simpleAddPdS_
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z23device_vector_simpleAddPdS_"
.section .rodata.str1.1
.LC15:
.string "_Z20device_vector_reducePdPi"
.LC16:
.string "_Z18device_vector_multPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z23device_vector_simpleAddPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z20device_vector_reducePdPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z18device_vector_multPdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long -1598689907
.long 1051772663
.align 8
.LC11:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "ex1b.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13timeInSecondsR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z13timeInSecondsR7timevalS0_
.p2align 4, 0x90
.type _Z13timeInSecondsR7timevalS0_,@function
_Z13timeInSecondsR7timevalS0_: # @_Z13timeInSecondsR7timevalS0_
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
movq 8(%rsi), %rcx
subq (%rdi), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI0_0(%rip), %xmm1
subq 8(%rdi), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI0_1(%rip), %xmm0
retq
.Lfunc_end0:
.size _Z13timeInSecondsR7timevalS0_, .Lfunc_end0-_Z13timeInSecondsR7timevalS0_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__device_vector_multPdS_S_ # -- Begin function _Z33__device_stub__device_vector_multPdS_S_
.p2align 4, 0x90
.type _Z33__device_stub__device_vector_multPdS_S_,@function
_Z33__device_stub__device_vector_multPdS_S_: # @_Z33__device_stub__device_vector_multPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18device_vector_multPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z33__device_stub__device_vector_multPdS_S_, .Lfunc_end1-_Z33__device_stub__device_vector_multPdS_S_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__device_vector_reducePdPi # -- Begin function _Z35__device_stub__device_vector_reducePdPi
.p2align 4, 0x90
.type _Z35__device_stub__device_vector_reducePdPi,@function
_Z35__device_stub__device_vector_reducePdPi: # @_Z35__device_stub__device_vector_reducePdPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20device_vector_reducePdPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z35__device_stub__device_vector_reducePdPi, .Lfunc_end2-_Z35__device_stub__device_vector_reducePdPi
.cfi_endproc
# -- End function
.globl _Z38__device_stub__device_vector_simpleAddPdS_ # -- Begin function _Z38__device_stub__device_vector_simpleAddPdS_
.p2align 4, 0x90
.type _Z38__device_stub__device_vector_simpleAddPdS_,@function
_Z38__device_stub__device_vector_simpleAddPdS_: # @_Z38__device_stub__device_vector_simpleAddPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23device_vector_simpleAddPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z38__device_stub__device_vector_simpleAddPdS_, .Lfunc_end3-_Z38__device_stub__device_vector_simpleAddPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100, 4(%rsp)
cmpl $2, %edi
jl .LBB4_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%rsp)
.LBB4_2:
movslq 4(%rsp), %rax
leaq (,%rax,8), %rcx
testq %rax, %rax
movq $-1, %rbx
cmovnsq %rcx, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r12
movq %rbx, %rdi
callq _Znam
movq %rax, %r15
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
movq %rbx, %rdi
callq _Znam
movq %rax, %rbx
movl $42, %edi
callq srand
cmpl $0, 4(%rsp)
jle .LBB4_5
# %bb.3: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r12,%r13,8)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r15,%r13,8)
movq $0, (%r14,%r13,8)
movq $0, (%rbx,%r13,8)
incq %r13
movslq 4(%rsp), %rax
cmpq %rax, %r13
jl .LBB4_4
.LBB4_5: # %._crit_edge
leaq 176(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB4_8
# %bb.6: # %.lr.ph117.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_7: # %.lr.ph117
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r15,%rcx,8), %xmm0
movsd %xmm0, (%r14,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_7
.LBB4_8: # %._crit_edge118
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
xorpd %xmm0, %xmm0
testl %eax, %eax
jle .LBB4_9
# %bb.31: # %.lr.ph122.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_32: # %.lr.ph122
# =>This Inner Loop Header: Depth=1
addsd (%r14,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_32
.LBB4_9: # %._crit_edge123
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_12
# %bb.11:
movzbl 67(%r14), %ecx
jmp .LBB4_13
.LBB4_12:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB4_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 160(%rsp), %rax
movq 168(%rsp), %rcx
movq 176(%rsp), %rbp
movq 184(%rsp), %r13
movq %rax, 208(%rsp) # 8-byte Spill
subq %rbp, %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rcx, %rax
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
movq %r13, 200(%rsp) # 8-byte Spill
cmpb $0, 56(%r14)
movq %rbp, 192(%rsp) # 8-byte Spill
je .LBB4_16
# %bb.15:
movzbl 67(%r14), %ecx
jmp .LBB4_17
.LBB4_16:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB4_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 144(%rsp), %r13
movq 152(%rsp), %rbp
movq %r13, %rax
subq 208(%rsp), %rax # 8-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %rbp, %rax
subq 8(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r14)
je .LBB4_20
# %bb.19:
movzbl 67(%r14), %ecx
jmp .LBB4_21
.LBB4_20:
movq %r14, %rdi
movq %rax, 8(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq 8(%rsp), %rax # 8-byte Reload
.LBB4_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq 192(%rsp), %r13 # 8-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 200(%rsp), %rbp # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_59
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%r14)
je .LBB4_24
# %bb.23:
movzbl 67(%r14), %ecx
jmp .LBB4_25
.LBB4_24:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB4_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movabsq $4294967296, %r14 # imm = 0x100000000
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, 32(%rsp)
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl 4(%rsp), %eax
shll $3, %eax
movslq %eax, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 176(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %edx
orq %r14, %rdx
leaq 1(%r14), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_27
# %bb.26:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18device_vector_multPdS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_27:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
xorpd %xmm0, %xmm0
testl %eax, %eax
jle .LBB4_28
# %bb.51: # %.lr.ph127.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_52: # %.lr.ph127
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_52
.LBB4_28: # %._crit_edge128
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB4_33
# %bb.30:
movzbl 67(%rbx), %ecx
jmp .LBB4_34
.LBB4_33:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 160(%rsp), %r14
movq 168(%rsp), %r13
movq 176(%rsp), %r12
movq 184(%rsp), %r15
movq %r14, %rax
subq %r12, %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %r13, %rax
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81
cmpb $0, 56(%rbx)
movq %r15, 8(%rsp) # 8-byte Spill
je .LBB4_37
# %bb.36:
movzbl 67(%rbx), %ecx
jmp .LBB4_38
.LBB4_37:
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB4_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit84
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 144(%rsp), %r15
movq 152(%rsp), %rbp
movq %r15, %rax
subq %r14, %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
movq %rbp, %rax
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i86
cmpb $0, 56(%rbx)
je .LBB4_41
# %bb.40:
movzbl 67(%rbx), %ecx
jmp .LBB4_42
.LBB4_41:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit89
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r15
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 8(%rsp), %rbp # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91
cmpb $0, 56(%rbx)
movabsq $4294967296, %r15 # imm = 0x100000000
je .LBB4_45
# %bb.44:
movzbl 67(%rbx), %ecx
jmp .LBB4_46
.LBB4_45:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit94
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movl 4(%rsp), %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_48
# %bb.47:
movq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20device_vector_reducePdPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_48:
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 112(%rsp)
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 112(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i96
cmpb $0, 56(%rbx)
je .LBB4_53
# %bb.50:
movzbl 67(%rbx), %ecx
jmp .LBB4_54
.LBB4_53:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit99
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_59
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i101
cmpb $0, 56(%rbx)
je .LBB4_57
# %bb.56:
movzbl 67(%rbx), %ecx
jmp .LBB4_58
.LBB4_57:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit104
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_59:
.cfi_def_cfa_offset 272
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18device_vector_multPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20device_vector_reducePdPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23device_vector_simpleAddPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18device_vector_multPdS_S_,@object # @_Z18device_vector_multPdS_S_
.section .rodata,"a",@progbits
.globl _Z18device_vector_multPdS_S_
.p2align 3, 0x0
_Z18device_vector_multPdS_S_:
.quad _Z33__device_stub__device_vector_multPdS_S_
.size _Z18device_vector_multPdS_S_, 8
.type _Z20device_vector_reducePdPi,@object # @_Z20device_vector_reducePdPi
.globl _Z20device_vector_reducePdPi
.p2align 3, 0x0
_Z20device_vector_reducePdPi:
.quad _Z35__device_stub__device_vector_reducePdPi
.size _Z20device_vector_reducePdPi, 8
.type _Z23device_vector_simpleAddPdS_,@object # @_Z23device_vector_simpleAddPdS_
.globl _Z23device_vector_simpleAddPdS_
.p2align 3, 0x0
_Z23device_vector_simpleAddPdS_:
.quad _Z38__device_stub__device_vector_simpleAddPdS_
.size _Z23device_vector_simpleAddPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Dot product is: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time for multiplication (seconds): "
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time for addition (seconds): "
.size .L.str.2, 36
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Overall time (seconds): "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU-mult Dot product is: "
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU-mult Time for multiplication (seconds): "
.size .L.str.5, 45
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU-mult Time for addition (seconds): "
.size .L.str.6, 45
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU-mult Overall time (seconds): "
.size .L.str.7, 45
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU-full Dot product is: "
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Size of Vectors is: "
.size .L.str.9, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18device_vector_multPdS_S_"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20device_vector_reducePdPi"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z23device_vector_simpleAddPdS_"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__device_vector_multPdS_S_
.addrsig_sym _Z35__device_stub__device_vector_reducePdPi
.addrsig_sym _Z38__device_stub__device_vector_simpleAddPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18device_vector_multPdS_S_
.addrsig_sym _Z20device_vector_reducePdPi
.addrsig_sym _Z23device_vector_simpleAddPdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/** Homework 3 question 1 code
*
* \file q1.cu
* \author Jose Carlos Martinez Garcia-Vaso <[email protected]>
* \author Utkarsh Vardan <[email protected]>
*/
#include <cstdio> // standard I/O
#include <string> // strings
#include <fstream> // streams
#include <vector> // std::vector
#include <sstream> // std::stringstream
#include <cuda_runtime.h> // CUDA functions
// Globals
#define DEBUG 0 //! Enable debug messages (0: no log output, 1: non-verbose logs, 2: verbose logs, 3: all logs)
#define INPUT_FILE "inp.txt" //! Input filename
#define OUTPUT_FILE_Q1A "q1a.txt" //! Q1 a output filename
#define OUTPUT_FILE_Q1B "q1b.txt" //! Q1 b output filename
#define EXIT_OK 0 //! Exit code success
#define EXIT_FATAL 1 //! Exit code unrecoverable error
/** Read input from file
*
* This function assumes the file contains a single line, as per the format in
* the README.txt.
*
* \param filename Name of input file to read
* \return Vector containing the input array in the file
*/
std::vector<int> read_input (std::string filename) {
// Create a vector of integers to store the array in file
std::vector<int> v_in;
// Create an input filestream
std::ifstream fin(filename);
// Make sure the file is open
if (!fin.is_open()) {
fprintf(stderr, "ERROR:read_input: Could not open file\n");
exit(EXIT_FATAL);
}
// Helper vars
std::string line;
int val;
// Read the column names
if (fin.good()) {
// Extract the first line in the file
std::getline(fin, line);
// Create a stringstream from line
std::stringstream ss(line);
// Extract each integer
while (ss >> val) {
// Add the current integer to the vector
v_in.push_back(val);
// If the next token is a comma, ignore it and move on
if (ss.peek() == ',') ss.ignore();
}
}
// Close file
fin.close();
return v_in;
}
/** Write formated output to file
*
* This function uses the output format described in the README.txt file. If the
* file already exists, it will be overwritten.
*
* \param filename Name of the output file
* \param v_out Vector to save to file
*/
void write_output (std::string filename, const std::vector<int> &v_out) {
// Create an output filestream object
std::ofstream fout(filename);
// Send v_out vector entries to the stream
for (int i = 0; i < v_out.size(); ++i) {
fout << v_out.at(i);
if(i != v_out.size() - 1) fout << ", "; // No comma at end of line
}
//fout << "\n"; // inp.txt doesn't have a newline at the end of the file
// Close the file
fout.close();
}
/** CUDA kernel for the Hillis-Steele parallel scan min
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void parallelScanMinKernel(int *d_out, int *d_in, int n) {
// Initialize global and thread IDs, and other variables
int gid = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
int val = 0;
// Ensure we only access available array entries
if (gid < n) {
#if DEBUG >= 3
if (tid == 0) {
printf("\t\tIterations:\n\t\t\tBlock %d: d = %d: d_in = [ ",
blockIdx.x, 0);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
for (int d=1; d<n; d=d*2) {
if (gid >= d) {
val = d_in[gid - d];
}
__syncthreads();
if (gid >= d) {
d_in[gid] = d_in[gid] <= val ? d_in[gid] : val;
}
__syncthreads();
#if DEBUG >= 3
if (tid == 0) {
printf("\t\t\tBlock %d: d = %d: d_in = [ ", blockIdx.x, d);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
}
/* The result for a block is in the last thread entry for that block.
* If n is not a multiple of blockDim.x, the result is the entry of
* gid == n-1.
*/
if ((tid == blockDim.x-1 && gid != n-1) || gid == n-1) {
d_out[blockIdx.x] = d_in[gid];
#if DEBUG >= 2
printf("\t\tBlock %d min: d_out[%d] = %d\n",
blockIdx.x, blockIdx.x, d_out[blockIdx.x]);
#endif
}
}
}
/** CUDA kernel to compute array with the last digit of entries in input array
*
* Specifically, compute array d_out such that d_out[i] is the last digit of
* d_in[i] for all i.
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void lastDigitKernel(int *d_out, int *d_in, int n) {
// Initialize global ID
int gid = threadIdx.x + blockDim.x * blockIdx.x;
// Ensure we only access available array entries
if (gid < n) {
// Save last digit to output array
d_out[gid] = d_in[gid] % 10;
#if DEBUG >= 3
printf("\t\t\td_in[%d] = %d\td_out[%d] = %d\n",
gid, d_in[gid], gid, d_out[gid]);
#endif
}
}
/** Q1 a) Compute minA, the minimum value in the input array
*
* This function uses the Hillis-Steele version of parallel scan to find the
* minimum value in the input array. Then, it outputs the result to the
* OUTPUT_FILE_Q1A output file.
*
* This function will only work for problems of size (input array size)
* (cudaDeviceProp.maxThreadsPerBlock)^2. For example, if we have a
* cudaDeviceProp.maxThreadsPerBlock = 1024 (a normal value for current Nvidia
* GPUs), the max problem size is N = 1024^2 = 1,048,576. Since the professor
* said the max graded size should be 10^6, this restriction sufices.
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1a (const std::vector<int> &v_in, cudaDeviceProp *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_intermediate, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = sizeof(int); // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
cudaMalloc((void **) &d_in, d_in_size);
cudaMalloc((void **) &d_intermediate, d_in_size); // overallocated
cudaMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
cudaMemcpy(d_in, &v_in[0], d_in_size, cudaMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("\tFinding minimum entry in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
cudaEventRecord(start, 0);
#endif
// Launch the kernel to find min
parallelScanMinKernel<<<blocks_per_grid, threads_per_block>>>
(d_intermediate, d_in, N);
// Make sure all the blocks finish executing
cudaDeviceSynchronize();
cudaDeviceSynchronize();
// If there are more than one block, we need to repeat the process with their results
if (blocks_per_grid > 1) {
#if DEBUG >=2
// Copy array to host
int *a_out;
a_out = (int*) malloc(d_in_size);
cudaMemcpy(a_out, d_intermediate, d_in_size, cudaMemcpyDeviceToHost);
printf("\tBlock results: d_intermediate = [ ");
for (int i=0; i<blocks_per_grid; ++i) {
if (i == blocks_per_grid-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
free(a_out);
#endif
#if DEBUG >= 2
printf("\tThreads per block: %d\n", blocks_per_grid);
printf("\tBlocks per grid: %d\n", 1);
printf("\tRunning kernel...\n");
#endif
// Fill one block with the results from the other blocks
parallelScanMinKernel<<<1, blocks_per_grid>>>
(d_out, d_intermediate, blocks_per_grid);
}
#if DEBUG
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the min result from GPU
int a_out;
if (blocks_per_grid > 1) {
cudaMemcpy(&a_out, d_out, d_out_size, cudaMemcpyDeviceToHost);
} else {
cudaMemcpy(&a_out, d_intermediate, d_out_size, cudaMemcpyDeviceToHost);
}
#if DEBUG >= 2
printf("\ta_out: %d\n", a_out);
#endif
// Copy result to output vector
std::vector<int> v_out (&a_out, &a_out + 1);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
// Write output to file
write_output(OUTPUT_FILE_Q1A, v_out);
}
/** Q1 b) Compute an array B such that B[i] is the last digit of A[i] for all i
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1b (const std::vector<int> &v_in, cudaDeviceProp *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = d_in_size; // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
/*
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
*/
cudaMalloc((void **) &d_in, d_in_size);
cudaMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
cudaMemcpy(d_in, &v_in[0], d_in_size, cudaMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("\tFinding last digit for all entries in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
cudaEventRecord(start, 0);
#endif
#if DEBUG >= 3
printf("\t\tIterations:\n");
#endif
// Launch the kernel to find min
lastDigitKernel<<<blocks_per_grid, threads_per_block>>>
(d_out, d_in, N);
// Make sure all the blocks finish executing
cudaDeviceSynchronize();
cudaDeviceSynchronize();
#if DEBUG
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the result from GPU
int *a_out;
a_out = (int*) malloc(d_out_size);
cudaMemcpy(a_out, d_out, d_out_size, cudaMemcpyDeviceToHost);
#if DEBUG >= 2
printf("\ta_out = [ ");
for (int i=0; i<N; ++i) {
if (i == N-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
#endif
// Copy resulting array to output vector
std::vector<int> v_out (a_out, a_out + N);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
cudaFree(d_in);
cudaFree(d_out);
// Free host memory
free(a_out);
// Save output to file
write_output(OUTPUT_FILE_Q1B, v_out);
}
/** Main
*
* Set up CUDA device, read input file, and run Q1a and Q1b.
*
* \param argc Number of command-line arguments
* \param argv Array of command-line arguments
* \return Program return code
*/
int main (int argc, char **argv) {
#if DEBUG
std::printf("Executing main...\n");
#endif
std::vector<int> v_in;
int device_count;
int dev = 0;
cudaDeviceProp dev_props;
#if DEBUG
printf("Detecting CUDA devices...\n");
#endif
// Check there are CUDA devices available
cudaGetDeviceCount(&device_count);
if (device_count == 0) {
fprintf(stderr, "ERROR:main: no CUDA devices found\n");
exit(EXIT_FATAL);
}
// Use device 0
cudaSetDevice(dev);
if (cudaGetDeviceProperties(&dev_props, dev) == 0) {
#if DEBUG
printf("Using device:\n"
"\tID: %d\n"
"\tName: %s\n"
"\tGlobal mem: %d B\n"
"\tMax threads per block: %d\n"
"\tCompute: v%d.%d\n"
"\tClock: %d kHz\n",
dev,
dev_props.name,
(int)dev_props.totalGlobalMem,
(int)dev_props.maxThreadsPerBlock,
(int)dev_props.major,
(int)dev_props.minor,
(int)dev_props.clockRate);
#endif
} else {
fprintf(stderr, "ERROR:main: could not find CUDA device information\n");
exit(EXIT_FATAL);
}
#if DEBUG
std::printf("Reading input array...\n");
#endif
// Read input array
v_in = read_input(INPUT_FILE);
#if DEBUG >= 2
printf("\tInput array = [ ");
for (int i=0; i<v_in.size(); ++i) {
if (i == v_in.size()-1) {
printf("%d ]\n", v_in[i]);
} else {
printf("%d, ", v_in[i]);
}
}
#endif
#if DEBUG
std::printf("Running Q1 a...\n");
#endif
// Problem q1 a
q1a(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Running Q1 b...\n");
#endif
// Problem q1 b
q1b(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Done\n");
#endif
return 0;
}
|
code for sm_80
Function : _Z15lastDigitKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.HI R0, R2, 0x66666667, RZ ; /* 0x6666666702007827 */
/* 0x004fca00078e02ff */
/*00b0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*00c0*/ LEA.HI.SX32 R7, R0, R5, 0x1e ; /* 0x0000000500077211 */
/* 0x000fe200078ff2ff */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R7, R7, -0xa, R2 ; /* 0xfffffff607077824 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21parallelScanMinKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R8, c[0x0][0x0], R11 ; /* 0x0000000008007a24 */
/* 0x001fca00078e020b */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc60000000a00 */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fcc0003f06270 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fce00078e0203 */
/*00b0*/ @!P0 BRA 0x1b0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fc80000000f00 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 MOV R5, 0x4 ; /* 0x0000000400050802 */
/* 0x000fe20000000f00 */
/*0100*/ @P0 IMAD.IADD R4, R0, 0x1, -R7 ; /* 0x0000000100040824 */
/* 0x000fc800078e0a07 */
/*0110*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004040625 */
/* 0x000fca00078e0205 */
/*0120*/ @P0 LDG.E R6, [R4.64] ; /* 0x0000000804060981 */
/* 0x000ea8000c1e1900 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @P0 LDG.E R9, [R2.64] ; /* 0x0000000802090981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0160*/ @P0 IMNMX R9, R6, R9, PT ; /* 0x0000000906090217 */
/* 0x004fca0003800200 */
/*0170*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0001e8000c101908 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06270 */
/*01a0*/ @!P0 BRA 0xe0 ; /* 0xffffff3000008947 */
/* 0x001fea000383ffff */
/*01b0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*01c0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe40000000800 */
/*01d0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*01e0*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*01f0*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000fffe13f */
/*0200*/ ISETP.NE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe4000bf05270 */
/*0210*/ ISETP.NE.AND P1, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fda000bf25270 */
/*0220*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*0230*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*0240*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0250*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0005 */
/*0260*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101908 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/** Homework 3 question 1 code
*
* \file q1.cu
* \author Jose Carlos Martinez Garcia-Vaso <[email protected]>
* \author Utkarsh Vardan <[email protected]>
*/
#include <cstdio> // standard I/O
#include <string> // strings
#include <fstream> // streams
#include <vector> // std::vector
#include <sstream> // std::stringstream
#include <cuda_runtime.h> // CUDA functions
// Globals
#define DEBUG 0 //! Enable debug messages (0: no log output, 1: non-verbose logs, 2: verbose logs, 3: all logs)
#define INPUT_FILE "inp.txt" //! Input filename
#define OUTPUT_FILE_Q1A "q1a.txt" //! Q1 a output filename
#define OUTPUT_FILE_Q1B "q1b.txt" //! Q1 b output filename
#define EXIT_OK 0 //! Exit code success
#define EXIT_FATAL 1 //! Exit code unrecoverable error
/** Read input from file
*
* This function assumes the file contains a single line, as per the format in
* the README.txt.
*
* \param filename Name of input file to read
* \return Vector containing the input array in the file
*/
std::vector<int> read_input (std::string filename) {
// Create a vector of integers to store the array in file
std::vector<int> v_in;
// Create an input filestream
std::ifstream fin(filename);
// Make sure the file is open
if (!fin.is_open()) {
fprintf(stderr, "ERROR:read_input: Could not open file\n");
exit(EXIT_FATAL);
}
// Helper vars
std::string line;
int val;
// Read the column names
if (fin.good()) {
// Extract the first line in the file
std::getline(fin, line);
// Create a stringstream from line
std::stringstream ss(line);
// Extract each integer
while (ss >> val) {
// Add the current integer to the vector
v_in.push_back(val);
// If the next token is a comma, ignore it and move on
if (ss.peek() == ',') ss.ignore();
}
}
// Close file
fin.close();
return v_in;
}
/** Write formated output to file
*
* This function uses the output format described in the README.txt file. If the
* file already exists, it will be overwritten.
*
* \param filename Name of the output file
* \param v_out Vector to save to file
*/
void write_output (std::string filename, const std::vector<int> &v_out) {
// Create an output filestream object
std::ofstream fout(filename);
// Send v_out vector entries to the stream
for (int i = 0; i < v_out.size(); ++i) {
fout << v_out.at(i);
if(i != v_out.size() - 1) fout << ", "; // No comma at end of line
}
//fout << "\n"; // inp.txt doesn't have a newline at the end of the file
// Close the file
fout.close();
}
/** CUDA kernel for the Hillis-Steele parallel scan min
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void parallelScanMinKernel(int *d_out, int *d_in, int n) {
// Initialize global and thread IDs, and other variables
int gid = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
int val = 0;
// Ensure we only access available array entries
if (gid < n) {
#if DEBUG >= 3
if (tid == 0) {
printf("\t\tIterations:\n\t\t\tBlock %d: d = %d: d_in = [ ",
blockIdx.x, 0);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
for (int d=1; d<n; d=d*2) {
if (gid >= d) {
val = d_in[gid - d];
}
__syncthreads();
if (gid >= d) {
d_in[gid] = d_in[gid] <= val ? d_in[gid] : val;
}
__syncthreads();
#if DEBUG >= 3
if (tid == 0) {
printf("\t\t\tBlock %d: d = %d: d_in = [ ", blockIdx.x, d);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
}
/* The result for a block is in the last thread entry for that block.
* If n is not a multiple of blockDim.x, the result is the entry of
* gid == n-1.
*/
if ((tid == blockDim.x-1 && gid != n-1) || gid == n-1) {
d_out[blockIdx.x] = d_in[gid];
#if DEBUG >= 2
printf("\t\tBlock %d min: d_out[%d] = %d\n",
blockIdx.x, blockIdx.x, d_out[blockIdx.x]);
#endif
}
}
}
/** CUDA kernel to compute array with the last digit of entries in input array
*
* Specifically, compute array d_out such that d_out[i] is the last digit of
* d_in[i] for all i.
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void lastDigitKernel(int *d_out, int *d_in, int n) {
// Initialize global ID
int gid = threadIdx.x + blockDim.x * blockIdx.x;
// Ensure we only access available array entries
if (gid < n) {
// Save last digit to output array
d_out[gid] = d_in[gid] % 10;
#if DEBUG >= 3
printf("\t\t\td_in[%d] = %d\td_out[%d] = %d\n",
gid, d_in[gid], gid, d_out[gid]);
#endif
}
}
/** Q1 a) Compute minA, the minimum value in the input array
*
* This function uses the Hillis-Steele version of parallel scan to find the
* minimum value in the input array. Then, it outputs the result to the
* OUTPUT_FILE_Q1A output file.
*
* This function will only work for problems of size (input array size)
* (cudaDeviceProp.maxThreadsPerBlock)^2. For example, if we have a
* cudaDeviceProp.maxThreadsPerBlock = 1024 (a normal value for current Nvidia
* GPUs), the max problem size is N = 1024^2 = 1,048,576. Since the professor
* said the max graded size should be 10^6, this restriction sufices.
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1a (const std::vector<int> &v_in, cudaDeviceProp *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_intermediate, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = sizeof(int); // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
cudaMalloc((void **) &d_in, d_in_size);
cudaMalloc((void **) &d_intermediate, d_in_size); // overallocated
cudaMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
cudaMemcpy(d_in, &v_in[0], d_in_size, cudaMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("\tFinding minimum entry in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
cudaEventRecord(start, 0);
#endif
// Launch the kernel to find min
parallelScanMinKernel<<<blocks_per_grid, threads_per_block>>>
(d_intermediate, d_in, N);
// Make sure all the blocks finish executing
cudaDeviceSynchronize();
cudaDeviceSynchronize();
// If there are more than one block, we need to repeat the process with their results
if (blocks_per_grid > 1) {
#if DEBUG >=2
// Copy array to host
int *a_out;
a_out = (int*) malloc(d_in_size);
cudaMemcpy(a_out, d_intermediate, d_in_size, cudaMemcpyDeviceToHost);
printf("\tBlock results: d_intermediate = [ ");
for (int i=0; i<blocks_per_grid; ++i) {
if (i == blocks_per_grid-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
free(a_out);
#endif
#if DEBUG >= 2
printf("\tThreads per block: %d\n", blocks_per_grid);
printf("\tBlocks per grid: %d\n", 1);
printf("\tRunning kernel...\n");
#endif
// Fill one block with the results from the other blocks
parallelScanMinKernel<<<1, blocks_per_grid>>>
(d_out, d_intermediate, blocks_per_grid);
}
#if DEBUG
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the min result from GPU
int a_out;
if (blocks_per_grid > 1) {
cudaMemcpy(&a_out, d_out, d_out_size, cudaMemcpyDeviceToHost);
} else {
cudaMemcpy(&a_out, d_intermediate, d_out_size, cudaMemcpyDeviceToHost);
}
#if DEBUG >= 2
printf("\ta_out: %d\n", a_out);
#endif
// Copy result to output vector
std::vector<int> v_out (&a_out, &a_out + 1);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
// Write output to file
write_output(OUTPUT_FILE_Q1A, v_out);
}
/** Q1 b) Compute an array B such that B[i] is the last digit of A[i] for all i
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1b (const std::vector<int> &v_in, cudaDeviceProp *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = d_in_size; // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
/*
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
*/
cudaMalloc((void **) &d_in, d_in_size);
cudaMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
cudaMemcpy(d_in, &v_in[0], d_in_size, cudaMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("\tFinding last digit for all entries in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
cudaEventRecord(start, 0);
#endif
#if DEBUG >= 3
printf("\t\tIterations:\n");
#endif
// Launch the kernel to find min
lastDigitKernel<<<blocks_per_grid, threads_per_block>>>
(d_out, d_in, N);
// Make sure all the blocks finish executing
cudaDeviceSynchronize();
cudaDeviceSynchronize();
#if DEBUG
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the result from GPU
int *a_out;
a_out = (int*) malloc(d_out_size);
cudaMemcpy(a_out, d_out, d_out_size, cudaMemcpyDeviceToHost);
#if DEBUG >= 2
printf("\ta_out = [ ");
for (int i=0; i<N; ++i) {
if (i == N-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
#endif
// Copy resulting array to output vector
std::vector<int> v_out (a_out, a_out + N);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
cudaFree(d_in);
cudaFree(d_out);
// Free host memory
free(a_out);
// Save output to file
write_output(OUTPUT_FILE_Q1B, v_out);
}
/** Main
*
* Set up CUDA device, read input file, and run Q1a and Q1b.
*
* \param argc Number of command-line arguments
* \param argv Array of command-line arguments
* \return Program return code
*/
int main (int argc, char **argv) {
#if DEBUG
std::printf("Executing main...\n");
#endif
std::vector<int> v_in;
int device_count;
int dev = 0;
cudaDeviceProp dev_props;
#if DEBUG
printf("Detecting CUDA devices...\n");
#endif
// Check there are CUDA devices available
cudaGetDeviceCount(&device_count);
if (device_count == 0) {
fprintf(stderr, "ERROR:main: no CUDA devices found\n");
exit(EXIT_FATAL);
}
// Use device 0
cudaSetDevice(dev);
if (cudaGetDeviceProperties(&dev_props, dev) == 0) {
#if DEBUG
printf("Using device:\n"
"\tID: %d\n"
"\tName: %s\n"
"\tGlobal mem: %d B\n"
"\tMax threads per block: %d\n"
"\tCompute: v%d.%d\n"
"\tClock: %d kHz\n",
dev,
dev_props.name,
(int)dev_props.totalGlobalMem,
(int)dev_props.maxThreadsPerBlock,
(int)dev_props.major,
(int)dev_props.minor,
(int)dev_props.clockRate);
#endif
} else {
fprintf(stderr, "ERROR:main: could not find CUDA device information\n");
exit(EXIT_FATAL);
}
#if DEBUG
std::printf("Reading input array...\n");
#endif
// Read input array
v_in = read_input(INPUT_FILE);
#if DEBUG >= 2
printf("\tInput array = [ ");
for (int i=0; i<v_in.size(); ++i) {
if (i == v_in.size()-1) {
printf("%d ]\n", v_in[i]);
} else {
printf("%d, ", v_in[i]);
}
}
#endif
#if DEBUG
std::printf("Running Q1 a...\n");
#endif
// Problem q1 a
q1a(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Running Q1 b...\n");
#endif
// Problem q1 b
q1b(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Done\n");
#endif
return 0;
}
|
/** Homework 3 question 1 code
*
* \file q1.cu
* \author Jose Carlos Martinez Garcia-Vaso <[email protected]>
* \author Utkarsh Vardan <[email protected]>
*/
#include <cstdio> // standard I/O
#include <string> // strings
#include <fstream> // streams
#include <vector> // std::vector
#include <sstream> // std::stringstream
#include <hip/hip_runtime.h> // CUDA functions
// Globals
#define DEBUG 0 //! Enable debug messages (0: no log output, 1: non-verbose logs, 2: verbose logs, 3: all logs)
#define INPUT_FILE "inp.txt" //! Input filename
#define OUTPUT_FILE_Q1A "q1a.txt" //! Q1 a output filename
#define OUTPUT_FILE_Q1B "q1b.txt" //! Q1 b output filename
#define EXIT_OK 0 //! Exit code success
#define EXIT_FATAL 1 //! Exit code unrecoverable error
/** Read input from file
*
* This function assumes the file contains a single line, as per the format in
* the README.txt.
*
* \param filename Name of input file to read
* \return Vector containing the input array in the file
*/
std::vector<int> read_input (std::string filename) {
// Create a vector of integers to store the array in file
std::vector<int> v_in;
// Create an input filestream
std::ifstream fin(filename);
// Make sure the file is open
if (!fin.is_open()) {
fprintf(stderr, "ERROR:read_input: Could not open file\n");
exit(EXIT_FATAL);
}
// Helper vars
std::string line;
int val;
// Read the column names
if (fin.good()) {
// Extract the first line in the file
std::getline(fin, line);
// Create a stringstream from line
std::stringstream ss(line);
// Extract each integer
while (ss >> val) {
// Add the current integer to the vector
v_in.push_back(val);
// If the next token is a comma, ignore it and move on
if (ss.peek() == ',') ss.ignore();
}
}
// Close file
fin.close();
return v_in;
}
/** Write formated output to file
*
* This function uses the output format described in the README.txt file. If the
* file already exists, it will be overwritten.
*
* \param filename Name of the output file
* \param v_out Vector to save to file
*/
void write_output (std::string filename, const std::vector<int> &v_out) {
// Create an output filestream object
std::ofstream fout(filename);
// Send v_out vector entries to the stream
for (int i = 0; i < v_out.size(); ++i) {
fout << v_out.at(i);
if(i != v_out.size() - 1) fout << ", "; // No comma at end of line
}
//fout << "\n"; // inp.txt doesn't have a newline at the end of the file
// Close the file
fout.close();
}
/** CUDA kernel for the Hillis-Steele parallel scan min
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void parallelScanMinKernel(int *d_out, int *d_in, int n) {
// Initialize global and thread IDs, and other variables
int gid = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
int val = 0;
// Ensure we only access available array entries
if (gid < n) {
#if DEBUG >= 3
if (tid == 0) {
printf("\t\tIterations:\n\t\t\tBlock %d: d = %d: d_in = [ ",
blockIdx.x, 0);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
for (int d=1; d<n; d=d*2) {
if (gid >= d) {
val = d_in[gid - d];
}
__syncthreads();
if (gid >= d) {
d_in[gid] = d_in[gid] <= val ? d_in[gid] : val;
}
__syncthreads();
#if DEBUG >= 3
if (tid == 0) {
printf("\t\t\tBlock %d: d = %d: d_in = [ ", blockIdx.x, d);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
}
/* The result for a block is in the last thread entry for that block.
* If n is not a multiple of blockDim.x, the result is the entry of
* gid == n-1.
*/
if ((tid == blockDim.x-1 && gid != n-1) || gid == n-1) {
d_out[blockIdx.x] = d_in[gid];
#if DEBUG >= 2
printf("\t\tBlock %d min: d_out[%d] = %d\n",
blockIdx.x, blockIdx.x, d_out[blockIdx.x]);
#endif
}
}
}
/** CUDA kernel to compute array with the last digit of entries in input array
*
* Specifically, compute array d_out such that d_out[i] is the last digit of
* d_in[i] for all i.
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void lastDigitKernel(int *d_out, int *d_in, int n) {
// Initialize global ID
int gid = threadIdx.x + blockDim.x * blockIdx.x;
// Ensure we only access available array entries
if (gid < n) {
// Save last digit to output array
d_out[gid] = d_in[gid] % 10;
#if DEBUG >= 3
printf("\t\t\td_in[%d] = %d\td_out[%d] = %d\n",
gid, d_in[gid], gid, d_out[gid]);
#endif
}
}
/** Q1 a) Compute minA, the minimum value in the input array
*
* This function uses the Hillis-Steele version of parallel scan to find the
* minimum value in the input array. Then, it outputs the result to the
* OUTPUT_FILE_Q1A output file.
*
* This function will only work for problems of size (input array size)
* (cudaDeviceProp.maxThreadsPerBlock)^2. For example, if we have a
* cudaDeviceProp.maxThreadsPerBlock = 1024 (a normal value for current Nvidia
* GPUs), the max problem size is N = 1024^2 = 1,048,576. Since the professor
* said the max graded size should be 10^6, this restriction sufices.
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1a (const std::vector<int> &v_in, hipDeviceProp_t *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_intermediate, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = sizeof(int); // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
hipMalloc((void **) &d_in, d_in_size);
hipMalloc((void **) &d_intermediate, d_in_size); // overallocated
hipMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
hipMemcpy(d_in, &v_in[0], d_in_size, hipMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("\tFinding minimum entry in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
hipEventRecord(start, 0);
#endif
// Launch the kernel to find min
parallelScanMinKernel<<<blocks_per_grid, threads_per_block>>>
(d_intermediate, d_in, N);
// Make sure all the blocks finish executing
hipDeviceSynchronize();
hipDeviceSynchronize();
// If there are more than one block, we need to repeat the process with their results
if (blocks_per_grid > 1) {
#if DEBUG >=2
// Copy array to host
int *a_out;
a_out = (int*) malloc(d_in_size);
hipMemcpy(a_out, d_intermediate, d_in_size, hipMemcpyDeviceToHost);
printf("\tBlock results: d_intermediate = [ ");
for (int i=0; i<blocks_per_grid; ++i) {
if (i == blocks_per_grid-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
free(a_out);
#endif
#if DEBUG >= 2
printf("\tThreads per block: %d\n", blocks_per_grid);
printf("\tBlocks per grid: %d\n", 1);
printf("\tRunning kernel...\n");
#endif
// Fill one block with the results from the other blocks
parallelScanMinKernel<<<1, blocks_per_grid>>>
(d_out, d_intermediate, blocks_per_grid);
}
#if DEBUG
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the min result from GPU
int a_out;
if (blocks_per_grid > 1) {
hipMemcpy(&a_out, d_out, d_out_size, hipMemcpyDeviceToHost);
} else {
hipMemcpy(&a_out, d_intermediate, d_out_size, hipMemcpyDeviceToHost);
}
#if DEBUG >= 2
printf("\ta_out: %d\n", a_out);
#endif
// Copy result to output vector
std::vector<int> v_out (&a_out, &a_out + 1);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
// Write output to file
write_output(OUTPUT_FILE_Q1A, v_out);
}
/** Q1 b) Compute an array B such that B[i] is the last digit of A[i] for all i
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1b (const std::vector<int> &v_in, hipDeviceProp_t *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = d_in_size; // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
/*
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
*/
hipMalloc((void **) &d_in, d_in_size);
hipMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
hipMemcpy(d_in, &v_in[0], d_in_size, hipMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("\tFinding last digit for all entries in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
hipEventRecord(start, 0);
#endif
#if DEBUG >= 3
printf("\t\tIterations:\n");
#endif
// Launch the kernel to find min
lastDigitKernel<<<blocks_per_grid, threads_per_block>>>
(d_out, d_in, N);
// Make sure all the blocks finish executing
hipDeviceSynchronize();
hipDeviceSynchronize();
#if DEBUG
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the result from GPU
int *a_out;
a_out = (int*) malloc(d_out_size);
hipMemcpy(a_out, d_out, d_out_size, hipMemcpyDeviceToHost);
#if DEBUG >= 2
printf("\ta_out = [ ");
for (int i=0; i<N; ++i) {
if (i == N-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
#endif
// Copy resulting array to output vector
std::vector<int> v_out (a_out, a_out + N);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
hipFree(d_in);
hipFree(d_out);
// Free host memory
free(a_out);
// Save output to file
write_output(OUTPUT_FILE_Q1B, v_out);
}
/** Main
*
* Set up CUDA device, read input file, and run Q1a and Q1b.
*
* \param argc Number of command-line arguments
* \param argv Array of command-line arguments
* \return Program return code
*/
int main (int argc, char **argv) {
#if DEBUG
std::printf("Executing main...\n");
#endif
std::vector<int> v_in;
int device_count;
int dev = 0;
hipDeviceProp_t dev_props;
#if DEBUG
printf("Detecting CUDA devices...\n");
#endif
// Check there are CUDA devices available
hipGetDeviceCount(&device_count);
if (device_count == 0) {
fprintf(stderr, "ERROR:main: no CUDA devices found\n");
exit(EXIT_FATAL);
}
// Use device 0
hipSetDevice(dev);
if (hipGetDeviceProperties(&dev_props, dev) == 0) {
#if DEBUG
printf("Using device:\n"
"\tID: %d\n"
"\tName: %s\n"
"\tGlobal mem: %d B\n"
"\tMax threads per block: %d\n"
"\tCompute: v%d.%d\n"
"\tClock: %d kHz\n",
dev,
dev_props.name,
(int)dev_props.totalGlobalMem,
(int)dev_props.maxThreadsPerBlock,
(int)dev_props.major,
(int)dev_props.minor,
(int)dev_props.clockRate);
#endif
} else {
fprintf(stderr, "ERROR:main: could not find CUDA device information\n");
exit(EXIT_FATAL);
}
#if DEBUG
std::printf("Reading input array...\n");
#endif
// Read input array
v_in = read_input(INPUT_FILE);
#if DEBUG >= 2
printf("\tInput array = [ ");
for (int i=0; i<v_in.size(); ++i) {
if (i == v_in.size()-1) {
printf("%d ]\n", v_in[i]);
} else {
printf("%d, ", v_in[i]);
}
}
#endif
#if DEBUG
std::printf("Running Q1 a...\n");
#endif
// Problem q1 a
q1a(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Running Q1 b...\n");
#endif
// Problem q1 b
q1b(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Done\n");
#endif
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/** Homework 3 question 1 code
*
* \file q1.cu
* \author Jose Carlos Martinez Garcia-Vaso <[email protected]>
* \author Utkarsh Vardan <[email protected]>
*/
#include <cstdio> // standard I/O
#include <string> // strings
#include <fstream> // streams
#include <vector> // std::vector
#include <sstream> // std::stringstream
#include <hip/hip_runtime.h> // CUDA functions
// Globals
#define DEBUG 0 //! Enable debug messages (0: no log output, 1: non-verbose logs, 2: verbose logs, 3: all logs)
#define INPUT_FILE "inp.txt" //! Input filename
#define OUTPUT_FILE_Q1A "q1a.txt" //! Q1 a output filename
#define OUTPUT_FILE_Q1B "q1b.txt" //! Q1 b output filename
#define EXIT_OK 0 //! Exit code success
#define EXIT_FATAL 1 //! Exit code unrecoverable error
/** Read input from file
*
* This function assumes the file contains a single line, as per the format in
* the README.txt.
*
* \param filename Name of input file to read
* \return Vector containing the input array in the file
*/
std::vector<int> read_input (std::string filename) {
// Create a vector of integers to store the array in file
std::vector<int> v_in;
// Create an input filestream
std::ifstream fin(filename);
// Make sure the file is open
if (!fin.is_open()) {
fprintf(stderr, "ERROR:read_input: Could not open file\n");
exit(EXIT_FATAL);
}
// Helper vars
std::string line;
int val;
// Read the column names
if (fin.good()) {
// Extract the first line in the file
std::getline(fin, line);
// Create a stringstream from line
std::stringstream ss(line);
// Extract each integer
while (ss >> val) {
// Add the current integer to the vector
v_in.push_back(val);
// If the next token is a comma, ignore it and move on
if (ss.peek() == ',') ss.ignore();
}
}
// Close file
fin.close();
return v_in;
}
/** Write formated output to file
*
* This function uses the output format described in the README.txt file. If the
* file already exists, it will be overwritten.
*
* \param filename Name of the output file
* \param v_out Vector to save to file
*/
void write_output (std::string filename, const std::vector<int> &v_out) {
// Create an output filestream object
std::ofstream fout(filename);
// Send v_out vector entries to the stream
for (int i = 0; i < v_out.size(); ++i) {
fout << v_out.at(i);
if(i != v_out.size() - 1) fout << ", "; // No comma at end of line
}
//fout << "\n"; // inp.txt doesn't have a newline at the end of the file
// Close the file
fout.close();
}
/** CUDA kernel for the Hillis-Steele parallel scan min
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void parallelScanMinKernel(int *d_out, int *d_in, int n) {
// Initialize global and thread IDs, and other variables
int gid = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
int val = 0;
// Ensure we only access available array entries
if (gid < n) {
#if DEBUG >= 3
if (tid == 0) {
printf("\t\tIterations:\n\t\t\tBlock %d: d = %d: d_in = [ ",
blockIdx.x, 0);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
for (int d=1; d<n; d=d*2) {
if (gid >= d) {
val = d_in[gid - d];
}
__syncthreads();
if (gid >= d) {
d_in[gid] = d_in[gid] <= val ? d_in[gid] : val;
}
__syncthreads();
#if DEBUG >= 3
if (tid == 0) {
printf("\t\t\tBlock %d: d = %d: d_in = [ ", blockIdx.x, d);
for (int i=0; i<n; ++i) {
if (i == n-1) {
printf("%d ]\n", d_in[i]);
} else {
printf("%d, ", d_in[i]);
}
}
}
#endif
}
/* The result for a block is in the last thread entry for that block.
* If n is not a multiple of blockDim.x, the result is the entry of
* gid == n-1.
*/
if ((tid == blockDim.x-1 && gid != n-1) || gid == n-1) {
d_out[blockIdx.x] = d_in[gid];
#if DEBUG >= 2
printf("\t\tBlock %d min: d_out[%d] = %d\n",
blockIdx.x, blockIdx.x, d_out[blockIdx.x]);
#endif
}
}
}
/** CUDA kernel to compute array with the last digit of entries in input array
*
* Specifically, compute array d_out such that d_out[i] is the last digit of
* d_in[i] for all i.
*
* \param d_out Pointer to output array in global memory
* \param d_in Pointer to input array in global memory
* \param n Size of the problem (input array size)
*/
__global__ void lastDigitKernel(int *d_out, int *d_in, int n) {
// Initialize global ID
int gid = threadIdx.x + blockDim.x * blockIdx.x;
// Ensure we only access available array entries
if (gid < n) {
// Save last digit to output array
d_out[gid] = d_in[gid] % 10;
#if DEBUG >= 3
printf("\t\t\td_in[%d] = %d\td_out[%d] = %d\n",
gid, d_in[gid], gid, d_out[gid]);
#endif
}
}
/** Q1 a) Compute minA, the minimum value in the input array
*
* This function uses the Hillis-Steele version of parallel scan to find the
* minimum value in the input array. Then, it outputs the result to the
* OUTPUT_FILE_Q1A output file.
*
* This function will only work for problems of size (input array size)
* (cudaDeviceProp.maxThreadsPerBlock)^2. For example, if we have a
* cudaDeviceProp.maxThreadsPerBlock = 1024 (a normal value for current Nvidia
* GPUs), the max problem size is N = 1024^2 = 1,048,576. Since the professor
* said the max graded size should be 10^6, this restriction sufices.
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1a (const std::vector<int> &v_in, hipDeviceProp_t *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_intermediate, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = sizeof(int); // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
hipMalloc((void **) &d_in, d_in_size);
hipMalloc((void **) &d_intermediate, d_in_size); // overallocated
hipMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
hipMemcpy(d_in, &v_in[0], d_in_size, hipMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("\tFinding minimum entry in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
hipEventRecord(start, 0);
#endif
// Launch the kernel to find min
parallelScanMinKernel<<<blocks_per_grid, threads_per_block>>>
(d_intermediate, d_in, N);
// Make sure all the blocks finish executing
hipDeviceSynchronize();
hipDeviceSynchronize();
// If there are more than one block, we need to repeat the process with their results
if (blocks_per_grid > 1) {
#if DEBUG >=2
// Copy array to host
int *a_out;
a_out = (int*) malloc(d_in_size);
hipMemcpy(a_out, d_intermediate, d_in_size, hipMemcpyDeviceToHost);
printf("\tBlock results: d_intermediate = [ ");
for (int i=0; i<blocks_per_grid; ++i) {
if (i == blocks_per_grid-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
free(a_out);
#endif
#if DEBUG >= 2
printf("\tThreads per block: %d\n", blocks_per_grid);
printf("\tBlocks per grid: %d\n", 1);
printf("\tRunning kernel...\n");
#endif
// Fill one block with the results from the other blocks
parallelScanMinKernel<<<1, blocks_per_grid>>>
(d_out, d_intermediate, blocks_per_grid);
}
#if DEBUG
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the min result from GPU
int a_out;
if (blocks_per_grid > 1) {
hipMemcpy(&a_out, d_out, d_out_size, hipMemcpyDeviceToHost);
} else {
hipMemcpy(&a_out, d_intermediate, d_out_size, hipMemcpyDeviceToHost);
}
#if DEBUG >= 2
printf("\ta_out: %d\n", a_out);
#endif
// Copy result to output vector
std::vector<int> v_out (&a_out, &a_out + 1);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
// Write output to file
write_output(OUTPUT_FILE_Q1A, v_out);
}
/** Q1 b) Compute an array B such that B[i] is the last digit of A[i] for all i
*
* \param v_in Input array as a vector
* \param dev_props CUDA device properties
*/
void q1b (const std::vector<int> &v_in, hipDeviceProp_t *dev_props) {
#if DEBUG
printf("\tTransfering input array to GPU memory...\n");
#endif
// Declare GPU memory pointers
int *d_in, *d_out;
// Allocate GPU memory
int N = v_in.size(); // Problem size (input array size)
int d_in_size = N * sizeof(int); // Input array size in bytes
int d_out_size = d_in_size; // Output array size in bytes
#if DEBUG
printf("\tN (input array size): %d\n", N);
#endif
/*
if (N > ((int)((*dev_props).maxThreadsPerBlock) * (int)((*dev_props).maxThreadsPerBlock))) {
fprintf(stderr, "ERROR:q1a: problem size (input array size) is too large\n");
exit(EXIT_FATAL);
}
*/
hipMalloc((void **) &d_in, d_in_size);
hipMalloc((void **) &d_out, d_out_size);
/* Transfer the input array to the GPU
* Since the elements of a vector are stored contiguously in memory, we can
* pass a pointer to the first element of the vector, and that will act as
* if we passed a C array.
*/
hipMemcpy(d_in, &v_in[0], d_in_size, hipMemcpyHostToDevice);
#if DEBUG
// Set up a timer to measure the elapsed time to find the min
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("\tFinding last digit for all entries in the array...\n");
#endif
// Calculate the number of blocks and threads to use
int threads_per_block = (int)((*dev_props).maxThreadsPerBlock); // Max number of threads per block
int blocks_per_grid = (N + (threads_per_block - 1)) / threads_per_block;
#if DEBUG
printf("\tThreads per block: %d\n", threads_per_block);
printf("\tBlocks per grid: %d\n", blocks_per_grid);
printf("\tRunning kernel...\n");
hipEventRecord(start, 0);
#endif
#if DEBUG >= 3
printf("\t\tIterations:\n");
#endif
// Launch the kernel to find min
lastDigitKernel<<<blocks_per_grid, threads_per_block>>>
(d_out, d_in, N);
// Make sure all the blocks finish executing
hipDeviceSynchronize();
hipDeviceSynchronize();
#if DEBUG
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Calculate elapsed time, and print it
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("\tAverage time elapsed: %f\n", elapsedTime);
#endif
// Copy back the result from GPU
int *a_out;
a_out = (int*) malloc(d_out_size);
hipMemcpy(a_out, d_out, d_out_size, hipMemcpyDeviceToHost);
#if DEBUG >= 2
printf("\ta_out = [ ");
for (int i=0; i<N; ++i) {
if (i == N-1) {
printf("%d ]\n", a_out[i]);
} else {
printf("%d, ", a_out[i]);
}
}
#endif
// Copy resulting array to output vector
std::vector<int> v_out (a_out, a_out + N);
#if DEBUG
printf("\tOutput = [ ");
for (int i=0; i<v_out.size(); ++i) {
if (i == v_out.size()-1) {
printf("%d ]\n", v_out[i]);
} else {
printf("%d, ", v_out[i]);
}
}
#endif
// Free GPU memory
hipFree(d_in);
hipFree(d_out);
// Free host memory
free(a_out);
// Save output to file
write_output(OUTPUT_FILE_Q1B, v_out);
}
/** Main
*
* Set up CUDA device, read input file, and run Q1a and Q1b.
*
* \param argc Number of command-line arguments
* \param argv Array of command-line arguments
* \return Program return code
*/
int main (int argc, char **argv) {
#if DEBUG
std::printf("Executing main...\n");
#endif
std::vector<int> v_in;
int device_count;
int dev = 0;
hipDeviceProp_t dev_props;
#if DEBUG
printf("Detecting CUDA devices...\n");
#endif
// Check there are CUDA devices available
hipGetDeviceCount(&device_count);
if (device_count == 0) {
fprintf(stderr, "ERROR:main: no CUDA devices found\n");
exit(EXIT_FATAL);
}
// Use device 0
hipSetDevice(dev);
if (hipGetDeviceProperties(&dev_props, dev) == 0) {
#if DEBUG
printf("Using device:\n"
"\tID: %d\n"
"\tName: %s\n"
"\tGlobal mem: %d B\n"
"\tMax threads per block: %d\n"
"\tCompute: v%d.%d\n"
"\tClock: %d kHz\n",
dev,
dev_props.name,
(int)dev_props.totalGlobalMem,
(int)dev_props.maxThreadsPerBlock,
(int)dev_props.major,
(int)dev_props.minor,
(int)dev_props.clockRate);
#endif
} else {
fprintf(stderr, "ERROR:main: could not find CUDA device information\n");
exit(EXIT_FATAL);
}
#if DEBUG
std::printf("Reading input array...\n");
#endif
// Read input array
v_in = read_input(INPUT_FILE);
#if DEBUG >= 2
printf("\tInput array = [ ");
for (int i=0; i<v_in.size(); ++i) {
if (i == v_in.size()-1) {
printf("%d ]\n", v_in[i]);
} else {
printf("%d, ", v_in[i]);
}
}
#endif
#if DEBUG
std::printf("Running Q1 a...\n");
#endif
// Problem q1 a
q1a(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Running Q1 b...\n");
#endif
// Problem q1 b
q1b(v_in, &dev_props);
/*
#if DEBUG
std::printf("Reseting device...\n");
#endif
cudaDeviceReset();
*/
#if DEBUG
std::printf("Done\n");
#endif
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21parallelScanMinKernelPiS_i
.globl _Z21parallelScanMinKernelPiS_i
.p2align 8
.type _Z21parallelScanMinKernelPiS_i,@function
_Z21parallelScanMinKernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_10
s_load_b64 s[6:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s3, 2
s_cbranch_scc1 .LBB0_8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v5, 0
s_mov_b32 s8, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s8, s8, 1
s_waitcnt_vscnt null, 0x0
s_cmp_ge_i32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_4:
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_6
v_subrev_nc_u32_e32 v5, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, s6, v5
v_add_co_ci_u32_e64 v6, s2, s7, v6, s2
global_load_b32 v5, v[5:6], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v6, v6, v5
global_store_b32 v[3:4], v6, off
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_add_i32 s5, s5, -1
s_add_i32 s3, s3, -1
v_cmp_eq_u32_e32 vcc_lo, s5, v0
v_cmp_eq_u32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21parallelScanMinKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21parallelScanMinKernelPiS_i, .Lfunc_end0-_Z21parallelScanMinKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15lastDigitKernelPiS_i
.globl _Z15lastDigitKernelPiS_i
.p2align 8
.type _Z15lastDigitKernelPiS_i,@function
_Z15lastDigitKernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v3, v2, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 2, v3
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 10
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15lastDigitKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15lastDigitKernelPiS_i, .Lfunc_end1-_Z15lastDigitKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21parallelScanMinKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21parallelScanMinKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15lastDigitKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15lastDigitKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z15lastDigitKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.HI R0, R2, 0x66666667, RZ ; /* 0x6666666702007827 */
/* 0x004fca00078e02ff */
/*00b0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*00c0*/ LEA.HI.SX32 R7, R0, R5, 0x1e ; /* 0x0000000500077211 */
/* 0x000fe200078ff2ff */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R7, R7, -0xa, R2 ; /* 0xfffffff607077824 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21parallelScanMinKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R8, c[0x0][0x0], R11 ; /* 0x0000000008007a24 */
/* 0x001fca00078e020b */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc60000000a00 */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fcc0003f06270 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fce00078e0203 */
/*00b0*/ @!P0 BRA 0x1b0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fc80000000f00 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 MOV R5, 0x4 ; /* 0x0000000400050802 */
/* 0x000fe20000000f00 */
/*0100*/ @P0 IMAD.IADD R4, R0, 0x1, -R7 ; /* 0x0000000100040824 */
/* 0x000fc800078e0a07 */
/*0110*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004040625 */
/* 0x000fca00078e0205 */
/*0120*/ @P0 LDG.E R6, [R4.64] ; /* 0x0000000804060981 */
/* 0x000ea8000c1e1900 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @P0 LDG.E R9, [R2.64] ; /* 0x0000000802090981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0160*/ @P0 IMNMX R9, R6, R9, PT ; /* 0x0000000906090217 */
/* 0x004fca0003800200 */
/*0170*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0001e8000c101908 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06270 */
/*01a0*/ @!P0 BRA 0xe0 ; /* 0xffffff3000008947 */
/* 0x001fea000383ffff */
/*01b0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*01c0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe40000000800 */
/*01d0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*01e0*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*01f0*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000fffe13f */
/*0200*/ ISETP.NE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe4000bf05270 */
/*0210*/ ISETP.NE.AND P1, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fda000bf25270 */
/*0220*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*0230*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*0240*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0250*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0005 */
/*0260*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101908 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21parallelScanMinKernelPiS_i
.globl _Z21parallelScanMinKernelPiS_i
.p2align 8
.type _Z21parallelScanMinKernelPiS_i,@function
_Z21parallelScanMinKernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_10
s_load_b64 s[6:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s3, 2
s_cbranch_scc1 .LBB0_8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v5, 0
s_mov_b32 s8, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s8, s8, 1
s_waitcnt_vscnt null, 0x0
s_cmp_ge_i32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_4:
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_6
v_subrev_nc_u32_e32 v5, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, s6, v5
v_add_co_ci_u32_e64 v6, s2, s7, v6, s2
global_load_b32 v5, v[5:6], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v6, v6, v5
global_store_b32 v[3:4], v6, off
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_add_i32 s5, s5, -1
s_add_i32 s3, s3, -1
v_cmp_eq_u32_e32 vcc_lo, s5, v0
v_cmp_eq_u32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21parallelScanMinKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21parallelScanMinKernelPiS_i, .Lfunc_end0-_Z21parallelScanMinKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15lastDigitKernelPiS_i
.globl _Z15lastDigitKernelPiS_i
.p2align 8
.type _Z15lastDigitKernelPiS_i,@function
_Z15lastDigitKernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v3, v2, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 2, v3
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 10
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15lastDigitKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15lastDigitKernelPiS_i, .Lfunc_end1-_Z15lastDigitKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21parallelScanMinKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21parallelScanMinKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15lastDigitKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15lastDigitKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
char *title = "Floyd's algorithm";
char *description = "Алгоритм Флойда - поиск всех кратчайших путей в графе";
/*
Алгоритм Флойда является одним из методов поиска кратчайших путей в графе.
В отличии от алгоритма Дейкстры, который позволяет при доведении до конца построить
ориентированное дерево кратчайших путей от некоторой вершины, метод Флойда позволяет
найти длины всех кратчайших путей в графе. Конечно эта задача может быть решена
и многократным применением алгоритма Дейкстры (каждый раз последовательно выбираем
вершину от первой до N-ной, пока не получим кратчайшие пути от всех вершин графа),
однако реализация подобной процедуры потребовала бы значительных вычислительных затрат.
Прежде чем представлять алгоритмы, необходимо ввести некоторые обозначения.
Перенумеруем вершины исходного графа целыми числами от 1 до N. Обозначим через di,jm длину кратчайшего пути
из вершинм i в вершину j, который в качестве промежуточных может содержать только первые m вершин графа.
(Напомним, что промежуточной вершиной пути является любая принадлежащая ему вершина, не совпадающая
с его начальной или конечной вершинами.) Если между вершинами i и j не существует ни одного пути указанного типа,
то условно будем считать, что di,jm=∞. Из данного определения величин di,jm следует, что величина di,j0,
представляет длину кратчайшего пути из вершины i в вершину j, не имеющего промежуточных вершин,
т. е. длину кратчайшей дуги, соединяющей i с j (если такие дуги присутствуют в графе).
для любой вершины i положим di,im= 0. Отметим далее, что величина di,jmпредставляет длину кратчайшего пути
между вершинами i и j.
Обозначим через Dm матрицу размера NxN, элемент (i, j) которой совпадает с di,jm.
Если в исходном графе нам известна длина каждой дуги, то мы можем сформировать матрицу D0.
Наша цель состоит в определении матрицы DN, представляющей кратчайшие пути между всеми вершинами рассматриваемого графа.
В алгоритме Флойда в качестве исходной выступает матрица D0.
Вначале из этой матрицы вычисляется матрица D1.
Затем по матрице D1 вычисляется матрицав D2 и т. д.
Процесс повторяется до тех пор, пока по матрице DN-1 не будет вычислена матрица DN.
Рассмотрим основную идею, лежащую в основе алгоритма Флойда.
Суть алгоритма Флойда заключается в проверке того, не окажется ли путь из вершины i в вершину j короче,
если он будет проходить через некоторую промежуточную вершину m. Предположим, что нам известны:
кратчайший путь из вершины i в вершину m, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины m в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины i в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин.
Поскольку по предположению исходный граф не может содержать контуров отрицательной длины,
один из двух путей — путь, совпадающий с представленным в пункте 3, или путь, являющийся объединением
путей из пунктов 1 и 2 — должен быть кратчайшим путем из вершины i в вершину j,
в котором в качестве промежуточных допускается использование только первых m вершин. Таким образом,
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
Из соотношения видно, что для вычисления элементов матрицы Dm необходимо располагать лишь элементами матрицы Dm-1.
Более того, соответствующие вычисления могут быть проведены без обращения к исходному графу.
Теперь мм в состоянии дать формальное описание алгоритма Флойда для нахождения на графе кратчайших путей
между всеми парами вершин.
Алгоритм
Перенумеровать вершины графа от 1 до N целыми числами, определить матрицу D0, каждый элемент di,j
которой есть длина кратчайшей дуги между вершинами i и j. Если такой дуги нет, положить значение элемента
равным ∞. Кроме того, положить значения диагонального элемента di,iравным 0.
Для целого m, последовательно принимающего значения 1...N определить по элементам матрицы Dm-1 элементы Dm
Алгоритм заканчивается получением матрицы всех кратчайших путей DN, N – число вершин графа.
Напомним, для определения по известным элементам матрицы Dm-1 элементов матрицы Dm
в алгоритме Флойда применяется рекурсивное соотношение:
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
di,jm – элемент матрицы Dm, di,jm-1 – элементы матрицы Dm-1 найденой на предыдущем шаге алгоритма.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <ctype.h>
#include <limits.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define assert( bool )
int strempty(const char *p)
{
if (!p)
return (1);
for (; *p; p++)
if (!isspace(*p))
return (0);
return (1);
}
char *mystrtok(char **m, char *s, char c)
{
char *p = s ? s : *m;
if (!*p)
return 0;
*m = strchr(p, c);
if (*m)
*(*m)++ = 0;
else
*m = p + strlen(p);
return p;
}
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
__global__ void global_init(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
intermedian[id] = -1;
}
}
__global__ void global_floyd(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
int i = id/n;
int j = id%n;
if(i != j && prev[i*n+m] != LONG_MAX && prev[m*n+j] != LONG_MAX && (prev[i*n+m] + prev[m*n+j]) < prev[i*n+j]){
next[id] = prev[i*n+m] + prev[m*n+j];
intermedian[id] = m;
}
else {
next[id] = prev[id];
}
}
}
__host__ void host_floyd(int gridSize, int blockSize, long *matrix, int *intermedian, int n)
{
cudaError_t err;
long *device_prev;
long *device_next;
int *device_intermedian;
err = cudaMalloc((void**)&device_prev, n*n * sizeof(long));
err = cudaMalloc((void**)&device_next, n*n * sizeof(long));
err = cudaMalloc((void**)&device_intermedian, n*n * sizeof(int));
err = cudaMemcpy(device_prev, matrix, n*n*sizeof(long), cudaMemcpyHostToDevice);
int blocks = (gridSize > 0)? gridSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
int threads = (blockSize > 0)? blockSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
global_init <<< blocks, threads >>>(device_prev, device_next, device_intermedian, -1, n);
for(int m = 0; m < n ; m++){
global_floyd <<< blocks, threads >>>(device_prev, device_next, device_intermedian, m, n);
err = cudaMemcpy(matrix, device_next, n*n*sizeof(long), cudaMemcpyDeviceToHost);
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
}
}
printf("\n");
long * t = device_prev; device_prev = device_next; device_next = t;
}
err = cudaMemcpy(matrix, device_prev, n*n*sizeof(long), cudaMemcpyDeviceToHost);
err = cudaMemcpy(intermedian, device_intermedian, n*n*sizeof(int), cudaMemcpyDeviceToHost);
err = cudaFree(device_prev);
err = cudaFree(device_next);
err = cudaFree(device_intermedian);
err = err;
}
int main(int argc, char* argv[])
{
int gridSize = 0;
int blockSize = 0;
printf("Title :\t%s\n", title); fflush(stdout);
if (argc < 4) {
printf("Usage :\t%s [-g <gridSize>] [-b <blockSize>] <inputfilename> <outputfilename> <intermedianfilename>\n", argv[0]); fflush(stdout);
printf("\tinputfilename - source matrix of path prices or empty\n"); fflush(stdout);
printf("\toutputfilename - output floyd's matrix of path prices\n"); fflush(stdout);
printf("\tintermedianfilename - output matrix of intermedian points or empty\n"); fflush(stdout);
exit(-1);
}
int argId = 1;
for(; argId < argc && argv[argId][0]=='-' ; argId++){
switch(argv[argId][1]){
case 'g':
gridSize = atoi(argv[++argId]);
break;
case 'b':
blockSize = atoi(argv[++argId]);
break;
}
}
char *inputFileName = argv[argId++];
char *outputFileName = argv[argId++];
char *intermedianFileName = argv[argId++];
printf("Input File Name :\t%s\n", inputFileName); fflush(stdout);
printf("Output File Name :\t%s\n", outputFileName); fflush(stdout);
printf("Intermedian File Name :\t%s\n", intermedianFileName); fflush(stdout);
char buffer[4096];
char *tok;
char *p;
int n; /* Ранг текущего массива */
long *matrix; /* Массив цен */
int *intermedian; /* Массивов промежуточных точек */
int i, j;
FILE *fs = fopen(inputFileName, "r");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", inputFileName); fflush(stderr);
exit(-1);
}
n = 0;
/* Заполняем массив числами из файла */
/* Операция выполняетя только на хост процессе */
/* Операция выполняетя в два прохода по файлу */
/* На первом проходе определяется ранг матрицы */
/* На втором проходе считываются данные */
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
j++;
}
n = max(n, j);
}
n = max(n, i);
matrix = (long *)malloc(n*n*sizeof(long));
intermedian = (int *)malloc(n*n*sizeof(int));
fseek(fs, 0, SEEK_SET);
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
/* Пустые элементы - это запрещённые пути */
matrix[n*i + j++] = strempty(tok) ? LONG_MAX : atol(tok);
}
for (; j < n; j++) matrix[n*i + j] = LONG_MAX;
}
for (j = 0; j < (n - i)*n; j++) matrix[n*i + j] = LONG_MAX;
for (i = 0; i < n; i++) matrix[n*i + i] = LONG_MAX; /* Запрещаем петли */
fclose(fs);
printf("Matrix rank :\t%d\n", n);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : "\t"));
}
}
fflush(stdout);
// Find/set the device.
int device_size = 0;
cudaGetDeviceCount(&device_size);
for (i = 0; i < device_size; ++i)
{
cudaDeviceProp cudaDeviceProp;
cudaGetDeviceProperties(&cudaDeviceProp, i);
printf("Running on GPU %d (%s)\n", i, cudaDeviceProp.name);
printf("Device has ECC support enabled %d\n",cudaDeviceProp.ECCEnabled);
printf("Number of asynchronous engines %d\n",cudaDeviceProp.asyncEngineCount);
printf("Device can map host memory with cudaHostAlloc/cudaHostGetDevicePointer %d\n",cudaDeviceProp.canMapHostMemory);
printf("Clock frequency in kilohertz %d\n",cudaDeviceProp.clockRate);
printf("Compute mode (See cudaComputeMode) %d\n",cudaDeviceProp.computeMode);
printf("Device can possibly execute multiple kernels concurrently %d\n",cudaDeviceProp.concurrentKernels);
printf("Device can concurrently copy memory and execute a kernel. Deprecated. Use instead asyncEngineCount. %d\n",cudaDeviceProp.deviceOverlap);
printf("Device is integrated as opposed to discrete %d\n",cudaDeviceProp.integrated);
printf("Specified whether there is a run time limit on kernels %d\n",cudaDeviceProp.kernelExecTimeoutEnabled);
printf("Size of L2 cache in bytes %d\n",cudaDeviceProp.l2CacheSize);
printf("Major compute capability %d\n",cudaDeviceProp.major);
printf("Maximum size of each dimension of a grid %d\n",cudaDeviceProp.maxGridSize[0]);
printf("Maximum size of each dimension of a grid %d\n",cudaDeviceProp.maxGridSize[1]);
printf("Maximum size of each dimension of a grid %d\n",cudaDeviceProp.maxGridSize[2]);
printf("Maximum 1D surface size %d\n",cudaDeviceProp.maxSurface1D);
printf("Maximum 1D layered surface dimensions %d\n",cudaDeviceProp.maxSurface1DLayered[0]);
printf("Maximum 1D layered surface dimensions %d\n",cudaDeviceProp.maxSurface1DLayered[1]);
printf("Maximum 2D surface dimensions %d\n",cudaDeviceProp.maxSurface2D[0]);
printf("Maximum 2D surface dimensions %d\n",cudaDeviceProp.maxSurface2D[1]);
printf("Maximum 2D layered surface dimensions %d\n",cudaDeviceProp.maxSurface2DLayered[0]);
printf("Maximum 2D layered surface dimensions %d\n",cudaDeviceProp.maxSurface2DLayered[1]);
printf("Maximum 2D layered surface dimensions %d\n",cudaDeviceProp.maxSurface2DLayered[2]);
printf("Maximum 3D surface dimensions %d\n",cudaDeviceProp.maxSurface3D[0]);
printf("Maximum 3D surface dimensions %d\n",cudaDeviceProp.maxSurface3D[1]);
printf("Maximum 3D surface dimensions %d\n",cudaDeviceProp.maxSurface3D[2]);
printf("Maximum Cubemap surface dimensions %d\n",cudaDeviceProp.maxSurfaceCubemap);
printf("Maximum Cubemap layered surface dimensions %d\n",cudaDeviceProp.maxSurfaceCubemapLayered[0]);
printf("Maximum Cubemap layered surface dimensions %d\n",cudaDeviceProp.maxSurfaceCubemapLayered[1]);
printf("Maximum 1D texture size %d\n",cudaDeviceProp.maxTexture1D);
printf("Maximum 1D layered texture dimensions %d\n",cudaDeviceProp.maxTexture1DLayered[0]);
printf("Maximum 1D layered texture dimensions %d\n",cudaDeviceProp.maxTexture1DLayered[1]);
printf("Maximum size for 1D textures bound to linear memory %d\n",cudaDeviceProp.maxTexture1DLinear);
printf("Maximum 1D mipmapped texture size %d\n",cudaDeviceProp.maxTexture1DMipmap);
printf("Maximum 2D texture dimensions %d\n",cudaDeviceProp.maxTexture2D[0]);
printf("Maximum 2D texture dimensions %d\n",cudaDeviceProp.maxTexture2D[1]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",cudaDeviceProp.maxTexture2DGather[0]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",cudaDeviceProp.maxTexture2DGather[1]);
printf("Maximum 2D layered texture dimensions %d\n",cudaDeviceProp.maxTexture2DLayered[0]);
printf("Maximum 2D layered texture dimensions %d\n",cudaDeviceProp.maxTexture2DLayered[1]);
printf("Maximum 2D layered texture dimensions %d\n",cudaDeviceProp.maxTexture2DLayered[2]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",cudaDeviceProp.maxTexture2DLinear[0]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",cudaDeviceProp.maxTexture2DLinear[1]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",cudaDeviceProp.maxTexture2DLinear[2]);
printf("Maximum 2D mipmapped texture dimensions %d\n",cudaDeviceProp.maxTexture2DMipmap[0]);
printf("Maximum 2D mipmapped texture dimensions %d\n",cudaDeviceProp.maxTexture2DMipmap[1]);
printf("Maximum 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3D[0]);
printf("Maximum 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3D[1]);
printf("Maximum 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3D[2]);
printf("Maximum alternate 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3DAlt[0]);
printf("Maximum alternate 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3DAlt[1]);
printf("Maximum alternate 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3DAlt[2]);
printf("Maximum Cubemap texture dimensions %d\n",cudaDeviceProp.maxTextureCubemap);
printf("Maximum Cubemap layered texture dimensions %d\n",cudaDeviceProp.maxTextureCubemapLayered[0]);
printf("Maximum Cubemap layered texture dimensions %d\n",cudaDeviceProp.maxTextureCubemapLayered[1]);
printf("Maximum size of each dimension of a block %d\n",cudaDeviceProp.maxThreadsDim[0]);
printf("Maximum size of each dimension of a block %d\n",cudaDeviceProp.maxThreadsDim[1]);
printf("Maximum size of each dimension of a block %d\n",cudaDeviceProp.maxThreadsDim[2]);
printf("Maximum number of threads per block %d\n",cudaDeviceProp.maxThreadsPerBlock);
printf("Maximum resident threads per multiprocessor %d\n",cudaDeviceProp.maxThreadsPerMultiProcessor);
printf("Maximum pitch in bytes allowed by memory copies %d\n",cudaDeviceProp.memPitch);
printf("Global memory bus width in bits %d\n",cudaDeviceProp.memoryBusWidth);
printf("Peak memory clock frequency in kilohertz %d\n",cudaDeviceProp.memoryClockRate);
printf("Minor compute capability %d\n",cudaDeviceProp.minor);
printf("Number of multiprocessors on device %d\n",cudaDeviceProp.multiProcessorCount);
printf("PCI bus ID of the device %d\n",cudaDeviceProp.pciBusID);
printf("PCI device ID of the device %d\n",cudaDeviceProp.pciDeviceID);
printf("PCI domain ID of the device %d\n",cudaDeviceProp.pciDomainID);
printf("32-bit registers available per block %d\n",cudaDeviceProp.regsPerBlock);
printf("Shared memory available per block in bytes %d\n",cudaDeviceProp.sharedMemPerBlock);
printf("Device supports stream priorities %d\n",cudaDeviceProp.streamPrioritiesSupported);
printf("Alignment requirements for surfaces %d\n",cudaDeviceProp.surfaceAlignment);
printf("1 if device is a Tesla device using TCC driver, 0 otherwise %d\n",cudaDeviceProp.tccDriver);
printf("Alignment requirement for textures %d\n",cudaDeviceProp.textureAlignment);
printf("Pitch alignment requirement for texture references bound to pitched memory %d\n",cudaDeviceProp.texturePitchAlignment);
printf("Constant memory available on device in bytes %d\n",cudaDeviceProp.totalConstMem);
printf("Global memory available on device in bytes %d\n",cudaDeviceProp.totalGlobalMem);
printf("Device shares a unified address space with the host %d\n",cudaDeviceProp.unifiedAddressing);
printf("Warp size in threads %d\n",cudaDeviceProp.warpSize);
fflush(stdout);
}
host_floyd(gridSize, blockSize, matrix, intermedian, n);
cudaDeviceReset();
/* Bыводим результаты */
fs = fopen(outputFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", outputFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (matrix[i*n + j] != LONG_MAX)
fprintf(fs, "%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
/* Bыводим результаты */
fs = fopen(intermedianFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", intermedianFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (intermedian[i*n + j] >= 0)
fprintf(fs, "%d%s", intermedian[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
free(matrix);
free(intermedian);
exit(0);
}
|
code for sm_80
Function : _Z12global_floydPlS_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R0, c[0x0][0x17c] ; /* 0x00005f0000007a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R5, R5, R0, RZ ; /* 0x0000000005057224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fc800078e0002 */
/*0120*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fe20000000000 */
/*0130*/ HFMA2.MMA R15, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0f7435 */
/* 0x000fe200000001ff */
/*0140*/ IABS R8, c[0x0][0x17c] ; /* 0x00005f0000087a13 */
/* 0x000fe20000000000 */
/*0150*/ BSSY B0, 0x4b0 ; /* 0x0000035000007945 */
/* 0x000fe20003800000 */
/*0160*/ BSSY B1, 0x460 ; /* 0x000002f000017945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.HI.U32 R2, R5, R6, RZ ; /* 0x0000000605027227 */
/* 0x000fe200078e00ff */
/*0180*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fc60000011404 */
/*0190*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01a0*/ IMAD R3, R8, R3, R6 ; /* 0x0000000308037224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IADD3 R3, R3, -R8, RZ ; /* 0x800000080303a210 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe40003f06070 */
/*01f0*/ LOP3.LUT R3, R4, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0004037a12 */
/* 0x000fe400078e3cff */
/*0200*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*0210*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0220*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fca0007ffe0ff */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0002 */
/*0240*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*0250*/ @!P2 LOP3.LUT R8, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff08aa12 */
/* 0x000fca00078e33ff */
/*0260*/ IMAD.MOV R3, RZ, RZ, -R8 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a08 */
/*0270*/ IMAD R13, R3, c[0x0][0x17c], R4 ; /* 0x00005f00030d7a24 */
/* 0x000fe400078e0204 */
/*0280*/ IMAD.WIDE R2, R4, R15, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc600078e020f */
/*0290*/ ISETP.NE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fda0003f05270 */
/*02a0*/ @!P0 BRA 0x450 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD R8, R8, R6, c[0x0][0x178] ; /* 0x00005e0008087624 */
/* 0x000fc800078e0206 */
/*02d0*/ IMAD.WIDE R8, R8, R15, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020f */
/*02e0*/ LDG.E.64 R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea4000c1e1b00 */
/*02f0*/ ISETP.NE.U32.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fc80003f05070 */
/*0300*/ ISETP.NE.AND.EX P0, PT, R11, 0x7fffffff, PT, P0 ; /* 0x7fffffff0b00780c */
/* 0x000fda0003f05300 */
/*0310*/ @!P0 BRA 0x450 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD R8, R6, c[0x0][0x178], R13 ; /* 0x00005e0006087a24 */
/* 0x000fc800078e020d */
/*0330*/ IMAD.WIDE R8, R8, R15, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020f */
/*0340*/ LDG.E.64 R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000ea4000c1e1b00 */
/*0350*/ ISETP.NE.U32.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fc80003f05070 */
/*0360*/ ISETP.NE.AND.EX P0, PT, R13, 0x7fffffff, PT, P0 ; /* 0x7fffffff0d00780c */
/* 0x000fda0003f05300 */
/*0370*/ @!P0 BRA 0x450 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0380*/ IMAD.WIDE R8, R4, R15, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fcc00078e020f */
/*0390*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IADD3 R12, P0, R10, R12, RZ ; /* 0x0000000c0a0c7210 */
/* 0x000fca0007f1e0ff */
/*03b0*/ IMAD.X R13, R11, 0x1, R13, P0 ; /* 0x000000010b0d7824 */
/* 0x000fe200000e060d */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R12, R8, PT ; /* 0x000000080c00720c */
/* 0x004fc80003f06070 */
/*03d0*/ ISETP.GE.AND.EX P0, PT, R13, R9, PT, P0 ; /* 0x000000090d00720c */
/* 0x000fda0003f06300 */
/*03e0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b8424 */
/* 0x000fe200078e00ff */
/*03f0*/ @!P0 MOV R15, c[0x0][0x178] ; /* 0x00005e00000f8a02 */
/* 0x000fe20000000f00 */
/*0400*/ @!P0 STG.E.64 [R2.64], R12 ; /* 0x0000000c02008986 */
/* 0x0001e2000c101b06 */
/*0410*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*0420*/ @!P0 IMAD.WIDE R10, R4, R11, c[0x0][0x170] ; /* 0x00005c00040a8625 */
/* 0x000fca00078e020b */
/*0430*/ @!P0 STG.E [R10.64], R15 ; /* 0x0000000f0a008986 */
/* 0x0001e2000c101906 */
/*0440*/ @!P0 BRA 0x4a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0450*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0460*/ LEA R6, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004067a11 */
/* 0x000fc800078018ff */
/*0470*/ LEA.HI.X R7, R4, c[0x0][0x164], R7, 0x3, P0 ; /* 0x0000590004077a11 */
/* 0x000fcc00000f1c07 */
/*0480*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1b00 */
/*0490*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0043e4000c101b06 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x003fc800078e00ff */
/*04c0*/ IMAD R4, R3, c[0x0][0xc], R4 ; /* 0x0000030003047a24 */
/* 0x000fca00078e0204 */
/*04d0*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*04e0*/ @!P0 BRA 0x120 ; /* 0xfffffc3000008947 */
/* 0x000fea000383ffff */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11global_initPlS_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, 0xffffffff ; /* 0xffffffff00077802 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fce0000000f00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101906 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0100*/ @!P0 BRA 0xc0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
char *title = "Floyd's algorithm";
char *description = "Алгоритм Флойда - поиск всех кратчайших путей в графе";
/*
Алгоритм Флойда является одним из методов поиска кратчайших путей в графе.
В отличии от алгоритма Дейкстры, который позволяет при доведении до конца построить
ориентированное дерево кратчайших путей от некоторой вершины, метод Флойда позволяет
найти длины всех кратчайших путей в графе. Конечно эта задача может быть решена
и многократным применением алгоритма Дейкстры (каждый раз последовательно выбираем
вершину от первой до N-ной, пока не получим кратчайшие пути от всех вершин графа),
однако реализация подобной процедуры потребовала бы значительных вычислительных затрат.
Прежде чем представлять алгоритмы, необходимо ввести некоторые обозначения.
Перенумеруем вершины исходного графа целыми числами от 1 до N. Обозначим через di,jm длину кратчайшего пути
из вершинм i в вершину j, который в качестве промежуточных может содержать только первые m вершин графа.
(Напомним, что промежуточной вершиной пути является любая принадлежащая ему вершина, не совпадающая
с его начальной или конечной вершинами.) Если между вершинами i и j не существует ни одного пути указанного типа,
то условно будем считать, что di,jm=∞. Из данного определения величин di,jm следует, что величина di,j0,
представляет длину кратчайшего пути из вершины i в вершину j, не имеющего промежуточных вершин,
т. е. длину кратчайшей дуги, соединяющей i с j (если такие дуги присутствуют в графе).
для любой вершины i положим di,im= 0. Отметим далее, что величина di,jmпредставляет длину кратчайшего пути
между вершинами i и j.
Обозначим через Dm матрицу размера NxN, элемент (i, j) которой совпадает с di,jm.
Если в исходном графе нам известна длина каждой дуги, то мы можем сформировать матрицу D0.
Наша цель состоит в определении матрицы DN, представляющей кратчайшие пути между всеми вершинами рассматриваемого графа.
В алгоритме Флойда в качестве исходной выступает матрица D0.
Вначале из этой матрицы вычисляется матрица D1.
Затем по матрице D1 вычисляется матрицав D2 и т. д.
Процесс повторяется до тех пор, пока по матрице DN-1 не будет вычислена матрица DN.
Рассмотрим основную идею, лежащую в основе алгоритма Флойда.
Суть алгоритма Флойда заключается в проверке того, не окажется ли путь из вершины i в вершину j короче,
если он будет проходить через некоторую промежуточную вершину m. Предположим, что нам известны:
кратчайший путь из вершины i в вершину m, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины m в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины i в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин.
Поскольку по предположению исходный граф не может содержать контуров отрицательной длины,
один из двух путей — путь, совпадающий с представленным в пункте 3, или путь, являющийся объединением
путей из пунктов 1 и 2 — должен быть кратчайшим путем из вершины i в вершину j,
в котором в качестве промежуточных допускается использование только первых m вершин. Таким образом,
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
Из соотношения видно, что для вычисления элементов матрицы Dm необходимо располагать лишь элементами матрицы Dm-1.
Более того, соответствующие вычисления могут быть проведены без обращения к исходному графу.
Теперь мм в состоянии дать формальное описание алгоритма Флойда для нахождения на графе кратчайших путей
между всеми парами вершин.
Алгоритм
Перенумеровать вершины графа от 1 до N целыми числами, определить матрицу D0, каждый элемент di,j
которой есть длина кратчайшей дуги между вершинами i и j. Если такой дуги нет, положить значение элемента
равным ∞. Кроме того, положить значения диагонального элемента di,iравным 0.
Для целого m, последовательно принимающего значения 1...N определить по элементам матрицы Dm-1 элементы Dm
Алгоритм заканчивается получением матрицы всех кратчайших путей DN, N – число вершин графа.
Напомним, для определения по известным элементам матрицы Dm-1 элементов матрицы Dm
в алгоритме Флойда применяется рекурсивное соотношение:
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
di,jm – элемент матрицы Dm, di,jm-1 – элементы матрицы Dm-1 найденой на предыдущем шаге алгоритма.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <ctype.h>
#include <limits.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define assert( bool )
int strempty(const char *p)
{
if (!p)
return (1);
for (; *p; p++)
if (!isspace(*p))
return (0);
return (1);
}
char *mystrtok(char **m, char *s, char c)
{
char *p = s ? s : *m;
if (!*p)
return 0;
*m = strchr(p, c);
if (*m)
*(*m)++ = 0;
else
*m = p + strlen(p);
return p;
}
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
__global__ void global_init(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
intermedian[id] = -1;
}
}
__global__ void global_floyd(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
int i = id/n;
int j = id%n;
if(i != j && prev[i*n+m] != LONG_MAX && prev[m*n+j] != LONG_MAX && (prev[i*n+m] + prev[m*n+j]) < prev[i*n+j]){
next[id] = prev[i*n+m] + prev[m*n+j];
intermedian[id] = m;
}
else {
next[id] = prev[id];
}
}
}
__host__ void host_floyd(int gridSize, int blockSize, long *matrix, int *intermedian, int n)
{
cudaError_t err;
long *device_prev;
long *device_next;
int *device_intermedian;
err = cudaMalloc((void**)&device_prev, n*n * sizeof(long));
err = cudaMalloc((void**)&device_next, n*n * sizeof(long));
err = cudaMalloc((void**)&device_intermedian, n*n * sizeof(int));
err = cudaMemcpy(device_prev, matrix, n*n*sizeof(long), cudaMemcpyHostToDevice);
int blocks = (gridSize > 0)? gridSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
int threads = (blockSize > 0)? blockSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
global_init <<< blocks, threads >>>(device_prev, device_next, device_intermedian, -1, n);
for(int m = 0; m < n ; m++){
global_floyd <<< blocks, threads >>>(device_prev, device_next, device_intermedian, m, n);
err = cudaMemcpy(matrix, device_next, n*n*sizeof(long), cudaMemcpyDeviceToHost);
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
}
}
printf("\n");
long * t = device_prev; device_prev = device_next; device_next = t;
}
err = cudaMemcpy(matrix, device_prev, n*n*sizeof(long), cudaMemcpyDeviceToHost);
err = cudaMemcpy(intermedian, device_intermedian, n*n*sizeof(int), cudaMemcpyDeviceToHost);
err = cudaFree(device_prev);
err = cudaFree(device_next);
err = cudaFree(device_intermedian);
err = err;
}
int main(int argc, char* argv[])
{
int gridSize = 0;
int blockSize = 0;
printf("Title :\t%s\n", title); fflush(stdout);
if (argc < 4) {
printf("Usage :\t%s [-g <gridSize>] [-b <blockSize>] <inputfilename> <outputfilename> <intermedianfilename>\n", argv[0]); fflush(stdout);
printf("\tinputfilename - source matrix of path prices or empty\n"); fflush(stdout);
printf("\toutputfilename - output floyd's matrix of path prices\n"); fflush(stdout);
printf("\tintermedianfilename - output matrix of intermedian points or empty\n"); fflush(stdout);
exit(-1);
}
int argId = 1;
for(; argId < argc && argv[argId][0]=='-' ; argId++){
switch(argv[argId][1]){
case 'g':
gridSize = atoi(argv[++argId]);
break;
case 'b':
blockSize = atoi(argv[++argId]);
break;
}
}
char *inputFileName = argv[argId++];
char *outputFileName = argv[argId++];
char *intermedianFileName = argv[argId++];
printf("Input File Name :\t%s\n", inputFileName); fflush(stdout);
printf("Output File Name :\t%s\n", outputFileName); fflush(stdout);
printf("Intermedian File Name :\t%s\n", intermedianFileName); fflush(stdout);
char buffer[4096];
char *tok;
char *p;
int n; /* Ранг текущего массива */
long *matrix; /* Массив цен */
int *intermedian; /* Массивов промежуточных точек */
int i, j;
FILE *fs = fopen(inputFileName, "r");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", inputFileName); fflush(stderr);
exit(-1);
}
n = 0;
/* Заполняем массив числами из файла */
/* Операция выполняетя только на хост процессе */
/* Операция выполняетя в два прохода по файлу */
/* На первом проходе определяется ранг матрицы */
/* На втором проходе считываются данные */
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
j++;
}
n = max(n, j);
}
n = max(n, i);
matrix = (long *)malloc(n*n*sizeof(long));
intermedian = (int *)malloc(n*n*sizeof(int));
fseek(fs, 0, SEEK_SET);
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
/* Пустые элементы - это запрещённые пути */
matrix[n*i + j++] = strempty(tok) ? LONG_MAX : atol(tok);
}
for (; j < n; j++) matrix[n*i + j] = LONG_MAX;
}
for (j = 0; j < (n - i)*n; j++) matrix[n*i + j] = LONG_MAX;
for (i = 0; i < n; i++) matrix[n*i + i] = LONG_MAX; /* Запрещаем петли */
fclose(fs);
printf("Matrix rank :\t%d\n", n);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : "\t"));
}
}
fflush(stdout);
// Find/set the device.
int device_size = 0;
cudaGetDeviceCount(&device_size);
for (i = 0; i < device_size; ++i)
{
cudaDeviceProp cudaDeviceProp;
cudaGetDeviceProperties(&cudaDeviceProp, i);
printf("Running on GPU %d (%s)\n", i, cudaDeviceProp.name);
printf("Device has ECC support enabled %d\n",cudaDeviceProp.ECCEnabled);
printf("Number of asynchronous engines %d\n",cudaDeviceProp.asyncEngineCount);
printf("Device can map host memory with cudaHostAlloc/cudaHostGetDevicePointer %d\n",cudaDeviceProp.canMapHostMemory);
printf("Clock frequency in kilohertz %d\n",cudaDeviceProp.clockRate);
printf("Compute mode (See cudaComputeMode) %d\n",cudaDeviceProp.computeMode);
printf("Device can possibly execute multiple kernels concurrently %d\n",cudaDeviceProp.concurrentKernels);
printf("Device can concurrently copy memory and execute a kernel. Deprecated. Use instead asyncEngineCount. %d\n",cudaDeviceProp.deviceOverlap);
printf("Device is integrated as opposed to discrete %d\n",cudaDeviceProp.integrated);
printf("Specified whether there is a run time limit on kernels %d\n",cudaDeviceProp.kernelExecTimeoutEnabled);
printf("Size of L2 cache in bytes %d\n",cudaDeviceProp.l2CacheSize);
printf("Major compute capability %d\n",cudaDeviceProp.major);
printf("Maximum size of each dimension of a grid %d\n",cudaDeviceProp.maxGridSize[0]);
printf("Maximum size of each dimension of a grid %d\n",cudaDeviceProp.maxGridSize[1]);
printf("Maximum size of each dimension of a grid %d\n",cudaDeviceProp.maxGridSize[2]);
printf("Maximum 1D surface size %d\n",cudaDeviceProp.maxSurface1D);
printf("Maximum 1D layered surface dimensions %d\n",cudaDeviceProp.maxSurface1DLayered[0]);
printf("Maximum 1D layered surface dimensions %d\n",cudaDeviceProp.maxSurface1DLayered[1]);
printf("Maximum 2D surface dimensions %d\n",cudaDeviceProp.maxSurface2D[0]);
printf("Maximum 2D surface dimensions %d\n",cudaDeviceProp.maxSurface2D[1]);
printf("Maximum 2D layered surface dimensions %d\n",cudaDeviceProp.maxSurface2DLayered[0]);
printf("Maximum 2D layered surface dimensions %d\n",cudaDeviceProp.maxSurface2DLayered[1]);
printf("Maximum 2D layered surface dimensions %d\n",cudaDeviceProp.maxSurface2DLayered[2]);
printf("Maximum 3D surface dimensions %d\n",cudaDeviceProp.maxSurface3D[0]);
printf("Maximum 3D surface dimensions %d\n",cudaDeviceProp.maxSurface3D[1]);
printf("Maximum 3D surface dimensions %d\n",cudaDeviceProp.maxSurface3D[2]);
printf("Maximum Cubemap surface dimensions %d\n",cudaDeviceProp.maxSurfaceCubemap);
printf("Maximum Cubemap layered surface dimensions %d\n",cudaDeviceProp.maxSurfaceCubemapLayered[0]);
printf("Maximum Cubemap layered surface dimensions %d\n",cudaDeviceProp.maxSurfaceCubemapLayered[1]);
printf("Maximum 1D texture size %d\n",cudaDeviceProp.maxTexture1D);
printf("Maximum 1D layered texture dimensions %d\n",cudaDeviceProp.maxTexture1DLayered[0]);
printf("Maximum 1D layered texture dimensions %d\n",cudaDeviceProp.maxTexture1DLayered[1]);
printf("Maximum size for 1D textures bound to linear memory %d\n",cudaDeviceProp.maxTexture1DLinear);
printf("Maximum 1D mipmapped texture size %d\n",cudaDeviceProp.maxTexture1DMipmap);
printf("Maximum 2D texture dimensions %d\n",cudaDeviceProp.maxTexture2D[0]);
printf("Maximum 2D texture dimensions %d\n",cudaDeviceProp.maxTexture2D[1]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",cudaDeviceProp.maxTexture2DGather[0]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",cudaDeviceProp.maxTexture2DGather[1]);
printf("Maximum 2D layered texture dimensions %d\n",cudaDeviceProp.maxTexture2DLayered[0]);
printf("Maximum 2D layered texture dimensions %d\n",cudaDeviceProp.maxTexture2DLayered[1]);
printf("Maximum 2D layered texture dimensions %d\n",cudaDeviceProp.maxTexture2DLayered[2]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",cudaDeviceProp.maxTexture2DLinear[0]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",cudaDeviceProp.maxTexture2DLinear[1]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",cudaDeviceProp.maxTexture2DLinear[2]);
printf("Maximum 2D mipmapped texture dimensions %d\n",cudaDeviceProp.maxTexture2DMipmap[0]);
printf("Maximum 2D mipmapped texture dimensions %d\n",cudaDeviceProp.maxTexture2DMipmap[1]);
printf("Maximum 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3D[0]);
printf("Maximum 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3D[1]);
printf("Maximum 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3D[2]);
printf("Maximum alternate 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3DAlt[0]);
printf("Maximum alternate 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3DAlt[1]);
printf("Maximum alternate 3D texture dimensions %d\n",cudaDeviceProp.maxTexture3DAlt[2]);
printf("Maximum Cubemap texture dimensions %d\n",cudaDeviceProp.maxTextureCubemap);
printf("Maximum Cubemap layered texture dimensions %d\n",cudaDeviceProp.maxTextureCubemapLayered[0]);
printf("Maximum Cubemap layered texture dimensions %d\n",cudaDeviceProp.maxTextureCubemapLayered[1]);
printf("Maximum size of each dimension of a block %d\n",cudaDeviceProp.maxThreadsDim[0]);
printf("Maximum size of each dimension of a block %d\n",cudaDeviceProp.maxThreadsDim[1]);
printf("Maximum size of each dimension of a block %d\n",cudaDeviceProp.maxThreadsDim[2]);
printf("Maximum number of threads per block %d\n",cudaDeviceProp.maxThreadsPerBlock);
printf("Maximum resident threads per multiprocessor %d\n",cudaDeviceProp.maxThreadsPerMultiProcessor);
printf("Maximum pitch in bytes allowed by memory copies %d\n",cudaDeviceProp.memPitch);
printf("Global memory bus width in bits %d\n",cudaDeviceProp.memoryBusWidth);
printf("Peak memory clock frequency in kilohertz %d\n",cudaDeviceProp.memoryClockRate);
printf("Minor compute capability %d\n",cudaDeviceProp.minor);
printf("Number of multiprocessors on device %d\n",cudaDeviceProp.multiProcessorCount);
printf("PCI bus ID of the device %d\n",cudaDeviceProp.pciBusID);
printf("PCI device ID of the device %d\n",cudaDeviceProp.pciDeviceID);
printf("PCI domain ID of the device %d\n",cudaDeviceProp.pciDomainID);
printf("32-bit registers available per block %d\n",cudaDeviceProp.regsPerBlock);
printf("Shared memory available per block in bytes %d\n",cudaDeviceProp.sharedMemPerBlock);
printf("Device supports stream priorities %d\n",cudaDeviceProp.streamPrioritiesSupported);
printf("Alignment requirements for surfaces %d\n",cudaDeviceProp.surfaceAlignment);
printf("1 if device is a Tesla device using TCC driver, 0 otherwise %d\n",cudaDeviceProp.tccDriver);
printf("Alignment requirement for textures %d\n",cudaDeviceProp.textureAlignment);
printf("Pitch alignment requirement for texture references bound to pitched memory %d\n",cudaDeviceProp.texturePitchAlignment);
printf("Constant memory available on device in bytes %d\n",cudaDeviceProp.totalConstMem);
printf("Global memory available on device in bytes %d\n",cudaDeviceProp.totalGlobalMem);
printf("Device shares a unified address space with the host %d\n",cudaDeviceProp.unifiedAddressing);
printf("Warp size in threads %d\n",cudaDeviceProp.warpSize);
fflush(stdout);
}
host_floyd(gridSize, blockSize, matrix, intermedian, n);
cudaDeviceReset();
/* Bыводим результаты */
fs = fopen(outputFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", outputFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (matrix[i*n + j] != LONG_MAX)
fprintf(fs, "%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
/* Bыводим результаты */
fs = fopen(intermedianFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", intermedianFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (intermedian[i*n + j] >= 0)
fprintf(fs, "%d%s", intermedian[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
free(matrix);
free(intermedian);
exit(0);
}
|
char *title = "Floyd's algorithm";
char *description = "Алгоритм Флойда - поиск всех кратчайших путей в графе";
/*
Алгоритм Флойда является одним из методов поиска кратчайших путей в графе.
В отличии от алгоритма Дейкстры, который позволяет при доведении до конца построить
ориентированное дерево кратчайших путей от некоторой вершины, метод Флойда позволяет
найти длины всех кратчайших путей в графе. Конечно эта задача может быть решена
и многократным применением алгоритма Дейкстры (каждый раз последовательно выбираем
вершину от первой до N-ной, пока не получим кратчайшие пути от всех вершин графа),
однако реализация подобной процедуры потребовала бы значительных вычислительных затрат.
Прежде чем представлять алгоритмы, необходимо ввести некоторые обозначения.
Перенумеруем вершины исходного графа целыми числами от 1 до N. Обозначим через di,jm длину кратчайшего пути
из вершинм i в вершину j, который в качестве промежуточных может содержать только первые m вершин графа.
(Напомним, что промежуточной вершиной пути является любая принадлежащая ему вершина, не совпадающая
с его начальной или конечной вершинами.) Если между вершинами i и j не существует ни одного пути указанного типа,
то условно будем считать, что di,jm=∞. Из данного определения величин di,jm следует, что величина di,j0,
представляет длину кратчайшего пути из вершины i в вершину j, не имеющего промежуточных вершин,
т. е. длину кратчайшей дуги, соединяющей i с j (если такие дуги присутствуют в графе).
для любой вершины i положим di,im= 0. Отметим далее, что величина di,jmпредставляет длину кратчайшего пути
между вершинами i и j.
Обозначим через Dm матрицу размера NxN, элемент (i, j) которой совпадает с di,jm.
Если в исходном графе нам известна длина каждой дуги, то мы можем сформировать матрицу D0.
Наша цель состоит в определении матрицы DN, представляющей кратчайшие пути между всеми вершинами рассматриваемого графа.
В алгоритме Флойда в качестве исходной выступает матрица D0.
Вначале из этой матрицы вычисляется матрица D1.
Затем по матрице D1 вычисляется матрицав D2 и т. д.
Процесс повторяется до тех пор, пока по матрице DN-1 не будет вычислена матрица DN.
Рассмотрим основную идею, лежащую в основе алгоритма Флойда.
Суть алгоритма Флойда заключается в проверке того, не окажется ли путь из вершины i в вершину j короче,
если он будет проходить через некоторую промежуточную вершину m. Предположим, что нам известны:
кратчайший путь из вершины i в вершину m, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины m в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины i в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин.
Поскольку по предположению исходный граф не может содержать контуров отрицательной длины,
один из двух путей — путь, совпадающий с представленным в пункте 3, или путь, являющийся объединением
путей из пунктов 1 и 2 — должен быть кратчайшим путем из вершины i в вершину j,
в котором в качестве промежуточных допускается использование только первых m вершин. Таким образом,
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
Из соотношения видно, что для вычисления элементов матрицы Dm необходимо располагать лишь элементами матрицы Dm-1.
Более того, соответствующие вычисления могут быть проведены без обращения к исходному графу.
Теперь мм в состоянии дать формальное описание алгоритма Флойда для нахождения на графе кратчайших путей
между всеми парами вершин.
Алгоритм
Перенумеровать вершины графа от 1 до N целыми числами, определить матрицу D0, каждый элемент di,j
которой есть длина кратчайшей дуги между вершинами i и j. Если такой дуги нет, положить значение элемента
равным ∞. Кроме того, положить значения диагонального элемента di,iравным 0.
Для целого m, последовательно принимающего значения 1...N определить по элементам матрицы Dm-1 элементы Dm
Алгоритм заканчивается получением матрицы всех кратчайших путей DN, N – число вершин графа.
Напомним, для определения по известным элементам матрицы Dm-1 элементов матрицы Dm
в алгоритме Флойда применяется рекурсивное соотношение:
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
di,jm – элемент матрицы Dm, di,jm-1 – элементы матрицы Dm-1 найденой на предыдущем шаге алгоритма.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <ctype.h>
#include <limits.h>
#include <hip/hip_runtime.h>
#define assert( bool )
int strempty(const char *p)
{
if (!p)
return (1);
for (; *p; p++)
if (!isspace(*p))
return (0);
return (1);
}
char *mystrtok(char **m, char *s, char c)
{
char *p = s ? s : *m;
if (!*p)
return 0;
*m = strchr(p, c);
if (*m)
*(*m)++ = 0;
else
*m = p + strlen(p);
return p;
}
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
__global__ void global_init(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
intermedian[id] = -1;
}
}
__global__ void global_floyd(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
int i = id/n;
int j = id%n;
if(i != j && prev[i*n+m] != LONG_MAX && prev[m*n+j] != LONG_MAX && (prev[i*n+m] + prev[m*n+j]) < prev[i*n+j]){
next[id] = prev[i*n+m] + prev[m*n+j];
intermedian[id] = m;
}
else {
next[id] = prev[id];
}
}
}
__host__ void host_floyd(int gridSize, int blockSize, long *matrix, int *intermedian, int n)
{
hipError_t err;
long *device_prev;
long *device_next;
int *device_intermedian;
err = hipMalloc((void**)&device_prev, n*n * sizeof(long));
err = hipMalloc((void**)&device_next, n*n * sizeof(long));
err = hipMalloc((void**)&device_intermedian, n*n * sizeof(int));
err = hipMemcpy(device_prev, matrix, n*n*sizeof(long), hipMemcpyHostToDevice);
int blocks = (gridSize > 0)? gridSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
int threads = (blockSize > 0)? blockSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
global_init <<< blocks, threads >>>(device_prev, device_next, device_intermedian, -1, n);
for(int m = 0; m < n ; m++){
global_floyd <<< blocks, threads >>>(device_prev, device_next, device_intermedian, m, n);
err = hipMemcpy(matrix, device_next, n*n*sizeof(long), hipMemcpyDeviceToHost);
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
}
}
printf("\n");
long * t = device_prev; device_prev = device_next; device_next = t;
}
err = hipMemcpy(matrix, device_prev, n*n*sizeof(long), hipMemcpyDeviceToHost);
err = hipMemcpy(intermedian, device_intermedian, n*n*sizeof(int), hipMemcpyDeviceToHost);
err = hipFree(device_prev);
err = hipFree(device_next);
err = hipFree(device_intermedian);
err = err;
}
int main(int argc, char* argv[])
{
int gridSize = 0;
int blockSize = 0;
printf("Title :\t%s\n", title); fflush(stdout);
if (argc < 4) {
printf("Usage :\t%s [-g <gridSize>] [-b <blockSize>] <inputfilename> <outputfilename> <intermedianfilename>\n", argv[0]); fflush(stdout);
printf("\tinputfilename - source matrix of path prices or empty\n"); fflush(stdout);
printf("\toutputfilename - output floyd's matrix of path prices\n"); fflush(stdout);
printf("\tintermedianfilename - output matrix of intermedian points or empty\n"); fflush(stdout);
exit(-1);
}
int argId = 1;
for(; argId < argc && argv[argId][0]=='-' ; argId++){
switch(argv[argId][1]){
case 'g':
gridSize = atoi(argv[++argId]);
break;
case 'b':
blockSize = atoi(argv[++argId]);
break;
}
}
char *inputFileName = argv[argId++];
char *outputFileName = argv[argId++];
char *intermedianFileName = argv[argId++];
printf("Input File Name :\t%s\n", inputFileName); fflush(stdout);
printf("Output File Name :\t%s\n", outputFileName); fflush(stdout);
printf("Intermedian File Name :\t%s\n", intermedianFileName); fflush(stdout);
char buffer[4096];
char *tok;
char *p;
int n; /* Ранг текущего массива */
long *matrix; /* Массив цен */
int *intermedian; /* Массивов промежуточных точек */
int i, j;
FILE *fs = fopen(inputFileName, "r");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", inputFileName); fflush(stderr);
exit(-1);
}
n = 0;
/* Заполняем массив числами из файла */
/* Операция выполняетя только на хост процессе */
/* Операция выполняетя в два прохода по файлу */
/* На первом проходе определяется ранг матрицы */
/* На втором проходе считываются данные */
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
j++;
}
n = max(n, j);
}
n = max(n, i);
matrix = (long *)malloc(n*n*sizeof(long));
intermedian = (int *)malloc(n*n*sizeof(int));
fseek(fs, 0, SEEK_SET);
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
/* Пустые элементы - это запрещённые пути */
matrix[n*i + j++] = strempty(tok) ? LONG_MAX : atol(tok);
}
for (; j < n; j++) matrix[n*i + j] = LONG_MAX;
}
for (j = 0; j < (n - i)*n; j++) matrix[n*i + j] = LONG_MAX;
for (i = 0; i < n; i++) matrix[n*i + i] = LONG_MAX; /* Запрещаем петли */
fclose(fs);
printf("Matrix rank :\t%d\n", n);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : "\t"));
}
}
fflush(stdout);
// Find/set the device.
int device_size = 0;
hipGetDeviceCount(&device_size);
for (i = 0; i < device_size; ++i)
{
hipDeviceProp_t hipDeviceProp_t;
hipGetDeviceProperties(&hipDeviceProp_t, i);
printf("Running on GPU %d (%s)\n", i, hipDeviceProp_t.name);
printf("Device has ECC support enabled %d\n",hipDeviceProp_t.ECCEnabled);
printf("Number of asynchronous engines %d\n",hipDeviceProp_t.asyncEngineCount);
printf("Device can map host memory with cudaHostAlloc/cudaHostGetDevicePointer %d\n",hipDeviceProp_t.canMapHostMemory);
printf("Clock frequency in kilohertz %d\n",hipDeviceProp_t.clockRate);
printf("Compute mode (See cudaComputeMode) %d\n",hipDeviceProp_t.computeMode);
printf("Device can possibly execute multiple kernels concurrently %d\n",hipDeviceProp_t.concurrentKernels);
printf("Device can concurrently copy memory and execute a kernel. Deprecated. Use instead asyncEngineCount. %d\n",hipDeviceProp_t.deviceOverlap);
printf("Device is integrated as opposed to discrete %d\n",hipDeviceProp_t.integrated);
printf("Specified whether there is a run time limit on kernels %d\n",hipDeviceProp_t.kernelExecTimeoutEnabled);
printf("Size of L2 cache in bytes %d\n",hipDeviceProp_t.l2CacheSize);
printf("Major compute capability %d\n",hipDeviceProp_t.major);
printf("Maximum size of each dimension of a grid %d\n",hipDeviceProp_t.maxGridSize[0]);
printf("Maximum size of each dimension of a grid %d\n",hipDeviceProp_t.maxGridSize[1]);
printf("Maximum size of each dimension of a grid %d\n",hipDeviceProp_t.maxGridSize[2]);
printf("Maximum 1D surface size %d\n",hipDeviceProp_t.maxSurface1D);
printf("Maximum 1D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface1DLayered[0]);
printf("Maximum 1D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface1DLayered[1]);
printf("Maximum 2D surface dimensions %d\n",hipDeviceProp_t.maxSurface2D[0]);
printf("Maximum 2D surface dimensions %d\n",hipDeviceProp_t.maxSurface2D[1]);
printf("Maximum 2D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface2DLayered[0]);
printf("Maximum 2D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface2DLayered[1]);
printf("Maximum 2D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface2DLayered[2]);
printf("Maximum 3D surface dimensions %d\n",hipDeviceProp_t.maxSurface3D[0]);
printf("Maximum 3D surface dimensions %d\n",hipDeviceProp_t.maxSurface3D[1]);
printf("Maximum 3D surface dimensions %d\n",hipDeviceProp_t.maxSurface3D[2]);
printf("Maximum Cubemap surface dimensions %d\n",hipDeviceProp_t.maxSurfaceCubemap);
printf("Maximum Cubemap layered surface dimensions %d\n",hipDeviceProp_t.maxSurfaceCubemapLayered[0]);
printf("Maximum Cubemap layered surface dimensions %d\n",hipDeviceProp_t.maxSurfaceCubemapLayered[1]);
printf("Maximum 1D texture size %d\n",hipDeviceProp_t.maxTexture1D);
printf("Maximum 1D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture1DLayered[0]);
printf("Maximum 1D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture1DLayered[1]);
printf("Maximum size for 1D textures bound to linear memory %d\n",hipDeviceProp_t.maxTexture1DLinear);
printf("Maximum 1D mipmapped texture size %d\n",hipDeviceProp_t.maxTexture1DMipmap);
printf("Maximum 2D texture dimensions %d\n",hipDeviceProp_t.maxTexture2D[0]);
printf("Maximum 2D texture dimensions %d\n",hipDeviceProp_t.maxTexture2D[1]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",hipDeviceProp_t.maxTexture2DGather[0]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",hipDeviceProp_t.maxTexture2DGather[1]);
printf("Maximum 2D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture2DLayered[0]);
printf("Maximum 2D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture2DLayered[1]);
printf("Maximum 2D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture2DLayered[2]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",hipDeviceProp_t.maxTexture2DLinear[0]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",hipDeviceProp_t.maxTexture2DLinear[1]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",hipDeviceProp_t.maxTexture2DLinear[2]);
printf("Maximum 2D mipmapped texture dimensions %d\n",hipDeviceProp_t.maxTexture2DMipmap[0]);
printf("Maximum 2D mipmapped texture dimensions %d\n",hipDeviceProp_t.maxTexture2DMipmap[1]);
printf("Maximum 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3D[0]);
printf("Maximum 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3D[1]);
printf("Maximum 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3D[2]);
printf("Maximum alternate 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3DAlt[0]);
printf("Maximum alternate 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3DAlt[1]);
printf("Maximum alternate 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3DAlt[2]);
printf("Maximum Cubemap texture dimensions %d\n",hipDeviceProp_t.maxTextureCubemap);
printf("Maximum Cubemap layered texture dimensions %d\n",hipDeviceProp_t.maxTextureCubemapLayered[0]);
printf("Maximum Cubemap layered texture dimensions %d\n",hipDeviceProp_t.maxTextureCubemapLayered[1]);
printf("Maximum size of each dimension of a block %d\n",hipDeviceProp_t.maxThreadsDim[0]);
printf("Maximum size of each dimension of a block %d\n",hipDeviceProp_t.maxThreadsDim[1]);
printf("Maximum size of each dimension of a block %d\n",hipDeviceProp_t.maxThreadsDim[2]);
printf("Maximum number of threads per block %d\n",hipDeviceProp_t.maxThreadsPerBlock);
printf("Maximum resident threads per multiprocessor %d\n",hipDeviceProp_t.maxThreadsPerMultiProcessor);
printf("Maximum pitch in bytes allowed by memory copies %d\n",hipDeviceProp_t.memPitch);
printf("Global memory bus width in bits %d\n",hipDeviceProp_t.memoryBusWidth);
printf("Peak memory clock frequency in kilohertz %d\n",hipDeviceProp_t.memoryClockRate);
printf("Minor compute capability %d\n",hipDeviceProp_t.minor);
printf("Number of multiprocessors on device %d\n",hipDeviceProp_t.multiProcessorCount);
printf("PCI bus ID of the device %d\n",hipDeviceProp_t.pciBusID);
printf("PCI device ID of the device %d\n",hipDeviceProp_t.pciDeviceID);
printf("PCI domain ID of the device %d\n",hipDeviceProp_t.pciDomainID);
printf("32-bit registers available per block %d\n",hipDeviceProp_t.regsPerBlock);
printf("Shared memory available per block in bytes %d\n",hipDeviceProp_t.sharedMemPerBlock);
printf("Device supports stream priorities %d\n",hipDeviceProp_t.streamPrioritiesSupported);
printf("Alignment requirements for surfaces %d\n",hipDeviceProp_t.surfaceAlignment);
printf("1 if device is a Tesla device using TCC driver, 0 otherwise %d\n",hipDeviceProp_t.tccDriver);
printf("Alignment requirement for textures %d\n",hipDeviceProp_t.textureAlignment);
printf("Pitch alignment requirement for texture references bound to pitched memory %d\n",hipDeviceProp_t.texturePitchAlignment);
printf("Constant memory available on device in bytes %d\n",hipDeviceProp_t.totalConstMem);
printf("Global memory available on device in bytes %d\n",hipDeviceProp_t.totalGlobalMem);
printf("Device shares a unified address space with the host %d\n",hipDeviceProp_t.unifiedAddressing);
printf("Warp size in threads %d\n",hipDeviceProp_t.warpSize);
fflush(stdout);
}
host_floyd(gridSize, blockSize, matrix, intermedian, n);
hipDeviceReset();
/* Bыводим результаты */
fs = fopen(outputFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", outputFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (matrix[i*n + j] != LONG_MAX)
fprintf(fs, "%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
/* Bыводим результаты */
fs = fopen(intermedianFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", intermedianFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (intermedian[i*n + j] >= 0)
fprintf(fs, "%d%s", intermedian[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
free(matrix);
free(intermedian);
exit(0);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
char *title = "Floyd's algorithm";
char *description = "Алгоритм Флойда - поиск всех кратчайших путей в графе";
/*
Алгоритм Флойда является одним из методов поиска кратчайших путей в графе.
В отличии от алгоритма Дейкстры, который позволяет при доведении до конца построить
ориентированное дерево кратчайших путей от некоторой вершины, метод Флойда позволяет
найти длины всех кратчайших путей в графе. Конечно эта задача может быть решена
и многократным применением алгоритма Дейкстры (каждый раз последовательно выбираем
вершину от первой до N-ной, пока не получим кратчайшие пути от всех вершин графа),
однако реализация подобной процедуры потребовала бы значительных вычислительных затрат.
Прежде чем представлять алгоритмы, необходимо ввести некоторые обозначения.
Перенумеруем вершины исходного графа целыми числами от 1 до N. Обозначим через di,jm длину кратчайшего пути
из вершинм i в вершину j, который в качестве промежуточных может содержать только первые m вершин графа.
(Напомним, что промежуточной вершиной пути является любая принадлежащая ему вершина, не совпадающая
с его начальной или конечной вершинами.) Если между вершинами i и j не существует ни одного пути указанного типа,
то условно будем считать, что di,jm=∞. Из данного определения величин di,jm следует, что величина di,j0,
представляет длину кратчайшего пути из вершины i в вершину j, не имеющего промежуточных вершин,
т. е. длину кратчайшей дуги, соединяющей i с j (если такие дуги присутствуют в графе).
для любой вершины i положим di,im= 0. Отметим далее, что величина di,jmпредставляет длину кратчайшего пути
между вершинами i и j.
Обозначим через Dm матрицу размера NxN, элемент (i, j) которой совпадает с di,jm.
Если в исходном графе нам известна длина каждой дуги, то мы можем сформировать матрицу D0.
Наша цель состоит в определении матрицы DN, представляющей кратчайшие пути между всеми вершинами рассматриваемого графа.
В алгоритме Флойда в качестве исходной выступает матрица D0.
Вначале из этой матрицы вычисляется матрица D1.
Затем по матрице D1 вычисляется матрицав D2 и т. д.
Процесс повторяется до тех пор, пока по матрице DN-1 не будет вычислена матрица DN.
Рассмотрим основную идею, лежащую в основе алгоритма Флойда.
Суть алгоритма Флойда заключается в проверке того, не окажется ли путь из вершины i в вершину j короче,
если он будет проходить через некоторую промежуточную вершину m. Предположим, что нам известны:
кратчайший путь из вершины i в вершину m, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины m в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин;
кратчайший путь из вершины i в вершину j, в котором в качестве промежуточных допускается использование только первых (m - 1) вершин.
Поскольку по предположению исходный граф не может содержать контуров отрицательной длины,
один из двух путей — путь, совпадающий с представленным в пункте 3, или путь, являющийся объединением
путей из пунктов 1 и 2 — должен быть кратчайшим путем из вершины i в вершину j,
в котором в качестве промежуточных допускается использование только первых m вершин. Таким образом,
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
Из соотношения видно, что для вычисления элементов матрицы Dm необходимо располагать лишь элементами матрицы Dm-1.
Более того, соответствующие вычисления могут быть проведены без обращения к исходному графу.
Теперь мм в состоянии дать формальное описание алгоритма Флойда для нахождения на графе кратчайших путей
между всеми парами вершин.
Алгоритм
Перенумеровать вершины графа от 1 до N целыми числами, определить матрицу D0, каждый элемент di,j
которой есть длина кратчайшей дуги между вершинами i и j. Если такой дуги нет, положить значение элемента
равным ∞. Кроме того, положить значения диагонального элемента di,iравным 0.
Для целого m, последовательно принимающего значения 1...N определить по элементам матрицы Dm-1 элементы Dm
Алгоритм заканчивается получением матрицы всех кратчайших путей DN, N – число вершин графа.
Напомним, для определения по известным элементам матрицы Dm-1 элементов матрицы Dm
в алгоритме Флойда применяется рекурсивное соотношение:
di,jm=min{ di,mm-1+ dm,jm-1; di,jm-1}
di,jm – элемент матрицы Dm, di,jm-1 – элементы матрицы Dm-1 найденой на предыдущем шаге алгоритма.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <ctype.h>
#include <limits.h>
#include <hip/hip_runtime.h>
#define assert( bool )
int strempty(const char *p)
{
if (!p)
return (1);
for (; *p; p++)
if (!isspace(*p))
return (0);
return (1);
}
char *mystrtok(char **m, char *s, char c)
{
char *p = s ? s : *m;
if (!*p)
return 0;
*m = strchr(p, c);
if (*m)
*(*m)++ = 0;
else
*m = p + strlen(p);
return p;
}
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
__global__ void global_init(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
intermedian[id] = -1;
}
}
__global__ void global_floyd(long *prev, long *next, int *intermedian, int m, int n){
for (int id = blockDim.x*blockIdx.x + threadIdx.x; id < n*n; id += blockDim.x*gridDim.x) {
int i = id/n;
int j = id%n;
if(i != j && prev[i*n+m] != LONG_MAX && prev[m*n+j] != LONG_MAX && (prev[i*n+m] + prev[m*n+j]) < prev[i*n+j]){
next[id] = prev[i*n+m] + prev[m*n+j];
intermedian[id] = m;
}
else {
next[id] = prev[id];
}
}
}
__host__ void host_floyd(int gridSize, int blockSize, long *matrix, int *intermedian, int n)
{
hipError_t err;
long *device_prev;
long *device_next;
int *device_intermedian;
err = hipMalloc((void**)&device_prev, n*n * sizeof(long));
err = hipMalloc((void**)&device_next, n*n * sizeof(long));
err = hipMalloc((void**)&device_intermedian, n*n * sizeof(int));
err = hipMemcpy(device_prev, matrix, n*n*sizeof(long), hipMemcpyHostToDevice);
int blocks = (gridSize > 0)? gridSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
int threads = (blockSize > 0)? blockSize : min(max(1, (int)pow((double)n*n, 0.333333333333333)), 15);
global_init <<< blocks, threads >>>(device_prev, device_next, device_intermedian, -1, n);
for(int m = 0; m < n ; m++){
global_floyd <<< blocks, threads >>>(device_prev, device_next, device_intermedian, m, n);
err = hipMemcpy(matrix, device_next, n*n*sizeof(long), hipMemcpyDeviceToHost);
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
}
}
printf("\n");
long * t = device_prev; device_prev = device_next; device_next = t;
}
err = hipMemcpy(matrix, device_prev, n*n*sizeof(long), hipMemcpyDeviceToHost);
err = hipMemcpy(intermedian, device_intermedian, n*n*sizeof(int), hipMemcpyDeviceToHost);
err = hipFree(device_prev);
err = hipFree(device_next);
err = hipFree(device_intermedian);
err = err;
}
int main(int argc, char* argv[])
{
int gridSize = 0;
int blockSize = 0;
printf("Title :\t%s\n", title); fflush(stdout);
if (argc < 4) {
printf("Usage :\t%s [-g <gridSize>] [-b <blockSize>] <inputfilename> <outputfilename> <intermedianfilename>\n", argv[0]); fflush(stdout);
printf("\tinputfilename - source matrix of path prices or empty\n"); fflush(stdout);
printf("\toutputfilename - output floyd's matrix of path prices\n"); fflush(stdout);
printf("\tintermedianfilename - output matrix of intermedian points or empty\n"); fflush(stdout);
exit(-1);
}
int argId = 1;
for(; argId < argc && argv[argId][0]=='-' ; argId++){
switch(argv[argId][1]){
case 'g':
gridSize = atoi(argv[++argId]);
break;
case 'b':
blockSize = atoi(argv[++argId]);
break;
}
}
char *inputFileName = argv[argId++];
char *outputFileName = argv[argId++];
char *intermedianFileName = argv[argId++];
printf("Input File Name :\t%s\n", inputFileName); fflush(stdout);
printf("Output File Name :\t%s\n", outputFileName); fflush(stdout);
printf("Intermedian File Name :\t%s\n", intermedianFileName); fflush(stdout);
char buffer[4096];
char *tok;
char *p;
int n; /* Ранг текущего массива */
long *matrix; /* Массив цен */
int *intermedian; /* Массивов промежуточных точек */
int i, j;
FILE *fs = fopen(inputFileName, "r");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", inputFileName); fflush(stderr);
exit(-1);
}
n = 0;
/* Заполняем массив числами из файла */
/* Операция выполняетя только на хост процессе */
/* Операция выполняетя в два прохода по файлу */
/* На первом проходе определяется ранг матрицы */
/* На втором проходе считываются данные */
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
j++;
}
n = max(n, j);
}
n = max(n, i);
matrix = (long *)malloc(n*n*sizeof(long));
intermedian = (int *)malloc(n*n*sizeof(int));
fseek(fs, 0, SEEK_SET);
for (i = 0; (tok = fgets(buffer, sizeof(buffer), fs)) != NULL; i++)
{
j = 0;
for (tok = mystrtok(&p, tok, ';'); tok != NULL; tok = mystrtok(&p, NULL, ';'))
{
/* Пустые элементы - это запрещённые пути */
matrix[n*i + j++] = strempty(tok) ? LONG_MAX : atol(tok);
}
for (; j < n; j++) matrix[n*i + j] = LONG_MAX;
}
for (j = 0; j < (n - i)*n; j++) matrix[n*i + j] = LONG_MAX;
for (i = 0; i < n; i++) matrix[n*i + i] = LONG_MAX; /* Запрещаем петли */
fclose(fs);
printf("Matrix rank :\t%d\n", n);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
printf("%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : "\t"));
}
}
fflush(stdout);
// Find/set the device.
int device_size = 0;
hipGetDeviceCount(&device_size);
for (i = 0; i < device_size; ++i)
{
hipDeviceProp_t hipDeviceProp_t;
hipGetDeviceProperties(&hipDeviceProp_t, i);
printf("Running on GPU %d (%s)\n", i, hipDeviceProp_t.name);
printf("Device has ECC support enabled %d\n",hipDeviceProp_t.ECCEnabled);
printf("Number of asynchronous engines %d\n",hipDeviceProp_t.asyncEngineCount);
printf("Device can map host memory with cudaHostAlloc/cudaHostGetDevicePointer %d\n",hipDeviceProp_t.canMapHostMemory);
printf("Clock frequency in kilohertz %d\n",hipDeviceProp_t.clockRate);
printf("Compute mode (See cudaComputeMode) %d\n",hipDeviceProp_t.computeMode);
printf("Device can possibly execute multiple kernels concurrently %d\n",hipDeviceProp_t.concurrentKernels);
printf("Device can concurrently copy memory and execute a kernel. Deprecated. Use instead asyncEngineCount. %d\n",hipDeviceProp_t.deviceOverlap);
printf("Device is integrated as opposed to discrete %d\n",hipDeviceProp_t.integrated);
printf("Specified whether there is a run time limit on kernels %d\n",hipDeviceProp_t.kernelExecTimeoutEnabled);
printf("Size of L2 cache in bytes %d\n",hipDeviceProp_t.l2CacheSize);
printf("Major compute capability %d\n",hipDeviceProp_t.major);
printf("Maximum size of each dimension of a grid %d\n",hipDeviceProp_t.maxGridSize[0]);
printf("Maximum size of each dimension of a grid %d\n",hipDeviceProp_t.maxGridSize[1]);
printf("Maximum size of each dimension of a grid %d\n",hipDeviceProp_t.maxGridSize[2]);
printf("Maximum 1D surface size %d\n",hipDeviceProp_t.maxSurface1D);
printf("Maximum 1D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface1DLayered[0]);
printf("Maximum 1D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface1DLayered[1]);
printf("Maximum 2D surface dimensions %d\n",hipDeviceProp_t.maxSurface2D[0]);
printf("Maximum 2D surface dimensions %d\n",hipDeviceProp_t.maxSurface2D[1]);
printf("Maximum 2D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface2DLayered[0]);
printf("Maximum 2D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface2DLayered[1]);
printf("Maximum 2D layered surface dimensions %d\n",hipDeviceProp_t.maxSurface2DLayered[2]);
printf("Maximum 3D surface dimensions %d\n",hipDeviceProp_t.maxSurface3D[0]);
printf("Maximum 3D surface dimensions %d\n",hipDeviceProp_t.maxSurface3D[1]);
printf("Maximum 3D surface dimensions %d\n",hipDeviceProp_t.maxSurface3D[2]);
printf("Maximum Cubemap surface dimensions %d\n",hipDeviceProp_t.maxSurfaceCubemap);
printf("Maximum Cubemap layered surface dimensions %d\n",hipDeviceProp_t.maxSurfaceCubemapLayered[0]);
printf("Maximum Cubemap layered surface dimensions %d\n",hipDeviceProp_t.maxSurfaceCubemapLayered[1]);
printf("Maximum 1D texture size %d\n",hipDeviceProp_t.maxTexture1D);
printf("Maximum 1D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture1DLayered[0]);
printf("Maximum 1D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture1DLayered[1]);
printf("Maximum size for 1D textures bound to linear memory %d\n",hipDeviceProp_t.maxTexture1DLinear);
printf("Maximum 1D mipmapped texture size %d\n",hipDeviceProp_t.maxTexture1DMipmap);
printf("Maximum 2D texture dimensions %d\n",hipDeviceProp_t.maxTexture2D[0]);
printf("Maximum 2D texture dimensions %d\n",hipDeviceProp_t.maxTexture2D[1]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",hipDeviceProp_t.maxTexture2DGather[0]);
printf("Maximum 2D texture dimensions if texture gather operations have to be performed %d\n",hipDeviceProp_t.maxTexture2DGather[1]);
printf("Maximum 2D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture2DLayered[0]);
printf("Maximum 2D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture2DLayered[1]);
printf("Maximum 2D layered texture dimensions %d\n",hipDeviceProp_t.maxTexture2DLayered[2]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",hipDeviceProp_t.maxTexture2DLinear[0]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",hipDeviceProp_t.maxTexture2DLinear[1]);
printf("Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory %d\n",hipDeviceProp_t.maxTexture2DLinear[2]);
printf("Maximum 2D mipmapped texture dimensions %d\n",hipDeviceProp_t.maxTexture2DMipmap[0]);
printf("Maximum 2D mipmapped texture dimensions %d\n",hipDeviceProp_t.maxTexture2DMipmap[1]);
printf("Maximum 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3D[0]);
printf("Maximum 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3D[1]);
printf("Maximum 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3D[2]);
printf("Maximum alternate 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3DAlt[0]);
printf("Maximum alternate 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3DAlt[1]);
printf("Maximum alternate 3D texture dimensions %d\n",hipDeviceProp_t.maxTexture3DAlt[2]);
printf("Maximum Cubemap texture dimensions %d\n",hipDeviceProp_t.maxTextureCubemap);
printf("Maximum Cubemap layered texture dimensions %d\n",hipDeviceProp_t.maxTextureCubemapLayered[0]);
printf("Maximum Cubemap layered texture dimensions %d\n",hipDeviceProp_t.maxTextureCubemapLayered[1]);
printf("Maximum size of each dimension of a block %d\n",hipDeviceProp_t.maxThreadsDim[0]);
printf("Maximum size of each dimension of a block %d\n",hipDeviceProp_t.maxThreadsDim[1]);
printf("Maximum size of each dimension of a block %d\n",hipDeviceProp_t.maxThreadsDim[2]);
printf("Maximum number of threads per block %d\n",hipDeviceProp_t.maxThreadsPerBlock);
printf("Maximum resident threads per multiprocessor %d\n",hipDeviceProp_t.maxThreadsPerMultiProcessor);
printf("Maximum pitch in bytes allowed by memory copies %d\n",hipDeviceProp_t.memPitch);
printf("Global memory bus width in bits %d\n",hipDeviceProp_t.memoryBusWidth);
printf("Peak memory clock frequency in kilohertz %d\n",hipDeviceProp_t.memoryClockRate);
printf("Minor compute capability %d\n",hipDeviceProp_t.minor);
printf("Number of multiprocessors on device %d\n",hipDeviceProp_t.multiProcessorCount);
printf("PCI bus ID of the device %d\n",hipDeviceProp_t.pciBusID);
printf("PCI device ID of the device %d\n",hipDeviceProp_t.pciDeviceID);
printf("PCI domain ID of the device %d\n",hipDeviceProp_t.pciDomainID);
printf("32-bit registers available per block %d\n",hipDeviceProp_t.regsPerBlock);
printf("Shared memory available per block in bytes %d\n",hipDeviceProp_t.sharedMemPerBlock);
printf("Device supports stream priorities %d\n",hipDeviceProp_t.streamPrioritiesSupported);
printf("Alignment requirements for surfaces %d\n",hipDeviceProp_t.surfaceAlignment);
printf("1 if device is a Tesla device using TCC driver, 0 otherwise %d\n",hipDeviceProp_t.tccDriver);
printf("Alignment requirement for textures %d\n",hipDeviceProp_t.textureAlignment);
printf("Pitch alignment requirement for texture references bound to pitched memory %d\n",hipDeviceProp_t.texturePitchAlignment);
printf("Constant memory available on device in bytes %d\n",hipDeviceProp_t.totalConstMem);
printf("Global memory available on device in bytes %d\n",hipDeviceProp_t.totalGlobalMem);
printf("Device shares a unified address space with the host %d\n",hipDeviceProp_t.unifiedAddressing);
printf("Warp size in threads %d\n",hipDeviceProp_t.warpSize);
fflush(stdout);
}
host_floyd(gridSize, blockSize, matrix, intermedian, n);
hipDeviceReset();
/* Bыводим результаты */
fs = fopen(outputFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", outputFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (matrix[i*n + j] != LONG_MAX)
fprintf(fs, "%ld%s", matrix[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
/* Bыводим результаты */
fs = fopen(intermedianFileName, "w");
if (fs == NULL) {
fprintf(stderr, "File open error (%s)\n", intermedianFileName); fflush(stderr);
exit(-1);
}
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
if (intermedian[i*n + j] >= 0)
fprintf(fs, "%d%s", intermedian[i*n + j], ((j == n - 1) ? "\n" : ";"));
else
fprintf(fs, "%s", ((j == n - 1) ? "\n" : ";"));
}
}
fclose(fs);
free(matrix);
free(intermedian);
exit(0);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11global_initPlS_Piii
.globl _Z11global_initPlS_Piii
.p2align 8
.type _Z11global_initPlS_Piii,@function
_Z11global_initPlS_Piii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x1c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mul_i32 s4, s6, s6
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11global_initPlS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11global_initPlS_Piii, .Lfunc_end0-_Z11global_initPlS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12global_floydPlS_Piii
.globl _Z12global_floydPlS_Piii
.p2align 8
.type _Z12global_floydPlS_Piii,@function
_Z12global_floydPlS_Piii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x1c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_mul_i32 s12, s9, s9
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_13
s_ashr_i32 s13, s9, 31
s_load_b32 s11, s[2:3], 0x0
s_add_i32 s4, s9, s13
s_mov_b32 s15, 0
s_xor_b32 s14, s4, s13
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_u32_e32 v0, s14
s_sub_i32 s8, 0, s14
s_sub_i32 s16, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, s8, v0
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s11, s10
s_brev_b32 s11, -2
s_mov_b32 s10, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s15, vcc_lo, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB1_13
.LBB1_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v2
v_xor_b32_e32 v3, v3, v2
v_xor_b32_e32 v2, s13, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v0
v_mul_lo_u32 v5, v4, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_subrev_nc_u32_e32 v6, s14, v3
v_cmp_le_u32_e32 vcc_lo, s14, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v6
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s14, v3
v_cndmask_b32_e32 v3, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v3, v2
v_sub_nc_u32_e32 v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, s16, v3, v[1:2]
v_cmp_eq_u32_e64 s17, v6, v3
v_cmpx_ne_u32_e64 v6, v3
s_cbranch_execz .LBB1_11
v_mad_u64_u32 v[6:7], null, v3, s9, s[8:9]
s_mov_b32 s19, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, s[10:11], v[3:4]
v_cmpx_ne_u64_e64 s[10:11], v[3:4]
s_cbranch_execz .LBB1_10
v_add_nc_u32_e32 v2, s8, v2
s_mov_b32 s21, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_mad_u64_u32 v[5:6], null, s9, v2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e64 s20, s[10:11], v[5:6]
v_cmpx_ne_u64_e64 s[10:11], v[5:6]
s_cbranch_execz .LBB1_9
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s23, -1
s_mov_b32 s22, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[1:2]
v_add_co_u32 v9, s0, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, s5, v8, s0
v_add_co_u32 v3, s0, v5, v3
v_add_co_ci_u32_e64 v4, s0, v6, v4, s0
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i64_e64 v[3:4], v[9:10]
s_cbranch_execz .LBB1_8
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v7, s0, s6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
v_mov_b32_e32 v2, s8
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_xor_b32 s23, exec_lo, -1
global_store_b64 v[7:8], v[3:4], off
global_store_b32 v[5:6], v2, off
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s20, exec_lo
s_and_b32 s20, s23, exec_lo
s_or_b32 s20, s0, s20
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_not1_b32 s0, vcc_lo, exec_lo
s_and_b32 s20, s20, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 vcc_lo, s0, s20
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s17, exec_lo
s_and_b32 s17, vcc_lo, exec_lo
s_or_b32 s17, s0, s17
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s0, s17
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[4:5], off
s_branch .LBB1_2
.LBB1_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12global_floydPlS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12global_floydPlS_Piii, .Lfunc_end1-_Z12global_floydPlS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11global_initPlS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11global_initPlS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12global_floydPlS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z12global_floydPlS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12global_floydPlS_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R0, c[0x0][0x17c] ; /* 0x00005f0000007a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R5, R5, R0, RZ ; /* 0x0000000005057224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fc800078e0002 */
/*0120*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fe20000000000 */
/*0130*/ HFMA2.MMA R15, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0f7435 */
/* 0x000fe200000001ff */
/*0140*/ IABS R8, c[0x0][0x17c] ; /* 0x00005f0000087a13 */
/* 0x000fe20000000000 */
/*0150*/ BSSY B0, 0x4b0 ; /* 0x0000035000007945 */
/* 0x000fe20003800000 */
/*0160*/ BSSY B1, 0x460 ; /* 0x000002f000017945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.HI.U32 R2, R5, R6, RZ ; /* 0x0000000605027227 */
/* 0x000fe200078e00ff */
/*0180*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fc60000011404 */
/*0190*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01a0*/ IMAD R3, R8, R3, R6 ; /* 0x0000000308037224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IADD3 R3, R3, -R8, RZ ; /* 0x800000080303a210 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe40003f06070 */
/*01f0*/ LOP3.LUT R3, R4, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0004037a12 */
/* 0x000fe400078e3cff */
/*0200*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*0210*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0220*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fca0007ffe0ff */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0002 */
/*0240*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*0250*/ @!P2 LOP3.LUT R8, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff08aa12 */
/* 0x000fca00078e33ff */
/*0260*/ IMAD.MOV R3, RZ, RZ, -R8 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a08 */
/*0270*/ IMAD R13, R3, c[0x0][0x17c], R4 ; /* 0x00005f00030d7a24 */
/* 0x000fe400078e0204 */
/*0280*/ IMAD.WIDE R2, R4, R15, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc600078e020f */
/*0290*/ ISETP.NE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fda0003f05270 */
/*02a0*/ @!P0 BRA 0x450 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD R8, R8, R6, c[0x0][0x178] ; /* 0x00005e0008087624 */
/* 0x000fc800078e0206 */
/*02d0*/ IMAD.WIDE R8, R8, R15, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020f */
/*02e0*/ LDG.E.64 R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea4000c1e1b00 */
/*02f0*/ ISETP.NE.U32.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fc80003f05070 */
/*0300*/ ISETP.NE.AND.EX P0, PT, R11, 0x7fffffff, PT, P0 ; /* 0x7fffffff0b00780c */
/* 0x000fda0003f05300 */
/*0310*/ @!P0 BRA 0x450 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD R8, R6, c[0x0][0x178], R13 ; /* 0x00005e0006087a24 */
/* 0x000fc800078e020d */
/*0330*/ IMAD.WIDE R8, R8, R15, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020f */
/*0340*/ LDG.E.64 R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000ea4000c1e1b00 */
/*0350*/ ISETP.NE.U32.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fc80003f05070 */
/*0360*/ ISETP.NE.AND.EX P0, PT, R13, 0x7fffffff, PT, P0 ; /* 0x7fffffff0d00780c */
/* 0x000fda0003f05300 */
/*0370*/ @!P0 BRA 0x450 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0380*/ IMAD.WIDE R8, R4, R15, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fcc00078e020f */
/*0390*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IADD3 R12, P0, R10, R12, RZ ; /* 0x0000000c0a0c7210 */
/* 0x000fca0007f1e0ff */
/*03b0*/ IMAD.X R13, R11, 0x1, R13, P0 ; /* 0x000000010b0d7824 */
/* 0x000fe200000e060d */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R12, R8, PT ; /* 0x000000080c00720c */
/* 0x004fc80003f06070 */
/*03d0*/ ISETP.GE.AND.EX P0, PT, R13, R9, PT, P0 ; /* 0x000000090d00720c */
/* 0x000fda0003f06300 */
/*03e0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b8424 */
/* 0x000fe200078e00ff */
/*03f0*/ @!P0 MOV R15, c[0x0][0x178] ; /* 0x00005e00000f8a02 */
/* 0x000fe20000000f00 */
/*0400*/ @!P0 STG.E.64 [R2.64], R12 ; /* 0x0000000c02008986 */
/* 0x0001e2000c101b06 */
/*0410*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*0420*/ @!P0 IMAD.WIDE R10, R4, R11, c[0x0][0x170] ; /* 0x00005c00040a8625 */
/* 0x000fca00078e020b */
/*0430*/ @!P0 STG.E [R10.64], R15 ; /* 0x0000000f0a008986 */
/* 0x0001e2000c101906 */
/*0440*/ @!P0 BRA 0x4a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0450*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0460*/ LEA R6, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004067a11 */
/* 0x000fc800078018ff */
/*0470*/ LEA.HI.X R7, R4, c[0x0][0x164], R7, 0x3, P0 ; /* 0x0000590004077a11 */
/* 0x000fcc00000f1c07 */
/*0480*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1b00 */
/*0490*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0043e4000c101b06 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x003fc800078e00ff */
/*04c0*/ IMAD R4, R3, c[0x0][0xc], R4 ; /* 0x0000030003047a24 */
/* 0x000fca00078e0204 */
/*04d0*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*04e0*/ @!P0 BRA 0x120 ; /* 0xfffffc3000008947 */
/* 0x000fea000383ffff */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11global_initPlS_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, 0xffffffff ; /* 0xffffffff00077802 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fce0000000f00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101906 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0100*/ @!P0 BRA 0xc0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11global_initPlS_Piii
.globl _Z11global_initPlS_Piii
.p2align 8
.type _Z11global_initPlS_Piii,@function
_Z11global_initPlS_Piii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x1c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mul_i32 s4, s6, s6
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11global_initPlS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11global_initPlS_Piii, .Lfunc_end0-_Z11global_initPlS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12global_floydPlS_Piii
.globl _Z12global_floydPlS_Piii
.p2align 8
.type _Z12global_floydPlS_Piii,@function
_Z12global_floydPlS_Piii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x1c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_mul_i32 s12, s9, s9
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_13
s_ashr_i32 s13, s9, 31
s_load_b32 s11, s[2:3], 0x0
s_add_i32 s4, s9, s13
s_mov_b32 s15, 0
s_xor_b32 s14, s4, s13
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_u32_e32 v0, s14
s_sub_i32 s8, 0, s14
s_sub_i32 s16, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, s8, v0
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s11, s10
s_brev_b32 s11, -2
s_mov_b32 s10, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s15, vcc_lo, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB1_13
.LBB1_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v2
v_xor_b32_e32 v3, v3, v2
v_xor_b32_e32 v2, s13, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v0
v_mul_lo_u32 v5, v4, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_subrev_nc_u32_e32 v6, s14, v3
v_cmp_le_u32_e32 vcc_lo, s14, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v6
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s14, v3
v_cndmask_b32_e32 v3, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v3, v2
v_sub_nc_u32_e32 v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, s16, v3, v[1:2]
v_cmp_eq_u32_e64 s17, v6, v3
v_cmpx_ne_u32_e64 v6, v3
s_cbranch_execz .LBB1_11
v_mad_u64_u32 v[6:7], null, v3, s9, s[8:9]
s_mov_b32 s19, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, s[10:11], v[3:4]
v_cmpx_ne_u64_e64 s[10:11], v[3:4]
s_cbranch_execz .LBB1_10
v_add_nc_u32_e32 v2, s8, v2
s_mov_b32 s21, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_mad_u64_u32 v[5:6], null, s9, v2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e64 s20, s[10:11], v[5:6]
v_cmpx_ne_u64_e64 s[10:11], v[5:6]
s_cbranch_execz .LBB1_9
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s23, -1
s_mov_b32 s22, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[1:2]
v_add_co_u32 v9, s0, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, s5, v8, s0
v_add_co_u32 v3, s0, v5, v3
v_add_co_ci_u32_e64 v4, s0, v6, v4, s0
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i64_e64 v[3:4], v[9:10]
s_cbranch_execz .LBB1_8
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v7, s0, s6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
v_mov_b32_e32 v2, s8
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_xor_b32 s23, exec_lo, -1
global_store_b64 v[7:8], v[3:4], off
global_store_b32 v[5:6], v2, off
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s20, exec_lo
s_and_b32 s20, s23, exec_lo
s_or_b32 s20, s0, s20
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_not1_b32 s0, vcc_lo, exec_lo
s_and_b32 s20, s20, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 vcc_lo, s0, s20
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s17, exec_lo
s_and_b32 s17, vcc_lo, exec_lo
s_or_b32 s17, s0, s17
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s0, s17
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[4:5], off
s_branch .LBB1_2
.LBB1_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12global_floydPlS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12global_floydPlS_Piii, .Lfunc_end1-_Z12global_floydPlS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11global_initPlS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11global_initPlS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12global_floydPlS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z12global_floydPlS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void cuda_dot(int N, double *a, double *b, double *c)
{
// __shared__ double localDot[threadsPerBlock]; /* Statically defined */
extern __shared__ double localDot[];
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int localIndex = threadIdx.x;
double localSum = 0;
while (ix < N)
{
localSum += a[ix] * b[ix]; /* Reduction is here */
ix += blockDim.x * gridDim.x;
}
/* Store sum computed by this thread */
localDot[localIndex] = localSum;
/* Wait for all threads to get to this point */
__syncthreads();
/* Every block should add up sum computed on
threads in the block */
int i = blockDim.x/2;
while (i != 0)
{
if (localIndex < i)
{
localDot[localIndex] += localDot[localIndex + i];
}
__syncthreads();
i /= 2;
}
/* Each block stores local dot product */
if (localIndex == 0)
c[blockIdx.x] = localDot[0];
}
|
code for sm_80
Function : _Z8cuda_dotiPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x160 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0040*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R0, c[0x0][0x0], R9 ; /* 0x0000000000047a24 */
/* 0x001fca00078e0209 */
/*0070*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x150 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*00a0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x001fd400000001ff */
/*00c0*/ IMAD.WIDE R4, R8, R7, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R6, R8, R7, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x000fe400078e0207 */
/*00e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD R8, R11, c[0x0][0xc], R8 ; /* 0x000003000b087a24 */
/* 0x000fca00078e0208 */
/*0120*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fe20003f06270 */
/*0130*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x0060580000000002 */
/*0140*/ @!P0 BRA 0xb0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0170*/ STS.64 [R9.X8], R2 ; /* 0x0000000209007388 */
/* 0x0023e20000008a00 */
/*0180*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*01b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01c0*/ @!P1 BRA 0x2b0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R6, R9, 0x8, RZ ; /* 0x0000000809067824 */
/* 0x003fe200078e00ff */
/*01e0*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x000fc80008000f00 */
/*01f0*/ ISETP.GE.AND P1, PT, R9, R7, PT ; /* 0x000000070900720c */
/* 0x000fda0003f26270 */
/*0200*/ @!P1 IMAD R4, R7.reuse, 0x8, R6 ; /* 0x0000000807049824 */
/* 0x040fe200078e0206 */
/*0210*/ @!P1 LDS.64 R2, [R9.X8] ; /* 0x0000000009029984 */
/* 0x000fea0000008a00 */
/*0220*/ @!P1 LDS.64 R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000a00 */
/*0230*/ @!P1 DADD R2, R2, R4 ; /* 0x0000000002029229 */
/* 0x0010640000000004 */
/*0240*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x001fc40007ffe0ff */
/*0250*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc600078f08ff */
/*0260*/ @!P1 STS.64 [R9.X8], R2 ; /* 0x0000000209009388 */
/* 0x0021e80000008a00 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0280*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0290*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fd60000011407 */
/*02a0*/ @P1 BRA 0x1f0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x002fea0003800000 */
/*02c0*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e620000000a00 */
/*02d0*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x001fca0000000f00 */
/*02e0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fca00078e0005 */
/*02f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b06 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void cuda_dot(int N, double *a, double *b, double *c)
{
// __shared__ double localDot[threadsPerBlock]; /* Statically defined */
extern __shared__ double localDot[];
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int localIndex = threadIdx.x;
double localSum = 0;
while (ix < N)
{
localSum += a[ix] * b[ix]; /* Reduction is here */
ix += blockDim.x * gridDim.x;
}
/* Store sum computed by this thread */
localDot[localIndex] = localSum;
/* Wait for all threads to get to this point */
__syncthreads();
/* Every block should add up sum computed on
threads in the block */
int i = blockDim.x/2;
while (i != 0)
{
if (localIndex < i)
{
localDot[localIndex] += localDot[localIndex + i];
}
__syncthreads();
i /= 2;
}
/* Each block stores local dot product */
if (localIndex == 0)
c[blockIdx.x] = localDot[0];
}
|
.file "tmpxft_000dd73b_00000000-6_cuda_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_
.type _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_, @function
_Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_dotiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_, .-_Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_
.globl _Z8cuda_dotiPdS_S_
.type _Z8cuda_dotiPdS_S_, @function
_Z8cuda_dotiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8cuda_dotiPdS_S_, .-_Z8cuda_dotiPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8cuda_dotiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_dotiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void cuda_dot(int N, double *a, double *b, double *c)
{
// __shared__ double localDot[threadsPerBlock]; /* Statically defined */
extern __shared__ double localDot[];
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int localIndex = threadIdx.x;
double localSum = 0;
while (ix < N)
{
localSum += a[ix] * b[ix]; /* Reduction is here */
ix += blockDim.x * gridDim.x;
}
/* Store sum computed by this thread */
localDot[localIndex] = localSum;
/* Wait for all threads to get to this point */
__syncthreads();
/* Every block should add up sum computed on
threads in the block */
int i = blockDim.x/2;
while (i != 0)
{
if (localIndex < i)
{
localDot[localIndex] += localDot[localIndex + i];
}
__syncthreads();
i /= 2;
}
/* Each block stores local dot product */
if (localIndex == 0)
c[blockIdx.x] = localDot[0];
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_dot(int N, double *a, double *b, double *c)
{
// __shared__ double localDot[threadsPerBlock]; /* Statically defined */
extern __shared__ double localDot[];
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int localIndex = threadIdx.x;
double localSum = 0;
while (ix < N)
{
localSum += a[ix] * b[ix]; /* Reduction is here */
ix += blockDim.x * gridDim.x;
}
/* Store sum computed by this thread */
localDot[localIndex] = localSum;
/* Wait for all threads to get to this point */
__syncthreads();
/* Every block should add up sum computed on
threads in the block */
int i = blockDim.x/2;
while (i != 0)
{
if (localIndex < i)
{
localDot[localIndex] += localDot[localIndex + i];
}
__syncthreads();
i /= 2;
}
/* Each block stores local dot product */
if (localIndex == 0)
c[blockIdx.x] = localDot[0];
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_dot(int N, double *a, double *b, double *c)
{
// __shared__ double localDot[threadsPerBlock]; /* Statically defined */
extern __shared__ double localDot[];
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int localIndex = threadIdx.x;
double localSum = 0;
while (ix < N)
{
localSum += a[ix] * b[ix]; /* Reduction is here */
ix += blockDim.x * gridDim.x;
}
/* Store sum computed by this thread */
localDot[localIndex] = localSum;
/* Wait for all threads to get to this point */
__syncthreads();
/* Every block should add up sum computed on
threads in the block */
int i = blockDim.x/2;
while (i != 0)
{
if (localIndex < i)
{
localDot[localIndex] += localDot[localIndex + i];
}
__syncthreads();
i /= 2;
}
/* Each block stores local dot product */
if (localIndex == 0)
c[blockIdx.x] = localDot[0];
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cuda_dotiPdS_S_
.globl _Z8cuda_dotiPdS_S_
.p2align 8
.type _Z8cuda_dotiPdS_S_,@function
_Z8cuda_dotiPdS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s4, s0, 32
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_4
s_load_b32 s11, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s11, v1
v_add_co_u32 v7, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[5:6], v[5:6], off
s_or_b32 s10, vcc_lo, s10
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[7:8], v[5:6], v[3:4]
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s10
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
v_lshl_add_u32 v1, v0, 3, 0
s_cmp_lt_u32 s3, 2
ds_store_b64 v1, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[2:3], 3
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 3, 0
ds_load_b64 v[2:3], v2
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cuda_dotiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cuda_dotiPdS_S_, .Lfunc_end0-_Z8cuda_dotiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cuda_dotiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cuda_dotiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_dot(int N, double *a, double *b, double *c)
{
// __shared__ double localDot[threadsPerBlock]; /* Statically defined */
extern __shared__ double localDot[];
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int localIndex = threadIdx.x;
double localSum = 0;
while (ix < N)
{
localSum += a[ix] * b[ix]; /* Reduction is here */
ix += blockDim.x * gridDim.x;
}
/* Store sum computed by this thread */
localDot[localIndex] = localSum;
/* Wait for all threads to get to this point */
__syncthreads();
/* Every block should add up sum computed on
threads in the block */
int i = blockDim.x/2;
while (i != 0)
{
if (localIndex < i)
{
localDot[localIndex] += localDot[localIndex + i];
}
__syncthreads();
i /= 2;
}
/* Each block stores local dot product */
if (localIndex == 0)
c[blockIdx.x] = localDot[0];
}
|
.text
.file "cuda_dot.hip"
.globl _Z23__device_stub__cuda_dotiPdS_S_ # -- Begin function _Z23__device_stub__cuda_dotiPdS_S_
.p2align 4, 0x90
.type _Z23__device_stub__cuda_dotiPdS_S_,@function
_Z23__device_stub__cuda_dotiPdS_S_: # @_Z23__device_stub__cuda_dotiPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_dotiPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cuda_dotiPdS_S_, .Lfunc_end0-_Z23__device_stub__cuda_dotiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_dotiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cuda_dotiPdS_S_,@object # @_Z8cuda_dotiPdS_S_
.section .rodata,"a",@progbits
.globl _Z8cuda_dotiPdS_S_
.p2align 3, 0x0
_Z8cuda_dotiPdS_S_:
.quad _Z23__device_stub__cuda_dotiPdS_S_
.size _Z8cuda_dotiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8cuda_dotiPdS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_dotiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_dotiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z8cuda_dotiPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x160 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0040*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R0, c[0x0][0x0], R9 ; /* 0x0000000000047a24 */
/* 0x001fca00078e0209 */
/*0070*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x150 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*00a0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x001fd400000001ff */
/*00c0*/ IMAD.WIDE R4, R8, R7, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R6, R8, R7, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x000fe400078e0207 */
/*00e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD R8, R11, c[0x0][0xc], R8 ; /* 0x000003000b087a24 */
/* 0x000fca00078e0208 */
/*0120*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fe20003f06270 */
/*0130*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x0060580000000002 */
/*0140*/ @!P0 BRA 0xb0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0170*/ STS.64 [R9.X8], R2 ; /* 0x0000000209007388 */
/* 0x0023e20000008a00 */
/*0180*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*01b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01c0*/ @!P1 BRA 0x2b0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R6, R9, 0x8, RZ ; /* 0x0000000809067824 */
/* 0x003fe200078e00ff */
/*01e0*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x000fc80008000f00 */
/*01f0*/ ISETP.GE.AND P1, PT, R9, R7, PT ; /* 0x000000070900720c */
/* 0x000fda0003f26270 */
/*0200*/ @!P1 IMAD R4, R7.reuse, 0x8, R6 ; /* 0x0000000807049824 */
/* 0x040fe200078e0206 */
/*0210*/ @!P1 LDS.64 R2, [R9.X8] ; /* 0x0000000009029984 */
/* 0x000fea0000008a00 */
/*0220*/ @!P1 LDS.64 R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000a00 */
/*0230*/ @!P1 DADD R2, R2, R4 ; /* 0x0000000002029229 */
/* 0x0010640000000004 */
/*0240*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x001fc40007ffe0ff */
/*0250*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc600078f08ff */
/*0260*/ @!P1 STS.64 [R9.X8], R2 ; /* 0x0000000209009388 */
/* 0x0021e80000008a00 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0280*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0290*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fd60000011407 */
/*02a0*/ @P1 BRA 0x1f0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x002fea0003800000 */
/*02c0*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e620000000a00 */
/*02d0*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x001fca0000000f00 */
/*02e0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fca00078e0005 */
/*02f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b06 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cuda_dotiPdS_S_
.globl _Z8cuda_dotiPdS_S_
.p2align 8
.type _Z8cuda_dotiPdS_S_,@function
_Z8cuda_dotiPdS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s4, s0, 32
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_4
s_load_b32 s11, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s11, v1
v_add_co_u32 v7, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[5:6], v[5:6], off
s_or_b32 s10, vcc_lo, s10
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[7:8], v[5:6], v[3:4]
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s10
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
v_lshl_add_u32 v1, v0, 3, 0
s_cmp_lt_u32 s3, 2
ds_store_b64 v1, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[2:3], 3
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 3, 0
ds_load_b64 v[2:3], v2
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cuda_dotiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cuda_dotiPdS_S_, .Lfunc_end0-_Z8cuda_dotiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cuda_dotiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cuda_dotiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000dd73b_00000000-6_cuda_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_
.type _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_, @function
_Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_dotiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_, .-_Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_
.globl _Z8cuda_dotiPdS_S_
.type _Z8cuda_dotiPdS_S_, @function
_Z8cuda_dotiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8cuda_dotiPdS_S_iPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8cuda_dotiPdS_S_, .-_Z8cuda_dotiPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8cuda_dotiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_dotiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "cuda_dot.hip"
.globl _Z23__device_stub__cuda_dotiPdS_S_ # -- Begin function _Z23__device_stub__cuda_dotiPdS_S_
.p2align 4, 0x90
.type _Z23__device_stub__cuda_dotiPdS_S_,@function
_Z23__device_stub__cuda_dotiPdS_S_: # @_Z23__device_stub__cuda_dotiPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_dotiPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cuda_dotiPdS_S_, .Lfunc_end0-_Z23__device_stub__cuda_dotiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_dotiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cuda_dotiPdS_S_,@object # @_Z8cuda_dotiPdS_S_
.section .rodata,"a",@progbits
.globl _Z8cuda_dotiPdS_S_
.p2align 3, 0x0
_Z8cuda_dotiPdS_S_:
.quad _Z23__device_stub__cuda_dotiPdS_S_
.size _Z8cuda_dotiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8cuda_dotiPdS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_dotiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_dotiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/***************************************************
* Module that negs all the elements on a matrix
* Author: Alonso Vidales <[email protected]>
*
* To be compiled with nvcc -ptx matrix_remove_bias_top.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_remove_bias_top.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixRemoveBiasTop(double* C, double* A, int width, int resW, int resH, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * width + x;
if (resultPos < resultSize && x < width) {
C[resultPos] = A[resultPos + width];
}
}
#ifdef __cplusplus
}
#endif
|
code for sm_80
Function : matrixRemoveBiasTop
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x001fc400078e0200 */
/*0060*/ IMAD R3, R2, c[0x0][0x178], R5 ; /* 0x00005e0002037a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R4, R3, c[0x0][0x170], R0 ; /* 0x00005c0003047a24 */
/* 0x000fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R2, R4, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/***************************************************
* Module that negs all the elements on a matrix
* Author: Alonso Vidales <[email protected]>
*
* To be compiled with nvcc -ptx matrix_remove_bias_top.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_remove_bias_top.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixRemoveBiasTop(double* C, double* A, int width, int resW, int resH, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * width + x;
if (resultPos < resultSize && x < width) {
C[resultPos] = A[resultPos + width];
}
}
#ifdef __cplusplus
}
#endif
|
.file "tmpxft_00111a0e_00000000-6_matrix_remove_bias_top.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii
.type _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii, @function
_Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrixRemoveBiasTop(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii, .-_Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii
.globl matrixRemoveBiasTop
.type matrixRemoveBiasTop, @function
matrixRemoveBiasTop:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixRemoveBiasTop, .-matrixRemoveBiasTop
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixRemoveBiasTop"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixRemoveBiasTop(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/***************************************************
* Module that negs all the elements on a matrix
* Author: Alonso Vidales <[email protected]>
*
* To be compiled with nvcc -ptx matrix_remove_bias_top.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_remove_bias_top.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixRemoveBiasTop(double* C, double* A, int width, int resW, int resH, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * width + x;
if (resultPos < resultSize && x < width) {
C[resultPos] = A[resultPos + width];
}
}
#ifdef __cplusplus
}
#endif
|
#include <hip/hip_runtime.h>
/***************************************************
* Module that negs all the elements on a matrix
* Author: Alonso Vidales <[email protected]>
*
* To be compiled with nvcc -ptx matrix_remove_bias_top.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_remove_bias_top.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixRemoveBiasTop(double* C, double* A, int width, int resW, int resH, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * width + x;
if (resultPos < resultSize && x < width) {
C[resultPos] = A[resultPos + width];
}
}
#ifdef __cplusplus
}
#endif
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
/***************************************************
* Module that negs all the elements on a matrix
* Author: Alonso Vidales <[email protected]>
*
* To be compiled with nvcc -ptx matrix_remove_bias_top.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_remove_bias_top.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixRemoveBiasTop(double* C, double* A, int width, int resW, int resH, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * width + x;
if (resultPos < resultSize && x < width) {
C[resultPos] = A[resultPos + width];
}
}
#ifdef __cplusplus
}
#endif
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrixRemoveBiasTop
.globl matrixRemoveBiasTop
.p2align 8
.type matrixRemoveBiasTop,@function
matrixRemoveBiasTop:
s_load_b128 s[4:7], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s4, v2
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s7, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b64 v[2:3], v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrixRemoveBiasTop
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrixRemoveBiasTop, .Lfunc_end0-matrixRemoveBiasTop
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrixRemoveBiasTop
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrixRemoveBiasTop.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
/***************************************************
* Module that negs all the elements on a matrix
* Author: Alonso Vidales <[email protected]>
*
* To be compiled with nvcc -ptx matrix_remove_bias_top.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_remove_bias_top.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixRemoveBiasTop(double* C, double* A, int width, int resW, int resH, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * width + x;
if (resultPos < resultSize && x < width) {
C[resultPos] = A[resultPos + width];
}
}
#ifdef __cplusplus
}
#endif
|
.text
.file "matrix_remove_bias_top.hip"
.globl __device_stub__matrixRemoveBiasTop # -- Begin function __device_stub__matrixRemoveBiasTop
.p2align 4, 0x90
.type __device_stub__matrixRemoveBiasTop,@function
__device_stub__matrixRemoveBiasTop: # @__device_stub__matrixRemoveBiasTop
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrixRemoveBiasTop, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__matrixRemoveBiasTop, .Lfunc_end0-__device_stub__matrixRemoveBiasTop
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixRemoveBiasTop, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixRemoveBiasTop,@object # @matrixRemoveBiasTop
.section .rodata,"a",@progbits
.globl matrixRemoveBiasTop
.p2align 3, 0x0
matrixRemoveBiasTop:
.quad __device_stub__matrixRemoveBiasTop
.size matrixRemoveBiasTop, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixRemoveBiasTop"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixRemoveBiasTop
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixRemoveBiasTop
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : matrixRemoveBiasTop
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x001fc400078e0200 */
/*0060*/ IMAD R3, R2, c[0x0][0x178], R5 ; /* 0x00005e0002037a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R4, R3, c[0x0][0x170], R0 ; /* 0x00005c0003047a24 */
/* 0x000fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R2, R4, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrixRemoveBiasTop
.globl matrixRemoveBiasTop
.p2align 8
.type matrixRemoveBiasTop,@function
matrixRemoveBiasTop:
s_load_b128 s[4:7], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s4, v2
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s7, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b64 v[2:3], v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrixRemoveBiasTop
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrixRemoveBiasTop, .Lfunc_end0-matrixRemoveBiasTop
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrixRemoveBiasTop
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrixRemoveBiasTop.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00111a0e_00000000-6_matrix_remove_bias_top.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii
.type _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii, @function
_Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrixRemoveBiasTop(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii, .-_Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii
.globl matrixRemoveBiasTop
.type matrixRemoveBiasTop, @function
matrixRemoveBiasTop:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19matrixRemoveBiasTopPdS_iiiiPdS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixRemoveBiasTop, .-matrixRemoveBiasTop
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixRemoveBiasTop"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixRemoveBiasTop(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrix_remove_bias_top.hip"
.globl __device_stub__matrixRemoveBiasTop # -- Begin function __device_stub__matrixRemoveBiasTop
.p2align 4, 0x90
.type __device_stub__matrixRemoveBiasTop,@function
__device_stub__matrixRemoveBiasTop: # @__device_stub__matrixRemoveBiasTop
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrixRemoveBiasTop, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__matrixRemoveBiasTop, .Lfunc_end0-__device_stub__matrixRemoveBiasTop
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixRemoveBiasTop, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixRemoveBiasTop,@object # @matrixRemoveBiasTop
.section .rodata,"a",@progbits
.globl matrixRemoveBiasTop
.p2align 3, 0x0
matrixRemoveBiasTop:
.quad __device_stub__matrixRemoveBiasTop
.size matrixRemoveBiasTop, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixRemoveBiasTop"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixRemoveBiasTop
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixRemoveBiasTop
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <vector>
#include <string>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
__device__ size_t compare(size_t a, size_t b, bool is_dilatation) {
if (is_dilatation)
return a > b ? a : b;
return a < b ? a : b;
}
__global__ void print_cuda(size_t* data, int height, int width) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
printf("%i, %i --> %lu\n", x, y, data[x+y*width]);
}
__global__ void compute_vHGW(size_t* data_read, size_t* data_write, int height, int width, size_t* g, size_t* h, size_t k, bool is_dilatation) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
auto m = width;
auto psa = (k - (m - 1) % k) - 1;
if (index >= width)
return;
size_t* curr_line = data_read+index*width;
size_t* g_line = g+index*width;
size_t* h_line = h+index*width;
size_t* v_line = data_write+index*width;
// Compute G
for (int x = 0; x < m; x++) {
g_line[x] = (x % k) == 0 ? curr_line[x] : compare(g_line[x - 1], curr_line[x], is_dilatation);
}
h_line[m - 1] = curr_line[m - 1];
for (size_t y = 1; y < m; y++)
{
size_t x = m - 1 - y;
h_line[x] = (x + 1) % k == 0 ? curr_line[x] : compare(h_line[x + 1], v_line[x], is_dilatation);
}
// Compute new line
for (size_t x = 0; x < m; x++)
{
auto div2 = k / 2;
if (x < div2)
v_line[x] = g_line[x + div2];
else if (x + div2 >= m)
v_line[x] = x + div2 < m + psa ? compare(g_line[m - 1], h_line[x - (div2)], is_dilatation) : h_line[x - (div2)];
else
v_line[x] = compare(g_line[x + div2], h_line[x - div2], is_dilatation);
}
}
void cuda_vHGW(size_t* data_host, int height, int width, size_t k, bool is_dilatation) {
size_t* data_read;
size_t* data_write;
size_t* h;
size_t* g;
// Allocate device memory
cudaMalloc(&data_read, sizeof(size_t) * height * width);
cudaMalloc(&data_write, sizeof(size_t) * height * width);
cudaMalloc(&g, sizeof(size_t) * height * width);
cudaMalloc(&h, sizeof(size_t) * height * width);
// Transfer data from host to device memory
cudaMemcpy(data_read, data_host, sizeof(size_t) * width * height, cudaMemcpyHostToDevice);
int bsize = 1;
// Executing kernel
compute_vHGW<<<height, bsize>>>(data_read, data_write, height, width, g, h, k, is_dilatation);
cudaDeviceSynchronize();
// Transfer data back to host memory
cudaMemcpy(data_host, data_write, sizeof(size_t) * width * height, cudaMemcpyDeviceToHost);
// Deallocate device memory
cudaFree(data_read);
cudaFree(data_write);
cudaFree(h);
cudaFree(g);
}
|
.file "tmpxft_00133e73_00000000-6_vhgw.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7comparemmb
.type _Z7comparemmb, @function
_Z7comparemmb:
.LFB4032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4032:
.size _Z7comparemmb, .-_Z7comparemmb
.globl _Z32__device_stub__Z10print_cudaPmiiPmii
.type _Z32__device_stub__Z10print_cudaPmiiPmii, @function
_Z32__device_stub__Z10print_cudaPmiiPmii:
.LFB4058:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10print_cudaPmii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z32__device_stub__Z10print_cudaPmiiPmii, .-_Z32__device_stub__Z10print_cudaPmiiPmii
.globl _Z10print_cudaPmii
.type _Z10print_cudaPmii, @function
_Z10print_cudaPmii:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10print_cudaPmiiPmii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z10print_cudaPmii, .-_Z10print_cudaPmii
.globl _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
.type _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb, @function
_Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb:
.LFB4060:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movl 216(%rsp), %eax
movb %al, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12compute_vHGWPmS_iiS_S_mb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb, .-_Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
.globl _Z12compute_vHGWPmS_iiS_S_mb
.type _Z12compute_vHGWPmS_iiS_S_mb, @function
_Z12compute_vHGWPmS_iiS_S_mb:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z12compute_vHGWPmS_iiS_S_mb, .-_Z12compute_vHGWPmS_iiS_S_mb
.globl _Z9cuda_vHGWPmiimb
.type _Z9cuda_vHGWPmiimb, @function
_Z9cuda_vHGWPmiimb:
.LFB4033:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movl %esi, %ebp
movl %edx, %r13d
movq %rcx, %r15
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %esi, %rbx
movslq %edx, %rax
imulq %rax, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movzbl %r14b, %r14d
pushq %r14
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
movq 32(%rsp), %r9
movq 40(%rsp), %r8
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4033:
.size _Z9cuda_vHGWPmiimb, .-_Z9cuda_vHGWPmiimb
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12compute_vHGWPmS_iiS_S_mb"
.LC1:
.string "_Z10print_cudaPmii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12compute_vHGWPmS_iiS_S_mb(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10print_cudaPmii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <vector>
#include <string>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
__device__ size_t compare(size_t a, size_t b, bool is_dilatation) {
if (is_dilatation)
return a > b ? a : b;
return a < b ? a : b;
}
__global__ void print_cuda(size_t* data, int height, int width) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
printf("%i, %i --> %lu\n", x, y, data[x+y*width]);
}
__global__ void compute_vHGW(size_t* data_read, size_t* data_write, int height, int width, size_t* g, size_t* h, size_t k, bool is_dilatation) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
auto m = width;
auto psa = (k - (m - 1) % k) - 1;
if (index >= width)
return;
size_t* curr_line = data_read+index*width;
size_t* g_line = g+index*width;
size_t* h_line = h+index*width;
size_t* v_line = data_write+index*width;
// Compute G
for (int x = 0; x < m; x++) {
g_line[x] = (x % k) == 0 ? curr_line[x] : compare(g_line[x - 1], curr_line[x], is_dilatation);
}
h_line[m - 1] = curr_line[m - 1];
for (size_t y = 1; y < m; y++)
{
size_t x = m - 1 - y;
h_line[x] = (x + 1) % k == 0 ? curr_line[x] : compare(h_line[x + 1], v_line[x], is_dilatation);
}
// Compute new line
for (size_t x = 0; x < m; x++)
{
auto div2 = k / 2;
if (x < div2)
v_line[x] = g_line[x + div2];
else if (x + div2 >= m)
v_line[x] = x + div2 < m + psa ? compare(g_line[m - 1], h_line[x - (div2)], is_dilatation) : h_line[x - (div2)];
else
v_line[x] = compare(g_line[x + div2], h_line[x - div2], is_dilatation);
}
}
void cuda_vHGW(size_t* data_host, int height, int width, size_t k, bool is_dilatation) {
size_t* data_read;
size_t* data_write;
size_t* h;
size_t* g;
// Allocate device memory
cudaMalloc(&data_read, sizeof(size_t) * height * width);
cudaMalloc(&data_write, sizeof(size_t) * height * width);
cudaMalloc(&g, sizeof(size_t) * height * width);
cudaMalloc(&h, sizeof(size_t) * height * width);
// Transfer data from host to device memory
cudaMemcpy(data_read, data_host, sizeof(size_t) * width * height, cudaMemcpyHostToDevice);
int bsize = 1;
// Executing kernel
compute_vHGW<<<height, bsize>>>(data_read, data_write, height, width, g, h, k, is_dilatation);
cudaDeviceSynchronize();
// Transfer data back to host memory
cudaMemcpy(data_host, data_write, sizeof(size_t) * width * height, cudaMemcpyDeviceToHost);
// Deallocate device memory
cudaFree(data_read);
cudaFree(data_write);
cudaFree(h);
cudaFree(g);
}
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <vector>
#include <string>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
__device__ size_t compare(size_t a, size_t b, bool is_dilatation) {
if (is_dilatation)
return a > b ? a : b;
return a < b ? a : b;
}
__global__ void print_cuda(size_t* data, int height, int width) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
printf("%i, %i --> %lu\n", x, y, data[x+y*width]);
}
__global__ void compute_vHGW(size_t* data_read, size_t* data_write, int height, int width, size_t* g, size_t* h, size_t k, bool is_dilatation) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
auto m = width;
auto psa = (k - (m - 1) % k) - 1;
if (index >= width)
return;
size_t* curr_line = data_read+index*width;
size_t* g_line = g+index*width;
size_t* h_line = h+index*width;
size_t* v_line = data_write+index*width;
// Compute G
for (int x = 0; x < m; x++) {
g_line[x] = (x % k) == 0 ? curr_line[x] : compare(g_line[x - 1], curr_line[x], is_dilatation);
}
h_line[m - 1] = curr_line[m - 1];
for (size_t y = 1; y < m; y++)
{
size_t x = m - 1 - y;
h_line[x] = (x + 1) % k == 0 ? curr_line[x] : compare(h_line[x + 1], v_line[x], is_dilatation);
}
// Compute new line
for (size_t x = 0; x < m; x++)
{
auto div2 = k / 2;
if (x < div2)
v_line[x] = g_line[x + div2];
else if (x + div2 >= m)
v_line[x] = x + div2 < m + psa ? compare(g_line[m - 1], h_line[x - (div2)], is_dilatation) : h_line[x - (div2)];
else
v_line[x] = compare(g_line[x + div2], h_line[x - div2], is_dilatation);
}
}
void cuda_vHGW(size_t* data_host, int height, int width, size_t k, bool is_dilatation) {
size_t* data_read;
size_t* data_write;
size_t* h;
size_t* g;
// Allocate device memory
hipMalloc(&data_read, sizeof(size_t) * height * width);
hipMalloc(&data_write, sizeof(size_t) * height * width);
hipMalloc(&g, sizeof(size_t) * height * width);
hipMalloc(&h, sizeof(size_t) * height * width);
// Transfer data from host to device memory
hipMemcpy(data_read, data_host, sizeof(size_t) * width * height, hipMemcpyHostToDevice);
int bsize = 1;
// Executing kernel
compute_vHGW<<<height, bsize>>>(data_read, data_write, height, width, g, h, k, is_dilatation);
hipDeviceSynchronize();
// Transfer data back to host memory
hipMemcpy(data_host, data_write, sizeof(size_t) * width * height, hipMemcpyDeviceToHost);
// Deallocate device memory
hipFree(data_read);
hipFree(data_write);
hipFree(h);
hipFree(g);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <vector>
#include <string>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
__device__ size_t compare(size_t a, size_t b, bool is_dilatation) {
if (is_dilatation)
return a > b ? a : b;
return a < b ? a : b;
}
__global__ void print_cuda(size_t* data, int height, int width) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height) {
return;
}
printf("%i, %i --> %lu\n", x, y, data[x+y*width]);
}
__global__ void compute_vHGW(size_t* data_read, size_t* data_write, int height, int width, size_t* g, size_t* h, size_t k, bool is_dilatation) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
auto m = width;
auto psa = (k - (m - 1) % k) - 1;
if (index >= width)
return;
size_t* curr_line = data_read+index*width;
size_t* g_line = g+index*width;
size_t* h_line = h+index*width;
size_t* v_line = data_write+index*width;
// Compute G
for (int x = 0; x < m; x++) {
g_line[x] = (x % k) == 0 ? curr_line[x] : compare(g_line[x - 1], curr_line[x], is_dilatation);
}
h_line[m - 1] = curr_line[m - 1];
for (size_t y = 1; y < m; y++)
{
size_t x = m - 1 - y;
h_line[x] = (x + 1) % k == 0 ? curr_line[x] : compare(h_line[x + 1], v_line[x], is_dilatation);
}
// Compute new line
for (size_t x = 0; x < m; x++)
{
auto div2 = k / 2;
if (x < div2)
v_line[x] = g_line[x + div2];
else if (x + div2 >= m)
v_line[x] = x + div2 < m + psa ? compare(g_line[m - 1], h_line[x - (div2)], is_dilatation) : h_line[x - (div2)];
else
v_line[x] = compare(g_line[x + div2], h_line[x - div2], is_dilatation);
}
}
void cuda_vHGW(size_t* data_host, int height, int width, size_t k, bool is_dilatation) {
size_t* data_read;
size_t* data_write;
size_t* h;
size_t* g;
// Allocate device memory
hipMalloc(&data_read, sizeof(size_t) * height * width);
hipMalloc(&data_write, sizeof(size_t) * height * width);
hipMalloc(&g, sizeof(size_t) * height * width);
hipMalloc(&h, sizeof(size_t) * height * width);
// Transfer data from host to device memory
hipMemcpy(data_read, data_host, sizeof(size_t) * width * height, hipMemcpyHostToDevice);
int bsize = 1;
// Executing kernel
compute_vHGW<<<height, bsize>>>(data_read, data_write, height, width, g, h, k, is_dilatation);
hipDeviceSynchronize();
// Transfer data back to host memory
hipMemcpy(data_host, data_write, sizeof(size_t) * width * height, hipMemcpyDeviceToHost);
// Deallocate device memory
hipFree(data_read);
hipFree(data_write);
hipFree(h);
hipFree(g);
}
|
.text
.file "vhgw.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__print_cudaPmii # -- Begin function _Z25__device_stub__print_cudaPmii
.p2align 4, 0x90
.type _Z25__device_stub__print_cudaPmii,@function
_Z25__device_stub__print_cudaPmii: # @_Z25__device_stub__print_cudaPmii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10print_cudaPmii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__print_cudaPmii, .Lfunc_end0-_Z25__device_stub__print_cudaPmii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__compute_vHGWPmS_iiS_S_mb # -- Begin function _Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.p2align 4, 0x90
.type _Z27__device_stub__compute_vHGWPmS_iiS_S_mb,@function
_Z27__device_stub__compute_vHGWPmS_iiS_S_mb: # @_Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movzbl 184(%rsp), %eax
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movb %al, 7(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 7(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12compute_vHGWPmS_iiS_S_mb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z27__device_stub__compute_vHGWPmS_iiS_S_mb, .Lfunc_end1-_Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.cfi_endproc
# -- End function
.globl _Z9cuda_vHGWPmiimb # -- Begin function _Z9cuda_vHGWPmiimb
.p2align 4, 0x90
.type _Z9cuda_vHGWPmiimb,@function
_Z9cuda_vHGWPmiimb: # @_Z9cuda_vHGWPmiimb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 28(%rsp) # 4-byte Spill
movq %rcx, %r15
movl %edx, %r12d
movl %esi, %r13d
movq %rdi, %r14
movslq %esi, %rbp
movslq %edx, %rbx
imulq %rbp, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq 48(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r13d, 36(%rsp)
movl %r12d, 32(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %r15, 104(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movb %al, 7(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 7(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12compute_vHGWPmS_iiS_S_mb, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9cuda_vHGWPmiimb, .Lfunc_end2-_Z9cuda_vHGWPmiimb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10print_cudaPmii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12compute_vHGWPmS_iiS_S_mb, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10print_cudaPmii,@object # @_Z10print_cudaPmii
.section .rodata,"a",@progbits
.globl _Z10print_cudaPmii
.p2align 3, 0x0
_Z10print_cudaPmii:
.quad _Z25__device_stub__print_cudaPmii
.size _Z10print_cudaPmii, 8
.type _Z12compute_vHGWPmS_iiS_S_mb,@object # @_Z12compute_vHGWPmS_iiS_S_mb
.globl _Z12compute_vHGWPmS_iiS_S_mb
.p2align 3, 0x0
_Z12compute_vHGWPmS_iiS_S_mb:
.quad _Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.size _Z12compute_vHGWPmS_iiS_S_mb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10print_cudaPmii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12compute_vHGWPmS_iiS_S_mb"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__print_cudaPmii
.addrsig_sym _Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10print_cudaPmii
.addrsig_sym _Z12compute_vHGWPmS_iiS_S_mb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00133e73_00000000-6_vhgw.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7comparemmb
.type _Z7comparemmb, @function
_Z7comparemmb:
.LFB4032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4032:
.size _Z7comparemmb, .-_Z7comparemmb
.globl _Z32__device_stub__Z10print_cudaPmiiPmii
.type _Z32__device_stub__Z10print_cudaPmiiPmii, @function
_Z32__device_stub__Z10print_cudaPmiiPmii:
.LFB4058:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10print_cudaPmii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z32__device_stub__Z10print_cudaPmiiPmii, .-_Z32__device_stub__Z10print_cudaPmiiPmii
.globl _Z10print_cudaPmii
.type _Z10print_cudaPmii, @function
_Z10print_cudaPmii:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10print_cudaPmiiPmii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z10print_cudaPmii, .-_Z10print_cudaPmii
.globl _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
.type _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb, @function
_Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb:
.LFB4060:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movl 216(%rsp), %eax
movb %al, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12compute_vHGWPmS_iiS_S_mb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb, .-_Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
.globl _Z12compute_vHGWPmS_iiS_S_mb
.type _Z12compute_vHGWPmS_iiS_S_mb, @function
_Z12compute_vHGWPmS_iiS_S_mb:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z12compute_vHGWPmS_iiS_S_mb, .-_Z12compute_vHGWPmS_iiS_S_mb
.globl _Z9cuda_vHGWPmiimb
.type _Z9cuda_vHGWPmiimb, @function
_Z9cuda_vHGWPmiimb:
.LFB4033:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movl %esi, %ebp
movl %edx, %r13d
movq %rcx, %r15
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %esi, %rbx
movslq %edx, %rax
imulq %rax, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movzbl %r14b, %r14d
pushq %r14
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
movq 32(%rsp), %r9
movq 40(%rsp), %r8
movl %r13d, %ecx
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z42__device_stub__Z12compute_vHGWPmS_iiS_S_mbPmS_iiS_S_mb
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4033:
.size _Z9cuda_vHGWPmiimb, .-_Z9cuda_vHGWPmiimb
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12compute_vHGWPmS_iiS_S_mb"
.LC1:
.string "_Z10print_cudaPmii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12compute_vHGWPmS_iiS_S_mb(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10print_cudaPmii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "vhgw.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__print_cudaPmii # -- Begin function _Z25__device_stub__print_cudaPmii
.p2align 4, 0x90
.type _Z25__device_stub__print_cudaPmii,@function
_Z25__device_stub__print_cudaPmii: # @_Z25__device_stub__print_cudaPmii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10print_cudaPmii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__print_cudaPmii, .Lfunc_end0-_Z25__device_stub__print_cudaPmii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__compute_vHGWPmS_iiS_S_mb # -- Begin function _Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.p2align 4, 0x90
.type _Z27__device_stub__compute_vHGWPmS_iiS_S_mb,@function
_Z27__device_stub__compute_vHGWPmS_iiS_S_mb: # @_Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movzbl 184(%rsp), %eax
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movb %al, 7(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 7(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12compute_vHGWPmS_iiS_S_mb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z27__device_stub__compute_vHGWPmS_iiS_S_mb, .Lfunc_end1-_Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.cfi_endproc
# -- End function
.globl _Z9cuda_vHGWPmiimb # -- Begin function _Z9cuda_vHGWPmiimb
.p2align 4, 0x90
.type _Z9cuda_vHGWPmiimb,@function
_Z9cuda_vHGWPmiimb: # @_Z9cuda_vHGWPmiimb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 28(%rsp) # 4-byte Spill
movq %rcx, %r15
movl %edx, %r12d
movl %esi, %r13d
movq %rdi, %r14
movslq %esi, %rbp
movslq %edx, %rbx
imulq %rbp, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq 48(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r13d, 36(%rsp)
movl %r12d, 32(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %r15, 104(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movb %al, 7(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 7(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12compute_vHGWPmS_iiS_S_mb, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9cuda_vHGWPmiimb, .Lfunc_end2-_Z9cuda_vHGWPmiimb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10print_cudaPmii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12compute_vHGWPmS_iiS_S_mb, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10print_cudaPmii,@object # @_Z10print_cudaPmii
.section .rodata,"a",@progbits
.globl _Z10print_cudaPmii
.p2align 3, 0x0
_Z10print_cudaPmii:
.quad _Z25__device_stub__print_cudaPmii
.size _Z10print_cudaPmii, 8
.type _Z12compute_vHGWPmS_iiS_S_mb,@object # @_Z12compute_vHGWPmS_iiS_S_mb
.globl _Z12compute_vHGWPmS_iiS_S_mb
.p2align 3, 0x0
_Z12compute_vHGWPmS_iiS_S_mb:
.quad _Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.size _Z12compute_vHGWPmS_iiS_S_mb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10print_cudaPmii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12compute_vHGWPmS_iiS_S_mb"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__print_cudaPmii
.addrsig_sym _Z27__device_stub__compute_vHGWPmS_iiS_S_mb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10print_cudaPmii
.addrsig_sym _Z12compute_vHGWPmS_iiS_S_mb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <vector>
#include <cmath>
using namespace std;
// void AssembleProlMatrix(vector<vector<vector<double>>> &P, vector<vector<size_t>> N, vector<size_t> numNodes, vector<size_t> num_rows, )
int main()
{
vector<vector<size_t>> N;
N.resize(2, vector<size_t>(2));
N[0] = {3, 1};
N[1] = {6, 2};
size_t lev = 0;
size_t dim = 2;
vector<size_t> numNodes(2);
numNodes[0] = 8;
numNodes[1] = 21;
vector<size_t> num_rows = { 16, 42 };
// vector<size_t> num_rows = { numNodes[0]*2, numNodes[1]*2 };
vector<vector<vector<double>>> A;
A.resize(2);
A[0].resize(num_rows[0], vector<double>(num_rows[0]));
A[1].resize(num_rows[1], vector<double>(num_rows[1]));
size_t numLevels = 2;
vector<vector<vector<double>>> P;
P.resize(numLevels - 1);
P[0].resize(num_rows[1], vector<double>(num_rows[0]));
// assembleProlMatrix()
for ( int i = 0 ; i < numNodes[0]*2 ; i += 2)
{
for ( int j = 0 ; j < dim ; j++ )
{
// same node
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j][i+j] = 1;
// east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2][i+j] += 0.5;
// north node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) ][i+j] += 0.5;
// west node
if ( (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2][i+j] += 0.5;
// south node
if ( i / 2 >= N[lev][0] + 1)
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1)][i+j] += 0.5;
// north-east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 && i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// north-west node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1) && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
// south-east node
if ( i / 2 >= N[lev][0] + 1 && (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// south-west node
if ( i / 2 >= N[lev][0] + 1 && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
}
}
for ( int i = 0 ; i < num_rows[1] ; i++ )
{
for ( int j = 0 ; j < num_rows[0] ; j++ )
cout << P[0][i][j] << " ";
cout << "\n";
}
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <vector>
#include <cmath>
using namespace std;
// void AssembleProlMatrix(vector<vector<vector<double>>> &P, vector<vector<size_t>> N, vector<size_t> numNodes, vector<size_t> num_rows, )
int main()
{
vector<vector<size_t>> N;
N.resize(2, vector<size_t>(2));
N[0] = {3, 1};
N[1] = {6, 2};
size_t lev = 0;
size_t dim = 2;
vector<size_t> numNodes(2);
numNodes[0] = 8;
numNodes[1] = 21;
vector<size_t> num_rows = { 16, 42 };
// vector<size_t> num_rows = { numNodes[0]*2, numNodes[1]*2 };
vector<vector<vector<double>>> A;
A.resize(2);
A[0].resize(num_rows[0], vector<double>(num_rows[0]));
A[1].resize(num_rows[1], vector<double>(num_rows[1]));
size_t numLevels = 2;
vector<vector<vector<double>>> P;
P.resize(numLevels - 1);
P[0].resize(num_rows[1], vector<double>(num_rows[0]));
// assembleProlMatrix()
for ( int i = 0 ; i < numNodes[0]*2 ; i += 2)
{
for ( int j = 0 ; j < dim ; j++ )
{
// same node
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j][i+j] = 1;
// east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2][i+j] += 0.5;
// north node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) ][i+j] += 0.5;
// west node
if ( (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2][i+j] += 0.5;
// south node
if ( i / 2 >= N[lev][0] + 1)
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1)][i+j] += 0.5;
// north-east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 && i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// north-west node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1) && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
// south-east node
if ( i / 2 >= N[lev][0] + 1 && (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// south-west node
if ( i / 2 >= N[lev][0] + 1 && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
}
}
for ( int i = 0 ; i < num_rows[1] ; i++ )
{
for ( int j = 0 ; j < num_rows[0] ; j++ )
cout << P[0][i][j] << " ";
cout << "\n";
}
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <cmath>
using namespace std;
// void AssembleProlMatrix(vector<vector<vector<double>>> &P, vector<vector<size_t>> N, vector<size_t> numNodes, vector<size_t> num_rows, )
int main()
{
vector<vector<size_t>> N;
N.resize(2, vector<size_t>(2));
N[0] = {3, 1};
N[1] = {6, 2};
size_t lev = 0;
size_t dim = 2;
vector<size_t> numNodes(2);
numNodes[0] = 8;
numNodes[1] = 21;
vector<size_t> num_rows = { 16, 42 };
// vector<size_t> num_rows = { numNodes[0]*2, numNodes[1]*2 };
vector<vector<vector<double>>> A;
A.resize(2);
A[0].resize(num_rows[0], vector<double>(num_rows[0]));
A[1].resize(num_rows[1], vector<double>(num_rows[1]));
size_t numLevels = 2;
vector<vector<vector<double>>> P;
P.resize(numLevels - 1);
P[0].resize(num_rows[1], vector<double>(num_rows[0]));
// assembleProlMatrix()
for ( int i = 0 ; i < numNodes[0]*2 ; i += 2)
{
for ( int j = 0 ; j < dim ; j++ )
{
// same node
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j][i+j] = 1;
// east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2][i+j] += 0.5;
// north node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) ][i+j] += 0.5;
// west node
if ( (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2][i+j] += 0.5;
// south node
if ( i / 2 >= N[lev][0] + 1)
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1)][i+j] += 0.5;
// north-east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 && i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// north-west node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1) && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
// south-east node
if ( i / 2 >= N[lev][0] + 1 && (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// south-west node
if ( i / 2 >= N[lev][0] + 1 && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
}
}
for ( int i = 0 ; i < num_rows[1] ; i++ )
{
for ( int j = 0 ; j < num_rows[0] ; j++ )
cout << P[0][i][j] << " ";
cout << "\n";
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <cmath>
using namespace std;
// void AssembleProlMatrix(vector<vector<vector<double>>> &P, vector<vector<size_t>> N, vector<size_t> numNodes, vector<size_t> num_rows, )
int main()
{
vector<vector<size_t>> N;
N.resize(2, vector<size_t>(2));
N[0] = {3, 1};
N[1] = {6, 2};
size_t lev = 0;
size_t dim = 2;
vector<size_t> numNodes(2);
numNodes[0] = 8;
numNodes[1] = 21;
vector<size_t> num_rows = { 16, 42 };
// vector<size_t> num_rows = { numNodes[0]*2, numNodes[1]*2 };
vector<vector<vector<double>>> A;
A.resize(2);
A[0].resize(num_rows[0], vector<double>(num_rows[0]));
A[1].resize(num_rows[1], vector<double>(num_rows[1]));
size_t numLevels = 2;
vector<vector<vector<double>>> P;
P.resize(numLevels - 1);
P[0].resize(num_rows[1], vector<double>(num_rows[0]));
// assembleProlMatrix()
for ( int i = 0 ; i < numNodes[0]*2 ; i += 2)
{
for ( int j = 0 ; j < dim ; j++ )
{
// same node
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j][i+j] = 1;
// east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2][i+j] += 0.5;
// north node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) ][i+j] += 0.5;
// west node
if ( (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2][i+j] += 0.5;
// south node
if ( i / 2 >= N[lev][0] + 1)
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1)][i+j] += 0.5;
// north-east node
if ( (i / 2 + 1) % (N[lev][0]+1) != 0 && i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1))
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// north-west node
if ( i / 2 + (N[lev][0] + 1) < (N[lev][0] + 1)*(N[lev][1] + 1) && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j + 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
// south-east node
if ( i / 2 >= N[lev][0] + 1 && (i / 2 + 1) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) + 2 ][i+j] = 0.25;
// south-west node
if ( i / 2 >= N[lev][0] + 1 && (i / 2) % (N[lev][0]+1) != 0 )
P[lev][( 2*(i % ( (N[lev][0] + 1)*dim) )) + ( (ceil)( i / ( 2*(N[lev][0] + 1 ) ) ) )*2*dim*(N[lev+1][0] + 1) + j - 2*(N[lev+1][0] + 1) - 2 ][i+j] = 0.25;
}
}
for ( int i = 0 ; i < num_rows[1] ; i++ )
{
for ( int j = 0 ; j < num_rows[0] ; j++ )
cout << P[0][i][j] << " ";
cout << "\n";
}
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void Add(float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("Adding %f and %f\n",x[(idx-1)*N + i], x[(idx-2)*N + i]);
//printf("idx = %d, N = %d, i = %d\n", idx, N, i);
//printf("%f %f %f %f %f %f\n", x[0], x[1], x[2], x[3], x[4], x[5]);
x[(idx-2)*N + i] = x[(idx-1)*N + i]*W0 + x[(idx-2)*N + i]*W1;
//printf("on stack %f\n",x[(idx-2)*N + i]);
//printf("%f %f %f %f\n", x[0], x[1], x[2], x[3]);//, x[4], x[5]);
}
return;
}
|
code for sm_80
Function : _Z3AddPfmmff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x170], RZ ; /* 0x80005c00ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe40007f1e1ff */
/*00e0*/ IADD3.X R3, RZ, ~c[0x0][0x174], RZ, P1, !PT ; /* 0x80005d00ff037a10 */
/* 0x000fe40000ffe4ff */
/*00f0*/ IADD3.X R6, R6, -0x1, RZ, P0, !PT ; /* 0xffffffff06067810 */
/* 0x000fc600007fe4ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x170], R2 ; /* 0x00005c0000027a25 */
/* 0x000fc800078e0002 */
/*0110*/ IMAD R7, R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a24 */
/* 0x000fe200078e02ff */
/*0120*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fc60000000f00 */
/*0130*/ IMAD R13, R0, c[0x0][0x174], R7 ; /* 0x00005d00000d7a24 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0150*/ IMAD.IADD R11, R3, 0x1, R13 ; /* 0x00000001030b7824 */
/* 0x000fe400078e020d */
/*0160*/ IADD3 R5, P0, R6, R2, RZ ; /* 0x0000000206057210 */
/* 0x000fca0007f1e0ff */
/*0170*/ IMAD.X R8, R7, 0x1, R11, P0 ; /* 0x0000000107087824 */
/* 0x000fe200000e060b */
/*0180*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fe200078010ff */
/*0190*/ IMAD.WIDE.U32 R6, R0, c[0x0][0x170], R6 ; /* 0x00005c0000067a25 */
/* 0x000fc600078e0006 */
/*01a0*/ LEA.HI.X R5, R5, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f1408 */
/*01b0*/ IADD3 R7, R13, R7, RZ ; /* 0x000000070d077210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LEA R8, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006087a11 */
/* 0x000fc800078010ff */
/*01d0*/ LEA.HI.X R9, R6, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590006097a11 */
/* 0x000fe400000f1407 */
/*01e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*0210*/ FMUL R7, R6, c[0x0][0x17c] ; /* 0x00005f0006077a20 */
/* 0x004fe40000400000 */
/*0220*/ IMAD R6, R15, c[0x0][0xc], R10 ; /* 0x000003000f067a24 */
/* 0x000fc400078e020a */
/*0230*/ FFMA R7, R8, c[0x0][0x178], R7 ; /* 0x00005e0008077a23 */
/* 0x008fc60000000007 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f06070 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0260*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe40000000f00 */
/*0270*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x001fc80000011406 */
/*0280*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*0290*/ @!P0 BRA 0x160 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void Add(float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("Adding %f and %f\n",x[(idx-1)*N + i], x[(idx-2)*N + i]);
//printf("idx = %d, N = %d, i = %d\n", idx, N, i);
//printf("%f %f %f %f %f %f\n", x[0], x[1], x[2], x[3], x[4], x[5]);
x[(idx-2)*N + i] = x[(idx-1)*N + i]*W0 + x[(idx-2)*N + i]*W1;
//printf("on stack %f\n",x[(idx-2)*N + i]);
//printf("%f %f %f %f\n", x[0], x[1], x[2], x[3]);//, x[4], x[5]);
}
return;
}
|
.file "tmpxft_00011269_00000000-6_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3AddPfmmffPfmmff
.type _Z26__device_stub__Z3AddPfmmffPfmmff, @function
_Z26__device_stub__Z3AddPfmmffPfmmff:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3AddPfmmff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3AddPfmmffPfmmff, .-_Z26__device_stub__Z3AddPfmmffPfmmff
.globl _Z3AddPfmmff
.type _Z3AddPfmmff, @function
_Z3AddPfmmff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3AddPfmmffPfmmff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3AddPfmmff, .-_Z3AddPfmmff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3AddPfmmff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3AddPfmmff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void Add(float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("Adding %f and %f\n",x[(idx-1)*N + i], x[(idx-2)*N + i]);
//printf("idx = %d, N = %d, i = %d\n", idx, N, i);
//printf("%f %f %f %f %f %f\n", x[0], x[1], x[2], x[3], x[4], x[5]);
x[(idx-2)*N + i] = x[(idx-1)*N + i]*W0 + x[(idx-2)*N + i]*W1;
//printf("on stack %f\n",x[(idx-2)*N + i]);
//printf("%f %f %f %f\n", x[0], x[1], x[2], x[3]);//, x[4], x[5]);
}
return;
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Add(float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("Adding %f and %f\n",x[(idx-1)*N + i], x[(idx-2)*N + i]);
//printf("idx = %d, N = %d, i = %d\n", idx, N, i);
//printf("%f %f %f %f %f %f\n", x[0], x[1], x[2], x[3], x[4], x[5]);
x[(idx-2)*N + i] = x[(idx-1)*N + i]*W0 + x[(idx-2)*N + i]*W1;
//printf("on stack %f\n",x[(idx-2)*N + i]);
//printf("%f %f %f %f\n", x[0], x[1], x[2], x[3]);//, x[4], x[5]);
}
return;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Add(float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("Adding %f and %f\n",x[(idx-1)*N + i], x[(idx-2)*N + i]);
//printf("idx = %d, N = %d, i = %d\n", idx, N, i);
//printf("%f %f %f %f %f %f\n", x[0], x[1], x[2], x[3], x[4], x[5]);
x[(idx-2)*N + i] = x[(idx-1)*N + i]*W0 + x[(idx-2)*N + i]*W1;
//printf("on stack %f\n",x[(idx-2)*N + i]);
//printf("%f %f %f %f\n", x[0], x[1], x[2], x[3]);//, x[4], x[5]);
}
return;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3AddPfmmff
.globl _Z3AddPfmmff
.p2align 8
.type _Z3AddPfmmff,@function
_Z3AddPfmmff:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_load_b32 s12, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s10, -1
s_addc_u32 s5, s11, -1
s_mul_i32 s7, s4, s3
s_mul_hi_u32 s13, s4, s2
s_mul_i32 s5, s5, s2
s_add_i32 s7, s13, s7
s_mul_i32 s4, s4, s2
s_add_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_add_u32 s7, s10, -2
s_addc_u32 s10, s11, -1
s_mul_i32 s11, s7, s3
s_mul_hi_u32 s13, s7, s2
s_mul_i32 s14, s10, s2
s_add_i32 s11, s13, s11
s_mul_i32 s10, s7, s2
s_add_i32 s11, s11, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 2
s_add_u32 s7, s8, s10
s_addc_u32 s8, s9, s11
s_add_i32 s15, s15, s12
s_mov_b32 s9, 0
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s12, s6
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s7, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s8, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v0, v[0:1], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, s1, v2
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s6, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v7, s0, v0
global_store_b32 v[5:6], v7, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3AddPfmmff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3AddPfmmff, .Lfunc_end0-_Z3AddPfmmff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3AddPfmmff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3AddPfmmff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Add(float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
//printf("Adding %f and %f\n",x[(idx-1)*N + i], x[(idx-2)*N + i]);
//printf("idx = %d, N = %d, i = %d\n", idx, N, i);
//printf("%f %f %f %f %f %f\n", x[0], x[1], x[2], x[3], x[4], x[5]);
x[(idx-2)*N + i] = x[(idx-1)*N + i]*W0 + x[(idx-2)*N + i]*W1;
//printf("on stack %f\n",x[(idx-2)*N + i]);
//printf("%f %f %f %f\n", x[0], x[1], x[2], x[3]);//, x[4], x[5]);
}
return;
}
|
.text
.file "Add.hip"
.globl _Z18__device_stub__AddPfmmff # -- Begin function _Z18__device_stub__AddPfmmff
.p2align 4, 0x90
.type _Z18__device_stub__AddPfmmff,@function
_Z18__device_stub__AddPfmmff: # @_Z18__device_stub__AddPfmmff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3AddPfmmff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__AddPfmmff, .Lfunc_end0-_Z18__device_stub__AddPfmmff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3AddPfmmff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3AddPfmmff,@object # @_Z3AddPfmmff
.section .rodata,"a",@progbits
.globl _Z3AddPfmmff
.p2align 3, 0x0
_Z3AddPfmmff:
.quad _Z18__device_stub__AddPfmmff
.size _Z3AddPfmmff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3AddPfmmff"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__AddPfmmff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3AddPfmmff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3AddPfmmff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x170], RZ ; /* 0x80005c00ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe40007f1e1ff */
/*00e0*/ IADD3.X R3, RZ, ~c[0x0][0x174], RZ, P1, !PT ; /* 0x80005d00ff037a10 */
/* 0x000fe40000ffe4ff */
/*00f0*/ IADD3.X R6, R6, -0x1, RZ, P0, !PT ; /* 0xffffffff06067810 */
/* 0x000fc600007fe4ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x170], R2 ; /* 0x00005c0000027a25 */
/* 0x000fc800078e0002 */
/*0110*/ IMAD R7, R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a24 */
/* 0x000fe200078e02ff */
/*0120*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fc60000000f00 */
/*0130*/ IMAD R13, R0, c[0x0][0x174], R7 ; /* 0x00005d00000d7a24 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0150*/ IMAD.IADD R11, R3, 0x1, R13 ; /* 0x00000001030b7824 */
/* 0x000fe400078e020d */
/*0160*/ IADD3 R5, P0, R6, R2, RZ ; /* 0x0000000206057210 */
/* 0x000fca0007f1e0ff */
/*0170*/ IMAD.X R8, R7, 0x1, R11, P0 ; /* 0x0000000107087824 */
/* 0x000fe200000e060b */
/*0180*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fe200078010ff */
/*0190*/ IMAD.WIDE.U32 R6, R0, c[0x0][0x170], R6 ; /* 0x00005c0000067a25 */
/* 0x000fc600078e0006 */
/*01a0*/ LEA.HI.X R5, R5, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f1408 */
/*01b0*/ IADD3 R7, R13, R7, RZ ; /* 0x000000070d077210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LEA R8, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006087a11 */
/* 0x000fc800078010ff */
/*01d0*/ LEA.HI.X R9, R6, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590006097a11 */
/* 0x000fe400000f1407 */
/*01e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*0210*/ FMUL R7, R6, c[0x0][0x17c] ; /* 0x00005f0006077a20 */
/* 0x004fe40000400000 */
/*0220*/ IMAD R6, R15, c[0x0][0xc], R10 ; /* 0x000003000f067a24 */
/* 0x000fc400078e020a */
/*0230*/ FFMA R7, R8, c[0x0][0x178], R7 ; /* 0x00005e0008077a23 */
/* 0x008fc60000000007 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f06070 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0260*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe40000000f00 */
/*0270*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x001fc80000011406 */
/*0280*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*0290*/ @!P0 BRA 0x160 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3AddPfmmff
.globl _Z3AddPfmmff
.p2align 8
.type _Z3AddPfmmff,@function
_Z3AddPfmmff:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_load_b32 s12, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s10, -1
s_addc_u32 s5, s11, -1
s_mul_i32 s7, s4, s3
s_mul_hi_u32 s13, s4, s2
s_mul_i32 s5, s5, s2
s_add_i32 s7, s13, s7
s_mul_i32 s4, s4, s2
s_add_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_add_u32 s7, s10, -2
s_addc_u32 s10, s11, -1
s_mul_i32 s11, s7, s3
s_mul_hi_u32 s13, s7, s2
s_mul_i32 s14, s10, s2
s_add_i32 s11, s13, s11
s_mul_i32 s10, s7, s2
s_add_i32 s11, s11, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 2
s_add_u32 s7, s8, s10
s_addc_u32 s8, s9, s11
s_add_i32 s15, s15, s12
s_mov_b32 s9, 0
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s12, s6
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s7, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s8, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v0, v[0:1], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, s1, v2
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s6, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v7, s0, v0
global_store_b32 v[5:6], v7, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3AddPfmmff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3AddPfmmff, .Lfunc_end0-_Z3AddPfmmff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3AddPfmmff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3AddPfmmff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00011269_00000000-6_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3AddPfmmffPfmmff
.type _Z26__device_stub__Z3AddPfmmffPfmmff, @function
_Z26__device_stub__Z3AddPfmmffPfmmff:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3AddPfmmff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3AddPfmmffPfmmff, .-_Z26__device_stub__Z3AddPfmmffPfmmff
.globl _Z3AddPfmmff
.type _Z3AddPfmmff, @function
_Z3AddPfmmff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3AddPfmmffPfmmff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3AddPfmmff, .-_Z3AddPfmmff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3AddPfmmff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3AddPfmmff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "Add.hip"
.globl _Z18__device_stub__AddPfmmff # -- Begin function _Z18__device_stub__AddPfmmff
.p2align 4, 0x90
.type _Z18__device_stub__AddPfmmff,@function
_Z18__device_stub__AddPfmmff: # @_Z18__device_stub__AddPfmmff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3AddPfmmff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__AddPfmmff, .Lfunc_end0-_Z18__device_stub__AddPfmmff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3AddPfmmff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3AddPfmmff,@object # @_Z3AddPfmmff
.section .rodata,"a",@progbits
.globl _Z3AddPfmmff
.p2align 3, 0x0
_Z3AddPfmmff:
.quad _Z18__device_stub__AddPfmmff
.size _Z3AddPfmmff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3AddPfmmff"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__AddPfmmff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3AddPfmmff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x;
unsigned int start = 2 * blockIdx.x * BLOCK_SIZE;
if (start + t < size)
sdata[t] = in[start + t];
else
sdata[t] = 0;
if (start + BLOCK_SIZE + t < size)
sdata[BLOCK_SIZE + t] = in[start + BLOCK_SIZE + t];
else
sdata[BLOCK_SIZE + t] = 0;
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
sdata[t] += sdata[t+stride];
}
if (t == 0)
out[blockIdx.x] = sdata[0];
}
|
code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R4, R0, R3, 0xa ; /* 0x0000000300047211 */
/* 0x001fc800078e50ff */
/*0050*/ IADD3 R6, R4.reuse, 0x200, RZ ; /* 0x0000020004067810 */
/* 0x040fe40007ffe0ff */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26070 */
/*0070*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f46070 */
/*0080*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fe400078e00ff */
/*0090*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x000fe40000000f00 */
/*00a0*/ @!P1 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004049625 */
/* 0x000fc800078e0005 */
/*00b0*/ @!P2 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x168] ; /* 0x00005a000606a625 */
/* 0x000fe400078e0007 */
/*00c0*/ @!P1 LDG.E R4, [R4.64] ; /* 0x0000000404049981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000040606a981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fc60003f04070 */
/*00f0*/ @P1 STS [R3.X4], RZ ; /* 0x000000ff03001388 */
/* 0x000fe80000004800 */
/*0100*/ @P2 STS [R3.X4+0x800], RZ ; /* 0x000800ff03002388 */
/* 0x000fe80000004800 */
/*0110*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x004fe20000004800 */
/*0120*/ ISETP.GT.U32.AND P1, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fc60003f24070 */
/*0130*/ @!P2 STS [R3.X4+0x800], R6 ; /* 0x000800060300a388 */
/* 0x008fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0160*/ @!P0 LDS R9, [R3.X4+0x800] ; /* 0x0008000003098984 */
/* 0x000e240000004800 */
/*0170*/ @!P0 FADD R2, R2, R9 ; /* 0x0000000902028221 */
/* 0x001fca0000000000 */
/*0180*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fca0003f04070 */
/*01b0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*01c0*/ @!P1 LDS R4, [R3.X4+0x400] ; /* 0x0004000003049984 */
/* 0x000e240000004800 */
/*01d0*/ @!P1 FADD R4, R5, R4 ; /* 0x0000000405049221 */
/* 0x001fca0000000000 */
/*01e0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ ISETP.GT.U32.AND P1, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f24070 */
/*0210*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0220*/ @!P0 LDS R6, [R3.X4+0x200] ; /* 0x0002000003068984 */
/* 0x000e240000004800 */
/*0230*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0240*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f04070 */
/*0270*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0280*/ @!P1 LDS R5, [R3.X4+0x100] ; /* 0x0001000003059984 */
/* 0x000e240000004800 */
/*0290*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f24070 */
/*02d0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*02e0*/ @!P0 LDS R5, [R3.X4+0x80] ; /* 0x0000800003058984 */
/* 0x000e240000004800 */
/*02f0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0300*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.U32.AND P0, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f04070 */
/*0330*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*0340*/ @!P1 LDS R6, [R3.X4+0x40] ; /* 0x0000400003069984 */
/* 0x000e240000004800 */
/*0350*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*0360*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GT.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f24070 */
/*0390*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*03a0*/ @!P0 LDS R5, [R3.X4+0x20] ; /* 0x0000200003058984 */
/* 0x000e240000004800 */
/*03b0*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*03c0*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f04070 */
/*03f0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0400*/ @!P1 LDS R5, [R3.X4+0x10] ; /* 0x0000100003059984 */
/* 0x000e240000004800 */
/*0410*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0420*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0440*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f25270 */
/*0450*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0460*/ @!P0 LDS R6, [R3.X4+0x8] ; /* 0x0000080003068984 */
/* 0x000e240000004800 */
/*0470*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0480*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x0001e80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04a0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04b0*/ LDS R2, [0x4] ; /* 0x00000400ff027984 */
/* 0x001fe80000000800 */
/*04c0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000e240000004800 */
/*04d0*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x001fc40000000000 */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*04f0*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe20000004800 */
/*0500*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0005 */
/*0510*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e280000000800 */
/*0520*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x;
unsigned int start = 2 * blockIdx.x * BLOCK_SIZE;
if (start + t < size)
sdata[t] = in[start + t];
else
sdata[t] = 0;
if (start + BLOCK_SIZE + t < size)
sdata[BLOCK_SIZE + t] = in[start + BLOCK_SIZE + t];
else
sdata[BLOCK_SIZE + t] = 0;
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
sdata[t] += sdata[t+stride];
}
if (t == 0)
out[blockIdx.x] = sdata[0];
}
|
.file "tmpxft_0012211c_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_jPfS_j
.type _Z31__device_stub__Z9reductionPfS_jPfS_j, @function
_Z31__device_stub__Z9reductionPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPfS_jPfS_j, .-_Z31__device_stub__Z9reductionPfS_jPfS_j
.globl _Z9reductionPfS_j
.type _Z9reductionPfS_j, @function
_Z9reductionPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfS_j, .-_Z9reductionPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x;
unsigned int start = 2 * blockIdx.x * BLOCK_SIZE;
if (start + t < size)
sdata[t] = in[start + t];
else
sdata[t] = 0;
if (start + BLOCK_SIZE + t < size)
sdata[BLOCK_SIZE + t] = in[start + BLOCK_SIZE + t];
else
sdata[BLOCK_SIZE + t] = 0;
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
sdata[t] += sdata[t+stride];
}
if (t == 0)
out[blockIdx.x] = sdata[0];
}
|
#include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x;
unsigned int start = 2 * blockIdx.x * BLOCK_SIZE;
if (start + t < size)
sdata[t] = in[start + t];
else
sdata[t] = 0;
if (start + BLOCK_SIZE + t < size)
sdata[BLOCK_SIZE + t] = in[start + BLOCK_SIZE + t];
else
sdata[BLOCK_SIZE + t] = 0;
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
sdata[t] += sdata[t+stride];
}
if (t == 0)
out[blockIdx.x] = sdata[0];
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x;
unsigned int start = 2 * blockIdx.x * BLOCK_SIZE;
if (start + t < size)
sdata[t] = in[start + t];
else
sdata[t] = 0;
if (start + BLOCK_SIZE + t < size)
sdata[BLOCK_SIZE + t] = in[start + BLOCK_SIZE + t];
else
sdata[BLOCK_SIZE + t] = 0;
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
sdata[t] += sdata[t+stride];
}
if (t == 0)
out[blockIdx.x] = sdata[0];
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
s_lshl_b32 s6, s15, 10
v_mov_b32_e32 v4, 0
v_or_b32_e32 v1, s6, v0
v_mov_b32_e32 v2, 0
s_mov_b32 s2, s15
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v1, v0, s6, 0x200
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_movk_i32 s3, 0x200
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v4, v[1:2], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:2048
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v1, s3, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_j
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_j, .Lfunc_end0-_Z9reductionPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x;
unsigned int start = 2 * blockIdx.x * BLOCK_SIZE;
if (start + t < size)
sdata[t] = in[start + t];
else
sdata[t] = 0;
if (start + BLOCK_SIZE + t < size)
sdata[BLOCK_SIZE + t] = in[start + BLOCK_SIZE + t];
else
sdata[BLOCK_SIZE + t] = 0;
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
sdata[t] += sdata[t+stride];
}
if (t == 0)
out[blockIdx.x] = sdata[0];
}
|
.text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_j, .Lfunc_end0-_Z24__device_stub__reductionPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_j,@object # @_Z9reductionPfS_j
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_j
.p2align 3, 0x0
_Z9reductionPfS_j:
.quad _Z24__device_stub__reductionPfS_j
.size _Z9reductionPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R4, R0, R3, 0xa ; /* 0x0000000300047211 */
/* 0x001fc800078e50ff */
/*0050*/ IADD3 R6, R4.reuse, 0x200, RZ ; /* 0x0000020004067810 */
/* 0x040fe40007ffe0ff */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26070 */
/*0070*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f46070 */
/*0080*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fe400078e00ff */
/*0090*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x000fe40000000f00 */
/*00a0*/ @!P1 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004049625 */
/* 0x000fc800078e0005 */
/*00b0*/ @!P2 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x168] ; /* 0x00005a000606a625 */
/* 0x000fe400078e0007 */
/*00c0*/ @!P1 LDG.E R4, [R4.64] ; /* 0x0000000404049981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000040606a981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fc60003f04070 */
/*00f0*/ @P1 STS [R3.X4], RZ ; /* 0x000000ff03001388 */
/* 0x000fe80000004800 */
/*0100*/ @P2 STS [R3.X4+0x800], RZ ; /* 0x000800ff03002388 */
/* 0x000fe80000004800 */
/*0110*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x004fe20000004800 */
/*0120*/ ISETP.GT.U32.AND P1, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fc60003f24070 */
/*0130*/ @!P2 STS [R3.X4+0x800], R6 ; /* 0x000800060300a388 */
/* 0x008fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0160*/ @!P0 LDS R9, [R3.X4+0x800] ; /* 0x0008000003098984 */
/* 0x000e240000004800 */
/*0170*/ @!P0 FADD R2, R2, R9 ; /* 0x0000000902028221 */
/* 0x001fca0000000000 */
/*0180*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fca0003f04070 */
/*01b0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*01c0*/ @!P1 LDS R4, [R3.X4+0x400] ; /* 0x0004000003049984 */
/* 0x000e240000004800 */
/*01d0*/ @!P1 FADD R4, R5, R4 ; /* 0x0000000405049221 */
/* 0x001fca0000000000 */
/*01e0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ ISETP.GT.U32.AND P1, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f24070 */
/*0210*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0220*/ @!P0 LDS R6, [R3.X4+0x200] ; /* 0x0002000003068984 */
/* 0x000e240000004800 */
/*0230*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0240*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f04070 */
/*0270*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0280*/ @!P1 LDS R5, [R3.X4+0x100] ; /* 0x0001000003059984 */
/* 0x000e240000004800 */
/*0290*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f24070 */
/*02d0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*02e0*/ @!P0 LDS R5, [R3.X4+0x80] ; /* 0x0000800003058984 */
/* 0x000e240000004800 */
/*02f0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0300*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.U32.AND P0, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f04070 */
/*0330*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*0340*/ @!P1 LDS R6, [R3.X4+0x40] ; /* 0x0000400003069984 */
/* 0x000e240000004800 */
/*0350*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*0360*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GT.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f24070 */
/*0390*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*03a0*/ @!P0 LDS R5, [R3.X4+0x20] ; /* 0x0000200003058984 */
/* 0x000e240000004800 */
/*03b0*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*03c0*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f04070 */
/*03f0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0400*/ @!P1 LDS R5, [R3.X4+0x10] ; /* 0x0000100003059984 */
/* 0x000e240000004800 */
/*0410*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0420*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0440*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f25270 */
/*0450*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0460*/ @!P0 LDS R6, [R3.X4+0x8] ; /* 0x0000080003068984 */
/* 0x000e240000004800 */
/*0470*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0480*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x0001e80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04a0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04b0*/ LDS R2, [0x4] ; /* 0x00000400ff027984 */
/* 0x001fe80000000800 */
/*04c0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000e240000004800 */
/*04d0*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x001fc40000000000 */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*04f0*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe20000004800 */
/*0500*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0005 */
/*0510*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e280000000800 */
/*0520*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
s_lshl_b32 s6, s15, 10
v_mov_b32_e32 v4, 0
v_or_b32_e32 v1, s6, v0
v_mov_b32_e32 v2, 0
s_mov_b32 s2, s15
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v1, v0, s6, 0x200
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_movk_i32 s3, 0x200
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v4, v[1:2], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:2048
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v1, s3, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_j
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_j, .Lfunc_end0-_Z9reductionPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0012211c_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_jPfS_j
.type _Z31__device_stub__Z9reductionPfS_jPfS_j, @function
_Z31__device_stub__Z9reductionPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPfS_jPfS_j, .-_Z31__device_stub__Z9reductionPfS_jPfS_j
.globl _Z9reductionPfS_j
.type _Z9reductionPfS_j, @function
_Z9reductionPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfS_j, .-_Z9reductionPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_j, .Lfunc_end0-_Z24__device_stub__reductionPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_j,@object # @_Z9reductionPfS_j
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_j
.p2align 3, 0x0
_Z9reductionPfS_j:
.quad _Z24__device_stub__reductionPfS_j
.size _Z9reductionPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdlib.h>
#include <stdio.h>
// The conventions for pointers is: if the value is stored in the device(GPU) it starts with d_, else if the value is stored
// in the host(CPU) the convention is to start with a h_
__global__ void kernel(float *d_out, float *d_in)
{
// Create a function that returns pointers
int idx = threadIdx.x;
float f = d_in[idx];
// Output to a pointer from a float operation
d_out[idx] = f * f * f;
}
int main()
{
// Define the size of the array to utilize
const int ARRAY_SIZE = 1000;
// Calculate the size in bytes
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// Create the input array on the host(CPU)
float h_in[ARRAY_SIZE];
for(int i = 0; i<ARRAY_SIZE; i++)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
// Declare GPU memory pointers
float *d_in;
float *d_out;
// Allocate GPU memory
cudaMalloc((void **)&d_in, ARRAY_BYTES);
cudaMalloc((void **)&d_out, ARRAY_BYTES);
// Transfer the array to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
// Launch the kernel, each block(left input) defines how many times the threads(right input) will be executed
kernel <<<1, ARRAY_SIZE>>>(d_out, d_in);
// Copy back the array to the host
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
// Print the resulting array
for(int i = 0; i<ARRAY_SIZE; i++)
{
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cudaFree(d_in);
cudaFree(d_out);
system("pause");
return 0;
}
|
code for sm_80
Function : _Z6kernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fc80000400000 */
/*0080*/ FMUL R7, R2, R7 ; /* 0x0000000702077220 */
/* 0x000fca0000400000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdlib.h>
#include <stdio.h>
// The conventions for pointers is: if the value is stored in the device(GPU) it starts with d_, else if the value is stored
// in the host(CPU) the convention is to start with a h_
__global__ void kernel(float *d_out, float *d_in)
{
// Create a function that returns pointers
int idx = threadIdx.x;
float f = d_in[idx];
// Output to a pointer from a float operation
d_out[idx] = f * f * f;
}
int main()
{
// Define the size of the array to utilize
const int ARRAY_SIZE = 1000;
// Calculate the size in bytes
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// Create the input array on the host(CPU)
float h_in[ARRAY_SIZE];
for(int i = 0; i<ARRAY_SIZE; i++)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
// Declare GPU memory pointers
float *d_in;
float *d_out;
// Allocate GPU memory
cudaMalloc((void **)&d_in, ARRAY_BYTES);
cudaMalloc((void **)&d_out, ARRAY_BYTES);
// Transfer the array to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
// Launch the kernel, each block(left input) defines how many times the threads(right input) will be executed
kernel <<<1, ARRAY_SIZE>>>(d_out, d_in);
// Copy back the array to the host
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
// Print the resulting array
for(int i = 0; i<ARRAY_SIZE; i++)
{
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cudaFree(d_in);
cudaFree(d_out);
system("pause");
return 0;
}
|
.file "tmpxft_00155985_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPfS_PfS_
.type _Z27__device_stub__Z6kernelPfS_PfS_, @function
_Z27__device_stub__Z6kernelPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPfS_PfS_, .-_Z27__device_stub__Z6kernelPfS_PfS_
.globl _Z6kernelPfS_
.type _Z6kernelPfS_, @function
_Z6kernelPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPfS_, .-_Z6kernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.LC1:
.string "\n"
.LC2:
.string "%f"
.LC3:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $3968, %rsp
.cfi_def_cfa_offset 8112
movq %fs:40, %rax
movq %rax, 8056(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1000, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
leaq 4048(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 4048(%rsp), %r14
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
movq %rbp, %rsi
cmove %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1000, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rdi
call system@PLT
movq 8056(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $8064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6kernelPfS_PfS_
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6kernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdlib.h>
#include <stdio.h>
// The conventions for pointers is: if the value is stored in the device(GPU) it starts with d_, else if the value is stored
// in the host(CPU) the convention is to start with a h_
__global__ void kernel(float *d_out, float *d_in)
{
// Create a function that returns pointers
int idx = threadIdx.x;
float f = d_in[idx];
// Output to a pointer from a float operation
d_out[idx] = f * f * f;
}
int main()
{
// Define the size of the array to utilize
const int ARRAY_SIZE = 1000;
// Calculate the size in bytes
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// Create the input array on the host(CPU)
float h_in[ARRAY_SIZE];
for(int i = 0; i<ARRAY_SIZE; i++)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
// Declare GPU memory pointers
float *d_in;
float *d_out;
// Allocate GPU memory
cudaMalloc((void **)&d_in, ARRAY_BYTES);
cudaMalloc((void **)&d_out, ARRAY_BYTES);
// Transfer the array to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
// Launch the kernel, each block(left input) defines how many times the threads(right input) will be executed
kernel <<<1, ARRAY_SIZE>>>(d_out, d_in);
// Copy back the array to the host
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
// Print the resulting array
for(int i = 0; i<ARRAY_SIZE; i++)
{
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cudaFree(d_in);
cudaFree(d_out);
system("pause");
return 0;
}
|
#include "hip/hip_runtime.h"
#include <stdlib.h>
#include <stdio.h>
// The conventions for pointers is: if the value is stored in the device(GPU) it starts with d_, else if the value is stored
// in the host(CPU) the convention is to start with a h_
__global__ void kernel(float *d_out, float *d_in)
{
// Create a function that returns pointers
int idx = threadIdx.x;
float f = d_in[idx];
// Output to a pointer from a float operation
d_out[idx] = f * f * f;
}
int main()
{
// Define the size of the array to utilize
const int ARRAY_SIZE = 1000;
// Calculate the size in bytes
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// Create the input array on the host(CPU)
float h_in[ARRAY_SIZE];
for(int i = 0; i<ARRAY_SIZE; i++)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
// Declare GPU memory pointers
float *d_in;
float *d_out;
// Allocate GPU memory
hipMalloc((void **)&d_in, ARRAY_BYTES);
hipMalloc((void **)&d_out, ARRAY_BYTES);
// Transfer the array to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
// Launch the kernel, each block(left input) defines how many times the threads(right input) will be executed
kernel <<<1, ARRAY_SIZE>>>(d_out, d_in);
// Copy back the array to the host
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
// Print the resulting array
for(int i = 0; i<ARRAY_SIZE; i++)
{
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
hipFree(d_in);
hipFree(d_out);
system("pause");
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include "hip/hip_runtime.h"
#include <stdlib.h>
#include <stdio.h>
// The conventions for pointers is: if the value is stored in the device(GPU) it starts with d_, else if the value is stored
// in the host(CPU) the convention is to start with a h_
__global__ void kernel(float *d_out, float *d_in)
{
// Create a function that returns pointers
int idx = threadIdx.x;
float f = d_in[idx];
// Output to a pointer from a float operation
d_out[idx] = f * f * f;
}
int main()
{
// Define the size of the array to utilize
const int ARRAY_SIZE = 1000;
// Calculate the size in bytes
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// Create the input array on the host(CPU)
float h_in[ARRAY_SIZE];
for(int i = 0; i<ARRAY_SIZE; i++)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
// Declare GPU memory pointers
float *d_in;
float *d_out;
// Allocate GPU memory
hipMalloc((void **)&d_in, ARRAY_BYTES);
hipMalloc((void **)&d_out, ARRAY_BYTES);
// Transfer the array to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
// Launch the kernel, each block(left input) defines how many times the threads(right input) will be executed
kernel <<<1, ARRAY_SIZE>>>(d_out, d_in);
// Copy back the array to the host
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
// Print the resulting array
for(int i = 0; i<ARRAY_SIZE; i++)
{
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
hipFree(d_in);
hipFree(d_out);
system("pause");
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_
.globl _Z6kernelPfS_
.p2align 8
.type _Z6kernelPfS_,@function
_Z6kernelPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_, .Lfunc_end0-_Z6kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdlib.h>
#include <stdio.h>
// The conventions for pointers is: if the value is stored in the device(GPU) it starts with d_, else if the value is stored
// in the host(CPU) the convention is to start with a h_
__global__ void kernel(float *d_out, float *d_in)
{
// Create a function that returns pointers
int idx = threadIdx.x;
float f = d_in[idx];
// Output to a pointer from a float operation
d_out[idx] = f * f * f;
}
int main()
{
// Define the size of the array to utilize
const int ARRAY_SIZE = 1000;
// Calculate the size in bytes
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
// Create the input array on the host(CPU)
float h_in[ARRAY_SIZE];
for(int i = 0; i<ARRAY_SIZE; i++)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
// Declare GPU memory pointers
float *d_in;
float *d_out;
// Allocate GPU memory
hipMalloc((void **)&d_in, ARRAY_BYTES);
hipMalloc((void **)&d_out, ARRAY_BYTES);
// Transfer the array to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
// Launch the kernel, each block(left input) defines how many times the threads(right input) will be executed
kernel <<<1, ARRAY_SIZE>>>(d_out, d_in);
// Copy back the array to the host
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
// Print the resulting array
for(int i = 0; i<ARRAY_SIZE; i++)
{
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
hipFree(d_in);
hipFree(d_out);
system("pause");
return 0;
}
|
.text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_ # -- Begin function _Z21__device_stub__kernelPfS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_,@function
_Z21__device_stub__kernelPfS_: # @_Z21__device_stub__kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_, .Lfunc_end0-_Z21__device_stub__kernelPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $8088, %rsp # imm = 0x1F98
.cfi_def_cfa_offset 8112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 4080(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4080(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 999(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r14d, %eax
notl %eax
testb $3, %al
movl $.L.str.1, %edi
cmoveq %rbx, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $1000, %r14 # imm = 0x3E8
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str.3, %edi
callq system
xorl %eax, %eax
addq $8088, %rsp # imm = 0x1F98
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_,@object # @_Z6kernelPfS_
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_
.p2align 3, 0x0
_Z6kernelPfS_:
.quad _Z21__device_stub__kernelPfS_
.size _Z6kernelPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "pause"
.size .L.str.3, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6kernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fc80000400000 */
/*0080*/ FMUL R7, R2, R7 ; /* 0x0000000702077220 */
/* 0x000fca0000400000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_
.globl _Z6kernelPfS_
.p2align 8
.type _Z6kernelPfS_,@function
_Z6kernelPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_, .Lfunc_end0-_Z6kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00155985_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPfS_PfS_
.type _Z27__device_stub__Z6kernelPfS_PfS_, @function
_Z27__device_stub__Z6kernelPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPfS_PfS_, .-_Z27__device_stub__Z6kernelPfS_PfS_
.globl _Z6kernelPfS_
.type _Z6kernelPfS_, @function
_Z6kernelPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPfS_, .-_Z6kernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.LC1:
.string "\n"
.LC2:
.string "%f"
.LC3:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $3968, %rsp
.cfi_def_cfa_offset 8112
movq %fs:40, %rax
movq %rax, 8056(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1000, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
leaq 4048(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 4048(%rsp), %r14
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
movq %rbp, %rsi
cmove %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1000, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rdi
call system@PLT
movq 8056(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $8064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6kernelPfS_PfS_
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6kernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_ # -- Begin function _Z21__device_stub__kernelPfS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_,@function
_Z21__device_stub__kernelPfS_: # @_Z21__device_stub__kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_, .Lfunc_end0-_Z21__device_stub__kernelPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $8088, %rsp # imm = 0x1F98
.cfi_def_cfa_offset 8112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 4080(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4080(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 999(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r14d, %eax
notl %eax
testb $3, %al
movl $.L.str.1, %edi
cmoveq %rbx, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $1000, %r14 # imm = 0x3E8
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str.3, %edi
callq system
xorl %eax, %eax
addq $8088, %rsp # imm = 0x1F98
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_,@object # @_Z6kernelPfS_
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_
.p2align 3, 0x0
_Z6kernelPfS_:
.quad _Z21__device_stub__kernelPfS_
.size _Z6kernelPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "pause"
.size .L.str.3, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
float res = 0.;
for(int i=0;i<N;++i) res += input[i];
*output = res/N;
}
|
code for sm_80
Function : _Z11naiveKerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0040*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 BRA 0x750 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R4.reuse, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00b0*/ @!P0 BRA 0x670 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fd400078e00ff */
/*0120*/ @!P0 BRA 0x570 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x3d0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x0000a8000c1e1900 */
/*0180*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000408020e7981 */
/* 0x0000e8000c1e1900 */
/*0190*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080802107981 */
/* 0x000128000c1e1900 */
/*01a0*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0802127981 */
/* 0x000168000c1e1900 */
/*01b0*/ LDG.E R20, [R2.64+0x10] ; /* 0x0000100802147981 */
/* 0x000168000c1e1900 */
/*01c0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140802167981 */
/* 0x000168000c1e1900 */
/*01d0*/ LDG.E R24, [R2.64+0x18] ; /* 0x0000180802187981 */
/* 0x000168000c1e1900 */
/*01e0*/ LDG.E R26, [R2.64+0x1c] ; /* 0x00001c08021a7981 */
/* 0x000168000c1e1900 */
/*01f0*/ LDG.E R28, [R2.64+0x20] ; /* 0x00002008021c7981 */
/* 0x000168000c1e1900 */
/*0200*/ LDG.E R12, [R2.64+0x24] ; /* 0x00002408020c7981 */
/* 0x000168000c1e1900 */
/*0210*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002808020b7981 */
/* 0x000168000c1e1900 */
/*0220*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c08020a7981 */
/* 0x000168000c1e1900 */
/*0230*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300802097981 */
/* 0x000168000c1e1900 */
/*0240*/ LDG.E R7, [R2.64+0x34] ; /* 0x0000340802077981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380802087981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R6, [R2.64+0x3c] ; /* 0x00003c0802067981 */
/* 0x000162000c1e1900 */
/*0270*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*0280*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0290*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*02a0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f5e0ff */
/*02b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*02c0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fc80000000000 */
/*02d0*/ FADD R13, R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x008fc80000000000 */
/*02e0*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x010fc80000000000 */
/*02f0*/ FADD R13, R13, R18 ; /* 0x000000120d0d7221 */
/* 0x020fc80000000000 */
/*0300*/ FADD R13, R13, R20 ; /* 0x000000140d0d7221 */
/* 0x000fc80000000000 */
/*0310*/ FADD R13, R13, R22 ; /* 0x000000160d0d7221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R13, R13, R24 ; /* 0x000000180d0d7221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R13, R13, R26 ; /* 0x0000001a0d0d7221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R13, R13, R28 ; /* 0x0000001c0d0d7221 */
/* 0x000fc80000000000 */
/*0350*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R11, R12, R11 ; /* 0x0000000b0c0b7221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R10, R10, R9 ; /* 0x000000090a0a7221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R7, R10, R7 ; /* 0x000000070a077221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R0, R7, R6 ; /* 0x0000000607007221 */
/* 0x000fe20000000000 */
/*03c0*/ @P1 BRA 0x170 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*03d0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*03e0*/ @!P1 BRA 0x550 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*03f0*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080802097981 */
/* 0x000f28000c1e1900 */
/*0420*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c08020b7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001008020d7981 */
/* 0x000168000c1e1900 */
/*0440*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001408020f7981 */
/* 0x000168000c1e1900 */
/*0450*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180802117981 */
/* 0x000168000c1e1900 */
/*0460*/ LDG.E R19, [R2.64+0x1c] ; /* 0x00001c0802137981 */
/* 0x000162000c1e1900 */
/*0470*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0480*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0490*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fc80000000000 */
/*04b0*/ FADD R6, R7, R6 ; /* 0x0000000607067221 */
/* 0x008fe20000000000 */
/*04c0*/ IADD3 R7, P1, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fc60007f3e0ff */
/*04d0*/ FADD R6, R6, R9 ; /* 0x0000000906067221 */
/* 0x010fe40000000000 */
/*04e0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe400008e0603 */
/*04f0*/ FADD R6, R6, R11 ; /* 0x0000000b06067221 */
/* 0x020fe40000000000 */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0510*/ FADD R6, R6, R13 ; /* 0x0000000d06067221 */
/* 0x000fc80000000000 */
/*0520*/ FADD R6, R6, R15 ; /* 0x0000000f06067221 */
/* 0x000fc80000000000 */
/*0530*/ FADD R6, R6, R17 ; /* 0x0000001106067221 */
/* 0x000fc80000000000 */
/*0540*/ FADD R0, R6, R19 ; /* 0x0000001306007221 */
/* 0x000fe40000000000 */
/*0550*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0560*/ @!P0 BRA 0x670 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ee8000c1e1900 */
/*0590*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080802097981 */
/* 0x000f28000c1e1900 */
/*05a0*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c08020b7981 */
/* 0x000f62000c1e1900 */
/*05b0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*05d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*05e0*/ FADD R7, R7, R0 ; /* 0x0000000007077221 */
/* 0x004fc80000000000 */
/*05f0*/ FADD R6, R7, R6 ; /* 0x0000000607067221 */
/* 0x008fe20000000000 */
/*0600*/ IADD3 R7, P1, R2, 0x10, RZ ; /* 0x0000001002077810 */
/* 0x000fc60007f3e0ff */
/*0610*/ FADD R6, R6, R9 ; /* 0x0000000906067221 */
/* 0x010fe40000000000 */
/*0620*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe400008e0603 */
/*0630*/ FADD R0, R6, R11 ; /* 0x0000000b06007221 */
/* 0x020fe40000000000 */
/*0640*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0660*/ @P0 BRA 0x570 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0680*/ @!P0 BRA 0x750 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0690*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*06a0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*06b0*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*06c0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe4000f8e00ff */
/*06d0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fca000f8e00ff */
/*06e0*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0700*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000ff1e03f */
/*0710*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0720*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0730*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x004fd60000000000 */
/*0740*/ @P0 BRA 0x6c0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0750*/ I2F R3, c[0x0][0x160] ; /* 0x0000580000037b06 */
/* 0x000e300000201400 */
/*0760*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e300000001000 */
/*0770*/ FCHK P0, R0, R3 ; /* 0x0000000300007302 */
/* 0x000e620000000000 */
/*0780*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*0790*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fc80000000002 */
/*07a0*/ FFMA R2, R5, R0, RZ ; /* 0x0000000005027223 */
/* 0x000fc800000000ff */
/*07b0*/ FFMA R4, -R3, R2, R0 ; /* 0x0000000203047223 */
/* 0x000fc80000000100 */
/*07c0*/ FFMA R5, R5, R4, R2 ; /* 0x0000000405057223 */
/* 0x000fe20000000002 */
/*07d0*/ @!P0 BRA 0x810 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*07e0*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe40000000f00 */
/*07f0*/ MOV R0, 0x810 ; /* 0x0000081000007802 */
/* 0x000fe40000000f00 */
/*0800*/ CALL.REL.NOINC 0x850 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0810*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0820*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0830*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101908 */
/*0840*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0850*/ SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011603 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*0870*/ SHF.R.U32.HI R2, RZ, 0x17, R8.reuse ; /* 0x00000017ff027819 */
/* 0x100fe40000011608 */
/*0880*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0890*/ LOP3.LUT R9, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02097812 */
/* 0x000fe200078ec0ff */
/*08a0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*08b0*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R10, R9, -0x1, RZ ; /* 0xffffffff090a7810 */
/* 0x000fc40007ffe0ff */
/*08d0*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fc80003f04070 */
/*08e0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*08f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0900*/ @!P0 BRA 0xa80 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0910*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0920*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0940*/ @P0 BRA 0xe60 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, R2, 0xc8, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c802 */
/*0960*/ @!P0 BRA 0xe40 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0980*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0990*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*09a0*/ @!P1 BRA !P2, 0xe40 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*09b0*/ LOP3.LUT P2, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02ff7812 */
/* 0x000fc8000784c0ff */
/*09c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*09d0*/ @P1 BRA 0xe20 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*09f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a00*/ @P0 BRA 0xdf0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0a20*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f26270 */
/*0a30*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0a40*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0a50*/ @!P0 FFMA R2, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008028823 */
/* 0x000fe400000000ff */
/*0a60*/ @!P1 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003059823 */
/* 0x000fe200000000ff */
/*0a70*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ LEA R8, R4, 0xc0800000, 0x17 ; /* 0xc080000004087811 */
/* 0x000fe400078eb8ff */
/*0a90*/ IADD3 R3, R9, -0x7f, RZ ; /* 0xffffff8109037810 */
/* 0x000fc60007ffe0ff */
/*0aa0*/ IMAD.IADD R8, R5, 0x1, -R8 ; /* 0x0000000105087824 */
/* 0x000fe400078e0a08 */
/*0ab0*/ IMAD R2, R3.reuse, -0x800000, R2 ; /* 0xff80000003027824 */
/* 0x040fe200078e0202 */
/*0ac0*/ IADD3 R3, R3, 0x7f, -R4 ; /* 0x0000007f03037810 */
/* 0x000fe20007ffe804 */
/*0ad0*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e220000001000 */
/*0ae0*/ FADD.FTZ R7, -R8, -RZ ; /* 0x800000ff08077221 */
/* 0x000fe40000010100 */
/*0af0*/ IADD3 R3, R3, R6, RZ ; /* 0x0000000603037210 */
/* 0x000fe40007ffe0ff */
/*0b00*/ FFMA R10, R5, R7, 1 ; /* 0x3f800000050a7423 */
/* 0x001fc80000000007 */
/*0b10*/ FFMA R9, R5, R10, R5 ; /* 0x0000000a05097223 */
/* 0x000fc80000000005 */
/*0b20*/ FFMA R5, R2, R9, RZ ; /* 0x0000000902057223 */
/* 0x000fc800000000ff */
/*0b30*/ FFMA R10, R7, R5, R2 ; /* 0x00000005070a7223 */
/* 0x000fc80000000002 */
/*0b40*/ FFMA R10, R9, R10, R5 ; /* 0x0000000a090a7223 */
/* 0x000fc80000000005 */
/*0b50*/ FFMA R7, R7, R10, R2 ; /* 0x0000000a07077223 */
/* 0x000fc80000000002 */
/*0b60*/ FFMA R5, R9, R7, R10 ; /* 0x0000000709057223 */
/* 0x000fca000000000a */
/*0b70*/ SHF.R.U32.HI R2, RZ, 0x17, R5 ; /* 0x00000017ff027819 */
/* 0x000fc80000011605 */
/*0b80*/ LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02027812 */
/* 0x000fca00078ec0ff */
/*0b90*/ IMAD.IADD R6, R2, 0x1, R3 ; /* 0x0000000102067824 */
/* 0x000fca00078e0203 */
/*0ba0*/ IADD3 R2, R6, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x000fc80007ffe0ff */
/*0bb0*/ ISETP.GE.U32.AND P0, PT, R2, 0xfe, PT ; /* 0x000000fe0200780c */
/* 0x000fda0003f06070 */
/*0bc0*/ @!P0 BRA 0xdd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ ISETP.GT.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f04270 */
/*0be0*/ @P0 BRA 0xda0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*0c00*/ @P0 BRA 0xe70 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.GE.AND P0, PT, R6, -0x18, PT ; /* 0xffffffe80600780c */
/* 0x000fe40003f06270 */
/*0c20*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0c30*/ @!P0 BRA 0xe70 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0c40*/ FFMA.RZ R2, R9.reuse, R7.reuse, R10.reuse ; /* 0x0000000709027223 */
/* 0x1c0fe2000000c00a */
/*0c50*/ ISETP.NE.AND P2, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe20003f45270 */
/*0c60*/ FFMA.RM R3, R9.reuse, R7.reuse, R10.reuse ; /* 0x0000000709037223 */
/* 0x1c0fe2000000400a */
/*0c70*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0c80*/ LOP3.LUT R4, R2, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff02047812 */
/* 0x000fe200078ec0ff */
/*0c90*/ FFMA.RP R2, R9, R7, R10 ; /* 0x0000000709027223 */
/* 0x000fe2000000800a */
/*0ca0*/ IADD3 R7, R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a06 */
/*0cc0*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fe400078efcff */
/*0cd0*/ FSETP.NEU.FTZ.AND P0, PT, R2, R3, PT ; /* 0x000000030200720b */
/* 0x000fc40003f1d000 */
/*0ce0*/ SHF.L.U32 R7, R4, R7, RZ ; /* 0x0000000704077219 */
/* 0x000fe400000006ff */
/*0cf0*/ SEL R3, R6, RZ, P2 ; /* 0x000000ff06037207 */
/* 0x000fe40001000000 */
/*0d00*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0d10*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*0d20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0d30*/ SHF.R.U32.HI R7, RZ, 0x1, R3 ; /* 0x00000001ff077819 */
/* 0x000fc40000011603 */
/*0d40*/ SEL R2, RZ, 0x1, !P0 ; /* 0x00000001ff027807 */
/* 0x000fc80004000000 */
/*0d50*/ LOP3.LUT R2, R2, 0x1, R7, 0xf8, !PT ; /* 0x0000000102027812 */
/* 0x000fc800078ef807 */
/*0d60*/ LOP3.LUT R2, R2, R3, RZ, 0xc0, !PT ; /* 0x0000000302027212 */
/* 0x000fca00078ec0ff */
/*0d70*/ IMAD.IADD R2, R7, 0x1, R2 ; /* 0x0000000107027824 */
/* 0x000fca00078e0202 */
/*0d80*/ LOP3.LUT R5, R2, R5, RZ, 0xfc, !PT ; /* 0x0000000502057212 */
/* 0x000fe200078efcff */
/*0d90*/ BRA 0xe70 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0da0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0db0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0dc0*/ BRA 0xe70 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0dd0*/ IMAD R5, R3, 0x800000, R5 ; /* 0x0080000003057824 */
/* 0x000fe200078e0205 */
/*0de0*/ BRA 0xe70 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0df0*/ LOP3.LUT R5, R5, 0x80000000, R2, 0x48, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078e4802 */
/*0e00*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0e10*/ BRA 0xe70 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e20*/ LOP3.LUT R5, R5, 0x80000000, R2, 0x48, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078e4802 */
/*0e30*/ BRA 0xe70 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e40*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0e50*/ BRA 0xe70 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e60*/ FADD.FTZ R5, R8, R3 ; /* 0x0000000308057221 */
/* 0x000fe40000010000 */
/*0e70*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0e80*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0e90*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff16002007950 */
/* 0x000fea0003c3ffff */
/*0ea0*/ BRA 0xea0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
float res = 0.;
for(int i=0;i<N;++i) res += input[i];
*output = res/N;
}
|
.file "tmpxft_000a7ef6_00000000-6_naiveKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.type _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, @function
_Z34__device_stub__Z11naiveKerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11naiveKerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, .-_Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.globl _Z11naiveKerneliPfS_
.type _Z11naiveKerneliPfS_, @function
_Z11naiveKerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11naiveKerneliPfS_, .-_Z11naiveKerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11naiveKerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11naiveKerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
float res = 0.;
for(int i=0;i<N;++i) res += input[i];
*output = res/N;
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
float res = 0.;
for(int i=0;i<N;++i) res += input[i];
*output = res/N;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
float res = 0.;
for(int i=0;i<N;++i) res += input[i];
*output = res/N;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11naiveKerneliPfS_
.globl _Z11naiveKerneliPfS_
.p2align 8
.type _Z11naiveKerneliPfS_,@function
_Z11naiveKerneliPfS_:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s5, s4
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_add_i32 s5, s5, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, s6, v0
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
.LBB0_4:
v_cvt_f32_i32_e32 v1, s4
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v2, null, v1, v1, v0
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v0, v1, v0
v_mul_f32_e32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v5, v4
v_fmac_f32_e32 v5, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v5, v4
v_div_fmas_f32 v2, v2, v3, v5
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v0, v2, v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11naiveKerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11naiveKerneliPfS_, .Lfunc_end0-_Z11naiveKerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11naiveKerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z11naiveKerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
float res = 0.;
for(int i=0;i<N;++i) res += input[i];
*output = res/N;
}
|
.text
.file "naiveKernel.hip"
.globl _Z26__device_stub__naiveKerneliPfS_ # -- Begin function _Z26__device_stub__naiveKerneliPfS_
.p2align 4, 0x90
.type _Z26__device_stub__naiveKerneliPfS_,@function
_Z26__device_stub__naiveKerneliPfS_: # @_Z26__device_stub__naiveKerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11naiveKerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__naiveKerneliPfS_, .Lfunc_end0-_Z26__device_stub__naiveKerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11naiveKerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11naiveKerneliPfS_,@object # @_Z11naiveKerneliPfS_
.section .rodata,"a",@progbits
.globl _Z11naiveKerneliPfS_
.p2align 3, 0x0
_Z11naiveKerneliPfS_:
.quad _Z26__device_stub__naiveKerneliPfS_
.size _Z11naiveKerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11naiveKerneliPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__naiveKerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11naiveKerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11naiveKerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0040*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 BRA 0x750 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R4.reuse, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00b0*/ @!P0 BRA 0x670 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fd400078e00ff */
/*0120*/ @!P0 BRA 0x570 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x3d0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x0000a8000c1e1900 */
/*0180*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000408020e7981 */
/* 0x0000e8000c1e1900 */
/*0190*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080802107981 */
/* 0x000128000c1e1900 */
/*01a0*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0802127981 */
/* 0x000168000c1e1900 */
/*01b0*/ LDG.E R20, [R2.64+0x10] ; /* 0x0000100802147981 */
/* 0x000168000c1e1900 */
/*01c0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140802167981 */
/* 0x000168000c1e1900 */
/*01d0*/ LDG.E R24, [R2.64+0x18] ; /* 0x0000180802187981 */
/* 0x000168000c1e1900 */
/*01e0*/ LDG.E R26, [R2.64+0x1c] ; /* 0x00001c08021a7981 */
/* 0x000168000c1e1900 */
/*01f0*/ LDG.E R28, [R2.64+0x20] ; /* 0x00002008021c7981 */
/* 0x000168000c1e1900 */
/*0200*/ LDG.E R12, [R2.64+0x24] ; /* 0x00002408020c7981 */
/* 0x000168000c1e1900 */
/*0210*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002808020b7981 */
/* 0x000168000c1e1900 */
/*0220*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c08020a7981 */
/* 0x000168000c1e1900 */
/*0230*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300802097981 */
/* 0x000168000c1e1900 */
/*0240*/ LDG.E R7, [R2.64+0x34] ; /* 0x0000340802077981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380802087981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R6, [R2.64+0x3c] ; /* 0x00003c0802067981 */
/* 0x000162000c1e1900 */
/*0270*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*0280*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0290*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*02a0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f5e0ff */
/*02b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*02c0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fc80000000000 */
/*02d0*/ FADD R13, R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x008fc80000000000 */
/*02e0*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x010fc80000000000 */
/*02f0*/ FADD R13, R13, R18 ; /* 0x000000120d0d7221 */
/* 0x020fc80000000000 */
/*0300*/ FADD R13, R13, R20 ; /* 0x000000140d0d7221 */
/* 0x000fc80000000000 */
/*0310*/ FADD R13, R13, R22 ; /* 0x000000160d0d7221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R13, R13, R24 ; /* 0x000000180d0d7221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R13, R13, R26 ; /* 0x0000001a0d0d7221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R13, R13, R28 ; /* 0x0000001c0d0d7221 */
/* 0x000fc80000000000 */
/*0350*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R11, R12, R11 ; /* 0x0000000b0c0b7221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R10, R10, R9 ; /* 0x000000090a0a7221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R7, R10, R7 ; /* 0x000000070a077221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R0, R7, R6 ; /* 0x0000000607007221 */
/* 0x000fe20000000000 */
/*03c0*/ @P1 BRA 0x170 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*03d0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*03e0*/ @!P1 BRA 0x550 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*03f0*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080802097981 */
/* 0x000f28000c1e1900 */
/*0420*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c08020b7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001008020d7981 */
/* 0x000168000c1e1900 */
/*0440*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001408020f7981 */
/* 0x000168000c1e1900 */
/*0450*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180802117981 */
/* 0x000168000c1e1900 */
/*0460*/ LDG.E R19, [R2.64+0x1c] ; /* 0x00001c0802137981 */
/* 0x000162000c1e1900 */
/*0470*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0480*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0490*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fc80000000000 */
/*04b0*/ FADD R6, R7, R6 ; /* 0x0000000607067221 */
/* 0x008fe20000000000 */
/*04c0*/ IADD3 R7, P1, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fc60007f3e0ff */
/*04d0*/ FADD R6, R6, R9 ; /* 0x0000000906067221 */
/* 0x010fe40000000000 */
/*04e0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe400008e0603 */
/*04f0*/ FADD R6, R6, R11 ; /* 0x0000000b06067221 */
/* 0x020fe40000000000 */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0510*/ FADD R6, R6, R13 ; /* 0x0000000d06067221 */
/* 0x000fc80000000000 */
/*0520*/ FADD R6, R6, R15 ; /* 0x0000000f06067221 */
/* 0x000fc80000000000 */
/*0530*/ FADD R6, R6, R17 ; /* 0x0000001106067221 */
/* 0x000fc80000000000 */
/*0540*/ FADD R0, R6, R19 ; /* 0x0000001306007221 */
/* 0x000fe40000000000 */
/*0550*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0560*/ @!P0 BRA 0x670 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ee8000c1e1900 */
/*0590*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080802097981 */
/* 0x000f28000c1e1900 */
/*05a0*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c08020b7981 */
/* 0x000f62000c1e1900 */
/*05b0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*05d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*05e0*/ FADD R7, R7, R0 ; /* 0x0000000007077221 */
/* 0x004fc80000000000 */
/*05f0*/ FADD R6, R7, R6 ; /* 0x0000000607067221 */
/* 0x008fe20000000000 */
/*0600*/ IADD3 R7, P1, R2, 0x10, RZ ; /* 0x0000001002077810 */
/* 0x000fc60007f3e0ff */
/*0610*/ FADD R6, R6, R9 ; /* 0x0000000906067221 */
/* 0x010fe40000000000 */
/*0620*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe400008e0603 */
/*0630*/ FADD R0, R6, R11 ; /* 0x0000000b06007221 */
/* 0x020fe40000000000 */
/*0640*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0660*/ @P0 BRA 0x570 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0680*/ @!P0 BRA 0x750 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0690*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*06a0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*06b0*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*06c0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe4000f8e00ff */
/*06d0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fca000f8e00ff */
/*06e0*/ LDG.E R3, [R2.64] ; /* 0x0000000802037981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0700*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000ff1e03f */
/*0710*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0720*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0730*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x004fd60000000000 */
/*0740*/ @P0 BRA 0x6c0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0750*/ I2F R3, c[0x0][0x160] ; /* 0x0000580000037b06 */
/* 0x000e300000201400 */
/*0760*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e300000001000 */
/*0770*/ FCHK P0, R0, R3 ; /* 0x0000000300007302 */
/* 0x000e620000000000 */
/*0780*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*0790*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fc80000000002 */
/*07a0*/ FFMA R2, R5, R0, RZ ; /* 0x0000000005027223 */
/* 0x000fc800000000ff */
/*07b0*/ FFMA R4, -R3, R2, R0 ; /* 0x0000000203047223 */
/* 0x000fc80000000100 */
/*07c0*/ FFMA R5, R5, R4, R2 ; /* 0x0000000405057223 */
/* 0x000fe20000000002 */
/*07d0*/ @!P0 BRA 0x810 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*07e0*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe40000000f00 */
/*07f0*/ MOV R0, 0x810 ; /* 0x0000081000007802 */
/* 0x000fe40000000f00 */
/*0800*/ CALL.REL.NOINC 0x850 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0810*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0820*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0830*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101908 */
/*0840*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0850*/ SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011603 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*0870*/ SHF.R.U32.HI R2, RZ, 0x17, R8.reuse ; /* 0x00000017ff027819 */
/* 0x100fe40000011608 */
/*0880*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0890*/ LOP3.LUT R9, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02097812 */
/* 0x000fe200078ec0ff */
/*08a0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*08b0*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R10, R9, -0x1, RZ ; /* 0xffffffff090a7810 */
/* 0x000fc40007ffe0ff */
/*08d0*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fc80003f04070 */
/*08e0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*08f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0900*/ @!P0 BRA 0xa80 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0910*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0920*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0940*/ @P0 BRA 0xe60 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, R2, 0xc8, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c802 */
/*0960*/ @!P0 BRA 0xe40 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0980*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0990*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*09a0*/ @!P1 BRA !P2, 0xe40 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*09b0*/ LOP3.LUT P2, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02ff7812 */
/* 0x000fc8000784c0ff */
/*09c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*09d0*/ @P1 BRA 0xe20 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*09f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a00*/ @P0 BRA 0xdf0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0a20*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f26270 */
/*0a30*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0a40*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0a50*/ @!P0 FFMA R2, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008028823 */
/* 0x000fe400000000ff */
/*0a60*/ @!P1 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003059823 */
/* 0x000fe200000000ff */
/*0a70*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ LEA R8, R4, 0xc0800000, 0x17 ; /* 0xc080000004087811 */
/* 0x000fe400078eb8ff */
/*0a90*/ IADD3 R3, R9, -0x7f, RZ ; /* 0xffffff8109037810 */
/* 0x000fc60007ffe0ff */
/*0aa0*/ IMAD.IADD R8, R5, 0x1, -R8 ; /* 0x0000000105087824 */
/* 0x000fe400078e0a08 */
/*0ab0*/ IMAD R2, R3.reuse, -0x800000, R2 ; /* 0xff80000003027824 */
/* 0x040fe200078e0202 */
/*0ac0*/ IADD3 R3, R3, 0x7f, -R4 ; /* 0x0000007f03037810 */
/* 0x000fe20007ffe804 */
/*0ad0*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e220000001000 */
/*0ae0*/ FADD.FTZ R7, -R8, -RZ ; /* 0x800000ff08077221 */
/* 0x000fe40000010100 */
/*0af0*/ IADD3 R3, R3, R6, RZ ; /* 0x0000000603037210 */
/* 0x000fe40007ffe0ff */
/*0b00*/ FFMA R10, R5, R7, 1 ; /* 0x3f800000050a7423 */
/* 0x001fc80000000007 */
/*0b10*/ FFMA R9, R5, R10, R5 ; /* 0x0000000a05097223 */
/* 0x000fc80000000005 */
/*0b20*/ FFMA R5, R2, R9, RZ ; /* 0x0000000902057223 */
/* 0x000fc800000000ff */
/*0b30*/ FFMA R10, R7, R5, R2 ; /* 0x00000005070a7223 */
/* 0x000fc80000000002 */
/*0b40*/ FFMA R10, R9, R10, R5 ; /* 0x0000000a090a7223 */
/* 0x000fc80000000005 */
/*0b50*/ FFMA R7, R7, R10, R2 ; /* 0x0000000a07077223 */
/* 0x000fc80000000002 */
/*0b60*/ FFMA R5, R9, R7, R10 ; /* 0x0000000709057223 */
/* 0x000fca000000000a */
/*0b70*/ SHF.R.U32.HI R2, RZ, 0x17, R5 ; /* 0x00000017ff027819 */
/* 0x000fc80000011605 */
/*0b80*/ LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02027812 */
/* 0x000fca00078ec0ff */
/*0b90*/ IMAD.IADD R6, R2, 0x1, R3 ; /* 0x0000000102067824 */
/* 0x000fca00078e0203 */
/*0ba0*/ IADD3 R2, R6, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x000fc80007ffe0ff */
/*0bb0*/ ISETP.GE.U32.AND P0, PT, R2, 0xfe, PT ; /* 0x000000fe0200780c */
/* 0x000fda0003f06070 */
/*0bc0*/ @!P0 BRA 0xdd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ ISETP.GT.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f04270 */
/*0be0*/ @P0 BRA 0xda0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*0c00*/ @P0 BRA 0xe70 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.GE.AND P0, PT, R6, -0x18, PT ; /* 0xffffffe80600780c */
/* 0x000fe40003f06270 */
/*0c20*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0c30*/ @!P0 BRA 0xe70 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0c40*/ FFMA.RZ R2, R9.reuse, R7.reuse, R10.reuse ; /* 0x0000000709027223 */
/* 0x1c0fe2000000c00a */
/*0c50*/ ISETP.NE.AND P2, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe20003f45270 */
/*0c60*/ FFMA.RM R3, R9.reuse, R7.reuse, R10.reuse ; /* 0x0000000709037223 */
/* 0x1c0fe2000000400a */
/*0c70*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0c80*/ LOP3.LUT R4, R2, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff02047812 */
/* 0x000fe200078ec0ff */
/*0c90*/ FFMA.RP R2, R9, R7, R10 ; /* 0x0000000709027223 */
/* 0x000fe2000000800a */
/*0ca0*/ IADD3 R7, R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a06 */
/*0cc0*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fe400078efcff */
/*0cd0*/ FSETP.NEU.FTZ.AND P0, PT, R2, R3, PT ; /* 0x000000030200720b */
/* 0x000fc40003f1d000 */
/*0ce0*/ SHF.L.U32 R7, R4, R7, RZ ; /* 0x0000000704077219 */
/* 0x000fe400000006ff */
/*0cf0*/ SEL R3, R6, RZ, P2 ; /* 0x000000ff06037207 */
/* 0x000fe40001000000 */
/*0d00*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0d10*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*0d20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0d30*/ SHF.R.U32.HI R7, RZ, 0x1, R3 ; /* 0x00000001ff077819 */
/* 0x000fc40000011603 */
/*0d40*/ SEL R2, RZ, 0x1, !P0 ; /* 0x00000001ff027807 */
/* 0x000fc80004000000 */
/*0d50*/ LOP3.LUT R2, R2, 0x1, R7, 0xf8, !PT ; /* 0x0000000102027812 */
/* 0x000fc800078ef807 */
/*0d60*/ LOP3.LUT R2, R2, R3, RZ, 0xc0, !PT ; /* 0x0000000302027212 */
/* 0x000fca00078ec0ff */
/*0d70*/ IMAD.IADD R2, R7, 0x1, R2 ; /* 0x0000000107027824 */
/* 0x000fca00078e0202 */
/*0d80*/ LOP3.LUT R5, R2, R5, RZ, 0xfc, !PT ; /* 0x0000000502057212 */
/* 0x000fe200078efcff */
/*0d90*/ BRA 0xe70 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0da0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0db0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0dc0*/ BRA 0xe70 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0dd0*/ IMAD R5, R3, 0x800000, R5 ; /* 0x0080000003057824 */
/* 0x000fe200078e0205 */
/*0de0*/ BRA 0xe70 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0df0*/ LOP3.LUT R5, R5, 0x80000000, R2, 0x48, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078e4802 */
/*0e00*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0e10*/ BRA 0xe70 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e20*/ LOP3.LUT R5, R5, 0x80000000, R2, 0x48, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078e4802 */
/*0e30*/ BRA 0xe70 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e40*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0e50*/ BRA 0xe70 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e60*/ FADD.FTZ R5, R8, R3 ; /* 0x0000000308057221 */
/* 0x000fe40000010000 */
/*0e70*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0e80*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0e90*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff16002007950 */
/* 0x000fea0003c3ffff */
/*0ea0*/ BRA 0xea0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11naiveKerneliPfS_
.globl _Z11naiveKerneliPfS_
.p2align 8
.type _Z11naiveKerneliPfS_,@function
_Z11naiveKerneliPfS_:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s5, s4
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_add_i32 s5, s5, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, s6, v0
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
.LBB0_4:
v_cvt_f32_i32_e32 v1, s4
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v2, null, v1, v1, v0
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v0, v1, v0
v_mul_f32_e32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v5, v4
v_fmac_f32_e32 v5, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v5, v4
v_div_fmas_f32 v2, v2, v3, v5
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v0, v2, v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11naiveKerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11naiveKerneliPfS_, .Lfunc_end0-_Z11naiveKerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11naiveKerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z11naiveKerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000a7ef6_00000000-6_naiveKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.type _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, @function
_Z34__device_stub__Z11naiveKerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11naiveKerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, .-_Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.globl _Z11naiveKerneliPfS_
.type _Z11naiveKerneliPfS_, @function
_Z11naiveKerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11naiveKerneliPfS_, .-_Z11naiveKerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11naiveKerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11naiveKerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "naiveKernel.hip"
.globl _Z26__device_stub__naiveKerneliPfS_ # -- Begin function _Z26__device_stub__naiveKerneliPfS_
.p2align 4, 0x90
.type _Z26__device_stub__naiveKerneliPfS_,@function
_Z26__device_stub__naiveKerneliPfS_: # @_Z26__device_stub__naiveKerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11naiveKerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__naiveKerneliPfS_, .Lfunc_end0-_Z26__device_stub__naiveKerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11naiveKerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11naiveKerneliPfS_,@object # @_Z11naiveKerneliPfS_
.section .rodata,"a",@progbits
.globl _Z11naiveKerneliPfS_
.p2align 3, 0x0
_Z11naiveKerneliPfS_:
.quad _Z26__device_stub__naiveKerneliPfS_
.size _Z11naiveKerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11naiveKerneliPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__naiveKerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11naiveKerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<iostream>
__global__ void add(int a,int b,int *c)
{
*c = a+b;
}
int main()
{
int c;
int *dev_c;
cudaMalloc((void **)&dev_c,sizeof(int));
add<<<1,1>>>(2,7,dev_c);
cudaMemcpy(&c,dev_c,sizeof(int),cudaMemcpyDeviceToHost);
std::cout<<c<<std::endl;
cudaFree(dev_c);
return 0;
}
|
code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<iostream>
__global__ void add(int a,int b,int *c)
{
*c = a+b;
}
int main()
{
int c;
int *dev_c;
cudaMalloc((void **)&dev_c,sizeof(int));
add<<<1,1>>>(2,7,dev_c);
cudaMemcpy(&c,dev_c,sizeof(int),cudaMemcpyDeviceToHost);
std::cout<<c<<std::endl;
cudaFree(dev_c);
return 0;
}
|
.file "tmpxft_0002fbf7_00000000-6_simple.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiiPi, .-_Z3addiiPi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<iostream>
__global__ void add(int a,int b,int *c)
{
*c = a+b;
}
int main()
{
int c;
int *dev_c;
cudaMalloc((void **)&dev_c,sizeof(int));
add<<<1,1>>>(2,7,dev_c);
cudaMemcpy(&c,dev_c,sizeof(int),cudaMemcpyDeviceToHost);
std::cout<<c<<std::endl;
cudaFree(dev_c);
return 0;
}
|
#include <hip/hip_runtime.h>
#include<iostream>
__global__ void add(int a,int b,int *c)
{
*c = a+b;
}
int main()
{
int c;
int *dev_c;
hipMalloc((void **)&dev_c,sizeof(int));
add<<<1,1>>>(2,7,dev_c);
hipMemcpy(&c,dev_c,sizeof(int),hipMemcpyDeviceToHost);
std::cout<<c<<std::endl;
hipFree(dev_c);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include<iostream>
__global__ void add(int a,int b,int *c)
{
*c = a+b;
}
int main()
{
int c;
int *dev_c;
hipMalloc((void **)&dev_c,sizeof(int));
add<<<1,1>>>(2,7,dev_c);
hipMemcpy(&c,dev_c,sizeof(int),hipMemcpyDeviceToHost);
std::cout<<c<<std::endl;
hipFree(dev_c);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include<iostream>
__global__ void add(int a,int b,int *c)
{
*c = a+b;
}
int main()
{
int c;
int *dev_c;
hipMalloc((void **)&dev_c,sizeof(int));
add<<<1,1>>>(2,7,dev_c);
hipMemcpy(&c,dev_c,sizeof(int),hipMemcpyDeviceToHost);
std::cout<<c<<std::endl;
hipFree(dev_c);
return 0;
}
|
.text
.file "simple.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0002fbf7_00000000-6_simple.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiiPi, .-_Z3addiiPi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "simple.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
/**
*
* Function my_gettimeofday()
* Used to compute time of execution
*
**/
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/**
*
* Function read_param()
* "l h
* n"
*
**/
int read_param(char *name, unsigned long **data, int *n, int *l, int *h){
FILE* fp = NULL;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
fscanf(fp, "%u %u", l, h);
fscanf(fp, "%u", n);
fclose(fp);
return 0;
}
/**
*
* Function read_data()
* "l h
* n
* x_0 y_0
* ...
* x_n y_n"
*
**/
int read_data(char *name, unsigned long **data, int n){
FILE* fp = NULL;
int i = 0, a = 0, b = 0;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
/* Ghost reading */
fscanf(fp, "%u %u", &a, &b);
fscanf(fp, "%u", &a);
for(i = 0; i < n; i++)
fscanf(fp, "%lu %lu", &data[0][i], &data[1][i]);
fclose(fp);
return 0;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
/**
*
* Function my_gettimeofday()
* Used to compute time of execution
*
**/
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/**
*
* Function read_param()
* "l h
* n"
*
**/
int read_param(char *name, unsigned long **data, int *n, int *l, int *h){
FILE* fp = NULL;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
fscanf(fp, "%u %u", l, h);
fscanf(fp, "%u", n);
fclose(fp);
return 0;
}
/**
*
* Function read_data()
* "l h
* n
* x_0 y_0
* ...
* x_n y_n"
*
**/
int read_data(char *name, unsigned long **data, int n){
FILE* fp = NULL;
int i = 0, a = 0, b = 0;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
/* Ghost reading */
fscanf(fp, "%u %u", &a, &b);
fscanf(fp, "%u", &a);
for(i = 0; i < n; i++)
fscanf(fp, "%lu %lu", &data[0][i], &data[1][i]);
fclose(fp);
return 0;
}
|
.file "tmpxft_00034955_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15my_gettimeofdayv
.type _Z15my_gettimeofdayv, @function
_Z15my_gettimeofdayv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
fildq 24(%rsp)
fldt .LC0(%rip)
fmulp %st, %st(1)
fildq 16(%rsp)
faddp %st, %st(1)
fstpl 8(%rsp)
movsd 8(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15my_gettimeofdayv, .-_Z15my_gettimeofdayv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "r"
.LC3:
.string "fopen :\t ERROR\n"
.LC4:
.string "%u %u"
.LC5:
.string "%u"
.text
.globl _Z10read_paramPcPPmPiS2_S2_
.type _Z10read_paramPcPPmPiS2_S2_, @function
_Z10read_paramPcPPmPiS2_S2_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdx, %rbp
movq %rcx, %r12
movq %r8, %r13
leaq .LC2(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L11
movq %rax, %rbx
movq %r13, %rcx
movq %r12, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbp, %rdx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdi
call fclose@PLT
movl $0, %eax
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z10read_paramPcPPmPiS2_S2_, .-_Z10read_paramPcPPmPiS2_S2_
.section .rodata.str1.1
.LC6:
.string "%lu %lu"
.text
.globl _Z9read_dataPcPPmi
.type _Z9read_dataPcPPmi, @function
_Z9read_dataPcPPmi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbp
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movl $0, 4(%rsp)
leaq .LC2(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %r13
leaq 4(%rsp), %rcx
movq %rsp, %rbx
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdx
leaq .LC5(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %r12d, %r12d
jle .L15
movslq %r12d, %r12
salq $3, %r12
movl $0, %ebx
leaq .LC6(%rip), %r14
.L16:
movq %rbx, %rcx
addq 8(%rbp), %rcx
movq %rbx, %rdx
addq 0(%rbp), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L16
.L15:
movq %r13, %rdi
call fclose@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L12
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9read_dataPcPPmi, .-_Z9read_dataPcPPmi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -1351849546
.long -2043167483
.long 16363
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
/**
*
* Function my_gettimeofday()
* Used to compute time of execution
*
**/
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/**
*
* Function read_param()
* "l h
* n"
*
**/
int read_param(char *name, unsigned long **data, int *n, int *l, int *h){
FILE* fp = NULL;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
fscanf(fp, "%u %u", l, h);
fscanf(fp, "%u", n);
fclose(fp);
return 0;
}
/**
*
* Function read_data()
* "l h
* n
* x_0 y_0
* ...
* x_n y_n"
*
**/
int read_data(char *name, unsigned long **data, int n){
FILE* fp = NULL;
int i = 0, a = 0, b = 0;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
/* Ghost reading */
fscanf(fp, "%u %u", &a, &b);
fscanf(fp, "%u", &a);
for(i = 0; i < n; i++)
fscanf(fp, "%lu %lu", &data[0][i], &data[1][i]);
fclose(fp);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
/**
*
* Function my_gettimeofday()
* Used to compute time of execution
*
**/
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/**
*
* Function read_param()
* "l h
* n"
*
**/
int read_param(char *name, unsigned long **data, int *n, int *l, int *h){
FILE* fp = NULL;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
fscanf(fp, "%u %u", l, h);
fscanf(fp, "%u", n);
fclose(fp);
return 0;
}
/**
*
* Function read_data()
* "l h
* n
* x_0 y_0
* ...
* x_n y_n"
*
**/
int read_data(char *name, unsigned long **data, int n){
FILE* fp = NULL;
int i = 0, a = 0, b = 0;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
/* Ghost reading */
fscanf(fp, "%u %u", &a, &b);
fscanf(fp, "%u", &a);
for(i = 0; i < n; i++)
fscanf(fp, "%lu %lu", &data[0][i], &data[1][i]);
fclose(fp);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
/**
*
* Function my_gettimeofday()
* Used to compute time of execution
*
**/
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/**
*
* Function read_param()
* "l h
* n"
*
**/
int read_param(char *name, unsigned long **data, int *n, int *l, int *h){
FILE* fp = NULL;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
fscanf(fp, "%u %u", l, h);
fscanf(fp, "%u", n);
fclose(fp);
return 0;
}
/**
*
* Function read_data()
* "l h
* n
* x_0 y_0
* ...
* x_n y_n"
*
**/
int read_data(char *name, unsigned long **data, int n){
FILE* fp = NULL;
int i = 0, a = 0, b = 0;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
/* Ghost reading */
fscanf(fp, "%u %u", &a, &b);
fscanf(fp, "%u", &a);
for(i = 0; i < n; i++)
fscanf(fp, "%lu %lu", &data[0][i], &data[1][i]);
fclose(fp);
return 0;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
/**
*
* Function my_gettimeofday()
* Used to compute time of execution
*
**/
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/**
*
* Function read_param()
* "l h
* n"
*
**/
int read_param(char *name, unsigned long **data, int *n, int *l, int *h){
FILE* fp = NULL;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
fscanf(fp, "%u %u", l, h);
fscanf(fp, "%u", n);
fclose(fp);
return 0;
}
/**
*
* Function read_data()
* "l h
* n
* x_0 y_0
* ...
* x_n y_n"
*
**/
int read_data(char *name, unsigned long **data, int n){
FILE* fp = NULL;
int i = 0, a = 0, b = 0;
fp = fopen(name, "r");
if(fp == NULL){
printf("fopen :\t ERROR\n");
return -1;
}
/* Ghost reading */
fscanf(fp, "%u %u", &a, &b);
fscanf(fp, "%u", &a);
for(i = 0; i < n; i++)
fscanf(fp, "%lu %lu", &data[0][i], &data[1][i]);
fclose(fp);
return 0;
}
|
.text
.file "utils.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15my_gettimeofdayv
.LCPI0_0:
.quad 0x8637bd05af6c69b6 # x86_fp80 1.00000000000000000004E-6
.short 0x3feb
.zero 6
.text
.globl _Z15my_gettimeofdayv
.p2align 4, 0x90
.type _Z15my_gettimeofdayv,@function
_Z15my_gettimeofdayv: # @_Z15my_gettimeofdayv
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 8(%rsp)
fildll 8(%rsp)
movq %rcx, 16(%rsp)
fildll 16(%rsp)
fldt .LCPI0_0(%rip)
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl (%rsp)
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15my_gettimeofdayv, .Lfunc_end0-_Z15my_gettimeofdayv
.cfi_endproc
# -- End function
.globl _Z10read_paramPcPPmPiS2_S2_ # -- Begin function _Z10read_paramPcPPmPiS2_S2_
.p2align 4, 0x90
.type _Z10read_paramPcPPmPiS2_S2_,@function
_Z10read_paramPcPPmPiS2_S2_: # @_Z10read_paramPcPPmPiS2_S2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r15
movq %rcx, %r12
movq %rdx, %rbx
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_1
# %bb.2:
movq %rax, %r14
xorl %ebp, %ebp
movl $.L.str.2, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r14, %rdi
callq fclose
jmp .LBB1_3
.LBB1_1:
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %ebp
.LBB1_3:
movl %ebp, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10read_paramPcPPmPiS2_S2_, .Lfunc_end1-_Z10read_paramPcPPmPiS2_S2_
.cfi_endproc
# -- End function
.globl _Z9read_dataPcPPmi # -- Begin function _Z9read_dataPcPPmi
.p2align 4, 0x90
.type _Z9read_dataPcPPmi,@function
_Z9read_dataPcPPmi: # @_Z9read_dataPcPPmi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %rbx
movl $0, 12(%rsp)
movl $0, 8(%rsp)
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.2:
movq %rax, %r14
xorl %ebp, %ebp
leaq 12(%rsp), %r12
leaq 8(%rsp), %rcx
movl $.L.str.2, %esi
movq %rax, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %r15d, %r15d
jle .LBB2_5
# %bb.3: # %.lr.ph
movl %r15d, %r15d
shlq $3, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rdx
addq %r12, %rdx
movq 8(%rbx), %rcx
addq %r12, %rcx
movl $.L.str.4, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
cmpq %r12, %r15
jne .LBB2_4
.LBB2_5: # %._crit_edge
movq %r14, %rdi
callq fclose
jmp .LBB2_6
.LBB2_1:
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %ebp
.LBB2_6:
movl %ebp, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9read_dataPcPPmi, .Lfunc_end2-_Z9read_dataPcPPmi
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%u %u"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%u"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%lu %lu"
.size .L.str.4, 8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "fopen :\t ERROR"
.size .Lstr.1, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00034955_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15my_gettimeofdayv
.type _Z15my_gettimeofdayv, @function
_Z15my_gettimeofdayv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
fildq 24(%rsp)
fldt .LC0(%rip)
fmulp %st, %st(1)
fildq 16(%rsp)
faddp %st, %st(1)
fstpl 8(%rsp)
movsd 8(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15my_gettimeofdayv, .-_Z15my_gettimeofdayv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "r"
.LC3:
.string "fopen :\t ERROR\n"
.LC4:
.string "%u %u"
.LC5:
.string "%u"
.text
.globl _Z10read_paramPcPPmPiS2_S2_
.type _Z10read_paramPcPPmPiS2_S2_, @function
_Z10read_paramPcPPmPiS2_S2_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdx, %rbp
movq %rcx, %r12
movq %r8, %r13
leaq .LC2(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L11
movq %rax, %rbx
movq %r13, %rcx
movq %r12, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbp, %rdx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdi
call fclose@PLT
movl $0, %eax
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z10read_paramPcPPmPiS2_S2_, .-_Z10read_paramPcPPmPiS2_S2_
.section .rodata.str1.1
.LC6:
.string "%lu %lu"
.text
.globl _Z9read_dataPcPPmi
.type _Z9read_dataPcPPmi, @function
_Z9read_dataPcPPmi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbp
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movl $0, 4(%rsp)
leaq .LC2(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %r13
leaq 4(%rsp), %rcx
movq %rsp, %rbx
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdx
leaq .LC5(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %r12d, %r12d
jle .L15
movslq %r12d, %r12
salq $3, %r12
movl $0, %ebx
leaq .LC6(%rip), %r14
.L16:
movq %rbx, %rcx
addq 8(%rbp), %rcx
movq %rbx, %rdx
addq 0(%rbp), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L16
.L15:
movq %r13, %rdi
call fclose@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L12
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9read_dataPcPPmi, .-_Z9read_dataPcPPmi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -1351849546
.long -2043167483
.long 16363
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "utils.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15my_gettimeofdayv
.LCPI0_0:
.quad 0x8637bd05af6c69b6 # x86_fp80 1.00000000000000000004E-6
.short 0x3feb
.zero 6
.text
.globl _Z15my_gettimeofdayv
.p2align 4, 0x90
.type _Z15my_gettimeofdayv,@function
_Z15my_gettimeofdayv: # @_Z15my_gettimeofdayv
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 8(%rsp)
fildll 8(%rsp)
movq %rcx, 16(%rsp)
fildll 16(%rsp)
fldt .LCPI0_0(%rip)
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl (%rsp)
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15my_gettimeofdayv, .Lfunc_end0-_Z15my_gettimeofdayv
.cfi_endproc
# -- End function
.globl _Z10read_paramPcPPmPiS2_S2_ # -- Begin function _Z10read_paramPcPPmPiS2_S2_
.p2align 4, 0x90
.type _Z10read_paramPcPPmPiS2_S2_,@function
_Z10read_paramPcPPmPiS2_S2_: # @_Z10read_paramPcPPmPiS2_S2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r15
movq %rcx, %r12
movq %rdx, %rbx
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_1
# %bb.2:
movq %rax, %r14
xorl %ebp, %ebp
movl $.L.str.2, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r14, %rdi
callq fclose
jmp .LBB1_3
.LBB1_1:
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %ebp
.LBB1_3:
movl %ebp, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10read_paramPcPPmPiS2_S2_, .Lfunc_end1-_Z10read_paramPcPPmPiS2_S2_
.cfi_endproc
# -- End function
.globl _Z9read_dataPcPPmi # -- Begin function _Z9read_dataPcPPmi
.p2align 4, 0x90
.type _Z9read_dataPcPPmi,@function
_Z9read_dataPcPPmi: # @_Z9read_dataPcPPmi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %rbx
movl $0, 12(%rsp)
movl $0, 8(%rsp)
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.2:
movq %rax, %r14
xorl %ebp, %ebp
leaq 12(%rsp), %r12
leaq 8(%rsp), %rcx
movl $.L.str.2, %esi
movq %rax, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %r15d, %r15d
jle .LBB2_5
# %bb.3: # %.lr.ph
movl %r15d, %r15d
shlq $3, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rdx
addq %r12, %rdx
movq 8(%rbx), %rcx
addq %r12, %rcx
movl $.L.str.4, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
cmpq %r12, %r15
jne .LBB2_4
.LBB2_5: # %._crit_edge
movq %r14, %rdi
callq fclose
jmp .LBB2_6
.LBB2_1:
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %ebp
.LBB2_6:
movl %ebp, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9read_dataPcPPmi, .Lfunc_end2-_Z9read_dataPcPPmi
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%u %u"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%u"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%lu %lu"
.size .L.str.4, 8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "fopen :\t ERROR"
.size .Lstr.1, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <math.h>
#define N 512
#define MAX_ERR 1
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x + (blockIdx.x * blockDim.x);
//printf("index: %d\n", index);
for(int i = index; i < n; i+=blockDim.x){
printf("i=%d \n", i);
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Initialize array
for(int i = 0; i < N; i++){
a[i] = 1.0f; b[i] = 2.0f;
}
// Allocate device memory for a
cudaMalloc((void**)&d_a, sizeof(float) * N);
cudaMalloc((void**)&d_b, sizeof(float) * N);
cudaMalloc((void**)&d_out, sizeof(float) * N);
// Transfer data from host t o device memory
cudaMemcpy(d_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeof(float) * N, cudaMemcpyHostToDevice);
// Main function
vector_add<<</*1*/(N+256)/256,256>>>(d_out, d_a, d_b, N);
// Transfer data from device to host memory
cudaMemcpy(out, d_out, sizeof(float) * N, cudaMemcpyDeviceToHost);
// Print results
for(int i=0; i < N; i++){
//if(fabs(out[i] - a[i] - b[i]) < MAX_ERR )
//printf("failed");
printf("%i.- %f = %f + %f \n", i, out[i], a[i], b[i]);
}
// Cleanup after kernel execution
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
free(a);
free(b);
free(out);
}
|
code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R16, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001107a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD R18, R18, c[0x0][0x0], R3 ; /* 0x0000000012127a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.X R17, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff117624 */
/* 0x000fe400008e06ff */
/*0090*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00a0*/ STL [R1], R18 ; /* 0x0000001201007387 */
/* 0x0011e20000100800 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00d0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0011 */
/*0100*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0110*/ MOV R11, 0x180 ; /* 0x00000180000b7802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0160*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0170*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0190*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01a0*/ IMAD.WIDE R2, R18, R7, c[0x0][0x168] ; /* 0x00005a0012027625 */
/* 0x000fc800078e0207 */
/*01b0*/ IMAD.WIDE R4, R18.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0012047625 */
/* 0x0c0fe400078e0207 */
/*01c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.WIDE R6, R18.reuse, R7, c[0x0][0x160] ; /* 0x0000580012067625 */
/* 0x040fe200078e0207 */
/*01f0*/ IADD3 R18, R18, c[0x0][0x0], RZ ; /* 0x0000000012127a10 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fe20003f06270 */
/*0210*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0220*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0230*/ @!P0 BRA 0x90 ; /* 0xfffffe5000008947 */
/* 0x000fea000383ffff */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <math.h>
#define N 512
#define MAX_ERR 1
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x + (blockIdx.x * blockDim.x);
//printf("index: %d\n", index);
for(int i = index; i < n; i+=blockDim.x){
printf("i=%d \n", i);
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Initialize array
for(int i = 0; i < N; i++){
a[i] = 1.0f; b[i] = 2.0f;
}
// Allocate device memory for a
cudaMalloc((void**)&d_a, sizeof(float) * N);
cudaMalloc((void**)&d_b, sizeof(float) * N);
cudaMalloc((void**)&d_out, sizeof(float) * N);
// Transfer data from host t o device memory
cudaMemcpy(d_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeof(float) * N, cudaMemcpyHostToDevice);
// Main function
vector_add<<</*1*/(N+256)/256,256>>>(d_out, d_a, d_b, N);
// Transfer data from device to host memory
cudaMemcpy(out, d_out, sizeof(float) * N, cudaMemcpyDeviceToHost);
// Print results
for(int i=0; i < N; i++){
//if(fabs(out[i] - a[i] - b[i]) < MAX_ERR )
//printf("failed");
printf("%i.- %f = %f + %f \n", i, out[i], a[i], b[i]);
}
// Cleanup after kernel execution
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
free(a);
free(b);
free(out);
}
|
.file "tmpxft_001af61c_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%i.- %f = %f + %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $2048, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $3, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r14
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 0(%rbp,%rbx,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $512, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <math.h>
#define N 512
#define MAX_ERR 1
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x + (blockIdx.x * blockDim.x);
//printf("index: %d\n", index);
for(int i = index; i < n; i+=blockDim.x){
printf("i=%d \n", i);
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Initialize array
for(int i = 0; i < N; i++){
a[i] = 1.0f; b[i] = 2.0f;
}
// Allocate device memory for a
cudaMalloc((void**)&d_a, sizeof(float) * N);
cudaMalloc((void**)&d_b, sizeof(float) * N);
cudaMalloc((void**)&d_out, sizeof(float) * N);
// Transfer data from host t o device memory
cudaMemcpy(d_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeof(float) * N, cudaMemcpyHostToDevice);
// Main function
vector_add<<</*1*/(N+256)/256,256>>>(d_out, d_a, d_b, N);
// Transfer data from device to host memory
cudaMemcpy(out, d_out, sizeof(float) * N, cudaMemcpyDeviceToHost);
// Print results
for(int i=0; i < N; i++){
//if(fabs(out[i] - a[i] - b[i]) < MAX_ERR )
//printf("failed");
printf("%i.- %f = %f + %f \n", i, out[i], a[i], b[i]);
}
// Cleanup after kernel execution
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
free(a);
free(b);
free(out);
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define N 512
#define MAX_ERR 1
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x + (blockIdx.x * blockDim.x);
//printf("index: %d\n", index);
for(int i = index; i < n; i+=blockDim.x){
printf("i=%d \n", i);
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Initialize array
for(int i = 0; i < N; i++){
a[i] = 1.0f; b[i] = 2.0f;
}
// Allocate device memory for a
hipMalloc((void**)&d_a, sizeof(float) * N);
hipMalloc((void**)&d_b, sizeof(float) * N);
hipMalloc((void**)&d_out, sizeof(float) * N);
// Transfer data from host t o device memory
hipMemcpy(d_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeof(float) * N, hipMemcpyHostToDevice);
// Main function
vector_add<<</*1*/(N+256)/256,256>>>(d_out, d_a, d_b, N);
// Transfer data from device to host memory
hipMemcpy(out, d_out, sizeof(float) * N, hipMemcpyDeviceToHost);
// Print results
for(int i=0; i < N; i++){
//if(fabs(out[i] - a[i] - b[i]) < MAX_ERR )
//printf("failed");
printf("%i.- %f = %f + %f \n", i, out[i], a[i], b[i]);
}
// Cleanup after kernel execution
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
free(a);
free(b);
free(out);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define N 512
#define MAX_ERR 1
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x + (blockIdx.x * blockDim.x);
//printf("index: %d\n", index);
for(int i = index; i < n; i+=blockDim.x){
printf("i=%d \n", i);
out[i] = a[i] + b[i];
}
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Initialize array
for(int i = 0; i < N; i++){
a[i] = 1.0f; b[i] = 2.0f;
}
// Allocate device memory for a
hipMalloc((void**)&d_a, sizeof(float) * N);
hipMalloc((void**)&d_b, sizeof(float) * N);
hipMalloc((void**)&d_out, sizeof(float) * N);
// Transfer data from host t o device memory
hipMemcpy(d_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeof(float) * N, hipMemcpyHostToDevice);
// Main function
vector_add<<</*1*/(N+256)/256,256>>>(d_out, d_a, d_b, N);
// Transfer data from device to host memory
hipMemcpy(out, d_out, sizeof(float) * N, hipMemcpyDeviceToHost);
// Print results
for(int i=0; i < N; i++){
//if(fabs(out[i] - a[i] - b[i]) < MAX_ERR )
//printf("failed");
printf("%i.- %f = %f + %f \n", i, out[i], a[i], b[i]);
}
// Cleanup after kernel execution
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
free(a);
free(b);
free(out);
}
|
.text
.file "vector_add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 24(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 253(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $512, 36(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rbx,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r14,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str, %edi
movl %r12d, %esi
movb $3, %al
callq printf
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i.- %f = %f + %f \n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001af61c_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%i.- %f = %f + %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $2048, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $3, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r14
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 0(%rbp,%rbx,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $512, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "vector_add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 24(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 253(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $512, 36(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rbx,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r14,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str, %edi
movl %r12d, %esi
movb $3, %al
callq printf
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i.- %f = %f + %f \n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
* Copyright (c) 2020 Yaroslav Pogrebnyak <[email protected]>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern "C" {
__global__ void Overlay_Cuda(
int x_position, int y_position,
unsigned char* main, int main_linesize,
unsigned char* overlay, int overlay_linesize,
int overlay_w, int overlay_h,
unsigned char* overlay_alpha, int alpha_linesize,
int alpha_adj_x, int alpha_adj_y)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= overlay_w + x_position ||
y >= overlay_h + y_position ||
x < x_position ||
y < y_position ) {
return;
}
int overlay_x = x - x_position;
int overlay_y = y - y_position;
float alpha = 1.0;
if (alpha_linesize) {
alpha = overlay_alpha[alpha_adj_x * overlay_x + alpha_adj_y * overlay_y * alpha_linesize] / 255.0f;
}
main[x + y*main_linesize] = alpha * overlay[overlay_x + overlay_y * overlay_linesize] + (1.0f - alpha) * main[x + y*main_linesize];
}
}
|
code for sm_80
Function : Overlay_Cuda
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR6, c[0x0][0x188] ; /* 0x0000620000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0050*/ UIADD3 UR5, UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc6000fffe03f */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0070*/ ULDC UR6, c[0x0][0x184] ; /* 0x0000610000067ab9 */
/* 0x000fe40000000800 */
/*0080*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000fffe03f */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R2, R2, c[0x0][0x4], R3 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R2, UR5, PT ; /* 0x0000000502007c0c */
/* 0x000fe2000bf06270 */
/*00c0*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0200 */
/*00d0*/ ISETP.GE.OR P0, PT, R5, UR4, P0 ; /* 0x0000000405007c0c */
/* 0x000fc80008706670 */
/*00e0*/ ISETP.LT.OR P0, PT, R5, c[0x0][0x160], P0 ; /* 0x0000580005007a0c */
/* 0x000fc80000701670 */
/*00f0*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x164], P0 ; /* 0x0000590002007a0c */
/* 0x000fda0000701670 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x198], PT ; /* 0x00006600ff007a0c */
/* 0x000fe20003f05270 */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IADD3 R0, R5, -c[0x0][0x160], RZ ; /* 0x8000580005007a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff067424 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R3, R2, -c[0x0][0x164], RZ ; /* 0x8000590002037a10 */
/* 0x000fd20007ffe0ff */
/*0160*/ @!P0 BRA 0x2d0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD R4, R0, c[0x0][0x19c], RZ ; /* 0x0000670000047a24 */
/* 0x000fe400078e02ff */
/*0180*/ IMAD R7, R3, c[0x0][0x198], RZ ; /* 0x0000660003077a24 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD R4, R7, c[0x0][0x1a0], R4 ; /* 0x0000680007047a24 */
/* 0x000fca00078e0204 */
/*01a0*/ IADD3 R6, P0, R4, c[0x0][0x190], RZ ; /* 0x0000640004067a10 */
/* 0x000fc80007f1e0ff */
/*01b0*/ LEA.HI.X.SX32 R7, R4, c[0x0][0x194], 0x1, P0 ; /* 0x0000650004077a11 */
/* 0x000fca00000f0eff */
/*01c0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1100 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff047424 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B1, 0x2c0 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3b808081 ; /* 0x3b808081ff097424 */
/* 0x000fc800078e00ff */
/*0200*/ FFMA R4, R9, -255, R4 ; /* 0xc37f000009047823 */
/* 0x000fc80000000004 */
/*0210*/ FFMA R9, R4, R9, 0.0039215688593685626984 ; /* 0x3b80808104097423 */
/* 0x000fe20000000009 */
/*0220*/ I2F.U16 R8, R6 ; /* 0x0000000600087306 */
/* 0x004e300000101000 */
/*0230*/ FCHK P0, R8, 255 ; /* 0x437f000008007902 */
/* 0x001e220000000000 */
/*0240*/ FFMA R4, R8, R9, RZ ; /* 0x0000000908047223 */
/* 0x000fc800000000ff */
/*0250*/ FFMA R10, R4, -255, R8 ; /* 0xc37f0000040a7823 */
/* 0x000fc80000000008 */
/*0260*/ FFMA R4, R9, R10, R4 ; /* 0x0000000a09047223 */
/* 0x000fe20000000004 */
/*0270*/ @!P0 BRA 0x2b0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0280*/ MOV R4, 0x2a0 ; /* 0x000002a000047802 */
/* 0x000fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*02b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*02d0*/ IMAD R5, R2, c[0x0][0x170], R5 ; /* 0x00005c0002057a24 */
/* 0x000fe400078e0205 */
/*02e0*/ IMAD R0, R3, c[0x0][0x180], R0 ; /* 0x0000600003007a24 */
/* 0x000fc600078e0200 */
/*02f0*/ IADD3 R2, P1, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005027a10 */
/* 0x040fe40007f3e0ff */
/*0300*/ IADD3 R4, P0, R0.reuse, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x040fe40007f1e0ff */
/*0310*/ LEA.HI.X.SX32 R3, R5, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0005037a11 */
/* 0x000fe400008f0eff */
/*0320*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x17c], 0x1, P0 ; /* 0x00005f0000057a11 */
/* 0x000fc600000f0eff */
/*0330*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea8000c1e1100 */
/*0340*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ee2000c1e1100 */
/*0350*/ FADD R9, -R6, 1 ; /* 0x3f80000006097421 */
/* 0x000fe20000000100 */
/*0360*/ I2F.U16 R0, R0 ; /* 0x0000000000007306 */
/* 0x004e300000101000 */
/*0370*/ I2F.U16 R7, R4 ; /* 0x0000000400077306 */
/* 0x008e620000101000 */
/*0380*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x001fc80000400000 */
/*0390*/ FFMA R7, R7, R6, R9 ; /* 0x0000000607077223 */
/* 0x002fcc0000000009 */
/*03a0*/ F2I.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f000 */
/*03b0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101106 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ SHF.R.U32.HI R6, RZ, 0x17, R8.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011608 */
/*03e0*/ BSSY B0, 0x9b0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*03f0*/ BSSY B2, 0x5a0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0400*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0410*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0420*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc80007ffe0ff */
/*0430*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, !PT ; /* 0x000000fd0b00780c */
/* 0x000fda0007f04470 */
/*0440*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x590 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fda0003f1c200 */
/*0470*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0480*/ @P0 BRA 0x990 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0490*/ IMAD.MOV.U32 R10, RZ, RZ, 0x437f0000 ; /* 0x437f0000ff0a7424 */
/* 0x000fca00078e00ff */
/*04a0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c807 */
/*04b0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*04c0*/ @!P0 BRA 0x970 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*04d0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*04e0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x950 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1d200 */
/*0510*/ LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000782c0ff */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0530*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0540*/ @P0 BRA 0x920 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f06270 */
/*0560*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0570*/ @!P0 FFMA R7, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008078823 */
/* 0x000fe400000000ff */
/*0580*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0590*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05a0*/ UMOV UR4, 0x437f0000 ; /* 0x437f000000047882 */
/* 0x000fe20000000000 */
/*05b0*/ IADD3 R8, R6, -0x7f, RZ ; /* 0xffffff8106087810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ UIADD3 UR4, UR4, -0x3800000, URZ ; /* 0xfc80000004047890 */
/* 0x000fe2000fffe03f */
/*05d0*/ BSSY B2, 0x910 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*05e0*/ IADD3 R9, R9, -0x7, R8 ; /* 0xfffffff909097810 */
/* 0x000fe20007ffe008 */
/*05f0*/ IMAD R7, R8, -0x800000, R7 ; /* 0xff80000008077824 */
/* 0x000fc400078e0207 */
/*0600*/ FADD.FTZ R12, -RZ, -UR4 ; /* 0x80000004ff0c7e21 */
/* 0x000fc60008010100 */
/*0610*/ MUFU.RCP R10, UR4 ; /* 0x00000004000a7d08 */
/* 0x000e240008001000 */
/*0620*/ FFMA R11, R10, R12, 1 ; /* 0x3f8000000a0b7423 */
/* 0x001fc8000000000c */
/*0630*/ FFMA R10, R10, R11, R10 ; /* 0x0000000b0a0a7223 */
/* 0x000fc8000000000a */
/*0640*/ FFMA R11, R7, R10, RZ ; /* 0x0000000a070b7223 */
/* 0x000fc800000000ff */
/*0650*/ FFMA R6, R12, R11, R7 ; /* 0x0000000b0c067223 */
/* 0x000fc80000000007 */
/*0660*/ FFMA R11, R10, R6, R11 ; /* 0x000000060a0b7223 */
/* 0x000fc8000000000b */
/*0670*/ FFMA R12, R12, R11, R7 ; /* 0x0000000b0c0c7223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R6, R10, R12, R11 ; /* 0x0000000c0a067223 */
/* 0x000fca000000000b */
/*0690*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*06a0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*06b0*/ IMAD.IADD R13, R7, 0x1, R9 ; /* 0x00000001070d7824 */
/* 0x000fca00078e0209 */
/*06c0*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*06e0*/ @!P0 BRA 0x8f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0700*/ @P0 BRA 0x8c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0720*/ @P0 BRA 0x900 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0740*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0750*/ @!P0 BRA 0x900 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0760*/ FFMA.RZ R7, R10.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0a077223 */
/* 0x1c0fe2000000c00b */
/*0770*/ IADD3 R9, R13.reuse, 0x20, RZ ; /* 0x000000200d097810 */
/* 0x040fe40007ffe0ff */
/*0780*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0790*/ LOP3.LUT R8, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07087812 */
/* 0x000fe200078ec0ff */
/*07a0*/ FFMA.RP R7, R10.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0a077223 */
/* 0x1c0fe2000000800b */
/*07b0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*07c0*/ FFMA.RM R10, R10, R12, R11 ; /* 0x0000000c0a0a7223 */
/* 0x000fe2000000400b */
/*07d0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV R11, RZ, RZ, -R13 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0a0d */
/*07f0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0800*/ FSETP.NEU.FTZ.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720b */
/* 0x000fe40003f1d000 */
/*0810*/ SEL R7, R11, RZ, P2 ; /* 0x000000ff0b077207 */
/* 0x000fe40001000000 */
/*0820*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0830*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0840*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0850*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*0860*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fc80004000000 */
/*0870*/ LOP3.LUT R8, R8, 0x1, R9, 0xf8, !PT ; /* 0x0000000108087812 */
/* 0x000fc800078ef809 */
/*0880*/ LOP3.LUT R8, R8, R7, RZ, 0xc0, !PT ; /* 0x0000000708087212 */
/* 0x000fca00078ec0ff */
/*0890*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fca00078e0208 */
/*08a0*/ LOP3.LUT R6, R9, R6, RZ, 0xfc, !PT ; /* 0x0000000609067212 */
/* 0x000fe200078efcff */
/*08b0*/ BRA 0x900 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*08d0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x900 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe400078e0206 */
/*0900*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0910*/ BRA 0x9a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R6, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a067812 */
/* 0x000fc800078e4807 */
/*0930*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0940*/ BRA 0x9a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R6, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a067812 */
/* 0x000fe200078e4807 */
/*0960*/ BRA 0x9a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0970*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0980*/ BRA 0x9a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0990*/ FADD.FTZ R6, R8, 255 ; /* 0x437f000008067421 */
/* 0x000fe40000010000 */
/*09a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09b0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*09c0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*09d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff61006007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
* Copyright (c) 2020 Yaroslav Pogrebnyak <[email protected]>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern "C" {
__global__ void Overlay_Cuda(
int x_position, int y_position,
unsigned char* main, int main_linesize,
unsigned char* overlay, int overlay_linesize,
int overlay_w, int overlay_h,
unsigned char* overlay_alpha, int alpha_linesize,
int alpha_adj_x, int alpha_adj_y)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= overlay_w + x_position ||
y >= overlay_h + y_position ||
x < x_position ||
y < y_position ) {
return;
}
int overlay_x = x - x_position;
int overlay_y = y - y_position;
float alpha = 1.0;
if (alpha_linesize) {
alpha = overlay_alpha[alpha_adj_x * overlay_x + alpha_adj_y * overlay_y * alpha_linesize] / 255.0f;
}
main[x + y*main_linesize] = alpha * overlay[overlay_x + overlay_y * overlay_linesize] + (1.0f - alpha) * main[x + y*main_linesize];
}
}
|
.file "tmpxft_00050c36_00000000-6_vf_overlay_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z12Overlay_CudaiiPhiS_iiiS_iiiiiPhiS_iiiS_iii
.type _Z45__device_stub__Z12Overlay_CudaiiPhiS_iiiS_iiiiiPhiS_iiiS_iii, @function
_Z45__device_stub__Z12Overlay_CudaiiPhiS_iiiS_iiiiiPhiS_iiiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq Overlay_Cuda(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z12Overlay_CudaiiPhiS_iiiS_iiiiiPhiS_iiiS_iii, .-_Z45__device_stub__Z12Overlay_CudaiiPhiS_iiiS_iiiiiPhiS_iiiS_iii
.globl Overlay_Cuda
.type Overlay_Cuda, @function
Overlay_Cuda:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z12Overlay_CudaiiPhiS_iiiS_iiiiiPhiS_iiiS_iii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size Overlay_Cuda, .-Overlay_Cuda
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Overlay_Cuda"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq Overlay_Cuda(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* Copyright (c) 2020 Yaroslav Pogrebnyak <[email protected]>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern "C" {
__global__ void Overlay_Cuda(
int x_position, int y_position,
unsigned char* main, int main_linesize,
unsigned char* overlay, int overlay_linesize,
int overlay_w, int overlay_h,
unsigned char* overlay_alpha, int alpha_linesize,
int alpha_adj_x, int alpha_adj_y)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= overlay_w + x_position ||
y >= overlay_h + y_position ||
x < x_position ||
y < y_position ) {
return;
}
int overlay_x = x - x_position;
int overlay_y = y - y_position;
float alpha = 1.0;
if (alpha_linesize) {
alpha = overlay_alpha[alpha_adj_x * overlay_x + alpha_adj_y * overlay_y * alpha_linesize] / 255.0f;
}
main[x + y*main_linesize] = alpha * overlay[overlay_x + overlay_y * overlay_linesize] + (1.0f - alpha) * main[x + y*main_linesize];
}
}
|
#include <hip/hip_runtime.h>
/*
* Copyright (c) 2020 Yaroslav Pogrebnyak <[email protected]>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern "C" {
__global__ void Overlay_Cuda(
int x_position, int y_position,
unsigned char* main, int main_linesize,
unsigned char* overlay, int overlay_linesize,
int overlay_w, int overlay_h,
unsigned char* overlay_alpha, int alpha_linesize,
int alpha_adj_x, int alpha_adj_y)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= overlay_w + x_position ||
y >= overlay_h + y_position ||
x < x_position ||
y < y_position ) {
return;
}
int overlay_x = x - x_position;
int overlay_y = y - y_position;
float alpha = 1.0;
if (alpha_linesize) {
alpha = overlay_alpha[alpha_adj_x * overlay_x + alpha_adj_y * overlay_y * alpha_linesize] / 255.0f;
}
main[x + y*main_linesize] = alpha * overlay[overlay_x + overlay_y * overlay_linesize] + (1.0f - alpha) * main[x + y*main_linesize];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
/*
* Copyright (c) 2020 Yaroslav Pogrebnyak <[email protected]>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern "C" {
__global__ void Overlay_Cuda(
int x_position, int y_position,
unsigned char* main, int main_linesize,
unsigned char* overlay, int overlay_linesize,
int overlay_w, int overlay_h,
unsigned char* overlay_alpha, int alpha_linesize,
int alpha_adj_x, int alpha_adj_y)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= overlay_w + x_position ||
y >= overlay_h + y_position ||
x < x_position ||
y < y_position ) {
return;
}
int overlay_x = x - x_position;
int overlay_y = y - y_position;
float alpha = 1.0;
if (alpha_linesize) {
alpha = overlay_alpha[alpha_adj_x * overlay_x + alpha_adj_y * overlay_y * alpha_linesize] / 255.0f;
}
main[x + y*main_linesize] = alpha * overlay[overlay_x + overlay_y * overlay_linesize] + (1.0f - alpha) * main[x + y*main_linesize];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Overlay_Cuda
.globl Overlay_Cuda
.p2align 8
.type Overlay_Cuda,@function
Overlay_Cuda:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x54
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_add_i32 s2, s2, s6
s_add_i32 s3, s3, s7
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_le_i32_e64 s3, s6, v0
v_cmp_le_i32_e64 s4, s7, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x38
v_subrev_nc_u32_e32 v2, s6, v0
v_subrev_nc_u32_e32 v3, s7, v1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x3c
s_load_b64 s[6:7], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v2, s4
s_mul_i32 s2, s5, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s2, v3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
global_load_u8 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, 0x437f0000, 0x437f0000, v4
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v4, 0x437f0000, v4
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v4, v5, 0x437f0000, v4
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v4, 1.0
.LBB0_4:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, v1, s4, v[0:1]
v_mad_u64_u32 v[0:1], null, v3, s5, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v5
v_add_co_u32 v1, vcc_lo, s2, v5
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v3, vcc_lo
global_load_u8 v0, v[1:2], off
global_load_u8 v3, v[5:6], off
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v0, v0
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_sub_f32_e32 v5, 1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v5, v0
v_fmac_f32_e32 v0, v4, v3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
global_store_b8 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Overlay_Cuda
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Overlay_Cuda, .Lfunc_end0-Overlay_Cuda
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Overlay_Cuda
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: Overlay_Cuda.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
/*
* Copyright (c) 2020 Yaroslav Pogrebnyak <[email protected]>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern "C" {
__global__ void Overlay_Cuda(
int x_position, int y_position,
unsigned char* main, int main_linesize,
unsigned char* overlay, int overlay_linesize,
int overlay_w, int overlay_h,
unsigned char* overlay_alpha, int alpha_linesize,
int alpha_adj_x, int alpha_adj_y)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= overlay_w + x_position ||
y >= overlay_h + y_position ||
x < x_position ||
y < y_position ) {
return;
}
int overlay_x = x - x_position;
int overlay_y = y - y_position;
float alpha = 1.0;
if (alpha_linesize) {
alpha = overlay_alpha[alpha_adj_x * overlay_x + alpha_adj_y * overlay_y * alpha_linesize] / 255.0f;
}
main[x + y*main_linesize] = alpha * overlay[overlay_x + overlay_y * overlay_linesize] + (1.0f - alpha) * main[x + y*main_linesize];
}
}
|
.text
.file "vf_overlay_cuda.hip"
.globl __device_stub__Overlay_Cuda # -- Begin function __device_stub__Overlay_Cuda
.p2align 4, 0x90
.type __device_stub__Overlay_Cuda,@function
__device_stub__Overlay_Cuda: # @__device_stub__Overlay_Cuda
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $Overlay_Cuda, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size __device_stub__Overlay_Cuda, .Lfunc_end0-__device_stub__Overlay_Cuda
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Overlay_Cuda, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Overlay_Cuda,@object # @Overlay_Cuda
.section .rodata,"a",@progbits
.globl Overlay_Cuda
.p2align 3, 0x0
Overlay_Cuda:
.quad __device_stub__Overlay_Cuda
.size Overlay_Cuda, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Overlay_Cuda"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Overlay_Cuda
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Overlay_Cuda
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : Overlay_Cuda
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR6, c[0x0][0x188] ; /* 0x0000620000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0050*/ UIADD3 UR5, UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc6000fffe03f */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0070*/ ULDC UR6, c[0x0][0x184] ; /* 0x0000610000067ab9 */
/* 0x000fe40000000800 */
/*0080*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000fffe03f */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R2, R2, c[0x0][0x4], R3 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R2, UR5, PT ; /* 0x0000000502007c0c */
/* 0x000fe2000bf06270 */
/*00c0*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0200 */
/*00d0*/ ISETP.GE.OR P0, PT, R5, UR4, P0 ; /* 0x0000000405007c0c */
/* 0x000fc80008706670 */
/*00e0*/ ISETP.LT.OR P0, PT, R5, c[0x0][0x160], P0 ; /* 0x0000580005007a0c */
/* 0x000fc80000701670 */
/*00f0*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x164], P0 ; /* 0x0000590002007a0c */
/* 0x000fda0000701670 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x198], PT ; /* 0x00006600ff007a0c */
/* 0x000fe20003f05270 */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IADD3 R0, R5, -c[0x0][0x160], RZ ; /* 0x8000580005007a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff067424 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R3, R2, -c[0x0][0x164], RZ ; /* 0x8000590002037a10 */
/* 0x000fd20007ffe0ff */
/*0160*/ @!P0 BRA 0x2d0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD R4, R0, c[0x0][0x19c], RZ ; /* 0x0000670000047a24 */
/* 0x000fe400078e02ff */
/*0180*/ IMAD R7, R3, c[0x0][0x198], RZ ; /* 0x0000660003077a24 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD R4, R7, c[0x0][0x1a0], R4 ; /* 0x0000680007047a24 */
/* 0x000fca00078e0204 */
/*01a0*/ IADD3 R6, P0, R4, c[0x0][0x190], RZ ; /* 0x0000640004067a10 */
/* 0x000fc80007f1e0ff */
/*01b0*/ LEA.HI.X.SX32 R7, R4, c[0x0][0x194], 0x1, P0 ; /* 0x0000650004077a11 */
/* 0x000fca00000f0eff */
/*01c0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1100 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff047424 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B1, 0x2c0 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3b808081 ; /* 0x3b808081ff097424 */
/* 0x000fc800078e00ff */
/*0200*/ FFMA R4, R9, -255, R4 ; /* 0xc37f000009047823 */
/* 0x000fc80000000004 */
/*0210*/ FFMA R9, R4, R9, 0.0039215688593685626984 ; /* 0x3b80808104097423 */
/* 0x000fe20000000009 */
/*0220*/ I2F.U16 R8, R6 ; /* 0x0000000600087306 */
/* 0x004e300000101000 */
/*0230*/ FCHK P0, R8, 255 ; /* 0x437f000008007902 */
/* 0x001e220000000000 */
/*0240*/ FFMA R4, R8, R9, RZ ; /* 0x0000000908047223 */
/* 0x000fc800000000ff */
/*0250*/ FFMA R10, R4, -255, R8 ; /* 0xc37f0000040a7823 */
/* 0x000fc80000000008 */
/*0260*/ FFMA R4, R9, R10, R4 ; /* 0x0000000a09047223 */
/* 0x000fe20000000004 */
/*0270*/ @!P0 BRA 0x2b0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0280*/ MOV R4, 0x2a0 ; /* 0x000002a000047802 */
/* 0x000fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*02b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*02d0*/ IMAD R5, R2, c[0x0][0x170], R5 ; /* 0x00005c0002057a24 */
/* 0x000fe400078e0205 */
/*02e0*/ IMAD R0, R3, c[0x0][0x180], R0 ; /* 0x0000600003007a24 */
/* 0x000fc600078e0200 */
/*02f0*/ IADD3 R2, P1, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005027a10 */
/* 0x040fe40007f3e0ff */
/*0300*/ IADD3 R4, P0, R0.reuse, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x040fe40007f1e0ff */
/*0310*/ LEA.HI.X.SX32 R3, R5, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0005037a11 */
/* 0x000fe400008f0eff */
/*0320*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x17c], 0x1, P0 ; /* 0x00005f0000057a11 */
/* 0x000fc600000f0eff */
/*0330*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea8000c1e1100 */
/*0340*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ee2000c1e1100 */
/*0350*/ FADD R9, -R6, 1 ; /* 0x3f80000006097421 */
/* 0x000fe20000000100 */
/*0360*/ I2F.U16 R0, R0 ; /* 0x0000000000007306 */
/* 0x004e300000101000 */
/*0370*/ I2F.U16 R7, R4 ; /* 0x0000000400077306 */
/* 0x008e620000101000 */
/*0380*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x001fc80000400000 */
/*0390*/ FFMA R7, R7, R6, R9 ; /* 0x0000000607077223 */
/* 0x002fcc0000000009 */
/*03a0*/ F2I.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f000 */
/*03b0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101106 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ SHF.R.U32.HI R6, RZ, 0x17, R8.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011608 */
/*03e0*/ BSSY B0, 0x9b0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*03f0*/ BSSY B2, 0x5a0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0400*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0410*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0420*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc80007ffe0ff */
/*0430*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, !PT ; /* 0x000000fd0b00780c */
/* 0x000fda0007f04470 */
/*0440*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x590 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fda0003f1c200 */
/*0470*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0480*/ @P0 BRA 0x990 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0490*/ IMAD.MOV.U32 R10, RZ, RZ, 0x437f0000 ; /* 0x437f0000ff0a7424 */
/* 0x000fca00078e00ff */
/*04a0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c807 */
/*04b0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*04c0*/ @!P0 BRA 0x970 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*04d0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*04e0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x950 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1d200 */
/*0510*/ LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000782c0ff */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0530*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0540*/ @P0 BRA 0x920 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f06270 */
/*0560*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0570*/ @!P0 FFMA R7, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008078823 */
/* 0x000fe400000000ff */
/*0580*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0590*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05a0*/ UMOV UR4, 0x437f0000 ; /* 0x437f000000047882 */
/* 0x000fe20000000000 */
/*05b0*/ IADD3 R8, R6, -0x7f, RZ ; /* 0xffffff8106087810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ UIADD3 UR4, UR4, -0x3800000, URZ ; /* 0xfc80000004047890 */
/* 0x000fe2000fffe03f */
/*05d0*/ BSSY B2, 0x910 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*05e0*/ IADD3 R9, R9, -0x7, R8 ; /* 0xfffffff909097810 */
/* 0x000fe20007ffe008 */
/*05f0*/ IMAD R7, R8, -0x800000, R7 ; /* 0xff80000008077824 */
/* 0x000fc400078e0207 */
/*0600*/ FADD.FTZ R12, -RZ, -UR4 ; /* 0x80000004ff0c7e21 */
/* 0x000fc60008010100 */
/*0610*/ MUFU.RCP R10, UR4 ; /* 0x00000004000a7d08 */
/* 0x000e240008001000 */
/*0620*/ FFMA R11, R10, R12, 1 ; /* 0x3f8000000a0b7423 */
/* 0x001fc8000000000c */
/*0630*/ FFMA R10, R10, R11, R10 ; /* 0x0000000b0a0a7223 */
/* 0x000fc8000000000a */
/*0640*/ FFMA R11, R7, R10, RZ ; /* 0x0000000a070b7223 */
/* 0x000fc800000000ff */
/*0650*/ FFMA R6, R12, R11, R7 ; /* 0x0000000b0c067223 */
/* 0x000fc80000000007 */
/*0660*/ FFMA R11, R10, R6, R11 ; /* 0x000000060a0b7223 */
/* 0x000fc8000000000b */
/*0670*/ FFMA R12, R12, R11, R7 ; /* 0x0000000b0c0c7223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R6, R10, R12, R11 ; /* 0x0000000c0a067223 */
/* 0x000fca000000000b */
/*0690*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*06a0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*06b0*/ IMAD.IADD R13, R7, 0x1, R9 ; /* 0x00000001070d7824 */
/* 0x000fca00078e0209 */
/*06c0*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*06e0*/ @!P0 BRA 0x8f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0700*/ @P0 BRA 0x8c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0720*/ @P0 BRA 0x900 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0740*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0750*/ @!P0 BRA 0x900 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0760*/ FFMA.RZ R7, R10.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0a077223 */
/* 0x1c0fe2000000c00b */
/*0770*/ IADD3 R9, R13.reuse, 0x20, RZ ; /* 0x000000200d097810 */
/* 0x040fe40007ffe0ff */
/*0780*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0790*/ LOP3.LUT R8, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07087812 */
/* 0x000fe200078ec0ff */
/*07a0*/ FFMA.RP R7, R10.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0a077223 */
/* 0x1c0fe2000000800b */
/*07b0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*07c0*/ FFMA.RM R10, R10, R12, R11 ; /* 0x0000000c0a0a7223 */
/* 0x000fe2000000400b */
/*07d0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV R11, RZ, RZ, -R13 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0a0d */
/*07f0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0800*/ FSETP.NEU.FTZ.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720b */
/* 0x000fe40003f1d000 */
/*0810*/ SEL R7, R11, RZ, P2 ; /* 0x000000ff0b077207 */
/* 0x000fe40001000000 */
/*0820*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0830*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0840*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0850*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*0860*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fc80004000000 */
/*0870*/ LOP3.LUT R8, R8, 0x1, R9, 0xf8, !PT ; /* 0x0000000108087812 */
/* 0x000fc800078ef809 */
/*0880*/ LOP3.LUT R8, R8, R7, RZ, 0xc0, !PT ; /* 0x0000000708087212 */
/* 0x000fca00078ec0ff */
/*0890*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fca00078e0208 */
/*08a0*/ LOP3.LUT R6, R9, R6, RZ, 0xfc, !PT ; /* 0x0000000609067212 */
/* 0x000fe200078efcff */
/*08b0*/ BRA 0x900 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*08d0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x900 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe400078e0206 */
/*0900*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0910*/ BRA 0x9a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R6, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a067812 */
/* 0x000fc800078e4807 */
/*0930*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0940*/ BRA 0x9a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R6, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a067812 */
/* 0x000fe200078e4807 */
/*0960*/ BRA 0x9a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0970*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0980*/ BRA 0x9a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0990*/ FADD.FTZ R6, R8, 255 ; /* 0x437f000008067421 */
/* 0x000fe40000010000 */
/*09a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09b0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*09c0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*09d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff61006007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Overlay_Cuda
.globl Overlay_Cuda
.p2align 8
.type Overlay_Cuda,@function
Overlay_Cuda:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x54
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_add_i32 s2, s2, s6
s_add_i32 s3, s3, s7
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_le_i32_e64 s3, s6, v0
v_cmp_le_i32_e64 s4, s7, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x38
v_subrev_nc_u32_e32 v2, s6, v0
v_subrev_nc_u32_e32 v3, s7, v1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x3c
s_load_b64 s[6:7], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v2, s4
s_mul_i32 s2, s5, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s2, v3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
global_load_u8 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, 0x437f0000, 0x437f0000, v4
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v4, 0x437f0000, v4
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v4, v5, 0x437f0000, v4
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v4, 1.0
.LBB0_4:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, v1, s4, v[0:1]
v_mad_u64_u32 v[0:1], null, v3, s5, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v5
v_add_co_u32 v1, vcc_lo, s2, v5
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v3, vcc_lo
global_load_u8 v0, v[1:2], off
global_load_u8 v3, v[5:6], off
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v0, v0
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_sub_f32_e32 v5, 1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v5, v0
v_fmac_f32_e32 v0, v4, v3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
global_store_b8 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Overlay_Cuda
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Overlay_Cuda, .Lfunc_end0-Overlay_Cuda
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Overlay_Cuda
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: Overlay_Cuda.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
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